WO2023173595A1 - Régulateur de tension et son procédé de commande - Google Patents

Régulateur de tension et son procédé de commande Download PDF

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Publication number
WO2023173595A1
WO2023173595A1 PCT/CN2022/096425 CN2022096425W WO2023173595A1 WO 2023173595 A1 WO2023173595 A1 WO 2023173595A1 CN 2022096425 W CN2022096425 W CN 2022096425W WO 2023173595 A1 WO2023173595 A1 WO 2023173595A1
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Prior art keywords
voltage
coupled
node
signal
output
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PCT/CN2022/096425
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English (en)
Chinese (zh)
Inventor
陈啸宸
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长鑫存储技术有限公司
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Publication of WO2023173595A1 publication Critical patent/WO2023173595A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a voltage regulator and a control method thereof.
  • the voltage stabilizer is a power supply circuit or power supply equipment that can automatically adjust the output voltage. Its function is to stabilize the power supply voltage that fluctuates greatly and does not meet the requirements of electrical equipment within its set value range, so that various circuits can Or the electrical equipment can work normally under the rated working voltage.
  • the voltage regulator needs to have a faster response speed.
  • Embodiments of the present disclosure provide a voltage regulator and a control method thereof, which are at least conducive to accelerating the startup of the voltage regulator.
  • an embodiment of the present disclosure provides a voltage regulator, including: a comparison module configured to compare a reference voltage and a feedback voltage and generate an error voltage based on the comparison; an output voltage adjustment module, and the The output terminal of the comparison module is coupled to the first node and is configured to adjust the input voltage received by the output voltage adjustment module based on the error voltage to provide an output voltage to the output node; a feedback circuit is coupled to the between the output node and the ground voltage, the feedback circuit is configured to divide the output voltage to provide the feedback voltage; a driving voltage adjustment module coupled to the first node for stabilizing The potential at the first node is adjusted during the startup phase of the voltage regulator operation.
  • the driving voltage adjustment module is configured to reduce time-consuming adjustment of the input voltage received by the output voltage adjustment module.
  • the driving voltage adjustment module includes: a start unit coupled to a control terminal of the output voltage adjustment module, the start unit stops adjusting the potential of the first node to start based on a start signal.
  • the voltage regulator an adjustment unit, coupled with the control end of the output voltage adjustment module, the adjustment unit adjusts the potential of the first node based on the adjustment signal to accelerate the startup of the voltage regulator.
  • the output voltage adjustment module includes a first PMOS transistor, a control end of the first PMOS transistor is coupled to the first node, and a first end of the first PMOS transistor is coupled to the working power supply. The second end of the first PMOS transistor is coupled to the output node.
  • the startup unit includes a second PMOS transistor
  • the adjustment unit includes a second NMOS transistor
  • the control end of the second PMOS transistor receives the startup signal
  • the third PMOS transistor of the second PMOS transistor receives the startup signal.
  • One end is coupled to the working power supply
  • the second end of the second PMOS tube is coupled to the first node
  • the control end of the second NMOS tube receives the adjustment signal
  • the second NMOS tube The first end of the second NMOS transistor is coupled to the ground end
  • the second end of the second NMOS transistor is coupled to the first node.
  • the startup unit includes a second NMOS transistor
  • the adjustment unit includes a second PMOS transistor
  • the control end of the second NMOS transistor receives the startup signal
  • the third NMOS transistor of the second NMOS transistor receives the startup signal.
  • One end is coupled to the working power supply
  • the second end of the second NMOS tube is coupled to the first node
  • the control end of the second PMOS tube receives the adjustment signal
  • the second PMOS tube The first end of the second PMOS transistor is coupled to the ground end
  • the second end of the second PMOS transistor is coupled to the first node.
  • the output voltage adjustment module includes a first NMOS transistor, a control end of the first NMOS transistor is coupled to the first node, and a first end of the first NMOS transistor is coupled to the working power supply. The second end of the first NMOS transistor is coupled to the output node.
  • the startup unit includes a second PMOS transistor
  • the adjustment unit includes a second NMOS transistor
  • the control end of the second PMOS transistor receives the startup signal
  • the third PMOS transistor of the second PMOS transistor receives the startup signal.
  • One end is coupled to the ground end
  • the second end of the second PMOS tube is coupled to the first node
  • the control end of the second NMOS tube receives the adjustment signal
  • the third end of the second NMOS tube One end is coupled to the working power supply, and a second end of the second NMOS transistor is coupled to the first node.
  • the startup unit includes a second NMOS transistor
  • the adjustment unit includes a second PMOS transistor
  • the control end of the second NMOS transistor receives the startup signal
  • the third NMOS transistor of the second NMOS transistor receives the startup signal.
  • One end is coupled to the ground end
  • the second end of the second NMOS tube is coupled to the first node
  • the control end of the second PMOS tube receives the adjustment signal
  • the third end of the second PMOS tube One end is coupled to the working power supply, and a second end of the second PMOS tube is coupled to the first node.
  • the voltage regulator further includes: a signal generation module, configured to generate the adjustment signal based on the startup signal; wherein generating the adjustment signal based on the startup signal includes: The start signal is sequentially inverted and delayed, and a logical AND operation is performed with the start signal to generate the adjustment signal.
  • the signal generation module includes: an inversion unit, the input end of the inversion unit receives the start signal; a delay unit, the input end of the delay unit is connected to the input end of the inversion unit.
  • the output terminal is coupled; an AND gate circuit, the first input terminal of the AND gate circuit is coupled with the output terminal of the delay unit, the second input terminal of the AND gate circuit receives the start signal, and the AND gate circuit
  • the output terminal of the gate circuit outputs the adjustment signal.
  • the voltage regulator further includes: a signal generation module, configured to generate the adjustment signal based on the startup signal; wherein generating the adjustment signal based on the startup signal includes: The start signal is sequentially inverted and delayed, and the signal obtained by performing logical OR operation with the start signal is used to generate the adjustment signal.
  • the signal generation module includes: an inversion unit, the input end of the inversion unit receives the start signal; a delay unit, the input end of the delay unit is connected to the input end of the inversion unit.
  • the output terminal is coupled; an OR gate circuit, the first input terminal of the OR gate circuit is coupled with the output terminal of the delay unit, the second input terminal of the OR gate circuit receives the start signal, and the OR gate circuit The output terminal of the gate circuit outputs the adjustment signal.
  • the feedback circuit includes: a first voltage dividing module coupled between the output node and the comparison module; a second voltage dividing module coupled between the first voltage dividing module and Between the ground terminals, the feedback voltage is the potential at the coupling point between the first voltage dividing module and the second voltage dividing module.
  • the comparison module includes: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the control end of the third PMOS transistor and the fourth PMOS transistor The control terminal is coupled, and there is a third node between the control terminal of the third PMOS tube and the control terminal of the fourth PMOS tube; the first terminal of the third PMOS tube and the control terminal of the fourth PMOS tube The third end is coupled to the operating power supply, the second end of the third PMOS transistor is coupled to the fifth end of the third NMOS transistor, and the fourth end of the fourth PMOS transistor is coupled to the fourth end of the fourth NMOS transistor.
  • the seventh end has a fourth node between the second end and the fifth end, the fourth node is coupled to the first node, and there is a between the fourth end and the seventh end.
  • the fifth node, the fifth node is coupled to the third node; the sixth terminal of the third NMOS tube is coupled to the eighth terminal of the fourth NMOS tube, and the control of the third NMOS tube
  • the terminal is the first input terminal of the comparison module, the control terminal of the fourth NMOS tube is the second input terminal of the comparison module, and the fourth node is the output terminal of the comparison module.
  • the voltage regulator further includes: a fifth NMOS transistor, the control terminal of the fifth NMOS transistor receives a bias voltage. , the first end of the fifth NMOS transistor is coupled to the sixth node, and the second end of the fifth NMOS transistor is coupled to the ground end.
  • the embodiments of the present disclosure also provide a control method for a voltage regulator, including: providing a voltage regulator as described in any one of the foregoing; providing a reference voltage and a driving voltage, where In the startup phase of the voltage regulator operation, the driving voltage adjustment module adjusts the potential at the first node based on the driving voltage, so that the feedback circuit generates a feedback voltage, and the comparison module adjusts the potential at the first node based on the reference voltage. and the feedback voltage to generate an error voltage, and causing the output voltage adjustment module to generate an output voltage based on the error voltage.
  • the output voltage adjustment module includes a first PMOS transistor or a first NMOS transistor; the driving voltage includes a start signal and an adjustment signal.
  • providing the driving voltage includes: providing a startup signal; and generating the adjustment signal based on the startup signal.
  • control method of the voltage regulator further includes: providing a bias voltage, and the comparison module receives the bias voltage.
  • a driving voltage adjustment module is provided in the voltage regulator, so that during the startup phase of the voltage regulator operation, the potential at the first node can be quickly adjusted to the potential required to start the output voltage adjustment module through the driving voltage adjustment module, thereby accelerating
  • the startup of the output voltage adjustment module is to increase the speed at which the output voltage adjustment module provides the output voltage to the output node, thereby facilitating the startup of the voltage regulator.
  • 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator provided by an embodiment of the present disclosure
  • Figure 5 is a waveform diagram of a start signal and an adjustment signal provided by an embodiment of the present disclosure
  • Figure 6 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 5;
  • Figure 7 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 6;
  • Figures 8 and 9 are schematic diagrams of two other circuit structures of a voltage regulator provided by an embodiment of the present disclosure.
  • Figure 10 is another waveform diagram of a start signal and an adjustment signal provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 10;
  • Figure 12 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 11;
  • FIG. 13 is a schematic diagram of another circuit structure of a voltage regulator provided by an embodiment of the present disclosure.
  • the implementation of the present disclosure provides a voltage stabilizer and a control method thereof.
  • a driving voltage adjustment module is provided in the voltage stabilizer, so that during the startup phase of the voltage stabilizer operation, the potential at the first node can be quickly adjusted through the driving voltage adjustment module. Adjust to the potential required to start the output voltage adjustment module, thereby accelerating the start-up of the output voltage adjustment module, so as to increase the speed at which the output voltage adjustment module provides the output voltage to the output node, thus facilitating the acceleration of the start-up of the voltage regulator.
  • FIGS. 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator provided by an embodiment of the present disclosure
  • Figure 5 is a waveform diagram of a starting signal and an adjustment signal provided by an embodiment of the present disclosure
  • Figure 6 is the same as Figure 5
  • Figure 7 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 6
  • Figures 8 and 9 are two other circuit structures of the voltage regulator provided by an embodiment of the present disclosure.
  • FIG. 10 is another waveform diagram of the startup signal and the adjustment signal provided by an embodiment of the present disclosure
  • Figure 11 is a schematic circuit structure diagram of the signal generation module corresponding to Figure 10
  • Figure 12 is the signal generation corresponding to Figure 11
  • FIG. 13 is another schematic circuit structure diagram of the voltage regulator provided by an embodiment of the present disclosure.
  • the voltage regulator includes: a comparison module 100 configured to compare a reference voltage 10a and a feedback voltage 10b and generate an error voltage 10c based on the comparison; an output voltage adjustment module 101 coupled to the first output terminal of the comparison module 100 Node 102 is configured to adjust the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide the output voltage 10d to the output node 103; the feedback circuit 104 is coupled between the output node 103 and the ground voltage, the feedback circuit 104 is configured to divide the output voltage 10d to provide the feedback voltage 10b; the driving voltage adjustment module 105 is coupled to the first node 102 and is used to adjust the potential at the first node 102 during the startup phase of the voltage regulator operation.
  • the potential at the first node 102 is first adjusted by driving the voltage adjustment module 105, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly
  • the output voltage adjustment module 101 is started, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, and the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide an output voltage 10d to the output node 103.
  • the drive voltage adjustment module 105 is configured to reduce the time required to adjust the input voltage received by the output voltage adjustment module 101 .
  • the input voltage received by the output voltage adjustment module 101 is the potential at the first node 102.
  • the output voltage adjustment module 101 starts or shuts down based on the potential at the first node 102.
  • the driving voltage adjustment module 105 is conducive to reducing the adjustment of the output voltage adjustment.
  • the input voltage received by the module 101 takes time, that is, during the startup phase of the voltage regulator operation, the driving voltage adjustment module 105 can quickly adjust the potential at the first node 102 to the potential required to start the output voltage adjustment module 101, so as to The startup of the output voltage regulation module 101 is accelerated, thereby further accelerating the startup of the voltage regulator.
  • the driving voltage adjustment module 105 includes: a start unit 115 coupled to the control terminal of the output voltage adjustment module 101.
  • the start unit 115 stops adjusting the potential of the first node 102 based on the start signal 11a to start voltage regulation. regulator;
  • the adjustment unit 125 is coupled to the control end of the output voltage adjustment module 101.
  • the adjustment unit 125 adjusts the potential of the first node 102 based on the adjustment signal 11b to accelerate the startup of the voltage regulator.
  • the startup unit 115 can adjust the potential at the first node 102 based on the startup signal 11a, so that the output voltage adjustment module 101 is based on the potential at the first node 102 at this time.
  • the output voltage adjustment module 101 is controlled by the startup unit 115 not to provide the output voltage 10d to the output node 103, and the comparison module 100 is also in a non-working state, so that the entire voltage regulator is in a non-working state.
  • the output voltage adjustment module 101 includes a first PMOS transistor 111 , the control end of the first PMOS transistor 111 is coupled to the first node 102 , and the first end of the first PMOS transistor 111 is coupled to the working power supply. VDD is coupled, and the second terminal of the first PMOS transistor 111 is coupled to the output node 103 .
  • the startup unit 115 includes a second PMOS transistor 135, and the adjustment unit 125 includes a second NMOS transistor 145.
  • the control end of the second PMOS transistor 135 receives the startup signal 11a, and the first end of the second PMOS transistor 135 is coupled to the operating power supply VDD. connected, the second end of the second PMOS transistor 135 is coupled to the first node 102, the control end of the second NMOS transistor 145 receives the adjustment signal 11b, the first end of the second NMOS transistor 145 is coupled to the ground end, and the second NMOS The second end of tube 145 is coupled to first node 102 .
  • the second PMOS transistor 135 can be in the on state based on the start signal 11a, and the second NMOS transistor 145 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the working power supply.
  • VDD coupling that is, the second PMOS transistor 135 that is in the conductive state at this time can pull up the potential at the first node 102 to a higher value, so that the first PMOS transistor 111 receives the voltage at the first node 102 In the off state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
  • the second PMOS transistor 135 can be in the off state based on the startup signal 11a, and the second NMOS transistor 145 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is connected to the first node 102 with a higher potential.
  • the ground terminal is coupled, that is, the second NMOS transistor 145 that is in the conductive state at this time can quickly pull down the potential at the first node 102 to the potential required to start the first PMOS transistor 111, thereby realizing the driving voltage adjustment module. 105.
  • the voltage regulation module 101 provides the speed of the output voltage 10d to the output node 103, thereby facilitating the startup of the voltage regulator.
  • the second PMOS transistor 135 may be in the off state based on the start signal 11a, and the second NMOS transistor 145 may also be in the off state based on the adjustment signal 11b,
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
  • the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts based on the error voltage 10c.
  • the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
  • the output voltage adjustment module 101 includes a first NMOS transistor 121.
  • the control end of the first NMOS transistor 121 is coupled to the first node 102.
  • the first end of the first NMOS transistor 121 is coupled to the operating power supply VDD.
  • the second end of the first NMOS transistor 121 is coupled to the output node 103 .
  • the startup unit 115 includes a second PMOS transistor 135, and the adjustment unit 125 includes a second NMOS transistor 145.
  • the control end of the second PMOS transistor receives the startup signal 11a, and the first end of the second PMOS transistor 135 is coupled to the ground end.
  • the second end of the second PMOS transistor 135 is coupled to the first node 102.
  • the control end of the second NMOS transistor 145 receives the adjustment signal 11b.
  • the first end of the second NMOS transistor 145 is coupled to the operating power supply VDD.
  • the second end of 145 is coupled to first node 102 .
  • the second PMOS transistor 135 can be in the on state based on the start signal 11a, and the second NMOS transistor 145 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the ground terminal. Coupling, that is, the potential at the first node 102 can be pulled down to a lower value through the second PMOS transistor 135 that is in a conductive state at this time, so that the first NMOS transistor 121 that receives the voltage at the first node 102 is turned off. state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
  • the second PMOS transistor 135 can be in the off state based on the startup signal 11a, and the second NMOS transistor 145 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is connected to the
  • the working power supply VDD is coupled, that is, the potential at the first node 102 can be quickly pulled up to the potential required to start the first NMOS transistor 121 through the second NMOS transistor 145 that is in the conductive state at this time, thereby realizing the driving voltage through
  • the adjustment module 105 adjusts the potential at the first node 102 so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby Increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103 is beneficial to speeding up the startup of the voltage regulator.
  • the second PMOS transistor 135 may be in the off state based on the start signal 11a, and the second NMOS transistor 145 may also be in the off state based on the adjustment signal 11b,
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
  • the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts based on the error voltage 10c.
  • the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
  • the waveform diagrams of the start signal 11a and the adjustment signal 11b can be shown in Figure 5.
  • the potentials represented by the startup signal 11a and the adjustment signal 11b are both at low values, then the second PMOS transistor 135 can be in a conductive state based on the startup signal 11a, and the second NMOS transistor 145 can be in a conducting state based on the adjustment signal.
  • the signal 11b is in the cut-off state; in the second phase II, the potentials represented by the start-up signal 11a and the adjustment signal 11b are both at higher values, then the second PMOS transistor 135 can be in the cut-off state based on the start-up signal 11a, and the second NMOS transistor 145 It can be based on the fact that the adjustment signal 11b is in a conductive state; in the third stage III, the potential represented by the startup signal 11a is at a higher value and the potential represented by the adjustment signal 11b is at a lower value, then the second PMOS transistor 135 can be based on The start signal 11a is in a cut-off state, and the second NMOS transistor 145 may also be in a cut-off state based on the adjustment signal 11b.
  • the lower value of the potential and the higher value of the potential are relative to the magnitudes of the start signal 11a and the adjustment signal 11b in the first phase I, the second phase II and the third phase III.
  • the value of the potential represented by the startup signal 11a in the first phase I is smaller than the value of the potential represented by the second phase II, then it can be considered that the potential represented by the startup signal 11a in the first phase I is at a lower level. value, the potential represented by the activation signal 11a in the second phase II is at a higher value.
  • the voltage regulator may also include: a signal generation module 106 for generating an adjustment signal 11b based on the startup signal 11a; wherein generating the adjustment signal 11b based on the startup signal 11a includes: The signal 11a is sequentially inverted and delayed, and the signal obtained is logically ANDed with the start signal 11a to generate the adjustment signal 11b.
  • the signal generation module 106 may include: an inverter unit 116 whose input terminal receives the start signal 11a; a delay unit 126 whose input terminal is connected to the inverter unit 116 .
  • the output terminal of the unit 116 is coupled; the AND gate circuit 136, the first input terminal of the AND gate circuit 136 is coupled with the output terminal of the delay unit 126, the second input terminal of the AND gate circuit 136 receives the start signal 11a, and the AND gate circuit 136
  • the output terminal of 136 outputs the adjustment signal 11b.
  • the AND gate circuit 136 may include NAND gates 146 and 156 connected in series with each other. It should be noted that in FIG. 7 , only the AND gate circuit 136 includes NAND gates 146 and 156 connected in series with each other.
  • the NOT gate 156 is used as an example. In practical applications, the AND gate circuit 136 can be composed of a single AND gate or a combination of other logic gate circuits, as long as the AND gate circuit 136 can perform a logical AND operation on the two received signals. That’s it.
  • the potential values represented by the start signal 11a or the adjustment signal 11b are both low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; the start signal When the potential values represented by 11a or the adjustment signal 11b are both high, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.
  • the start signal 11 a appears to be 0, the signal received by the first input terminal of the AND gate circuit 136 appears to be 1, and the start signal received by the second input terminal of the AND gate circuit 136 11a behaves as 0, then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 behaves as 0; in the second stage II, the start signal 11a behaves as 1, because the delay unit 126 responds to the received signal output by the inverting unit 116 The delay effect of The adjustment signal 11b output by the output terminal of 136 appears to be 1; in the third stage III, the start signal 11a appears to be 1, and the first input terminal of the AND gate circuit 136 has received the change of the start signal 11a in the second stage II.
  • the signal received by the first input terminal of the AND gate circuit 136 changes, the signal received by the first input terminal of the AND gate circuit 136 will appear as 0, and the start signal 11a received by the second input terminal of the AND gate circuit 136 will appear as 1. , then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 appears to be 0.
  • the output voltage adjustment module 101 includes a first PMOS transistor 111 .
  • the control end of the first PMOS transistor 111 is coupled to the first node 102 .
  • the first end of the first PMOS transistor 111 is connected to the working end of the first PMOS transistor 111 .
  • the power supply VDD is coupled, and the second terminal of the first PMOS transistor 111 is coupled to the output node 103 .
  • the startup unit 115 includes a second NMOS transistor 145
  • the adjustment unit 125 includes a second PMOS transistor 135.
  • the control end of the second NMOS transistor 145 receives the startup signal 11a, and the first end of the second NMOS transistor 145 is coupled to the operating power supply VDD.
  • the second end of the second NMOS transistor 145 is coupled to the first node 102
  • the control end of the second PMOS transistor 135 receives the adjustment signal 11b
  • the first end of the second PMOS transistor 135 is coupled to the ground end
  • the second PMOS transistor 135 is coupled to the ground end.
  • the second end of tube 135 is coupled to first node 102 .
  • the second NMOS transistor 145 can be in the on state based on the start signal 11a, and the second PMOS transistor 135 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the working power supply.
  • VDD coupling that is, the second NMOS transistor 145 in the on state at this time can pull up the potential at the first node 102 to a higher value, so that the first PMOS transistor 111 receives the voltage at the first node 102 In the off state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
  • the second NMOS transistor 145 can be in the off state based on the startup signal 11a, and the second PMOS transistor 135 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is connected to the first node 102 with a higher potential.
  • the ground terminal is coupled, that is, the second PMOS transistor 135 that is in the conductive state at this time can quickly pull down the potential at the first node 102 to the potential required to start the first PMOS transistor 111, thereby realizing the driving voltage adjustment module. 105.
  • the voltage regulation module 101 provides the speed of the output voltage 10d to the output node 103, thereby facilitating the startup of the voltage regulator.
  • the second NMOS transistor 145 may be in the off state based on the start signal 11a, and the second PMOS transistor 135 may also be in the off state based on the adjustment signal 11b,
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
  • the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts based on the error voltage 10c.
  • the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
  • the output voltage adjustment module 101 includes a first NMOS transistor 121 .
  • the control end of the first NMOS transistor 121 is coupled to the first node 102 .
  • the first end of the first NMOS transistor 121 is connected to the working end of the first NMOS transistor 121 .
  • the power supply VDD is coupled, and the second terminal of the first NMOS transistor 121 is coupled to the output node 103 .
  • the startup unit 115 includes a second NMOS transistor 145
  • the adjustment unit 125 includes a second PMOS transistor 135.
  • the control end of the second NMOS transistor 145 receives the startup signal 11a, and the first end of the second NMOS transistor 145 is coupled to the ground end.
  • the second end of the second NMOS transistor 145 is coupled to the first node 102
  • the control end of the second PMOS transistor 135 receives the adjustment signal 11b
  • the first end of the second PMOS transistor 135 is coupled to the operating power supply VDD
  • the second PMOS transistor 135 The second end of tube 135 is coupled to first node 102 .
  • the second NMOS transistor 145 can be in the on state based on the start signal 11a, and the second PMOS transistor 135 can be in the off state based on the adjustment signal 11b, then the first node 102 is equivalent to the ground terminal. Coupling, that is, the potential at the first node 102 can be pulled down to a lower value through the second NMOS transistor 145 that is in the on state at this time, so that the first NMOS transistor 121 that receives the voltage at the first node 102 is turned off. state, that is, the output voltage adjustment module 101 is in a closed state and does not provide the output voltage 10d to the output node 103.
  • the second NMOS transistor 145 can be in the off state based on the startup signal 11a, and the second PMOS transistor 135 can be in the on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is connected to the The working power supply VDD is coupled, that is, the potential at the first node 102 can be quickly pulled up to the potential required to start the first NMOS transistor 121 through the second PMOS transistor 135 that is in the conductive state at this time, thereby realizing the driving voltage.
  • the adjustment module 105 adjusts the potential at the first node 102 so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby Increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103 is beneficial to speeding up the startup of the voltage regulator.
  • the second NMOS transistor 145 may be in the off state based on the start signal 11a, and the second PMOS transistor 135 may also be in the off state based on the adjustment signal 11b,
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100.
  • the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts based on the error voltage 10c.
  • the input voltage received by the output voltage adjustment module 101 is to use the comparison module 100 to adjust the potential at the first node 102 so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in a conductive state. , providing a stable output voltage 10d to the output node 103.
  • the waveform diagrams of the start signal 11a and the adjustment signal 11b can be shown in Figure 10.
  • the potentials represented by the startup signal 11a and the adjustment signal 11b are both at relatively high values, then the second NMOS transistor 145 can be in a conductive state based on the startup signal 11a, and the second PMOS transistor 135 can be in a conducting state based on the adjustment signal.
  • the signal 11b is in the cut-off state; in the second phase II, the potentials represented by the start-up signal 11a and the adjustment signal 11b are both at low values, then the second NMOS transistor 145 can be in the cut-off state based on the start-up signal 11a, and the second PMOS transistor 135 It can be based on the fact that the adjustment signal 11b is in a conductive state; in the third stage III, the potential represented by the start signal 11a is at a lower value, and the potential represented by the adjustment signal 11b is at a higher value, then the second NMOS transistor 145 can be based on The start signal 11a is in a cut-off state, and the second PMOS transistor 135 may also be in a cut-off state based on the adjustment signal 11b.
  • the lower value of the potential and the higher value of the potential are relative to the magnitudes of the start signal 11a and the adjustment signal 11b in the first phase I, the second phase II and the third phase III.
  • the value of the potential represented by the startup signal 11a in the first phase I is greater than the value of the potential represented by the second phase II, then it can be considered that the potential represented by the startup signal 11a in the first phase I is at a higher level. value, the potential represented by the activation signal 11a in the second phase II is at a lower value.
  • the voltage regulator may also include: a signal generation module 106 for generating an adjustment signal 11b based on the startup signal 11a; wherein generating the adjustment signal 11b based on the startup signal 11a includes: The signal 11a is sequentially inverted and delayed, and the resulting signal is logically ORed with the start signal 11a to generate the adjustment signal 11b.
  • the signal generation module 106 may include: an inverting unit 116 whose input terminal receives the start signal 11a; a delay unit 126 whose input terminal is connected to the inverting unit 116 .
  • the output terminal of the unit 116 is coupled; the OR gate circuit 166, the first input terminal of the OR gate circuit 166 is coupled with the output terminal of the delay unit 126, the second input terminal of the OR gate circuit 166 receives the start signal 11a, the OR gate circuit
  • the output terminal of 166 outputs the adjustment signal 11b.
  • the OR circuit 166 may include a NOR gate 176 and a NOT gate 156 connected in series. It should be noted that in FIG. 12 , only the OR circuit 166 includes a NOR gate 176 and a NOR gate 156 connected in series.
  • the NOT gate 156 is an example. In practical applications, the OR circuit 166 can be composed of a single OR gate or a combination of other logic gate circuits, as long as the OR circuit 166 can perform a logical OR operation on the two received signals. That’s it.
  • the potential values represented by the start signal 11a or the adjustment signal 11b are both low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; the start signal When the potential values represented by 11a or the adjustment signal 11b are both high, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.
  • the start signal 11a is 1, the signal received by the first input terminal of the AND gate circuit 136 is 0, and the start signal received by the second input terminal of the AND gate circuit 136 is 11a behaves as 1, then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 behaves as 1; in the second stage II, the start signal 11a behaves as 0, because the delay unit 126 responds to the received signal output by the inverting unit 116 The delay effect of The adjustment signal 11b output by the output terminal of 136 appears to be 0; in the third stage III, the start signal 11a appears to be 0, and the first input terminal of the AND gate circuit 136 has received the change of the start signal 11a in the second stage II.
  • the signal received by the first input terminal of the AND gate circuit 136 changes, the signal received by the first input terminal of the AND gate circuit 136 will appear as 1, and the start signal 11a received by the second input terminal of the AND gate circuit 136 will appear as 0. , then the adjustment signal 11b output by the output terminal of the AND gate circuit 136 appears to be 1.
  • the inverter unit 116 may include: a first switch unit 186 coupled between the operating power supply VDD and the input end of the delay unit 126 . There is a second node 107 between a switch unit 186 and the input terminal of the delay unit 126; the second switch unit 196 is coupled between the ground terminal and the second node 107; wherein, the control terminal of the first switch unit 186, The control terminals of the second switch unit 196 both receive the start signal 11a.
  • the first switching unit 186 may be one of a PMOS transistor and an NMOS transistor
  • the second switching unit 196 may be the other of a PMOS transistor and an NMOS transistor.
  • the first switch unit 186 may be a PMOS transistor, and the second switch unit 196 may be an NMOS transistor.
  • the first switching unit may be an NMOS transistor
  • the second switching unit may be a PMOS transistor.
  • the first switch unit 186 and the second switch unit 196 can also be other switching devices that can be turned on or off based on the start signal 11a, as long as the first switch satisfies the start signal 11a at the same time.
  • One of the unit 186 and the second switch unit 196 is turned on based on the start signal 11a at this time, and the other one of the first switch unit 186 and the second switch unit 196 is turned off based on the start signal 11a at this time.
  • the delay unit 126 may include: an even number of series-connected inverters 118 .
  • the delay unit 126 including two series-connected inverters 118 is used as an example. In actual applications, it only needs to be an even number of inverters 118 . 5 and 10 , an even number of series-connected inverters 118 are used to delay the signal received by the delay unit 126 from the output end of the inverter unit 116 .
  • the value of the potential represented by the start signal 11a has changed, and the value of the potential represented by the signal received by the delay unit 126 from the output end of the inverting unit 116 has not yet arrived.
  • the value of the potential represented by the signal received by the delay unit 126 from the output end of the inverting unit 116 also changes, so that the adjustment signal 11b and the start signal 11a in the third stage II represent
  • the values of the potentials are at different levels, that is, the potential represented by one of the adjustment signal 11b and the startup signal 11a in the circuit is 1, and the potential of the other one of the adjustment signal 11b and the startup signal 11a is represented in the circuit. The potential appears to be 0.
  • the delay unit 126 in addition to including an even number of series-connected inverters 118, may also include: a charge and discharge unit 108 coupled between the second node 107 and ground. between ends. Among them, the charging and discharging unit 108 is beneficial to enhancing the delay effect of the delay unit 126 on the signal received from the output end of the inverting unit 116 .
  • the feedback circuit 104 may include: a first voltage dividing module 114 coupled between the output node 103 and the comparison module 100; a second voltage dividing module 124, coupled between the first voltage dividing module 114 and the ground terminal, the feedback voltage 10b is the potential at the coupling point of the first voltage dividing module 114 and the second voltage dividing module 124.
  • the comparison module 100 it is beneficial to control the size of the feedback voltage 10b provided to the comparison module 100 through the first voltage dividing module 114 and the second voltage dividing module 124 when the output voltage 10d meeting the numerical requirements is output through the output voltage adjustment module 101, so that the feedback
  • the magnitude of the voltage 10b is consistent with the magnitude of the reference voltage 10a, that is, the difference between the feedback voltage 10b and the reference voltage 10a is very small or 0, so that the comparison module 100 can output a numerically stable error voltage 10c based on the reference voltage 10a and the feedback voltage 10b.
  • the comparison module 100 includes: a third PMOS transistor 110 , a fourth PMOS transistor 120 , a third NMOS transistor 130 and a fourth NMOS transistor 140 ; wherein, the control end of the third PMOS transistor 110 and The control terminal of the fourth PMOS tube 120 is coupled, and there is a third node 109 between the control terminal of the third PMOS tube 110 and the control terminal of the fourth PMOS tube 120; the first terminal of the third PMOS tube 110 and the fourth PMOS tube
  • the third end of 120 is coupled to the working power supply VDD
  • the second end of the third PMOS transistor 110 is coupled to the fifth end of the third NMOS transistor 130
  • the fourth end of the fourth PMOS transistor 120 is coupled to the third end of the fourth NMOS transistor 140.
  • a fourth node 119 is between the second terminal and the fifth terminal, the fourth node 119 is coupled to the first node 102, a fifth node 129 is between the fourth terminal and the seventh terminal, the fifth node 129 is connected to The third node 109 is coupled; the sixth terminal of the third NMOS tube 130 is coupled to the eighth terminal of the fourth NMOS tube 140.
  • the control terminal of the third NMOS tube 130 is the first input terminal of the comparison module 100.
  • the fourth NMOS The control end of the tube 140 is the second input end of the comparison module 100, and the fourth node 119 is the output end of the comparison module.
  • control terminal of the third NMOS transistor 130 receives the reference voltage 10a
  • control terminal of the fourth NMOS transistor 140 receives the feedback voltage 10b.
  • the third PMOS transistor 110, the fourth PMOS transistor 120, the third NMOS transistor 130 and the fourth NMOS transistor 140 are all in a conductive state.
  • the conduction degree of the third NMOS transistor 130 is greater than the conduction degree of the fourth NMOS transistor 140, that is, the voltage drop generated by the third NMOS transistor 130 is smaller than the voltage drop generated by the fourth NMOS transistor 140.
  • the potential at the fourth node 119 is caused to be lower than the potential at the fifth node 129 .
  • the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120
  • the third PMOS transistor 110 and the fourth PMOS transistor 120 The conduction degree of 120 decreases, that is, the voltage drop generated by the third PMOS transistor 110 increases, causing the potential at the fourth node 119 to decrease, that is, the error voltage 10c output by the comparison module 100 decreases, causing the potential at the first node 102 to decrease.
  • the conduction degree of the first PMOS tube 111 increases, that is, the voltage drop generated by the first PMOS tube 111 decreases, which is beneficial to increasing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, thereby increasing the feedback circuit 104 divides the feedback voltage 10b provided based on the output voltage 10d to reduce the difference between the reference voltage 10a and the feedback voltage 10b.
  • the conduction degree of the third NMOS transistor 130 is less than the conduction degree of the fourth NMOS transistor 140, that is, the voltage drop generated by the third NMOS transistor 130 is greater than the voltage drop generated by the fourth NMOS transistor 140.
  • the potential at the fourth node 119 is caused to be higher than the potential at the fifth node 129 .
  • the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120, if the potential at the fifth node 129 decreases, the third PMOS transistor 110 and the fourth PMOS transistor 120
  • the conduction degree of The potential increases, causing the conduction degree of the first PMOS transistor 111 to decrease, that is, the voltage drop generated by the first PMOS transistor 111 increases, which is beneficial to reducing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, thereby reducing the
  • the small feedback circuit 104 divides the feedback voltage 10b provided by the output voltage 10d to reduce the difference between the reference voltage 10a and the feedback voltage 10b.
  • the voltage regulator may also include: a bias voltage module 150, one end of the bias voltage module 150 is connected to the sixth node 139 is coupled, and the other end of the bias voltage module 150 is coupled to the ground.
  • the bias voltage module 150 can be used as a power supply module of the voltage regulator, which is beneficial to the voltage regulator working based on the larger reference voltage 10a.
  • the bias voltage module 150 may include a fifth NMOS transistor. The control terminal of the fifth NMOS transistor receives the bias voltage 10e. The first end of the fifth NMOS transistor is coupled to the sixth node 139. The fifth NMOS transistor The second end is coupled to the ground end.
  • the potential at the first node 102 is first adjusted by driving the voltage adjustment module 105 so that the potential at the first node 102 quickly reaches the level required to start the output voltage adjustment module 101 potential to quickly start the output voltage adjustment module 101, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, thereby conducive to accelerating the start-up of the voltage regulator.
  • the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, and the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c.
  • the output voltage adjustment module 101 adjusts the input voltage received by the output voltage adjustment module 101 based on the error voltage 10c to provide an output voltage 10d to the output node 103.
  • Another embodiment of the present disclosure also provides a control method for a voltage regulator, which is used to control the voltage regulator provided in the previous embodiment.
  • a control method for a voltage regulator provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • the control method of the voltage regulator includes: providing a voltage stabilizer as described in any of the preceding items; providing a reference voltage 10a and a driving voltage.
  • the driving voltage adjustment module 105 is based on the driving voltage.
  • the potential at the first node 102 is adjusted so that the feedback circuit 104 generates the feedback voltage 10b, the comparison module 100 generates the error voltage 10c based on the reference voltage 10a and the feedback voltage 10b, and the output voltage adjustment module 101 generates an output based on the error voltage 10c. Voltage 10d.
  • the potential at the first node 102 is first adjusted based on the driving voltage, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly
  • the output voltage adjustment module 101 is started, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.
  • the output voltage adjustment module 101 includes a first PMOS transistor or a first NMOS transistor; the driving voltage includes a start signal 11a and an adjustment signal 11b.
  • the driving voltage adjustment module 105 adjusts the potential at the first node 102 based on the driving voltage, refer to the relevant descriptions of the foregoing embodiments and will not be described again.
  • the step of providing the driving voltage includes: providing the activation signal 11a; and generating the adjustment signal 11b based on the activation signal 11a.
  • the adjustment signal 11b based on the start signal 11a refer to the relevant descriptions of the foregoing embodiments and will not be described again.
  • control method of the voltage regulator further includes: providing a bias voltage 10e, and the comparison module 100 receiving the bias voltage 10e.
  • the bias voltage 10e can be used as a power supply for the voltage regulator, which is beneficial to the voltage regulator updating based on numerical values. Large reference voltage 10a operates.
  • control method of the voltage regulator provided by another embodiment of the present disclosure is conducive to making the potential at the first node 102 quickly reach the potential required to start the output voltage adjustment module 101 during the startup phase of the voltage regulator operation. , to quickly start the output voltage adjustment module 101, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, which is beneficial to accelerating the start-up of the voltage regulator.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

Régulateur de tension et son procédé de commande. Le régulateur de tension comprend : un module de comparaison (100), qui est configuré pour comparer une tension de référence (10a) à une tension de rétroaction (10b), et générer une tension d'erreur (10c) sur la base de la comparaison ; un module de régulation de tension de sortie (101), qui est couplé à une extrémité de sortie du module de comparaison (100) au niveau d'un premier nœud (102), et est configuré pour ajuster, sur la base de la tension d'erreur (10c), une tension d'entrée reçue par le module de régulation de tension de sortie (101), de façon à fournir une tension de sortie (10d) à un nœud de sortie (103) ; un circuit de rétroaction (104), qui est couplé entre le nœud de sortie (103) et une tension de mise à la terre, le circuit de rétroaction (104) étant configuré pour effectuer une division de tension sur la tension de sortie (10d), de façon à fournir la tension de rétroaction (10b) ; et un module de régulation de tension d'attaque (105), qui est couplé au premier nœud (102) et est utilisé pour réguler le potentiel au niveau du premier nœud (102) pendant une étape de démarrage du fonctionnement du régulateur de tension. Le régulateur de tension et le procédé de commande sont avantageux pour accélérer le démarrage du régulateur de tension.
PCT/CN2022/096425 2022-03-14 2022-05-31 Régulateur de tension et son procédé de commande WO2023173595A1 (fr)

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