WO2023168753A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2023168753A1
WO2023168753A1 PCT/CN2022/082200 CN2022082200W WO2023168753A1 WO 2023168753 A1 WO2023168753 A1 WO 2023168753A1 CN 2022082200 W CN2022082200 W CN 2022082200W WO 2023168753 A1 WO2023168753 A1 WO 2023168753A1
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layer
dielectric layer
sub
substrate
support
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PCT/CN2022/082200
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English (en)
French (fr)
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宋志浩
李忠华
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长鑫存储技术有限公司
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Priority to EP22782654.2A priority Critical patent/EP4270472A4/en
Priority to US17/804,591 priority patent/US20230320082A1/en
Publication of WO2023168753A1 publication Critical patent/WO2023168753A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure includes a substrate and a bonding pad structure located on the substrate.
  • the bonding pad structure and the substrate are separated by a dielectric layer.
  • the bonding pad structure usually has a large vertical distance from the substrate, and the dielectric layer located under the bonding pad structure has a large thickness, which can easily lead to damage of the semiconductor structure.
  • the stability is poor; in addition, the stress generated when the semiconductor structure is bonded to other structures through the bonding pad structure can easily cause damage to the dielectric layer located under the bonding pad structure, thereby reducing the performance of the semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure, including:
  • the pad structure is located above the support layer, and the material strength of the support layer is greater than the material strength of the first dielectric layer.
  • the material of the support layer includes one or more of silicon germanium, polysilicon, tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride.
  • the first dielectric layer includes a first sub-layer and a second sub-layer located on the first sub-layer; the support layer is formed on the first sub-layer and the second sub-layer. between layers.
  • the support layer is plate-shaped, and the pad structure overlaps with a projection of the support layer in a direction perpendicular to the substrate.
  • the substrate includes a storage area and a peripheral area, and the first dielectric layer, the support layer and the bonding pad structure are all located above the peripheral area.
  • the semiconductor structure further includes:
  • a capacitor structure located above the storage area; a capacitor covering layer covering the upper surface of the capacitor structure.
  • the material of the support layer and the capacitor covering layer are the same.
  • the support layer and the capacitor cover layer are formed in the same process step.
  • the bonding pad structure includes a top metal layer, and the top metal layer is plate-shaped.
  • the bonding pad structure further includes at least one middle metal layer located below the top metal layer, and a conductive plug electrically connecting at least one middle metal layer and the top metal layer in sequence. Plug; wherein, the middle metal layer is annular.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:
  • a bonding pad structure is formed on the first dielectric layer, and the bonding pad structure is located above the support layer.
  • the first dielectric layer includes a first sub-layer and a second sub-layer; forming the first dielectric layer and the support layer on the substrate includes:
  • the second sub-layer is formed, covering the support layer and the first sub-layer.
  • the substrate includes a storage area and a peripheral area, and the first dielectric layer, the support layer and the bonding pad structure are formed above the peripheral area.
  • the method further includes:
  • a capacitor covering layer is formed, and the capacitor covering layer covers the upper surface of the capacitor structure.
  • the capacitor cover layer and the support layer are formed in the same process step.
  • the method further includes: forming a second dielectric layer on the first dielectric layer, and the bonding pad structure is located in the second dielectric layer.
  • forming the bonding pad structure includes: forming a top metal layer, at least one middle metal layer located below the top metal layer, and placing at least one layer of the middle metal layer, the top metal layer Conductive plugs are electrically connected in sequence; wherein, the top metal layer is plate-shaped, the upper surface of the top metal layer is exposed outside the second dielectric layer, and the middle metal layer is ring-shaped.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate; a first dielectric layer located on the substrate; a bonding pad structure located on the first dielectric layer; wherein , there is at least one support layer in the first dielectric layer, the pad structure is located above the support layer, and the material strength of the support layer is greater than the material strength of the first dielectric layer.
  • the semiconductor structure provided by the embodiment of the present disclosure includes a support layer located under the bonding pad structure. The material of the support layer has greater strength than the material of the first dielectric layer. In this way, the support layer can strengthen The stability of the semiconductor structure; at the same time, the support layer can relieve the stress generated during bonding, thereby reducing or eliminating the damage caused by the stress to the first dielectric layer, thereby improving the performance of the semiconductor structure.
  • Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a three-dimensional schematic view of the bonding pad structure shown in Figure 1;
  • Figure 3 is a flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
  • the semiconductor structure includes a substrate and a bonding pad structure located on the substrate.
  • the bonding pad structure and the substrate are separated by a dielectric layer.
  • the semiconductor structure is bonded to other structures through the bonding pad structure.
  • the bonding pad structure usually has a large vertical distance from the substrate, and the dielectric layer located under the bonding pad structure has a large thickness, which can easily lead to damage of the semiconductor structure.
  • the stability is poor; at the same time, when forming the dielectric layer with a large thickness, it is difficult to perform a planarization process on the dielectric layer, resulting in poor flatness of the surface of the dielectric layer.
  • the stress generated when the semiconductor structure is bonded to other structures through the bonding pad structure can easily cause damage to the dielectric layer located under the bonding pad structure, thereby reducing the performance of the semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a first dielectric layer located on the substrate; a bonding pad structure located on the first dielectric layer; wherein, within the first dielectric layer There is at least one support layer, the pad structure is located above the support layer, and the material strength of the support layer is greater than the material strength of the first dielectric layer.
  • the semiconductor structure provided by the embodiment of the present disclosure includes a support layer located under the bonding pad structure.
  • the material of the support layer has greater strength than the material of the first dielectric layer. In this way, the support layer can strengthen The stability of the semiconductor structure; at the same time, the support layer can relieve the stress generated during bonding, thereby reducing or eliminating the damage caused by the stress to the first dielectric layer, thereby improving the performance of the semiconductor structure.
  • the semiconductor structure provided by embodiments of the present disclosure may be a dynamic random access memory (DRAM). But it is not limited thereto, and the semiconductor structure may also be any other semiconductor structure.
  • DRAM dynamic random access memory
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a three-dimensional schematic diagram of the bonding pad structure shown in FIG. 1 .
  • the semiconductor structure provided by the embodiment of the present disclosure will be described in further detail below with reference to FIGS. 1 and 2 .
  • the semiconductor structure includes: a substrate 10; a first dielectric layer 15 located on the substrate 10; a bonding pad structure 19 located on the first dielectric layer 15; wherein, the first There is at least one support layer 16 in the dielectric layer 15 .
  • the pad structure 19 is located above the support layer 16 .
  • the material strength of the support layer 16 is greater than the material strength of the first dielectric layer 15 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate may have structures such as word lines, bit lines, active areas, isolation structures, and contact layers.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 10 includes a storage area and a peripheral area.
  • the substrate 10 further includes an underlying metal layer M0 disposed on the surface of the substrate 10 , a plurality of connection pads 102 , and is located between the underlying metal layer M0 and the plurality of connection pads 102
  • the insulating layer 101; the underlying metal layer M0 is located in the peripheral area, and a plurality of the connection pads 102 are located in the storage area.
  • the underlying metal layer M0 may be electrically connected to some structures located within the substrate 10 .
  • the materials of the underlying metal layer M0 and the connection pad 102 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal One or more types of silicides and metal alloys.
  • the material of the insulating layer 101 may be nitride, such as silicon nitride.
  • the first dielectric layer 15 includes a first sub-layer 151 and a second sub-layer 152 located on the first sub-layer 151; the support layer 16 is formed on the first sub-layer 151. and the second sub-layer 152 .
  • the second sub-layer 152 covers the first sub-layer 151 and the support layer 16.
  • the material of the first sub-layer 151 and the material of the second sub-layer 152 include oxide.
  • the first sub-layer 151 and the second sub-layer 152 are made of the same material, such as silicon oxide. But it is not limited thereto.
  • the material of the first sub-layer 151 and the material of the second sub-layer 152 may also be different.
  • the first dielectric layer 15 and the support layer 16 may be formed as follows: first, forming the first sub-layer 151 on the substrate 10; then, forming the first sub-layer 151 on the substrate 10; The support layer 16 is formed on the layer 151; then, the second sub-layer 152 is formed on the first sub-layer 151 and the support layer 16. More specifically, the first sub-layer 151 and the second sub-layer 152 can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD) and other processes. Optionally, a planarization process can also be used, such as Chemical mechanical polishing (CMP) and/or etching processes are used to planarize the upper surfaces of the first sub-layer 151 and the second sub-layer 152 .
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • a planarization process can also be used, such as Chemical mechanical polishing (CMP) and/or etching processes are used to planarize the upper surfaces of the first sub-layer 151 and the
  • the first sub-layer 151 when forming the first dielectric layer 15 with a larger thickness, the first sub-layer 151 is first formed, and then the second sub-layer 152 is formed.
  • the first sub-layer 151 and the The thickness of the second sub-layer 152 is smaller, which reduces the difficulty of performing a planarization process on the first sub-layer 151 and the second sub-layer 152 compared with related technologies, and increases the thickness of the first sub-layer 151 and the surface flatness of the second sub-layer 152 .
  • the number of layers of the support layer 16 is not limited to that shown in FIG. 1 , and the number of layers of the support layer 16 can be more, such as 2 layers, 3 layers or 4 layers.
  • Multiple layers of the support layer 16 are longitudinally distributed in the first dielectric layer 15 and located below the bonding pad structure 19 .
  • Providing at least one layer of the support layer 16 below the bonding pad structure 19 can enhance the stability of the semiconductor structure and relieve stress caused by bonding. It can be understood that the more layers of the support layer 16 , the better the support effect and stress relief effect it can have, but too many layers will lead to an increase in process complexity. Therefore, the number of layers of the support layer 16 The number should not be too many.
  • the material of the support layer 16 includes one or more of silicon germanium, polysilicon, tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride. But it is not limited thereto. Any material whose material strength meets the above requirements can be used as the support layer 16 in the embodiment of the present disclosure.
  • the support layer 16 is plate-shaped, and the pad structure 19 overlaps with the projection of the support layer 16 in a direction perpendicular to the substrate 10 . But it is not limited thereto.
  • the projection of the bonding pad structure 19 in the direction perpendicular to the substrate 10 may also fall within the projection of the support layer 16 in the direction perpendicular to the substrate 10 .
  • the first dielectric layer 15 , the support layer 16 and the bonding pad structure 19 are all located above the peripheral area.
  • the semiconductor structure further includes: a capacitor structure 11 located above the storage area; and a capacitor covering layer 17 covering the upper surface of the capacitor structure 11 .
  • the capacitor structure 11 includes: a plurality of discrete lower electrode layers 111 located on the substrate 10 , the lower electrode layer 111 has a cylindrical structure, and the plurality of lower electrode layers 111 are connected to a plurality of The connection pads 102 are connected in a one-to-one correspondence; the capacitive dielectric layer 112 covers at least the surface of the lower electrode layer 111; the upper electrode layer 113, the upper electrode layer 113 covers the surface of the capacitive dielectric layer 112; and the upper electrode filling layer 114, located on the upper electrode layer 113 and between the plurality of separate lower electrode layers 111.
  • the capacitor structure 11 is formed before forming the first dielectric layer 15 .
  • the capacitor covering layer 17 covers the upper surface of the upper electrode filling layer 114 .
  • the material of the support layer 16 and the capacitor covering layer 17 are the same.
  • the support layer 16 and the capacitor covering layer 17 are formed in the same process step, and the second sub-layer 152 also covers the capacitor covering layer 17 .
  • the number of the support layers 16 is multiple, at least one layer of the support layer 16 and the capacitor covering layer 17 are formed in the same process step. In this way, the manufacturing process of the semiconductor structure can be simplified.
  • the semiconductor structure further includes a bottom support layer 12, a middle support layer 13 and a top support layer 14 formed sequentially from bottom to top above the peripheral area, and the lower electrode layer 111 is disposed on the The bottom support layer 12 , the middle support layer 13 and the top support layer 14 are used to support the lower electrode layer 111 .
  • the bonding pad structure 19 includes a top metal layer M4, and the top metal layer M4 is plate-shaped.
  • the bonding pad structure 19 further includes at least one middle metal layer M1, M2, M3 located below the top metal layer M4, and at least one middle metal layer M1, M2, M3 , the top metal layer M4 is electrically connected to the conductive plugs V1, V2, and V3 in sequence; wherein the middle metal layers M1, M2, and M3 are ring-shaped.
  • the materials of the top metal layer, the middle metal layer, and the conductive plug include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride.
  • W tungsten
  • Cu copper
  • Ti titanium
  • Ta tantalum
  • TiN titanium nitride
  • tantalum nitride tantalum nitride.
  • TaN metal silicides
  • metal alloys metal alloys.
  • the number of the intermediate metal layers is not limited to that shown in Figure 1 and Figure 2.
  • the number of the intermediate metal layers can be more or less, for example, 1 layer, 2 layers, 4 layers; adjacent layers
  • the number of conductive plugs between two metal layers is not limited to that shown in FIG. 2 , and the number of conductive plugs may be more or less.
  • the semiconductor structure further includes a second dielectric layer 18 located on the first dielectric layer 15 , the bonding pad structure 19 is located within the second dielectric layer 18 , and the top metal layer M4 The upper surface is exposed outside the second dielectric layer 18 .
  • the second dielectric layer 18 is not a single-layer structure, but is formed from multiple layers of insulating materials in multiple process steps.
  • the vertical distance between the bonding pad structure 19 , especially the top metal layer M4 and the substrate 10 is relatively large.
  • the semiconductor structure also includes a capacitor structure 11 with a larger height, further increasing the vertical distance between the bonding pad structure 19 and the substrate 10 .
  • the semiconductor structure provided by the embodiment of the present disclosure includes a support layer 16 located below the bonding pad structure 19.
  • the material of the support layer 16 has greater strength than the material of the first dielectric layer 15. In this way, the The support layer 16 can enhance the stability of the semiconductor structure; at the same time, the support layer 16 can relieve the stress generated during bonding, thereby reducing or eliminating the damage caused by the stress to the first dielectric layer 15, thereby improving the overall stability of the semiconductor structure. Describe the properties of semiconductor structures.
  • Embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, as shown in Figure 3.
  • the method includes the following steps:
  • Step 301 Provide a substrate
  • Step 302 Form a first dielectric layer and at least one support layer located within the first dielectric layer on the substrate; wherein the material strength of the support layer is greater than the material strength of the first dielectric layer;
  • Step 303 Form a bonding pad structure on the first dielectric layer, and the bonding pad structure is located above the support layer.
  • step 301 is performed, as shown in FIG. 4 , to provide a substrate 10 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate may have structures such as word lines, bit lines, active areas, isolation structures, and contact layers.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 10 includes a storage area and a peripheral area.
  • the substrate 10 further includes an underlying metal layer M0 disposed on the surface of the substrate 10 , a plurality of connection pads 102 , and is located between the underlying metal layer M0 and the plurality of connection pads 102
  • the insulating layer 101; the underlying metal layer M0 is located in the peripheral area, and a plurality of the connection pads 102 are located in the storage area.
  • the underlying metal layer M0 may be electrically connected to some structures located within the substrate 10 .
  • the materials of the underlying metal layer M0 and the connection pad 102 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal One or more types of silicides and metal alloys.
  • the material of the insulating layer 101 may be nitride, such as silicon nitride.
  • step 302 is performed. As shown in FIGS. 5-7 , a first dielectric layer 15 and at least one support layer 16 located in the first dielectric layer 15 are formed on the substrate 10; wherein, The material strength of the support layer 16 is greater than the material strength of the first dielectric layer 15 .
  • the first dielectric layer 15 includes a first sub-layer 151 and a second sub-layer 152; forming the first dielectric layer 15 and the support layer 16 on the substrate 10 includes:
  • the first sub-layer 151 is formed on the substrate 10, as shown in Figure 5;
  • the support layer 16 is formed on the first sub-layer 151, as shown in Figure 6;
  • the second sub-layer 152 is formed, and the second sub-layer 152 covers the support layer 16 and the first sub-layer 151 , as shown in FIG. 7 .
  • the first sub-layer 151 and the second sub-layer 152 can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD) and other processes.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • a planarization process can also be used, such as Chemical mechanical polishing (CMP) and/or etching processes are used to planarize the upper surfaces of the first sub-layer 151 and the second sub-layer 152 .
  • CMP Chemical mechanical polishing
  • etching processes are used to planarize the upper surfaces of the first sub-layer 151 and the second sub-layer 152 .
  • the first sub-layer 151 and the The thickness of the second sub-layer 152 is smaller, which reduces the difficulty of performing a planarization process on the first sub-layer 151 and the second sub-layer 152 compared with related technologies, and increases the thickness of the first sub-layer 151 and the surface flatness of the second sub-layer 152 .
  • the material of the first sub-layer 151 and the material of the second sub-layer 152 include oxide.
  • the first sub-layer 151 and the second sub-layer 152 are made of the same material, such as silicon oxide. But it is not limited thereto.
  • the material of the first sub-layer 151 and the material of the second sub-layer 152 may also be different.
  • the support layer 16 is plate-shaped. It should be noted that the number of support layers 16 is not limited to that shown in Figures 6 and 7. More support layers 16 can also be formed in the first dielectric layer 15, such as 2, 3 or 4 layers. , multiple layers of the support layer 16 are longitudinally distributed in the first dielectric layer 15 .
  • the support layer 16 can enhance the stability of the semiconductor structure and relieve stress caused by bonding. It can be understood that the more layers of the support layer 16 , the better the support effect and stress relief effect it can have, but too many layers will lead to an increase in process complexity, so the number of layers of the support layer 16 The number should not be too many.
  • the material of the support layer 16 includes one or more of silicon germanium, polysilicon, tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride. But it is not limited to this, and any material whose material strength meets the above requirements can be used as the support layer 16 in the embodiment of the present disclosure.
  • the method further includes:
  • a capacitor covering layer 17 is formed, and the capacitor covering layer 17 covers the upper surface of the capacitor structure 11 .
  • forming the capacitor structure 11 on the storage area includes: forming a plurality of discrete lower electrode layers 111 on the substrate 10.
  • the lower electrode layer 111 has a cylindrical structure.
  • the plurality of lower electrodes The layer 111 is connected to a plurality of the connection pads 102 in a one-to-one correspondence; a capacitive dielectric layer 112 is formed, and the capacitive dielectric layer 112 at least covers the surface of the lower electrode layer 111; an upper electrode layer 113 is formed, and the upper electrode layer 113 Cover the surface of the capacitive dielectric layer 112; form an upper electrode filling layer 114, the upper electrode filling layer 114 is located on the upper electrode layer 113 and between a plurality of separate lower electrode layers 111.
  • the capacitor structure 11 is formed before forming the first dielectric layer 15 .
  • the capacitor covering layer 17 covers the upper surface of the upper electrode filling layer 114 .
  • the material of the support layer 16 and the capacitor covering layer 17 are the same.
  • the capacitor cover layer 17 and the support layer 16 are formed in the same process step, and the second sub-layer 152 also covers the capacitor cover layer 17 .
  • the number of the support layers 16 is multiple, at least one layer of the support layer 16 and the capacitor covering layer 17 are formed in the same process step. In this way, the manufacturing process of the semiconductor structure is simplified.
  • the method further includes: sequentially forming a bottom support layer 12 , an intermediate support layer 13 and a top support layer 14 above the peripheral area, and the lower electrode layer 111 is formed above the peripheral area.
  • the bottom support layer 12 , the middle support layer 13 and the top support layer 14 are used to support the lower electrode layer 111 .
  • step 303 is performed. As shown in FIGS. 8-9 and 1 , a bonding pad structure 19 is formed on the first dielectric layer 15 , and the bonding pad structure 19 is located above the support layer 16 .
  • the bonding pad structure 19 is formed above the peripheral area. In some embodiments, the bonding pad structure 19 overlaps with the projection of the support layer 16 in a direction perpendicular to the substrate 10 . But it is not limited thereto. The projection of the bonding pad structure 19 in the direction perpendicular to the substrate 10 may also fall within the projection of the support layer 16 in the direction perpendicular to the substrate 10 .
  • the method further includes: forming a second dielectric layer 18 on the first dielectric layer 15, and the bonding pad structure 19 is located on the second dielectric layer 15. within the dielectric layer 18.
  • the second dielectric layer 18 is not a single-layer structure, but is formed from multiple layers of insulating materials in multiple process steps.
  • forming the bonding pad structure 19 includes: forming a top metal layer M4, at least one middle metal layer M1, M2, M3 located below the top metal layer M4, and placing at least one middle metal layer M1 , M2, M3, and the conductive plugs V1, V2, and V3 electrically connected to the top metal layer M4 in sequence; wherein the top metal layer M4 is plate-shaped, and the upper surface of the top metal layer M4 is exposed to the In addition to the two dielectric layers 18, the intermediate metal layers M1, M2, and M3 are ring-shaped.
  • a second dielectric layer 18 is formed on the first dielectric layer 15 , the second dielectric layer 18 is patterned, and an intermediate metal is formed in the patterned second dielectric layer 18 Layer M1;
  • a second dielectric layer 18 covering the intermediate metal layer M1 is formed, a through hole is formed in the second dielectric layer, and a conductive material is formed in the through hole to form the contact.
  • the middle metal layers M2 and M3, the top metal layer M4, and the conductive plugs V2 and V3 that electrically connect the middle metal layers M2, M3, and the top metal layer M4 in sequence are formed, and finally the formation is as shown in Figure 1
  • the structure shown; the formation method of the middle metal layers M2, M3, and the top metal layer M4 is consistent with the formation method of the middle metal layer M1, and the formation method of the conductive plugs V2, V3 is consistent with the formation method of the conductive plugs V2, V3.
  • the plug V1 is formed in the same way.
  • the materials of the top metal layer, the middle metal layer, and the conductive plug include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride.
  • W tungsten
  • Cu copper
  • Ti titanium
  • Ta tantalum
  • TiN titanium nitride
  • tantalum nitride tantalum nitride.
  • TaN metal silicides
  • metal alloys metal alloys.
  • the number of the intermediate metal layers is not limited to that shown in Figure 1 and Figure 2.
  • the number of the intermediate metal layers can be more or less, for example, 1 layer, 2 layers, 4 layers; adjacent layers
  • the number of conductive plugs between two metal layers is not limited to that shown in FIG. 2 , and the number of conductive plugs may be more or less.
  • the semiconductor structure provided by the embodiment of the present disclosure includes a support layer 16 located below the bonding pad structure 19.
  • the material of the support layer 16 has greater strength than the material of the first dielectric layer 15. In this way, the The support layer 16 can enhance the stability of the semiconductor structure; at the same time, the support layer 16 can relieve the stress generated during bonding, thereby reducing or eliminating the damage caused by the stress to the first dielectric layer 15, thereby improving the overall stability of the semiconductor structure. Describe the properties of semiconductor structures.
  • the semiconductor structure provided by the embodiment of the present disclosure includes a support layer located under the bonding pad structure.
  • the material of the support layer has greater strength than the material of the first dielectric layer. In this way, the support layer can strengthen The stability of the semiconductor structure; at the same time, the support layer can relieve the stress generated during bonding, thereby reducing or eliminating the damage caused by the stress to the first dielectric layer, thereby improving the performance of the semiconductor structure.

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Abstract

本公开实施例公开了一种半导体结构及其制造方法，所述半导体结构包括：衬底；第一介质层，位于所述衬底上；焊垫结构，位于所述第一介质层上；其中，所述第一介质层内具有至少一层支撑层，所述焊垫结构位于所述支撑层的上方，所述支撑层的材料强度大于所述第一介质层的材料强度。

Description

一种半导体结构及其制造方法
相关申请的交叉引用
本公开基于申请号为202210237831.5、申请日为2022年03月11日、发明名称为“一种半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
半导体结构，包括衬底及位于衬底上的焊垫结构，焊垫结构与衬底之间由介质层分隔开。
然而，在相关技术中，所述焊垫结构通常与所述衬底之间具有较大的垂直距离，位于所述焊垫结构下方的介质层具有较大的厚度，容易导致所述半导体结构的稳定性较差；此外，所述半导体结构在通过焊垫结构与其他结构进行键合时产生的应力容易对位于所述焊垫结构下方的介质层造成损伤，从而降低所述半导体结构的性能。
发明内容
本公开实施例提供一种半导体结构，包括：
衬底；
第一介质层，位于所述衬底上；
焊垫结构，位于所述第一介质层上；
其中，所述第一介质层内具有至少一层支撑层，所述焊垫结构位于所述支撑层的上方，所述支撑层的材料强度大于所述第一介质层的材料强度。
在一些实施例中，所述支撑层的材料包括硅锗、多晶硅、钨、钛、钽、氮化钨、氮化钛、氮化钽中的一种或多种。
在一些实施例中，所述第一介质层包括第一子层和位于所述第一子层上的第二子层；所述支撑层形成在所述第一子层和所述第二子层之间。
在一些实施例中，所述支撑层呈板状，所述焊垫结构与所述支撑层在垂直于所述衬底的方向上的投影重叠。
在一些实施例中，所述衬底包括存储区和外围区，所述第一介质层、所述支撑层以及所述焊垫结构均位于所述外围区上方。
在一些实施例中，所述半导体结构还包括：
位于所述存储区上方的电容结构；电容覆盖层，所述电容覆盖层覆盖所述电容结构的上表面。
在一些实施例中，所述支撑层的材料和所述电容覆盖层的材料相同。
在一些实施例中，所述支撑层和所述电容覆盖层在同一工艺步骤中形成。
在一些实施例中，所述焊垫结构包括顶层金属层，所述顶层金属层呈板状。
在一些实施例中，所述焊垫结构还包括位于所述顶层金属层下方的至少一层中间金属层，以及将至少一层所述中间金属层、所述顶层金属层依次电连接的导电插塞；其中，所述中间金属层呈环状。
本公开实施例还提供了一种半导体结构的制造方法，包括：
提供衬底；
在所述衬底上形成第一介质层以及位于所述第一介质层内的至少一层支撑层；其中，所述支撑层的材料强度大于所述第一介质层的材料强度；
在所述第一介质层上形成焊垫结构，所述焊垫结构位于所述支撑层的上方。
在一些实施例中，所述第一介质层包括第一子层和第二子层；在所述 衬底上形成所述第一介质层及所述支撑层，包括：
在所述衬底上形成所述第一子层；
在所述第一子层上形成所述支撑层；
形成所述第二子层，所述第二子层覆盖所述支撑层及所述第一子层。
在一些实施例中，所述衬底包括存储区和外围区，所述第一介质层、所述支撑层以及所述焊垫结构形成在所述外围区的上方。
在一些实施例中，所述方法还包括：
在所述存储区上形成电容结构；
形成电容覆盖层，所述电容覆盖层覆盖所述电容结构的上表面。
在一些实施例中，所述电容覆盖层与所述支撑层是在同一工艺步骤中形成。
在一些实施例中，在形成所述第一介质层之后，所述方法还包括：在所述第一介质层上形成第二介质层，所述焊垫结构位于所述第二介质层内。
在一些实施例中，形成所述焊垫结构，包括：形成顶层金属层、位于所述顶层金属层下方的至少一层中间金属层以及将至少一层所述中间金属层、所述顶层金属层依次电连接的导电插塞；其中，所述顶层金属层呈板状，所述顶层金属层的上表面暴露在所述第二介质层之外，所述中间金属层呈环状。
本公开实施例提供的半导体结构及其制造方法，其中，所述半导体结构包括：衬底；第一介质层，位于所述衬底上；焊垫结构，位于所述第一介质层上；其中，所述第一介质层内具有至少一层支撑层，所述焊垫结构位于所述支撑层的上方，所述支撑层的材料强度大于所述第一介质层的材料强度。本公开实施例提供的半导体结构包括位于所述焊垫结构下方的支撑层，所述支撑层的材料相对于所述第一介质层的材料具有更大的强度，如此，所述支撑层能够增强所述半导体结构的稳定性；同时，所述支撑层能够缓解键合时产生的应力，从而降低或消除该应力对所述第一介质层造 成的损伤，进而提高所述半导体结构的性能。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的示意图；
图2为图1中示出的焊垫结构的立体示意图；
图3为本公开实施例提供的半导体结构制造方法的流程框图；
图4-图9为本公开实施例提供的半导体结构的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸 大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和 /或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体结构，包括衬底及位于衬底上的焊垫结构，焊垫结构与衬底之间由介质层分隔开。所述半导体结构通过所述焊垫结构与其他结构进行键合。
然而，在相关技术中，所述焊垫结构通常与所述衬底之间具有较大的垂直距离，位于所述焊垫结构下方的介质层具有较大的厚度，容易导致所述半导体结构的稳定性较差；同时，在形成具有较大厚度的所述介质层时，难以对所述介质层执行平坦化工艺，导致所述介质层表面的平整度较差。此外，所述半导体结构在通过焊垫结构与其他结构进行键合时产生的应力容易对位于所述焊垫结构下方的介质层造成损伤，从而降低所述半导体结构的性能。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体结构，包括：衬底；第一介质层，位于所述衬底上；焊垫结构，位于所述第一介质层上；其中，所述第一介质层内具有至少一层支撑层，所述焊垫结构位于所述支撑层的上方，所述支撑层的材料强度大于所述第一介质层的材料强度。
本公开实施例提供的半导体结构包括位于所述焊垫结构下方的支撑层，所述支撑层的材料相对于所述第一介质层的材料具有更大的强度，如此，所述支撑层能够增强所述半导体结构的稳定性；同时，所述支撑层能够缓解键合时产生的应力，从而降低或消除该应力对所述第一介质层造成的损伤，进而提高所述半导体结构的性能。
本公开实施例提供的半导体结构可以是动态随机存储器(DRAM)。但不限于此，所述半导体结构还可以是其他任何半导体结构。
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开 实施例时，为便于说明，示意图会不依一般比例做局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1为本公开实施例提供的半导体结构的示意图，图2为图1中示出的焊垫结构的立体示意图。以下结合图1、图2对本公开实施例提供的半导体结构再作进一步详细的说明。
如图所示，所述半导体结构包括：衬底10；第一介质层15，位于所述衬底10上；焊垫结构19，位于所述第一介质层15上；其中，所述第一介质层15内具有至少一层支撑层16，所述焊垫结构19位于所述支撑层16的上方，所述支撑层16的材料强度大于所述第一介质层15的材料强度。
所述衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一些实施例中，所述衬底内可以具有字线、位线、有源区、隔离结构以及接触层等结构。在一具体实施例中，所述衬底为硅衬底，所述硅衬底可经掺杂或未经掺杂。
在一实施例中，所述衬底10包括存储区和外围区。在一些实施例中，所述衬底10还包括设置在所述衬底10表面的底层金属层M0、多个连接垫102以及位于所述底层金属层M0和多个所述连接垫102之间的绝缘层101；所述底层金属层M0位于所述外围区，多个所述连接垫102位于所述存储区。所述底层金属层M0可以与位于所述衬底10内的一些结构电连接。所述底层金属层M0和所述连接垫102的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金中的一种或多种。所述绝缘层101的材料可以是氮化物，例如氮化硅。
在一实施例中，所述第一介质层15包括第一子层151和位于所述第一子层151上的第二子层152；所述支撑层16形成在所述第一子层151和所述第二子层152之间。如图1所示，所述第二子层152覆盖所述第一子层 151和所述支撑层16。所述第一子层151的材料和所述第二子层152的材料包括氧化物。在一些实施例中，所述第一子层151的材料和所述第二子层152的材料相同，例如氧化硅。但不限于此，所述第一子层151的材料和所述第二子层152的材料也可以不同。
在实际工艺中，所述第一介质层15和所述支撑层16的形成方式可以是：首先，在所述衬底10上形成所述第一子层151；接着，在所述第一子层151上形成所述支撑层16；接着，在所述第一子层151、所述支撑层16上形成所述第二子层152。更具体的，所述第一子层151、所述第二子层152可以采用原子层沉积(ALD)、化学气相沉积(CVD)等工艺形成，可选的，还可以采用平坦化工艺，如化学机械研磨(CMP)和/或刻蚀工艺，使所述第一子层151、所述第二子层152的上表面平坦化。本公开实施例在形成具有较大厚度的所述第一介质层15时，先形成所述第一子层151，接着形成所述第二子层152，所述第一子层151和所述第二子层152的厚度较小，与相关技术相比，降低了对所述第一子层151和所述第二子层152执行平坦化工艺的难度，增加了所述第一子层151和所述第二子层152的表面平整度。
需要说明的是，所述支撑层16的层数不限于图1所示，所述支撑层16的层数可以更多，例如2层、3层或4层。多层所述支撑层16纵向分布在所述第一介质层15内，且位于所述焊垫结构19的下方。在所述焊垫结构19的下方设置至少一层所述支撑层16，能够增强所述半导体结构的稳定性并缓解由于键合产生的应力。可以理解的，所述支撑层16的层数越多，其能起到的支撑效果和缓解应力的效果越好，但是层数过多会导致工艺复杂度增加，因此所述支撑层16的层数也不宜过多。所述支撑层16的材料包括硅锗、多晶硅、钨、钛、钽、氮化钨、氮化钛、氮化钽中的一种或多种。但不限于此，任何材料强度符合上述要求的材料都可以作为本公开实施例中的支撑层16使用。
在一实施例中，所述支撑层16呈板状，所述焊垫结构19与所述支撑层16在垂直于所述衬底10的方向上的投影重叠。但不限于此，所述焊垫结构19在垂直于所述衬底10的方向上的投影还可以落入所述支撑层16在垂直于所述衬底10的方向上的投影内。
在一实施例中，所述第一介质层15、所述支撑层16以及所述焊垫结构19均位于所述外围区上方。在一些实施例中，所述半导体结构还包括：位于所述存储区上方的电容结构11；电容覆盖层17，所述电容覆盖层17覆盖所述电容结构11的上表面。
具体地，所述电容结构11包括：位于所述衬底10上的多个分立的下电极层111，所述下电极层111具有筒状结构，多个所述下电极层111与多个所述连接垫102一一对应连接；电容介质层112，至少覆盖所述下电极层111的表面；上电极层113，所述上电极层113覆盖所述电容介质层112的表面；上电极填充层114，位于所述上电极层113上以及多个分立的所述下电极层111之间。在一实施例中，在形成所述第一介质层15之前形成所述电容结构11。
如图1所示，所述电容覆盖层17覆盖所述上电极填充层114的上表面。在一实施例中，所述支撑层16的材料和所述电容覆盖层17的材料相同。在一具体的实施例中，所述支撑层16和所述电容覆盖层17在同一工艺步骤中形成，所述第二子层152还覆盖所述电容覆盖层17。当所述支撑层16的数量为多层时，至少一层所述支撑层16和所述电容覆盖层17在同一工艺步骤中形成。如此，能够简化所述半导体结构的制造工艺。
在一实施例中，所述半导体结构还包括从下往上依次形成在所述外围区上方的底层支撑层12、中间支撑层13及顶层支撑层14，所述下电极层111设置在所述底层支撑层12、所述中间支撑层13及所述顶层支撑层14内，所述底层支撑层12、所述中间支撑层13及所述顶层支撑层14用于支撑所述下电极层111。
如图2和图3所示，在一实施例中，所述焊垫结构19包括顶层金属层M4，所述顶层金属层M4呈板状。在一些实施例中，所述焊垫结构19还包括位于所述顶层金属层M4下方的至少一层中间金属层M1、M2、M3，以及将至少一层所述中间金属层M1、M2、M3、所述顶层金属层M4依次电连接的导电插塞V1、V2、V3；其中，所述中间金属层M1、M2、M3呈环状。
所述顶层金属层、所述中间金属层、所述导电插塞的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金中的一种或多种。
需要说明的是，所述中间金属层的数量不限于图1和图2所示，所述中间金属层的数量可以更多或者更少，例如，1层，2层，4层；相邻的两层金属层之间的导电插塞的数量不限于图2所示，所述导电插塞的数量可以更多或者更少。
在一实施例中，所述半导体结构还包括位于所述第一介质层15上的第二介质层18，所述焊垫结构19位于所述第二介质层18内，所述顶层金属层M4的上表面暴露在所述第二介质层18之外。在一些实施例中，所述第二介质层18并非单层结构，其由多层绝缘材料在多次工艺步骤中形成。
所述焊垫结构19尤其是所述顶层金属层M4与所述衬底10之间的垂直距离较大。在一些实施例中，所述半导体结构还包括具有较大高度的电容结构11，进一步增加了所述焊垫结构19与所述衬底10之间的垂直距离。本公开实施例提供的半导体结构包括位于所述焊垫结构19下方的支撑层16，所述支撑层16的材料相对于所述第一介质层15的材料具有更大的强度，如此，所述支撑层16能够增强所述半导体结构的稳定性；同时，所述支撑层16能够缓解键合时产生的应力，从而降低或消除该应力对所述第一介质层15造成的损伤，进而提高所述半导体结构的性能。
本公开实施例还提供了一种半导体结构的制造方法，如图3所示，所 述方法包括以下步骤：
步骤301、提供衬底；
步骤302、在所述衬底上形成第一介质层以及位于所述第一介质层内的至少一层支撑层；其中，所述支撑层的材料强度大于所述第一介质层的材料强度；
步骤303、在所述第一介质层上形成焊垫结构，所述焊垫结构位于所述支撑层的上方。
下面，结合图4-图9对本公开实施例的半导体结构的制造方法再做进一步详细的说明。
首先，执行步骤301，如图4所示，提供衬底10。
所述衬底可以为半导体衬底，并且可以包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底)、至少一个III-V化合物半导体材料、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一些实施例中，所述衬底内可以具有字线、位线、有源区、隔离结构以及接触层等结构。在一具体实施例中，所述衬底为硅衬底，所述硅衬底可经掺杂或未经掺杂。
在一实施例中，所述衬底10包括存储区和外围区。在一些实施例中，所述衬底10还包括设置在所述衬底10表面的底层金属层M0、多个连接垫102以及位于所述底层金属层M0和多个所述连接垫102之间的绝缘层101；所述底层金属层M0位于所述外围区，多个所述连接垫102位于所述存储区。所述底层金属层M0可以与位于所述衬底10内的一些结构电连接。所述底层金属层M0和所述连接垫102的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金中的一种或多种。所述绝缘层101的材料可以是氮化物，例如氮化硅。
接下来，执行步骤302，如图5-图7所示，在所述衬底10上形成第一介质层15以及位于所述第一介质层15内的至少一层支撑层16；其中，所 述支撑层16的材料强度大于所述第一介质层15的材料强度。
具体的，所述第一介质层15包括第一子层151和第二子层152；在所述衬底10上形成所述第一介质层15及所述支撑层16，包括：
在所述衬底10上形成所述第一子层151，如图5所示；
在所述第一子层151上形成所述支撑层16，如图6所示；
形成所述第二子层152，所述第二子层152覆盖所述支撑层16及所述第一子层151，如图7所示。
更具体的，所述第一子层151、所述第二子层152可以采用原子层沉积(ALD)、化学气相沉积(CVD)等工艺形成，可选的，还可以采用平坦化工艺，如化学机械研磨(CMP)和/或刻蚀工艺，使所述第一子层151、所述第二子层152的上表面平坦化。本公开实施例在形成具有较大厚度的所述第一介质层15时，先形成所述第一子层151，接着形成所述第二子层152，所述第一子层151和所述第二子层152的厚度较小，与相关技术相比，降低了对所述第一子层151和所述第二子层152执行平坦化工艺的难度，增加了所述第一子层151和所述第二子层152的表面平整度。所述第一子层151的材料和所述第二子层152的材料包括氧化物。在一些实施例中，所述第一子层151的材料和所述第二子层152的材料相同，例如氧化硅。但不限于此，所述第一子层151的材料和所述第二子层152的材料也可以不同。
在一些实施例中，所述支撑层16呈板状。需要说明的是，所述支撑层16的层数不限于图6和图7所示，还可以在所述第一介质层15内形成更多支撑层16，例如2层、3层或4层，多层所述支撑层16纵向分布在所述第一介质层15内。所述支撑层16能够增强所述半导体结构的稳定性并缓解由于键合产生的应力。可以理解的，所述支撑层16的层数越多，其能起到的支撑效果和缓解应力的效果越好，但是层数过多会导致工艺复杂度增加，因此所述支撑层16的层数也不宜过多。所述支撑层16的材料包括硅锗、多晶硅、钨、钛、钽、氮化钨、氮化钛、氮化钽中的一种或多种。但不限 于此，任何材料强度符合上述要求的材料都可以作为本公开实施例中的支撑层16使用。
在一实施例中，所述第一介质层15、所述支撑层16形成在所述外围区的上方。再次参见图5-图6，在一些实施例中，所述方法还包括：
在所述存储区上形成电容结构11；
形成电容覆盖层17，所述电容覆盖层17覆盖所述电容结构11的上表面。
具体的，在所述存储区上形成电容结构11，包括：在所述衬底10上形成多个分立的下电极层111，所述下电极层111具有筒状结构，多个所述下电极层111与多个所述连接垫102一一对应连接；形成电容介质层112，所述电容介质层112至少覆盖所述下电极层111的表面；形成上电极层113，所述上电极层113覆盖所述电容介质层112的表面；形成上电极填充层114，所述上电极填充层114位于所述上电极层113上以及多个分立的所述下电极层111之间。在一实施例中，在形成所述第一介质层15之前形成所述电容结构11。
如图6所示，所述电容覆盖层17覆盖所述上电极填充层114的上表面。在一实施例中，所述支撑层16的材料和所述电容覆盖层17的材料相同。在一具体实施例中，所述电容覆盖层17与所述支撑层16是在同一工艺步骤中形成，所述第二子层152还覆盖所述电容覆盖层17。当所述支撑层16的数量为多层时，至少一层所述支撑层16和所述电容覆盖层17在同一工艺步骤中形成。如此，简化了所述半导体结构的制造工艺。
继续参见图5，在一实施例中，所述方法还包括：在所述外围区的上方依次形成底层支撑层12、中间支撑层13及顶层支撑层14，所述下电极层111形成在所述底层支撑层12、所述中间支撑层13及所述顶层支撑层14内，所述底层支撑层12、所述中间支撑层13及所述顶层支撑层14用于支撑所述下电极层111。
接下来，执行步骤303，如图8-图9、图1所示，在所述第一介质层15上形成焊垫结构19，所述焊垫结构19位于所述支撑层16的上方。
在一实施例中，所述焊垫结构19形成在所述外围区的上方。在一些实施例中，所述焊垫结构19与所述支撑层16在垂直于所述衬底10的方向上的投影重叠。但不限于此，所述焊垫结构19在垂直于所述衬底10的方向上的投影还可以落入所述支撑层16在垂直于所述衬底10的方向上的投影内。
再次参见图8-图9、图1，在一实施例中，所述方法还包括：在所述第一介质层15上形成第二介质层18，所述焊垫结构19位于所述第二介质层18内。在一些实施例中，所述第二介质层18并非单层结构，其由多层绝缘材料在多次工艺步骤中形成。
具体的，形成所述焊垫结构19，包括：形成顶层金属层M4、位于所述顶层金属层M4下方的至少一层中间金属层M1、M2、M3以及将至少一层所述中间金属层M1、M2、M3、所述顶层金属层M4依次电连接的导电插塞V1、V2、V3；其中，所述顶层金属层M4呈板状，所述顶层金属层M4的上表面暴露在所述第二介质层18之外，所述中间金属层M1、M2、M3呈环状。
下面，结合图8-图9、图1详细说明所述焊垫结构19的制造过程，需要明确的是，以下叙述的制造过程仅是一种示例，还可以采用其他方法来形成所述焊垫结构19。
首先，如图8所示，在所述第一介质层15上形成第二介质层18，将所述第二介质层18图案化，在所述图案化的第二介质层18内形成中间金属层M1；
接下来，如图9所示，形成覆盖所述中间金属层M1的第二介质层18，在所述第二介质层内形成通孔，在所述通孔内形成导电材料以形成所述接触孔V1；
接下来，形成所述中间金属层M2、M3、顶层金属层M4以及将所述中间金属层M2、M3、所述顶层金属层M4依次电连接的导电插塞V2、V3，最终形成如图1所示的结构；所述中间金属层M2、M3、所述顶层金属层M4的形成方法与所述中间金属层M1的形成方法一致，所述导电插塞V2、V3的形成方法与所述导电插塞V1的形成方法一致。
所述顶层金属层、所述中间金属层、所述导电插塞的材料包括钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金属硅化物、金属合金中的一种或多种。
需要说明的是，所述中间金属层的数量不限于图1和图2所示，所述中间金属层的数量可以更多或者更少，例如，1层，2层，4层；相邻的两层金属层之间的导电插塞的数量不限于图2所示，所述导电插塞的数量可以更多或者更少。
本公开实施例提供的半导体结构包括位于所述焊垫结构19下方的支撑层16，所述支撑层16的材料相对于所述第一介质层15的材料具有更大的强度，如此，所述支撑层16能够增强所述半导体结构的稳定性；同时，所述支撑层16能够缓解键合时产生的应力，从而降低或消除该应力对所述第一介质层15造成的损伤，进而提高所述半导体结构的性能。
应当说明的是，本领域技术人员能够对上述步骤顺序进行变换而并不离开本公开的保护范围，以上所述，仅为本公开的可选实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供的半导体结构包括位于所述焊垫结构下方的支撑层，所述支撑层的材料相对于所述第一介质层的材料具有更大的强度，如此，所述支撑层能够增强所述半导体结构的稳定性；同时，所述支撑层能 够缓解键合时产生的应力，从而降低或消除该应力对所述第一介质层造成的损伤，进而提高所述半导体结构的性能。

Claims (17)

  1. 一种半导体结构，包括：
    衬底；
    第一介质层，位于所述衬底上；
    焊垫结构，位于所述第一介质层上；
    其中，所述第一介质层内具有至少一层支撑层，所述焊垫结构位于所述支撑层的上方，所述支撑层的材料强度大于所述第一介质层的材料强度。
  2. 根据权利要求1所述的半导体结构，其中，所述支撑层的材料包括硅锗、多晶硅、钨、钛、钽、氮化钨、氮化钛、氮化钽中的一种或多种。
  3. 根据权利要求1所述的半导体结构，其中，所述第一介质层包括第一子层和位于所述第一子层上的第二子层；所述支撑层形成在所述第一子层和所述第二子层之间。
  4. 根据权利要求1所述的半导体结构，其中，所述支撑层呈板状，所述焊垫结构与所述支撑层在垂直于所述衬底的方向上的投影重叠。
  5. 根据权利要求1所述的半导体结构，其中，所述衬底包括存储区和外围区，所述第一介质层、所述支撑层以及所述焊垫结构均位于所述外围区上方。
  6. 根据权利要求5所述的半导体结构，其中，所述半导体结构还包括：
    位于所述存储区上方的电容结构；电容覆盖层，所述电容覆盖层覆盖所述电容结构的上表面。
  7. 根据权利要求6所述的半导体结构，其中，所述支撑层的材料和所述电容覆盖层的材料相同。
  8. 根据权利要求7所述的半导体结构，其中，所述支撑层和所述电容覆盖层在同一工艺步骤中形成。
  9. 根据权利要求1所述的半导体结构，其中，所述焊垫结构包括顶层 金属层，所述顶层金属层呈板状。
  10. 根据权利要求9所述的半导体结构，其中，所述焊垫结构还包括位于所述顶层金属层下方的至少一层中间金属层，以及将至少一层所述中间金属层、所述顶层金属层依次电连接的导电插塞；其中，所述中间金属层呈环状。
  11. 一种半导体结构的制造方法，包括：
    提供衬底；
    在所述衬底上形成第一介质层以及位于所述第一介质层内的至少一层支撑层；其中，所述支撑层的材料强度大于所述第一介质层的材料强度；
    在所述第一介质层上形成焊垫结构，所述焊垫结构位于所述支撑层的上方。
  12. 根据权利要求11所述的制造方法，其中，所述第一介质层包括第一子层和第二子层；在所述衬底上形成所述第一介质层及所述支撑层，包括：
    在所述衬底上形成所述第一子层；
    在所述第一子层上形成所述支撑层；
    形成所述第二子层，所述第二子层覆盖所述支撑层及所述第一子层。
  13. 根据权利要求11所述的制造方法，其中，所述衬底包括存储区和外围区，所述第一介质层、所述支撑层以及所述焊垫结构形成在所述外围区的上方。
  14. 根据权利要求13所述的制造方法，其中，所述方法还包括：
    在所述存储区上形成电容结构；
    形成电容覆盖层，所述电容覆盖层覆盖所述电容结构的上表面。
  15. 根据权利要求14所述的制造方法，其中，所述电容覆盖层与所述支撑层是在同一工艺步骤中形成。
  16. 根据权利要求11所述的制造方法，其中，在形成所述第一介质层 之后，所述方法还包括：在所述第一介质层上形成第二介质层，所述焊垫结构位于所述第二介质层内。
  17. 根据权利要求16所述的制造方法，其中，形成所述焊垫结构，包括：形成顶层金属层、位于所述顶层金属层下方的至少一层中间金属层以及将至少一层所述中间金属层、所述顶层金属层依次电连接的导电插塞；其中，所述顶层金属层呈板状，所述顶层金属层的上表面暴露在所述第二介质层之外，所述中间金属层呈环状。
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