WO2023164795A1 - 片外输出级驱动电路 - Google Patents

片外输出级驱动电路 Download PDF

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Publication number
WO2023164795A1
WO2023164795A1 PCT/CN2022/078574 CN2022078574W WO2023164795A1 WO 2023164795 A1 WO2023164795 A1 WO 2023164795A1 CN 2022078574 W CN2022078574 W CN 2022078574W WO 2023164795 A1 WO2023164795 A1 WO 2023164795A1
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Prior art keywords
signal
output
circuit
amplifier
output stage
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PCT/CN2022/078574
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English (en)
French (fr)
Inventor
胡伟波
秦克凡
马伟
汪青
于洪宇
肖知明
Original Assignee
南开大学
南方科技大学
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Priority to PCT/CN2022/078574 priority Critical patent/WO2023164795A1/zh
Publication of WO2023164795A1 publication Critical patent/WO2023164795A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor

Definitions

  • the embodiments of the present application relate to the technical field of electronic circuits, for example, to an off-chip output stage driving circuit.
  • An embodiment of the present application provides an off-chip output stage driving circuit, so as to improve the driving capability of the driving circuit and reduce energy waste.
  • An embodiment of the present application provides an off-chip output stage drive circuit, including:
  • an amplification module configured to receive an input signal, and amplify the input signal to output a primary output signal
  • a driving module configured to generate a driving signal according to the primary output signal, the driving signal is used to drive an off-chip output stage circuit, and make the off-chip output stage circuit generate an output stage current;
  • a calibration module configured to convert the output stage current into a comparison voltage, output an adjustment signal according to a comparison result between the comparison voltage and a reference voltage, and feed back the adjustment signal to the driving module, so that the driving module
  • the driving signal is adjusted according to the adjustment signal, so that the output stage current meets a preset condition.
  • the amplification module includes:
  • a differential amplifier circuit configured to receive a first input signal and a second input signal, and amplify and process the first input signal and the second input signal to form an amplified signal
  • the level shifting circuit is used for adjusting the DC bias voltage of the amplified signal to form a first primary output signal and a second primary output signal with different voltages.
  • the drive module includes:
  • the first gate drive circuit is configured to amplify the first primary output signal to form a first drive signal, and the first drive signal is used to drive the off-chip output stage circuit so that the off-chip output
  • the stage circuit generates a first output signal
  • the second gate driving circuit is used to amplify the second primary output signal to form a second driving signal, and the second driving signal is used to drive the off-chip output stage circuit so that the off-chip output The stage circuit generates a second output signal.
  • the calibration module includes:
  • a first calibration circuit configured to output a first adjustment signal according to the ratio of the first output signal to a first reference voltage, and feed back the first adjustment signal to the first gate drive circuit, so that the first gate drive circuit adjusts the first drive signal according to the first adjustment signal;
  • a second calibration circuit configured to output a second adjustment signal according to the ratio of the second output signal to a second reference voltage, and feed back the second adjustment signal to the second gate drive circuit, so that the The second gate driving circuit adjusts the second driving signal according to the second adjusting signal.
  • the first gate drive circuit includes a first amplifier, a first adjustable current source, a first input resistor and a first voltage dividing resistor;
  • the positive input terminal of the first amplifier is used to receive the first primary output signal, the negative input terminal of the first amplifier is grounded through the first input resistor, and the output terminal of the first amplifier is used to output the The first drive signal;
  • the first voltage dividing resistor is arranged between the negative input terminal of the first amplifier and the output terminal of the first amplifier;
  • One end of the first adjustable current source is connected to the working power supply, and the other end is connected to the negative input end of the first amplifier.
  • the second gate drive circuit includes a second amplifier, a second adjustable current source, a second input resistor and a second voltage dividing resistor;
  • the positive input terminal of the second amplifier is used to receive the second primary output signal, the negative input terminal of the second amplifier is grounded through the second input resistor, and the output terminal of the second amplifier is used to output the The second drive signal;
  • the second voltage dividing resistor is arranged between the negative input terminal of the second amplifier and the output terminal of the second amplifier;
  • One end of the second adjustable current source is connected to the working power supply, and the other end is connected to the negative input end of the second amplifier.
  • the off-chip output stage circuit includes a PMOS transistor and an NMOS transistor; the gate of the PMOS transistor is connected to the output terminal of the first amplifier through a first switch, and the gate of the NMOS transistor is connected to the output terminal of the first amplifier through a second switch.
  • the output end of the second amplifier is connected; the source of the PMOS transistor is connected to the working power supply, the source of the NMOS transistor is grounded; the drain of the PMOS transistor is connected to the drain of the NMOS transistor.
  • the first calibration circuit includes a first reference amplifier, a first comparator, a first preset current source, a first transistor, a first comparison resistor, a second comparison resistor and a first control signal generating circuit;
  • the negative input terminal of the first reference amplifier is used to receive a preset voltage signal, the positive input terminal of the first reference amplifier is connected to the drain of the PMOS transistor through a third switch, and the output terminal of the first reference amplifier connected to the gate of the first transistor;
  • the drain of the first transistor is connected to the positive input terminal of the first reference amplifier
  • One end of the first comparison resistor is connected to the source of the first transistor and the first input end of the first comparator, and the other end is grounded;
  • One end of the second comparison resistor is connected to the first preset current source and the second input end of the first comparator, and the other end is grounded;
  • the output end of the first comparator is connected to the first control signal generating circuit, and the first control signal generating circuit is connected to the first adjustable current source.
  • the second calibration circuit includes a second reference amplifier, a second comparator, a second preset current source, a second transistor, a third comparison resistor, a fourth comparison resistor and a second control signal generating circuit;
  • the negative input terminal of the second reference amplifier is used to receive a preset voltage signal, the positive input terminal of the second reference amplifier is connected to the drain of the NMOS transistor through a fourth switch, and the output terminal of the second reference amplifier connected to the gate of the second transistor;
  • the source of the second transistor is connected to the positive input terminal of the second reference amplifier
  • One end of the third comparison resistor is connected to the drain of the second transistor and the first input end of the second comparator, and the other end is connected to a working power supply;
  • One end of the fourth comparison resistor is connected to the second preset current source and the second input end of the second comparator, and the other end is connected to a working power supply;
  • the output end of the second comparator is connected to the second control signal generating circuit, and the second control signal generating circuit is connected to the second adjustable current source.
  • the first control signal generation circuit includes a count clock generation circuit, a comparator clock generation circuit and a count unit;
  • the counting clock generating circuit includes an inverter and a plurality of D flip-flops, the clock signal terminals of all D flip-flops are connected to a preset clock signal, and the data input end of the i-th D flip-flop is connected to the i-1th D flip-flop.
  • the data output end of the flip-flop is connected, wherein, i ⁇ n; the input end of the inverter is connected to the data output end of the last D flip-flop, and the output end of the inverter is connected to the enable ends of all D flip-flops ;
  • the comparator clock generating circuit includes a buffer and an OR gate logic circuit, the input end of the buffer is connected to the data output end of the D flip-flop, and the output end of the buffer is connected to one of the OR gate logic circuits.
  • an input terminal, the other input terminal of the OR gate logic circuit is connected to the preset clock signal, and the output terminal of the OR gate logic circuit is connected to the clock signal terminal of the first comparator;
  • the number fetching unit includes a clock terminal, a signal input terminal and a signal output terminal, the clock terminal is connected to the data output terminal of the D flip-flop, the signal input terminal is connected to the output terminal of the first comparator, and the The signal output end is connected to the first adjustable current source.
  • the off-chip output stage drive circuit provided by the embodiment of the present application introduces a calibration circuit into the off-chip output stage drive circuit, so that the circuit as a whole forms a feedback regulation, which can adjust the current in the off-chip output stage circuit at any time, that is, the output stage current
  • the self-adaptive calibration can improve the driving capability of the driving circuit and reduce energy waste.
  • FIG. 1 is a schematic diagram of an off-chip output stage drive circuit provided in Embodiment 1 of the present application;
  • FIG. 2 is a schematic diagram of an off-chip output stage drive circuit provided in Embodiment 2 of the present application;
  • FIG. 3 is a schematic structural diagram of the amplification module provided in Embodiment 2 of the present application.
  • FIG. 4 is a schematic structural diagram of a first control signal generating circuit provided in Embodiment 2 of the present application.
  • FIG. 5 is a schematic structural diagram of a count clock generating circuit provided in Embodiment 2 of the present application.
  • FIG. 6 is a schematic structural diagram of a comparator clock generating circuit provided in Embodiment 2 of the present application.
  • FIG. 7 is a schematic structural diagram of the number fetching unit provided in Embodiment 2 of the present application.
  • FIG. 8 is a working timing diagram of the comparator provided in Embodiment 2 of the present application.
  • FIG. 9 is a schematic diagram of current changes in the calibration process provided by Embodiment 2 of the present application.
  • Some exemplary embodiments are described as processes or circuits depicted as flowcharts. Although the flowcharts describe the steps as sequential processing, many of the steps may be performed in parallel, concurrently, or simultaneously. Additionally, the order of steps may be rearranged. A process may be terminated when its operations are complete, but may also have additional steps not included in the figure. A process may correspond to a circuit, function, procedure, subroutine, subroutine, or the like.
  • first”, “second”, etc. may be used herein to describe various directions, actions, steps or elements, etc., but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element.
  • the terms “first”, “second”, etc. should not be interpreted as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the meanings of "plurality” and “batch” are at least two, such as two, three, etc., unless otherwise specifically defined.
  • FIG. 1 is a schematic diagram of an off-chip output stage driving circuit provided by an embodiment of the present application.
  • the off-chip output stage drive circuit provided by the embodiment of the present application includes: an amplification module 100, a drive module 200 and a calibration module 300, the amplification module 100 is connected to the drive module 200, and the drive module 200 is connected to the off-chip output stage circuit 400 , the calibration module 300 is connected between the off-chip output stage circuit 400 and the driving module 200 to form feedback regulation.
  • the off-chip output stage circuit is referred to as off-chip output stage or output stage for short, and details will not be described later.
  • the amplifying module 100 receives an input signal (such as an input voltage signal), and amplifies the input signal to output a primary output signal.
  • the driving module 200 takes the primary output signal of the amplification module 100 as an input, and generates a driving signal according to the primary output signal.
  • the driving signal is input into the off-chip output stage circuit 400, and the off-chip output stage circuit 400 is driven to generate an output signal.
  • the output signal generated by the off-chip output stage circuit 400 includes an output voltage and an output stage current, the output voltage is used to supply power to the load connected to the off-chip output stage circuit 400, and the output stage current is the current flowing through the off-chip output stage circuit 400 .
  • the DC output voltage generated by the off-chip output stage circuit 400 is a common-mode voltage signal.
  • the embodiment of the present application introduces the calibration module 300 .
  • the calibration module 300 detects the output stage current generated by the off-chip output stage circuit 400, converts the output stage current into a comparison voltage, compares the comparison voltage with a known reference voltage, and outputs an adjustment signal.
  • the adjustment signal is fed back to the driving module 200 to change the magnitude of the driving signal, and the change of the driving signal affects the magnitude of the output stage current of the off-chip output stage circuit 400 .
  • the comparison voltage converted by the output stage current will be greater than the reference voltage, and the adjustment signal fed back to the drive module 200 is to reduce the drive signal; when the drive signal decreases Small, the output stage current is reduced to achieve the purpose of adjusting the output stage current.
  • the reference voltage represents an adjustment target of the output stage current, and when the corresponding comparison voltage is consistent with the reference voltage, it means that the output stage current meets the preset condition.
  • the off-chip output stage drive circuit provided by the embodiment of the present application introduces a calibration circuit into the off-chip output stage drive circuit, so that the circuit as a whole forms a feedback regulation, which can adjust the current in the off-chip output stage circuit at any time, that is, the output stage current
  • the self-adaptive calibration can improve the driving capability of the driving circuit and reduce energy waste.
  • FIG. 2 is a schematic structural diagram of an off-chip output stage driving circuit provided in Embodiment 2 of the present application.
  • the off-chip output stage drive circuit provided by Embodiment 2 of the present application includes: an amplification module 100, a driving module 200 and a calibration module 300, the amplification module 100 is connected to the driving module 200, and the driving module 200 is connected to the off-chip output stage
  • the circuit 400 and the calibration module 300 are connected between the off-chip output stage circuit 400 and the driving module 200 to form feedback regulation.
  • the specific circuit structure of the amplification module 100 is shown in FIG. 3 .
  • the amplification module 100 includes a differential amplification circuit 110 and a level shift circuit 120 .
  • the differential amplifier circuit 110 adopts a folded differential input stage structure, so that a larger input voltage range can be obtained.
  • the differential amplifier circuit 110 includes NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, PMOS tube M9, PMOS tube M10, PMOS tube M11, PMOS tube Tube M12, PMOS tube M13, capacitor C1 and capacitor C2.
  • the gate of the NMOS transistor M1 is used to receive the first input signal Vin+, and the gate of the NMOS transistor M2 is used to receive the second input signal Vin ⁇ .
  • the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and then connected to the drain of the NMOS transistor M4.
  • the source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M3.
  • the drain of the PMOS transistor M9 is connected to the source of the PMOS transistor M11 and connected to the drain of the NMOS transistor M1, the drain of the PMOS transistor M11 is connected to the source of the PMOS transistor M13, and the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M7.
  • the drain is connected, the source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M5.
  • the drain of the PMOS transistor M10 is connected to the source of the PMOS transistor M12 and to the drain of the NMOS transistor M2 , and the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M6 .
  • the source of the PMOS transistor M9 and the source of the PMOS transistor M10 are jointly connected to the positive pole of the working power supply; the sources of the NMOS transistor M3, the source of the NMOS transistor M5 and the source of the NMOS transistor M5 are commonly connected to the negative pole of the working power supply.
  • the gate of the NMOS transistor M4 is connected to the working voltage Vb2, the gate of the NMOS transistor M3 is connected to the working voltage Vb1, the gate of the NMOS transistor M5 is connected to the gate of the NMOS transistor M6 and connected to the drain of the NMOS transistor M7, and the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M6.
  • the gate and the gate of the NMOS transistor M8 are connected to the working voltage Vb3, the gate of the PMOS transistor M9 and the gate of the PMOS transistor M10 are connected to the working voltage Vb4, the gate of the PMOS transistor M11 and the gate of the PMOS transistor M12 are connected to the working voltage Vb5, The gate of the PMOS transistor M13 is connected to the working voltage Vb6.
  • a capacitor C1 and a capacitor C2 are connected in series between the drain of the PMOS transistor M12 and the drain of the NMOS transistor M8.
  • the common terminal of the capacitor C1 and the capacitor C2 outputs an amplified signal V0, which is the signal outputted by the differential amplifier circuit 110 after amplifying the first input signal Vin+ and the second input signal Vin ⁇ .
  • the function of the level shift circuit 120 is to change the DC bias voltage of the output signal of the differential amplifier circuit 110 (that is, the amplified signal V0), so that it is separated into the first primary output signal Vo1 and the second primary output signal Vo2, and the first primary output signal Vo1 and the second primary output signal Vo2 are two different voltages, one is a high level signal and the other is a low level signal.
  • the level shift circuit 120 includes a PMOS transistor Mp1, a PMOS transistor Mp2, an NMOS transistor Mn1 and an NMOS transistor Mn2.
  • the drain of the PMOS transistor Mp1 is connected to the source of the PMOS transistor Mp2, and the source of the NMOS transistor Mn1 is connected to the drain of the NMOS transistor Mn2.
  • the source of the PMOS transistor Mp1 is connected to the drain of the NMOS transistor Mn1 and connected to the drain of the PMOS transistor M12
  • the source of the NMOS transistor Mn2 is connected to the drain of the PMOS transistor Mp2 and connected to the drain of the NMOS transistor M8 .
  • the gate of the PMOS transistor Mp1 is connected to the working voltage Vbp2
  • the gate of the PMOS transistor Mp2 is connected to the working voltage Vbp2
  • the gate of the NMOS transistor Mn1 is connected to the working voltage Vbn1
  • the gate of the NMOS transistor Mn2 is connected to the working voltage Vbn2.
  • the common end of the PMOS transistor Mp1 and the NMOS transistor Mn1 outputs the first primary output signal Vo1
  • the common end of the NMOS transistor Mn2 and the PMOS transistor Mp2 outputs the second primary output signal Vo2.
  • the driving module 200 includes a first gate driving circuit 210 and a second gate driving circuit 220 .
  • the first gate driving circuit 210 receives the first primary output signal Vo1, amplifies the first primary output signal Vo1, and outputs a first driving signal Vop.
  • the second gate driving circuit 220 receives the second primary output signal Vo2, amplifies the second primary output signal Vo2, and outputs the second driving signal Von.
  • the first gate driving circuit 210 includes a first amplifier A1 , a first adjustable current source I1 , a first input resistor Rr1 and a first voltage dividing resistor Rf1 .
  • the positive input end of the first amplifier A1 is connected to the common end of the PMOS transistor Mp1 and the NMOS transistor Mn1 to receive the first primary output signal Vo1.
  • the negative input terminal of the first amplifier A1 is grounded through the first input resistor Rr1, and the output terminal of the first amplifier A1 is used to output the first drive signal Vop;
  • the first voltage dividing resistor Rf1 is arranged between the negative input terminal of the first amplifier A1 and the first amplifier A1.
  • one end of the first adjustable current source I1 is connected to the working power supply Vdd, and the other end is connected to the negative input end of the first amplifier A1.
  • the second gate driving circuit 220 includes a second amplifier A2 , a second adjustable current source I2 , a second input resistor Rr2 and a second voltage dividing resistor Rf2 .
  • the positive input end of the second amplifier A2 is connected to the common end of the PMOS transistor Mp2 and the NMOS transistor Mn2 to receive the second primary output signal Vo2.
  • the negative input terminal of the second amplifier A2 is connected to the working power supply Vdd through the second input resistor Rr2, and the output terminal of the second amplifier A2 is used to output the second drive signal Von; the second voltage dividing resistor Rf2 is set at the negative input of the second amplifier A2 Between the terminal and the output terminal of the second amplifier A2; one terminal of the second adjustable current source I2 is connected to the working power supply Vdd, and the other terminal is connected to the negative input terminal of the second amplifier A2.
  • the first driving signal Vop output by the first gate driving circuit 210 and the second driving signal Von output by the second gate driving circuit 220 are the driving signals of the off-chip output stage circuit 400 .
  • the off-chip output stage circuit 400 adopts a class A and B output stage structure, which is composed of a discrete PMOS transistor Mm1 and a discrete NMOS transistor Mm2, as shown in FIG. 2 .
  • the source of the PMOS transistor Mm1 is connected to the working power supply Vdd
  • the drain of the PMOS transistor Mm1 is connected to the drain of the NMOS transistor Mm2, and the source of the NMOS transistor Mm2 is grounded.
  • the gate of the PMOS transistor Mm1 is connected to the output terminal of the first amplifier A1 through the first switch S1 to receive the first driving signal Vop; the gate of the NMOS transistor Mm2 is connected to the output terminal of the second amplifier A2 through the second switch S2 to receive The second driving signal Von.
  • the common end formed by the drain of the PMOS transistor Mm1 and the drain of the NMOS transistor Mm2 is the signal output end of the off-chip output stage circuit 400, and the signal output end is used to output the subsequent load circuit connected to the off-chip output stage circuit 400 The desired voltage signal Vout.
  • the off-chip output stage circuit 400 may also have other structures, and a suitable transistor may be selected according to a specific application scenario.
  • the size of the output stage DC bias is a key parameter that affects the overall circuit performance and power consumption. If the DC bias is large, a lot of power is wasted when the input signal is small. If the DC bias is small, it will affect the linearity of the circuit.
  • this embodiment adds a calibration module 300 to the off-chip output stage drive circuit, corresponding to the Class A and B output stage structure in this embodiment, the calibration module 300 includes a first calibration circuit 310 and a second calibration circuit 320 .
  • the first calibration circuit 310 includes a first reference amplifier Aa1, a first comparator Ab1, a first preset current source If1, a first transistor T1, a first comparison resistor R1, a second comparison resistor R2 and a first comparison resistor R2.
  • a control signal generating circuit 311 is shown in FIG. 2, the first calibration circuit 310 includes a first reference amplifier Aa1, a first comparator Ab1, a first preset current source If1, a first transistor T1, a first comparison resistor R1, a second comparison resistor R2 and a first comparison resistor R2.
  • the negative input terminal of the first reference amplifier Aa1 is used to receive the preset voltage signal VCM, the positive input terminal of the first reference amplifier Aa1 is connected to the drain of the PMOS transistor Mm1 through the third switch S3, and the output terminal of the first reference amplifier Aa1 is connected to the first The gate of a transistor T1; the drain of the first transistor T1 is connected to the positive input terminal of the first reference amplifier Aa1; one end of the first comparison resistor R1 is connected to the source of the first transistor T1 and the first input of the first comparator Ab1 end, the other end is grounded; one end of the second comparison resistor R2 is connected to the first preset current source If1 and the second input end of the first comparator Ab1, and the other end is grounded; the output end of the first comparator Ab1 is connected to the first control signal
  • the generating circuit 311 is connected, and the first control signal generating circuit 311 is connected to the first adjustable current source I1.
  • the first control signal generation circuit 311 includes a count clock generation circuit 3111 , a comparator clock generation circuit 3112 and a count unit 3113 .
  • the first control signal generation circuit 311 generates the first adjustment signal CTL1 ⁇ i> according to the signal at the output terminal of the first comparator Ab1, and feeds back the first adjustment signal CTL1 ⁇ i> to the first adjustable current source I1, so that the first The output current of the adjustable current source I1 changes, thereby changing the first driving signal Vop.
  • the first calibration circuit 310 is used to calibrate the first driving signal Vop.
  • the data fetching clock generating circuit 3111 includes an inverter and a plurality of D flip-flops, the clock signal terminals of all D flip-flops are connected to the preset clock signal, the data input end of the i-th D flip-flop and the data input end of the i-th D flip-flop The data output terminals of i-1 D flip-flops are connected, where i ⁇ n; the input terminal of the inverter is connected to the data output terminal of the last D flip-flop, and the output terminal of the inverter is connected to the enable of all D flip-flops end. As shown in FIG.
  • the count clock generation circuit 3111 includes an inverter and 10 D flip-flops (denoted as DFF ⁇ 1> ⁇ DFF ⁇ 10>).
  • the clock signal terminals (CK pins) of all D flip-flops are connected to the preset clock signal CLK_IN.
  • the data input terminal (D pin) of the first D flip-flop DFF ⁇ 1> is connected to the working power supply Vdd, after that, the data output terminal (Q pin) of the previous D flip-flop is connected to the data input terminal of the next D flip-flop (D pin) connection.
  • the data output terminal (Q pin) of the last D flip-flop DFF ⁇ 10> is connected to the input terminal of the inverter.
  • the output end of the inverter is connected with the enable end (RN pin) of all D flip-flops.
  • the output signal of the i-th D flip-flop is recorded as SHFT ⁇ i>.
  • the comparator clock generating circuit 3112 includes a buffer F and an OR gate logic circuit, and the input end of the buffer is connected to the data output end (Q pin) of the D flip-flop to receive the output signal of the last D flip-flop.
  • the output end of the buffer is connected to an input end of the OR gate logic circuit; the other input end of the OR gate logic circuit is connected to the preset clock signal CLK_IN, and the output end of the OR gate logic circuit is connected to the clock signal end of the first comparator Ab1 (wherein , the clock signal terminal of the first comparator Ab1 is not shown in the figure) to output the comparator clock signal CLKC.
  • the fetching unit 3113 is also composed of D flip-flops. As shown in FIG. 7 , the fetching unit 3113 includes a clock terminal (CK pin), a signal input terminal (D pin), a signal output terminal (Q pin) and an enable terminal (RN pin).
  • the clock terminal (CK pin) is connected to the data output terminal of the D flip-flop in the data fetching clock generation circuit 3111, that is, the clock signal of the data fetching unit 3113 is the output signal SHFT ⁇ i> of the D flip-flop, and the i-th output
  • the signal SHFT ⁇ i> represents the i-th fetch cycle.
  • the signal input end (D pin) is connected to the output end of the first comparator Ab1 for receiving the comparison result COMP_OUT output by the first comparator Ab1.
  • the signal output terminal (Q pin) is connected to the first adjustable current source I1 for feeding back the first adjustment signal CTL1 ⁇ i> to the first adjustable current source I1.
  • the enable terminal (RN pin) is connected to the calibration enable signal RST_CALI, and the calibration enable signal RST_CALI is used to clear the output of the number fetching unit 3113 when the initial state is calibrated.
  • the working principle of the first calibration circuit 310 will be described below.
  • the first transistor T1 in the first calibration circuit 310 is an NMOS transistor, so the calibration work of the first calibration circuit 310 can also be referred to as NMOS calibration.
  • the calibration process it is necessary to simulate the normal working state of the off-chip output stage drive circuit, that is, the voltage signal Vout of the signal output terminal of the off-chip output stage is a common-mode voltage signal, so the positive input terminal of the first reference amplifier Aa1 receives the pre-set Assuming the voltage signal VCM, the preset voltage signal VCM is the same as the voltage signal Vout of the signal output terminal of the off-chip output stage, that is, the voltage signal of the signal output terminal of the off-chip output stage remains unchanged at the common mode voltage.
  • the first switch S1 and the third switch S3 are closed, and the PMOS transistor Mm1, the first transistor T1 and the first comparison resistor R1 of the off-chip output stage circuit 400 form a current calibration path, and the current flowing through the output stage (output stage current) flows in the current calibration path, so the current flowing through the first comparison resistor R1 is also the output stage current.
  • Measure the voltage drop on the first comparison resistor R1, and the output stage current flowing through the first comparison resistor R1 can be measured by Ohm’s law, so the voltage on the first comparison resistor R1 can also represent the current flowing through the first comparison resistor R1
  • the magnitude of the output stage current, the voltage on the first comparison resistor R1 is recorded as the first comparison voltage Vc1.
  • the first preset current source If1 is a current source with known current, which flows through the second comparison resistor R2 to form a fixed voltage value, and the voltage on the second comparison resistor R2 is recorded as the second comparison voltage Vc2.
  • the first comparator Ab1 fetches data at the rising edge of the comparator clock signal CLKC received at its clock signal input terminal, performs comparison at the falling edge of the comparator clock signal CLKC, and outputs the comparison result.
  • the working sequence diagram of the first comparator Ab1 is shown in FIG. 8 .
  • the comparison result COMP_OUT of the first comparator Ab1 is 1, it means that the first comparison voltage Vc1 is greater than the second comparison voltage Vc2, that is, the output stage current is too large, then the DC bias voltage provided to the output stage (that is, the first The drive signal Vop) is relatively large, and it is necessary to reduce the DC bias voltage provided by the previous stage to the output stage, that is, to reduce the output current of the first adjustable current source I1.
  • the comparison result COMP_OUT of the first comparator Ab1 is 0, it means that the first comparison voltage Vc1 is smaller than the second comparison voltage Vc2, that is, the DC bias voltage (that is, the first driving signal Vop) provided to the output stage is relatively small, Then it is necessary to increase the output current of the first adjustable current source I1, and then increase the first driving signal Vop.
  • the first adjustable current source I1 is a two-level programmable current source, that is, the output signal of the first adjustable current source I1 can be controlled by binary data. There are n channels of current in the first adjustable current source I1, and when the i-th first adjustment signal CTL1 ⁇ i> is received, the i-th current output is controlled on the basis of the number of previous output current channels. The current regulation process is shown in FIG. 9 , and the variation ⁇ V of each change of the first driving signal Vop decreases in the form of 2 n .
  • the second calibration circuit 320 includes a second reference amplifier Aa2, a second comparator Ab2, a second preset current source If2, a second transistor T2, a third comparison resistor R3, a fourth comparison resistor R4 and a second control Signal generating circuit 321.
  • the negative input terminal of the second reference amplifier Aa2 is used to receive the preset voltage signal VCM, the positive input terminal of the second reference amplifier Aa2 is connected to the drain of the NMOS transistor Mm2 through the fourth switch S4, and the output terminal of the second reference amplifier Aa2 is connected to the first The gate of the second transistor T2; the source of the second transistor T2 is connected to the positive input terminal of the second reference amplifier Aa2; one end of the third comparison resistor R3 is connected to the drain of the second transistor T2 and the first input of the second comparator Ab2 end, the other end is connected to the working power supply Vdd; one end of the fourth comparison resistor R4 is connected to the second preset current source If2 and the second input terminal of the second comparator Ab2, and the other end is connected to the working power supply Vdd; the output of the second comparator Ab2
  • the terminal is connected to the second control signal generating circuit 321, and the second control signal generating circuit 321 is connected to the second adjustable current source I2.
  • the second control signal generation circuit 321 includes a count clock generation circuit, a comparator clock generation circuit and a count unit.
  • the second control signal generating circuit 321 is completely consistent with the first control signal generating circuit 311, and the specific structure and working principle of the second control signal generating circuit 321 can refer to the relevant description of the first control signal generating circuit 311, in This will not be repeated here.
  • the working principle of the second calibration circuit 320 will be described below.
  • the second transistor T2 in the second calibration circuit 320 is a PMOS transistor, so the calibration work of the second calibration circuit 320 can also be referred to as PMOS calibration.
  • the second switch S2 and the fourth switch S4 are closed, and the NMOS transistor Mm2, the second transistor T2 and the third comparison resistor R3 of the off-chip output stage circuit 400 form a current calibration path, and the current flowing through the output stage (output Stage current) flows in the current calibration path, so the current flowing through the third comparison resistor R3 is also the output stage current.
  • the second preset current source If2 is a current source with known current, which flows through the fourth comparison resistor R4 to form a fixed voltage value, and the voltage on the fourth comparison resistor R4 is recorded as the fourth comparison voltage Vc4.
  • the working principle of the second comparator Ab2 is the same as that of the first comparator Ab1, and will not be repeated here.
  • the second adjustable current source I2 is a binary programmable current source, that is, the output signal of the second adjustable current source I2 can be controlled by binary data. If the comparison result of the second comparator Ab2 is 1, it means that the third comparison voltage Vc3 is greater than the fourth comparison voltage Vc4, that is, the output stage current is too large, so the DC bias voltage provided to the output stage (that is, the second drive The signal Von) is relatively large, and it is necessary to reduce the DC bias voltage provided by the previous stage to the output stage, that is, to reduce the output current of the second adjustable current source I2.
  • the comparison result of the second comparator Ab2 is 0, it means that the third comparison voltage Vc3 is smaller than the fourth comparison voltage Vc4, that is, the DC bias voltage (that is, the second driving signal Von) provided to the output stage is relatively small, then It is necessary to increase the output current of the second adjustable current source I2.
  • the off-chip output stage drive circuit provided by the embodiment of the present application is based on an analog circuit and simple control logic, and an adaptive calibration circuit for the optimal DC bias of the off-chip high-power output stage is built, so that the output stage has an extremely high operating Under the premise of high efficiency, it is guaranteed that the output signal still has good linearity.

Abstract

本申请实施例公开了一种片外输出级驱动电路，包括：放大模块，用于接收输入信号，并对输入信号进行放大后输出初级输出信号；驱动模块，用于根据初级输出信号生成驱动信号，驱动信号用于驱动片外输出级电路，并使片外输出级电路产生输出级电流；校准模块，用于将输出级电流转换为比较电压，根据比较电压与参考电压的比较结果输出调节信号，并将调节信号反馈至驱动模块，以使驱动模块根据调节信号调节驱动信号，进而使输出级电流符合预设条件。

Description

片外输出级驱动电路 技术领域
本申请实施例涉及电子电路技术领域，例如涉及一种片外输出级驱动电路。
背景技术
随着科技的飞速发展，电子产品成为了人们的日常必需品之一。在电子产品中，许多应用场合需要输出功率大、驱动能力强的放大器。
目前，放大器大多包括两个部分：片外输出级电路和片内输出级的驱动电路，这样可以使片外输出级电路根据实际情况选择不同的工艺，从而拓展放大器的应用范围。但当所驱动的负载离放大器较远时，需要在片外输出级电路的输出端口和负载之间通过长线来连接。较长的导线将导致更大的寄生电感和寄生电阻。由于流经负载电路的电流通常较大，因此寄生电感和寄生电阻不仅会对电路性能产生严重影响，同时也会造成大量的能量浪费。
发明内容
本申请实施例提供一种片外输出级驱动电路，以提高驱动电路的驱动能力，降低能量浪费。
本申请实施例提供一种片外输出级驱动电路，包括：
放大模块，用于接收输入信号，并对所述输入信号进行放大后输出初级输出信号；
驱动模块，用于根据所述初级输出信号生成驱动信号，所述驱动信号用于驱动片外输出级电路，并使所述片外输出级电路产生输出级电流；
校准模块，用于将所述输出级电流转换为比较电压，根据所述比较电压与 参考电压的比较结果输出调节信号，并将所述调节信号反馈至所述驱动模块，以使所述驱动模块根据所述调节信号调节所述驱动信号，进而使所述输出级电流符合预设条件。
所述放大模块包括：
差分放大电路，用于接收第一输入信号和第二输入信号，并对所述第一输入信号和所述第二输入信号放大处理后形成放大信号；
电平移位电路，用于调节所述放大信号的直流偏置电压，以形成电压不同的第一初级输出信号和第二初级输出信号。
所述驱动模块包括：
第一栅极驱动电路，用于对所述第一初级输出信号进行放大以形成第一驱动信号，所述第一驱动信号用于驱动所述片外输出级电路，以使所述片外输出级电路产生第一输出信号；
第二栅极驱动电路，用于对所述第二初级输出信号进行放大以形成第二驱动信号，所述第二驱动信号用于驱动所述片外输出级电路，以使所述片外输出级电路产生第二输出信号。
所述校准模块包括：
第一校准电路，用于根据所述第一输出信号与第一参考电压的比值输出第一调节信号，并将所述第一调节信号反馈至所述第一栅极驱动电路，以使所述第一栅极驱动电路根据所述第一调节信号调节所述第一驱动信号；
第二校准电路，用于根据所述第二输出信号与第二参考电压的比值输出第二调节信号，并将所述第二调节信号反馈至所述第二栅极驱动电路，以使所述第二栅极驱动电路根据所述第二调节信号调节所述第二驱动信号。
所述第一栅极驱动电路包括第一放大器、第一可调电流源、第一输入电阻 和第一分压电阻；
所述第一放大器的正极输入端用于接收所述第一初级输出信号，所述第一放大器的负极输入端通过所述第一输入电阻接地，所述第一放大器的输出端用于输出所述第一驱动信号；
所述第一分压电阻设于所述第一放大器的负极输入端和所述第一放大器的输出端之间；
所述第一可调电流源的一端连接工作电源，另一端连接所述第一放大器的负极输入端。
所述第二栅极驱动电路包括第二放大器、第二可调电流源、第二输入电阻和第二分压电阻；
所述第二放大器的正极输入端用于接收所述第二初级输出信号，所述第二放大器的负极输入端通过所述第二输入电阻接地，所述第二放大器的输出端用于输出所述第二驱动信号；
所述第二分压电阻设于所述第二放大器的负极输入端和所述第二放大器的输出端之间；
所述第二可调电流源的一端连接工作电源，另一端连接所述第二放大器的负极输入端。
所述片外输出级电路包括PMOS管和NMOS管；所述PMOS管的栅极通过第一开关与所述第一放大器的输出端连接，所述NMOS管的栅极通过第二开关与所述第二放大器的输出端连接；所述PMOS管的源极连接工作电源，所述NMOS管的源极接地；所述PMOS管的漏极与所述NMOS管的漏极连接。
所述第一校准电路包括第一基准放大器、第一比较器、第一预设电流源、第一晶体管、第一比较电阻、第二比较电阻和第一控制信号产生电路；
所述第一基准放大器的负极输入端用于接收预设电压信号，所述第一基准放大器的正极输入端通过第三开关连接所述PMOS管的漏极，所述第一基准放大器的输出端连接所述第一晶体管的栅极；
所述第一晶体管的漏极连接所述第一基准放大器的正极输入端；
所述第一比较电阻的一端连接所述第一晶体管的源极和所述第一比较器的第一输入端，另一端接地；
所述第二比较电阻的一端连接所述第一预设电流源和所述第一比较器的第二输入端，另一端接地；
所述第一比较器的输出端与所述第一控制信号产生电路连接，所述第一控制信号产生电路与所述第一可调电流源连接。
所述第二校准电路包括第二基准放大器、第二比较器、第二预设电流源、第二晶体管、第三比较电阻、第四比较电阻和第二控制信号产生电路；
所述第二基准放大器的负极输入端用于接收预设电压信号，所述第二基准放大器的正极输入端通过第四开关连接所述NMOS管的漏极，所述第二基准放大器的输出端连接所述第二晶体管的栅极；
所述第二晶体管的源极连接所述第二基准放大器的正极输入端；
所述第三比较电阻的一端连接所述第二晶体管的漏极和所述第二比较器的第一输入端，另一端连接工作电源；
所述第四比较电阻的一端连接所述第二预设电流源和所述第二比较器的第二输入端，另一端连接工作电源；
所述第二比较器的输出端与所述第二控制信号产生电路连接，所述第二控制信号产生电路与所述第二可调电流源连接。
所述第一控制信号产生电路包括取数时钟产生电路、比较器时钟产生电路 和取数单元；
所述取数时钟产生电路包括反向器和多个D触发器，所有D触发器的时钟信号端均连接预设时钟信号，第i个D触发器的数据输入端和第i-1个D触发器的数据输出端连接，其中，i≤n；所述反向器的输入端连接最后一个D触发器的数据输出端，所述反向器的输出端连接所有D触发器的使能端；
所述比较器时钟产生电路包括缓冲器和或门逻辑电路，所述缓冲器的输入端连接所述D触发器的数据输出端，所述缓冲器的输出端连接所述或门逻辑电路的一个输入端，所述或门逻辑电路的另一个输入端连接所述预设时钟信号，所述或门逻辑电路的输出端连接所述第一比较器的时钟信号端；
所述取数单元包括时钟端、信号输入端和信号输出端，所述时钟端连接所述D触发器的数据输出端，所述信号输入端连接所述第一比较器的输出端，所述信号输出端连接所述第一可调电流源。
本申请实施例提供的片外输出级驱动电路通过在片外输出级驱动电路中引入校准电路，使电路整体形成了反馈调节，能够随时调节片外输出级电路中的电流，即使得输出级电流能够自适应校准，提高了驱动电路的驱动能力，降低了能量浪费。
附图说明
图1为本申请实施例一提供的一种片外输出级驱动电路的示意图；
图2为本申请实施例二提供的一种片外输出级驱动电路的示意图；
图3为本申请实施例二提供的放大模块的结构示意图；
图4为本申请实施例二提供的第一控制信号产生电路的结构示意图；
图5为本申请实施例二提供的取数时钟产生电路的结构示意图；
图6为本申请实施例二提供的比较器时钟产生电路的结构示意图；
图7为本申请实施例二提供的取数单元的结构示意图；
图8为本申请实施例二提供的比较器的工作时序图；
图9为本申请实施例二提供的校准过程的电流变化示意图。
具体实施方式
下面结合附图和实施例对本申请作说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
一些示例性实施例被描述成作为流程图描绘的处理或电路。虽然流程图将各步骤描述成顺序的处理，但是其中的许多步骤可以被并行地、并发地或者同时实施。此外，各步骤的顺序可以被重新安排。当其操作完成时处理可以被终止，但是还可以具有未包括在附图中的附加步骤。处理可以对应于电路、函数、规程、子例程、子程序等等。
此外，术语“第一”、“第二”等可在本文中用于描述各种方向、动作、步骤或元件等，但这些方向、动作、步骤或元件不受这些术语限制。这些术语仅用于将第一个方向、动作、步骤或元件与另一个方向、动作、步骤或元件区分。术语“第一”、“第二”等而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”、“批量”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
实施例一
图1为本申请实施例提供的一种片外输出级驱动电路的示意图。如图1所示，本申请实施例提供的片外输出级驱动电路包括：放大模块100、驱动模块200和校准模块300，放大模块100与驱动模块200连接，驱动模块200连接片外输出级电路400，校准模块300连接于片外输出级电路400和驱动模块200之间，形成反馈调节。一般的，片外输出级电路简称片外输出级或输出级，后续不再赘述。
放大模块100接收输入信号(如输入电压信号)，并对输入信号进行放大后输出初级输出信号。驱动模块200以放大模块100的初级输出信号作为输入，根据初级输出信号生成驱动信号。驱动信号输入至片外输出级电路400中，驱动片外输出级电路400产生输出信号。片外输出级电路400产生的输出信号包括输出电压以及输出级电流，该输出电压用于向片外输出级电路400所接负载供电，输出级电流即为流经片外输出级电路400的电流。一般的，片外输出级电路400产生的直流输出电压为共模电压信号。
在片外输出级电路400的工作过程中，存在某些情况，片外输出级会流过一个较大的电流，为了防止大电流造成能量浪费，本申请实施例引入校准模块300。校准模块300检测片外输出级电路400产生的输出级电流，将该输出级电流转换为比较电压，并将该比较电压与已知的参考电压进行比较，输出调节信号。该调节信号反馈至驱动模块200，可以改变驱动信号的大小，驱动信号的改变则影响片外输出级电路400的输出级电流大小。例如，当片外输出级电路400产生的输出级电流过大，则输出级电流转换的比较电压将大于参考电压，此时反馈至驱动模块200的调节信号为减小驱动信号；当驱动信号减小，输出级电 流则减小，达到调节输出级电流的目的。参考电压表示输出级电流的调节目标，当对应的比较电压与参考电压一致时，则说明输出级电流符合预设条件。
本申请实施例提供的片外输出级驱动电路通过在片外输出级驱动电路中引入校准电路，使电路整体形成了反馈调节，能够随时调节片外输出级电路中的电流，即使得输出级电流能够自适应校准，提高了驱动电路的驱动能力，降低了能量浪费。
实施例二
图2为本申请实施例二提供的一种片外输出级驱动电路的结构示意图，本实施例是对上述实施的细化。如图2所示，本申请实施例二提供的片外输出级驱动电路包括：放大模块100、驱动模块200和校准模块300，放大模块100与驱动模块200连接，驱动模块200连接片外输出级电路400，校准模块300连接于片外输出级电路400和驱动模块200之间，形成反馈调节。
放大模块100的具体电路结构如图3所示。放大模块100包括差分放大电路110和电平移位电路120。差分放大电路110采用了折叠式差分输入级结构，这样可以得到较大的输入电压范围。差分放大电路110包括NMOS管M1、NMOS管M2、NMOS管M3、NMOS管M4、NMOS管M5、NMOS管M6、NMOS管M7、NMOS管M8、PMOS管M9、PMOS管M10、PMOS管M11、PMOS管M12、PMOS管M13、电容C1和电容C2。NMOS管M1的栅极用于接收第一输入信号Vin+，NMOS管M2的栅极用于接收第二输入信号Vin-。NMOS管M1的源极和NMOS管M2的源极连接后与NMOS管M4的漏极连接。NMOS管M4的源极与NMOS管M3的漏极连接。PMOS管M9的漏极与PMOS管M11的源极连接且与NMOS管M1的漏极连接，PMOS管M11的漏极与PMOS管 M13的源极连接，PMOS管M13的漏极与NMOS管M7的漏极连接，NMOS管M7的源极与NMOS管M5的漏极连接。PMOS管M10的漏极与PMOS管M12的源极连接且与NMOS管M2的漏极连接，NMOS管M8的源极与NMOS管M6的漏极连接。PMOS管M9的源极与PMOS管M10的源极共同连接工作电源正极；NMOS管M3的源极、NMOS管M5的源极和NMOS管M5的源极共同连接工作电源负极。NMOS管M4的栅极接工作电压Vb2，NMOS管M3的栅极接工作电压Vb1，NMOS管M5的栅极与NMOS管M6的栅极连接且与NMOS管M7的漏极连接，NMOS管M7的栅极和NMOS管M8的栅极接工作电压Vb3，PMOS管M9的栅极和PMOS管M10的栅极接工作电压Vb4，PMOS管M11的栅极和PMOS管M12的栅极接工作电压Vb5，PMOS管M13的栅极接工作电压Vb6。PMOS管M12的漏极和NMOS管M8的漏极之间串联电容C1和电容C2。电容C1和电容C2的公共端输出放大信号V0，该放大信号V0即为差分放大电路110对第一输入信号Vin+和第二输入信号Vin-进行放大后所输出的信号。
电平移位电路120的作用是改变差分放大电路110输出信号(即放大信号V0)的直流偏置电压，使其分离为第一初级输出信号Vo1和第二初级输出信号Vo2，第一初级输出信号Vo1和第二初级输出信号Vo2为两个不同的电压，一个是高电平信号，一个是低电平信号。电平移位电路120包括PMOS管Mp1、PMOS管Mp2、NMOS管Mn1和NMOS管Mn2。PMOS管Mp1的漏极与PMOS管Mp2的源极连接，NMOS管Mn1的源极与NMOS管Mn2的漏极连接。PMOS管Mp1的源极与NMOS管Mn1的漏极连接且与PMOS管M12的漏极连接，NMOS管Mn2的源极与PMOS管Mp2的漏极连接且与NMOS管M8的漏极连接。PMOS管Mp1的栅极连接工作电压Vbp2，PMOS管Mp2的栅极连接工作 电压Vbp2，NMOS管Mn1的栅极连接工作电压Vbn1，NMOS管Mn2的栅极连接工作电压Vbn2。PMOS管Mp1和NMOS管Mn1的公共端输出第一初级输出信号Vo1，NMOS管Mn2和PMOS管Mp2的公共端输出第二初级输出信号Vo2。
如图2所示，驱动模块200包括第一栅极驱动电路210和第二栅极驱动电路220。第一栅极驱动电路210接收第一初级输出信号Vo1，对第一初级输出信号Vo1进行放大处理，输出第一驱动信号Vop。第二栅极驱动电路220接收第二初级输出信号Vo2，对第二初级输出信号Vo2进行放大处理，输出第二驱动信号Von。
如图2所示，第一栅极驱动电路210包括第一放大器A1、第一可调电流源I1、第一输入电阻Rr1和第一分压电阻Rf1。第一放大器A1的正极输入端连接PMOS管Mp1和NMOS管Mn1的公共端，以接收第一初级输出信号Vo1。第一放大器A1的负极输入端通过第一输入电阻Rr1接地，第一放大器A1的输出端用于输出第一驱动信号Vop；第一分压电阻Rf1设于第一放大器A1的负极输入端和第一放大器A1的输出端之间；第一可调电流源I1的一端连接工作电源Vdd，另一端连接第一放大器A1的负极输入端。
如图2所示，第二栅极驱动电路220包括第二放大器A2、第二可调电流源I2、第二输入电阻Rr2和第二分压电阻Rf2。第二放大器A2的正极输入端连接PMOS管Mp2和NMOS管Mn2的公共端，以接收第二初级输出信号Vo2。第二放大器A2的负极输入端通过第二输入电阻Rr2连接工作电源Vdd，第二放大器A2的输出端用于输出第二驱动信号Von；第二分压电阻Rf2设于第二放大器A2的负极输入端和第二放大器A2的输出端之间；第二可调电流源I2的一端连接工作电源Vdd，另一端连接第二放大器A2的负极输入端。
本实施例中，第一栅极驱动电路210输出的第一驱动信号Vop和第二栅极驱动电路220输出的第二驱动信号Von即为片外输出级电路400的驱动信号。本实施例中，为了达到更加高效的输出，片外输出级电路400采用甲乙类输出级结构，由一个分立的PMOS管Mm1和一个分立的NMOS管Mm2组成，如图2所示。PMOS管Mm1的源极连接工作电源Vdd，PMOS管Mm1的漏极与NMOS管Mm2的漏极连接，NMOS管Mm2的源极接地。PMOS管Mm1的栅极通过第一开关S1连接第一放大器A1的输出端，以接收第一驱动信号Vop；NMOS管Mm2的栅极通过第二开关S2连接第二放大器A2的输出端，以接收第二驱动信号Von。其中，PMOS管Mm1的漏极与NMOS管Mm2的漏极所形成的公共端为片外输出级电路400的信号输出端，该信号输出端用于输出片外输出级电路400后续所接负载电路所需的电压信号Vout。可选的，片外输出级电路400也可以是其他结构，通过具体的应用场景来选择合适的晶体管即可。
输出级直流偏置大小是影响整体电路性能和功耗的关键参数。如果直流偏置较大，则在输入信号很小的情况下浪费了很多功耗。如果直流偏置较小，则会影响电路的线性度。为了实现输出级直流偏置的最优化，也即输出级电流最小化，本实施例在片外输出级驱动电路中加入校准模块300，对应于本实施例中的甲乙类输出级结构，校准模块300包括第一校准电路310和第二校准电路320。
如图2所示，第一校准电路310包括第一基准放大器Aa1、第一比较器Ab1、第一预设电流源If1、第一晶体管T1、第一比较电阻R1、第二比较电阻R2和第一控制信号产生电路311。第一基准放大器Aa1的负极输入端用于接收预设电压信号VCM，第一基准放大器Aa1的正极输入端通过第三开关S3连接PMOS管Mm1的漏极，第一基准放大器Aa1的输出端连接第一晶体管T1的栅极；第一晶体管T1的漏极连接第一基准放大器Aa1的正极输入端；第一比较电阻R1的 一端连接第一晶体管T1的源极和第一比较器Ab1的第一输入端，另一端接地；第二比较电阻R2的一端连接第一预设电流源If1和第一比较器Ab1的第二输入端，另一端接地；第一比较器Ab1的输出端与第一控制信号产生电路311连接，第一控制信号产生电路311与第一可调电流源I1连接。
如图4所示，第一控制信号产生电路311包括取数时钟产生电路3111、比较器时钟产生电路3112和取数单元3113。第一控制信号产生电路311根据第一比较器Ab1输出端的信号产生第一调节信号CTL1<i>，并将该第一调节信号CTL1<i>反馈至第一可调电流源I1，使第一可调电流源I1的输出电流发生改变，进而改变第一驱动信号Vop。可见，第一校准电路310用于对第一驱动信号Vop进行校准。
如图5所示，取数时钟产生电路3111包括反向器和多个D触发器，所有D触发器的时钟信号端均连接预设时钟信号，第i个D触发器的数据输入端和第i-1个D触发器的数据输出端连接，其中，i≤n；反向器的输入端连接最后一个D触发器的数据输出端，反向器的输出端连接所有D触发器的使能端。如图5所示，本实施例中，取数时钟产生电路3111包括一个反向器和10个D触发器(记为DFF<1>～DFF<10>)。所有D触发器的时钟信号端(CK引脚)均连接预设时钟信号CLK_IN。第一个D触发器DFF<1>的数据输入端(D引脚)连接工作电源Vdd，此后，前一个D触发器的数据输出端(Q引脚)与后一个D触发器的数据输入端(D引脚)连接。最后一个D触发器DFF<10>的数据输出端(Q引脚)连接反向器的输入端。反向器的输出端与所有D触发器的使能端(RN引脚)连接。将第i个D触发器的输出信号记为SHFT<i>。
如图6所示，比较器时钟产生电路3112包括缓冲器F和或门逻辑电路，缓冲器的输入端连接D触发器的数据输出端(Q引脚)，用以接收最后一个D触 发器的输出信号SHFT<10>。缓冲器的输出端连接或门逻辑电路的一个输入端；或门逻辑电路的另一个输入端连接预设时钟信号CLK_IN，或门逻辑电路的输出端连接第一比较器Ab1的时钟信号端(其中，第一比较器Ab1的时钟信号端在图中未示出)，用以输出比较器时钟信号CLKC。
取数单元3113也由D触发器构成。如图7所示，取数单元3113包括时钟端(CK引脚)、信号输入端(D引脚)、信号输出端(Q引脚)和使能端(RN引脚)。时钟端(CK引脚)连接取数时钟产生电路3111中的D触发器的数据输出端，也即，取数单元3113的时钟信号为D触发器的输出信号SHFT<i>，第i个输出信号SHFT<i>表示第i个取数周期。信号输入端(D引脚)连接第一比较器Ab1的输出端，用以接收第一比较器Ab1输出的比较结果COMP_OUT。信号输出端(Q引脚)连接第一可调电流源I1，用以向第一可调电流源I1反馈第一调节信号CTL1<i>。使能端(RN引脚)连接校准使能信号RST_CALI，该校准使能信号RST_CALI用于在校准初始状态时，将取数单元3113的输出清零。
下面说明第一校准电路310的工作原理。
本实施例中，第一校准电路310中的第一晶体管T1为NMOS管，故而第一校准电路310的校准工作也可称为NMOS校准。在校准过程中，需要模拟出片外输出级驱动电路的正常工作状态，即片外输出级的信号输出端的电压信号Vout为共模电压信号，故而将第一基准放大器Aa1的正极输入端接收预设电压信号VCM，该预设电压信号VCM与片外输出级的信号输出端的电压信号Vout相同，也即使片外输出级信号输出端的电压信号保持共模电压不变。
校准时，将第一开关S1和第三开关S3闭合，片外输出级电路400的PMOS管Mm1、第一晶体管T1和第一比较电阻R1构成一电流校准通路，流经输出级的电流(输出级电流)在该电流校准通路中流通，故而流经第一比较电阻R1的 电流也为输出级电流。测量第一比较电阻R1上的压降，通过欧姆定律即可测得流经第一比较电阻R1的输出级电流，故而第一比较电阻R1上的电压大小也可以表示流经第一比较电阻R1的输出级电流大小，将第一比较电阻R1上的电压记为第一比较电压Vc1。同时，第一预设电流源If1为一已知电流的电流源，其流经第二比较电阻R2形成一固定电压值，将第二比较电阻R2上的电压记为第二比较电压Vc2。将第一比较电压Vc1和第二比较电压Vc2输入第一比较器Ab1进行比较，即可得出输出级电流与第一预设电流源If1的大小关系。
第一比较器Ab1在其时钟信号输入端接收的比较器时钟信号CLKC上升沿进行取数，在比较器时钟信号CLKC下降沿进行比较并输出比较结果。第一比较器Ab1的工作时序图如图8所示。
如果第一比较器Ab1的比较结果COMP_OUT为1，则说明第一比较电压Vc1大于第二比较电压Vc2，也即输出级电流过大，那么提供给输出级的直流偏置电压(也即第一驱动信号Vop)较大，需要减小前级提供给输出级的直流偏置电压，也即减小第一可调电流源I1的输出电流。如果第一比较器Ab1的比较结果COMP_OUT为0，则说明第一比较电压Vc1小于第二比较电压Vc2，也即提供给输出级的直流偏置电压(也即第一驱动信号Vop)较小，那么需要增大第一可调电流源I1的输出电流，进而增大第一驱动信号Vop。本实施例中，第一可调电流源I1为二级制可编程电流源，即可通过二进制数据控制第一可调电流源I1的输出信号。第一可调电流源I1中有n路电流，当接收到第i个第一调节信号CTL1<i>时，在之前输出电流路数的基础上再控制第i路电流输出。电流调节过程如图9所示，第一驱动信号Vop每次改变的变化量ΔV按照2 n形式递减。
参考图2，第二校准电路320包括第二基准放大器Aa2、第二比较器Ab2、 第二预设电流源If2、第二晶体管T2、第三比较电阻R3、第四比较电阻R4和第二控制信号产生电路321。第二基准放大器Aa2的负极输入端用于接收预设电压信号VCM，第二基准放大器Aa2的正极输入端通过第四开关S4连接NMOS管Mm2的漏极，第二基准放大器Aa2的输出端连接第二晶体管T2的栅极；第二晶体管T2的源极连接第二基准放大器Aa2的正极输入端；第三比较电阻R3的一端连接第二晶体管T2的漏极和第二比较器Ab2的第一输入端，另一端连接工作电源Vdd；第四比较电阻R4的一端连接第二预设电流源If2和第二比较器Ab2的第二输入端，另一端连接工作电源Vdd；第二比较器Ab2的输出端与第二控制信号产生电路321连接，第二控制信号产生电路321与第二可调电流源I2连接。
第二控制信号产生电路321包括取数时钟产生电路、比较器时钟产生电路和取数单元。本实施例中，第二控制信号产生电路321与第一控制信号产生电路311完全一致，第二控制信号产生电路321的具体结构和工作原理可以参考第一控制信号产生电路311的相关描述，在此不再赘述。
下面说明第二校准电路320的工作原理。
本实施例中，第二校准电路320中的第二晶体管T2为PMOS管，故而第二校准电路320的校准工作也可称为PMOS校准。校准时，将第二开关S2和第四开关S4闭合，片外输出级电路400的NMOS管Mm2、第二晶体管T2和第三比较电阻R3构成一电流校准通路，流经输出级的电流(输出级电流)在该电流校准通路中流通，故而流经第三比较电阻R3的电流也为输出级电流。测量第三比较电阻R3上的压降，通过欧姆定律即可测得流经第三比较电阻R3的输出级电流，故而第三比较电阻R3上的电压大小也可以表示流经第三比较电阻R3的输出级电流大小，将第三比较电阻R3上的电压记为第三比较电压Vc3。同时， 第二预设电流源If2为一已知电流的电流源，其流经第四比较电阻R4形成一固定电压值，将第四比较电阻R4上的电压记为第四比较电压Vc4。将第三比较电压Vc3和第四比较电压Vc4输入第二比较器Ab2进行比较，即可得出输出级电流与第二预设电流源If2的大小关系。
第二比较器Ab2的工作原理与第一比较器Ab1相同，在此不再赘述。
本实施例中，第二可调电流源I2为二级制可编程电流源，即可通过二进制数据控制第二可调电流源I2的输出信号。如果第二比较器Ab2的比较结果为1，则说明第三比较电压Vc3大于第四比较电压Vc4，也即输出级电流过大，那么提供给输出级的直流偏置电压(也即第二驱动信号Von)较大，需要减小前级提供给输出级的直流偏置电压，也即减小第二可调电流源I2的输出电流。如果第二比较器Ab2的比较结果为0，则说明第三比较电压Vc3小于第四比较电压Vc4，也即提供给输出级的直流偏置电压(也即第二驱动信号Von)较小，那么需要增大第二可调电流源I2的输出电流。
本申请实施例提供的片外输出级驱动电路基于模拟电路和简单的控制逻辑，搭建了一个片外大功率输出级最佳直流偏置的自适应校准电路，使得输出级在具有极高的工作效率前提下，保证输出信号仍具有良好的线性度。

Claims (10)

  1. 一种片外输出级驱动电路，包括：
    放大模块，用于接收输入信号，并对所述输入信号进行放大后输出初级输出信号；
    驱动模块，用于根据所述初级输出信号生成驱动信号，所述驱动信号用于驱动片外输出级电路，并使所述片外输出级电路产生输出级电流；
    校准模块，用于将所述输出级电流转换为比较电压，根据所述比较电压与参考电压的比较结果输出调节信号，并将所述调节信号反馈至所述驱动模块，以使所述驱动模块根据所述调节信号调节所述驱动信号，进而使所述输出级电流符合预设条件。
  2. 如权利要求1所述的片外输出级驱动电路，其中，所述放大模块包括：
    差分放大电路，用于接收第一输入信号和第二输入信号，并对所述第一输入信号和所述第二输入信号放大处理后形成放大信号；
    电平移位电路，用于调节所述放大信号的直流偏置电压，以形成电压不同的第一初级输出信号和第二初级输出信号。
  3. 如权利要求2所述的片外输出级驱动电路，其中，所述驱动模块包括：
    第一栅极驱动电路，用于对所述第一初级输出信号进行放大以形成第一驱动信号，所述第一驱动信号用于驱动所述片外输出级电路，以使所述片外输出级电路产生第一输出信号；
    第二栅极驱动电路，用于对所述第二初级输出信号进行放大以形成第二驱动信号，所述第二驱动信号用于驱动所述片外输出级电路，以使所述片外输出级电路产生第二输出信号。
  4. 如权利要求3所述的片外输出级驱动电路，其中，所述校准模块包括：
    第一校准电路，用于根据所述第一输出信号与第一参考电压的比值输出第 一调节信号，并将所述第一调节信号反馈至所述第一栅极驱动电路，以使所述第一栅极驱动电路根据所述第一调节信号调节所述第一驱动信号；
    第二校准电路，用于根据所述第二输出信号与第二参考电压的比值输出第二调节信号，并将所述第二调节信号反馈至所述第二栅极驱动电路，以使所述第二栅极驱动电路根据所述第二调节信号调节所述第二驱动信号。
  5. 如权利要求4所述的片外输出级驱动电路，其中，所述第一栅极驱动电路包括第一放大器、第一可调电流源、第一输入电阻和第一分压电阻；
    所述第一放大器的正极输入端用于接收所述第一初级输出信号，所述第一放大器的负极输入端通过所述第一输入电阻接地，所述第一放大器的输出端用于输出所述第一驱动信号；
    所述第一分压电阻设于所述第一放大器的负极输入端和所述第一放大器的输出端之间；
    所述第一可调电流源的一端连接工作电源，另一端连接所述第一放大器的负极输入端。
  6. 如权利要求5所述的片外输出级驱动电路，其中，所述第二栅极驱动电路包括第二放大器、第二可调电流源、第二输入电阻和第二分压电阻；
    所述第二放大器的正极输入端用于接收所述第二初级输出信号，所述第二放大器的负极输入端通过所述第二输入电阻接地，所述第二放大器的输出端用于输出所述第二驱动信号；
    所述第二分压电阻设于所述第二放大器的负极输入端和所述第二放大器的输出端之间；
    所述第二可调电流源的一端连接工作电源，另一端连接所述第二放大器的负极输入端。
  7. 如权利要求6所述的片外输出级驱动电路，其中，所述片外输出级电路包括PMOS管和NMOS管；所述PMOS管的栅极通过第一开关与所述第一放大器的输出端连接，所述NMOS管的栅极通过第二开关与所述第二放大器的输出端连接；所述PMOS管的源极连接工作电源，所述NMOS管的源极接地；所述PMOS管的漏极与所述NMOS管的漏极连接。
  8. 如权利要求7所述的片外输出级驱动电路，其中，所述第一校准电路包括第一基准放大器、第一比较器、第一预设电流源、第一晶体管、第一比较电阻、第二比较电阻和第一控制信号产生电路；
    所述第一基准放大器的负极输入端用于接收预设电压信号，所述第一基准放大器的正极输入端通过第三开关连接所述PMOS管的漏极，所述第一基准放大器的输出端连接所述第一晶体管的栅极；
    所述第一晶体管的漏极连接所述第一基准放大器的正极输入端；
    所述第一比较电阻的一端连接所述第一晶体管的源极和所述第一比较器的第一输入端，另一端接地；
    所述第二比较电阻的一端连接所述第一预设电流源和所述第一比较器的第二输入端，另一端接地；
    所述第一比较器的输出端与所述第一控制信号产生电路连接，所述第一控制信号产生电路与所述第一可调电流源连接。
  9. 如权利要求7所述的片外输出级驱动电路，其中，所述第二校准电路包括第二基准放大器、第二比较器、第二预设电流源、第二晶体管、第三比较电阻、第四比较电阻和第二控制信号产生电路；
    所述第二基准放大器的负极输入端用于接收预设电压信号，所述第二基准放大器的正极输入端通过第四开关连接所述PMOS管的漏极，所述第二基准放 大器的输出端连接所述第二晶体管的栅极；
    所述第二晶体管的源极连接所述第二基准放大器的正极输入端；
    所述第三比较电阻的一端连接所述第二晶体管的漏极和所述第二比较器的第一输入端，另一端连接工作电源；
    所述第四比较电阻的一端连接所述第二预设电流源和所述第二比较器的第二输入端，另一端连接工作电源；
    所述第二比较器的输出端与所述第二控制信号产生电路连接，所述第二控制信号产生电路与所述第二可调电流源连接。
  10. 如权利要求8所述的片外输出级驱动电路，其中，所述第一控制信号产生电路包括取数时钟产生电路、比较器时钟产生电路和取数单元；
    所述取数时钟产生电路包括反向器和多个D触发器，所有D触发器的时钟信号端均连接预设时钟信号，第i个D触发器的数据输入端和第i-1个D触发器的数据输出端连接，其中，i≤n；所述反向器的输入端连接最后一个D触发器的数据输出端，所述反向器的输出端连接所有D触发器的使能端；
    所述比较器时钟产生电路包括缓冲器和或门逻辑电路，所述缓冲器的输入端连接所述D触发器的数据输出端，所述缓冲器的输出端连接所述或门逻辑电路的一个输入端，所述或门逻辑电路的另一个输入端连接所述预设时钟信号，所述或门逻辑电路的输出端连接所述第一比较器的时钟信号端；
    所述取数单元包括时钟端、信号输入端和信号输出端，所述时钟端连接所述D触发器的数据输出端，所述信号输入端连接所述第一比较器的输出端，所述信号输出端连接所述第一可调电流源。
PCT/CN2022/078574 2022-03-01 2022-03-01 片外输出级驱动电路 WO2023164795A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387315A (zh) * 2001-05-18 2002-12-25 阿尔卡塔尔公司 包括静态电流控制电路的运算放大器装置
US20030155945A1 (en) * 2002-02-21 2003-08-21 Broadcom Corporation Methods and systems for providing load-adaptive output current drive
CN109729295A (zh) * 2018-12-19 2019-05-07 芯原微电子(上海)有限公司 发送端驱动电路及方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387315A (zh) * 2001-05-18 2002-12-25 阿尔卡塔尔公司 包括静态电流控制电路的运算放大器装置
US20030155945A1 (en) * 2002-02-21 2003-08-21 Broadcom Corporation Methods and systems for providing load-adaptive output current drive
CN109729295A (zh) * 2018-12-19 2019-05-07 芯原微电子(上海)有限公司 发送端驱动电路及方法

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