WO2023161754A1 - 半導体装置、記憶装置、及び電子機器 - Google Patents

半導体装置、記憶装置、及び電子機器 Download PDF

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Publication number
WO2023161754A1
WO2023161754A1 PCT/IB2023/051188 IB2023051188W WO2023161754A1 WO 2023161754 A1 WO2023161754 A1 WO 2023161754A1 IB 2023051188 W IB2023051188 W IB 2023051188W WO 2023161754 A1 WO2023161754 A1 WO 2023161754A1
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Prior art keywords
insulator
conductor
oxide
transistor
semiconductor device
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PCT/IB2023/051188
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English (en)
French (fr)
Japanese (ja)
Inventor
木村肇
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202380021311.3A priority Critical patent/CN118696617A/zh
Priority to JP2024502576A priority patent/JPWO2023161754A1/ja
Priority to US18/838,504 priority patent/US20250159869A1/en
Priority to KR1020247026531A priority patent/KR20240155858A/ko
Publication of WO2023161754A1 publication Critical patent/WO2023161754A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Definitions

  • One embodiment of the present invention relates to semiconductor devices, memory devices, and electronic devices.
  • one aspect of the present invention is not limited to the above technical field.
  • TECHNICAL FIELD The technical field of the inventions disclosed in this specification and the like relates to products, methods of operation, or methods of manufacture. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, the technical fields of one embodiment of the present invention disclosed in this specification more specifically include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, and sensors. , processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a large memory capacity. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high storage density. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Alternatively, an object of one embodiment of the present invention is to provide a memory device including the above semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide an electronic device including the memory device. Alternatively, an object of one embodiment of the present invention is to provide a novel storage device or a novel electronic device.
  • the problem of one embodiment of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Still other issues are issues not mentioned in this section, which will be described in the following description.
  • Problems not mentioned in this section can be derived from the descriptions in the specification, drawings, or the like by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention is to solve at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.
  • One embodiment of the present invention is a semiconductor device including a first memory layer and a second memory layer.
  • a second memory layer is located on the first memory layer.
  • each of the first memory layer and the second memory layer includes a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and a sixth insulator.
  • the oxide contains one or more selected from indium, zinc, and the element M.
  • Element M includes gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.
  • the second insulator is located on the first insulator, and the oxide is located on the second insulator.
  • the first conductor is positioned over the first insulator, the second insulator, and the oxide
  • the second conductor is positioned over the first insulator and the second insulator.
  • the third insulator is positioned on the first conductor, the second conductor, and the first insulator
  • the fourth insulator is positioned on the third insulator.
  • the fourth insulator has a first opening reaching the oxide in a region that does not overlap the first conductor, the second conductor and the third insulator.
  • a fifth insulator is located on the oxide and on the side of the fourth insulator in the first opening, and a third conductor is located on the fifth insulator. Also, the fourth insulator has a second opening reaching the second conductor in a region where the second insulator and the oxide do not overlap.
  • a sixth insulator is positioned on the second conductor and on the side surface of the fourth insulator in the second opening, and the fourth conductor is positioned on the sixth insulator.
  • the fourth conductor of the first memory layer overlaps the second insulator of the second memory layer and the oxide of the second memory layer.
  • the fifth insulator and the sixth insulator each include the same insulating material, and the third conductor and the fourth conductor
  • Each of the bodies may be constructed of the same electrically conductive material as each other.
  • one embodiment of the present invention is a semiconductor device that includes a first memory layer and a second memory layer and has a structure different from that of (1) above.
  • the second memory layer is located on the first memory layer.
  • each of the first memory layer and the second memory layer includes a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and a sixth insulator.
  • the oxide contains one or more selected from indium, zinc, and the element M.
  • Element M includes gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.
  • the second insulator is located on the first insulator, and the oxide is located on the second insulator.
  • a first conductor overlies the oxide and a second conductor overlies the oxide.
  • the third insulator is positioned on the first conductor, the second conductor, and the first insulator, and the fourth insulator is positioned on the third insulator.
  • the fourth insulator has a first opening reaching the oxide in a region that does not overlap the first conductor, the second conductor, and the third insulator.
  • a fifth insulator is located on the oxide and on the side of the fourth insulator in the first opening, and a third conductor is located on the fifth insulator.
  • the fourth insulator has a second opening reaching the second conductor in a region overlapping the second insulator and the oxide.
  • a sixth insulator is positioned on the second conductor and on the side surface of the fourth insulator in the second opening, and the fourth conductor is positioned on the sixth insulator.
  • the fourth conductor of the first memory layer overlaps the second insulator of the second memory layer and the oxide of the second memory layer.
  • the fifth insulator and the sixth insulator each include the same insulating material, and the third conductor and the fourth conductor
  • Each of the bodies may be constructed of the same electrically conductive material as each other.
  • one embodiment of the present invention is a memory device including the semiconductor device described in any one of (1) to (4) above and a driver circuit.
  • one embodiment of the present invention is an electronic device including the storage device of (5) and a housing.
  • a semiconductor device with large memory capacity can be provided.
  • a semiconductor device with high storage density can be provided.
  • a novel semiconductor device or the like can be provided.
  • a memory device including the above semiconductor device can be provided.
  • an electronic device including the above memory device can be provided.
  • a new storage device or a new electronic device can be provided.
  • FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 3 is a schematic perspective view showing a configuration example of a semiconductor device.
  • FIG. 4 is a schematic cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 5 is a layout diagram showing a configuration example of a semiconductor device.
  • FIG. 6A is a schematic plan view showing a configuration example of a semiconductor device, and FIGS. 6B to 6D are schematic cross-sectional views showing configuration examples of the semiconductor device.
  • FIG. 7A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIGS. 7B to 7D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 8A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 8B to 8D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 9A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 9B to 9D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 10A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 10B to 10D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIGS. 11A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 11B to 11D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 12A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 12B to 12D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 13A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 13B to 13D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 14A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIGS. 14B to 14D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 15A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 15B to 15D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 16A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 16B to 16D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 17A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 17B to 17D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIGS. 18A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 18B to 18D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 19A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 19B to 19D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 20A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 20B to 20D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 21A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 21A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 21A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 21A is a schematic plan view showing
  • FIGS. 25A and 25A are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIGS. 25B to 25D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 26B to 26D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 27A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 27B to 27D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 28A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 28B to 28D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 29A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 29B to 29D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 30A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 30B to 30D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 31A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 31B to 31D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 32A is a schematic perspective view illustrating a configuration example of a memory device
  • FIG. 32B is a block diagram illustrating a configuration example of a semiconductor device.
  • FIG. 33 is a block diagram illustrating a configuration example of a storage device;
  • FIG. 33 is a block diagram illustrating a configuration example of a storage device
  • FIG. 34 is a schematic cross-sectional view illustrating a configuration example of a storage device.
  • 35A is a schematic perspective view showing an example of a semiconductor wafer
  • FIG. 35B is a schematic perspective view showing an example of a chip
  • FIGS. 35C and 35D are schematic perspective views showing an example of an electronic component.
  • FIG. 36 is a block diagram explaining a CPU.
  • 37A to 37J are perspective views illustrating examples of electronic devices.
  • 38A, 38B, and 38D are perspective views showing configuration examples of electronic equipment
  • FIG. 38C is a diagram showing an example of part of the electronic equipment.
  • 39A to 39E are schematic perspective views illustrating an example of electronic equipment.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit that includes semiconductor elements (eg, transistors, diodes, and photodiodes), and a device that has the same circuit.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • an integrated circuit, a chip including the integrated circuit, and an electronic component containing the chip in a package are examples of semiconductor devices.
  • storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves may be semiconductor devices or may include semiconductor devices.
  • connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.
  • X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display devices, light emitting devices, and loads) can be connected between X and Y one or more times.
  • the switch has a function of being controlled to be turned on and off. In other words, the switch has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to allow current to flow.
  • both an element and a power supply line for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring that gives a desired potential
  • VDD high power supply potential
  • VSS low power supply potential
  • GND ground potential
  • X and Y are electrically connected when they are connected. Note that when only a power supply line is arranged between X and Y, there is no other element between X and Y, so X and Y are directly connected. Become.
  • X and Y are electrically connected when the drain and source of the transistor are interposed between X and Y.
  • a capacitive element when a capacitive element is arranged between X and Y, it may or may not be defined that X and Y are electrically connected.
  • a capacitive element in the configuration of a digital circuit or logic circuit, if a capacitive element is arranged between X and Y, it may not be defined that X and Y are electrically connected.
  • X and Y may be defined as being electrically connected.
  • X and Y are functionally connected is a circuit that enables functional connection between X and Y (e.g., logic circuit (e.g., inverter, NAND circuit, and NOR circuit), Signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of signals), voltage source, current source, switching circuit, amplifier circuit (for example, a circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, and buffer circuit), signal generation circuit, memory circuit, and control circuit ) can be connected between X and Y one or more times. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element or connected via another circuit) and when X and Y are directly connected (that is, connected without another element or another circuit between X and Y). (if any) and
  • X and Y, and the source (which may be referred to as one of the first terminal or the second terminal) and the drain (which may be referred to as the other of the first terminal or the second terminal) of the transistor are , are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y.”
  • the source of the transistor is electrically connected to X
  • the drain of the transistor is electrically connected to Y
  • X, the source of the transistor, the drain of the transistor, Y are electrically connected in that order.
  • X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order.”
  • X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).
  • circuit diagram shows independent components electrically connected to each other, if one component has the functions of multiple components.
  • one component has the functions of multiple components.
  • one conductive film has both the function of the wiring and the function of the electrode. Therefore, the term "electrically connected" in this specification includes cases where one conductive film functions as a plurality of constituent elements.
  • a “resistive element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ or a wiring having a resistance value higher than 0 ⁇ . Therefore, in this specification and the like, a “resistive element” includes a wiring having a resistance value, a transistor, a diode, or a coil through which a current flows between a source and a drain.
  • resistive element may be interchanged with the terms “resistance,””load,” or “region having a resistance value.”
  • the terms “resistor,””load,” or “region having a resistance value” may be interchanged with the term “resistive element.”
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, still more preferably 10 m ⁇ or more and 1 ⁇ or less. Also, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • capacitor element refers to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or It can be the gate capacitance of a transistor. Also, the terms “capacitance element”, “parasitic capacitance”, or “gate capacitance” may be interchanged with the term “capacitance”.
  • capacitor may be interchanged with the terms “capacitive element,” “parasitic capacitance,” or “gate capacitance.”
  • a “capacity” (including a “capacity” with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term “pair of conductors” in “capacitance” can be replaced with “pair of electrodes,” “pair of conductive regions,” “pair of regions,” or “pair of terminals.” Also, the terms “one of a pair of terminals” and “the other of a pair of terminals” may be referred to as a first terminal and a second terminal, respectively.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • a transistor has three terminals called a gate, a source, and a drain.
  • a gate is a control terminal that controls the conduction state of a transistor.
  • the two terminals functioning as source or drain are the input and output terminals of the transistor.
  • One of the two input/output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of potentials applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
  • a transistor may have a back gate in addition to the three terminals described above, depending on the structure of the transistor.
  • one of the gate and back gate of the transistor may be referred to as a first gate
  • the other of the gate and back gate of the transistor may be referred to as a second gate.
  • the terms "gate” and “backgate” may be used interchangeably for the same transistor.
  • the respective gates may be referred to as a first gate, a second gate, a third gate, or the like in this specification and the like.
  • a multi-gate transistor having two or more gate electrodes can be used as an example of a transistor.
  • the multi-gate structure since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is obtained. Therefore, the multi-gate structure can reduce off-state current and improve the breakdown voltage (reliability) of the transistor.
  • the multi-gate structure even if the voltage between the drain and source changes when operating in the saturation region, the current between the drain and source does not change much and the slope is flat. properties can be obtained.
  • the flat-slope voltage-current characteristic an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.
  • circuit elements such as “light-emitting device” and “light-receiving device” may have polarities called “anode” and “cathode”.
  • anode In the case of a “light emitting device”, it may be possible to cause the “light emitting device” to emit light by applying a forward bias (applying a positive potential to the "anode” with respect to the "cathode”).
  • the “anode” and “cathode” are sometimes treated as input/output terminals in circuit elements such as “light-emitting device” and “light-receiving device”.
  • the “anode” and “cathode” of circuit elements such as “light-emitting device” and “light-receiving device” are sometimes referred to as terminals (first terminal, second terminal, etc.).
  • terminals first terminal, second terminal, etc.
  • one of the “anode” and the “cathode” may be referred to as the first terminal, and the other of the “anode” and the “cathode” may be referred to as the second terminal.
  • the circuit element may have a plurality of circuit elements.
  • the circuit element when one resistor is described on the circuit diagram, it includes the case where two or more resistors are electrically connected in series.
  • the case where one capacitor is described on the circuit diagram includes the case where two or more capacitors are electrically connected in parallel.
  • the switch when one transistor is illustrated in a circuit diagram, two or more transistors are electrically connected in series and the gates of the transistors are electrically connected to each other. shall include Similarly, for example, when one switch is described on the circuit diagram, the switch has two or more transistors, and the two or more transistors are electrically connected in series or in parallel. and the gates of the respective transistors are electrically connected to each other.
  • a node can be called a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. Terminals, wirings, and the like can also be called nodes.
  • Voltage is a potential difference from a reference potential.
  • the reference potential is ground potential
  • “voltage” can be replaced with “potential”. Note that the ground potential does not necessarily mean 0V.
  • the potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit etc. also change.
  • high-level potential and low-level potential do not mean specific potentials.
  • the high-level potentials supplied by both wirings do not have to be equal to each other.
  • the low-level potentials applied by both wirings need not be equal to each other.
  • electrical current refers to the movement phenomenon of charge (electrical conduction).
  • electrical conduction occurs in a positive In other words, “electrical conduction is occurring”. Therefore, in this specification and the like, unless otherwise specified, the term “electric current” refers to a charge transfer phenomenon (electrical conduction) associated with the movement of carriers.
  • carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the current flow system (eg, semiconductor, metal, electrolyte, and in vacuum).
  • the "direction of current” in wiring or the like is the direction in which carriers that become positive charges move, and is described as a positive amount of current.
  • the direction in which the carriers that become negative charges move is the direction opposite to the direction of the current, and is represented by the amount of negative current. Therefore, in this specification and the like, when there is no notice about the positive or negative of the current (or the direction of the current), the description of "current flows from the element A to the element B" should be rephrased as “current flows from the element B to the element A.” It shall be possible. Also, the description of "a current is input to the element A" can be rephrased as "a current is output from the element A”.
  • ordinal numbers such as “first”, “second”, and “third” are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Also, the order of the components is not limited. For example, the component referred to as “first” in one of the embodiments such as this specification may be the component referred to as “second” in another embodiment or the scope of claims. can also be Further, for example, the component referred to as “first” in one of the embodiments of this specification etc. may be omitted in other embodiments or the scope of claims.
  • the terms “above” and “below” do not limit the positional relationship of the components to being directly above or below and in direct contact with each other.
  • the expression “electrode B on insulating layer A” does not require that electrode B be formed on insulating layer A in direct contact with another configuration between insulating layer A and electrode B. Do not exclude those containing elements.
  • the expression “electrode B above the insulating layer A” it is not necessary that the electrode B is formed on the insulating layer A in direct contact with the insulating layer A and the electrode B.
  • electrode B under the insulating layer A it is not necessary that the electrode B is formed under the insulating layer A in direct contact with the insulating layer A and the electrode B. Do not exclude other components between
  • the terms “row” and “column” may be used to describe components arranged in a matrix and their positional relationships.
  • the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases explained in the specification, etc., and can be appropriately rephrased according to the situation.
  • the expression “row-wise” may be rephrased as “column-wise” by rotating the orientation of the drawing shown by 90 degrees.
  • the terms “film” and “layer” can be interchanged depending on the situation. For example, it may be possible to change the term “conductive layer” to the term “conductive film.” Or, for example, it may be possible to change the term “insulating film” to the term “insulating layer”. Alternatively, the terms “film” and “layer” may be omitted and replaced with other terms as the case may or may be. For example, it may be possible to change the term “conductive layer” or “conductive film” to the term “conductor.” Also, for example, it may be possible to change the term “insulating layer” or “insulating film” to the term “insulator”.
  • electrode in this specification do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” includes the case where a plurality of “electrodes” or “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” or an “electrode”, and vice versa.
  • terminal includes the case where two or more selected from “electrode”, “wiring”, and “terminal” are integrally formed.
  • an “electrode” can be part of a “wiring” or a “terminal”, and a “terminal” can be part of a “wiring” or an “electrode”, for example.
  • the terms “electrode”, “wiring”, or “terminal” may be replaced with the term “region” in some cases.
  • the terms “wiring”, “signal line”, and “power line” can be interchanged depending on the case or situation. For example, it may be possible to change the term “wiring” to the term “signal line”. Also, for example, it may be possible to change the term “wiring” to a term such as "power supply line”. Also, vice versa, it may be possible to change the term “signal line” or “power line” to the term “wiring”. It may be possible to change the term "power line” to the term “signal line”. Also, vice versa, the term “signal line” may be changed to the term "power line”. Also, the term “potential” applied to the wiring can be changed to the term “signal” in some cases or depending on the situation. And vice versa, the term “signal” may be changed to the term “potential”.
  • timing charts are sometimes used to describe the operation method of the semiconductor device.
  • the timing charts used in this specification and the like show ideal operation examples. is not limited unless otherwise specified.
  • the magnitude and timing of signals (for example, potential or current) input to each wiring (including nodes) in the timing chart may be changed depending on the situation. It can be performed. For example, even if the timing chart shows two periods at equal intervals, the lengths of the two periods may differ from each other. Also, for example, in two periods, even if one period is long and the other period is described as short, the length of both periods may be equal, or one period may be short And the other period may be longer in some cases.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can constitute a channel-forming region of a transistor having at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide is called a metal oxide semiconductor. can do. In the case of describing an OS transistor, it can also be referred to as a transistor including a metal oxide or an oxide semiconductor.
  • nitrogen-containing metal oxides may also be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
  • semiconductor impurities refer to, for example, substances other than the main component that constitutes the semiconductor layer.
  • impurities may cause one or more of, for example, an increase in defect level density, a decrease in carrier mobility, and a decrease in crystallinity in a semiconductor.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, and Group 15 elements.
  • transition metals other than the main constituents among others, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (including oxygen and hydrogen). not).
  • a switch is one that has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to pass current.
  • a switch has a function of selecting and switching a path through which current flows. Therefore, the switch may have two or more terminals through which current flows, in addition to the control terminal.
  • an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control current.
  • Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes , and diode-connected transistors), or a logic circuit combining these.
  • transistors eg, bipolar transistors, MOS transistors, etc.
  • diodes eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes , and diode-connected transistors
  • the “conducting state” of the transistor means, for example, a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which a current flows between the source electrode and the drain electrode.
  • a “non-conducting state” of a transistor means a state in which a source electrode and a drain electrode of the transistor can be considered to be electrically cut off. Note that the polarity (conductivity type) of the transistor is not particularly limited when the transistor is operated as a simple switch.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of ⁇ 5° or more and 5° or less is also included.
  • substantially parallel or “substantially parallel” refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
  • Perfect means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.
  • the content (or part of the content) described in one embodiment may be combined with another content (or part of the content) described in that embodiment, or one or a plurality of other implementations. can be applied, combined, or replaced with at least one of the contents described in the form of (may be part of the contents).
  • figure (may be part of) described in one embodiment refers to another part of that figure, another figure (may be part) described in that embodiment, and one or more other More drawings can be formed by combining at least one of the drawings (or part of them) described in the embodiments.
  • plan views may be used to describe the configuration according to each embodiment.
  • a plan view is, for example, a diagram showing a surface of the structure viewed from the vertical direction, or a diagram showing a surface (cut) obtained by cutting the structure in the horizontal direction.
  • Hidden lines for example, dashed lines
  • the term "plan view” can be replaced with the term "plan view”, “projection view”, "top view”, or "bottom view”.
  • a plane (cut) obtained by cutting the configuration in a direction different from the horizontal direction may be called a plan view instead of a plane (cut) obtained by cutting the configuration in the horizontal direction.
  • cross-sectional views may be used to describe the configuration according to each embodiment.
  • a cross-sectional view is, for example, a diagram showing a plane of the structure viewed from the horizontal direction, or a diagram showing a plane (cut) obtained by cutting the structure in the vertical direction.
  • the term "cross-sectional view” can be replaced with the terms "cross-sectional schematic view", “front view”, or "side view”.
  • a plane (cut) obtained by cutting the configuration in a direction different from the vertical direction may be referred to as a cross-sectional view instead of a plane (cut) obtained by cutting the configuration in the vertical direction.
  • FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device DEV which is one embodiment of the present invention.
  • the semiconductor device DEV has, for example, a memory layer ALYa and a memory layer ALYb. Note that in FIG. 1, the memory layer ALYb is located above the memory layer ALYa.
  • Each of the memory layer ALYa and the memory layer ALYb has a plurality of memory cells.
  • a plurality of memory cells are arranged in an array in each of the memory layers ALYa and ALYb.
  • memory cells are arranged in a matrix of m rows and n columns (where m is an integer of 1 or more and n is an integer of 1 or more) in each of the memory layers ALYa and ALYb. ing.
  • the memory cell MC located in the first row and first column of the matrix of the memory layer ALYa is described as memory cell MCa[1,1].
  • the memory cell positioned at the m-th row and the n-th column of the matrix of the memory layer ALYb is referred to as memory cell MCb[m,n].
  • the number of rows and columns of the matrix of the memory layer ALYa is the same as the number of rows and columns of the matrix of the memory layer ALYb.
  • the number of rows and the number of columns of may not necessarily match.
  • the memory cell MC shown in FIG. 1 is an example of a memory cell called a DRAM (Dynamic Random Access Memory), and has a transistor M1 and a capacitor C1.
  • a DRAM using an OS transistor as the transistor M1 may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark).
  • an OS transistor is preferably applied to the transistor M1.
  • metal oxides included in the channel formation region of the OS transistor include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains one or more selected from indium, the element M, and zinc.
  • Element M includes gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.
  • the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) also referred to as IGZO
  • an oxide containing indium, tin, and zinc also referred to as ITZO (registered trademark)
  • ITZO registered trademark
  • oxides containing indium, gallium, tin, and zinc are preferably used.
  • an oxide containing indium (In), aluminum (Al), and zinc (Zn) is preferably used.
  • an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used.
  • IAGZO oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn)
  • a transistor other than the OS transistor may be applied to the transistor M1.
  • a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) can be applied to the transistor M1.
  • silicon for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon) can be used.
  • the transistor M1 includes, for example, a transistor whose channel formation region contains germanium, zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium.
  • a transistor whose channel formation region includes a compound semiconductor, a transistor whose channel formation region includes a carbon nanotube, or a transistor whose channel formation region includes an organic semiconductor can be used.
  • the transistor M1 illustrated in FIG. 1 is an n-channel transistor, it may be a p-channel transistor depending on the situation or circumstances. Also, when the n-channel transistor is replaced with the p-channel transistor, it is necessary to appropriately change the potential input to the memory cell MC so that the memory cell MC operates normally. Note that this applies not only to the transistors described in FIG. 1 but also to the transistors described in other parts of the specification or illustrated in other drawings. Also, in this embodiment, the configuration of the memory cell MC will be described with the transistor M1 as an n-channel transistor.
  • transistor M1 when the transistor M1 is on, it is preferable to operate in the saturation region. Also, in some situations, transistor M1 may operate in its linear region when it is on. Also, the transistor M1 may operate in the sub-threshold region.
  • the transistor M1 is, for example, a transistor with a structure having gates above and below a channel, and the transistor M1 has a first gate and a second gate.
  • the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be exchanged with each other. can be done. Therefore, in this specification and the like, the term “gate” can be replaced with the term “back gate”.
  • backgate can be interchanged with the term “gate.”
  • a connection configuration in which "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring” is replaced by “the back gate is electrically connected to the first wiring.” and the gate is electrically connected to the second wiring”.
  • the first terminal of the transistor M1 is connected to the capacitor C1. is electrically connected to the first terminal of the
  • the second terminal of the transistor M1 is electrically connected to the wiring BLa[1]. It is connected.
  • the second terminal of the transistor M1 is electrically connected to the wiring BLa[n]. properly connected.
  • the second terminal of the transistor M1 is electrically connected to the wiring BLb[1]. properly connected.
  • the second terminal of the transistor M1 is electrically connected to the wiring BLb[n]. properly connected.
  • the gates of the transistors M1 are electrically connected to the wiring WLa[1].
  • the second terminal of the capacitor C1 is electrically connected to the wiring CLa[1].
  • the gate of the transistor M1 is electrically connected to the wiring WLa[m].
  • a second terminal of the capacitor C1 is electrically connected to the wiring CLa[m].
  • the gate of the transistor M1 is electrically connected to the wiring WLb[1].
  • the second terminal of the capacitor C1 is electrically connected to the wiring CLb[1].
  • the gate of the transistor M1 is electrically connected to the wiring WLb[m].
  • a second terminal of the capacitor C1 is electrically connected to the wiring CLb[m].
  • the back gates of the transistors M1 are extended to the memory layer ALYa. is electrically connected to the wiring CLa[1].
  • the back gates of the transistors M1 are extended to the memory layer ALYa. is electrically connected to the wiring CLa[m].
  • the back gates of the transistors M1 included in each of the memory cells MCa[1,1] to MCa[m,n] arranged in the memory layer ALYa extend below the memory layer ALYa, for example. It may be electrically connected to the wiring provided (not shown). Further, the wirings CLa[1] to CLa[m] extending in the memory layer ALYb may be electrically connected to the back gates of the transistors arranged above the memory layer ALYb, for example. (not shown).
  • the wirings WLa[1] to WLa[m] function as word lines for the memory cells MCa[1,1] to MCa[m,n] included in the memory layer ALYa.
  • the wirings WLb[1] to WLb[m] function as word lines for the memory cells MCb[1,1] to MCb[m,n] included in the memory layer ALYb. That is, the wirings WLa[1] to WLa[m] and the wirings WLb[1] to WLb[m] are used as selection signals (current, variable potential) for selecting the memory cells MC to be written or read. , or pulse voltage). Note that the wirings WLa[1] to WLa[m] and the wirings WLb[1] to WLb[m] may function as wirings that supply a constant potential depending on the situation.
  • the wirings BLa[1] to BLa[n] function as bit lines for the memory cells MCa[1,1] to MCa[m,n] included in the memory layer ALYa.
  • the wirings BLb[1] to BLb[n] function as bit lines for the memory cells MCb[1,1] to MCb[m,n] included in the memory layer ALYb. That is, the wirings BLa[1] to BLa[n] and the wirings BLb[1] to BLb[n] are wirings for transmitting write data to the selected memory cell MC, and the wirings for transmitting write data to the selected memory cell. It functions as a wiring for transmitting read data from the MC. Note that the wirings BLa[1] to BLa[n] and the wirings BLb[1] to BLb[n] may function as wirings for applying a constant potential depending on the situation.
  • the wirings CLa[1] to CLa[m] and the wirings CLb[1] to CLb[m] function as wirings that apply a constant potential.
  • the constant potential can be, for example, a high level potential, a low level potential, a positive potential, a ground potential, or a negative potential.
  • the wirings CLa[1] to CLa[m] and the wirings CLb[1] to CLb[m] function as wirings for applying a variable potential (for example, a pulse voltage) instead of a constant potential depending on the situation. You may
  • FIG. 2 is a schematic cross-sectional view showing a configuration example of a semiconductor device DEV that is one embodiment of the present invention.
  • the semiconductor device DEV has a configuration in which not only the memory layers ALYa and ALYb but also memory layers are provided below the memory layer ALYa and above the memory layer ALYb.
  • FIG. 3 is a schematic perspective view showing a configuration example of the semiconductor device DEV in FIG.
  • the hatching of insulators 222_1 and 222_2, which will be described later, is intentionally omitted, and the insulator 275 is not shown.
  • the X direction shown in FIG. 2 is parallel to the channel length direction of the transistor M1
  • the Y direction is perpendicular to the X direction
  • the Z direction is perpendicular to the X and Y directions.
  • the X direction, Y direction, and Z direction shown in FIG. 2 are right-handed. Note that the X direction, Y direction, and Z direction shown in FIG. 2 are also shown in FIG. 3 and each drawing described later.
  • the memory layer ALYa includes an insulator 222_1, an insulator 224, an insulator 253, an insulator 254, an insulator 275, an insulator 153_2, an insulator 154_2, an insulator 280_2, and a conductor 242 a , a conductor 242 b , a conductor 160_2 , a conductor 260 , and an oxide 230 .
  • the memory layer located below the memory layer ALYa has, for example, an insulator 153_1, an insulator 154_2, an insulator 280_1, and a conductor 160_1.
  • the memory cell MCa has a transistor M1 and a capacitor C1.
  • the transistor M1 is an OS transistor as an example. That is, the semiconductor layer of the transistor M1 contains metal oxide.
  • the transistor M1 includes an insulator 224, an insulator 253, an insulator 254, a conductor 242a, a conductor 242b, a conductor 260, a conductor 160_1, and an oxide 230.
  • the capacitor C1 includes an insulator 153_2, an insulator 154_2, a conductor 242b, and a conductor 160_2.
  • the conductor 260 is provided so as to overlap with the region including the oxide 230, for example.
  • Conductor 260 functions as the gate (sometimes referred to as the first gate) of transistor M1.
  • the conductor 260 functions as one of the wirings WLa[1] to WLa[m] in FIG.
  • the insulator 253 and the insulator 254 function as a first gate insulating film.
  • the oxide 230 is provided so as to overlap with a region including the conductor 160_1 with the insulator 222_1 interposed therebetween.
  • the oxide 230 functions as a semiconductor included in the channel formation region of the transistor M1.
  • the conductor 160_1 functions as a back gate (sometimes referred to as a second gate) in the transistor M1.
  • the conductor 160_1 also functions as one of a pair of electrodes of the capacitor included in the memory cell of the memory layer located below the memory layer ALYa.
  • the conductor 160_1 is provided so as to fill the opening formed in the insulator 280_1. Note that an insulator 153_1, an insulator 154_1, and a conductor 160_1 are formed in this order in the opening.
  • the insulator 222_1 and the insulator 224 function as a second gate insulating film in the transistor M1.
  • the conductor 242a is provided over part of the oxide 230 and part of the insulator 222_1.
  • the conductor 242b is provided over part of the oxide 230 and over part of the insulator 222_1, for example.
  • conductor 242 a and conductor 242 b are physically separated from each other by conductor 260 .
  • Conductor 242a functions as one of the source and drain of transistor M1
  • conductor 242b functions as the other of the source and drain of transistor M1.
  • the conductor 242a functions as one of the wirings BLa[1] to BLa[n] in FIG. 1 or a conductor electrically connected to the wiring.
  • an insulator 275 is provided over the conductors 242a and 242b to prevent diffusion of oxygen to the conductors 242a and 242b.
  • the conductor 160_2 is provided over the conductor 242b in a region that does not overlap with the oxide 230 with insulators 153_1 and 153_2 functioning as dielectrics interposed therebetween.
  • the insulator functioning as a dielectric is provided over the conductor 160_2, and the conductor 160_2 is provided over the insulator.
  • the dielectric functions as an insulator sandwiched between a pair of electrodes in the capacitor C1 in FIG. 1, and the conductor 160_2 corresponds to the second terminal of the capacitor C1 in FIG.
  • the conductor 160_2 functions as one of the wirings CLa[1] to CLa[m] in FIG. Furthermore, the conductor 160_2 also functions as a back gate of the transistor M1 included in the memory cell MCb of the memory layer ALYb in FIG.
  • the memory layer ALYb has an insulator 222_2 as an example.
  • An insulator 222_2 is provided above the conductor 260 and the conductor 160_2.
  • part of the memory cell MCb is provided on the insulator 222_2.
  • the transistor M1 of the memory cell MCb is included in the channel formation region of the transistor M1 of the memory cell MCb in the region including the conductor 160_2 functioning as the second terminal of the capacitor C1, similarly to the transistor M1 of the memory cell MCa.
  • the semiconductors are arranged so that they overlap.
  • the conductor 160_2 included in the capacitor C1 of the memory cell MCb also functions as the back gate of the transistor M1 included in the memory cell of the memory layer arranged above the memory layer ALYb.
  • a conductor corresponding to the second terminal of the capacitor C1 of the memory cell in the lower memory layer and a back gate of the transistor M1 of the memory cell in the upper memory layer. can also serve as conductors.
  • a conductor corresponding to the gate of the transistor M1 included in the memory cell and a conductor corresponding to the second terminal of the capacitor C1 can be formed at the same time. That is, with the configuration shown in FIG. 2, the effects of reducing the number of photomasks for manufacturing the semiconductor device DEV and shortening the manufacturing process of the semiconductor device DEV are obtained.
  • the configuration of the semiconductor device DEV in FIG. 2 may be changed depending on the situation.
  • the semiconductor device DEV in FIG. 2 may be modified to have the configuration of the semiconductor device DEV shown in FIG.
  • a conductor 270 functioning as a plug or a wiring is provided over the conductor 242a that does not overlap with the oxide 230
  • a conductor 242c is provided over the conductor 270 and the insulator 222_2.
  • the conductor 242c can be formed simultaneously with the conductors 242a and 242b included in the memory cell MCb of the memory layer ALYb.
  • the same material as the conductors 242a and 242b can be used for the conductor 242c.
  • the conductor 242c functions as one of the wirings BLa[1] to BLa[n] in the memory layer ALYa.
  • FIG. 5 is a layout diagram (plan view) showing the circuit configuration of the memory layer ALYa of the semiconductor device DEV shown in FIG. Note that in FIG. 5, for convenience, the wiring extending below the memory layer ALYa and electrically connected to the back gate of the transistor M1 included in the memory cell MCa is designated as the wiring CLz[1] to the wiring CLz[1]. It is illustrated as CLz[m]. Also, FIG. 5 does not show an insulator included in the semiconductor device DEV.
  • a conductor 160_1 is provided below the memory layer ALYa, similar to the description of the semiconductor device DEV in FIG. Also, an oxide 230 is provided above the conductor 160_1. A conductor 242 a and a conductor 242 b are provided to cover part of the oxide 230 . A conductor 260 is provided over the oxide 230, the conductor 242a, and the conductor 242b. A conductor 160_2 is provided above the conductors 242a and 242b.
  • the conductors 242a function as wirings BLa[1] to BLa[n] extending in the column direction, as shown in FIG.
  • the conductor 160_1 functions as the wiring CLz[1] to the wiring CLz[m] extending in the row direction. Note that when the memory layer ALYa illustrated in FIG. 5 is replaced with the memory layer ALYb, the conductor 160_1 can be regarded as the wirings CLa[1] to CLa[m] extending in the row direction.
  • the conductor 160_2 functions as wirings CLa[1] to CLa[m] extending in the row direction. Note that when the memory layer ALYa illustrated in FIG. 5 is replaced with the memory layer ALYb, the conductor 160_2 can be regarded as the wiring CLb[1] to the wiring CLb[m] extending in the row direction.
  • the transistor M1 is formed by the oxide 230, a partial conductor 242a, a partial conductor 242b, a partial conductor 260, a partial conductor 160_1, a gate insulating film (not shown), and the like. formed.
  • a capacitor C1 is formed by a part of the conductor 242b, a part of the conductor 160_2, an insulator (not shown) functioning as a dielectric, and the like.
  • Each of the oxide 230, the conductor 242a, the conductor 242b, the conductor 260, the conductor 160_1, and the conductor 160_2 can be formed using a lithography method, for example.
  • a conductive material to be the conductor 242a is formed using one or more methods selected from a sputtering method, a CVD method, a PLD method, and an ALD method. , and then a desired pattern may be formed by lithography.
  • the oxide 230, the conductor 242b, the conductor 260, the conductor 160_1, and the conductor 160_2 can also be formed by a method similar to the above.
  • an insulator may be provided between the oxide 230 and the conductor 260, between the oxide 230 and the conductor 160_1, and between the conductor 242b and the conductor 160_2.
  • an insulator provided between the oxide 230 and the conductor 260 may function as a first gate insulating film (also referred to as a gate insulating film or a front gate insulating film).
  • planarization using a chemical mechanical polishing method or the like is performed in order to align the height of the film surface on which one or more selected from insulators, conductors, and semiconductors are formed. It may be planarized by processing.
  • FIG. 6A to 6D are a schematic plan view and a schematic cross-sectional view of a memory cell MC having a transistor M1 and a capacitor C1 in the semiconductor device DEV of FIG. 2.
  • FIG. FIG. 6A is a schematic plan view of the memory cell MC.
  • 6B to 6D are schematic cross-sectional views of the memory cell MC.
  • FIG. 6B is a cross-sectional view taken along the dashed-dotted line A1-A2 shown in FIG. 6A, and is also a cross-sectional view in the channel length direction of the transistor M1.
  • FIG. 6C is a schematic cross-sectional view of the portion of the dashed-dotted line A3-A4 shown in FIG.
  • FIG. 6A is also a schematic cross-sectional view of the transistor M1 in the channel width direction.
  • FIG. 6D is a cross-sectional view taken along the dashed-dotted line A5-A6 shown in FIG. 6A, and is also a schematic cross-sectional view of the capacitor C1. Note that some elements are omitted in the top view of FIG. 6A for clarity of illustration.
  • the memory cell MC has an insulator 280_1, an insulator 153_1, an insulator 154_1, and a conductor 160_1 (a conductor 160a_1 and a conductor 160b_1) over a substrate (not shown).
  • the memory cell MC also has an insulator 222_1 over the insulator 280_1, the insulator 153_1, the insulator 154_1, and the conductor 160_1.
  • the memory cell MC includes an insulator 224, an oxide 230a over the insulator 224, and an oxide 230b over the oxide 230a in a region over the insulator 222_1 that overlaps with the conductor 160_1. .
  • the memory cell MC has conductors 242a (a conductor 242a1 and a conductor 242a2) over the insulator 222_1, the side surface of the insulator 224, the side surface of the oxide 230a, and the oxide 230b, and the conductor 242b ( a conductor 242b1 and a conductor 242b2).
  • the memory cell MC also includes an insulator 275 over the insulator 222_1, the conductor 242a, and the conductor 242b, and an insulator 280_2 over the insulator 275.
  • the memory cell MC also includes an insulator 253 over the oxide 230b, an insulator 254 over the insulator 253, and a conductor 260 (a conductor 260a and a conductor 260b) over the insulator 254.
  • the memory cell MC includes an insulator 153_2 which is located over the conductor 242b and does not overlap with the oxides 230a and 230b, an insulator 154_2 over the insulator 153_2, and a conductor 160_2 over the insulator 154_2. (Conductor 160a_2 and Conductor 160b_2).
  • the memory cell MC also has an insulator 222_2 over the insulator 280_2, the insulator 253, the insulator 254, the conductor 260, the insulator 153_2, the insulator 154_2, and the conductor 160_2.
  • transistor M1 and capacitor C1 are disposed embedded in insulator 280_2.
  • the oxide 230a and the oxide 230b are collectively referred to as the oxide 230 in some cases.
  • the insulator 280_2 and the insulator 275 are provided with openings 258 reaching the oxide 230b.
  • the opening 258 has a region that overlaps with the oxide 230b.
  • the insulator 275 has an opening that overlaps with the opening of the insulator 280_2. That is, the opening 258 includes the opening of the insulator 280_2 and the opening of the insulator 275 .
  • an insulator 253 , an insulator 254 , and a conductor 260 are arranged in the opening 258 . That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 253 and 254 interposed therebetween.
  • a conductor 260, an insulator 253, and an insulator 254 are provided between the conductor 242a and the conductor 242b in the channel length direction of the transistor M1.
  • the insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260 . Note that the top surface of the insulator 222_1 is exposed in a region of the opening 258 that does not overlap with the oxide 230, as shown in FIG. 6C.
  • the oxide 230 preferably has an oxide 230a overlying the insulator 224 and an oxide 230b overlying the oxide 230a.
  • the transistor M1 shows a structure in which the oxide 230 has two layers of the oxide 230a and the oxide 230b stacked, the present invention is not limited to this.
  • a single layer of the oxide 230b or a layered structure of three or more layers may be provided, or each of the oxides 230a and 230b may have a layered structure.
  • transistor M1 comprises an oxide 230 that functions as a semiconductor layer, a conductor 260 that functions as a first gate (also called gate, top gate, or front gate) electrode, and a second gate (back gate) electrode.
  • It also has an insulator 253 and an insulator 254 that function as a first gate insulator.
  • It also has an insulator 222_1 and an insulator 224 that act as a second gate insulator.
  • the gate insulator is sometimes called a gate insulating layer or a gate insulating film. At least part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.
  • the first gate electrode and the first gate insulating film are arranged in the insulator 280_2 and the opening 258 formed in the insulator 275 . That is, conductor 260 , insulator 254 , and insulator 253 are positioned within opening 258 .
  • the capacitor C1 has a conductor 242b functioning as a lower electrode, insulators 153_2 and 154_2 functioning as dielectrics, and a conductor 160_2 functioning as an upper electrode. That is, the capacitance C1 constitutes an MIM (Metal-Insulator-Metal) capacitance.
  • MIM Metal-Insulator-Metal
  • the upper electrode of the capacitor C1 and the dielectric are arranged in the openings 158 formed in the insulator 280_2 and the insulator 275, respectively. That is, the conductor 160_2, the insulator 153_2, and the insulator 154_2 are arranged within the opening 158.
  • FIG. 1 The conductor 160_2, the insulator 153_2, and the insulator 154_2 are arranged within the opening 158.
  • the memory cell MC including the transistor M1 and the capacitor C1 described in this embodiment can be used as a memory cell of a memory device.
  • the conductor 242a may be electrically connected to the sense amplifier, and the conductor 242a functions as a bit line.
  • the capacitor C1 is provided so as to overlap with the conductor 242b of the transistor M1. Therefore, in a plan view, the capacitor C1 can be provided without greatly increasing the occupied area, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • each A indicates a schematic plan view.
  • B in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A1-A2 shown in each A, and is also a schematic cross-sectional view in the channel length direction of the transistor M1.
  • C in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A3-A4 shown in each A, and is also a schematic cross-sectional view in the channel width direction of the transistor M1.
  • D in each figure is a schematic cross-sectional view of the portion of the dashed-dotted line A5-A6 shown in each A. As shown in FIG. In the schematic plan view of A in each figure, some elements are omitted for clarity of the drawing.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is a sputtering method, a CVD (Chemical Vapor Deposition) method, an MBE (Molecular A film can be formed by appropriately using a film formation method such as a beam epitaxy) method, a PLD (Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method.
  • a substrate (not shown) is prepared, and an insulator 280_1, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are formed over the substrate (see FIGS. 7A to 7D).
  • an insulator 280_1 is formed over the substrate, and then openings are formed in the insulator 280_1 in regions where the insulator 153_1, the insulator 154_1, and the conductor 160_1 are to be formed. After the opening is formed, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are sequentially formed in the opening, and then a planarization process such as a chemical mechanical polishing (CMP) method is performed. Then, the insulator 153_1, the insulator 154_1, and the conductor 160_1 are partially removed to expose the insulator 280_1.
  • CMP chemical mechanical polishing
  • the insulator 153_1, the insulator 154_1, and the conductor 160_1 can be formed only in the opening formed in the conductor 160_1.
  • a method for forming the insulator 153_2, the insulator 154_2, and the conductor 160_2, which will be described later, can be referred to (see FIGS. 12A to 16D). .
  • an insulator 222_1 is formed over the insulator 280_1, the insulator 153_1, the insulator 154_1, and the conductor 160_1 (see FIGS. 7A to 7D).
  • an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited.
  • the insulator containing oxides of one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • hafnium-zirconium oxide is preferably used.
  • An insulator containing oxides of one or both of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Since the insulator 222_1 has barrier properties against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor M1 into the transistor M1 through the insulator 222_1 is suppressed. , the generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222_1 can be deposited using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • hafnium oxide is deposited as the insulator 222_1 by an ALD method.
  • a high-k material with a high dielectric constant may be used as the insulating material used for the insulator 222_1.
  • the high-k material having a high dielectric constant include, in addition to the hafnium oxide described above, one or two selected from aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium. Metal oxides containing more than one species are included.
  • the insulator 222_1 may be aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing oxides of one or both of aluminum and hafnium. .
  • the insulator 222_1 may have a layered structure including two or more materials selected from the above materials.
  • the heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment after the insulator 222_1 is formed, treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1.
  • impurities such as water or hydrogen contained in the insulator 222_1 can be removed.
  • part of the insulator 222_1 might be crystallized by the heat treatment.
  • the heat treatment can be performed at a timing such as after the insulator 224 is formed.
  • an insulating film 224Af is formed over the insulator 222_1 (see FIGS. 8A to 8D).
  • the insulating film 224Af can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a silicon oxide film is formed as the insulating film 224Af by a sputtering method.
  • the hydrogen concentration in the insulating film 224Af can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Since the insulating film 224Af will be in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this manner.
  • an insulating material such as silicon oxynitride may be used.
  • an oxide film 230Af and an oxide film 230Bf are formed in this order on the insulating film 224Af (see FIGS. 8A to 8D).
  • the oxide film 230Af and the oxide film 230Bf are preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposure to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230Af and the oxide film 230Bf. can be kept clean.
  • the oxide film 230Af and the oxide film 230Bf can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the sputtering method is used to form the oxide films 230Af and 230Bf.
  • the oxide film 230Af and the oxide film 230Bf are formed by sputtering
  • oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased.
  • the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.
  • part of the oxygen contained in the sputtering gas may be supplied to the insulator 224 when forming the oxide film 230Af. Therefore, the percentage of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230Bf is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is set to more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxide film 230Bf is oxygen-excessive oxidation. A material semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this.
  • an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% or more and 30% or less, preferably 5% or more and 20% or less. be.
  • a transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
  • the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf are preferably formed by a sputtering method without being exposed to the air.
  • a multi-chamber film deposition apparatus may be used.
  • the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf can be prevented from being mixed with hydrogen between the film formation steps.
  • the ALD method may be used to form the oxide films 230Af and 230Bf.
  • films having a uniform thickness can be formed even in trenches or openings with a large aspect ratio.
  • the oxide films 230Af and 230Bf can be formed at a lower temperature than the thermal ALD method.
  • the heat treatment may be performed within a temperature range in which the oxide film 230Af and the oxide film 230Bf are not polycrystallized, and may be performed at 250° C. or higher and 650° C. or lower, preferably 400° C. or higher and 600° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas may be about 20%.
  • heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less.
  • the heat treatment is performed at a temperature of 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • Such heat treatment including oxygen gas can reduce impurities such as carbon, water, or hydrogen in the oxide films 230Af and 230Bf.
  • the crystallinity of the oxide film 230Bf can be improved, and the structure can be made denser with higher density.
  • the crystal regions in the oxide films 230Af and 230Bf can be increased, and the in-plane variation of the crystal regions in the oxide films 230Af and 230Bf can be reduced. Therefore, in-plane variations in electrical characteristics of the transistor M1 can be reduced.
  • hydrogen in the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf moves to the insulator 222_1 and is absorbed into the insulator 222_1.
  • hydrogen in the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf diffuses into the insulator 222_1. Therefore, the hydrogen concentration in the insulator 222_1 increases, but the hydrogen concentrations in the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf decrease.
  • the insulating film 224Af functions as a gate insulator of the transistor M1
  • the oxide films 230Af and 230Bf function as channel formation regions of the transistor M1. Therefore, the transistor M1 including the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf with reduced hydrogen concentration is preferable because it has high reliability.
  • the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf are processed into strips by lithography to form the insulating layer 224A, the oxide layer 230A, and the oxide layer 230B (FIGS. 9A to 9D). 9D).
  • the insulating layer 224A, the oxide layer 230A, and the oxide layer 230B extend in a direction parallel to the dashed-dotted line A3-A4 (the channel width direction of the transistor M1 or the Y direction shown in FIG. 6A). Form. At least part of the insulating layer 224A, the oxide layer 230A, and the oxide layer 230B overlaps with the conductor 160_1.
  • a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing. Also, the insulating film 224Af, the oxide film 230Af, and the oxide film 230Bf may be processed under different conditions.
  • the resist is first exposed through a mask.
  • the exposed regions are removed or left using a developer to form a resist mask.
  • a conductor, a semiconductor, or an insulator can be processed into a desired shape by etching treatment through the resist mask.
  • a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.
  • a hard mask made of an insulator or conductor may be used under the resist mask.
  • an insulating film or a conductive film as a hard mask material is formed on the oxide film 230Bf, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • the etching of the oxide film 230Bf or the like may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the oxide film 230Bf.
  • the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.
  • a conductive film 242Af and a conductive film 242Bf are formed in this order over the insulator 222_1 and the oxide layer 230B (see FIGS. 10A to 10D).
  • the conductive films 242Af and 242Bf can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • tantalum nitride may be deposited by a sputtering method as the conductive film 242Af
  • tungsten may be deposited as the conductive film 242Bf. Note that heat treatment may be performed before the conductive film 242Af is formed.
  • the heat treatment may be performed under reduced pressure to continuously form the conductive film 242Af without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide layer 230B can be removed, and the moisture concentration and hydrogen concentration in the oxide layers 230A and 230B can be reduced. .
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.
  • the conductive film 242Af includes, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, and a nitride containing titanium.
  • Conductive materials such as nitrides containing aluminum may also be used.
  • a conductive material such as, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even after absorbing oxygen.
  • the conductive film 242Bf includes, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, A conductive material such as a metal element selected from indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the metal elements described above, or an alloy combining the metal elements described above may be used.
  • conductive materials such as titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel do not oxidize. It is preferable because it is a conductive material that is difficult to resist or a material that maintains conductivity even if it absorbs oxygen.
  • the conductive film 242Af and the conductive film 242Bf may be used for the conductive film 242Af and the conductive film 242Bf.
  • the conductive film 242Af and the conductive film 242Bf may be made of the same material. That is, in the memory cell MC, the conductor 242a1 and the conductor 242a2 may be one conductor. Similarly, conductor 242b1 and conductor 242b2 may be one conductor.
  • the insulating layer 224A, the oxide layer 230A, the oxide layer 230B, the conductive film 242Af, and the conductive film 242Bf are processed by a lithography method to form an island-shaped insulator 224, an oxide layer 230a, and an oxide layer 230B.
  • An object 230b and island-shaped conductive layers 242A and 242B having openings are formed (see FIGS. 11A to 11D).
  • the insulating layer 224A, the oxide layer 230A, the oxide layer 230B, the conductive film 242Af, and the conductive film 242Bf are processed to form island-shaped insulators 224, oxides 230a, and 230b, and the dashed-dotted line A1.
  • the conductive layers 242A and 242B are formed.
  • an island-shaped conductive layer 242A and a conductive layer 242B having openings are formed.
  • the insulating layer 224A, the oxide layer 230A, the oxide layer 230B, the conductive film 242Af, and the conductive film 242Bf are processed into an island shape to form the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, After the conductive layers 242A and 242B are formed, openings may be formed in the conductive layers 242A and 242B.
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B are formed so that at least part of them overlaps with the conductor 160_1.
  • the openings in the conductive layers 242A and 242B are formed so as not to overlap with the oxide 230b.
  • a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing.
  • the insulating layer 224A, the oxide layer 230A, the oxide layer 230B, the conductive film 242Af, and the conductive film 242Bf may be processed under different conditions.
  • side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B may be tapered.
  • the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B may have a taper angle of, for example, 60° or more and less than 90°.
  • the structure is not limited to the above, and side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B may be substantially perpendicular to the top surface of the insulator 222_1. With such a configuration, it is possible to reduce the area and increase the density when providing a plurality of transistors M1.
  • by-products generated in the above etching step are formed in layers on side surfaces of the insulator 224, the oxides 230a and 230b, the conductive layers 242A, and the conductive layers 242B in some cases.
  • the layered byproduct is formed between the insulator 224 , the oxide 230 a , the oxide 230 b , the conductive layers 242 A and 242 B, and the insulator 275 . Therefore, the layered byproduct formed in contact with the top surface of the insulator 222_1 is preferably removed.
  • an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B (see FIGS. 12A to 12D).
  • the insulator 275 is preferably in contact with the top surface of the insulator 222_1 and the side surface of the insulator 224 .
  • the insulator 275 can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • An insulating film having a function of suppressing permeation of oxygen is preferably used as the insulator 275 .
  • silicon nitride may be deposited by ALD.
  • aluminum oxide is deposited by a sputtering method, and silicon nitride is deposited thereon by a PEALD method.
  • the function of suppressing diffusion of impurities such as water or hydrogen and oxygen may be improved.
  • the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B can be covered with the insulator 275, which has a function of suppressing diffusion of oxygen. Accordingly, direct diffusion of oxygen from the insulator 280_2 to be formed later into the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B in a later step can be reduced.
  • an insulating film to be the insulator 280_2 is formed over the insulator 275 .
  • the insulating film can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a silicon oxide film may be formed by a sputtering method.
  • the insulator 280_2 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280_2 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • heat treatment may be performed before the insulating film is formed.
  • the heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air.
  • moisture and hydrogen adsorbed to the surface of the insulator 275 or the like can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b, and the insulator 224 can be reduced.
  • the heat treatment conditions described above can be used for the heat treatment.
  • a material with a low dielectric constant is preferably used for the insulating film that serves as the insulator 280_2.
  • materials with a low dielectric constant include, for example, silicon oxide and silicon oxynitride.
  • silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be given.
  • silicon nitride oxide or silicon nitride may be used for the insulating film to be the insulator 280_2.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • nitride oxide refers to a material whose composition contains more nitrogen than oxygen. point to the material.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. indicates
  • planarization treatment such as CMP is performed on the insulating film to be the insulator 280_2 to form the insulator 280_2 with a flat upper surface (see FIGS. 12A to 12D).
  • a silicon nitride film may be formed over the insulator 280_2 by a sputtering method, for example, and CMP treatment may be performed until the silicon nitride reaches the insulator 280_2.
  • part of the insulator 280_2 part of the insulator 275, part of the conductive layer 242A, and part of the conductive layer 242B are processed and oxidized.
  • An opening 258 is formed that reaches object 230b. The formation of openings 258 allows conductors 242a1 and 242b1 to be formed from conductive layer 242A and conductors 242a2 and 242b2 to be formed from conductive layer 242B (see FIGS. 13A-13D).
  • a dry etching method or a wet etching method can be used for processing part of the insulator 280_2, part of the insulator 275, and part of the conductive layer 242B. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280_2 may be processed by a dry etching method, part of the insulator 275 may be processed by a wet etching method, and part of the conductive layer 242B may be processed by a dry etching method.
  • the opening 258 is formed extending in a direction parallel to the dashed-dotted line A3-A4 (the channel width direction of the transistor or the Y direction shown in FIGS. 6A and 6C). It is preferable to By forming the opening 258 in this manner, the conductor 260 which is formed later can be extended in the above direction, and the conductor 260 can function as a wiring. Further, the opening 258 is preferably formed so as to overlap with the conductor 160_1.
  • the width of the opening 258 is preferably fine because it is reflected in the channel length of the transistor M1.
  • the width of the opening 258 is preferably 1 nm or more, or 5 nm or more, and 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less.
  • part of the insulator 280_2 part of the insulator 275, part of the conductive layer 242B, and part of the conductive layer 242A are processed by anisotropic etching. is preferred. In particular, processing by dry etching is preferable because it is suitable for fine processing. Further, the processing may be performed under different conditions.
  • the side surfaces of the conductor 242a and the conductor 242b facing each other correspond to the top surface of the oxide 230b.
  • the side surfaces of the conductor 242a and the conductor 242b facing each other correspond to the top surface of the oxide 230b.
  • the side surfaces of the insulator 280_2, the insulator 275, and the conductor 242 may be tapered without being limited to the above.
  • the taper angle of the insulator 280_2 may be larger than the taper angle of the conductor 242 .
  • the top of oxide 230b may be removed.
  • the impurity may adhere to or diffuse into the side surface of the oxide 230a, the top surface and side surface of the oxide 230b, the side surface of the conductor 242, the side surface of the insulator 280_2, or the like. be.
  • a step of removing such impurities may be performed.
  • the dry etching may form a damaged region on the surface of the oxide 230b. Such damaged areas may be removed.
  • the impurities include components contained in the insulator 280_2, the insulator 275, the conductive layer 242B, and the conductive layer 242A, components contained in members used in an apparatus used for forming the opening, and substances used for etching. caused by the components contained in the gas or liquid to be discharged.
  • Such impurities include hafnium, aluminum, silicon, tantalum, fluorine, or chlorine, for example.
  • impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of the oxide 230b and its vicinity. Further, it is preferable that the concentration of the impurity is reduced.
  • the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, and 1.0 atomic % or less. Atom % or less is more preferable, and less than 0.3 atomic % is even more preferable.
  • VOH oxygen deficiency
  • VOH is VOH
  • a defect in which hydrogen enters is formed in large amounts, and the transistor tends to be normally on (a state in which a channel exists when a voltage of 0 V is applied between the gate and the source, and a current flows through the transistor). Therefore, the regions with low crystallinity of the oxide 230b are preferably reduced or removed.
  • the oxide 230b have a layered CAAC structure.
  • the CAAC structure up to the lower end of the drain of the oxide 230b.
  • the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the low-crystallinity region of the oxide 230b is removed, and the CAAC structure further suppresses variations in the electrical characteristics of the transistor M1. can. Also, the reliability of the transistor M1 can be improved.
  • a cleaning process is performed to remove impurities adhered to the surface of the oxide 230b in the etching process.
  • a cleaning method there are wet cleaning using a cleaning solution (also referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate. Note that the cleaning process may deepen the groove.
  • an aqueous solution obtained by diluting one or more selected from ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water can be used.
  • pure water or carbonated water may be used for wet cleaning.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these washings may be appropriately combined.
  • an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid
  • an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water.
  • concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate depending on impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like.
  • the ammonia concentration of the diluted ammonia water should be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
  • the concentration of hydrogen fluoride in the diluted hydrofluoric acid should be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher is preferably used for ultrasonic cleaning, and a frequency of 900 kHz or higher is more preferably used. By using the frequency, damage to the oxide 230b and the like can be reduced.
  • the above cleaning treatment may be performed multiple times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted ammonia water may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
  • Heat treatment may be performed after the above etching or after the above cleaning.
  • the heat treatment may be performed at 100° C. or higher and 450° C. or lower, preferably 350° C. or higher and 400° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxides 230a and 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved.
  • after heat treatment in an oxygen atmosphere heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the air.
  • part of the insulator 280_2 and part of the insulator 275 are processed. , forming an opening 158 reaching the conductive layer 242B (conductor 242b2) (see FIGS. 13A-13D).
  • a dry etching method or a wet etching method can be used to form the opening 158, similarly to the formation of the opening 258.
  • part of the insulator 280_2 may be processed by a dry etching method and part of the insulator 275 may be processed by a wet etching method.
  • the opening 158 is formed extending in a direction parallel to the dashed-dotted line A5-A6 (the channel width direction of the transistor or the Y direction shown in FIGS. 6A and 13D). It is preferable to By forming the opening 158 in this manner, the conductor 160_2, which is formed later, can be extended in the above direction, and the conductor 160_2 can function as a wiring.
  • openings 158 and 258 may be formed together, or one of the openings 158 and 258 may be formed first and then the other. It should be noted that opening 258 is preferably formed to expose oxide 230b at the bottom of opening 258, and opening 158 is preferably formed to expose conductor 242b2 at the bottom of opening 158. FIG. For this reason, it is preferable to use processing methods with mutually different conditions for forming the openings 158 and 258 .
  • the insulating film 253A is an insulating film that becomes the insulator 253 and the insulator 153_2 in a later step.
  • the insulating film 253A can be deposited using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 253A is preferably formed using the ALD method.
  • the insulating film 253A is preferably formed with a thin film thickness, and it is necessary to reduce variations in film thickness.
  • the ALD method is a method of forming a film by alternately introducing a precursor and a reactant (for example, an oxidizing agent). Film thickness can be adjusted.
  • the insulating film 253A needs to be deposited on the bottom and side surfaces of the opening 258 and the opening 158 with good coverage.
  • the top and side surfaces of the oxide 230 are preferably deposited with good coverage.
  • the upper surface and the side surface of the conductor 242b be coated with a film with good filming properties.
  • atomic layers can be deposited one by one on the bottom and side surfaces of the opening 258 and the opening 158, so that the insulating film 253A can be formed with good coverage over the respective openings. can.
  • ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidizing agent.
  • oxygen (O 2 ), or the like that does not contain hydrogen can be used as an oxidizing agent.
  • hafnium oxide is deposited by thermal ALD as the insulating film 253A.
  • a high-k material with a high dielectric constant may be used as the insulating material used for the insulating film 253A.
  • the high-k material having a high dielectric constant include, in addition to the hafnium oxide described above, one or two selected from aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium. Metal oxides containing more than one species are included.
  • aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing oxides of one or both of aluminum and hafnium may be used.
  • an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride oxide can be used for the insulating film 253A.
  • an insulating material such as silicon oxide to which fluorine is added or silicon oxide to which carbon is added can be used for the insulating film 253A.
  • silicon oxide to which carbon and nitrogen are added can be used for the insulating film 253A.
  • silicon oxide having holes can be used for the insulating film 253A.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulating film 253A may have a layered structure including two or more materials selected from the above materials.
  • the microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • microwave treatment may be performed at the stage when part of the insulating film 253A is formed.
  • the microwave treatment may be performed after the silicon oxide film or the silicon oxynitride film is formed.
  • Dotted arrows shown in FIGS. 14B to 14D indicate high frequencies such as microwaves or RF, oxygen plasma, oxygen radicals, and the like.
  • a microwave treatment apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • the frequency of the microwave processing device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz.
  • High-density oxygen radicals can be generated by using high-density plasma.
  • the power of the power source for applying microwaves in the microwave processing apparatus may be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power supply for applying RF to the substrate side. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • V OH contained in regions of the oxide 230 that do not overlap with the conductors 242a and 242b can be disrupted and hydrogen can be removed from the regions. That is, VOH contained in the region can be reduced. Accordingly, oxygen vacancies and VOH in the region can be reduced, and the carrier concentration can be lowered. Further, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the region, the oxygen vacancies in the region can be further reduced and the carrier concentration can be lowered.
  • the conductors 242a and 242b block the action of high frequencies such as microwaves or RF, oxygen plasma, and the like. It does not extend into the region of overlying oxide 230b. Accordingly, the microwave treatment does not reduce V OH and supply an excessive amount of oxygen in the region, so that the carrier concentration can be prevented from decreasing.
  • An insulator 253 having a barrier property against oxygen is provided in contact with side surfaces of the conductors 242a and 242b. Accordingly, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to microwave treatment can be suppressed.
  • the film quality of the insulator 253 can be improved, the reliability of the transistor M1 is improved.
  • oxygen vacancies and VOH are selectively removed from regions of the oxide 230 that do not overlap with the conductors 242a and 242b to make the regions i-type or substantially i-type. can be done.
  • excessive supply of oxygen to regions of the oxide 230 overlapping with the conductors 242a and 242b, which function as source and drain regions, can be suppressed, and conductivity can be maintained.
  • fluctuations in the electrical characteristics of the transistor M1 can be suppressed, and variation in the electrical characteristics of the transistor M1 within the substrate plane can be suppressed.
  • heat energy may be directly transmitted to the oxide 230b due to the electromagnetic interaction between the microwave and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
  • Such heat treatment is sometimes called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. Further, when hydrogen is contained in the oxide 230b, this thermal energy may be transmitted to hydrogen in the oxide 230b, and thus activated hydrogen may be released from the oxide 230b.
  • the microwave treatment may be performed before the insulating film 253A is formed without performing the microwave treatment after the insulating film 253A is formed.
  • the heat treatment may be performed while the reduced pressure state is maintained.
  • hydrogen in the insulating film 253A, the oxide 230b, and the oxide 230a can be removed efficiently.
  • part of the hydrogen might be gettered by the conductors 242 (the conductors 242a and 242b).
  • the step of performing the heat treatment may be repeated a plurality of times while the reduced pressure state is maintained. By repeating the heat treatment, hydrogen in the insulating film 253A, the oxide 230b, and the oxide 230a can be removed more efficiently.
  • the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.
  • the above-described microwave treatment that is, microwave annealing may serve as the heat treatment. When the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.
  • an insulating film 254A to be the insulator 254 and the insulator 154_2 is formed (see FIGS. 15A to 15D).
  • a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be used to deposit the insulating film 254A.
  • the insulating film 254A is preferably formed using the ALD method similarly to the insulating film 253A.
  • the insulating film 254A can be formed with a thin film thickness and good coverage.
  • silicon nitride is deposited by the PEALD method as the insulating film 254A.
  • an insulating material that can be applied to the insulating film 253A may be used for the insulating film 254A.
  • the insulating film 254A may be made of the same material as the insulating film 253A. That is, in the memory cell MC, the insulator 253 and the insulator 254 may be one insulator. Similarly, the insulator 153_1 and the insulator 154_1 may be one insulator, and the insulator 153_2 and the insulator 154_2 may be one insulator.
  • a conductive film 260A to be the conductors 260a and 160a_2 and a conductive film 260B to be the conductors 260b and 160b_2 are formed in this order (see FIGS. 15A to 15D).
  • the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a titanium nitride film is formed as the conductive film 260A to be the conductor 260a by an ALD method, and tungsten is formed by a CVD method as the conductive film 260B to be the conductor 260b.
  • a conductive material such as tantalum, tantalum nitride, titanium, ruthenium, or ruthenium oxide may be used for the conductive film 260A.
  • the conductive film 260A may have a stacked structure including two or more materials selected from the above materials.
  • the conductive film 260B may be made of a conductive material other than tungsten, such as copper or aluminum.
  • the conductive film 260B may have a stacked-layer structure including two or more materials selected from the above materials.
  • the insulating film 253A, the insulating film 254A, the conductor 260a, and the conductor 260b are polished by planarization treatment such as CMP until the insulator 280_2 is exposed. That is, portions of the insulating film 253A, the insulating film 254A, the conductors 260a, and the conductors 260b exposed from the openings 258 and 158 are removed.
  • a body 160_2 (a conductor 160a_2 and a conductor 160b_2) is formed (see FIGS. 16A to 16D).
  • the insulator 253 is provided in contact with the inner walls and side surfaces of the opening 258 overlapping the oxide 230b.
  • the conductor 260 is arranged to fill the opening 258 with the insulators 253 and 254 interposed therebetween.
  • transistor M1 is formed.
  • the insulator 153_2 is provided in contact with the inner wall and side surfaces of the opening 158 overlapping the conductor 242b.
  • the conductor 160_2 is arranged to fill the opening 158 with the insulator 153_2 and the insulator 154_2 interposed therebetween. Capacitor C1 is thus formed.
  • heat treatment may be performed under the same conditions as the above heat treatment.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • the concentration of moisture and the concentration of hydrogen in the insulator 280_2 can be reduced.
  • the insulator 222_2 may be formed continuously without exposure to the air.
  • an insulator 222_2 is formed over the insulator 253, the insulator 254, the conductor 260, the insulator 153_2, the insulator 154_2, the conductor 160_2, and the insulator 280_2 (FIGS. 6A to 6D). See Figure 6D).
  • the insulator 222_2 can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 222_2 is preferably formed, for example, by ALD using hafnium oxide with a reduced hydrogen concentration, similarly to the insulator 222_1.
  • a semiconductor device having the memory cell MCa or the memory cell MCb shown in FIG. 2 can be manufactured.
  • the capacitor C1 and the transistor M1 can be manufactured in the same step. Accordingly, the manufacturing steps of the semiconductor device having the capacitor C1 and the transistor M1 can be reduced.
  • the area occupied by the memory cells can be reduced. That is, the recording density of the semiconductor device can be increased.
  • the method for manufacturing a semiconductor device is not limited to the methods illustrated in FIGS. 6A to 16D.
  • materials and steps may be changed according to circumstances.
  • a semiconductor device may be manufactured through the manufacturing steps illustrated in FIGS. 17A to 21D.
  • opening 258 down to oxide 230b.
  • the formation of openings 258 allows conductors 242a1 and 242b1 to be formed from conductive layer 242A and conductors 242a2 and 242b2 to be formed from conductive layer 242B (see FIGS. 17A-17D). Note that the description of FIGS. 13A to 13D can be referred to for specific steps.
  • an insulating film 253A, an insulating film 254A, a conductive film 260A, and a conductive film 260B are formed in this order over the insulator 280_2 and the oxide 230 (see FIGS. 18A to 18D). Note that the description of FIGS. 15A to 15D can be referred to for specific steps.
  • the insulating film 253A, the insulating film 254A, the conductors 260a, and the conductors 260b are polished by planarization treatment such as the CMP method until the insulator 280_2 is exposed.
  • planarization treatment such as the CMP method
  • insulators 253, 254, and conductors 260 are formed in the openings 258 (see FIGS. 19A to 19D). Note that the description of FIGS. 16A to 16D can be referred to for specific steps. This corresponds to the gate of the transistor M1.
  • the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are formed in this order over the insulator 280_2 and over the conductor 242b (over the conductor 242b2) (see FIGS. 21A to 21D). ).
  • a material applicable to the insulating film 253A can be used.
  • a material that can be applied to the insulating film 254A can be used.
  • the conductive film 160A for example, a material that can be applied to the conductive film 260A can be used.
  • the conductive film 160B for example, a material that can be applied to the conductive film 260B can be used. Note that the description of FIGS. 15A to 15D can be referred to for specific steps.
  • the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are polished by a planarization process such as the CMP method until the insulator 280_2 is exposed.
  • a planarization process such as the CMP method
  • an insulator 153_2, an insulator 154_2, and a conductor 160_2 are formed in the opening 158.
  • FIG. 21D the semiconductor device shown in FIGS. 21A to 21D has substantially the same structure as that shown in FIGS. 16A to 16D by planarization treatment. Note that the description of FIGS. 16A to 16D can be referred to for specific steps of the planarization treatment.
  • the semiconductor device of one embodiment of the present invention can be manufactured by performing the manufacturing steps illustrated in FIGS. 17A to 21D after the insulator 280_2 is formed in FIGS. 12A to 12D.
  • the opening 158 is formed first, and the insulator 153_2, the insulator 154_2, and the conductor 160_2 (the conductor 160a_2 and the conductor 160b_2 are formed in the opening 158). ), followed by the formation of openings 258 and the formation of insulators 253, 254, and conductors 260 (conductors 260a and 260b) in openings 258 (as shown in the figure). do not).
  • the schematic cross-sectional view of FIG. 22 is a modification of the semiconductor device DEV shown in FIG. Specifically, the semiconductor device DEV shown in FIG. 22 is different from the semiconductor device DEV shown in FIG. 2 in that the conductor 242b and oxide 230 and the capacitor C1 overlap each other.
  • FIG. 23 is a schematic perspective view showing a configuration example of the semiconductor device DEV of FIG.
  • the hatching of insulators 222_1 and 222_2, which will be described later, is intentionally omitted, and the insulator 275 is not shown.
  • the semiconductor device DEV in FIG. 22 may have a structure in which a conductor functioning as a plug or wiring is provided over the conductor 242a, and a wiring is provided over the conductor.
  • the semiconductor device DEV shown in FIG. 24 is a modification of the semiconductor device DEV shown in FIG. A conductor 242c functioning as a wiring is provided over the body 222_2.
  • the conductor 242c can be formed at the same time as the conductor 242a and the conductor 242b included in the memory cell MCb of the memory layer ALYb.
  • the same material as the conductors 242a and 242b can be used for the conductor 242c.
  • the conductor 242c functions as one of the wirings BLa[1] to BLa[n] in the memory layer ALYa.
  • FIG. 25A to 25D are a schematic plan view and a schematic cross-sectional view of a memory cell MC having a transistor M1 and a capacitor C1 in the semiconductor device DEV of FIG. 22.
  • FIG. FIG. 25A is a schematic plan view of the memory cell MC.
  • 25B to 25D are schematic cross-sectional views of the memory cell MC.
  • FIG. 25B is a cross-sectional view taken along the dashed-dotted line A1-A2 shown in FIG. 25A, and is also a cross-sectional view in the channel length direction of the transistor M1.
  • FIG. 25C is a schematic cross-sectional view of the portion of the dashed-dotted line A3-A4 shown in FIG.
  • FIG. 25A is also a schematic cross-sectional view of the transistor M1 in the channel width direction.
  • FIG. 25D is a cross-sectional view taken along dashed-dotted line A5-A6 shown in FIG. 25A, and is also a schematic cross-sectional view of the capacitor C1. Note that some elements are omitted in the top view of FIG. 25A for clarity of illustration.
  • the memory cell MC has an insulator 280_1, an insulator 153_1, an insulator 154_1, and a conductor 160_1 (a conductor 160a_1 and a conductor 160b_1) over a substrate (not shown).
  • the memory cell MC also has an insulator 222_1 over the insulator 280_1, the insulator 153_1, the insulator 154_1, and the conductor 160_1.
  • the memory cell MC includes an insulator 224, an oxide 230a over the insulator 224, and an oxide 230b over the oxide 230a in a region over the insulator 222_1 that overlaps with the conductor 160_1. .
  • the memory cell MC also includes a conductor 242a (a conductor 242a1 and a conductor 242a2) and a conductor 242b (a conductor 242b1 and a conductor 242b2) over the oxide 230b.
  • a conductor 242a a conductor 242a1 and a conductor 242a2
  • a conductor 242b a conductor 242b1 and a conductor 242b2
  • an insulator 275 over the insulator 222_1, the side surface of the insulator 224, the side surface of the oxide 230, the side surface of the conductor 242a, and the conductor 242b, and the insulator 275 and a body 280_2.
  • the memory cell MC includes the insulator 253 located over the oxide 230b in a region overlapping with the conductor 160_1, the insulator 254 over the insulator 253, and the conductor 260 over the insulator 254 (the conductors 260a and 260a). It has a conductor 260b).
  • the memory cell MC includes an insulator 153_2 located in a region on the conductor 242b that does not overlap with the conductor 160_1, an insulator 154_2 on the insulator 153_2, and a conductor 160_2 on the insulator 154_2 (conductor 160a_2). and a conductor 160b_2).
  • the memory cell MC also has an insulator 222_2 over the insulator 280_2, the insulator 253, the insulator 254, the conductor 260, the insulator 153_2, the insulator 154_2, and the conductor 160_2.
  • transistor M1 and capacitor C1 are disposed embedded in insulator 280_2.
  • the conductors 242a and 242b are also provided over the side surfaces of the insulator 224, the oxide 230a, and the oxide 230. may Similarly, the conductor 242a and the conductor 242b may be provided over the insulator 222_1.
  • the sides of the oxide 230a, the sides of the oxide 230, and the insulator 222_1 are provided.
  • the conductors 242a and 242b provided over the side surface, the side surface of the oxide 230, and the insulator 222_1 are wirings electrically connected to one of the source electrode and the drain electrode of the transistor M1. can be done. Further, in this case, the wiring functions as a bit line.
  • each A indicates a schematic plan view.
  • B in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A1-A2 shown in each A, and is also a schematic cross-sectional view in the channel length direction of the transistor M1.
  • C in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A3-A4 shown in each A, and is also a schematic cross-sectional view in the channel width direction of the transistor M1.
  • D in each figure is a schematic cross-sectional view of the portion of the dashed-dotted line A5-A6 shown in each A. As shown in FIG. In the schematic plan view of A in each figure, some elements are omitted for clarity of the drawing.
  • the description may be omitted with respect to the part that overlaps with the manufacturing method of the memory cell of the semiconductor device DEV in FIG.
  • the method for manufacturing the memory cell of the semiconductor device DEV in FIG. 22 can use the method for manufacturing the memory cell in the semiconductor device DEV in FIG.
  • a substrate (not shown) is prepared, and an insulator 280_1, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are formed over the substrate (see FIGS. 26A to 26D).
  • 7A to 7D can be referred to for the method for forming the insulator 280_1, the insulator 153_1, the insulator 154_1, and the conductor 160_1.
  • an insulator 222_1 is formed over the insulator 280_1, the insulator 153_1, the insulator 154_1, and the conductor 160_1 (see FIGS. 26A to 26D). Note that the description of FIGS. 7A to 7D can be referred to for the method for forming the insulator 222_1.
  • an insulating layer 224A, an oxide layer 230A, and an oxide layer 230B are formed over the insulator 222_1 (see FIGS. 26A to 26D). Specifically, as described with reference to FIGS. 8A to 8D, an insulating film to be the insulating layer 224A, an oxide film to be the oxide layer 230A, and an oxide film to be the oxide layer 230B are formed in this order. As described with reference to 9A to 9D, the insulating film to be the insulating layer 224A, the oxide film to be the oxide layer 230A, and the oxide layer 230B may be processed by lithography or the like.
  • the insulating layer 224A, the oxide layer 230A, and the oxide layer 230B are also formed in a region where the capacitor C1 is formed later, for example, a region that does not overlap with the conductor 160_1.
  • 9A to 9D in that the formation method is different from that shown in FIGS.
  • a conductive film 242Af and a conductive film 242Bf are formed in this order over the insulator 222_1 and the oxide layer 230B (see FIGS. 27A to 27D). Note that the description in FIGS. 10A to 10D can be referred to for the method for forming the conductive films 242Af and 242Bf.
  • the insulating layer 224A, the oxide layer 230A, the oxide layer 230B, the conductive film 242Af, and the conductive film 242Bf are processed by a lithography method to form an island-shaped insulator 224, an oxide layer 230a, and an oxide layer 230B.
  • 230b, conductive layer 242A, and conductive layer 242B are formed (see FIGS. 28A-28D).
  • the description in FIGS. 11A to 11D can be referred to.
  • conductive layers 242A and 242B are formed over the insulator 222_1, the side surface of the insulator 224, the side surface of the oxide 230a, and the side surface of the oxide 230b. Processing may be performed so as to form The conductive layers 242A and 242B formed over the insulator 222_1, the side surface of the insulator 224, the side surface of the oxide 230a, and the side surface of the oxide 230b function as wirings, for example.
  • the insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242A, and the conductive layer 242B, and an insulating film to be the insulator 280_2 is formed over the insulator 275. form a film.
  • planarization treatment such as CMP is performed on the insulating film to be the insulator 280_2 to form the insulator 280_2 with a flat top surface (see FIGS. 29A to 29D). Note that the description of FIGS. 12A to 12D can be referred to for the method for forming the insulator 275 and the insulator 280_2.
  • opening 258 is formed that reaches object 230b.
  • the formation of openings 258 allows conductors 242a1 and 242b1 to be formed from conductive layer 242A and conductors 242a2 and 242b2 to be formed from conductive layer 242B (see FIGS. 30A-30D). Note that the method for forming the opening 258 can be referred to the description in FIGS. 13A to 13D.
  • part of the insulator 280_2 and part of the insulator 275 are processed in a region where the conductive layer 242A, the conductive layer 242B, and the insulator 222_1 overlap and the conductor 160_1 and the oxide 230 do not overlap.
  • An opening 158 is formed that reaches the conductive layer 242B (conductor 242b2) (see FIGS. 30A to 30D). Note that the method for forming the opening 158 can refer to the description in FIGS. 13A to 13D.
  • openings 158 and 258 may be formed together, or one of the openings 158 and 258 may be formed first and then the other. It should be noted that opening 258 is preferably formed to expose oxide 230b at the bottom of opening 258, and opening 158 is preferably formed to expose conductor 242b2 at the bottom of opening 158. FIG. For this reason, it is preferable to use processing methods with mutually different conditions for forming the openings 158 and 258 .
  • an insulating film to be the insulator 253 is formed over the insulator 280_2, the bottom surface and side surfaces of the opening 258, and the bottom surface and side surfaces of the opening 158. Further, microwave treatment may be performed after the insulating film to be the insulator 253 is formed. After that, an insulating film to be the insulator 254 and conductive films to be the conductors 260 and 160_2 are formed in this order over the insulating film to be the insulator 253 .
  • planarization treatment such as CMP is performed to planarize the insulating film to be the insulator 253, the insulating film to be the insulator 254, the conductors 260 and 160_2. Polishing is performed until the conductive film to be 160_2 is exposed. That is, portions of the insulating film to be the insulator 253, the insulating film to be the insulator 254, and the conductive films to be the conductors 260 and 160_2 exposed from the openings 258 and 158 are removed.
  • a body 160_2 (a conductor 160a_2 and a conductor 160b_2) is formed (see FIGS. 31A to 31D).
  • the conductor 260, the insulator 153_2, the insulator 154_2, and the conductor 160_2 the description with reference to FIGS. 14A to 16D can be referred to.
  • an insulator 222_2 is formed over the insulator 253, the insulator 254, the conductor 260, the insulator 153_2, the insulator 154_2, the conductor 160_2, and the insulator 280_2 (see FIGS. 25A to 25C). See Figure 25D). Note that for the method for forming the insulator 222_2, the description of the method for forming the insulator 222_2, which is given after FIGS. 16A to 16D, can be referred to.
  • a semiconductor device having the memory cell MCa or the memory cell MCb shown in FIG. 22 can be manufactured.
  • the capacitor C1 and the transistor M1 can be manufactured in the same step. Accordingly, the manufacturing steps of the semiconductor device having the capacitor C1 and the transistor M1 can be reduced.
  • the semiconductor device having the memory cell MCa or the memory cell MCb illustrated in FIG. 22 can reduce the area occupied by the memory cells. That is, the recording density of the semiconductor device can be increased.
  • the method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the methods illustrated in FIGS. 26A to 31D. In the method for manufacturing a semiconductor device, materials and steps may be changed according to circumstances.
  • an opening 258 is first formed, similarly to FIGS.
  • An insulator 253, an insulator 254, and a conductor 260 (a conductor 260a and a conductor 260b) are formed in the opening 258, and then the opening 158 is formed, and the insulator 153_2 and the insulator 153_2 are formed in the opening 158.
  • 154_2, and a conductor 160_2 (a conductor 160a_2 and a conductor 160b_2) may be formed.
  • the opening 258 is formed, and the insulator 253 , the insulator 254 , and the conductor 260 (the conductor 260 a and the conductor 260 b ) are formed in the opening 258 .
  • FIG. 32A shows a schematic perspective view showing a configuration example of the storage device 100.
  • FIG. FIG. 32B shows a block diagram showing a configuration example of the storage device 100.
  • the memory device 100 has a drive circuit layer 50 and memory layers 60 of N layers (N is an integer equal to or greater than 1).
  • One memory layer 60 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns. Note that in FIG. 32B, memory cell 10[1,1], memory cell 10[m,1] (here, m is an integer equal to or greater than 1), and memory cell 10[1,n] are shown in memory layer 60_k.
  • memory cell 10 [m, n] memory cell 10 [i, j] (where i is an integer of 1 or more and m or less, and j is An integer of 1 or more and n or less) is arranged.
  • the memory layer 60 corresponds to the memory layer ALYa or the memory layer ALYb described in the first embodiment. Also, the memory cell 10 corresponds to the memory cell MCa or the memory cell MCb described in the first embodiment.
  • the N memory layers 60 are provided on the drive circuit layer 50 .
  • the area occupied by the memory device 100 can be reduced. Also, the storage capacity per unit area can be increased.
  • the first memory layer 60 is indicated as a memory layer 60_1, the second memory layer 60 is indicated as a memory layer 60_2, and the third memory layer 60 is indicated as a memory layer 60_3.
  • the k-th (k is an integer of 1 or more and N or less) memory layer 60 is indicated as memory layer 60_k
  • the N-th memory layer 60 is indicated as memory layer 60_N.
  • the term "storage layer 60" is simply used. sometimes.
  • the drive circuit layer 50 has a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31 .
  • the peripheral circuit 31 has a peripheral circuit 41 , a control circuit 32 and a voltage generation circuit 33 .
  • each circuit, each signal, and each voltage can be appropriately discarded as needed. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • the signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • the signal WDA is write data and the signal RDA is read data.
  • the signal PON1 and the signal PON2 are power gating control signals.
  • the signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 100 .
  • the control circuit logically operates the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, write operation and read operation) of the storage device 100 .
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33 . For example, when an H level signal is applied to signal WAKE, signal CLK is input to voltage generation circuit 33, and voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing data to and reading data from the memory cell 10 .
  • the peripheral circuit 41 has a row decoder 42 , a column decoder 44 , a row driver 43 , a column driver 45 , an input circuit 47 , an output circuit 48 and a sense amplifier 46 .
  • Row decoder 42 and column decoder 44 have the function of decoding the signal ADDR.
  • Row decoder 42 is a circuit for specifying a row to be accessed
  • column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL (write and read word lines) specified by the row decoder 42 .
  • the column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, and a function of holding the read data.
  • the column driver 45 has a function of selecting the wiring BL (write and read bit lines) specified by the column decoder 44 .
  • the input circuit 47 has a function of holding the signal WDA.
  • Data held by the input circuit 47 (referred to as first data in the above embodiment) is output to the column driver 45 .
  • Output data of the input circuit 47 is data (Din) to be written to the memory cell 10 .
  • Data (Dout) read from the memory cells 10 by the column driver 45 is output to the output circuit 48 .
  • the read data (Dout) is treated as the data of the calculation result.
  • the output circuit 48 has a function of holding Dout. Also, the output circuit 48 has a function of outputting Dout to the outside of the storage device 100 . Data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has the function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW 23 has the function of controlling the supply of VHM to row driver 43 .
  • the high power supply voltage of the memory device 100 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to drive word lines to a high level and is higher than VDD.
  • the signal PON1 switches the PSW 22 between the ON state and the OFF state
  • the signal PON2 switches the PSW 23 between the ON state and the OFF state.
  • the number of power supply domains to which VDD is supplied is set to one, but it can be set to a plurality. In this case, a power switch may be provided for each power domain.
  • FIG. 33 is a block diagram showing a configuration example of the peripheral circuit 41 and the memory layer 60_k.
  • the row decoder 42 and the row driver 43 are electrically connected to the wirings WL[1] to WL[m], respectively, and the column decoder 44, the column driver 45, and the sense amplifier 46 are connected to the wirings BL[1]. 1] to the wiring BL[n].
  • the wirings WL[1] to WL[m] correspond to the wirings WLa[1] to WLa[m] or the wirings WLb[1] to WLb[m] described in Embodiment 1. is. In other words, the wirings WL[1] to WL[m] function as word lines.
  • the wirings BL[1] to BL[n] correspond to the wirings BLa[1] to BLa[n] or the wirings BLb[1] to BLb[n] described in Embodiment 1. is. In other words, the wirings BL[1] to BL[n] function as bit lines.
  • the memory cell 10[i,j] arranged in the i-th row and the j-th column is electrically connected to the wiring WL[i] and the wiring BL[j].
  • FIG. 34 shows a cross-sectional configuration example of the storage device 100 according to one embodiment of the present invention.
  • the memory device 100 shown in FIG. 34 has a plurality of memory layers 60 (memory layers ALYa or memory layers ALYb) above the drive circuit layer 50 .
  • memory layers ALYa or memory layers ALYb memory layers ALYa or memory layers ALYb
  • the description of the memory layer 60 in this embodiment is omitted.
  • FIG. 34 illustrates the transistor 400 included in the driver circuit layer 50 .
  • the transistor 400 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and one of a source region and a drain region. and a low resistance region 314b functioning as the other of the source and drain regions.
  • Transistor 400 can be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 for example, a single crystal silicon substrate can be used.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductor 316 is provided so as to cover side surfaces and a top surface of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 400 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate.
  • an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion.
  • a semiconductor film having a convex shape may be formed by processing an SOI (Silicon On Insulator) substrate.
  • transistor 400 illustrated in FIG. 34 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer provided with an interlayer film, a wiring, and a plug may be provided between each structure.
  • the wiring layer can be provided in a plurality of layers depending on the design.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as wiring, and part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as interlayer films.
  • a conductor 328 or the like is embedded in the insulators 320 and 322 .
  • a conductor 330 or the like is embedded in the insulators 324 and 326 . Note that the conductor 328 and the conductor 330 function as contact plugs or wirings.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder.
  • the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330 .
  • an insulator 350 , an insulator 357 , and an insulator 352 are stacked in this order over the insulator 326 and the conductor 330 .
  • a conductor 356 is formed over the insulators 350 , 357 , and 352 .
  • Conductors 356 function as contact plugs or interconnects.
  • Transistor 400 is electrically connected through conductor 356, conductor 330, and the like.
  • This embodiment mode shows an example of a semiconductor wafer on which the memory device and the like described in the above embodiment are formed, and an electronic component in which the memory device is incorporated.
  • a semiconductor wafer 4800 shown in FIG. 35A has a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is the area for dicing.
  • a semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of a wafer 4801 through a pre-process. After that, the wafer 4801 may be thinned by grinding the opposite surface of the wafer 4801 on which the plurality of circuit portions 4802 are formed. By this process, warping of the wafer 4801 can be reduced, and miniaturization as a component can be achieved.
  • the next step is the dicing process. Dicing is performed along a scribe line SCL1 and a scribe line SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines.
  • the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel, and a plurality of scribe lines SCL2 are provided so that the scribe lines SCL1 and SCL2 are parallel. It is preferable to provide it vertically.
  • a chip 4800a as shown in FIG. 35B can be cut out from the semiconductor wafer 4800 by performing the dicing process.
  • the chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of the spacing 4803 between the adjacent circuit portions 4802 is substantially equal to the width of the scribe line SCL1 or the width of the scribe line SCL2.
  • the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 35A.
  • the shape of the element substrate can be appropriately changed according to the manufacturing process of the element and the device for manufacturing the element.
  • FIG. 35C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted.
  • Electronic component 4700 shown in FIG. 35C has chip 4800 a in mold 4711 .
  • the chip 4800a shown in FIG. 35C has a structure in which the circuit section 4802 is stacked. That is, the memory device described in the above embodiment can be applied to the circuit portion 4802 .
  • FIG. 35C is partially omitted to show the inside of electronic component 4700 .
  • Electronic component 4700 has lands 4712 outside mold 4711 . Land 4712 is electrically connected to electrode pad 4713 , and electrode pad 4713 is electrically connected to chip 4800 a by wire 4714 .
  • Electronic component 4700 is mounted on printed circuit board 4702, for example.
  • a mounting board 4704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 4702 .
  • FIG. 35D A perspective view of the electronic component 4730 is shown in FIG. 35D.
  • Electronic component 4730 is an example of SiP (System in Package) or MCM (Multi Chip Module).
  • An electronic component 4730 includes an interposer 4731 provided over a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 provided over the interposer 4731 .
  • the electronic component 4730 has a semiconductor device 4710 .
  • the semiconductor device 4710 can be, for example, the memory device described in any of the above embodiments, a high bandwidth memory (HBM), or the like.
  • HBM high bandwidth memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or memory device can be used, for example.
  • a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 4732 .
  • a silicon interposer or a resin interposer can be used for the interposer 4731 .
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers. In addition, the interposer 4731 has a function of electrically connecting the integrated circuit provided over the interposer 4731 to electrodes provided over the package substrate 4732 . For these reasons, the interposer is sometimes called a "rewiring board” or an "intermediate board". In some cases, through electrodes are provided in the interposer 4731 and the integrated circuit and the package substrate 4732 are electrically connected using the through electrodes. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as a through electrode.
  • TSV Three Silicon Via
  • a silicon interposer is preferably used as the interposer 4731 . Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
  • HBM In HBM, it is necessary to connect many wires in order to achieve a wide memory bandwidth. Therefore, an interposer for mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the HBM.
  • SiPs or MCMs using a silicon interposer are unlikely to suffer a decrease in reliability due to the difference in coefficient of expansion between the integrated circuit and the interposer.
  • the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur.
  • a 2.5D package 2.5-dimensional packaging in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided overlapping with the electronic component 4730 .
  • a heat sink it is preferable that the heights of the integrated circuits provided over the interposer 4731 be uniform.
  • the semiconductor device 4710 and the semiconductor device 4735 have the same height.
  • Electrodes 4733 may be provided on the bottom of the package substrate 4732 in order to mount the electronic component 4730 on another substrate.
  • FIG. 35D shows an example of forming the electrodes 4733 with solder balls.
  • BGA All Grid Array
  • the electrodes 4733 may be formed of conductive pins.
  • PGA Peripheral Component Interconnect
  • the electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN Quad Flat Non-leaded package
  • FIG. 36 is a block diagram showing an example configuration of a CPU partially using the storage device described in the above embodiments.
  • the CPU shown in FIG. (Bus I/F), rewritable ROM 1199, and ROM interface 1189 (ROM I/F).
  • a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190 .
  • the ROM 1199 and ROM interface 1189 may be provided on separate chips.
  • the CPU shown in FIG. 36 is merely an example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their uses.
  • a configuration including a CPU or an arithmetic circuit shown in FIG. 36 may be used as one core, a plurality of such cores may be included, and the cores may operate in parallel, that is, a configuration like a GPU.
  • the number of bits that the CPU can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits or more.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
  • the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on decoded instructions. Specifically, ALU controller 1192 generates signals for controlling the operation of ALU 1191 . In addition, the interrupt controller 1194 judges and processes an interrupt request from an external input/output device or a peripheral circuit from its priority or mask state while the CPU is executing a program. A register controller 1197 generates an address for the register 1196 and reads or writes the register 1196 according to the state of the CPU.
  • the timing controller 1195 generates signals for controlling the timing of the operations of the ALU 1191 , ALU controller 1192 , instruction decoder 1193 , interrupt controller 1194 and register controller 1197 .
  • the timing controller 1195 has an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register 1196 is provided with memory cells.
  • the register 1196 may have, for example, the storage devices described in the previous embodiments.
  • the register controller 1197 selects the holding operation in the register 1196 according to instructions from the ALU 1191 . That is, in the memory cells included in the register 1196, it is selected whether data is held by a flip-flop or a capacitor. When data holding by the flip-flop is selected, power supply voltage is supplied to the memory cells in the register 1196 . When data retention in the capacitor is selected, data is rewritten in the capacitor, and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
  • An information terminal 5500 shown in FIG. 37A is a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • the display portion 5511 is provided with a touch panel, and the housing 5510 is provided with buttons.
  • the information terminal 5500 can hold temporary files generated when an application is executed (for example, a cache when using a web browser).
  • FIG. 37B illustrates an information terminal 5900 that is an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, operation buttons 5903, a crown 5904, and a band 5905, for example.
  • the wearable terminal like the information terminal 5500 described above, can hold temporary files generated when an application is executed by applying the storage device described in the above embodiment.
  • a desktop information terminal 5300 is also illustrated in FIG. 37C.
  • the desktop information terminal 5300 has an information terminal main body 5301 , a display 5302 and a keyboard 5303 .
  • the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying the storage device described in the above embodiment.
  • smartphones, wearable terminals, and desktop information terminals are illustrated as examples of electronic devices in FIGS. 37A to 37C, respectively. can.
  • Examples of information terminals other than smart phones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), laptop information terminals, and workstations.
  • FIG. 37D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance.
  • the electric refrigerator-freezer 5800 has, for example, a housing 5801 , a refrigerator compartment door 5802 and a freezer compartment door 5803 .
  • the electric refrigerator-freezer 5800 can be used as, for example, IoT (Internet of Things).
  • IoT Internet of Things
  • the electric freezer-refrigerator 5800 can transmit and receive information such as the foodstuffs stored in the electric freezer-refrigerator 5800 and the expiration date of the foodstuffs to and from the above-described information terminal or the like via the Internet or the like. can.
  • the electric refrigerator-freezer 5800 can hold the information as a temporary file in the storage device.
  • an electric refrigerator/freezer was explained as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment, etc.
  • FIG. 37E also shows a portable game machine 5200, which is an example of a game machine.
  • a portable game machine 5200 includes a housing 5201, a display portion 5202, and buttons 5203, for example.
  • FIG. 37F illustrates a stationary game machine 7500, which is an example of a game machine.
  • a stationary game machine 7500 has a main body 7520 and a controller 7522 .
  • a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 includes one or more selected from a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, and a sliding knob. can be provided.
  • the shape of the controller 7522 is not limited to that shown in FIG. 37F, and the shape of the controller 7522 may be changed variously according to the genre of the game.
  • a button can be used as a trigger and a controller shaped like a gun can be used.
  • a controller shaped like a musical instrument, music equipment, or the like can be used.
  • the stationary game machine may not use a controller, but may instead include a camera, depth sensor, microphone, etc., and may be operated by the game player's gestures and/or voice.
  • the video of the game machine described above can be output by a display device provided in a television device, a personal computer display, a game display, or a head-mounted display.
  • the portable game machine 5200 with low power consumption can be realized.
  • the low power consumption can reduce the heat generated from the circuit, so that the influence of the heat on the circuit itself, the peripheral circuits, and the module can be reduced.
  • FIGS. 37E and 37F illustrate a portable game machine and a stationary game machine as examples of game machines
  • the electronic device of one embodiment of the present invention is not limited to these.
  • Examples of electronic devices of one embodiment of the present invention include arcade game machines installed in amusement facilities (for example, game centers and amusement parks) and pitching machines for batting practice installed in sports facilities.
  • the storage devices described in the above embodiments can be applied to automobiles, which are moving bodies, and to the vicinity of the driver's seat of automobiles.
  • FIG. 37G An automobile 5700, which is an example of a mobile object, is illustrated in FIG. 37G.
  • an instrument panel that displays various information such as speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioner settings. Further, a display device for displaying such information may be provided around the driver's seat.
  • the display device can compensate for the blind spots in the driver's seat and the visibility blocked by pillars, etc., and enhance safety. be able to.
  • the storage device described in the above embodiment can temporarily hold information
  • the storage device can be used for an automatic driving system of the automobile 5700, and the storage device can be used for road guidance, danger prediction, etc. can be used to hold necessary temporary information in
  • the display device may be configured to display temporary information such as road guidance and danger prediction. Also, a configuration may be adopted in which the image of the driving recorder installed in the automobile 5700 is held.
  • moving objects may include trains, monorails, ships, flying objects (eg, helicopters, unmanned aerial vehicles (drone), airplanes, or rockets), and the like.
  • FIG. 37H illustrates a digital camera 6240 as an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, and a shutter button 6244, and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated.
  • the digital camera 6240 may have a configuration in which a strobe device or a viewfinder can be attached separately.
  • the digital camera 6240 with low power consumption can be realized.
  • the low power consumption can reduce the heat generated from the circuit, so that the influence of the heat on the circuit itself, the peripheral circuits, and the module can be reduced.
  • Video camera The storage devices described in the above embodiments can be applied to video cameras.
  • FIG. 37I illustrates a video camera 6300 as an example of an imaging device.
  • a video camera 6300 has a first housing 6301 , a second housing 6302 , a display portion 6303 , operation keys 6304 , a lens 6305 , and a connection portion 6306 .
  • the operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display portion 6303 is provided on the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306 .
  • the video camera 6300 can hold temporary files generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 37J is a cross-sectional schematic diagram showing an example of an ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. make it
  • the ICD main body 5400 has a function as a pacemaker, and paces the heart when the heart rate deviates from the specified range. Also, if pacing does not improve heart rate (eg, rapid ventricular tachycardia or ventricular fibrillation), treatment with electric shocks is given.
  • heart rate eg, rapid ventricular tachycardia or ventricular fibrillation
  • the ICD main body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting heart rate. In addition, the ICD main body 5400 can store heart rate data acquired by the sensor or the like, the number of pacing treatments, time, and the like in the electronic component 4700 .
  • the ICD main body 5400 having a plurality of batteries can enhance safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the rest of the batteries can still function, so the ICD also functions as an auxiliary power source.
  • an antenna capable of transmitting physiological signals may be provided.
  • a system may be configured to monitor various cardiac activity.
  • the storage devices described in the above embodiments can be applied to electronic devices for XR (Extended Reality or Cross Reality) such as AR (Augmented Reality) and VR (Virtual Reality).
  • XR Extended Reality or Cross Reality
  • AR Augmented Reality
  • VR Virtual Reality
  • FIGS. 38A to 38C are diagrams showing the appearance of an electronic device 8300 that is a head mounted display.
  • An electronic device 8300 illustrated in FIGS. 38A to 38C includes a housing 8301, a display portion 8302, a band-like fixture 8304, a fixture 8304a attached to the head, and a pair of lenses 8305.
  • FIG. Note that the electronic device 8300 may be provided with operation buttons.
  • the user can visually recognize the display on the display unit 8302 through the lens 8305 .
  • the display portion 8302 it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high presence.
  • three-dimensional display or the like using parallax can be performed.
  • the configuration is not limited to the configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided and one display portion may be arranged for one eye of the user.
  • the display unit 8302 for example, it is preferable to use a display device with extremely high definition. By using a high-definition display device for the display portion 8302, even if the image is enlarged using the lens 8305 as shown in FIG. be able to.
  • the head-mounted display which is an electronic device of one embodiment of the present invention, may have the structure of an electronic device 8200 that is a glass-type head-mounted display illustrated in FIG. 38D.
  • the electronic device 8200 has a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205.
  • a battery 8206 is built in the mounting portion 8201 .
  • a cable 8205 supplies power from a battery 8206 to the main body 8203 .
  • a main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204 .
  • the main body 8203 is equipped with a camera, and information on the movement of the user's eyeballs or eyelids can be used as input means.
  • the mounting section 8201 may be provided with a plurality of electrodes capable of detecting a current flowing along with the movement of the user's eyeballs at a position where it touches the user, and may have a function of recognizing the line of sight. Moreover, it may have a function of monitoring the user's pulse based on the current flowing through the electrode.
  • the mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, or an acceleration sensor.
  • a function of changing an image displayed on the display portion 8204 may be provided.
  • Extension device for PC The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.
  • FIG. 39A shows an expansion device 6100 externally attached to a PC, mounted with a portable chip capable of storing information, as an example of the expansion device.
  • the expansion device 6100 can store information by the chip, for example, by connecting to a PC via a USB (Universal Serial Bus) or the like.
  • FIG. 39A illustrates the expansion device 6100 in a portable form, the expansion device according to one aspect of the present invention is not limited to this. It may also be an expansion device in a larger form.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104.
  • a substrate 6104 is housed in a housing 6101 .
  • a substrate 6104 is provided with a circuit for driving the memory device or the like described in the above embodiment mode.
  • substrate 6104 has electronic components 4700 and controller chip 6106 mounted thereon.
  • a USB connector 6103 functions as an interface for connecting with an external device.
  • SD card The storage devices described in the above embodiments can be applied to SD cards that can be attached to electronic devices such as information terminals and digital cameras.
  • FIG. 39B is a schematic diagram of the appearance of the SD card
  • FIG. 39C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111 , a connector 5112 and a substrate 5113 .
  • a connector 5112 functions as an interface for connecting with an external device.
  • a substrate 5113 is housed in a housing 5111 .
  • a substrate 5113 is provided with a memory device and a circuit for driving the memory device.
  • an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113 .
  • the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation.
  • a write circuit, a row driver, a read circuit, and the like included in electronic components may be incorporated in the controller chip 5115 instead of the electronic component 4700 .
  • the capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113 (the side opposite to the side on which the storage device and the circuit for driving the storage device are provided).
  • a wireless chip having a wireless communication function may be provided over the substrate 5113 .
  • wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 4700.
  • SSD Solid State Drives
  • electronic devices such as information terminals.
  • FIG. 39D is a schematic diagram of the appearance of the SSD
  • FIG. 39E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151 , a connector 5152 and a substrate 5153 .
  • a connector 5152 functions as an interface for connecting with an external device.
  • a substrate 5153 is housed in a housing 5151 .
  • a substrate 5153 is provided with a memory device and a circuit for driving the memory device.
  • substrate 5153 has electronic component 4700, memory chip 5155, and controller chip 5156 mounted thereon.
  • the capacity of the SSD 5150 can be increased by providing the electronic component 4700 also on the back side of the substrate 5153 (the side opposite to the side on which the memory device and the circuit for driving the memory device are provided).
  • the memory chip 5155 incorporates a work memory.
  • the memory chip 5155 may be a DRAM chip.
  • the controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances.
  • the controller chip 5156 may also be provided with a memory functioning as a work memory.
  • a novel electronic device can be provided by applying the storage device of the above-described embodiment to the storage device included in the above-described electronic device.

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  • Thin Film Transistor (AREA)
PCT/IB2023/051188 2022-02-25 2023-02-10 半導体装置、記憶装置、及び電子機器 Ceased WO2023161754A1 (ja)

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US18/838,504 US20250159869A1 (en) 2022-02-25 2023-02-10 Semiconductor device, memory device, and electronic device
KR1020247026531A KR20240155858A (ko) 2022-02-25 2023-02-10 반도체 장치, 기억 장치, 및 전자 기기

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JP2018195814A (ja) * 2017-05-12 2018-12-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019029666A (ja) * 2017-07-26 2019-02-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2021009589A1 (ja) * 2019-07-12 2021-01-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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US9177872B2 (en) 2011-09-16 2015-11-03 Micron Technology, Inc. Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
US9634097B2 (en) 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel

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JP2018195814A (ja) * 2017-05-12 2018-12-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019029666A (ja) * 2017-07-26 2019-02-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2021009589A1 (ja) * 2019-07-12 2021-01-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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US20250159869A1 (en) 2025-05-15

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