WO2023157794A1 - 配線回路基板およびその製造方法 - Google Patents

配線回路基板およびその製造方法 Download PDF

Info

Publication number
WO2023157794A1
WO2023157794A1 PCT/JP2023/004740 JP2023004740W WO2023157794A1 WO 2023157794 A1 WO2023157794 A1 WO 2023157794A1 JP 2023004740 W JP2023004740 W JP 2023004740W WO 2023157794 A1 WO2023157794 A1 WO 2023157794A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
metal support
layer
coating layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/004740
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
裕紀 ▲桑▼山
淳 石井
恭也 大薮
真樹 鎌倉
将行 程野
直史 重良
知起 阿曽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to CN202380022364.7A priority Critical patent/CN118715877A/zh
Priority to JP2024501361A priority patent/JPWO2023157794A1/ja
Priority to KR1020247031054A priority patent/KR20240147693A/ko
Publication of WO2023157794A1 publication Critical patent/WO2023157794A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

Definitions

  • the present invention relates to a printed circuit board and its manufacturing method.
  • wired circuit boards are used to transmit and receive electrical signals between multiple electronic components.
  • Electronic components such as semiconductor chips are connected to the printed circuit board.
  • a printed circuit board including a metal substrate has been proposed.
  • a wiring board (wiring circuit board) described in Patent Document 1 includes a core substrate.
  • the core substrate is made of aluminum, for example, and has through vias.
  • the upper and lower surfaces of the core substrate and the inner peripheral surfaces of the through vias are covered with an insulating layer.
  • the insulating layer is formed by an anodizing treatment using an organic acid.
  • a wiring layer is provided on each of the upper and lower surfaces of the core substrate with an insulating layer interposed therebetween.
  • a conductor layer is provided inside the through via of the core substrate with an insulating layer interposed therebetween. JP 2004-179291 A
  • a conductor layer is formed so as to cover the inner peripheral surface of the insulating layer. Therefore, a through hole is formed from the upper surface to the lower surface of the core substrate at the center of the through via. In such a configuration, it is difficult to overlap a through via of another wiring board on the through via and to form a terminal for mounting an electronic component on the through via.
  • Via-fill plating uses a special plating bath or the like that is different from normal plating. Therefore, it is necessary to newly prepare an apparatus for performing via-fill plating. Therefore, manufacturing a wiring board using such via-fill plating is not as easy as manufacturing a wiring board using normal plating.
  • An object of the present invention is to provide a wired circuit board which is easy to manufacture and has improved reliability of electrical continuity, and a method of manufacturing the same.
  • a printed circuit board comprises a metal support having a first surface and a second surface facing opposite to each other and having a via hole penetrating from the first surface to the second surface; an insulating coating layer formed to cover at least a partial region of the first surface and the second surface of the metal support and to cover the inner peripheral surface of the via hole; a first conductor layer to be formed; a second conductor layer to be formed on the second surface of the metal support; made of the same metal as the metal support; and a via conductor formed so as to electrically connect to and fill the internal space of the via hole via the insulating coating layer.
  • the metal support is formed, for example, by processing a metal plate. Therefore, it becomes possible to form part of the metal plate as a via conductor when forming the metal support.
  • the via conductor in the via hole is formed of a part of the metal plate, it is not necessary to form the via conductor in the via hole by plating or the like. Therefore, it is easy to form a via conductor in the via hole. Moreover, it is possible to prevent defects such as voids from occurring in the via conductors. As a result, it is possible to realize a printed circuit board which is easy to manufacture and has improved reliability of electrical continuity.
  • the insulating coating layer may be made of an organic insulating material.
  • the organic insulating material ensures insulation between the first conductor layer, the second conductor layer, the via conductors, and the metal support.
  • the insulating coating layer may be made of a photosensitive organic insulating material.
  • the photosensitive organic insulating material ensures insulation between the first conductor layer, the second conductor layer, the via conductors, and the metal support.
  • the insulating coating layer can be easily formed on the desired region of the surface of the metal support by using the photolithographic technique.
  • the coefficient of linear expansion of the metal support may be 0 ⁇ m/K or more and 25 ⁇ m/K or less. In this case, it is possible to prevent the metal support from greatly deforming due to a change in the temperature of the printed circuit board. This improves the reliability of the printed circuit board.
  • the insulating coating layer is formed so as to be in contact with the metal support, and the metal support may contain a component that improves the adhesion of the insulating coating layer to the metal support. In this case, peeling of the insulating coating layer from the surface of the metal support is suppressed. As a result, the insulation between the metal support, the first conductor layer, the second conductor layer and the via conductors is ensured, thereby improving the reliability of the printed circuit board.
  • the printed circuit board is formed between the metal support and the insulation coating layer so as to be in contact with the metal support and the insulation coating layer, and contains a component that improves the adhesion of the insulation coating layer to the metal support.
  • An adhesion-enhancing layer may be further provided.
  • the adhesion-enhancing layer may contain chromium or aluminum, and the content of chromium or aluminum in the adhesion-enhancing layer may be 50% by weight or less.
  • Chromium and aluminum have a lower thermal conductivity due to oxidation. According to the above configuration, compared with the case where the content of chromium or aluminum in the adhesion-enhancing layer is more than 50% by weight, deterioration in thermal conductivity due to oxidation of the adhesion-enhancing layer is reduced.
  • the first conductor layer is formed to be electrically connectable to the first electronic component arranged on the first surface, and the second conductor layer is arranged on the second surface. It may be formed to be electrically connectable to the second electronic component.
  • the wired circuit board can be used as a rewiring board.
  • the insulating coating layer includes a first surface covering portion covering the first surface of the metal support, and the first conductor layer includes a first connection conductor overlapping the via conductor in a plan view, a planar and a second connection conductor portion that does not overlap the via conductor in view, the first connection conductor portion being in direct contact with the via conductor and continuously extending from the via conductor in the direction in which the first surface faces.
  • the tip portion of the connecting conductor portion of is configured to be electrically connectable to one terminal of the electronic component arranged on the first surface, and the second connecting conductor portion is a portion of the first surface covering portion is formed on the first surface of the metal support via and extends continuously from a portion of the first surface covering portion in the direction in which the first surface faces; It is configured to be electrically connectable to another terminal of an electronic component arranged on one surface, and in the direction in which the first surface faces, the tip of the first connection conductor and the second connection conductor are separated from each other.
  • the distance between the tips may be 15 ⁇ m or less.
  • the electronic component can be mounted on the printed circuit board so as to be positioned on the first surface of the metal support. During mounting, one terminal of the electronic component is connected to the tip of the first connection conductor, and the other terminal of the electronic component is connected to the tip of the second connection conductor.
  • the electronic component may be mounted on the printed circuit board in an unintended orientation. . Moreover, it may become difficult to electrically connect a plurality of terminals of the electronic component to the first conductor layer of the printed circuit board.
  • the tip portion of the first connection conductor and the second 2 is 15 ⁇ m or less from the tip of the connection conductor. Therefore, compared to the case where the distance between the tip of the first connection conductor and the tip of the second connection conductor is larger than 15 ⁇ m, the electronic component is structurally stable on the printed circuit board. can be implemented. Moreover, in a state where the electronic component is mounted on the printed circuit board, the reliability of electrical continuity between the printed circuit board and the electronic component is improved.
  • the thickness of a portion of the first surface covering portion may be smaller than the thickness of the other portion of the first surface covering portion, or may be 15 ⁇ m or less.
  • the distance between the tip of the first connection conductor and the tip of the second connection conductor becomes 15 ⁇ m or less.
  • the thickness of the first connection conductor may be greater than the thickness of the second connection conductor.
  • the tip of the first connection conductor and the tip of the second connection conductor is 15 ⁇ m or less.
  • a method of manufacturing a printed circuit board includes the steps of preparing a metal plate having a first surface and a second surface facing opposite to each other; a step of forming a metal support by forming a via hole penetrating through the surface of the metal support; covering at least a part of the first surface and the second surface of the metal support and covering the inner peripheral surface of the via hole; forming an overlying insulating coating layer; forming a first conductor layer on the first side of the metal support; and forming a second conductor layer on the second side of the metal support.
  • forming the metal support includes removing a region surrounding the portion of the metal plate to make the portion of the metal plate a via conductor that fills the internal space of the via hole;
  • the step of forming one conductor layer includes forming a first conductor layer to be electrically connected to the via conductor, and the step of forming the second conductor layer is electrically connected to the via conductor. Forming a second conductor layer to be connected.
  • a via conductor made of a part of the metal plate is formed in the via hole so as not to come into contact with the inner peripheral surface of the via hole when forming the metal support.
  • the via conductor in the via hole is formed of a part of the metal plate, it is not necessary to form the via conductor in the via hole by plating or the like. Therefore, it is easy to form a via conductor in the via hole. Moreover, it is possible to prevent defects such as voids from occurring in the via conductors. As a result, it is possible to realize a printed circuit board which is easy to manufacture and has improved reliability of electrical continuity.
  • the step of forming the insulating coating layer includes forming the insulating coating layer so as to be in contact with the metal support, and the step of preparing the metal plate improves the adhesion of the insulating coating layer to the metal support. It may comprise providing a metal plate as the metal plate, which contains a component that causes the
  • the method for manufacturing a printed circuit board includes covering a predetermined insulating region of the first surface and the second surface of the metal support and covering the inner peripheral surface of the via hole before forming the insulating coating layer. forming an adhesion-enhancing layer so as to be in contact with the metal support, wherein the step of forming an insulating coating layer comprises insulating on the adhesion-enhancing layer so as to be in contact with the adhesion-enhancing layer; Including forming a coating layer, the adhesion-enhancing layer may contain a component that improves the adhesion of the insulating coating layer to the metal support.
  • the step of forming the insulating coating layer includes forming a first surface covering portion covering the first surface of the metal support, and the step of forming the first conductor layer includes forming a via in plan view. forming a first connection conductor portion that overlaps the conductor and a second connection conductor portion that does not overlap the via conductor in a plan view, the first connection conductor portion being in direct contact with the via conductor and the via conductor; extending continuously from the first surface in the direction in which the first surface faces, and the tip of the first connection conductor is configured to be electrically connectable to one terminal of the electronic component arranged on the first surface,
  • the second connection conductor is formed on the first surface of the metal support through a portion of the first surface covering portion and is continuous from the portion of the first surface covering portion in a direction toward the first surface.
  • the tip of the second connection conductor is configured to be electrically connectable to another terminal of the electronic component arranged on the first surface, and the second connection conductor extends in the direction in which the first surface faces.
  • the distance between the tip of one connection conductor and the tip of the second connection conductor may be 15 ⁇ m or less.
  • wired circuit board produced by the above manufacturing method electronic components can be mounted on the wired circuit board so as to be positioned on the first surface of the metal support. During mounting, one terminal of the electronic component is connected to the tip of the first connection conductor, and the other terminal of the electronic component is connected to the tip of the second connection conductor.
  • the electronic component may be mounted on the printed circuit board in an unintended orientation. . Moreover, it may become difficult to electrically connect a plurality of terminals of the electronic component to the first conductor layer of the printed circuit board.
  • the tip portion of the first connection conductor and the second 2 is 15 ⁇ m or less from the tip of the connection conductor. Therefore, compared to the case where the distance between the tip of the first connection conductor and the tip of the second connection conductor is larger than 15 ⁇ m, the electronic component is structurally stable on the printed circuit board. can be implemented. Moreover, in a state where the electronic component is mounted on the printed circuit board, the reliability of electrical continuity between the printed circuit board and the electronic component is improved.
  • FIG. 1 is a schematic cross-sectional view showing the configuration of a rewiring board according to one embodiment of the present invention.
  • 2 is a schematic plan view of the rewiring board of FIG. 1.
  • FIG. 3 is a schematic bottom view of the rewiring board of FIG. 1.
  • FIG. 4A and 4B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 5A and 5B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 6A to 6C are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG.
  • FIG. 7A to 7C are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG. 8A to 8D are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG. 9A and 9B are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG. 10A and 10B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 11A and 11B are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG.
  • FIG. 12A and 12B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 13A and 13B are schematic cross-sectional views for explaining a first example of the method for manufacturing the rewiring board of FIG. 14A and 14B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 15A and 15B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG. 16A and 16B are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring board of FIG.
  • FIG. 17A and 17B are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG. 18A and 18B are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG. 19A and 19B are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG. 20A to 20C are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG.
  • FIG. 21 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. 22A to 22C are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG.
  • FIG. 23A to 23C are schematic cross-sectional views for explaining a second example of the method for manufacturing the rewiring board of FIG.
  • FIG. 24 is a schematic cross-sectional view showing a first configuration example of a rewiring board in consideration of reduction of variations in height positions of a plurality of terminal portions.
  • 25 is a plan view showing the positional relationship among the first terminal portion, the first connection conductor portion, the second terminal portion, the second connection conductor portion, the metal support and the via conductors in FIG. 24.
  • FIG. FIG. 26 is a diagram showing an example of mounting a semiconductor element on the rewiring board of FIG. 27A to 27C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG.
  • 28A and 28B are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 29A and 29B are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 30A to 30C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 31A to 31C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 32A to 32C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 33A to 33C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG.
  • FIG. 34A and 34B are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG.
  • FIG. 35 is a schematic cross-sectional view showing a second configuration example of a rewiring board in which variations in height positions of a plurality of terminal portions are reduced.
  • FIG. 36 is a schematic cross-sectional view showing a third configuration example of a rewiring board in which variations in height positions of a plurality of terminal portions are reduced.
  • FIG. 37 is a schematic cross-sectional view showing a fourth configuration example of a rewiring board in which variations in height positions of a plurality of terminal portions are reduced.
  • FIG. 38 is a schematic cross-sectional view of a rewiring board provided with an adhesion enhancing layer.
  • a wired circuit board and a manufacturing method thereof according to an embodiment of the present invention will be described below with reference to the drawings.
  • a rewiring board will be described as an example of the wiring circuit board.
  • a rewiring board is arranged between an electronic component such as a semiconductor element and another wiring circuit board such as a rigid printed wiring circuit board (hereinafter abbreviated as a rigid board), and is used to connect fine patterns of the electronic component and other components. It plays a role of converting the pitch from the rough pattern of the wiring circuit board.
  • a rewiring board is also called an interposer board.
  • FIG. 1 is a schematic cross-sectional view showing the configuration of a rewiring board according to an embodiment of the present invention.
  • FIG. 2 is a schematic plan view of the rewiring board 100 of FIG.
  • FIG. 3 is a schematic bottom view of the rewiring board 100 of FIG.
  • FIG. 1 represents a cross section taken along line AA of FIGS. 2 and 3.
  • FIG. 1 the rewiring board 100 mainly comprises a metal support 10, insulating layers 20 and 30, and conductor layers 50 and 60, and has a thickness of 60 ⁇ m or more and 500 ⁇ m or less. Also, the rewiring board 100 is arranged between the semiconductor element 700 and the rigid board 800 .
  • the semiconductor element 700 has a plurality of electrode pads 71 and the rigid substrate 800 has a plurality of electrode pads 81 .
  • the semiconductor element 700 is indicated by a one-dot chain line
  • the rigid substrate 800 is indicated by a two-dot chain line.
  • the metal support 10 is, for example, a metal or alloy containing one or more elements selected from the group consisting of copper, aluminum, iron, nickel, chromium, titanium and molybdenum.
  • the metal support 10 is made of stainless steel and formed into a plate shape.
  • the surface of the metal support 10 facing the semiconductor element 700 (the surface facing upward in FIG. 1) is referred to as the upper surface 10a
  • the surface of the metal support 10 facing the rigid substrate 800 (the surface facing downward in FIG. 1) is referred to as the lower surface. 10b.
  • the upper surface 10a and the lower surface 10b according to the present embodiment are parallel to each other, perpendicular to the thickness direction of the metal support 10, and flat.
  • the direction in which the upper surface 10a of the metal support 10 faces is the upper side of the rewiring board 100
  • the direction in which the lower surface 10b of the metal support 10 faces is the lower side of the rewiring board 100.
  • the metal support 10 is not limited to the above examples, and 42 alloy, Invar alloy, or the like may be used.
  • an Invar alloy is used for the metal support 10
  • the coefficient of linear expansion of the metal support 10 can be adjusted according to changes in the composition of nickel (Ni) in the Invar alloy. In this case, it is possible to suppress the occurrence of warpage in each layer constituting the rewiring board 100 .
  • the metal support 10 preferably has a thermal conductivity higher than that of the insulating layers 20 and 30. For example, it has a thermal conductivity of 10 W/mK or more and 400 W/mK or less. . Moreover, the metal support 10 preferably has a thickness of 10 ⁇ m or more and 100 ⁇ m or less, and more preferably has a thickness of 20 ⁇ m or more and 50 ⁇ m or less. Furthermore, the linear expansion coefficient of the metal support 10 at 25° C. to 200° C. is 0 ⁇ m/K or more and 25 ⁇ m/K or less.
  • a plurality of via holes 19 are formed in the metal support 10 .
  • Each of the plurality of via holes 19 of the present example has a circular or rectangular opening when viewed from above in the thickness direction of the rewiring board 100 (vertical direction of the rewiring board 100).
  • the maximum dimension of the opening of each via hole 19 perpendicular to the thickness direction of the rewiring board 100 is, for example, 10 ⁇ m or more and 250 ⁇ m or less.
  • the above maximum dimension refers to the maximum dimension of the inner diameter of the via hole 19 when the opening of the via hole 19 has a circular shape in a plan view, for example.
  • the maximum dimension of the diagonal line of the opening of the via hole 19 is used.
  • a coating layer 11 is formed on the outer surface of the metal support 10 . More specifically, in metal support 10 , coating layer 11 is formed so as to entirely cover upper surface 10 a , lower surface 10 b and inner peripheral surface 10 c of each via hole 19 .
  • the covering layer 11 is made of, for example, an organic insulating material.
  • the organic insulating material of the covering layer 11 is, for example, photosensitive polyimide.
  • the organic insulating material of the covering layer 11 is, for example, photosensitive polyimide.
  • the coating layer 11 has a thickness of 1 ⁇ m or more and 10 ⁇ m or less.
  • the coating layer 11 may be formed of other organic insulating materials such as acrylic resin, polyethernitrile resin, polyethersulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin, or polyvinyl chloride resin.
  • an inorganic insulating material can be used instead of the above organic insulating material.
  • silicon carbide, silicon dioxide, aluminum nitride, aluminum oxide, or the like can be used as the material of the coating layer 11 .
  • the coating layer 11 can be formed using a film forming technique such as sputtering or chemical vapor deposition, as described later.
  • the thickness of the coating layer 11 is the same as the thickness (1 ⁇ m or more and 10 ⁇ m or less) when using photosensitive polyimide. can be made even smaller.
  • a first insulating layer 21 and a second insulating layer 22 having a predetermined pattern are laminated in this order on the upper surface 10a of the metal support 10 .
  • An insulating layer 20 is formed by a first insulating layer 21 and a second insulating layer 22 .
  • a third insulating layer 31 and a fourth insulating layer 32 having a predetermined pattern are laminated in this order on the lower surface 10b of the metal support 10.
  • An insulating layer 30 is formed by a third insulating layer 31 and a fourth insulating layer 32 .
  • the insulating layers 20 and 30 are made of, for example, photosensitive polyimide.
  • the insulating layers 20 and 30 may be made of other resin such as acrylic resin, polyethernitrile resin, polyethersulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin, or polyvinyl chloride resin.
  • a via conductor 41 is provided in each via hole 19 of the metal support 10 with the coating layer 11 interposed therebetween.
  • via conductor 41 is made of the same metal as metal support 10 .
  • a first conductor layer 51 is formed on the upper surface 10 a of the metal support 10 in addition to the first insulating layer 21 . Specifically, on the upper surface 10 a of the metal support 10 , the first insulating layer 21 non-formation region (region having a pattern opposite to the pattern of the first insulating layer 21 ) is coated with the coating layer 11 interposed therebetween.
  • a first conductor layer 51 is formed. A portion of first conductor layer 51 is electrically connected to via conductor 41 .
  • Each of the plurality of via conductors 41 of this example has a shape similar to the opening of the via hole 19 in which the via conductor 41 is provided, for example, in plan view in the thickness direction of the rewiring board 100 .
  • the maximum dimension of each via conductor 41 perpendicular to the thickness direction of the rewiring board 100 is, for example, 5 ⁇ m or more and 200 ⁇ m or less.
  • a second insulating layer 22 non-formation region (a region having a pattern opposite to the pattern of the second insulating layer 22) is provided with a second A conductor layer 52 is formed. A portion of the second conductor layer 52 is electrically connected to the first conductor layer 51 .
  • a conductor layer 50 is formed by a first conductor layer 51 and a second conductor layer 52 .
  • the second conductor layer 52 has a plurality of terminal portions T1 exposed upward in regions where the second insulating layer 22 is not formed.
  • a plurality of electrode pads 71 of the semiconductor element 700 are connected via solder S to these terminal portions T1. Therefore, the number and arrangement of the plurality of terminal portions T1 are determined so as to correspond to the number and arrangement of the plurality of electrode pads 71 of the semiconductor element 700.
  • a third conductor layer 61 is formed in addition to the third insulating layer 31. Specifically, on the lower surface 10 b of the metal support 10 , the third insulating layer 31 non-formation region (region having a pattern opposite to the pattern of the third insulating layer 31 ) is coated with the coating layer 11 interposed therebetween. A third conductor layer 61 is formed. Part of third conductor layer 61 is electrically connected to via conductor 41 .
  • a fourth insulating layer 32 non-formation region (a region with a pattern opposite to the pattern of the fourth insulating layer 32) is provided with a fourth A conductor layer 62 is formed.
  • a portion of the fourth conductor layer 62 is electrically connected to the third conductor layer 61 .
  • a conductor layer 60 is formed by the third conductor layer 61 and the fourth conductor layer 62 .
  • the fourth conductor layer 62 is formed with a plurality of terminal portions T2 exposed downward in regions where the fourth insulating layer 32 is not formed.
  • a plurality of electrode pads 81 of the rigid substrate 800 are connected via solder S to these terminal portions T2. Therefore, the number and arrangement of the plurality of terminal portions T2 are determined so as to correspond to the number and arrangement of the plurality of electrode pads 81 of the rigid substrate 800.
  • the conductor layers 50 and 60 are made of copper.
  • Conductor layers 50 and 60 are made of a metal or alloy containing one or more of copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, and the like. may
  • each of the plurality of terminal portions T1 and T2 has a laminated structure of a nickel film and a gold plating film.
  • each terminal portion T1 has a structure in which a nickel film and a gold plating film are formed in this order on the surface of the upper end portion of the second conductor layer 52 .
  • Each terminal portion T2 has a structure in which a nickel film and a gold plating film are formed in this order on the surface of the lower end portion of the fourth conductor layer 62 .
  • each of the terminal portions T1 and T2 may be composed only of a gold-plated film without the nickel film. Corrosion resistance of each of the terminal portions T1 and T2 is ensured by the gold plating film.
  • each terminal portion T1 may be composed of the conductor layer 50 (second conductor layer 52) itself, or may have a structure in which the surface of the upper end portion of the second conductor layer 52 is subjected to antirust treatment.
  • each terminal portion T2 may be composed of the conductor layer 60 (fourth conductor layer 62) itself, or may have a structure in which the surface of the lower end portion of the fourth conductor layer 62 is subjected to antirust treatment. You may
  • each of the plurality of terminal portions T1 formed on the upper surface of the rewiring board 100 is formed on the lower surface of the rewiring board 100 through the plurality of via conductors 41 and the conductor layers 50 and 60. It is electrically connected to one of the plurality of terminal portions T2.
  • a plurality of electrode pads 71 of the semiconductor element 700 are connected to the plurality of terminal portions T1 of the rewiring substrate 100, and a plurality of electrode pads 81 of the rigid substrate 800 are connected to the plurality of terminal portions T2 of the rewiring substrate 100. be done. Thereby, the plurality of electrode pads 71 of the semiconductor element 700 and the plurality of electrode pads 81 of the rigid substrate 800 are electrically connected through the rewiring substrate 100 .
  • the number of terminal portions T1 located on the top surface of the rewiring board 100 and the number of terminal portions T2 located on the bottom surface of the rewiring board 100 are different. , but the invention is not limited to this. The number of terminal portions T1 located on the top surface of the rewiring board 100 and the number of terminal portions T2 located on the bottom surface of the rewiring board 100 do not have to match.
  • FIGS. It is a cross-sectional view. Schematic cross-sectional views shown in FIGS. 4 to 16 correspond to the schematic cross-sectional view of FIG. 7, 9 and 10 of FIGS. 4 to 16 show, in addition to the schematic cross-sectional views, partial enlarged plan views of the object (intermediate body of the rewiring board 100) in balloons.
  • the rewiring board 100 of this example is manufactured by a roll-to-roll method.
  • a roll around which a long metal plate 90 made of stainless steel is wound (hereinafter referred to as a delivery roll) is prepared.
  • a metal plate 90 is delivered from the prepared delivery roll.
  • the metal plate 90 delivered from the delivery roll is wound around another roll.
  • FIG. 4 shows a partial cross-section of the metal plate 90 delivered from the delivery roll.
  • Metal plate 90 is a member for forming metal support 10 described above, and has upper surface 10a and lower surface 10b. According to the roll-to-roll method, the following processes are sequentially performed on each area of the metal plate 90 while the long metal plate 90 moves in the longitudinal direction.
  • a carrier film CF0 is attached onto the lower surface 10b of the metal plate 90.
  • a photosensitive dry film resist 29a is applied on the upper surface 10a of the metal plate 90.
  • the photosensitive dry film resist 29a is exposed in a predetermined pattern and developed to form an etching resist 29b on the upper surface 10a of the metal plate 90, as shown in FIG.
  • the etching resist 29b of this example has a plurality of annular openings 29x surrounding a plurality of portions of the metal plate 90 in plan view in the thickness direction of the metal plate 90, as shown in the balloons in FIG. have.
  • a plurality of portions of the upper surface 10a of the metal plate 90 overlapping the plurality of openings 29x of the etching resist 29b are exposed upward.
  • Each of the plurality of openings 29x of the etching resist 29b is an opening for forming the via hole 19 of FIG.
  • a plurality of portions of the metal plate 90 exposed through the plurality of openings 29x of the etching resist 29b are etched. Further, as shown in FIG. 9, the etching resist 29b is removed from the upper surface 10a of the metal plate 90. Then, as shown in FIG. By forming a plurality of via holes 19 in the metal plate 90 in this manner, the metal support 10 is formed. At this time, as shown in the balloon of FIG. 9, inside the via hole 19, a part of the metal plate 90 is formed in the shape of an island as the via conductor 41 so as not to come into contact with the inner peripheral surface 10c of the via hole 19. .
  • the covering layer 11 made of photosensitive polyimide is formed on the exposed upper surface 10a and the inner peripheral surface 10c of the metal support 10 except for the upper surface of the via conductors 41. Then, as shown in FIG. Specifically, the formation of the coating layer 11 is performed as follows.
  • a precursor of photosensitive polyimide is applied onto the upper surface 10a of the metal support 10 .
  • the region between the inner peripheral surface 10c of the via hole 19 and the outer peripheral surface of the via conductor 41 is filled with a photosensitive polyimide precursor.
  • the coated photosensitive polyimide precursor is exposed and developed to form coating layer 11 except for the upper surface portions of via conductors 41 .
  • the formed coating layer 11 is cured.
  • the coating layer 11 is formed by sputtering, for example.
  • silicon carbide or aluminum oxide is used as the material of the coating layer 11, the coating layer 11 is formed by chemical vapor deposition, for example.
  • the carrier film CF0 is peeled off from the lower surface 10b of the metal support 10.
  • covering layer 11 made of photosensitive polyimide is formed on exposed lower surface 10 b of metal support 10 excluding the lower surface portions of via conductors 41 .
  • the formation of the coating layer 11 on the lower surface 10b of the metal support 10 is performed in the same manner as the formation of the coating layer 11 on the upper surface 10a of the metal support 10 .
  • the formed coating layer 11 is cured.
  • a first conductor layer 51 made of copper is formed in predetermined regions on the upper surfaces of the plurality of via conductors 41 and the upper surface 10 a of the metal support 10 . Furthermore, a third conductor layer 61 made of copper is formed in predetermined regions on the lower surface of the plurality of via conductors 41 and the lower surface 10 b of the metal support 10 . Specifically, the first conductor layer 51 and the third conductor layer 61 are formed as follows.
  • a seed layer composed of, for example, a chromium thin film and a copper thin film is formed by sputtering or electroless plating on the upper surface 10a of the metal support 10, the lower surface 10b of the metal support 10, the upper surface of the via conductor 41, and the lower surface of the via conductor 41. be done.
  • a plating resist having a predetermined pattern is formed on the seed layer.
  • parts of the first conductor layer 51 and the third conductor layer 61 are formed by electroplating on the seed layer exposed through the openings of the plating resist.
  • the first conductor layer 51 is electrically connected to the plurality of via conductors 41 .
  • the third conductor layer 61 is electrically connected to the plurality of via conductors 41 .
  • the portions of the first conductor layer 51 and the third conductor layer 61 formed here are used as wiring portions.
  • the first conductor layer 51 and the third conductor layer 61 include via portions in addition to the wiring portions described above. Therefore, after forming the wiring portions of the first conductor layer 51 and the third conductor layer 61, the via portions of the first conductor layer 51 and the third conductor layer 61 are further formed by electroplating using a plating resist. be done.
  • the plating resist is peeled off, and the exposed portions of the seed layer (the portions where the first conductor layer 51 and the third conductor layer 61 are not formed) are removed by etching. Furthermore, a barrier layer is formed on the outer surfaces of the first conductor layer 51 and the third conductor layer 61 to suppress the diffusion of copper.
  • the barrier layer is made of, for example, a nickel thin film. It should be noted that illustration of the seed layer and the barrier layer is omitted in FIG.
  • a photosensitive polyimide is applied to a region of the upper surface 10a of the metal support 10 where the first conductor layer 51 is not formed.
  • a first insulating layer 21 is formed.
  • the first insulating layer 21 is also formed in the region of the wiring portion of the first conductor layer 51 .
  • the wiring portion of the first conductor layer 51 is covered with the first insulating layer 21, and the via portion (portion other than the wiring portion) of the first conductor layer 51 is exposed.
  • a third insulating layer 31 made of photosensitive polyimide is formed in a region of the lower surface 10b of the metal support 10 where the third conductor layer 61 is not formed.
  • the third insulating layer 31 is also formed in the region of the wiring portion of the third conductor layer 61 .
  • the wiring portion of the third conductor layer 61 is covered with the third insulating layer 31, and the via portion (portion other than the wiring portion) of the third conductor layer 61 is exposed.
  • the first insulating layer 21 and the third insulating layer 31 are formed by applying a photosensitive polyimide precursor to the upper surface 10a and the lower surface 10b of the metal support 10, and exposing and developing the precursor. . Further, the formed first insulating layer 21 and third insulating layer 31 are cured.
  • the barrier layer existing in a predetermined region on the upper surface of the first conductor layer 51 is removed. Also, the barrier layer present in a predetermined region on the upper surface of the third conductor layer 61 is removed.
  • a second conductor layer 52 is formed in a predetermined region on the upper surface of the first conductor layer 51 and the upper surface of the first insulating layer 21 from which the barrier layer has been removed.
  • a fourth conductor layer 62 is formed in a predetermined region on the lower surface of the third conductor layer 61 and the lower surface of the third insulating layer 31 from which the barrier layer has been removed.
  • Each of the second conductor layer 52 and the fourth conductor layer 62 has a wiring portion and a via portion similarly to the first conductor layer 51 and the third conductor layer 61 . Therefore, the formation of the second conductor layer 52 and the fourth conductor layer 62 is basically performed in the same procedure as the formation of the first conductor layer 51 and the third conductor layer 61 .
  • a second insulating layer made of photosensitive polyimide is formed on the upper surfaces of the first insulating layer 21 and the first conductive layer 51 where the second conductive layer 52 is not formed. 22 are formed.
  • the second insulating layer 22 is also formed in the region of the wiring portion of the second conductor layer 52 .
  • the wiring portion of the second conductor layer 52 is covered with the second insulating layer 22, and the via portion (portion other than the wiring portion) of the second conductor layer 52 is exposed.
  • the fourth insulating layer 32 made of photosensitive polyimide is formed on the lower surfaces of the third insulating layer 31 and the third conductive layer 61 in areas where the fourth conductive layer 62 is not formed.
  • the fourth insulating layer 32 is also formed in the region of the wiring portion of the fourth conductor layer 62 .
  • the wiring portion of the fourth conductor layer 62 is covered with the fourth insulating layer 32, and the via portion (portion other than the wiring portion) of the fourth conductor layer 62 is exposed.
  • the second insulating layer 22 and the fourth insulating layer 32 are basically formed in the same procedure as the first insulating layer 21 and the third insulating layer 31 are formed.
  • the barrier layer formed on the plurality of portions exposed upward of the second conductor layer 52 is removed, and the terminal portions T1 are formed on the plurality of portions of the second conductor layer 52 from which the barrier layer has been removed. (FIG. 1) is formed.
  • the barrier layer formed on the plurality of portions exposed downward of the fourth conductor layer 62 is removed, and the terminal portions T2 ( 1) is formed.
  • the terminal portions T1 and T2 have a laminated structure of, for example, a nickel film and a gold plating film. Note that the terminal portions T1 and T2 may be formed only of the gold plating film. Thus, the rewiring board 100 is completed.
  • the carrier film CF0 attached to the metal plate 90 in the initial process may be made of a photosensitive material such as photosensitive polyimide.
  • the carrier film CF0 is exposed and developed to form the coating layer 11 on the lower surface 10b of the metal support 10. can be formed. Therefore, it becomes unnecessary to peel off the carrier film CF0.
  • FIGS. 17 to 23 are schematic cross-sectional views for explaining a second example of manufacturing method of the rewiring board 100 of FIG.
  • the schematic cross-sectional views shown in FIGS. 17-23 correspond to the schematic cross-sectional view of FIG. 1, as do the schematic cross-sectional views of FIGS. 4-16. 18, 20, 21, 22 and 23 out of FIGS. 17 to 23, in addition to the schematic cross-sectional views, one part of the object (the intermediate of the rewiring board 100) is shown in the balloon. A partial enlarged plan view is shown.
  • the second example of the method for manufacturing the rewiring board 100 will be described below mainly on the differences from the first example of the method for manufacturing the rewiring board 100 .
  • the rewiring board 100 of this example is manufactured by the roll-to-roll method as in the first example. Therefore, also in this example, first, a pay-out roll around which the long metal plate 90 made of stainless steel is wound is prepared. A metal plate 90 is delivered from a prepared delivery roll, and the delivered metal plate 90 is wound around another roll. Each region of the metal plate 90 moving from the supply roll to another roll is sequentially subjected to the following processes.
  • a photosensitive dry film resist 29a is adhered to the upper surface 10a of the metal plate 90, as shown in FIG. Attached. Thereafter, the photosensitive dry film resist 29a is exposed in a predetermined pattern and developed to form an etching resist 29b on the upper surface 10a of the metal plate 90, as shown in FIG.
  • the etching resist 29b of this example has a plurality of arcuate openings 29y in plan view in the thickness direction of the metal plate 90, as shown in the balloons in FIG. As a result, a plurality of portions of the upper surface 10a of the metal plate 90 overlapping the plurality of openings 29y of the etching resist 29b are exposed upward.
  • Each of the plurality of openings 29y is an opening for forming the via hole 19 of FIG.
  • the shape of each of the plurality of openings 29y in this example is close to an annular shape in a plan view.
  • a plurality of portions of the metal plate 90 exposed through the plurality of openings 29y of the etching resist 29b are etched.
  • the etching resist 29b is removed from the upper surface 10a of the metal plate 90. Then, as shown in FIG.
  • a plurality of arc-shaped openings 10y are formed in the metal plate 90, as shown in the balloon in FIG.
  • the conductor forming portion 10i and the connecting portion 10j are formed in the region of the metal plate 90 where each opening 10y is formed.
  • the connecting portion 10j is a portion located between one end and the other end of the opening 10y extending in an arc shape in plan view.
  • the conductor forming portion 10i is a portion surrounded by the opening portion 10y and the connecting portion 10j in plan view.
  • the conductor forming portion 10i and the connecting portion 10j are indicated by dashed lines.
  • the above conductor forming portion 10i is finally separated from other portions of the metal plate 90 to be used as the via conductor 41 .
  • the connecting portion 10j is integrally formed with other portions of the metal plate 90.
  • the metal plate 90 including the plurality of conductor forming portions 10i can be transported independently by the roll-to-roll method without using the carrier film CF0.
  • a covering layer 11 made of photosensitive polyimide is formed on the exposed upper and lower surfaces 10a and 10b of the metal plate 90 except for the upper and lower surfaces of the plurality of conductor forming portions 10i of the metal plate 90. be done. Also, the coating layer 11 is formed in the plurality of openings 10y of the metal plate 90 .
  • a photosensitive polyimide precursor is applied onto the upper surface 10 a and the lower surface 10 b of the metal plate 90 . Further, the inside of each opening 10y of the metal plate 90 is filled with a photosensitive polyimide precursor. Thereafter, the coated photosensitive polyimide precursor is exposed and developed to form the coating layer 11 on the entire surface of the metal plate 90 except for the upper and lower surfaces of the conductor forming portion 10i. The formed coating layer 11 is cured.
  • the multiple connecting portions 10j of the metal plate 90 are removed.
  • the plurality of connecting portions 10j can be removed by forming through holes H1 in the portion of the metal plate 90 including the connecting portions 10j using a laser processing technique. In this manner, a plurality of via holes 19 each having openings 10y and through holes H1 are formed in metal plate 90.
  • the metal plate 90 is formed as the metal support 10 . Formation of the through holes H1 for removing the plurality of connecting portions 10j may be performed using, for example, a drilling technique or a punching technique.
  • an insulating material MI is embedded inside the plurality of through holes H1 formed to remove the plurality of connecting portions 10j.
  • an insulating filler such as silicon carbide, silicon dioxide or aluminum nitride is used.
  • each conductor forming portion 10i is electrically isolated from the inner peripheral surface 10c of the via hole 19 by the covering layer 11 and the insulating material MI. Thereby, each conductor forming portion 10i can be used as a via conductor 41 in each via hole 19 in which the conductor forming portion 10i is accommodated.
  • a conductor layer 50 and an insulating layer 20 are formed above the metal support 10 shown in FIG.
  • a conductor layer 60 and an insulating layer 30 are formed below the metal support 10 shown in FIG. 23 in the same procedure as in the first example of the method for manufacturing the rewiring board 100 .
  • At least a portion of the first conductor layer 51 is electrically connected to the upper surfaces of the plurality of via conductors 41 exposed upward when the conductor layer 50 is formed.
  • formed to connect to At least part of the third conductor layer 61 is formed so as to be electrically connected to the lower surfaces of the plurality of via conductors 41 exposed downward.
  • the insulating material MI is used in addition to the covering layer 11 in order to electrically separate the metal support 10 and the via conductors 41 from each other. Therefore, according to the configuration of the rewiring board 100 manufactured according to the second example, the insulating material MI is added in the via hole 19 of the metal support 10 in the cross-sectional view of FIG.
  • the via made of a part of the metal plate 90 is placed in the via hole 19 so as not to contact the inner peripheral surface 10c of the via hole 19.
  • a conductor 41 is formed.
  • the via conductors 41 in the via holes 19 are made of a part of the metal plate 90, there is no need to form the via conductors 41 in the via holes 19 by plating or the like. Therefore, it is easy to form the via conductor 41 in the via hole 19 .
  • the rewiring board 100 that is easy to manufacture and has improved electrical continuity reliability is realized.
  • photosensitive polyimide for example, is used as the material of the coating layer 11 that covers the surface of the metal support 10 .
  • the coating layer 11 can be easily formed on a desired region of the surface of the metal support 10 by using a photolithographic technique.
  • the coating layer 11 is formed over substantially the entire surface of the metal support 10 in the above example, the coating layer 11 may be selectively formed on a part of the surface of the metal support 10. good.
  • the coating layer 11 includes the inner peripheral surface 10c of the via hole 19 of the metal support 10, the formation region of the first conductor layer 51 on the upper surface 10a of the metal support 10, and the third portion of the lower surface 10b of the metal support 10. may be formed only in the region where the conductor layer 61 is formed.
  • the linear expansion coefficient of the metal support 10 at 25°C to 200°C is 0 ⁇ m/K or more and 25 ⁇ m/K or less. In this case, it is possible to prevent the metal support 10 from greatly deforming due to a change in the temperature of the rewiring board 100 . Thereby, the reliability of the rewiring board 100 is improved.
  • the metal support 10 preferably contains a component that improves adhesion between the metal support 10 and the coating layer 11 .
  • a component that improves adhesion between the metal support 10 and the coating layer 11 peeling of the coating layer 11 from the surface of the metal support 10 is suppressed.
  • Components that improve adhesion between the metal support 10 and the coating layer 11 include copper, aluminum, nickel, chromium, titanium, molybdenum, and the like.
  • a semiconductor element 700 includes a plurality of electrode pads 71 as a plurality of terminals.
  • the plurality of electrode pads 71 are basically formed such that the tips of the plurality of electrode pads 71 (electrical connection portions with respect to the rewiring board 100) are positioned on one plane.
  • the semiconductor element 700 cannot be mounted on the rewiring board 100. less reliable.
  • the rewiring board 100 may be mounted on the rewiring board 100 in an unintended orientation.
  • the tip of each electrode pad 71 of the semiconductor element 700 has a circular exposed surface with a diameter of about 30 ⁇ m, for example.
  • the semiconductor element 700 is mounted on the rewiring board 100 , hemispherical solder S is provided in advance on the exposed surface of the tip of each electrode pad 71 . Therefore, the solder S provided on each electrode pad 71 protrudes from the tip of the electrode pad 71 by about 15 ⁇ m. Therefore, the rewiring board 100 needs to be formed so that the variation in the height positions of the plurality of terminal portions T1 is at least 15 ⁇ m or less.
  • the rewiring board 100 is preferably formed so that the height positional variation of the plurality of terminal portions T1 is 10 ⁇ m or less. Further, the rewiring board 100 is more preferably formed so that the variation in the height position of the plurality of terminal portions T1 is 5 ⁇ m or less, and the variation in the height position of the plurality of terminal portions T1 is 2 ⁇ m or less. It is further preferred that it is formed as follows.
  • ⁇ 2> Causes of Variation in Height Positions of Plurality of Terminals T1 Causes of variation in height positions of a plurality of terminals T1 are examined.
  • One or a plurality of terminal portions T1 overlapping the via conductors 41 in a plan view are formed by directly forming a conductor layer 50 on the upper surface of the via conductors 41 at the same height as the upper surface 10a of the metal support 10, for example. It is formed.
  • one or more terminal portions T1 which do not overlap the via conductors 41 in plan view are formed by forming a conductor layer 50 on the upper surface 10a of the metal support 10 excluding the via conductors 41 with the covering layer 11 interposed therebetween. be done.
  • variations in the height positions of the plurality of terminal portions T1 are mainly due to one or more terminal portions T1 overlapping the via conductors 41 in plan view and one or more terminal portions T1 not overlapping the via conductors 41 in plan view. occurs between In consideration of this point, the rewiring board 100 has the configuration (first to fourth configuration examples) described below so that the variation in the height positions of the plurality of terminal portions T1 is at least 15 ⁇ m or less. You may In addition, in the first to fourth configuration examples described below, each of the plurality of terminal portions T1 is formed of the conductor layer 50 itself.
  • FIG. 1 is a schematic cross-sectional view showing a configuration example of No. 1.
  • FIG. FIG. 24 shows an enlarged portion of the rewiring board 100 according to the first configuration example.
  • a rewiring board 100 in FIG. 24 has a metal support 10 in which via holes 19 are formed.
  • the via hole 19 is indicated by a thick dotted line frame.
  • a via conductor 41 made of the same metal as the metal support 10 is formed in the via hole 19 of the metal support 10 .
  • a coating layer 11 is formed so as to cover the upper surface 10 a and the lower surface 10 b of the metal support 10 and the inner peripheral surface 10 c of the via hole 19 of the metal support 10 .
  • a portion of the coating layer 11 that covers the upper surface 10a of the metal support 10 is called an upper surface coating portion 11a.
  • a portion of the coating layer 11 that covers the lower surface 10b of the metal support 10 is called a lower surface covering portion 11b.
  • a portion of the coating layer 11 that covers the inner peripheral surface 10c of the metal support 10 is called an in-hole coating portion 11c.
  • In-hole covering portion 11 c is located inside via hole 19 in plan view and surrounds via conductor 41 .
  • a plurality of conductor layers 50 having a predetermined pattern are formed on the upper surface covering portion 11a of the covering layer 11 .
  • An insulating layer 20 is formed so as to partially cover each conductor layer 50 .
  • a plurality of (two in this example) conductor layers 63 and 64 and a plurality of (two in this example) insulating layers 33 and 34 having a predetermined pattern are laminated on the lower surface covering portion 11b of the covering layer 11. ing.
  • one conductor layer 50 among the plurality of conductor layers 50 includes a first connection conductor portion 50a.
  • the first connection conductor portion 50 a is in contact with the via conductor 41 and extends upward from the via conductor 41 toward the rewiring board 100 . That is, the first connection conductor portion 50a extends from the via conductor 41 in the direction in which the upper surface 10a of the metal support 10 faces.
  • a tip portion of the first connection conductor portion 50a constitutes a terminal portion T1.
  • the terminal portion T1 formed by the tip portion of the first connection conductor portion 50a is referred to as the first terminal portion T1a.
  • the other conductor layer 50 among the plurality of conductor layers 50 includes the second connection conductor portion 50b.
  • the second connection conductor portion 50b is formed on the upper surface 10a of the metal support 10 via a portion of the upper surface covering portion 11a. Further, the second connection conductor portion 50b extends upward from the rewiring board 100 from a portion of the upper surface covering portion 11a. That is, the second connection conductor portion 50b extends from a portion of the upper surface covering portion 11a in the direction in which the upper surface 10a of the metal support 10 faces.
  • a tip portion of the second connection conductor portion 50b constitutes a terminal portion T1.
  • the terminal portion T1 formed by the tip portion of the second connection conductor portion 50b is referred to as the second terminal portion T1b.
  • FIG. 25 shows the positional relationship among the first terminal portion T1a, the first connection conductor portion 50a, the second terminal portion T1b, the second connection conductor portion 50b, the metal support 10 and the via conductor 41 of FIG. It is a top view. Note that the scale of the plan view of FIG. 25 is different from the scale of the schematic cross-sectional view of FIG. As shown in FIG. 25, the first terminal portion T1a and the first connection conductor portion 50a overlap the via conductor 41 in plan view. On the other hand, the second terminal portion T1b and the second connection conductor portion 50b do not overlap the via conductor 41 in plan view.
  • the vertical length (thickness) da of the first connection conductor 50a and the vertical length The length (thickness) db is almost the same. Therefore, the difference between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is the upper surface covering portion 11a located between the metal support 10 and the second connection conductor portion 50b. determined by the thickness of Therefore, in this example, the upper surface covering portion 11a is formed so that the thickness of the portion of the upper surface covering portion 11a where the second connection conductor portion 50b is formed is smaller than the thickness of the other portions. .
  • FIG. 26 is a diagram showing an example of mounting the semiconductor element 700 on the rewiring board 100 of FIG. As shown in FIG. 26, a semiconductor element 700 is mounted from above the rewiring board 100 . At this time, the solder S is provided on each of the plurality of electrode pads 71 of the semiconductor element 700 as described above. The solder S protrudes from the tip of the electrode pad 71 by a predetermined length sh.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is the solder S provided on the plurality of electrode pads 71 of the semiconductor element 700.
  • the thickness of the portion of the upper surface covering portion 11a that overlaps the second connection conductor portion 50b is adjusted so that the length sh is less than or equal to sh.
  • the length sh of the solder S provided on the plurality of electrode pads 71 is 15 ⁇ m.
  • the difference dd between the height positions of the first terminal portion T1a and the second terminal portion T1b is greater than the length sh (15 ⁇ m) of the solder S provided on the plurality of electrode pads 71.
  • the semiconductor element 700 can be structurally stably mounted on the rewiring board 100 as compared with a large size. Further, in a state where the semiconductor element 700 is mounted on the rewiring board 100, the reliability of electrical continuity between the rewiring board 100 and the semiconductor element 700 is improved.
  • the difference dd in the rewiring substrate 100 of the first configuration example is 10 ⁇ m or less. It is preferably 5 ⁇ m or less, more preferably 2 ⁇ m or less. In these cases, the reliability of mounting the semiconductor element 700 on the rewiring board 100 is further improved.
  • FIGS. 4 to 16 are schematic cross-sectional views for explaining an example of a method of manufacturing the rewiring board 100 of FIG.
  • the rewiring board 100 according to the first configuration example is manufactured by, for example, a roll-to-roll method in the same manner as the first example of the manufacturing method of the rewiring board 100 described with reference to FIGS. 4 to 16. .
  • a delivery roll around which a long metal plate 90 made of stainless steel is wound is prepared, and the metal plate 90 is delivered from the prepared delivery roll.
  • the delivered metal plate 90 is wound on another roll.
  • the metal plate 90 like the metal plate 90 in FIG. 4, is a member for forming the metal support 10, and has an upper surface 10a and a lower surface 10b. While the metal plate 90 moves in the longitudinal direction, each area of the metal plate 90 is sequentially subjected to the following processes.
  • the lower surface covering portion 11b is formed on the lower surface 10b of the metal plate 90 in a predetermined pattern.
  • the lower surface covering portion 11b is made of a photosensitive material.
  • the lower surface covering portion 11b can be easily patterned by selectively exposing the photosensitive material forming the lower surface covering portion 11b.
  • photosensitive polyimide can be used as the photosensitive material.
  • other photosensitive resins acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, polyvinyl chloride resin, or other photosensitive resin
  • photosensitive polyimide may also be used instead of photosensitive polyimide.
  • a plurality of conductor layers 63 are formed in a predetermined pattern on one surface of the lower surface covering portion 11b exposed downward and on the portion of the metal plate 90 exposed downward. Further, as shown in FIG. 29, the insulating layer 33 is formed in a predetermined pattern on the lower surface covering portion 11b so as to cover at least a portion of the conductor layer 63. As shown in FIG. 28, a plurality of conductor layers 63 are formed in a predetermined pattern on one surface of the lower surface covering portion 11b exposed downward and on the portion of the metal plate 90 exposed downward. Further, as shown in FIG. 29, the insulating layer 33 is formed in a predetermined pattern on the lower surface covering portion 11b so as to cover at least a portion of the conductor layer 63. As shown in FIG.
  • a plurality of conductor layers 64 are formed in a predetermined pattern on one surface of the insulating layer 33 exposed downward and on the portion of the conductor layer 63 exposed downward. Further, as shown in FIG. 31, an insulating layer 34 is formed in a predetermined pattern on the insulating layer 33 so as to cover at least part of the conductor layer 64 .
  • the formation of the conductor layers 63, 64 is performed in the same procedure as the formation of the respective conductor layers (51, 52, 61, 62) in the method of manufacturing the rewiring board 100 described with reference to FIGS.
  • the insulating layers 33 and 34 are formed in the same procedure as the insulating layers (21, 22, 31, 32) in the method of manufacturing the rewiring board 100 described with reference to FIGS. will be
  • the metal plate 90 is formed with an annular opening 19x.
  • the via hole 19 and the metal support 10 are formed by the annular opening 19x.
  • the via holes 19 are formed by the same method as the formation of the via holes 19 in the manufacturing method of the rewiring board 100 described with reference to FIGS.
  • a portion of metal plate 90 is formed in an island shape as via conductor 41 so as not to come into contact with inner peripheral surface 10 c of via hole 19 .
  • the in-hole covering portion 11c is formed to cover the inner peripheral surface 10c of the via hole 19 on one surface of the lower surface covering portion 11b exposed upward. Further, an upper surface covering portion 11a is formed on the upper surface 10a of the metal support 10 in a predetermined pattern.
  • the upper covering portion 11a is made of a photosensitive material, like the lower covering portion 11b.
  • an opening h11 for exposing the upper surface of the via conductor 41 is formed at a position above the via conductor 41 where the first connection conductor portion 50a of FIG. 24 is to be formed.
  • This opening h12 is formed using, for example, a gradation exposure technique.
  • the thickness of the portion of the upper covering portion 11a where the opening h12 is formed is preferably 1 ⁇ m to 5 ⁇ m, and is 2 ⁇ m in this example. Further, in this example, the thickness of the portion of the upper covering portion 11a where the opening h12 is not formed is 10 ⁇ m.
  • the maximum dimension of the opening h12 when viewed in plan is in the range of 10 ⁇ m or more and 50 ⁇ m or less than the design maximum dimension of the second terminal portion T1b when viewed in plan. It is preferably formed to be large.
  • the opening h12 has a maximum dimension value larger than the design maximum dimension value of the second terminal portion T1b when viewed from above in a range of 15 ⁇ m or more and 40 ⁇ m or less.
  • the opening h12 has a circular shape with a diameter of 40 ⁇ m in plan view or a circular shape with a diameter of 50 ⁇ m in plan view. It is preferably formed as follows. In this case, even if the formation positions of the plurality of conductor layers 50 are misaligned in the manufacturing process of the rewiring board 100, the misalignment is absorbed by the size of the openings h12.
  • a plurality of conductor layers 50 are formed in a predetermined pattern on a plurality of predetermined regions of the exposed upper surface of the upper surface covering portion 11a and the portions of the via conductors 41 exposed through the openings h11. formed by
  • the first connection conductor portion 50a is formed in the conductor layer 50 formed on the via conductor 41.
  • a second connection conductor portion 50b is formed in the conductor layer 50 formed on the bottom portion of the opening h12 of the upper surface covering portion 11a.
  • Each of the first connection conductor portion 50a and the second connection conductor portion 50b has a cylindrical shape extending in the vertical direction of the rewiring board 100, for example.
  • the tip portions of the plurality of first connection conductor portions 50a constitute the first terminal portion T1a, and the tip portions of the plurality of second connection conductor portions 50b constitute the second terminal portion T1b.
  • the vertical length (thickness) da of the first connection conductor portion 50a formed in this example and the vertical length (thickness) db of the second connection conductor portion 50b are the same (see FIG. 24). ).
  • the insulating layer 20 is formed in a predetermined pattern on the upper surface covering portion 11a so as to partially cover each conductor layer 50 .
  • the formation of the insulating layer 20 of this example is performed in the same procedure as the formation of the respective insulating layers (21, 22, 31, 32) in the manufacturing method of the rewiring board 100 described with reference to FIGS. As a result, the rewiring board 100 of FIG. 24 is completed.
  • the thickness of the portion of the upper covering portion 11a where the opening h12 is formed is 2 ⁇ m, and the thickness of the portion of the upper covering portion 11a where the opening h12 is not formed is 10 ⁇ m.
  • the difference dd (FIG. 26) between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is 8 ⁇ m.
  • FIG. 2 is a schematic cross-sectional view showing a configuration example of No. 2.
  • FIG. FIG. 35 shows an enlarged portion of the rewiring board 100 according to the second configuration example.
  • the rewiring board 100 according to the second configuration example differences from the rewiring board 100 according to the first configuration example shown in FIG. 24 will be described.
  • the total thickness of the upper surface covering portion 11a of the coating layer 11 is equal to the maximum thickness of the upper surface covering portion 11a according to the first configuration example. less than Specifically, the top covering portion 11a according to the second configuration example has a thickness of 15 ⁇ m or less, preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and 2 ⁇ m or less. It is more preferable to have thickness.
  • the first terminal A difference dd between the height position of the portion T1a and the height position of the second terminal portion T1b is equal to or less than 15 ⁇ m, which is the thickness of the upper surface covering portion 11a.
  • the lower surface covering portion 11b is also formed to have approximately the same thickness as the upper surface covering portion 11a.
  • the rewiring board 100 according to the second structural example is manufactured by the manufacturing method of FIGS. can be made in basically the same way.
  • a precursor of photosensitive polyimide is applied onto the upper surface 10a of the metal support 10, and a precursor of the photosensitive polyimide is filled in the via hole 19. fill the body.
  • the supply amount of the precursor is adjusted so that the thickness of the precursor applied onto the upper surface 10a of the metal support 10 is sufficiently small.
  • the coated and filled photosensitive polyimide is exposed and developed to form the upper surface covering portion 11a having a small thickness.
  • the upper surface covering portion 11a according to the second configuration example may be made of an inorganic insulating material such as silicon carbide, silicon dioxide, aluminum nitride or aluminum oxide instead of photosensitive resin such as photosensitive polyimide.
  • the top covering portion 11a can be formed using a film forming technique such as sputtering or chemical vapor deposition.
  • the difference dd in the rewiring substrate 100 of the second configuration example is It is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 2 ⁇ m or less. In these cases, the reliability of mounting the semiconductor element 700 on the rewiring board 100 is further improved.
  • FIG. 3 is a schematic cross-sectional view showing a configuration example of No. 3.
  • FIG. FIG. 36 shows an enlarged portion of the rewiring board 100 according to the third configuration example.
  • the rewiring board 100 according to the third configuration example differences from the rewiring board 100 according to the first configuration example shown in FIG. 24 will be described.
  • the opening h12 of FIG. 33 is not formed in the upper covering portion 11a of the covering layer 11. In other words, no locally thin portion is formed in the upper covering portion 11a.
  • the vertical length (thickness) da of the first connection conductor portion 50a overlapping the via conductor 41 in plan view is equal to that of the second connection conductor not overlapping the via conductor 41 in plan view. It is larger than the vertical length (thickness) db of the portion 50b.
  • the length (thickness) da in the vertical direction of the first connection conductor portion 50a in contact with the via conductor 41 is equal to that of the second connection conductor formed on the metal support 10 via the upper covering portion 11a. It is larger than the vertical length (thickness) db of the portion 50b.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is set to 15 ⁇ m or less.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is zero.
  • the rewiring board 100 according to the third configuration example is basically the same as the manufacturing method of FIGS. can be made in essentially the same way.
  • the upper surface covering portion 11a of this example is formed so as to have a uniform thickness as a whole. That is, the local opening h12 (FIG. 33) is not formed in the upper covering portion 11a.
  • the plating process for forming the first connection conductor part 50a and the plating process for forming the second connection conductor part 50b are performed separately under different conditions. done. The conditions of each plating process are adjusted so that the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is 0 or 15 ⁇ m or less.
  • all conductor layers 50 including the first connection conductor portion 50a and the second connection conductor portion 50b are simultaneously formed under common conditions.
  • the vertical length (thickness) da of the first connection conductor 50a and the vertical length (thickness) db of the second connection conductor 50b are, for example, the same.
  • the tip portion of the second connection conductor portion 50b is removed by grinding or cutting by the thickness of the upper surface covering portion 11a.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is adjusted to be 0 or 15 ⁇ m or less.
  • the difference dd in the rewiring board 100 of the third configuration example is It is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 2 ⁇ m or less. In these cases, the reliability of mounting the semiconductor element 700 on the rewiring board 100 is further improved.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is 0, illustration of the sign dd indicating the difference is omitted.
  • FIG. 4 is a schematic cross-sectional view showing a configuration example of No. 4.
  • FIG. FIG. 37 shows an enlarged part of the rewiring board 100 according to the fourth configuration example.
  • differences from the rewiring board 100 according to the third configuration example shown in FIG. 37 will be described.
  • the rewiring board 100 according to the fourth configuration example can be manufactured by the same method as the rewiring board 100 according to the third configuration example, except that the method of forming the plurality of conductor layers 50 is different. Specifically, when fabricating the rewiring board 100 according to the fourth configuration example, after the upper surface covering portion 11a is formed on the metal support 10, the openings h11 formed on the via conductors 41 are filled. Via fill plating is performed as follows. As a result, as indicated by symbol vf together with a two-dot chain line frame in FIG. be flush or almost flush.
  • the remaining portions of the plurality of conductor layers 50 are further formed on the upper surface covering portion 11a by, for example, normal electroplating. As a result, a plurality of conductor layers 50 located on via conductors 41 and a plurality of conductor layers 50 located on upper surface covering portion 11a are formed.
  • the length (thickness) da of the first connection conductor 50a in the vertical direction is greater than the length (thickness) db of the second connection conductor 50b in via fill plating in the opening h11. Large thickness.
  • the difference dd between the height position of the first terminal portion T1a and the height position of the second terminal portion T1b is 0 or substantially 0.
  • the difference dd in the rewiring board 100 of the fourth configuration example is It is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 2 ⁇ m or less. In these cases, the reliability of mounting the semiconductor element 700 on the rewiring board 100 is further improved.
  • the reference numeral dd indicating the difference is omitted.
  • the rewiring board 100 may include a configuration for reducing variations in the height positions of the plurality of terminal portions T2 (FIG. 1) positioned below the rewiring board 100.
  • the upper covering portion 11a, the insulating layer 20 and the conductor layer 50 according to any one of the first to fourth structural examples are added to a plurality of layers laminated on the lower surface 10b of the metal support 10.
  • a layer corresponding to may be formed.
  • the rewiring board 100 can be structurally stably mounted on the rigid board 800 by setting the height variation of the plurality of terminal portions T2 to 15 ⁇ m or less. Further, in a state where the rewiring board 100 is mounted on the rigid board 800, the reliability of electrical continuity between the rewiring board 100 and the rigid board 800 is improved.
  • the metal support An adhesion-enhancing layer may be formed to improve the adhesion between the outer surface of 10 and the coating layer 11 .
  • FIG. 38 is a schematic cross-sectional view of a rewiring board 100 having an adhesion enhancing layer.
  • FIG. 38 shows an enlarged cross section of one via hole 19 of the metal support 10 of the rewiring board 100 and its peripheral portion.
  • an adhesion reinforcing layer 12 is formed between the upper surface 10a, the lower surface 10b and the inner peripheral surface 10c of the metal support 10 and the covering layer 11.
  • FIG. 38 is a schematic cross-sectional view of a rewiring board 100 having an adhesion enhancing layer.
  • FIG. 38 shows an enlarged cross section of one via hole 19 of the metal support 10 of the rewiring board 100 and its peripheral portion.
  • an adhesion reinforcing layer 12 is formed between the upper surface 10a, the lower surface 10b and the inner peripheral surface 10c of the metal support 10 and the covering layer 11.
  • the adhesion-enhancing layer 12 contains a component that improves adhesion between the metal support 10 and the coating layer 11, and is, for example, sputtered or chemically applied to the upper surface 10a, the lower surface 10b, and the inner peripheral surface 10c of the metal support 10. It is formed by performing a film forming process using a vapor deposition method or the like.
  • the adhesion-enhancing layer 12 contains a component that improves the adhesion between the metal support 10 and the coating layer 11, and is anodic to the upper surface 10a, the lower surface 10b and the inner peripheral surface 10c of the metal support 10, for example. It is formed by performing surface treatment such as oxidation treatment.
  • the adhesion-enhancing layer 12 improves the adhesion between the metal support 10 and the coating layer 11 , peeling of the coating layer 11 from the metal support 10 is suppressed. As a result, the insulation between metal support 10 and via conductors 41 and conductor layers 50 and 60 is ensured, so that the reliability of metal support 10 is improved.
  • heat generated from semiconductor element 700 is transferred to metal support 10 through via conductor 41 , conductor layer 50 and coating layer 11 . Furthermore, the heat transferred to the metal support 10 is transferred to the rigid substrate 800 through the conductor layer 60, for example.
  • the metal support 10 since the metal support 10 has higher thermal conductivity than resin or the like, it functions as a heat dissipation member for the semiconductor element 700 or a heat transfer member between the semiconductor element 700 and the rigid substrate 800 .
  • the adhesion-enhancing layer 12 is composed of chromium or aluminum oxide
  • the content of chromium or aluminum oxide in the adhesion-enhancing layer 12 should be 50% by weight or less. is preferred.
  • Chromium and aluminum have a lower thermal conductivity due to oxidation. Therefore, according to the above configuration, the decrease in the thermal conductivity of the adhesion-enhancing layer 12 is reduced compared to the case where the content of chromium or aluminum oxide in the adhesion-enhancing layer 12 is greater than 50% by weight. be. Therefore, deterioration in the heat dissipation efficiency of the semiconductor element 700 due to the adhesion enhancing layer 12 is reduced.
  • the coating layer 11 according to the above embodiment is used on the upper surface 10a of the metal support 10 to ensure insulation between the first conductor layer 51 and the metal support 10.
  • the invention is not limited to this.
  • the covering layer 11 may be formed on the upper surface 10 a of the metal support 10 such that a portion of the first conductor layer 51 is in direct contact with the upper surface 10 a of the metal support 10 .
  • the portion of the first conductor layer 51 that is in direct contact with the upper surface 10a of the metal support 10 is used for efficient heat transfer between the electronic component provided on the upper surface 10a of the metal support 10 and the metal support 10.
  • a heat transfer wiring thermal wiring can be used to transfer the heat.
  • the coating layer 11 according to the above embodiment is used to ensure insulation between the third conductor layer 61 and the metal support 10 on the lower surface 10b of the metal support 10, but the present invention is used. is not limited to this.
  • the covering layer 11 may be formed on the bottom surface 10b of the metal support 10 so that a portion of the third conductor layer 61 is in direct contact with the bottom surface 10b of the metal support 10 .
  • the portion of the third conductor layer 61 that is in direct contact with the lower surface 10b of the metal support 10 is used for efficient heat transfer between the electronic component provided on the lower surface 10b of the metal support 10 and the metal support 10.
  • a heat transfer wiring thermal wiring can be used to transfer the heat.
  • the above embodiment is an example in which the present invention is applied to a rewiring board, but the present invention is not limited to this and may be applied to other wiring circuit boards having via holes. Further, the rewiring board 100 according to the above embodiment may constitute a part of the semiconductor package board.
  • the insulating layer 20 is formed of the first insulating layer 21 and the second insulating layer 22, but the present invention is not limited to this.
  • the insulating layer 20 may be a single insulating layer, or may be formed of three or more insulating layers.
  • the insulating layer 30 is formed of the third insulating layer 31 and the fourth insulating layer 32 in the above embodiment, the present invention is not limited to this.
  • the insulating layer 30 may be a single insulating layer, or may be formed of three or more insulating layers. In these cases, the shapes of the conductor layers 50 and 60 are determined according to the configuration of the insulating layers 20 and 30. FIG.
  • the coating layer 11 formed on the upper surface 10a of the metal support 10 and the coating layer 11 formed on the lower surface 10b of the metal support 10 are made of a photosensitive carrier film CF0.
  • a photosensitive carrier film CF0 may be formed using Specifically, a carrier film made of photosensitive polyimide is attached to the upper surface 10a of the metal support 10 (or the metal plate 90), and a photosensitive polyimide film is applied to the lower surface 10b of the metal support 10 (or the metal plate 90). A different carrier film may be attached.
  • the coating layers 11 can be formed above and below the metal support 10 by exposing and developing the carrier films above and below the metal support 10 .
  • the via hole 19 of the metal support 10 has a circular or rectangular opening when viewed from above, but the via hole 19 may have an elliptical opening when viewed from above. It may also have polygonal openings other than squares, such as triangles or pentagons.
  • the via conductor 41 provided in each via hole 19 has a shape similar to the opening of the via hole 19 in plan view. It may have different shapes.
  • the rewiring board 100 is an example of a printed circuit board
  • the upper surface 10a of the metal support 10 is an example of the first surface
  • the lower surface 10b of the metal support 10 is an example of a second surface.
  • the via hole 19 is an example of a via hole
  • the metal support 10 is an example of a metal support
  • the coating layer 11 is an example of an insulating coating layer.
  • the conductor layer 50 is an example of a first conductor layer
  • the conductor layer 60 is an example of a second conductor layer
  • the via conductor 41 is an example of a via conductor
  • the adhesion-enhancing layer 12 is an example of an adhesion-enhancing layer.
  • the semiconductor element 700 is an example of a first electronic component
  • the rigid substrate 800 is an example of a second electronic component.
  • the upper surface covering portion 11a is an example of a first surface covering portion
  • the first connection conductor portion 50a is an example of a first connection conductor portion
  • the second connection conductor portion 50b is an example of a second connection conductor.
  • the semiconductor element 700 is an example of an electronic component
  • a portion of the plurality of electrode pads 71 is an example of one terminal of the electronic component
  • another portion of the plurality of electrode pads 71 is an example of the electronic component. is an example of another terminal of .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
PCT/JP2023/004740 2022-02-16 2023-02-13 配線回路基板およびその製造方法 Ceased WO2023157794A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202380022364.7A CN118715877A (zh) 2022-02-16 2023-02-13 布线电路基板及其制造方法
JP2024501361A JPWO2023157794A1 (https=) 2022-02-16 2023-02-13
KR1020247031054A KR20240147693A (ko) 2022-02-16 2023-02-13 배선 회로 기판 및 그의 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022022327 2022-02-16
JP2022-022327 2022-02-16

Publications (1)

Publication Number Publication Date
WO2023157794A1 true WO2023157794A1 (ja) 2023-08-24

Family

ID=87578206

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/004740 Ceased WO2023157794A1 (ja) 2022-02-16 2023-02-13 配線回路基板およびその製造方法

Country Status (5)

Country Link
JP (1) JPWO2023157794A1 (https=)
KR (1) KR20240147693A (https=)
CN (1) CN118715877A (https=)
TW (1) TW202341823A (https=)
WO (1) WO2023157794A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025192060A1 (ja) * 2024-03-15 2025-09-18 株式会社村田製作所 弾性波フィルタ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004179291A (ja) * 2002-11-26 2004-06-24 Ibiden Co Ltd 配線板および配線板の製造方法
JP2008098202A (ja) * 2006-10-05 2008-04-24 Ngk Spark Plug Co Ltd 多層配線基板、多層配線基板構造体
JP2017108033A (ja) * 2015-12-11 2017-06-15 イビデン株式会社 配線基板及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004179291A (ja) * 2002-11-26 2004-06-24 Ibiden Co Ltd 配線板および配線板の製造方法
JP2008098202A (ja) * 2006-10-05 2008-04-24 Ngk Spark Plug Co Ltd 多層配線基板、多層配線基板構造体
JP2017108033A (ja) * 2015-12-11 2017-06-15 イビデン株式会社 配線基板及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025192060A1 (ja) * 2024-03-15 2025-09-18 株式会社村田製作所 弾性波フィルタ

Also Published As

Publication number Publication date
KR20240147693A (ko) 2024-10-08
JPWO2023157794A1 (https=) 2023-08-24
TW202341823A (zh) 2023-10-16
CN118715877A (zh) 2024-09-27

Similar Documents

Publication Publication Date Title
JP5544872B2 (ja) 半導体装置及びその製造方法
US7954234B2 (en) Method of manufacturing a wiring board
KR101392950B1 (ko) 배선기판 및 배선기판 제조방법
US20090017613A1 (en) Method of manufacturing interconnect substrate and semiconductor device
US20150245485A1 (en) Printed wiring board and method for manufacturing printed wiring board
US8178790B2 (en) Interposer and method for manufacturing interposer
JP5362569B2 (ja) インターポーザー及びインターポーザーの製造方法
WO2023157794A1 (ja) 配線回路基板およびその製造方法
US8664536B2 (en) Wiring substrate and manufacturing method thereof
US11935822B2 (en) Wiring substrate having metal post offset from conductor pad and method for manufacturing wiring substrate
US20050017058A1 (en) [method of fabricating circuit substrate]
JP5017872B2 (ja) 半導体装置及びその製造方法
JP2003045917A (ja) 半導体装置用テープキャリアおよびその製造方法
JP2024094622A (ja) 配線回路基板およびその製造方法
US12108530B2 (en) Circuit board structure and manufacturing method thereof
TWI301662B (en) Package substrate and the manufacturing method making the same
WO2023157502A1 (ja) 配線回路基板およびその製造方法
US7335591B2 (en) Method for forming three-dimensional structures on a substrate
US20260068699A1 (en) Electronic component embedded substrate and method of manufacturing the same
CN223829833U (zh) 陶瓷封装基板
JP2004228446A (ja) プリント基板
TW202326956A (zh) 再配線基板及其製造方法
KR101920434B1 (ko) 인쇄회로기판 및 그 제조방법
JP2024025484A (ja) 配線基板、半導体装置
TW202518954A (zh) 配線電路基板、及配線電路基板之製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23756319

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2024501361

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 202380022364.7

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 20247031054

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020247031054

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23756319

Country of ref document: EP

Kind code of ref document: A1