WO2023157452A1 - 窒化物半導体装置 - Google Patents

窒化物半導体装置 Download PDF

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Publication number
WO2023157452A1
WO2023157452A1 PCT/JP2022/046702 JP2022046702W WO2023157452A1 WO 2023157452 A1 WO2023157452 A1 WO 2023157452A1 JP 2022046702 W JP2022046702 W JP 2022046702W WO 2023157452 A1 WO2023157452 A1 WO 2023157452A1
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Prior art keywords
electrode
layer
field plate
drain
nitride semiconductor
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English (en)
French (fr)
Japanese (ja)
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浩隆 大嶽
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112022006355.6T priority Critical patent/DE112022006355T5/de
Priority to JP2024500984A priority patent/JPWO2023157452A1/ja
Priority to CN202280091589.3A priority patent/CN118696416A/zh
Publication of WO2023157452A1 publication Critical patent/WO2023157452A1/ja
Priority to US18/798,932 priority patent/US20240405117A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes

Definitions

  • the present disclosure relates to nitride semiconductor devices.
  • Patent Document 1 discloses a normally-off nitride semiconductor HEMT.
  • a nitride semiconductor HEMT includes an electron transit layer composed of a gallium nitride (GaN) layer and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer.
  • the HEMT channel is formed by a two-dimensional electron gas (2DEG) generated in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer.
  • 2DEG two-dimensional electron gas
  • Patent Document 1 discloses that a GaN layer (p-type GaN layer) containing an acceptor-type impurity is provided under a gate electrode to block a channel formed by 2DEG, thereby realizing normally-off operation. are doing.
  • a p-type nitride semiconductor layer for example, a p-type GaN layer
  • a gate electrode for example, when a large positive bias is applied to the gate electrode, holes injected from the gate electrode are transferred to the p-type nitride semiconductor. It accumulates locally at the interface between the layer and the electron supply layer. Such local accumulation of holes causes band bending of the electron supply layer, causing electron leakage (gate current leakage) from the electron transit layer to the p-type nitride semiconductor layer via the electron supply layer, and eventually gate current leakage. It can be a factor that lowers the breakdown voltage.
  • electric field concentration occurs near the gate electrode end in the drain-source region, especially near the gate electrode end on the drain electrode side.
  • Such electric field concentration can cause dielectric breakdown of, for example, the electron supply layer and the like, which can be a factor in lowering the breakdown voltage between the drain and the source.
  • the source electrode is arranged to cover the gate electrode and extend to a position facing the drain electrode.
  • Such an extended portion of the source electrode is called a field plate electrode or a source field plate electrode.
  • the source field plate electrode has the effect of alleviating electric field concentration near the edge of the gate electrode.
  • a HEMT with a source field plate electrode has a parasitic capacitance formed between the source field plate electrode and the 2DEG via the electron supply layer. Such drain-source parasitic capacitance can limit high-speed and high-frequency operation of the HEMT.
  • a nitride semiconductor device includes an electron transit layer made of a nitride semiconductor; a gate layer partially formed on the electron supply layer from a nitride semiconductor containing an acceptor-type impurity; a gate electrode formed on the gate layer; the electron supply layer, the gate layer, and a passivation layer covering the gate electrode and including a first opening and a second opening; a source electrode in contact with the electron supply layer through the first opening; and the electrons through the second opening. a drain electrode in contact with a supply layer; and a field plate electrode formed on the passivation layer between the gate layer and the drain electrode.
  • the gate layer includes a ridge portion where the gate electrode is located, a source side extension portion extending from the ridge portion toward the first opening, and an extension portion extending from the ridge toward the second opening. and a drain-side extension present.
  • the passivation layer includes a field plate non-overlapping region directly above the drain-side extension that does not overlap with the field plate electrode.
  • a nitride semiconductor device can realize a HEMT structure that achieves both an improvement in drain-source breakdown voltage and a reduction in drain-source parasitic capacitance while improving gate breakdown voltage.
  • FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the first embodiment.
  • FIG. 2 is a partially enlarged cross-sectional view of the nitride semiconductor device of FIG. 3 is a schematic plan view of the nitride semiconductor device taken along line F3-F3 in FIG. 1.
  • FIG. FIG. 4 is a partially enlarged plan view of FIG. 3 showing the connection structure between the source electrode and the field plate electrode of the nitride semiconductor device.
  • 5 is a partially enlarged cross-sectional view of the nitride semiconductor device taken along line F5-F5 of FIG. 4.
  • FIG. FIG. 6 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment.
  • FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the first embodiment.
  • FIG. 2 is a partially enlarged cross-sectional view of the nitride semiconductor device of FIG.
  • FIG. 7 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the third embodiment.
  • FIG. 8 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the fourth embodiment.
  • FIG. 9 is a schematic plan view showing another example of connection structure between the source electrode and the field plate electrode of the nitride semiconductor device.
  • FIG. 10 is a schematic plan view showing still another example of connection structure between the source electrode and the field plate electrode of the nitride semiconductor device.
  • FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to the first embodiment. First, referring to FIG. 1, the overall structure of nitride semiconductor device 10 will be described.
  • the nitride semiconductor device 10 can be configured as, for example, a high electron mobility transistor (HEMT) using a nitride semiconductor such as gallium nitride (GaN).
  • the nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16. including.
  • Substrate 12 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate material.
  • substrate 12 is a conductive Si substrate.
  • the thickness of the substrate 12 may be, for example, 200 ⁇ m or more and 1500 ⁇ m or less.
  • the Z direction of the mutually orthogonal XYZ axes shown in the drawing (for example, FIG. 1) is the direction orthogonal to the main surface of the substrate 12 .
  • the term "planar view" used in this specification refers to viewing the nitride semiconductor device 10 from above along the Z direction, unless otherwise explicitly stated.
  • the buffer layer 14 is located between the substrate 12 and the electron transit layer 16 and can be made of any material that can alleviate the lattice mismatch between the substrate 12 and the electron transit layer 16 .
  • buffer layer 14 includes one or more nitride semiconductor layers.
  • buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and graded AlGaN layers having different aluminum (Al) compositions.
  • the buffer layer 14 may be formed by a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. can be formed.
  • buffer layer 14 includes a first buffer layer formed over substrate 12 and a second buffer layer formed over the first buffer layer.
  • the first buffer layer is, for example, an AlN layer and may have a thickness of the order of 200 nm, for example.
  • the second buffer layer may include, for example, multiple AlGaN layers, each AlGaN layer having a thickness of the order of 100 nm, for example.
  • an impurity may be introduced into a part of the buffer layer 14 to make it semi-insulating.
  • the impurity is, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4 ⁇ 10 16 cm ⁇ 3 or more.
  • the electron transit layer 16 is composed of a nitride semiconductor, and may be, for example, a GaN layer.
  • the electron transit layer 16 can have a thickness of, for example, 0.5 ⁇ m or more and 2 ⁇ m or less.
  • an impurity may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface layer region.
  • the impurity may be C, for example, and the concentration of the impurity may be, for example, 1 ⁇ 10 19 cm ⁇ 3 or higher in peak concentration.
  • the electron supply layer 18 is composed of a nitride semiconductor having a bandgap larger than that of the electron transit layer 16, and may be an AlGaN layer, for example.
  • the bandgap increases as the Al composition increases, so the electron supply layer 18, which is an AlGaN layer, has a larger bandgap than the electron transit layer 16, which is a GaN layer.
  • the electron supply layer 18 is composed of Al x Ga 1-x N, where x is 0.1 ⁇ x ⁇ 0.4, more preferably 0.2 ⁇ x ⁇ 0.3. However, it is not necessarily limited to this range.
  • x may be 0.1 ⁇ x ⁇ 0.3.
  • the electron supply layer 18 can have a thickness of, for example, 5 nm or more and 20 nm or less.
  • the electron transit layer 16 and the electron supply layer 18 are composed of nitride semiconductors having lattice constants different from each other. Therefore, the nitride semiconductor (eg, GaN) forming the electron transit layer 16 and the nitride semiconductor (eg, AlGaN) forming the electron supply layer 18 form a lattice-mismatched junction. Due to the spontaneous polarization of the electron transit layer 16 and the electron supply layer 18 and the piezoelectric polarization caused by the stress applied to the heterojunction of the electron supply layer 18, the electrons in the vicinity of the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 are The energy level of the conduction band of the running layer 16 is lower than the Fermi level.
  • the nitride semiconductor eg, GaN
  • the nitride semiconductor eg, AlGaN
  • a two-dimensional electron gas (2DEG) 20 spreads in the electron transit layer 16 at a position near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (for example, a distance of several nm from the interface).
  • Nitride semiconductor device 10 further covers gate layer 22 formed on electron supply layer 18 , gate electrode 24 formed on gate layer 22 , electron supply layer 18 , gate layer 22 , and gate electrode 24 . and a passivation layer 26 .
  • the gate layer 22 is partially formed on the electron supply layer 18 with a nitride semiconductor containing acceptor-type impurities.
  • Gate layer 22 may be composed of any material that has a smaller bandgap than electron supply layer 18 .
  • the gate layer 22 may be a GaN layer doped with acceptor-type impurities, ie, a p-type GaN layer.
  • Acceptor-type impurities may include, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C).
  • the acceptor-type impurity can have a maximum concentration of, for example, 7 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the gate electrode 24 is formed on part or all of the upper surface of the gate layer 22 and forms a Schottky junction with the gate layer 22 .
  • the gate electrode 24 is composed of one or more metal layers, and may be, for example, a titanium nitride (TiN) layer.
  • the gate electrode 24 may be composed of a first metal layer (eg, Ti layer) and a second metal layer (eg, TiN layer) provided on the first metal layer.
  • the gate electrode 24 can have a thickness of, for example, 50 nm or more and 300 nm or less.
  • the passivation layer 26 is, for example, a silicon nitride (SiN) film, a silicon dioxide (SiO 2 ) film, a silicon oxynitride (SiON) film, an alumina (Al 2 O 3 ) film, an AlN film, and an aluminum oxynitride (AlON) film. or a composite membrane containing any combination of two or more thereof.
  • Passivation layer 26 includes a first opening 26A and a second opening 26B.
  • the gate layer 22 is positioned between the first opening 26A and the second opening 26B.
  • the nitride semiconductor device 10 further includes a source electrode 32 in contact with the electron supply layer 18 through the first opening 26A of the passivation layer 26, and a drain in contact with the electron supply layer 18 through the second opening 26B of the passivation layer 26. and electrodes 34 .
  • Nitride semiconductor device 10 further includes a field plate electrode 36 formed on passivation layer 26 .
  • the source electrode 32, the drain electrode 34, and the field plate electrode 36 are composed of one or more metal layers using, for example, at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. It is for example, source electrode 32, drain electrode 34, and field plate electrode 36 may be formed of the same material. In this case, it is advantageous in that the source electrode 32, the drain electrode 34, and the field plate electrode 36 can all be formed in the same process.
  • At least part of the source electrode 32 is filled in the first opening 26A of the passivation layer 26, and at least part of the drain electrode 34 is filled in the second opening 26B of the passivation layer 26.
  • the source electrode 32 and the drain electrode 34 are in ohmic contact with the 2DEG immediately below the electron supply layer 18 through the first opening 26A and the second opening 26B, respectively.
  • Step structure of gate layer With continued reference to FIG. 1, an exemplary stepped structure of gate layer 22 is described.
  • the gate layer 22 includes a ridge portion 40 where the gate electrode 24 is located, a source-side extension portion 42 extending from the ridge portion 40 toward the first opening 26A of the passivation layer 26, and a portion extending from the ridge portion 40 to the passivation layer 26. and a drain-side extension 44 that extends toward the second opening 26B.
  • the gate layer 22 has a stepped structure with the ridge portion 40 and the extension portions 42 and 44 .
  • the ridge portion 40 corresponds to a relatively thick portion of the gate layer 22 .
  • the ridge portion 40 includes a top surface 40T on which the gate electrode 24 is located, a first ridge end portion 40A continuous with the top surface 40T and from which the source-side extension portion 42 extends, and a drain-side extension portion continuous with the top surface 40T. and a second ridge end 40B from which 44 extends.
  • the ridge portion 40 can have a rectangular shape or a substantially rectangular shape (trapezoidal shape) in a cross section along the XZ plane of FIG.
  • the ridge portion 40 can have a thickness of 80 nm or more and 150 nm or less, for example.
  • the thickness of the ridge portion 40 refers to the distance from the top surface 40T of the ridge portion 40 to the bottom surface (the bottom surface of the gate layer 22 in contact with the electron supply layer 18).
  • the thickness of the gate layer 22 can be appropriately determined in consideration of various parameters such as gate breakdown voltage.
  • the source side extension 42 extends from the first ridge end 40A toward the first opening 26A, while the drain side extension 44 extends from the second ridge end 40B toward the second opening 26B. is extended.
  • the source-side extension 42 includes an end 42A facing the first opening 26A, and the drain-side extension 44 includes an end 44A facing the second opening 26B.
  • An end 42A of the source-side extension 42 is separated from the first opening 26A, and an end 44A of the drain-side extension 44 is separated from the second opening 26B.
  • the drain-side extending portion 44 extends longer outward from the ridge portion 40 than the source-side extending portion 42 in plan view.
  • the source-side extension portion 42 and the drain-side extension portion 44 may have the same length.
  • the source-side extending portion 42 has a length of, for example, 0.2 ⁇ m or more and 0.3 ⁇ m or less (from the first ridge end 40A to the source) in the direction extending from the first ridge end 40A toward the first opening 26A. length to end 42A of side extension 42).
  • the drain-side extending portion 44 has a length of, for example, 0.2 ⁇ m or more and 0.6 ⁇ m or less (the second ridge end portion 40B to the end 44A of the drain-side extension 44).
  • the source-side extension 42 and the drain-side extension 44 each have a slanted portion adjacent to the ridge 40 and a predetermined distance (i.e., slanted portion) from the ridge 40 .
  • at least one of the source-side extending portion 42 and the drain-side extending portion 44 may include only flat portions or only inclined portions.
  • the plateau has a substantially constant thickness.
  • substantially constant thickness means that the thickness is within a manufacturing variation (eg, 20%).
  • the source side extension 42 and the drain side extension 44 may each have a thickness of, for example, 5 nm or more and 25 nm or less.
  • each of the flat portion of the source-side extension portion 42 and the flat portion of the drain-side extension portion 44 may have a thickness of, for example, 5 nm or more and 25 nm or less.
  • FIG. 1 Outline of field plate electrode
  • a field plate electrode 36 is formed on passivation layer 26 between gate layer 22 and drain electrode 34 .
  • Field plate electrode 36 is electrically connected to source electrode 32, although not shown in FIG.
  • the connection structure between field plate electrode 36 and source electrode 32 will be described later with reference to FIGS. 4 and 5.
  • the field plate electrode 36 includes a first electrode end 36A and an opposite second electrode end 36B.
  • the first electrode end portion 36A is the end portion closer to the source electrode 32 (in other words, the side closer to the first ridge end portion 40A), and the second electrode end portion 36B is the end closer to the drain electrode 34. Department.
  • the first electrode end 36 A is physically separated from the source electrode 32 and the second electrode end 36 B is physically separated from the drain electrode 34 .
  • the second electrode end portion 36B faces the drain electrode 34 .
  • the field plate electrode 36 extends in the direction in which the drain-side extension 44 extends from the ridge 40 toward the second opening 26B (the X direction in FIG. 1: hereinafter referred to as the extension direction X of the drain-side extension 44). ), it may have a length greater than the length of the drain-side extension 44 .
  • the length of the field plate electrode 36 is the length from the first electrode end portion 36A of the field plate electrode 36 to the second electrode end portion 36B.
  • the field plate electrode 36 and the drain-side extension 44 may have the same length.
  • the field plate electrode 36 can have a length of 0.5 ⁇ m or more and 2 ⁇ m or less in the extension direction X, for example.
  • the field plate electrode 36 is arranged on the passivation layer 26 at a position that does not overlap the entire gate layer 22 or overlaps a part of the drain-side extension 44 of the gate layer 22 in plan view. In the example of FIG. 1, the field plate electrode 36 slightly overlaps the tip portion of the drain-side extension 44 in plan view. Note that the field plate electrode 36 does not entirely overlap the drain-side extending portion 44 in plan view, nor does it overlap the ridge portion 40 and the source-side extending portion 42 in plan view.
  • FIG. 2 is a partially enlarged cross-sectional view of nitride semiconductor device 10 of FIG.
  • the field plate electrode 36 is arranged on the passivation layer 26 at a position that does not overlap the entire gate layer 22 or overlaps a portion of the drain-side extension 44 in plan view. Therefore, the passivation layer 26 includes a field plate non-overlapping region 26RA that does not overlap with the field plate electrode 36 directly above the drain-side extension 44 .
  • passivation layer 26 also includes field plate overlapping region 26RB that overlaps field plate electrode 36 directly above drain-side extension 44 . That is, the passivation layer 26 has a field plate non-overlapping region 26RA (hereinafter simply referred to as “non-overlapping region 26RA”) and a field plate overlapping region 26RB (hereinafter simply “overlapping region 26RB”) directly above the drain-side extending portion 44. ) and The area of the non-overlapping region 26RA is larger than the area of the overlapping region 26RB.
  • the non-overlapping region 26RA has a length L1 and the overlapping region 26RB has a length L2.
  • the length L2 is smaller than the length L1, and the sum of the length L1 and the length L2 corresponds to the length L3 of the drain side extension portion 44 in the extension direction X.
  • the non-overlapping region 26RA may include both the sloped portion and the flat portion of the drain-side extension portion 44, or may include only the sloped portion or the flat portion.
  • the overlap region 26RB may include both the sloped portion and the flat portion of the drain-side extension portion 44, or may include only the sloped portion or only the flat portion.
  • part of the source electrode 32 may also be disposed on the passivation layer 26, but not only the field plate electrode 36 but also the source electrode 32 is present on the non-overlapping region 26RA of the passivation layer 26. not. Therefore, source electrode 32 is provided on passivation layer 26 outside non-overlapping region 26RA.
  • the field plate electrode 36 has a first portion 36RA that does not overlap the drain-side extension portion 44 in plan view and a second portion 36RB that overlaps the drain-side extension portion 44 in plan view. including.
  • the first portion 36RA has a length L4 and the second portion 36RB has a length L2. That is, the length L2 of the overlap region 26RB of the passivation layer 26 corresponds to the length L2 of the second portion 36RB of the field plate electrode 36 overlapping the drain-side extension portion 44 .
  • the length L4 is greater than the length L2, and the sum of the length L4 and the length L2 corresponds to the length L5 of the field plate electrode 36 in the extension direction X.
  • the length L5 of the field plate electrode 36 may be greater than the length L3 of the drain-side extension 44.
  • the length L5 of the field plate electrode 36 is, for example, 0.5 ⁇ m or more and 2 ⁇ m or less
  • the length L3 of the drain-side extension portion 44 is, for example, 0.2 ⁇ m or more and 0.6 ⁇ m or less.
  • the length L5 of the field plate electrode 36 may be 1.5 times or more the length L3 of the drain-side extension 44 .
  • the length L4 of the first portion 36RA of the field plate electrode 36 that does not overlap with the drain-side extension portion 44 may be, for example, 0.4 ⁇ m or more and 2 ⁇ m or less.
  • the length L4 of the first portion 36RA of the field plate electrode 36 may be greater than or equal to the length L3 of the drain-side extension portion 44.
  • the field plate electrode 36 is positioned closer to the gate layer 22 between the gate layer 22 and the drain electrode 34 .
  • the second electrode end portion 36B of the field plate electrode 36 is positioned closer to the field plate electrode 36 than the intermediate position MP between the opening end 26BE of the second opening portion 26B located closer to the field plate electrode 36 and the second ridge end portion 40B of the ridge portion 40. It is located near the second ridge end portion 40B.
  • a high voltage such as a surge (for example, about 150 V) may be momentarily applied to the drain electrode 34 .
  • a high voltage such as a surge (for example, about 150 V) may be momentarily applied to the drain electrode 34 .
  • an equivalent high voltage may be applied to the passivation layer 26 and the electron supply layer 18 immediately below the field plate electrode 36 . This causes dielectric breakdown of the passivation layer 26 and the electron supply layer 18 .
  • the second electrode end portion 36B of the field plate electrode 36 is closer to the gate layer 22 (the second ridge end portion) than the intermediate position MP so that the field plate electrode 36 is positioned farther from the drain electrode 34 . 40B) is located nearer.
  • FIG. 3 is a schematic plan view along line F3-F3 of FIG. 1 showing an exemplary formation pattern 100 of nitride semiconductor device 10 of FIG.
  • hatching indicating a cross section is omitted.
  • illustration of the gate electrode 24 is omitted in FIG.
  • the formation pattern 100 alternately includes active regions 102 that contribute to transistor operation and non-active regions 104 that do not contribute to transistor operation.
  • source electrode 32, gate layer 22 having gate electrode 24 (not shown in FIG. 3), field plate electrode 36, and drain electrode 34 are arranged side by side in one direction within active region 102.
  • it is configured as a HEMT.
  • the HEMT operates when a predetermined voltage is applied to the gate electrode 24 and current flows between the source and the drain in the active region 102 .
  • nitride semiconductor devices 10 are continuously formed in the X direction.
  • Each nitride semiconductor device 10 shown in FIG. 3 corresponds to the nitride semiconductor device 10 shown in FIG. That is, FIG. 1 shows one nitride semiconductor device 10 formed in the active region 102 .
  • the passivation layer 26 includes a non-overlapping region 26RA that does not overlap the field plate electrode 36 directly above the drain-side extension 44. As shown in FIG. This non-overlapping region 26RA is substantially the entire region of the passivation layer 26 located directly above the drain-side extension 44. As shown in FIG. In the active region 102 , the field plate electrode 36 overlaps the end portion 44 ⁇ /b>A of the drain-side extending portion 44 (part including it) in plan view, but is separated from the source electrode 32 .
  • the field plate electrode 36 is elongated in the direction (Y direction) along the gate layer 22 in plan view.
  • field plate electrode 36 may be formed with a length across active area 102 in a direction along gate layer 22 .
  • Field plate electrode 36 may also be formed with a length in the direction along gate layer 22 greater than the length of source electrode 32 (and drain electrode 34).
  • FIG. 4 is a partially enlarged plan view of FIG. 3 showing the electrical connection structure between the source electrode 32 and the field plate electrode 36.
  • FIG. FIG. 5 is a partially enlarged cross-sectional view of nitride semiconductor device 10 taken along line F5-F5 in FIG. Note that FIG. 5 shows one nitride semiconductor device 10 .
  • nitride semiconductor device 10 includes interlayer insulating layer 52 (not shown in FIG. 4), first via 54, second via 56, and source wiring 58. there is First via 54 and second via 56 are conductors or wires.
  • An interlayer insulating layer 52 covers the source electrode 32 , the drain electrode 34 , the field plate electrode 36 and the passivation layer 26 .
  • the first via 54 penetrates the interlayer insulating layer 52 and is connected to the source electrode 32
  • the second via 56 penetrates the interlayer insulating layer 52 and is connected to the field plate electrode 36 .
  • the source wiring 58 is formed on the interlayer insulating layer 52 and connected to the first via 54 and the second via 56 . Therefore, field plate electrode 36 is electrically connected to source electrode 32 through second via 56 , source wiring 58 and first via 54 .
  • the nitride semiconductor device 10 further includes a third via 62 penetrating the interlayer insulating layer 52 and connected to the drain electrode 34, and an interlayer insulating and a drain line 64 formed on the layer 52 and connected to the third via 62 . Therefore, a drain voltage is applied to the drain electrode 34 through the drain wiring 64 and the third via 62 .
  • the nitride semiconductor device 10 includes a gate layer 22 provided as a nitride semiconductor layer (for example, a p-type GaN layer) containing acceptor-type impurities.
  • the gate layer 22 includes a ridge portion 40 and a source side extension portion 42 and a drain side extension portion 44 extending in opposite directions from the ridge portion 40 .
  • the source-side extending portion 42 and the drain-side extending portion 44 allow the lines of electric force concentrated at the lower end of the ridge portion 40 during the gate positive bias to escape to the respective extending portions 42 and 44 , thereby increasing the X-direction potential in the gate layer 22 . can be equalized.
  • the intensity of the electric field applied to the ends of the gate electrode 24 can be reduced, so that the generation of gate leak current when a high gate voltage is applied can be suppressed, and the gate withstand voltage can be improved.
  • Nitride semiconductor device 10 also includes field plate electrode 36 provided on passivation layer 26 between gate layer 22 (gate electrode 24 ) and drain electrode 34 .
  • the field plate electrode 36 plays a role of extending the depletion layer from the field plate electrode 36 toward the 2DEG 20 immediately below when a high voltage is applied to the drain electrode 34, thereby reducing electric field concentration occurring in the region between the drain and the source. ease.
  • the vicinity of the edge of the gate electrode 24 near the drain electrode 34 (for example, the second ridge edge 40B and the edge 44A of the drain-side extension 44, etc.) This is a location where an electric field tends to concentrate. Electric field concentration at these locations is effectively alleviated by the extension of the depletion layer directly below the field plate electrode 36 . As a result, dielectric breakdown of the electron supply layer 18 and the passivation layer 26 due to local electric field concentration can be suppressed, and the drain-source withstand voltage can be improved.
  • the electron supply layer 18 (and part of the drain-side extension 44) and the passivation layer 26 are interposed between the field plate electrode 36 and the 2DEG 20. It has a parasitic capacitance that forms. This parasitic capacitance increases according to the area of the field plate electrode 36 arranged in the drain-source region.
  • the passivation layer 26 includes a field plate non-overlapping region 26RA directly above the drain-side extension 44 that does not overlap with the field plate electrode 36 (ie field plate electrode 36 is not present).
  • the drain-source parasitic capacitance can be reduced by increasing the area of the non-overlapping region 26RA (that is, decreasing the area of the overlapping region 26RB).
  • the nitride semiconductor device 10 of the first embodiment has the following advantages.
  • (1-1) The gate layer 22 includes a ridge portion 40 , a source side extension portion 42 and a drain side extension portion 44 .
  • the source-side extending portion 42 and the drain-side extending portion 44 can reduce the intensity of the electric field applied to the end portion of the gate electrode 24 when the gate is positively biased. be able to.
  • a field plate electrode 36 is provided on the passivation layer 26 between the gate layer 22 and the drain electrode 34 .
  • the field plate electrode 36 extends a depletion layer from the field plate electrode 36 toward the 2DEG 20 immediately below when a high voltage is applied to the drain electrode 34, thereby relaxing the electric field concentration in the drain-source region. Bring.
  • dielectric breakdown of the electron supply layer 18 and the passivation layer 26 due to local electric field concentration can be suppressed, and the drain-source withstand voltage can be improved.
  • the passivation layer 26 includes a field plate non-overlapping region 26RA that does not overlap with the field plate electrode 36 directly above the drain-side extension 44 .
  • no parasitic capacitance is formed in the non-overlapping region 26RA because the field plate electrode 36 does not exist on the non-overlapping region 26RA. This can reduce the parasitic capacitance between the drain and the source.
  • by increasing the area of the non-overlapping region 26RA that is, decreasing the area of the overlapping region 26RB), the parasitic capacitance between the drain and the source can be further reduced.
  • the entire gate layer 22 (that is, the entire ridge portion 50 and the extension portions 42 and 44) is By providing the covering field plate electrode, the gate breakdown voltage and the drain-source breakdown voltage can be improved.
  • the existence of the field plate electrode increases the parasitic capacitance between the drain and the source, which may limit the high-speed and high-frequency operation of the HEMT.
  • the passivation layer 26 includes a field plate non-overlapping region 26RA that does not overlap the field plate electrode 36 directly above the drain-side extension 44 .
  • the field plate electrode 36 overlaps the end portion 44A of the drain-side extension portion 44 in plan view (however, it does not overlap the entire drain-side extension portion 44).
  • the electric field concentrated on the end portion 44A of the drain-side extension portion 44 can be relaxed by the field plate electrode 36. can. That is, electric field concentration at the end portion 44A of the drain-side extension portion 44 can be alleviated while reducing the drain-source parasitic capacitance.
  • the field plate electrode 36 is separated from the source electrode 32 within the active region 102 .
  • the source electrode 32 also has a region provided on the passivation layer 26 at a position that does not overlap the drain-side extension portion 44 of the gate layer 22 in plan view.
  • the source electrode 32 has a region provided on the passivation layer 26 at a position that does not overlap not only the drain-side extension portion 44 but also the ridge portion 40 and the source-side extension portion 42 . ing.
  • FIG. 1 only a portion of field plate electrode 36 resides on passivation layer 26 directly above drain-side extension 44 . With this configuration, the drain-source parasitic capacitance can be effectively reduced.
  • the field plate electrode 36 includes an electrode end portion 36B facing the drain electrode 34;
  • the electrode end portion 36B is located closer to the second ridge end portion 40B than the intermediate position MP between the opening end 26BE of the second opening portion 26B located closer to the field plate electrode 36 and the second ridge end portion 40B.
  • the field plate electrode 36 is positioned further away from the drain electrode 34 .
  • concentration of an electric field on the passivation layer 26 and the electron supply layer 18 immediately below the field plate electrode 36 can be suppressed when a high voltage such as a surge is applied to the drain electrode 34 .
  • dielectric breakdown of the passivation layer 26 and the electron supply layer 18 can be suppressed.
  • the field plate electrode 36 can have a length L5 larger than the length L3 of the drain-side extension 44 in the extension direction X of the drain-side extension 44 . According to this configuration, the breakdown voltage between the drain and the source can be improved by the field plate electrode 36 having a larger area while improving the gate breakdown voltage and reducing the parasitic capacitance between the drain and the gate.
  • the field plate electrode 36 includes a first portion 36RA that does not overlap the drain-side extending portion 44 in plan view.
  • the first portion 36RA can have a length L4 in the extending direction X of the drain-side extending portion 44 that is equal to or greater than the length L3 of the drain-side extending portion 44. As shown in FIG. According to this configuration, it is possible to effectively achieve both a reduction in drain-gate parasitic capacitance and an improvement in drain-source breakdown voltage.
  • the (1-10) field plate electrode 36 can be made of the same material as the source electrode 32 and the drain electrode 34 . This configuration is advantageous in that the source electrode 32, the drain electrode 34, and the field plate electrode 36 can all be formed in the same process.
  • the (1-11) field plate electrode 36 may have a length greater than the length of the source electrode 32 in the direction along the gate layer 22 . According to this configuration, the drain-source breakdown voltage can be improved by the field plate electrode 36 having a larger area.
  • FIG. 6 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10A according to the second embodiment.
  • the same reference numerals are assigned to the same components as those of the nitride semiconductor device 10 according to the first embodiment.
  • descriptions of components that are the same as those of the first embodiment are omitted, and components that are different from those of the first embodiment are described.
  • the nitride semiconductor device 10A according to the second embodiment has a field plate electrode 361 instead of the field plate electrode 36 (see FIG. 1) of the first embodiment. It differs from the nitride semiconductor device 10 according to the embodiment. Other configurations are the same as those of the first embodiment.
  • the field plate electrode 361 is arranged on the passivation layer 26 at a position that does not overlap the drain-side extension 44 of the gate layer 22 in plan view. Therefore, in the second embodiment, the field plate electrode 361 includes the entire field plate electrode 361 as a first portion 361RA that does not overlap the drain-side extension portion 44 in plan view. For this reason, in the second embodiment, the passivation layer 26 includes the entire region of the passivation layer 26 immediately above the drain-side extension portion 44 as the field plate non-overlapping region 26RA. Note that structural features similar to those of the first embodiment can be employed in the second embodiment, except that the field plate electrode 361 does not overlap the drain-side extension portion 44 .
  • the nitride semiconductor device 10A of the second embodiment has the following advantages in addition to the advantages (1-1) to (1-4) and (1-6) to (1-11) of the first embodiment. have. (2-1)
  • the field plate electrode 361 does not overlap the drain-side extension 44 in plan view.
  • the passivation layer 26 includes all regions of the passivation layer 26 immediately above the drain-side extensions 44 as field plate non-overlapping regions 26RA. In this configuration, the parasitic capacitance caused by the field plate electrode 361 does not exist in the region of the drain-side extension 44, so the parasitic capacitance between the drain and the source can be minimized.
  • FIG. 7 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10B according to the third embodiment.
  • the same reference numerals are assigned to the same components as those of the nitride semiconductor device 10 according to the first embodiment.
  • descriptions of components that are the same as those of the first embodiment are omitted, and components that are different from those of the first embodiment are described.
  • the nitride semiconductor device 10B according to the third embodiment differs from the first embodiment in that it has a source electrode 321 instead of the source electrode 32 (see FIG. 1) of the first embodiment. It is different from the nitride semiconductor device 10 concerned. Other configurations are the same as those of the first embodiment.
  • the source electrode 321 extends over the passivation layer 26 from the position of the first opening 26A of the passivation layer 26 to a position overlapping the source-side extension 42 of the gate layer 22 in plan view.
  • the end portion 321A of the source electrode 321 is positioned on the flat portion of the source-side extending portion 42, but it may be positioned on the inclined portion of the source-side extending portion 42. good.
  • the source electrode 321 only needs to partially or entirely cover the source-side extension 42 .
  • the source electrode 321 does not cover the ridge portion 40 of the gate layer 22 . Note that structural features similar to those of the first embodiment can be employed in the third embodiment, except that the source electrode 321 overlaps the source-side extension portion 42 .
  • the nitride semiconductor device 10B of the third embodiment has the following advantages in addition to the advantages (1-1) to (1-5) and (1-7) to (1-11) of the first embodiment. have. (3-1)
  • the source electrode 321 overlaps the source-side extension 42 in plan view. If the source electrode 321 does not overlap the source-side extension 42, the gate-source parasitic capacitance formed between the source electrode 321 and the 2DEG 20 is reduced. However, a reduction in gate-source parasitic capacitance can lead to self-turn-on.
  • Self-turn-on is C gd expressed by the ratio of the gate-drain parasitic capacitance C gd to the gate-source parasitic capacitance C gs when a voltage is applied steeply between the drain and source of the HEMT in the OFF state. This is a phenomenon in which the HEMT is turned on by applying a gate voltage exceeding the threshold voltage to the gate-source parasitic capacitance C gs according to /C gs . This ratio C gd /C gs increases as the gate-source parasitic capacitance C gs decreases.
  • the passivation layer 26 includes a non-overlapping region 26RA that does not overlap the field plate electrode 36 directly above the drain-side extension 44, as in the first embodiment. Therefore, the gate-drain parasitic capacitance C gd is reduced (compared to the configuration without the non-overlapping region 26RA). As a result, it is possible to effectively suppress the increase in the ratio C gd /C gs and suppress the occurrence of self-turn-on.
  • FIG. 8 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10C according to the fourth embodiment.
  • the same reference numerals are assigned to the same components as those of the nitride semiconductor device 10 according to the first embodiment.
  • descriptions of components that are the same as those of the first embodiment are omitted, and components that are different from those of the first embodiment are described.
  • the nitride semiconductor device 10C according to the fourth embodiment differs from the first embodiment in that it has a source electrode 322 instead of the source electrode 32 (see FIG. 1) of the first embodiment. It is different from the nitride semiconductor device 10 concerned. Other configurations are the same as those of the first embodiment.
  • the source electrode 322 extends over the passivation layer 26 from the position of the first opening 26A of the passivation layer 26 to a position overlapping the gate electrode 24 in plan view.
  • the source electrode 322 covers the entire gate electrode 24, and the end portion 322A of the source electrode 322 is located on the ridge portion 40, but covers part of the gate electrode 24.
  • structural features similar to those of the first embodiment can also be employed in the fourth embodiment, except that the source electrode 322 overlaps the gate electrode 24 .
  • the nitride semiconductor device 10C of the fourth embodiment includes (1-1) to (1-5) and (1-7) to (1-11) of the first embodiment and (3-1 ), it has the following advantages:
  • the source electrode 322 overlaps the gate electrode 24 in plan view. Therefore, compared with the case of using the source electrode 321 of the third embodiment, it is possible to further suppress the reduction of the gate-source parasitic capacitance Cgs , thereby suppressing the occurrence of self-turn-on. As a result, the increase in the ratio C gd /C gs can be more effectively suppressed, and the occurrence of self-turn-on can be suppressed.
  • connection structure between the source electrode 32 and the field plate electrode 36 may be changed as shown in FIG.
  • FIG. 9 is a schematic plan view showing an example of another connection structure. It should be noted that the modified example of FIG. 9 described below can be similarly applied not only to the first embodiment but also to the second to fourth embodiments.
  • the nitride semiconductor device 10 includes an annular electrode 110, which includes a field plate electrode 112, a source electrode 114, and two connection wirings 116,118.
  • the field plate electrode 112 corresponds to the field plate electrode 36 of the first embodiment
  • the source electrode 114 corresponds to the source electrode 32 of the first embodiment.
  • the source electrode 114 has the same length in the Y direction as the field plate electrode 112 .
  • connection wirings 116, 118 are formed in the same layer as the field plate electrode 112 and the source electrode 114, and connect the field plate electrode 112 and the source electrode 114 in a ring.
  • Field plate electrode 112 and source electrode 114 are disposed within active area 102 .
  • connection wirings 116 and 118 are arranged within the non-active region 104 .
  • the ring-shaped electrode 110 electrically connects the field plate electrode 112 and the source electrode 114 via the connection wirings 116 and 118 .
  • the annular electrode 110 as shown in FIG. 9 can be In this case, since the connection wirings 116 and 118 are arranged in the non-active region 104, the influence of the connection wirings 116 and 118 on the device layout and device operation in the active region 102 can be reduced. Advantages similar to those of the above-described embodiments can be obtained even when the connection structure of FIG. 9 is adopted.
  • connection structure between the source electrode 32 and the field plate electrode 36 may be changed as shown in FIG.
  • FIG. 10 is a schematic plan view showing yet another example of connection structure. 10 described below can be applied not only to the first embodiment but also to the second to fourth embodiments.
  • nitride semiconductor device 10 includes field plate electrode 362 .
  • the field plate electrode 362 is arranged at a position that does not overlap with the drain-side extending portion 44 , but may be arranged so as to partially overlap with the drain-side extending portion 44 .
  • Field plate electrode 362 has a length greater than the length of source electrode 32 in the direction along gate layer 22 .
  • the field plate electrode 362 includes an electrode body 362A and an electrode connection portion 362B. Electrode body 362 A is disposed within active area 102 . On the other hand, the electrode connecting portion 362B is arranged within the non-active region 104. As shown in FIG. The electrode connection portion 362B has a width (length in the X direction) greater than that of the electrode main body 362A. A via 364 penetrating the interlayer insulating layer 52 (see FIG. 5) is connected to the electrode connecting portion 362B. Via 364 is a conductor or wire. Although not shown in detail, the electrode body 362A of the field plate electrode 362 is connected to the source wiring 58 via the electrode connecting portion 362B, the via 364, and other wiring on the interlayer insulating layer 52.
  • the electrode connection portion 362B is arranged in the non-active region 104, so that the influence of the electrode connection portion 362B on the device layout and device operation in the active region 102 can be reduced. Advantages similar to those of the above-described embodiments can be obtained even when the connection structure of FIG. 10 is employed.
  • the width and shape of the electrode connection portion 362B and the number of vias 364 can be changed arbitrarily.
  • the potential of the field plate electrode 36 instead of connecting the field plate electrode 36 to the source electrode 32, the potential of the field plate electrode 36 may be set to the source potential by an arbitrary potential setting circuit.
  • the field plate electrode 36 may be formed of a material different from that of the source electrode 32 and the drain electrode 34 .
  • the number of HEMTs formed in the active region 102 is not particularly limited.
  • a first layer is formed over a second layer means that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other implementations The configuration contemplates that the first layer may be positioned above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first and second layers.
  • each of the above-described embodiments in which the electron supply layer 18 is formed on the electron transit layer 16 has a structure in which an intermediate layer is positioned between the electron supply layer 18 and the electron transit layer 16 in order to stably form the 2DEG 20. Also includes
  • the Z-axis direction used in the present disclosure does not necessarily have to be the vertical direction, nor does it have to completely match the vertical direction.
  • various structures according to the present disclosure e.g., the structure shown in FIG. 1 are configured such that the Z-axis "top” and “bottom” described herein are the vertical “top” and “bottom” It is not limited to one thing.
  • the X-axis direction may be vertical, or the Y-axis direction may be vertical.
  • appendix A2 The nitride semiconductor device (10A) according to appendix A1, wherein the field plate non-overlapping region (26RA) is the entire region of the passivation layer (26) immediately above the drain-side extension (44).
  • Appendix A4 The source electrode (32), the gate layer (22) with the gate electrode (24) disposed thereon, the field plate electrode (36) and the drain electrode (34) are unidirectionally disposed within the active area (102). are placed next to each other, said field plate electrode (36) is spaced from said source electrode (32) within said active area (102); Any one of Appendices A1 to A3, wherein the source electrode (32) has a region provided on the passivation layer (26) at a position not overlapping with the drain-side extension (44) in plan view.
  • Appendix A5 The nitride semiconductor according to any one of Appendixes A1 to A4, wherein the source electrode (32) is provided on the passivation layer (26) outside the field plate non-overlapping region (26RA).
  • the ridge portion (40) is a top surface (40T) on which the gate electrode (24) is located; a first ridge end (40A) continuous with the upper surface (40T) and from which the source-side extension (42) extends; a second ridge end (40B) continuous with the upper surface (40T) and from which the drain-side extension (44) extends; said field plate electrode (36) includes an electrode end (36B) opposite said drain electrode (34); The electrode end (36B) is located at an intermediate position (MP ), the nitride semiconductor device (10; 10A; 10B; 10C) according to any one of Appendices A1 to A5, which is located closer to the second ridge end (40B) than ).
  • the field plate electrode (36) extends from the ridge (40) toward the second opening (26B) in the extending direction (X) in which the drain-side extending portion (44) extends toward the second opening (26B).
  • the nitride semiconductor device (10; 10A; 10B; 10C) according to any one of Appendices A1 to A6, having a length (L5) greater than the length (L3) of the side extending portion (44). ).
  • the field plate electrode (36) includes a first portion (36RA) that does not overlap the drain-side extension (44) in plan view,
  • the first portion (36RA) of the field plate electrode (36) is the length (L3 ) or more, the nitride semiconductor device (10; 10A; 10B; 10C) according to appendix A7.
  • the field plate electrode (36) includes a first portion (36RA) that does not overlap the drain-side extension (44) in plan view,
  • the length (L3) of the drain-side extension (44) is 0.2 ⁇ m or more and 0.6 ⁇ m or less, Note that the length (L4) of the first portion (36RA) of the field plate electrode (36) in the extending direction (X) of the drain-side extending portion (44) is 0.4 ⁇ m or more and 2 ⁇ m or less.
  • the field plate electrode (36) includes a second portion (36RB) that overlaps the drain-side extension (44) in plan view,
  • the source electrode (321) extends over the passivation layer (26) from the position of the first opening (26A) to a position overlapping with the source-side extension (42) in plan view.
  • the nitride semiconductor device (10B) according to any one of Appendices A1 to A11.
  • the source electrode (322) extends over the passivation layer (26) from the position of the first opening (26A) to a position overlapping with the gate electrode (24) in plan view.
  • the nitride semiconductor device (10C) according to any one of A1 to A12.
  • Appendix A14 The nitride semiconductor device (10; 10A; 10B) according to any one of Appendices A1 to A13, wherein the source electrode (32) and the field plate electrode (36) are electrically connected to each other. 10C).
  • the source electrode (32) and the field plate electrode (36) are elongated in a direction along the gate layer (22) in plan view, any one of Appendixes A1 to A15, wherein the field plate electrode (36) has a length in a direction along the gate layer (22) greater than the length of the source electrode (32)
  • the field plate electrode (362) comprises: an electrode body (362A) extending along the gate layer (22); an electrode connection portion (362B) having a width larger than the width of the electrode body portion (362A) in a direction orthogonal to the gate layer (22) in plan view;
  • connection wiring (116; 118) connecting the source electrode (114) and the field plate electrode (112);
  • the source electrode (114), the gate layer (22) on which the gate electrode (24) is arranged, the field plate electrode (114) and the drain electrode (34) are unidirectionally disposed within the active area (102). are placed next to each other, A nitride semiconductor device (10; 10A; 10B; 10C).
  • connection wiring (116; 118) is one of two connection wirings (116, 118) connecting the source electrode (114) and the field plate electrode (112); 10A; 10A; 10B; 10).
  • the electron transit layer (16) is a GaN layer
  • the electron supply layer (18) is an Al x Ga 1-x N layer (0.1 ⁇ x ⁇ 0.3)
  • the nitride semiconductor device (10; 10A; 10B) according to any one of Appendices A1 to A19, wherein the gate layer (22) is a GaN layer containing at least one of Mg and Zn as the acceptor-type impurity. ; 10C).

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074279A (ja) * 2011-09-29 2013-04-22 Fujitsu Ltd 半導体装置及びその製造方法
JP2013157407A (ja) * 2012-01-27 2013-08-15 Fujitsu Semiconductor Ltd 化合物半導体装置及びその製造方法
JP2016139718A (ja) * 2015-01-28 2016-08-04 株式会社東芝 半導体装置
JP2019102756A (ja) * 2017-12-07 2019-06-24 住友電工デバイス・イノベーション株式会社 半導体装置
WO2020213291A1 (ja) * 2019-04-15 2020-10-22 ローム株式会社 窒化物半導体装置およびその製造方法
JP2020184609A (ja) * 2019-04-30 2020-11-12 イノサイエンス （チューハイ） テクノロジー カンパニー リミテッドＩｎｎｏｓｃｉｅｎｃｅ （Ｚｈｕｈａｉ） Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． 半導体デバイス及びその製造方法
JP2022027722A (ja) * 2020-07-31 2022-02-14 台湾積體電路製造股▲ふん▼有限公司 段階的フィールドプレートを備えた窒化ガリウム系デバイス及びその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074279A (ja) * 2011-09-29 2013-04-22 Fujitsu Ltd 半導体装置及びその製造方法
JP2013157407A (ja) * 2012-01-27 2013-08-15 Fujitsu Semiconductor Ltd 化合物半導体装置及びその製造方法
JP2016139718A (ja) * 2015-01-28 2016-08-04 株式会社東芝 半導体装置
JP2019102756A (ja) * 2017-12-07 2019-06-24 住友電工デバイス・イノベーション株式会社 半導体装置
WO2020213291A1 (ja) * 2019-04-15 2020-10-22 ローム株式会社 窒化物半導体装置およびその製造方法
JP2020184609A (ja) * 2019-04-30 2020-11-12 イノサイエンス （チューハイ） テクノロジー カンパニー リミテッドＩｎｎｏｓｃｉｅｎｃｅ （Ｚｈｕｈａｉ） Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． 半導体デバイス及びその製造方法
JP2022027722A (ja) * 2020-07-31 2022-02-14 台湾積體電路製造股▲ふん▼有限公司 段階的フィールドプレートを備えた窒化ガリウム系デバイス及びその製造方法

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