WO2023156877A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023156877A1
WO2023156877A1 PCT/IB2023/051027 IB2023051027W WO2023156877A1 WO 2023156877 A1 WO2023156877 A1 WO 2023156877A1 IB 2023051027 W IB2023051027 W IB 2023051027W WO 2023156877 A1 WO2023156877 A1 WO 2023156877A1
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Prior art keywords
conductor
insulator
oxide
transistor
oxygen
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Ceased
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PCT/IB2023/051027
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
大貫達也
國武寛司
方堂涼太
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US18/838,307 priority Critical patent/US20250151295A1/en
Priority to JP2024500694A priority patent/JPWO2023156877A1/ja
Priority to KR1020247030538A priority patent/KR20240149947A/ko
Priority to CN202380021364.5A priority patent/CN118872401A/zh
Publication of WO2023156877A1 publication Critical patent/WO2023156877A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Definitions

  • One embodiment of the present invention relates to semiconductor devices, memory devices, and electronic devices. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), Their driving method or their manufacturing method can be mentioned as an example.
  • a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices.
  • a display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to include a semiconductor device in some cases.
  • LSIs Large Scale Integration
  • CPUs Central Processing Units
  • GPUs Graphic Processing Units
  • memories storage devices
  • These semiconductor devices are used in various electronic devices such as computers and personal digital assistants.
  • memories of various storage methods have been developed according to their uses, such as temporary storage during execution of arithmetic processing and long-term storage of data. Examples of typical memory systems include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.
  • Patent Document 1 and Non-Patent Document 1 disclose a memory cell formed by stacking transistors.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.
  • An object of one embodiment of the present invention is to provide a semiconductor device in which variations in electrical characteristics of transistors are small.
  • An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high on-state current.
  • An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.
  • An object of one embodiment of the present invention is to provide a memory device that occupies a small area.
  • An object of one embodiment of the present invention is to provide a highly reliable storage device.
  • An object of one embodiment of the present invention is to provide a memory device with low power consumption.
  • An object of one embodiment of the present invention is to provide a novel storage device.
  • One aspect of the present invention includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor.
  • each of the first memory cell and the second memory cell includes a transistor, a capacitor, a first insulator, and a second insulator; the transistor is on the first insulator;
  • a capacitive element including a metal oxide, a third conductor, a fourth conductor, a third insulator over the metal oxide, and a fifth conductor over the third insulator has a sixth conductor, a fourth insulator over the sixth conductor, a seventh conductor over the fourth insulator, the second insulator overlying the transistor
  • a portion where the sixth conductor, the fourth insulator, and the seventh conductor overlap is positioned on the second insulator, and through the opening provided in the second insulator , a third conductor, and a sixth conductor are electrically connected, the first conductor has a portion in contact with a fourth
  • the first conductor is preferably in contact with part of the top surface and part of the side surface of the fourth conductor included in the first memory cell.
  • the first conductor is preferably in contact with part of the top surface, part of the side surface, and part of the bottom surface of the fourth conductor included in the first memory cell.
  • the fourth conductor preferably has a portion positioned outside the end of the first insulator.
  • a portion where the first insulator, the metal oxide, the third insulator, and the fifth conductor of the second memory cell overlap with each other is located on the seventh conductor of the first memory cell. is preferred.
  • the fourth insulator preferably comprises one or both of zirconium oxide and aluminum oxide.
  • a portion of the seventh conductor is preferably located in an opening provided in the second insulator.
  • the transistor of the second memory cell preferably has an eighth conductor.
  • the eighth conductor is located on the second insulator of the first memory cell and preferably has the same material as the seventh conductor.
  • a portion where the first insulator, the metal oxide, the third insulator, and the fifth conductor of the second memory cell overlap is preferably positioned over the eighth conductor.
  • the end of the sixth conductor is preferably covered with a fourth insulator.
  • the ends of the sixth conductor are preferably aligned or substantially aligned with the ends of the seventh conductor.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high operating speed can be provided.
  • a semiconductor device with favorable electrical characteristics can be provided.
  • a semiconductor device with little variation in electrical characteristics of transistors can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device with low power consumption can be provided.
  • One embodiment of the present invention can provide a novel semiconductor device.
  • a storage device with a large storage capacity can be provided.
  • a memory device that occupies a small area can be provided.
  • a highly reliable storage device can be provided.
  • a memory device with low power consumption can be provided.
  • An aspect of the present invention can provide a novel storage device.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 2 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 3 is a cross-sectional view showing an example of a semiconductor device.
  • 4A and 4B are cross-sectional views showing examples of semiconductor devices.
  • 5A and 5B are cross-sectional views showing examples of semiconductor devices.
  • 6A and 6B are cross-sectional views showing examples of semiconductor devices.
  • FIG. 7 is a cross-sectional view showing an example of a semiconductor device.
  • 8A and 8B are top views showing an example of a semiconductor device.
  • 9A and 9B are top views showing an example of a semiconductor device.
  • 10A to 10C illustrate an example of a method for manufacturing a semiconductor device.
  • 11A and 11B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 12A to 12C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 13A and 13B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 14A to 14C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 15A to 15C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 16A to 16C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 17A and 17B are perspective views showing an example of a semiconductor device.
  • FIG. 18 is a block diagram illustrating an example of a storage device;
  • FIG. 19A is a schematic diagram showing an example of a storage device.
  • FIG. 19B is a schematic diagram and a circuit diagram showing an example of a memory device.
  • 20A and 20B are schematic diagrams showing an example of a storage device.
  • FIG. 21 is a circuit diagram showing an example of a memory device.
  • FIG. 22 is a timing chart for explaining an operation example of the storage device.
  • 23A and 23B are circuit diagrams showing examples of memory devices.
  • 24A and 24B are circuit diagrams showing examples of memory devices.
  • 25A and 25B are diagrams showing an example of a semiconductor device.
  • 26A and 26B are diagrams showing an example of an electronic component.
  • 27A to 27J are diagrams illustrating examples of electronic devices.
  • 28A to 28E are diagrams illustrating examples of electronic devices.
  • 29A to 29C are diagrams illustrating examples of electronic devices.
  • FIG. 30 is a diagram showing an example of space equipment.
  • the ordinal numbers “first” and “second” are used for convenience, and limit the number of constituent elements or the order of constituent elements (for example, the order of steps or the order of stacking). not something to do. Also, the ordinal number given to an element in one place in this specification may not match the ordinal number given to that element elsewhere in the specification or in the claims.
  • film and “layer” can be interchanged depending on the case or situation.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer”.
  • Openings include, for example, grooves and slits. Also, a region in which an opening is formed may be referred to as an opening.
  • drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening of the insulator is substantially perpendicular to the substrate surface or the formation surface, but it may be tapered.
  • a tapered shape refers to a shape in which at least part of a side surface of a structure is inclined with respect to a substrate surface or a formation surface.
  • a taper angle the angle formed by the inclined side surface and the substrate surface or the formation surface.
  • the side surfaces of the structure and the substrate surface are not necessarily completely flat, and may be substantially planar with a fine curvature or substantially planar with fine unevenness.
  • One aspect of the present invention includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor.
  • each of the first memory cell and the second memory cell includes a transistor, a capacitor, a first insulator, and a second insulator; the transistor is on the first insulator;
  • a capacitive element including a metal oxide, a third conductor, a fourth conductor, a third insulator over the metal oxide, and a fifth conductor over the third insulator has a sixth conductor, a fourth insulator over the sixth conductor, a seventh conductor over the fourth insulator, the second insulator overlying the transistor
  • a portion where the sixth conductor, the fourth insulator, and the seventh conductor overlap is positioned on the second insulator, and through the opening provided in the second insulator , a third conductor, and a sixth conductor are electrically connected, the first conductor has a portion in contact with a fourth
  • a semiconductor device of one embodiment of the present invention includes a transistor (OS transistor) including a metal oxide in a channel formation region. Since an OS transistor has a low off-state current, memory content can be retained for a long time by using the OS transistor for a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. Further, since the frequency characteristics of the OS transistor are high, reading from and writing to the memory device can be performed at high speed.
  • OS transistor transistor
  • the first conductor and the second conductor included in the semiconductor device of one embodiment of the present invention can function as part of a write bit line and a read bit line (also simply referred to as a bit line) in the memory device. can. That is, in the memory device to which one embodiment of the present invention is applied, a structure in which the fourth conductor is directly in contact with the bit line can be applied. With such a configuration, there is no need to separately provide a connection electrode between the fourth conductor and the bit line, and the degree of integration of the memory cell can be increased.
  • a plurality of memory cells are stacked, and a stacked structure of a plurality of conductors is applied to the bit line.
  • the first conductor has a portion in contact with the fourth conductor of the first memory cell
  • the second conductor has a portion in contact with the fourth conductor of the second memory cell.
  • the upper surface of the first conductor has a portion in contact with the lower surface of the second conductor.
  • the X direction is parallel to the channel length direction of the illustrated transistor
  • the Y direction is perpendicular to the X direction
  • the Z direction is perpendicular to the X and Y directions.
  • the semiconductor device shown in FIG. A conductor is provided extending in the Z direction so as to penetrate through m layers (m is an integer of 1 or more) layers 11 (first layer 11_1 to m-th layer 11 — m). 209 , an insulator 283 over the m-th layer 11 — m, and an insulator 285 over the insulator 283 .
  • the components included in the semiconductor device of this embodiment may each have a single-layer structure or a laminated structure.
  • the conductor 240 preferably includes a conductor 240a and a conductor 240b. As shown in FIG. 1, for example, conductor 240_1 has conductor 240a1 and conductor 240b1, and conductor 240_m has conductor 240am and conductor 240bm.
  • the conductor 209 functions as part of circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals.
  • a first layer 11_1 which is the lowest layer
  • a second layer 11_2 on the first layer 11_1 and a third layer 11_3 on the second layer 11_2.
  • the m-th layer 11 — m which is the top layer.
  • a conductor 240_1 as the lowest layer
  • a conductor 240_2 above the conductor 240_1 a conductor 240_3 above the conductor 240_2, and a conductor 240_3 as the uppermost layer 240_m and .
  • the present invention is not limited to this.
  • the number of conductors 240 can be 2 or more and m or less. Accordingly, the yield of the semiconductor device can be increased as compared with the case where there is one conductor 240 (one conductor 240a and one conductor 240b).
  • the semiconductor device of this embodiment can be used as a memory cell (or memory array) of a memory device.
  • Each layer of the m layers 11 corresponds to the memory array 20[i] in the storage device described in the second embodiment.
  • Each layer of the m layers 11 is provided with a plurality of memory cells.
  • the conductor 209 is electrically connected to a driver circuit provided below the conductor 209 for driving the memory cell.
  • the second layer 11_2 will be mainly described as an example in the present embodiment. Also, with regard to the first layer 11_1, the description of the same portions as the second layer 11_2 is omitted, and the portions different from the second layer 11_2 are mainly described.
  • the first layer 11_1 includes transistors 202a and 202b and capacitors 101a and 101b.
  • the second layer 11_2 includes transistors 201a and 201b and capacitors 101a and 101b.
  • Each layer from the third layer 11_3 to the m-th layer 11_m also includes transistors 201a and 201b and capacitors 101a and 101b.
  • the first layer 11_1 and the second layer 11_2 are symmetrical in the configuration on the right side and the configuration on the left side of the conductor 240, respectively. That is, in FIG. 1, the transistors 201a and 201b are symmetrical, the transistors 202a and 202b are symmetrical, and the capacitors 101a and 101b are symmetrical.
  • the structures on the left side of the first layer 11_1 and the second layer 11_2 are mainly described as an example.
  • the transistor 202a included in the first layer 11_1 is provided over the insulator 214 .
  • a conductor 205 (a conductor 205a and a conductor 205b) is provided as a gate electrode under the transistor 202a.
  • One electrode (lower electrode) of the capacitor 101a is physically and electrically connected to one of the source and the drain of the transistor 202a.
  • the other electrode (upper electrode) of the capacitor 101a included in the first layer 11_1 can function as a lower gate electrode of the transistor 201a included in the second layer 11_2.
  • One electrode (lower electrode) of the capacitor 101a is physically and electrically connected to one of the source and the drain of the transistor 201a included in the second layer 11_2.
  • the other electrode (upper electrode) of the capacitor 101a included in the second layer 11_2 can function as a lower gate electrode of the transistor 201a included in the third layer 11_3.
  • the transistor 202a has the conductor 205 as a lower gate electrode, whereas the lower gate electrode of the transistor 201a is also the upper electrode of the capacitor 101a one layer below.
  • the first layer 11_1 and the layers above the second layer 11_2 are different in that respect.
  • the other of the source and the drain of the transistor 202a included in the first layer 11_1 is connected to the conductor 240_1, and the other of the source and the drain of the transistor 201a included in the second layer 11_2 is connected to the conductor 240_2.
  • the opening when an opening for providing the conductor 240 is provided in the laminated structure of the insulator after m layers of the memory cells are stacked, the opening must be deep, and the processing is difficult, or Manufacturing yield may be low. Specifically, it may be difficult to keep the width of the opening (also referred to as the opening diameter, which corresponds to the length in the X-axis direction in FIG. 1 and the like) constant. For example, the width of the upper side of the opening (the m-th layer side) tends to be wide, and the width of the lower side of the opening (the first layer side) tends to be narrow.
  • an opening for providing the conductor 240_1 is provided in the insulator stacked structure.
  • a conductor 240_1 is embedded in the portion.
  • the capacitors 101a and 101b included in the first layer 11_1 and the transistors 201a and 201b included in the second layer 11_2 are formed, and an opening for providing the conductor 240_2 is provided in the insulator stacked structure.
  • a conductor 240_2 is embedded in the opening.
  • FIGS. 2 and 3 are modifications of the semiconductor device shown in FIG.
  • FIG. 1 shows an example in which the edges of insulator 284, insulator 222, and the other of the source or drain of the transistor on the side of conductor 240 are substantially aligned.
  • One embodiment of the present invention is not limited to this, and for example, as illustrated in FIGS. The other respective end of the drain may be located.
  • FIG. 2 shows an example in which the insulator 284 and the ends of the other conductor 240 side of the source or drain of the transistor are substantially aligned.
  • FIG. 3 shows an example in which the other end of the source or drain of the transistor is positioned outside the end of the insulator 284 (on the conductor 240 side).
  • a top surface shape refers to a shape in plan view.
  • recesses are provided in regions of the insulator 284 that do not overlap with the insulator 222 .
  • part of the insulator 284 may be removed and a recess may be formed when the insulator 222 is processed. Note that the insulator 284 does not have to have a recess.
  • FIG. 4A shows an enlarged view of the second layer 11_2 in FIG. 1 and the configuration of the left half of the vicinity thereof (the conductor 240_2 and the configuration shown to the left thereof).
  • 4B, 5A, and 5B show a modification of FIG. 4A.
  • the second layer 11_2 has a transistor 201a and a capacitive element 101a.
  • the transistor 201a includes an insulator 222, an insulator 224 over the insulator 222, an oxide 230 (an oxide 230a and an oxide 230b) over the insulator 224, part of the side surfaces of the insulator 224, and , a conductor 242a (a conductor 242a1 and a conductor 242a2) and a conductor 242b (a conductor 242b1 and a conductor 242b2) that cover part of the top surface and part of the side surface of the oxide 230, and insulation on the oxide 230 It has a body 253 , an insulator 254 over the insulator 253 , and conductors 260 (a conductor 260 a and a conductor 260 b ) over the insulator 254 .
  • An insulator 275 is provided over the conductors 242 a and 242 b , and an insulator 280 is provided over the insulator 275 .
  • the insulators 253 and 254 and the conductor 260 are embedded inside openings provided in the insulator 280 and the insulator 275 .
  • An insulator 282 is provided over the insulator 280 and the conductor 260 .
  • Oxide 230 has a region that functions as a channel formation region of transistor 201a.
  • the conductor 242a has a region that functions as one of the source and drain electrodes of the transistor 201a.
  • the conductor 242b has a region that functions as the other of the source and drain electrodes of the transistor 201a.
  • the conductor 260 has a region that functions as the first gate electrode (upper gate electrode) of the transistor 201a.
  • Insulators 253, 254 each have a region that functions as a first gate insulator for transistor 201a.
  • the conductor 160 in the first layer 11_1 overlaps with the oxide 230 and the conductor 260 included in the second layer 11_2 and forms a region functioning as the second gate electrode (lower gate electrode) of the transistor 201a.
  • Insulators 222, 224 each have a region that functions as a second gate insulator for transistor 201a.
  • the capacitor 101a includes the conductor 153 over the conductor 242b, the insulator 154 over the conductor 153, and the conductor 160 over the insulator 154 (the conductor 160a and the conductor 160b).
  • At least part of the conductor 153 , the insulator 154 , and the conductor 160 is placed inside the openings provided in the insulator 275 , the insulator 280 , and the insulator 282 , respectively.
  • Each end of conductor 153 , insulator 154 , and conductor 160 rests on insulator 282 .
  • the insulator 154 is provided so as to cover the end of the conductor 153 . Thereby, the conductor 153 and the conductor 160 can be electrically insulated.
  • the capacitance element 101a increases. can increase the capacitance of By increasing the capacitance per unit area of the capacitor 101a, miniaturization or high integration of the semiconductor device can be achieved.
  • the conductor 153 has a region functioning as one electrode (lower electrode) of the capacitor 101a.
  • the insulator 154 has a region functioning as a dielectric of the capacitor 101a.
  • the conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 101a.
  • the capacitive element 101a constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • FIG. 4A shows a structure in which the conductor 160 serves both as the upper electrode of the capacitor 101a and the second gate electrode of the transistor 201a
  • a conductor 161 (conductors 160c and 160d) functioning as a second gate electrode of the transistor 201a may be provided separately from the conductor 160 functioning as the upper electrode of the capacitor 101a. Accordingly, the potential of the conductor 160 and the potential of the conductor 161 can be set to different values.
  • the conductor 160a and the conductor 160c can be formed by processing one conductive film.
  • the conductor 160b and the conductor 160d can be formed by processing one conductive film. Therefore, the structure shown in FIG. 4B can be manufactured without increasing the number of manufacturing steps as compared with the case of manufacturing the structure shown in FIG. 4A.
  • FIG. 4A shows an example in which the insulator 154 covers the end of the conductor 153, but the present invention is not limited to this.
  • the ends of conductor 153, insulator 154, conductor 160a, and conductor 160b may be aligned or substantially aligned.
  • the conductor 153, the insulator 154, and the conductor 160 can be formed using the same mask; therefore, the number of masks can be reduced.
  • FIG. 4B shows an example in which the insulator 154a covers the end of the conductor 153a, but the present invention is not limited to this.
  • the ends of conductor 153a, insulator 154a, conductor 160a, and conductor 160b may be aligned or substantially aligned in cross-section.
  • the conductor 161 not only the insulator 154b but also the conductor 153b may be formed.
  • Conductor 242a which includes a region that functions as one of the source or drain electrodes of transistor 201a, extends beyond oxide 230, which functions as a semiconductor layer. Therefore, the conductor 242a also functions as a wiring. For example, in FIG. 4A, a portion of each of the top and side surfaces of conductor 242a is electrically connected to conductor 240_2 extending in the Z direction.
  • the conductor 240_2 Since the conductor 240_2 is in direct contact with at least one of the top surface, the side surface, and the bottom surface of the conductor 242a, there is no need to provide a separate electrode for connection; thus, the area occupied by the memory array can be reduced. Also, the degree of integration of memory cells is improved, and the storage capacity can be increased. Note that the conductor 240_2 is preferably in contact with two or more of the top surface, the side surface, and the bottom surface of the conductor 242a. The contact resistance between the conductor 240_2 and the conductor 242a can be reduced when the conductor 240_2 is in contact with multiple surfaces of the conductor 242a.
  • FIG. 6A shows an enlarged view of a region where the conductor 240_2 and the conductor 242a are in contact with each other and its vicinity in the configuration shown in FIG.
  • FIG. 6B shows an enlarged view of a region where the conductor 240_2 and the conductor 242a are in contact with each other and its vicinity in the configuration shown in FIG.
  • conductor 240_2 has a region with width W1 and a region with width W2.
  • the width W1 corresponds to the shortest distance between the conductor 242a of the transistor 201a and the conductor 242a of the transistor 201b.
  • the width W2 corresponds to, for example, the shortest distance between the interface between the insulator 280 and the conductor 240a2 on the transistor 201a side and the interface between the insulator 280 and the conductor 240a2 on the transistor 201b side.
  • width W2 is preferably greater than width W1.
  • the conductor 240_2 is in contact with at least part of the top surface and part of the side surface of the conductor 242a. Therefore, the area of the region where the conductor 240_2 and the conductor 242a are in contact can be increased.
  • the contact between the conductor 240_2 and the conductor 242a illustrated in FIGS. 6A and 6B and the like is sometimes referred to as a topside contact.
  • the conductor 240_2 may contact a portion of the lower surface of the conductor 242a. With this structure, the area of the region where the conductor 240_2 and the conductor 242a are in contact can be further increased.
  • the components of the transistor 201a are mainly described below as an example, the components of the transistor 202a can also be applied.
  • Oxide 230 preferably comprises oxide 230a over insulator 224 and oxide 230b over oxide 230a. By providing the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b is described in this embodiment, the structure is not limited to this.
  • the oxide 230 may have, for example, a single-layer structure of the oxide 230b or a stacked structure of three or more layers.
  • the oxide 230b includes a channel formation region and source and drain regions provided to sandwich the channel formation region in the transistor 201a. At least part of the channel formation region overlaps the conductor 260 . One of the source and drain regions overlaps the conductor 242a and the other overlaps the conductor 242b.
  • the channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel forming region can be said to be i-type (intrinsic) or substantially i-type.
  • the source region and the drain region are low-resistance regions with high carrier concentration because they have many oxygen vacancies or have a high concentration of impurities such as hydrogen, nitrogen, and metal elements. That is, the source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel forming region.
  • the carrier concentration of the channel formation region is 1 ⁇ 10 18 cm ⁇ 3 or less, less than 1 ⁇ 10 17 cm ⁇ 3 , less than 1 ⁇ 10 16 cm ⁇ 3 , less than 1 ⁇ 10 15 cm ⁇ 3 , and 1 ⁇ 10 14 .
  • cm ⁇ 3 less than 1 ⁇ 10 13 cm ⁇ 3 , less than 1 ⁇ 10 12 cm ⁇ 3 , less than 1 ⁇ 10 11 cm ⁇ 3 , or less than 1 ⁇ 10 10 cm ⁇ 3 .
  • the lower limit of the carrier concentration in the channel forming region is not particularly limited, but can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the impurity concentration in the oxide 230b is lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).
  • Reducing the impurity concentration in the oxide 230b is effective in stabilizing the electrical characteristics of the transistor 201a. Moreover, in order to reduce the impurity concentration of the oxide 230b, it is preferable to reduce the impurity concentration in adjacent films as well.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
  • the impurities in the oxide 230b refer to, for example, substances other than the main components of the oxide 230b. For example, an element with a concentration of less than 0.1 atomic percent can be considered an impurity.
  • the channel formation region, the source region, and the drain region may each be formed up to the oxide 230a in addition to the oxide 230b.
  • concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes for each region, and may change continuously within each region. That is, the closer the region is to the channel formation region, the lower the concentrations of the metal element and the impurity element such as hydrogen and nitrogen may be.
  • a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a and the oxide 230b).
  • the bandgap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the off-state current of the transistor can be reduced by using a metal oxide with a large bandgap.
  • Metal oxides such as indium oxide, gallium oxide, and zinc oxide are preferably used as the oxide 230 .
  • the oxide 230 it is preferable to use, for example, a metal oxide containing two or three elements selected from indium, the element M, and zinc.
  • Element M includes gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.
  • a metal oxide containing indium, the element M, and zinc is sometimes referred to as an In-M-Zn oxide.
  • the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions.
  • the atomic ratio of the element M to the main component metal element is the same as the atomic ratio of the element M to the main component metal element in the metal oxide used for the oxide 230b. Larger is preferable.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. With this structure, diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b can be suppressed.
  • the atomic ratio of In to the element M in the metal oxide used for the oxide 230b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the transistor 201a can have high on-state current and high frequency characteristics.
  • the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, the defect level density at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 201a can obtain a large on-state current and high frequency characteristics.
  • the neighboring composition includes a range of ⁇ 30% of the desired atomic number ratio.
  • the element M it is preferable to use gallium.
  • a metal oxide that can be used for the oxide 230a may be used as the oxide 230b.
  • the composition of the metal oxide that can be used for the oxides 230a and 230b is not limited to the above.
  • the composition of metal oxides that can be used for oxide 230a may be applied to oxide 230b.
  • the composition of metal oxides that can be used for oxide 230b may also be applied to oxide 230a.
  • the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and the atomic ratio of the sputtering target used for the deposition of the metal oxide. may be
  • the oxide 230b preferably has crystallinity.
  • CAAC-OS c-axis aligned crystal oxide semiconductor
  • CAAC-OS is a metal oxide that has a dense structure with high crystallinity and few impurities and defects (eg, oxygen vacancies).
  • heat treatment is performed at a temperature at which the metal oxide is not polycrystallized (for example, 400° C. or more and 600° C. or less), so that the CAAC-OS has a dense structure with higher crystallinity.
  • a temperature at which the metal oxide is not polycrystallized for example, 400° C. or more and 600° C. or less
  • CAAC-OS since it is difficult to confirm a clear crystal grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to a crystal grain boundary is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, a metal oxide including CAAC-OS is heat resistant and highly reliable.
  • the oxide 230b by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Accordingly, extraction of oxygen from the oxide 230b can be reduced even if heat treatment is performed, so that the transistor 201a is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • a transistor including an oxide semiconductor if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded.
  • hydrogen in the vicinity of oxygen vacancies may form defects in which hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V OH ) to generate electrons serving as carriers. Therefore, if oxygen vacancies are included in the region where the channel is formed in the oxide semiconductor, the transistor has normally-on characteristics (a channel exists even if no voltage is applied to the gate electrode, and current flows through the transistor). flow characteristics). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a region where a channel is formed in the oxide semiconductor. In other words, the region in which the channel is formed in the oxide semiconductor preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.
  • an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor, and heat treatment is performed so that the oxide semiconductor is converted from the insulator.
  • Oxygen can be supplied and oxygen vacancies and VOH can be reduced.
  • the on-state current or the field-effect mobility of the transistor 201a might decrease.
  • variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface cause variations in the characteristics of the semiconductor device having transistors.
  • the conductor when oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor is oxidized and the conductivity is impaired.
  • the electrical characteristics and reliability of the transistor may be adversely affected.
  • the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, while the source region and the drain region have a high carrier concentration and are n-type. is preferred.
  • oxygen vacancies and V OH in the channel formation region of the oxide semiconductor are preferably reduced.
  • the semiconductor device is configured such that the hydrogen concentration in the channel formation region is reduced, the oxidation of the conductors 242a, 242b, and 260 is suppressed, and the It is configured to suppress the decrease in the hydrogen concentration of.
  • the insulator 253 in contact with the channel formation region in the oxide 230b preferably has a function of trapping hydrogen and fixing hydrogen. Thereby, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, V OH in the channel formation region can be reduced, and the channel formation region can be i-type or substantially i-type.
  • a metal oxide having an amorphous structure is given as an insulator having a function of trapping and fixing hydrogen.
  • the insulator 253 for example, magnesium oxide or a metal oxide such as an oxide containing one or both of aluminum and hafnium is preferably used. Oxygen atoms in metal oxides having such an amorphous structure have dangling bonds, and the dangling bonds sometimes have the property of capturing or fixing hydrogen. That is, it can be said that a metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.
  • a high dielectric constant (high-k) material for the insulator 253 .
  • An example of a high-k material is an oxide containing one or both of aluminum and hafnium.
  • an oxide containing one or both of aluminum and hafnium is preferably used as the insulator 253, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used. It is more preferable to use hafnium oxide having a structure.
  • hafnium oxide is used as the insulator 253 .
  • the insulator 253 is an insulator containing at least oxygen and hafnium.
  • the hafnium oxide has an amorphous structure.
  • insulator 253 has an amorphous structure.
  • an insulator having a structure stable against heat such as silicon oxide or silicon oxynitride
  • the insulator 253 may be a stacked structure including aluminum oxide and silicon oxide or silicon oxynitride over the aluminum oxide.
  • the insulator 253 may be a stacked-layer structure including aluminum oxide, silicon oxide or silicon oxynitride over aluminum oxide, and hafnium oxide over silicon oxide or silicon oxynitride.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • nitride oxide refers to a material whose composition contains more nitrogen than oxygen. point to the material.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. indicates
  • barrier insulators against oxygen are preferably provided near the conductors 242a, 242b, and 260, respectively.
  • the insulators are the insulators 253, 254, and 275, for example.
  • a barrier insulator refers to an insulator having a barrier property.
  • the term "barrier property” refers to a function of suppressing diffusion of a corresponding substance (also referred to as low permeability).
  • the corresponding substance has the function of capturing and fixing (also called gettering).
  • Barrier insulators against oxygen include, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride.
  • oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). mentioned.
  • each of the insulator 253, the insulator 254, and the insulator 275 preferably has a single-layer structure or a laminated structure of barrier insulators against oxygen.
  • the insulator 253 preferably has a barrier property against oxygen. It is preferable that the insulator 253 is at least less permeable to oxygen than the insulator 280 .
  • the insulator 253 has regions in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. Since the insulator 253 has a barrier property against oxygen, the side surfaces of the conductors 242a and 242b are oxidized and formation of an oxide film on the side surfaces can be suppressed. Accordingly, reduction in on-state current or reduction in field-effect mobility of the transistor 201a can be suppressed.
  • the insulator 253 is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. Since the insulator 253 has a barrier property against oxygen, oxygen can be prevented from being released from the channel formation region of the oxide 230b when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxides 230a and 230b can be reduced.
  • the insulator 280 contains an excessive amount of oxygen, excessive supply of the oxygen to the oxides 230a and 230b can be suppressed. Therefore, excessive oxidation of the source region and the drain region and reduction in on-state current or reduction in field-effect mobility of the transistor 201a can be suppressed.
  • An oxide containing one or both of aluminum and hafnium can be suitably used as the insulator 253 because it has a barrier property against oxygen.
  • the insulator 254 preferably has a barrier property against oxygen.
  • the insulator 254 is provided between the channel forming region of the oxide 230 and the conductor 260 and between the insulator 280 and the conductor 260 . With this structure, diffusion of oxygen contained in the channel formation region of the oxide 230 into the conductor 260 and formation of oxygen vacancies in the channel formation region of the oxide 230 can be suppressed. In addition, oxygen contained in the oxide 230 and oxygen contained in the insulator 280 diffuse into the conductor 260, so that oxidation of the conductor 260 can be suppressed.
  • the insulator 254 is preferably at least less permeable to oxygen than the insulator 280 .
  • silicon nitride is preferably used as the insulator 254 .
  • the insulator 254 is an insulator containing at least nitrogen and silicon.
  • the insulator 254 preferably has a barrier property against hydrogen. Accordingly, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.
  • the insulator 275 preferably has a barrier property against oxygen.
  • the insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. With this structure, diffusion of oxygen contained in the insulator 280 to the conductors 242a and 242b can be suppressed. Therefore, it is possible to prevent the conductors 242a and 242b from being oxidized by oxygen contained in the insulator 280 to increase the resistivity and reduce the on-state current. It is preferable that the insulator 275 is at least less permeable to oxygen than the insulator 280 .
  • silicon nitride is preferably used as the insulator 275 .
  • the insulator 275 is an insulator containing at least nitrogen and silicon.
  • the barrier insulator against hydrogen is the insulator 275, for example.
  • Barrier insulators to hydrogen include oxides such as aluminum oxide, hafnium oxide, tantalum oxide, and nitrides such as silicon nitride.
  • the insulator 275 preferably has a single-layer structure or a laminated structure of the barrier insulator against hydrogen.
  • the insulator 275 preferably has a barrier property against hydrogen. Since the insulator 275 has a barrier property against hydrogen, the insulator 253 can suppress capture and fixation of hydrogen in the source and drain regions. Therefore, the source and drain regions can be n-type.
  • the channel formation region can be i-type or substantially i-type
  • the source region and the drain region can be n-type
  • a semiconductor device having good electrical characteristics can be provided. Further, with the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. Further, by miniaturizing the transistor 201a, high frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.
  • Insulator 253 and insulator 254 each function as part of the gate insulator.
  • the insulators 253 and 254 are provided in openings formed in the insulator 280 or the like together with the conductor 260 . It is preferable that the thickness of the insulator 253 and the thickness of the insulator 254 be small in order to miniaturize the transistor 201a.
  • the thickness of the insulator 253 is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and less than 5.0 nm, and 1.0 nm or more and 3.0 nm.
  • the thickness of the insulator 254 is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 3.0 nm, even more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 253 and 254 may have at least a part of the region with the thickness as described above.
  • the ALD method includes a thermal ALD (thermal ALD) method in which a precursor and a reactant react with only thermal energy, a PEALD (plasma enhanced ALD) method using a plasma-excited reactant, and the like.
  • thermal ALD thermal ALD
  • PEALD plasma enhanced ALD
  • film formation can be performed at a lower temperature by using plasma, which is preferable in some cases.
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with a high aspect ratio, to form films with few defects such as pinholes, and to improve coverage. There are effects such as excellent film formation and low temperature film formation. Therefore, the insulator 253 can be formed with a thin film thickness as described above with good coverage on the side surfaces of the opening formed in the insulator 280 and the like, the side ends of the conductors 242a and 242b, and the like. .
  • a film formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
  • quantification of impurities secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy) can be performed using
  • silicon nitride deposited by a PEALD method can be used as the insulator 254 .
  • the insulator 253 can also function as the insulator 254 .
  • the structure without the insulator 254 can simplify the manufacturing process of the semiconductor device and improve productivity.
  • the semiconductor device preferably has a structure in which entry of hydrogen into the transistors 201a and 202a and the like is suppressed.
  • an insulator having a function of suppressing diffusion of hydrogen is preferably provided so as to cover one or both of the top and bottom of the transistors 201a and 202a.
  • the insulator is the insulator 212, for example.
  • An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212 . Accordingly, diffusion of hydrogen from below the insulator 212 to the transistors 201a, 202a, and the like can be suppressed.
  • the insulator 212 any of the insulators that can be used for the insulator 275 can be used.
  • One or more of the insulator 212, the insulator 214, the insulator 282, the insulator 283, and the insulator 285 is exposed to impurities such as water and hydrogen from the substrate side or from above the transistors 201a and 202a. It preferably functions as a barrier insulator that suppresses diffusion into the transistors 201a, 202a, and the like.
  • one or more of insulator 212, insulator 214, insulator 282, insulator 283, and insulator 285 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and an insulating material having a function of suppressing the diffusion of impurities such as copper atoms (the above-mentioned impurities are difficult to permeate).
  • an insulating material that has a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules
  • Each of the insulator 212, the insulator 214, the insulator 282, the insulator 283, and the insulator 285 preferably has a function of suppressing diffusion of impurities such as water and hydrogen, and of oxygen.
  • impurities such as water and hydrogen, and of oxygen.
  • aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used.
  • the insulator 212 is preferably made of silicon nitride or the like, which has a higher hydrogen barrier property.
  • the insulator 214, the insulator 282, the insulator 283, and the insulator 285 preferably include aluminum oxide, magnesium oxide, or the like, which have high functions of capturing and fixing hydrogen, respectively. Accordingly, impurities such as water and hydrogen can be prevented from diffusing from the substrate side to the transistors 201 a and 202 a through the insulators 212 and 214 . Alternatively, impurities such as water and hydrogen can be prevented from diffusing into the transistors 201a and 202a and the like from the interlayer insulating film or the like provided outside the insulator 282 or the insulator 283 . Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side can be suppressed.
  • oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistors 201a, 202a, or the like through the insulator 282 or the like.
  • the conductor 205 overlaps with the oxide 230 and the conductor 260 in the transistors 202a and 202b.
  • the conductor 205 is preferably embedded in an opening formed in the insulator 216 . Also, part of the conductor 205 is embedded in the insulator 214 in some cases.
  • the conductor 205 may have a single-layer structure or a laminated structure.
  • the conductor 205 includes a conductor 205a and a conductor 205b.
  • the conductor 205a is provided in contact with the bottom surface and side walls of the opening.
  • the conductor 205b is provided so as to be embedded in the recess of the conductor 205a.
  • the height of the top surface of the conductor 205b approximately matches the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216 .
  • the conductor 205a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N 2 O, NO, NO 2 ), and copper atoms. It is preferable to have a conductive material with Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably included.
  • a conductive material having a function of reducing diffusion of hydrogen When a conductive material having a function of reducing diffusion of hydrogen is used for the conductor 205a, impurities such as hydrogen contained in the conductor 205b enter the oxide 230 through the insulators 216, 224, and the like. You can prevent it from spreading.
  • a conductive material having a function of suppressing diffusion of oxygen for the conductor 205a, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205b.
  • Examples of conductive materials having a function of suppressing diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.
  • the conductor 205a can have a single-layer structure or a laminated structure of the above conductive materials.
  • conductor 205a preferably comprises titanium nitride.
  • a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 205b.
  • conductor 205b preferably comprises tungsten.
  • Conductor 205 can function as a second gate electrode.
  • the potential applied to the conductor 205 is changed independently of the potential applied to the conductor 260, so that the threshold voltage (Vth) of the transistor 202a can be controlled.
  • Vth threshold voltage
  • the Vth of the transistor 202a can be increased and the off current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.
  • the electric resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electric resistivity. Also, the thickness of the insulator 216 is almost the same as that of the conductor 205 . Here, it is preferable to reduce the film thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205 . By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced; thus, diffusion of the impurities into the oxide 230 can be suppressed. .
  • Insulator 222 and insulator 224 function as gate insulators.
  • the insulator 222 preferably has a function of suppressing diffusion of hydrogen (eg, at least one of hydrogen atoms and hydrogen molecules). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • hydrogen eg, at least one of hydrogen atoms and hydrogen molecules
  • oxygen eg, at least one of oxygen atoms and oxygen molecules
  • the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen more than the insulator 224 does.
  • Insulator 222 preferably comprises an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 222 prevents the release of oxygen from the oxide 230 to the substrate side and the release of hydrogen or the like from the peripheral portions of the transistors 201a and 202a to the oxide 230.
  • the conductor 205 or the conductor 160 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230 .
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the above insulator.
  • the insulator 222 may have a single-layer structure or a laminated structure of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide.
  • thinning of gate insulators may cause problems such as leakage current.
  • a high-k material for an insulator that functions as a gate insulator it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a substance with a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr)TiO 3 (BST) may be used in some cases.
  • Insulator 224 in contact with oxide 230 preferably comprises, for example, silicon oxide or silicon oxynitride.
  • each of the insulators 222 and 224 may have a stacked structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.
  • the conductors 242a, 242b, and 260 are preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing diffusion of oxygen.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Accordingly, a decrease in the conductivity of the conductors 242a, 242b, and 260 can be suppressed.
  • the conductors 242a, 242b, and 260 are conductive materials containing at least metal and nitrogen. become a body.
  • the conductors 242a and 242b may have a single-layer structure or a laminated structure. Further, the conductor 260 may have a single-layer structure or a laminated structure.
  • conductors 242a and 242b are shown in a two-layer structure.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing diffusion of oxygen is preferably used for the layers (the conductors 242a1 and 242b1) in contact with the oxide 230b.
  • a material that easily absorbs (or extracts) hydrogen for the layers (the conductors 242a1 and 242b1) that are in contact with the oxide 230b, because the concentration of hydrogen in the oxide 230 can be reduced.
  • the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1.
  • the conductors 242a2 and 242b2 are preferably thicker than the conductors 242a1 and 242b1.
  • tantalum nitride or titanium nitride can be used for the conductors 242a1 and 242b1, and tungsten can be used for the conductors 242a2 and 242b2.
  • a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b in order to suppress a decrease in the conductivity of the conductors 242a and 242b.
  • a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin is preferable to use.
  • CAAC-OS extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b can be suppressed.
  • Examples of the conductors 242a and 242b include a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, and the like. is preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even after absorbing oxygen.
  • hydrogen contained in the oxide 230b or the like might diffuse into the conductor 242a or the conductor 242b.
  • hydrogen contained in the oxide 230b or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like might be absorbed by the conductor 242a or the conductor 242b.
  • Conductor 260 is arranged such that its top surface is approximately level with the top of insulator 254 , the top of insulator 253 , and the top of insulator 280 .
  • Conductor 260 functions as a first gate electrode of transistor 201a.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b disposed over the conductor 260a.
  • the conductor 260a is preferably arranged to wrap the bottom and side surfaces of the conductor 260b.
  • conductor 260 is shown in a two-layer structure. At this time, a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing diffusion of oxygen is preferably used as the conductor 260a.
  • a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used.
  • a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress oxidation of the conductor 260b due to oxygen contained in the insulator 280 or the like and a decrease in conductivity.
  • the conductive material having a function of suppressing diffusion of oxygen titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.
  • a conductor with high conductivity is preferably used for the conductor 260 .
  • the conductor 260b can use a conductive material whose main component is tungsten, copper, or aluminum.
  • the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.
  • the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like.
  • the conductor 260 can be reliably placed in the region between the conductors 242a and 242b without being aligned.
  • Insulator 216 , insulator 280 , and insulator 284 preferably each have a lower dielectric constant than insulator 214 .
  • the parasitic capacitance generated between wirings can be reduced.
  • insulator 216, insulator 280, and insulator 284 can be silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide, respectively. , silicon oxide having vacancies.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferable because a region containing oxygen released by heating can be easily formed.
  • top surfaces of the insulators 216, 280, and 284 may be planarized.
  • insulator 280 preferably comprises an oxide containing silicon, such as silicon oxide or silicon oxynitride.
  • the side wall of the insulator 280 may be substantially perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By tapering the side wall, coverage of the insulator 253 provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.
  • the conductor 153 and the conductor 160 included in the capacitor 101a can be formed using any of the conductors that can be used for the conductor 205, the conductor 242, or the conductor 260, respectively.
  • the conductors 153 and 160 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.
  • the lower surface of the conductor 153 is in contact with the upper surface of the conductor 242b.
  • the conductor 153 can be formed using titanium nitride or tantalum nitride deposited by an ALD method or a CVD method.
  • the conductor 160a can be titanium nitride deposited by an ALD method or a CVD method
  • the conductor 160b can be tungsten deposited by a CVD method. Note that when the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten deposited by a CVD method.
  • a high dielectric constant (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 154 included in the capacitor 101a.
  • the insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.
  • Insulators of high dielectric constant (high-k) materials include, for example, oxides, oxynitrides, nitride oxides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. things are mentioned.
  • the oxide, oxynitride, nitride oxide, or nitride may contain silicon. Insulators made of the above materials can also be laminated and used.
  • insulators of high-k materials such as aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides with silicon and hafnium, oxides with silicon and zirconium, oxynitrides with silicon and zirconium, oxides with hafnium and zirconium, and oxynitrides with hafnium and zirconium.
  • the insulator 154 can be thick enough to suppress leakage current and the capacitance of the capacitor 101a can be sufficiently secured.
  • a laminated insulator composed of the above materials, and a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material is used.
  • high-k high dielectric constant
  • high-k high dielectric constant
  • an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used as the insulator 154 .
  • an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in this order can be used.
  • a stack of insulators having relatively high dielectric strength such as aluminum oxide dielectric strength is improved and electrostatic breakdown of the capacitor 101a can be suppressed.
  • the conductor 240 is provided in contact with the inner wall of the opening of the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 275, the insulator 280, the insulator 282, and the insulator 284. .
  • the conductor 240 is in contact with the top surface and side surfaces of the conductor 242 a , the top surface and side surfaces of the conductor 242 a , and the top surface of the conductor 209 .
  • the conductor 240 is a plug or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals with the transistors 201a and 202a. function as
  • the conductor 240 functions as a write and read bit line.
  • the conductor 240 preferably has a laminated structure of a conductor 240a and a conductor 240b.
  • the conductor 240_2 can have a structure in which a conductor 240a2 is provided in contact with the inner wall of the opening, and a conductor 240b2 is provided inside. That is, the conductor 240a2 is arranged closer to the insulators 222, 275, 280, 282, and 284 than the conductor 240b2.
  • the conductor 240a2 is in contact with the upper surface and side surfaces of the conductor 242a.
  • a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used.
  • the conductor 240a can have a single-layer structure or a stacked structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. Accordingly, impurities such as water and hydrogen can be prevented from entering the oxide 230 through the conductor 240 .
  • the conductor 240 also functions as a wiring, a conductor with high conductivity is preferably used.
  • a conductor with high conductivity is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor 240b.
  • the conductor 240a is a conductor containing titanium and nitrogen
  • the conductor 240b is a conductor containing tungsten.
  • the conductor 240 may have a single-layer structure or a laminated structure of three or more layers.
  • FIGS. 17A and 17B are perspective views of insulator 210, insulator 212, insulator 214, first layer 11_1, and second layer 11_2.
  • FIG. 17A shows a cross section of a transistor in the channel length direction and a cross section of a capacitor in a direction parallel to the channel width direction of the transistor.
  • FIG. 17B shows a cross section of the transistor in the channel width direction.
  • each of the first layer 11_1 and the second layer 11_2 has three transistors in the channel width direction of the transistor.
  • each layer 11_2 has three capacitive elements in the channel width direction of the transistor.
  • the number of transistors and capacitors included in each layer is not particularly limited.
  • each layer may have four or more transistors and four or more capacitors in the channel width direction of the transistors.
  • a layer including the transistors 202c to 202e and the like (the functional layer described in Embodiment 2) is provided over a layer including the transistor 310 and the like (corresponding to the driver circuit 21 described in Embodiment 2). 50) is provided, and a stacked structure similar to the stacked structure shown in FIG. Since the configuration of layers above the insulator 212 in FIG. 7 is the same as in FIG. 1, detailed description thereof will be omitted.
  • FIG. Transistor 310 is provided on substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 comprising part of substrate 311, and a lower region functioning as a source or drain region. It has a resistance region 314a and a low resistance region 314b.
  • Transistor 310 can be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 for example, a single crystal silicon substrate can be used.
  • a semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductor 316 is provided so as to cover side surfaces and a top surface of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 310 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate.
  • an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion.
  • SOI Silicon Insulator
  • transistor 310 illustrated in FIG. 7 is an example, and the structure thereof is not limited, and an appropriate transistor can be used depending on the circuit configuration or the driving method.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between each structure.
  • the wiring layer can be provided in a plurality of layers depending on the design.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as wiring, and part of the conductor may function as a plug.
  • an insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order over the transistor 310 as interlayer films.
  • a conductor 328 or the like is embedded in the insulators 320 and 322 .
  • a conductor 330 or the like is embedded in the insulators 324 and 326 . Note that the conductor 328 and the conductor 330 function as contact plugs or wirings.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder.
  • the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to improve planarity.
  • CMP chemical mechanical polishing
  • FIG. 7 illustrates transistors 202c, 202d, and 202e included in the functional layer 50 described in Embodiment 2.
  • FIG. Transistors 202c, 202d, and 202e have the same configuration as transistors 202a and 202b included in memory cell 10 .
  • Transistors 202c, 202d and 202e correspond to transistors 52, 53 and 55 shown in FIG. 23A and the like.
  • the sources and drains of the transistors 202c, 202d, and 202e are connected in series, similar to the transistors 52, 53, and 55.
  • An insulator 208 is provided over the transistors 202 c , 202 d , and 202 e , and a conductor 207 is provided in openings formed in the insulator 208 .
  • the insulator 208 can be provided with an insulator similar to the insulator 210
  • the conductor 207 can be provided with a conductor similar to the conductor 209 .
  • the lower surface of conductor 207 is provided in contact with the upper surface of conductor 260d of transistor 202d. Also, the upper surface of the conductor 207 is provided in contact with the lower surface of the conductor 209 . With such a structure, the conductor 240 corresponding to the wiring BL functioning as a bit line and the gate of the transistor 202d corresponding to the transistor 52 can be electrically connected.
  • the X direction is parallel to the channel length direction of the illustrated transistor
  • the Y direction is parallel to the channel width direction of the illustrated transistor
  • the Z direction is the X direction and the Y direction. is perpendicular to 8 and 9, illustration of some components such as an insulator is omitted for the sake of simplification.
  • FIGS. 8A and 8B are layouts applicable to each layer above the second layer 11_2, showing transistors 201a and 201b, capacitive elements 101a and 101b, and the like.
  • FIGS. 8A and 8B are top layouts of the second layer 11_2, in FIG. 8B shows the conductor 160 of the first layer 11_1 (that is, the back gate electrodes of the transistors 201a and 201b in the second layer 11_2).
  • FIGS. 9A and 9B are modifications of FIGS. 8A and 8B.
  • 8A and 8B show an example in which adjacent memory cells share one conductor 160 without the conductor 240 interposed therebetween.
  • adjacent memory cells without the conductor 240 interposed therebetween may each independently have the conductor 160 .
  • FIGS. 8 and 9 are formed in a line-and-space pattern.
  • the margin of the portion where the two patterns are overlapped is 10 nm
  • the conductor 240 is designed with 25 nm ⁇ 25 nm with a margin for misalignment of 5 nm added
  • the cell density is 740 cells/ ⁇ m 2 .
  • the cell density of SRAM is 47.6 cells/ ⁇ m 2 when the technology node (design rule) is 5 nm, and 37 cells/ ⁇ m 2 when the technology node is 7 nm.
  • the cell density of the DRAM is, for example, 137 cells/ ⁇ m 2 to 380 cells/ ⁇ m 2 .
  • the conductor 240 is shown as a square when viewed from above, but the present invention is not limited to this.
  • the conductor 240 may have a circular shape, a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above.
  • each layer constituting the semiconductor device may have a single-layer structure or a laminated structure.
  • a substrate for forming a transistor for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used.
  • insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates.
  • semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the above-described semiconductor substrate such as an SOI (Silicon On Insulator) substrate, etc.
  • conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates.
  • Substrates and substrates in which a semiconductor or insulator is provided on a conductive substrate are included.
  • those substrates provided with one or more types of elements may be used.
  • Elements provided on the substrate include, for example, capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • insulator>> Examples of insulators include insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.
  • thinning of gate insulators may cause problems such as leakage current.
  • a high-k material for an insulator functioning as a gate insulator voltage reduction during transistor operation can be achieved while maintaining a physical film thickness.
  • a material with a low dielectric constant for the insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.
  • Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. and oxynitrides with silicon, and nitrides with silicon and hafnium.
  • Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and air. Examples include silicon oxide having pores and resin.
  • insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including one or more of lanthanum, neodymium, hafnium, and tantalum can be used in single layers or in stacks.
  • examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxide.
  • Metal oxides such as hafnium and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride are included.
  • An insulator that functions as a gate insulator preferably has a region containing oxygen that is released by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined.
  • Conductors include, for example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and lanthanum and nickel.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, respectively is a conductive material that is difficult to oxidize, or a material that maintains conductivity even if it absorbs oxygen.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a conductor having a laminated structure for example, a laminated structure in which a material containing the metal element described above and a conductive material containing oxygen are combined, or a material containing the metal element described above and a conductive material containing nitrogen. , or a laminated structure in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.
  • a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate electrode.
  • a conductive material containing the metal element and nitrogen described above may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • Indium tin oxides may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the oxide 230 .
  • Metal oxides that can be used as the oxide 230 according to one embodiment of the present invention are described below.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.
  • the metal oxide is an In-M-Zn oxide with indium, the element M and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
  • the element M there are cases where a plurality of the above elements may be combined.
  • the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as In—Ga—Zn oxide, IGZO) is preferably used for a semiconductor layer of a transistor.
  • an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor.
  • an oxide (IAGZO or IGAZO) containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) may be used as the semiconductor layer.
  • an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as In—Ga—Zn—Sn oxide, IGZTO) may be used for the semiconductor layer. good.
  • metal oxides containing nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may also be referred to as a metal oxynitride.
  • Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline. (polycrystal) and the like.
  • oxide semiconductors may be classified differently from the above when their structures are focused. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that includes a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the formation surface of the CAAC-OS film, or the normal direction to the surface of the CAAC-OS film.
  • a crystalline region is a region having periodicity in atomic arrangement. If the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement.
  • CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and has no obvious orientation in the ab plane direction.
  • each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystalline region is less than 10 nm.
  • the maximum diameter of the crystal region may be about several tens of nanometers.
  • a CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is less likely to occur in CAAC-OS.
  • a CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.
  • CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS for the OS transistor can increase the degree of freedom in the manufacturing process.
  • nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has minute crystals.
  • the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also called a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.
  • An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.
  • An a-like OS has void or low density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. In addition, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • CAC-OS relates to material composition.
  • CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called mosaic or patch.
  • CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). is called). That is, CAC-OS is a composite metal oxide in which the first region and the second region are mixed.
  • the CAC-OS in the In—Ga—Zn oxide refers to a material structure containing In, Ga, Zn, and O, in which a region containing In as a main component (first region) and a region containing In as a main component (first region) and A region (second region) containing Ga as a main component is a mosaic shape, and the configuration is such that these regions are randomly present. Therefore, CAC-OS is presumed to have a structure in which metal elements are unevenly distributed.
  • a CAC-OS can be formed, for example, by a sputtering method under conditions in which the substrate is not heated. Further, when the CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas is used as a deposition gas. can be done. Further, the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is preferably as low as possible. For example, the flow ratio of the oxygen gas to the total flow rate of the film forming gas during film formation is 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is developed. Therefore, by distributing the first region in the form of a cloud in the metal oxide, a high field effect mobility ( ⁇ ) can be realized.
  • the second region is a region with higher insulation than the first region.
  • the leakage current can be suppressed by distributing the second region in the metal oxide.
  • CAC-OS when used for a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementarily to provide a switching function (on/off). functions) can be given to the CAC-OS.
  • a part of the material has a conductive function
  • a part of the material has an insulating function
  • the whole material has a semiconductor function.
  • CAC-OS is most suitable for various semiconductor devices including display devices.
  • Oxide semiconductors have various structures and each has different characteristics.
  • An oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. may
  • a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer of the transistor.
  • a single element semiconductor such as silicon or a compound semiconductor such as gallium arsenide may be used.
  • a transition metal chalcogenide that functions as a semiconductor is preferably used for a semiconductor layer of a transistor, for example.
  • Specific examples of transition metal chalcogenides applicable to semiconductor layers of transistors include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ), and the like.
  • Example of a method for manufacturing a semiconductor device An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Here, the case of manufacturing the semiconductor device illustrated in FIG. 1 will be described as an example.
  • insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors are referred to as sputtering methods, chemical vapor deposition (CVD) method, molecular beam epitaxy (MBE) method, pulsed laser deposition (PLD) method, ALD method, or the like can be used as appropriate.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD method atomic layer deposition
  • Sputtering methods include an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method using a DC power source, and a pulse DC sputtering method in which a voltage applied to electrodes is varied in a pulsed manner.
  • the RF sputtering method is mainly used for forming an insulating film
  • the DC sputtering method is mainly used for forming a metal conductive film.
  • the pulse DC sputtering method is mainly used when forming a film of a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. Furthermore, it can be divided into a metal CVD (MCVD) method and an organic metal CVD (MOCVD) method depending on the raw material gas used.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD photo CVD
  • MCVD metal CVD
  • MOCVD organic metal CVD
  • the plasma CVD method can obtain high quality films at relatively low temperatures.
  • the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed.
  • wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device.
  • a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased.
  • the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • a thermal ALD method in which the reaction between the precursor and the reactant is performed only by thermal energy, a PEALD method using a plasma-excited reactant, or the like can be used.
  • CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.
  • a film having an arbitrary composition can be formed by controlling the flow rate ratio of the raw material gases.
  • the CVD method it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of source gases while forming a film.
  • the time required for film formation is reduced compared to film formation using a plurality of film formation chambers, as the time required for transportation or pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.
  • a film having an arbitrary composition can be formed by simultaneously introducing different kinds of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • a substrate (not shown) is prepared, and insulators 210 and conductors 209 are formed over the substrate.
  • an insulator 212 is formed over the insulator 210 and the conductor 209, an insulator 214 is formed over the insulator 212, and an insulator 216 is formed over the insulator 214 (FIG. 10A). .
  • the insulators 212, 214, and 216 are each preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 212, the insulator 214, or the insulator 216 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the method for forming the insulator 212, the insulator 214, and the insulator 216 is not limited to the sputtering method. good.
  • the insulators 212, 214, and 216 are preferably formed successively without exposure to the air.
  • silicon nitride is deposited as the insulator 212 by a pulse DC sputtering method using a silicon target in an atmosphere containing nitrogen gas.
  • a pulse DC sputtering method it is possible to suppress the generation of particles due to arcing on the target surface, so that the film thickness distribution can be made more uniform.
  • the rise and fall of the discharge can be steeper than the high-frequency voltage. As a result, power can be supplied to the electrodes more efficiently, and the sputtering rate and film quality can be improved.
  • an insulator such as silicon nitride
  • impurities such as water and hydrogen
  • diffusion of impurities such as water and hydrogen contained in a layer below the insulator 212 can be suppressed.
  • an insulator such as silicon nitride through which copper is difficult to permeate as the insulator 212, even if a metal such as copper that is easily diffused is used as a conductor in a layer (not shown) below the insulator 212, the metal does not easily pass through. The upward diffusion through the insulator 212 can be suppressed.
  • RF Radio Frequency
  • the amount of oxygen injected into layers below insulator 214 can be controlled by the amount of RF power applied to the substrate.
  • RF power is, for example, 0 W/cm 2 or more and 1.86 W/cm 2 or less.
  • the amount of oxygen suitable for the characteristics of the transistor can be changed and implanted according to the RF power when the insulator 214 is formed. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be implanted.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 214 it is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping hydrogen and a function of fixing hydrogen. Accordingly, hydrogen contained in the insulator 216 or the like can be captured or fixed, and diffusion of the hydrogen to the oxide 230 can be prevented.
  • a metal oxide having an amorphous structure such as aluminum oxide
  • aluminum oxide having an amorphous structure aluminum oxide having an amorphous structure as the insulator 214 because hydrogen can be captured or fixed more effectively in some cases. Accordingly, a highly reliable transistor and a semiconductor device having favorable characteristics can be manufactured.
  • silicon oxide is deposited as the insulator 216 by a pulse DC sputtering method using a silicon target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • an opening is formed in insulator 216 to reach insulator 214 .
  • an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected.
  • silicon oxide or silicon oxynitride is used for the insulator 216 forming the trench
  • silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214 .
  • a dry etching method or a wet etching method can be used to form the opening. Since processing by a dry etching method is suitable for fine processing, it is preferable to use a dry etching method.
  • an etching gas containing halogen can be used as an etching gas.
  • an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • C4F6 gas, C5F6 gas , C4F8 gas , CF4 gas , SF6 gas, CHF3 gas, Cl2 gas , BCl3 gas, SiCl4 gas, or BBr 3 gas etc. can be used individually or in mixture of 2 or more gases.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate to the above etching gas.
  • Etching conditions can be appropriately set according to the object to be etched.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as a dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency voltage having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency voltages having different frequencies may be applied to parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • a dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus.
  • ICP inductively coupled plasma
  • the conductive film to be the conductor 205a preferably contains a conductor having a function of suppressing permeation of oxygen.
  • the conductive film preferably includes one or more of tantalum nitride, tungsten nitride, and titanium nitride, for example.
  • the conductive film can be a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy.
  • a conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.
  • titanium nitride is deposited as a conductive film to be the conductor 205a.
  • a metal nitride as a lower layer of the conductor 205, oxidation of the conductor 205a by the insulator 216 or the like can be suppressed.
  • the metal can be prevented from diffusing out of the conductor 205a.
  • a conductive film to be the conductor 205b is formed (FIG. 10A).
  • a conductive film to be the conductor 205b preferably contains one or more of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy, for example.
  • the conductive film can be formed using, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment mode, tungsten is deposited as the conductive film to be the conductor 205b.
  • part of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b are removed, and the insulator 216 is exposed.
  • the conductors 205a and 205b remain only in the openings of the insulator 216 (FIG. 10A). Note that part of the insulator 216 is removed by the CMP treatment in some cases.
  • an insulator 222 is formed over the insulator 216 and the conductor 205 (FIG. 10A).
  • an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited.
  • the insulator containing oxides of one or both of aluminum and hafnium for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used.
  • hafnium-zirconium oxide is preferably used.
  • An insulator containing oxides of one or both of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor are suppressed from diffusing into the transistor through the insulator 222, and oxidation is prevented. The generation of oxygen vacancies in the substance 230 can be suppressed.
  • the insulator 222 can be a stacked film of an insulator containing oxides of one or both of aluminum and hafnium and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.
  • the insulator 222 can be deposited using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.
  • the insulator 222 is formed using hafnium oxide by an ALD method.
  • a stacked body of silicon nitride deposited by a PEALD method and hafnium oxide deposited by an ALD method may be used.
  • heat treatment is preferably performed.
  • the temperature of the heat treatment is preferably 250° C. or higher and 650° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 320° C. or higher and 450° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • oxygen gas is preferably about 20%.
  • heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • heat treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1 after the insulator 222 is formed. Impurities such as water and hydrogen contained in the insulator 222 can be removed by the heat treatment. In the case where an oxide containing hafnium is used as the insulator 222, the insulator 222 may be partly crystallized by the heat treatment. Further, the heat treatment can be performed at a timing such as after the insulator 224 is formed.
  • an insulating film 224f is formed over the insulator 222 (FIG. 10A).
  • the insulating film 224f can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 224f is formed using silicon oxide by a sputtering method.
  • the hydrogen concentration in the insulating film 224f can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Since the insulating film 224f will be in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • an oxide film 230af is formed on the insulating film 224f, and an oxide film 230bf is formed on the oxide film 230af (FIG. 10A).
  • the oxide film 230af and the oxide film 230bf are preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230af and the oxide film 230bf. can be kept clean.
  • the oxide film 230af and the oxide film 230bf can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the oxide film 230af and the oxide film 230bf are formed by sputtering.
  • the oxide film 230af and the oxide film 230bf are formed by sputtering
  • oxygen or a mixed gas of oxygen and noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased.
  • an In-M-Zn oxide target or the like can be used.
  • part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f during the formation of the oxide film 230af. Therefore, the percentage of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.
  • the oxide film 230bf is formed by a sputtering method
  • the percentage of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% or more and 100% or less, oxygen-excessive oxidation will occur.
  • a material semiconductor is formed.
  • a transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability.
  • one embodiment of the present invention is not limited to this.
  • an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% to 30%, preferably 5% to 20%. be.
  • a transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility.
  • the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
  • an oxide target of In:Ga:Zn 1:1:1.2 [atomic ratio]
  • an oxide target of In:Ga:Zn 1:1:2 [atomic ratio]
  • a film is formed using Note that each oxide film is preferably formed in accordance with characteristics required for the oxides 230a and 230b by appropriately selecting film formation conditions and atomic ratios.
  • the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably formed by sputtering without exposure to the air.
  • An ALD method may be used to form the oxide film 230af and the oxide film 230bf.
  • the ALD method for forming the oxide films 230af and 230bf films having a uniform thickness can be formed even in trenches or openings with a large aspect ratio.
  • the oxide films 230af and 230bf can be formed at a lower temperature than the thermal ALD method.
  • heat treatment is preferably performed.
  • the heat treatment may be performed within a temperature range in which the oxide films 230af and 230bf are not polycrystallized.
  • the temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher and 650° C. or lower, 600° C. or lower, or 550° C. or lower.
  • the atmosphere for the heat treatment is similar to the atmosphere that can be applied to the heat treatment after the insulator 222 is formed.
  • the gas used for the heat treatment is preferably highly purified.
  • moisture or the like can be prevented from being taken into the oxide films 230af, 230bf, and the like as much as possible.
  • heat treatment is performed at a temperature of 400° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1.
  • Such heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide films 230af and 230bf.
  • impurities such as carbon, water, and hydrogen in the oxide films 230af and 230bf.
  • the crystallinity of the oxide film 230bf can be improved, and a denser structure can be obtained.
  • the crystal regions in the oxide films 230af and 230bf can be increased, and the in-plane variation of the crystal regions in the oxide films 230af and 230bf can be reduced. Therefore, in-plane variations in electrical characteristics of the transistor can be reduced.
  • hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf moves to the insulator 222 and is absorbed into the insulator 222.
  • FIG. hydrogen in the insulator 216 , the insulating film 224 f, the oxide film 230 af, and the oxide film 230 bf diffuses into the insulator 222 . Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentrations in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decrease.
  • insulating film 224f (later insulator 224) functions as a gate insulator for transistor 202a
  • oxide film 230af and oxide film 230bf (later oxide 230a and oxide 230b) are channel-forming regions of transistor 202a. function as The transistor 202a formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf with reduced hydrogen concentration is preferable because it has high reliability.
  • the insulating film 224f, the oxide film 230af, and the oxide film 230bf are processed into an island shape by lithography to form the insulator 224, the oxide 230a, and the oxide 230b (FIG. 10B).
  • the insulator 224, the oxide 230a, and the oxide 230b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b may be tapered.
  • the taper angles of the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b may be, for example, 60° or more and less than 90°.
  • the structure is not limited to the above, and the side surfaces of the insulator 224 and the oxides 230 a and 230 b may be substantially perpendicular to the top surface of the insulator 222 .
  • the area can be reduced and the density can be increased when a plurality of transistors are provided.
  • a dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for fine processing. Further, the insulating film 224f, the oxide film 230af, and the oxide film 230bf may be processed under different conditions.
  • a resist mask can be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.
  • a hard mask made of an insulator or a conductor may be used under the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed on the oxide film 230bf, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • the etching of the oxide film 230bf or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the oxide film 230bf.
  • the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.
  • a conductive film to be the conductor 242_1 is formed over the insulator 222 and the oxide 230, and a conductive film to be the conductor 242_2 is formed over the conductive film (FIG. 10C).
  • the conductive film to be the conductor 242_1 and the conductive film to be the conductor 242_2 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, respectively, for example.
  • the conductive film to be the conductor 242_1 is formed using tantalum nitride by a sputtering method, and the conductive film to be the conductor 242_2 is formed using tungsten.
  • heat treatment may be performed before the conductive film to be the conductor 242_1 is formed.
  • the heat treatment may be performed under reduced pressure, and a conductive film to be the conductor 242_1 may be continuously formed without exposure to the air.
  • moisture and hydrogen adsorbed to the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.
  • each of the two conductors 242_1 illustrated in FIG. 10C may be provided in an island shape, or may be one island-shaped film having an opening overlapping with the conductor 209 .
  • the two conductors 242_2 illustrated in FIG. 10C may each be provided in an island shape, or may be one island-shaped film having an opening overlapping with the conductor 209.
  • FIG. 10C
  • the conductors 242_1 and 242_2 are formed so as to overlap with the conductor 205 at least partially. At least part of the conductor 242_1 and the conductor 242_2 is formed to overlap with the conductor 209 . By forming the conductors 242_1 and 242_2, part of the region of the insulator 222 overlapping with the conductor 209 is exposed.
  • a dry etching method or a wet etching method can be used for the above processing. Further, the conductive film to be the conductor 242_1 and the conductive film to be the conductor 242_2 may be processed under different conditions.
  • an insulator 275 is formed to cover the insulator 224 , the oxide 230 a , the oxide 230 b , the conductors 242_1 , and 242_2 , and the insulator 280 is formed over the insulator 275 .
  • the conductor 242_1, the conductor 242_2, the insulator 275, and the insulator 280 are processed to form an opening reaching the oxide 230b (FIG. 11A).
  • the insulator 275 is preferably in contact with the top surface of the insulator 222 .
  • an insulator with a flat top surface is preferably formed by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film.
  • a silicon nitride film may be formed over the insulator 280 by a sputtering method, for example, and CMP treatment may be performed until the silicon nitride reaches the insulator 280 .
  • An opening to oxide 230b is provided in the region where oxide 230b and conductor 205 overlap.
  • the insulators 275 and 280 can each be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.
  • An insulator having a function of suppressing permeation of oxygen is preferably used for the insulator 275 .
  • silicon nitride is preferably deposited by ALD.
  • the function of suppressing the diffusion of water, impurities such as hydrogen, and oxygen can be improved.
  • the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275 having a function of suppressing diffusion of oxygen. Accordingly, direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 in a later step can be suppressed.
  • the insulator 280 is preferably formed using silicon oxide by a sputtering method.
  • the insulator 280 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas. Note that heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air.
  • a dry etching method or a wet etching method can be used for the above processing. Further, the processing of the conductor 242_1, the conductor 242_2, the insulator 275, and the insulator 280 may be performed under different conditions.
  • the conductor 242_1 is divided into island-shaped conductors 242a1 and 242b1.
  • the conductor 242_2 is divided into island-shaped conductors 242a2 and 242b2, respectively.
  • the two conductors 242 a 1 illustrated in FIG. 11A may each be provided in an island shape, or may be one island-shaped film having an opening overlapping with the conductor 209 .
  • the two conductors 242 a 2 shown in FIG. 11A may each be provided in an island shape, or may be one island-shaped film having an opening overlapping with the conductor 209 .
  • impurities adhere to the side surface of the oxide 230a, the top surface and side surface of the oxide 230b, the side surface of the conductors 242a and 242b, the side surface of the insulator 275, the side surface of the insulator 280, or the like, or do not enter the inside thereof. Diffusion of the impurity may occur. A step of removing such impurities may be performed. Also, the dry etching may form a damaged region on the surface of the oxide 230b. Such damaged areas may be removed.
  • the impurities include, for example, components contained in the insulator 280, the insulator 275, and the conductors 242a and 242b, components contained in members of an apparatus used for forming the opening, and gas or gas used for etching. Examples include those caused by the components contained in the liquid.
  • Such impurities include, for example, hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.
  • impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, impurities such as aluminum and silicon are preferably removed from the surface of the oxide 230b and its vicinity. Further, it is preferable that the concentration of the impurity is reduced.
  • the concentration of aluminum atoms on and near the surface of the oxide 230b is preferably 5.0 atomic percent or less, more preferably 2.0 atomic percent or less, more preferably 1.5 atomic percent or less, and 1.0 atomic percent. % or less, and more preferably less than 0.3 atomic %.
  • the regions with low crystallinity of the oxide 230b are preferably reduced or removed.
  • oxide 230b have a layered CAAC structure.
  • the CAAC structure up to the lower end of the drain of the oxide 230b.
  • the conductor 242a or the conductor 242b functions as a drain.
  • the oxide 230b in the vicinity of the lower end portion of the conductor 242a or the conductor 242b has a CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the low crystallinity region of the oxide 230b is removed, and the CAAC structure can further suppress variations in the electrical characteristics of the transistor. . In addition, reliability of the transistor can be improved.
  • a cleaning process is performed to remove impurities attached to the surface of the oxide 230b in the etching process.
  • a cleaning method there are wet cleaning using a cleaning solution (also referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate. Note that the cleaning process may deepen the groove.
  • Wet cleaning may be performed using an aqueous solution obtained by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water, pure water, carbonated water, or the like.
  • aqueous solution obtained by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water, pure water, carbonated water, or the like.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these washings may be appropriately combined.
  • an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid
  • an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water.
  • concentration, temperature, and the like of the aqueous solution are appropriately adjusted depending on impurities to be removed, the structure of the semiconductor device to be cleaned, and the like.
  • the ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, more preferably 0.1% or more and 0.5% or less.
  • the hydrogen fluoride concentration of diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, more preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher is preferably used, and a frequency of 900 kHz or higher is more preferably used. By using the frequency, damage to the oxide 230b and the like can be reduced.
  • the cleaning treatment may be performed multiple times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted ammonia water may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.
  • Heat treatment may be performed after the etching or after the cleaning.
  • the temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher and 650° C. or lower, 600° C. or lower, 550° C. or lower, or 400° C. or lower.
  • the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxides 230a and 230b, and oxygen vacancies can be reduced. Further, by performing such heat treatment, the crystallinity of the oxide 230b can be improved.
  • the supplied oxygen reacts with the hydrogen remaining in the oxides 230a and 230b, so that the hydrogen can be removed as H 2 O (dehydrated). Accordingly, hydrogen remaining in the oxides 230a and 230b can be suppressed from being recombined with oxygen vacancies to form VOH .
  • heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the air.
  • the sheet resistance of the regions of the oxide 230b overlapping with the conductors 242a and 242b decreases. Sometimes. Also, the carrier concentration may increase. Therefore, the resistance of the region of the oxide 230b overlapping with the conductor 242a and the region of the oxide 230b overlapping with the conductor 242b can be reduced in a self-aligning manner.
  • an insulating film and a conductive film are formed and processed so as to fill the opening, so that the insulator 253, the insulator 254, the conductor 260a, and the conductor 260b are provided in positions overlapping with the conductor 205. (FIG. 11B).
  • an insulating film to be the insulator 253 is formed.
  • the insulating film can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film is preferably formed using an ALD method.
  • the insulator 253 is preferably formed with a small film thickness and needs to have a small variation in thickness.
  • the ALD method is a method of forming a film by alternately introducing a precursor and a reactant (for example, an oxidizing agent). Film thickness can be adjusted. Also, as shown in FIG.
  • the insulator 253 needs to be deposited on the bottom and side surfaces of the opening with good coverage.
  • atomic layers can be deposited one by one on the bottom and side surfaces of the opening, so that the insulator 253 can be formed with good coverage over the opening.
  • ozone (O 3 ), oxygen (O 2 ), water (H 2 O), or the like can be used as an oxidant.
  • oxygen (O 2 ), or the like that does not contain hydrogen can be reduced.
  • the insulating film to be the insulator 253 is formed using hafnium oxide by a thermal ALD method.
  • microwave treatment refers to treatment using an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to 2.45 GHz, for example.
  • High-density oxygen radicals can be generated by using high-density plasma.
  • the power of the power source for applying microwaves in the microwave processing apparatus is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power supply for applying RF to the substrate side. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • the microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less.
  • the treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be set to, for example, about 250°C.
  • heat treatment may be continuously performed without exposure to the outside air.
  • the temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower.
  • the microwave treatment can be performed using oxygen gas and argon gas.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 100%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 50%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is 10% or more and 40% or less.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 10% or more and 30% or less.
  • oxygen gas is plasmatized using microwaves or high frequencies such as RF, and the oxygen plasma is generated between the conductors 242a and 242b of the oxide 230b.
  • a region can be affected.
  • V OH in the region can be split into oxygen vacancies and hydrogen, and hydrogen can be removed from the region. That is, VOH contained in the channel formation region can be reduced. Therefore, oxygen vacancies and VOH in the channel formation region can be reduced, and the carrier concentration can be lowered.
  • the oxygen vacancies in the channel formation region can be further reduced and the carrier concentration can be lowered.
  • Oxygen implanted into the channel formation region has various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, atoms, molecules, or ions having unpaired electrons). Note that oxygen to be implanted into the channel forming region may be one or more of the above forms, and oxygen radicals are particularly preferable. In addition, since the film quality of the insulator 253 can be improved, the reliability of the transistor is improved.
  • oxide 230b has a region that overlaps with either conductor 242a or 242b.
  • the region can function as a source region or a drain region.
  • the conductors 242a and 242b preferably function as shielding films against the action of microwaves, high frequencies such as RF, and oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
  • Conductors 242a and 242b shield the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like, so that these effects do not extend to regions of oxide 230b that overlap with conductors 242a and 242b. As a result, reduction of V OH and supply of an excessive amount of oxygen do not occur in the source region and the drain region due to microwave treatment, so that a decrease in carrier concentration can be prevented.
  • An insulator 253 having a barrier property against oxygen is provided in contact with side surfaces of the conductors 242a and 242b. Accordingly, formation of an oxide film on the side surfaces of the conductors 242a and 242b due to the microwave treatment can be suppressed.
  • the film quality of the insulator 253 can be improved, the reliability of the transistor is improved.
  • oxygen vacancies and VOH can be selectively removed from the channel formation region of the oxide semiconductor to make the channel formation region i-type or substantially i-type. Furthermore, excessive supply of oxygen to a region functioning as a source region or a drain region can be suppressed, and conductivity (a state of a low-resistance region) before microwave treatment can be maintained. As a result, variations in the electrical characteristics of the transistors can be suppressed, and variation in the electrical characteristics of the transistors within the substrate surface can be suppressed.
  • microwave treatment heat energy may be directly transferred to the oxide 230b due to electromagnetic interaction between the microwave and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b.
  • Such heat treatment is sometimes called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. Further, when hydrogen is contained in the oxide 230b, it is conceivable that this thermal energy is transmitted to hydrogen in the oxide 230b and thus activated hydrogen is released from the oxide 230b.
  • the microwave treatment may not be performed after the insulating film to be the insulator 253 is formed, and the microwave treatment may be performed before the insulating film is formed.
  • heat treatment may be performed while the reduced pressure state is maintained.
  • hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be removed efficiently.
  • some of the hydrogen may be gettered by the conductors 242a and 242b.
  • the step of performing the heat treatment may be repeated a plurality of times while the reduced pressure state is maintained. By repeating the heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be removed more efficiently.
  • the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.
  • the above-described microwave treatment that is, microwave annealing may serve as the heat treatment. When the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.
  • the film quality of the insulating film to be the insulator 253 by microwave treatment, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, in a post-process such as formation of a conductive film to be the conductor 260 or a post-treatment such as heat treatment, hydrogen, water, impurities, or the like are diffused into the oxide 230b, the oxide 230a, or the like through the insulator 253. can be suppressed.
  • an insulating film to be the insulator 254 is formed.
  • the insulating film can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film is preferably formed by an ALD method, similarly to the insulating film to be the insulator 253 .
  • the insulating film to be the insulator 254 can be formed with a thin film thickness and good coverage.
  • silicon nitride is deposited as the insulating film by the PEALD method.
  • a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are formed in this order.
  • the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, respectively, for example.
  • titanium nitride is deposited as a conductive film to be the conductor 260a by an ALD method
  • tungsten is deposited as a conductive film to be the conductor 260b by a CVD method.
  • the insulating film to be the insulator 253, the insulating film to be the insulator 254, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are polished until the insulator 280 is exposed. do. That is, portions of the insulating film to be the insulator 253, the insulating film to be the insulator 254, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are removed from the openings.
  • an insulator 253, an insulator 254, and a conductor 260 are formed in the opening overlapping with the conductor 205 (FIG. 11B).
  • the insulator 253 is provided in contact with the inner wall and side surfaces of the opening overlapping with the oxide 230b, and the insulator 254 is provided along the inner wall and side surfaces of the opening with the insulator 253 interposed therebetween.
  • the conductor 260 is arranged to fill the opening with the insulators 253 and 254 interposed therebetween.
  • transistors 202a, 202b are formed. As described above, the transistors 202a and 202b can be manufactured in parallel in the same process.
  • heat treatment may be performed under the same conditions as the above heat treatment.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • the concentration of moisture and the concentration of hydrogen in the insulator 280 can be reduced.
  • the insulator 282 may be formed continuously without exposure to the air.
  • an insulator 282 is formed over the insulators 253 and 254, the conductor 260, and the insulator 280 (FIG. 11B).
  • the insulator 282 can be deposited using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, for example.
  • the insulator 282 is preferably deposited by a sputtering method.
  • the concentration of hydrogen in the insulator 282 can be reduced by using a sputtering method that does not require molecules containing hydrogen in the deposition gas.
  • the insulator 282 aluminum oxide is deposited as the insulator 282 by a pulse DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas.
  • the pulse DC sputtering method By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.
  • the RF power applied to the substrate is 1.86 W/cm 2 or less. Preferably, it is 0 W/cm 2 or more and 0.62 W/cm 2 or less. Note that the RF power of 0 W/cm 2 is synonymous with applying no RF power to the substrate.
  • the amount of oxygen injected into layers below the insulator 282 can be controlled by the amount of RF power applied to the substrate.
  • the insulator 282 may be formed to have a two-layer structure.
  • the lower layer of the insulator 282 is formed with an RF power of 0 W/cm 2 applied to the substrate, and the upper layer of the insulator 282 is formed with an RF power of 0.62 W/cm 2 applied to the substrate. film.
  • the RF frequency is preferably 10 MHz or higher. It is typically 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while the insulator 280 is being formed.
  • the insulator 280 can contain excess oxygen.
  • the insulator 282 is preferably formed while heating the substrate.
  • insulators 282, 280, 275, 222, 216, 214, and 212 are processed by lithography to expose part of the upper surface of conductor 209 (FIG. 12A).
  • a dry etching method or a wet etching method can be used to form the opening. Since processing by a dry etching method is suitable for fine processing, it is preferable to use a dry etching method.
  • a dry etching method As the etching gas, any of the above gases can be used.
  • aluminum oxide and hafnium oxide may be more difficult to etch than silicon oxide or silicon oxynitride. It can also be said that aluminum oxide and hafnium oxide are each difficult-to-etch materials.
  • opening the insulators in advance enables the processing step in FIG. 12A to be performed with high yield, thereby improving the productivity of the semiconductor device. can be done.
  • FIG. 12A shows an example in which the widths of the openings provided in the insulator 282 and the insulator 280 are approximately the same, but the present invention is not limited to this. If the insulator 282 and the insulator 280 have different etching rates, even if the insulator 282 and the insulator 280 are opened together, the edges of the insulator 282 and the insulator 280 may not be aligned in a cross-sectional view.
  • FIG. 12A shows an example in which the end of the conductor 242a and the ends of the insulators 212, 214, 216, and 222 approximately match each other in the opening, but this is not restrictive.
  • one or more of the insulators 212, 214, 216, and 222 may be side-etched so that the end of the conductor 242a is located inside (on the transistor side) the end of the conductor 242a. be.
  • openings are preferably formed in the insulators 212, 214, 216, 222, 275, 280, and 282 by anisotropic etching.
  • a dry etching method is preferably used for the anisotropic etching. Thereby, for example, an opening having the shape shown in FIG. 1 or 2 can be formed.
  • the width of the opening may then be widened by isotropic etching.
  • isotropic etching thereby, for example, an opening having a shape shown in FIG. 3 can be formed.
  • the width of the opening of the insulator 216 or the like can be increased while maintaining the width between the two conductors 242a.
  • a dry etching method or a wet etching method can be used for the isotropic etching.
  • Anisotropic etching and isotropic etching are preferably performed continuously without exposure to the atmosphere by using the same etching apparatus under different conditions.
  • dry etching is used for both anisotropic etching and isotropic etching, one or more of conditions such as power supply power, bias power, etching gas flow rate, etching gas species, and pressure It is possible to switch from anisotropic etching to isotropic etching by changing .
  • etching methods may be used for anisotropic etching and isotropic etching.
  • a dry etching method can be used for anisotropic etching
  • a wet etching method can be used for isotropic etching.
  • a conductive film to be the conductor 240a1 and a conductive film to be the conductor 240b1 are formed in this order.
  • the conductive film to be the conductor 240a1 preferably has a function of suppressing permeation of impurities such as water and hydrogen.
  • impurities such as water and hydrogen.
  • tantalum nitride or titanium nitride can be used for the conductive film to be the conductor 240a1.
  • tungsten, molybdenum, or copper can be used for the conductive film to be the conductor 240b1.
  • These conductive films can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • part of the conductive film to be the conductor 240a1 and part of the conductive film to be the conductor 240b1 are removed, and the top surface of the insulator 282 is exposed.
  • these conductive films remain only in the openings, so that conductors 240_1 (conductors 240a1 and 240b1) with flat top surfaces can be formed (FIG. 12B).
  • conductors 240_1 (conductors 240a1 and 240b1) with flat top surfaces can be formed (FIG. 12B). Note that part of the top surface of the insulator 282 is removed by the CMP treatment in some cases.
  • the conductor 240 electrically connected to the conductor 209 and the conductor 242a can be manufactured.
  • the insulators 282, 280 and 275 are processed by lithography to form openings reaching the conductors 242b (FIG. 12C).
  • the width of the opening formed in this step is preferably fine.
  • the width of the opening is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening provided in this step has a large aspect ratio, it is preferable to process part of the insulator 282, part of the insulator 280, and part of the insulator 275 by anisotropic etching.
  • processing by dry etching is preferable because it is suitable for fine processing. Further, the processing may be performed under different conditions.
  • capacitive elements 101a and 101b are formed to fill the openings. Specifically, the conductor 153, the insulator 154, the conductor 160a, and the conductor 160b are formed. The steps of forming the capacitive elements 101a and 101b will be described in detail below with reference to FIGS. 14 and 15. FIG.
  • a conductive film 153A to be the conductor 153 is formed so as to cover the opening and the insulator 282. Then, as shown in FIG.
  • the conductive film 153A is preferably formed in contact with the side and bottom surfaces of the opening. Therefore, the conductive film 153A is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method. For example, it is preferable to deposit titanium nitride or tantalum nitride using the ALD method or the CVD method.
  • a resist mask 152 is provided over the conductive film 153A, and the conductive film 153A is processed by a lithography method to form a conductor 153 (FIG. 14B). As a result, part of the conductor 153 is formed inside the opening, and the other part is in contact with part of the upper surface of the insulator 282 .
  • the conductive film 153A may be processed using a CMP method.
  • the top of the conductor 153 can be shaped to substantially match the top surface of the insulator 282 .
  • an insulating film 154A to be the insulator 154 is formed over the conductor 153 (FIG. 14C).
  • the insulating film 154A is preferably formed in contact with the conductor 153 provided inside the opening. Therefore, the insulating film 154A is preferably formed using a film formation method with good coverage, such as the ALD method or the CVD method.
  • the insulating film 154A is preferably formed using the above-described High-k material.
  • a conductive film 160A to be a conductor 160a and a conductive film 160B to be a conductor 160b are formed in order (FIG. 14C).
  • the conductive film 160A is preferably formed in contact with the insulating film 154A provided inside the opening, and the conductive film 160B is preferably formed so as to fill the opening. Therefore, the conductive films 160A and 160B are preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method.
  • a film formation method with good coverage such as an ALD method or a CVD method.
  • the average surface roughness of the upper surface of the conductive film 160B may increase as shown in FIG. 14C.
  • the insulating film 154A, the conductive film 160A, and the conductive film 160B are processed by lithography to form the insulator 154, the conductor 160a, and the conductor 160b (FIGS. 13A and 15B).
  • the insulator 154 , the conductor 160 a , and the conductor 160 b are preferably formed so as to cover side end portions of the conductor 153 .
  • the conductor 160 and the conductor 153 can be separated by the insulator 154, and short-circuiting between the conductor 160 and the conductor 153 can be suppressed.
  • the present invention is not limited to this.
  • a structure may be employed in which only the conductive films 160A and 160B are processed and the insulating film 154A is left unprocessed. Thereby, the processing steps of the insulator 154 can be reduced, and the productivity can be improved.
  • the capacitors 101a and 101b can be formed.
  • An insulator 284 is then preferably applied to fill between adjacent conductors 160 (FIGS. 13A and 15B). Further, the insulator 284 is preferably planarized by a CMP method.
  • the step shown in FIG. 15C is performed after the step shown in FIG. 15A. move on.
  • conductors 160a and 160c are formed by processing the conductive film 160A
  • conductors 160b and 160d are formed by processing the conductive film 160B.
  • a conductor 160 (conductors 160a and 160b) functioning as an upper electrode of the capacitor 101a and a conductor 161 (conductors 160c and 160d) functioning as a second gate electrode of the transistor 201a are formed. be able to.
  • the step shown in FIG. 16A is performed after the step shown in FIG. 14A.
  • a conductive film 153A is formed so as to cover the opening and the insulator 282
  • an insulating film 154A is formed on the conductive film 153A
  • a conductive film 160A is formed on the insulating film 154A.
  • a conductive film 160B is formed over the conductive film 160A.
  • the conductive film 160B is preferably formed so as to fill the opening.
  • the materials and formation methods that can be applied to the conductive film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are as described above.
  • the conductive film 160B is preferably planarized using the CMP method.
  • the conductive film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are processed by lithography.
  • a conductor 153, an insulator 154, a conductor 160a, and a conductor 160b are formed.
  • FIG. 16C shows an example of manufacturing a semiconductor device having the cross-sectional structure shown in FIG. 5B.
  • the conductive film 153A is processed to form conductors 153a and 153b
  • the insulating film 154A is processed to form insulators 154a and 154b.
  • conductors 160a and 160c are formed, and by processing the conductive film 160B, conductors 160b and 160d are formed.
  • a conductor 153a functioning as a lower electrode of the capacitor 101a, an insulator 154a functioning as a dielectric of the capacitor 101a, and a conductor 160 (conductors 160a and 160b) functioning as upper electrodes of the capacitor 101a are formed. and can be formed.
  • a conductor 161 (conductors 160c and 160d) functioning as a second gate electrode of the transistor 201a can be formed. Under the conductor 161, the insulator 154b and the conductor 153b remain.
  • the processing step illustrated in FIG. 16C is preferable because the conductive film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B can be opened with the same mask and the number of masks can be reduced.
  • FIG. 13B shows a cross-sectional configuration example when the formation of the insulator 282 of the second layer 11_2 is completed.
  • the semiconductor device illustrated in FIG. 1 can be manufactured.
  • the semiconductor device of this embodiment includes an OS transistor. Since an OS transistor has low off-state current, a semiconductor device or a memory device with low power consumption can be realized. In addition, since the OS transistor has high frequency characteristics, a semiconductor device or a memory device with high operating speed can be realized. In addition, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device or memory device can be realized.
  • the conductor 240 since the conductor 240 has a stacked structure of a plurality of conductors, manufacturing yield can be improved as compared to the case where one conductor is used.
  • a structure example of a memory device using the semiconductor device described in the above embodiment as a memory cell will be described.
  • a configuration example of a memory device in which a layer having a functional circuit having a function of amplifying and outputting a data potential held in a memory cell is provided between stacked layers having memory cells. explain.
  • FIG. 18 shows a block diagram of a storage device of one embodiment of the present invention.
  • a memory device 300 shown in FIG. 18 has a drive circuit 21 and a memory array 20 .
  • the memory array 20 has a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51 .
  • FIG. 18 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • 18 shows an example in which the functional circuit 51 is provided for each wiring BL functioning as a bit line, and the functional layer 50 includes a plurality of functional circuits 51 provided corresponding to n wirings BL. It shows an example with
  • the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n].
  • an arbitrary row may be referred to as i row.
  • j column when indicating an arbitrary column, it may be described as j column. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 10 in the i-th row and the j-th column is indicated as the memory cell 10[i,j].
  • the memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the wiring WL provided in the first line (first row) is indicated as the wiring WL[1]
  • the wiring WL provided in the m-th line (m-th row) is indicated as the wiring WL[m].
  • the wiring PL provided in the first line (first row) is indicated as a wiring PL[1]
  • the wiring PL provided in the m-th line (m-th row) is indicated as a wiring PL[m].
  • the wiring BL provided in the first line (first column) is referred to as the wiring BL[1]
  • the wiring BL provided in the nth line (nth column) is referred to as the wiring BL[n].
  • a plurality of memory cells 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • a plurality of memory cells 10 provided in the j-th column are electrically connected to a wiring BL in the j-th column (wiring BL[j]).
  • DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 20 .
  • a DOSRAM is a RAM having 1T (transistor) and 1C (capacitor) type memory cells, and is a memory in which an access transistor is an OS transistor. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leak current is extremely small.
  • a DOSRAM can hold electric charge corresponding to data held in a capacitive element (capacitor) for a long time by turning off (non-conducting) an access transistor. Therefore, a DOSRAM can reduce the frequency of refresh operations compared to a DRAM composed of a transistor (Si transistor) having silicon in a channel formation region. As a result, low power consumption can be achieved.
  • the memory cells 10 can be stacked.
  • a plurality of memory arrays 20[1] to 20[m] can be stacked.
  • the memory array 20[1] to 20[m] included in the memory array 20 in the direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, the memory density of the memory cells 10 can be improved.
  • the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20 .
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on/off (conducting state or non-conducting state) of an access transistor functioning as a switch.
  • the wiring PL has a function of transmitting a backgate potential to the backgate of the OS transistor, which is an access transistor, in addition to functioning as a constant potential line connected to the capacitor.
  • the memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through wirings BL.
  • the wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driving circuit 21 via the wiring GBL (not shown) described later. With this structure, a slight potential difference of the wiring BL can be amplified when data is read.
  • the wiring GBL can be arranged in the direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, like the wiring BL.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10 .
  • the wiring BL is provided in contact with a region functioning as a source or a drain of the semiconductor layer of the transistor included in the memory cell 10 .
  • the wiring BL is provided in contact with a conductor provided in contact with a region functioning as a source or a drain of the semiconductor layer of the transistor included in the memory cell 10 . That is, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor of the memory cell 10 in each layer of the memory array 20 and the functional circuit 51 in the vertical direction.
  • the memory array 20 can be provided over the driving circuit 21 .
  • the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and power consumption and signal delay can be reduced.
  • miniaturization of the storage device 300 can be realized.
  • the functional circuit 51 is composed of OS transistors in the same way as the transistors of the memory cells 10 of the DOSRAM, so that it can be freely placed on circuits using Si transistors like the memory arrays 20[1] to 20[m]. Since they can be arranged, they can be easily integrated. Since the function circuit 51 is configured to amplify the signal, circuits such as the sense amplifier 46 in the subsequent stage can be miniaturized, so that the memory device 300 can be miniaturized.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31 .
  • the peripheral circuit 31 has a peripheral circuit 41 , a control circuit 32 and a voltage generation circuit 33 .
  • each circuit, each signal, and each voltage can be omitted as appropriate. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • Signal BW, signal CE, and signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • the signal WDA is write data and the signal RDA is read data.
  • a signal PON1 and a signal PON2 are power gating control signals. The signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit having a function of controlling the overall operation of the storage device 300 .
  • the control circuit logically operates the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, write operation, read operation) of the memory device 300 .
  • control circuit 32 generates a control signal for peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33 . For example, when an H level signal is applied to signal WAKE, signal CLK is input to voltage generation circuit 33, and voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing data to and reading data from the memory cell 10 .
  • the peripheral circuit 41 is a circuit that outputs various signals for controlling the functional circuit 51 .
  • the peripheral circuit 41 includes a row decoder 42 (Row Decoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (Column Driver), an input circuit 47 (Input Circuit), an output circuit 48 ( Output Circuit) and a sense amplifier 46 (Sense Amplifier).
  • Row decoder 42 and column decoder 44 have the function of decoding signal ADDR.
  • Row decoder 42 is a circuit for specifying a row to be accessed
  • column decoder 44 is a circuit for specifying a column to be accessed.
  • Row driver 43 has a function of selecting line WL designated by row decoder 42 .
  • the column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, a function of holding the read data, and the like.
  • Input circuit 47 has a function of holding signal WDA. Data held by the input circuit 47 is output to the column driver 45 . Output data of the input circuit 47 is data (Din) to be written to the memory cell 10 . Data (Dout) read from the memory cells 10 by the column driver 45 is output to the output circuit 48 .
  • the output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the storage device 300 . Data output from the output circuit 48 is the signal RDA.
  • PSW 22 has a function of controlling the supply of VDD to peripheral circuit 31 .
  • PSW 23 has the function of controlling the supply of VHM to row driver 43 .
  • the high power supply voltage of the memory device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to drive word lines to a high level and is higher than VDD.
  • the signal PON1 controls ON/OFF of the PSW22, and the signal PON2 controls ON/OFF of the PSW23.
  • the number of power supply domains to which VDD is supplied is set to one, but may be set to a plurality. In this case, a power switch may be provided for each power domain.
  • the memory array 20 having the memory arrays 20[1] to 20[m] (m is an integer equal to or greater than 2) and the functional layer 50 can be provided by stacking a plurality of layers of the memory array 20 on the driving circuit 21.
  • FIG. 19A the memory array 20 provided in the first layer is indicated as memory array 20[1], the memory array 20 provided in the second layer is indicated as memory array 20[2], and the memory array 20 provided in the fifth layer is indicated as memory array 20[1].
  • the memory array 20 is shown as memory array 20[5].
  • FIG. 19A also shows the wiring WL and the wiring PL extending in the X direction, and the wiring BL extending in the Z direction (the direction perpendicular to the surface of the substrate provided with the driver circuit). Note that the wiring WL and the wiring PL included in each memory array 20 are partially omitted in order to make the drawing easier to see.
  • FIG. 19B is a schematic diagram illustrating a configuration example of the functional circuit 51 connected to the wiring BL illustrated in FIG. 19A and the memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. indicates FIG. 19B also illustrates the wiring GBL provided between the functional circuit 51 and the driver circuit 21 . Note that a structure in which a plurality of memory cells (memory cells 10) are electrically connected to one wiring BL is also called a “memory string”. Note that in the drawings, the wiring GBL may be illustrated with a thick line in order to improve visibility.
  • FIG. 19B illustrates an example of the circuit configuration of the memory cell 10 connected to the wiring BL.
  • a memory cell 10 includes a transistor 13 and a capacitor 12 .
  • Embodiment 1 can be referred to for a cross-sectional configuration example of the memory cell 10 corresponding to the circuit configuration.
  • the transistor 13 corresponds to the transistor 201a or the transistor 201b described in Embodiment 1.
  • the capacitor 12 corresponds to the capacitor 101a or the capacitor 101b described in Embodiment 1.
  • the wiring BL corresponds to the conductor 240 described in Embodiment 1.
  • the wiring BL (the conductor 240) has a conductive region including a region directly functioning as one of the source electrode and the drain electrode of the transistor 13 (the transistor 201a). It is in contact with at least one of a top surface, a side surface, and a bottom surface of the body 242a.
  • the degree of integration of the memory cells 10 is improved, and the storage capacity of the storage device 300 can be increased.
  • one of the source and the drain of the transistor 13 is connected to the wiring BL.
  • the other of the source and drain of the transistor 13 is connected to one electrode of the capacitor 12 .
  • the other electrode of the capacitive element 12 is connected to the wiring PL.
  • a gate of the transistor 13 is connected to the wiring WL.
  • a back gate of the transistor 13 is connected to the wiring PL.
  • the wiring PL is a wiring that applies a constant potential for holding the potential of the capacitor 12 . Further, the wiring PL can also be said to be a wiring that gives a constant potential for controlling the threshold voltage of the transistor 13 . For example, by supplying GND (ground potential) to the wiring PL, the stacked memory cells 10 can be electrically insulated. Further, by serving also as the back gate electrode of the transistor 13, off current can be sufficiently reduced.
  • GND ground potential
  • FIG. 20A shows a schematic diagram of the memory device 300 in which the functional circuit 51 and the memory arrays 20[1] to 20[m] are the repeating units 70.
  • FIG. 20A shows one wiring GBL as illustrated in FIG. 20A, the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50 .
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor included in the functional circuit 51 .
  • the wiring GBL is provided in contact with a region functioning as a source or a drain of the semiconductor layer of the transistor included in the functional circuit 51 .
  • the wiring GBL is provided in contact with a conductor provided in contact with a region functioning as a source or a drain of the semiconductor layer of the transistor included in the functional circuit 51 .
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the functional circuit 51 in the functional layer 50 and the driving circuit 21 in the vertical direction.
  • repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be stacked.
  • a storage device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 20B.
  • the wiring GBL is connected to the functional layer 50 included in the repeating unit 70 .
  • the wiring GBL may be provided as appropriate according to the number of functional circuits 51 .
  • OS transistors are stacked and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of the substrate over which the driver circuit 21 is provided.
  • the length of the wiring between the memory array 20 and the drive circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.
  • the layer provided with the memory array 20 includes a functional layer 50 having a functional circuit 51 having a function of amplifying and outputting the data potential held in the memory cell 10 .
  • the sense amplifier 46 included in the driver circuit 21 can be driven by amplifying a slight potential difference of the wiring BL functioning as a bit line when data is read. Since a circuit such as a sense amplifier can be miniaturized, miniaturization of the memory device 300 can be achieved. In addition, the memory cell 10 can be operated even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.
  • FIG. 21 A configuration example of the functional circuit 51 described with reference to FIGS. 18 to 20 and a configuration example of the sense amplifier 46 included in the memory array 20 and the drive circuit 21 will be described with reference to FIG.
  • functional circuits 51 (functional circuit 51_A, functional circuit 51_B) connected to memory cells 10 (memory cell 10_A, memory cell 10_B) connected to different wirings BL (wiring BL_A, wiring BL_B) are connected.
  • the driver circuit 21 connected to the wiring GBL (the wiring GBL_A and the wiring GBL_B) is illustrated.
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are shown.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as functional circuits 51_A and 51_B.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 21 are OS transistors like the transistor 13 included in the memory cell 10 .
  • the functional layer 50 having the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].
  • the wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b.
  • the wiring GBL_A is connected to one of the sources and drains of the transistors 53_a and 54_a.
  • the wiring GBL_B is connected to one of the sources and drains of the transistors 53_b and 54_b.
  • the wirings GBL_A and GBL_B are provided in the vertical direction similarly to the wirings BL_A and BL_B, and are connected to transistors included in the driver circuit 21 . Gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with the selection signal MUX, the control signal WE, or the control signal RE, respectively, as shown in FIG.
  • Transistors 81_1 to 81_6 and 82_1 to 82_4 forming the sense amplifier 46, the precharge circuit 71_A, and the precharge circuit 71_B shown in FIG. 21 are Si transistors.
  • the switches 83_A to 83_D that constitute the switch circuit 72_A and the switch circuit 72_B can also be composed of Si transistors.
  • One of the source or the drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to transistors or switches forming the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.
  • the precharge circuit 71_A includes n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A sets the wiring BL_A and the wiring BL_B to an intermediate potential corresponding to VDD/2 between the high power supply potential (VDD) and the low power supply potential (VSS) in accordance with a precharge signal applied to the precharge line PCL1. This is a circuit for precharging to the potential VPC.
  • the precharge circuit 71_B includes n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2. be.
  • the sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors forming an inverter loop.
  • the potentials of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switches 83_C and 83_D and the writing/reading circuit 73 .
  • the wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B correspond to a bit line pair.
  • the write/read circuit 73 is controlled to write the data signal according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling conduction between the sense amplifier 46 and the wirings GBL_A and GBL_B.
  • the switch circuit 72_A is switched on or off by control of the switching signal CSEL1.
  • the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on when it is at high level and turned off when it is at low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46 .
  • the switch circuit 72_B is switched on or off by control of the switching signal CSEL2.
  • Switches 83_C and 83_D may be similar to switches 83_A and 83_B.
  • the memory device 300 has a configuration in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected to each other through the wiring BL and the wiring GBL provided in the vertical direction which is the shortest distance. can be done. Although the number of functional layers 50 including transistors included in the functional circuit 51 is increased, the load on the wiring BL is reduced, so that writing time can be shortened and data can be easily read.
  • each transistor included in the functional circuits 51_A and 51_B is controlled according to the control signals WE and RE and the selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the driver circuit 21 through the wiring GBL in accordance with the control signal and the selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers including OS transistors. With this structure, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using a Si transistor.
  • FIG. 22 shows a timing chart for explaining the operation of the circuit diagram shown in FIG.
  • a period T11 is a write operation
  • a period T12 is a precharge operation of the wiring BL
  • a period T13 is a precharge operation of the wiring GBL
  • a period T14 is a charge sharing operation
  • a period T15 is a read standby operation.
  • the operation, period T16 corresponds to the period for explaining the read operation.
  • the potential of the wiring WL connected to the gate of the transistor 13 included in the memory cell 10 to which the data signal is to be written is set to a high level.
  • the control signal WE and the signal EN_data are set to a high level, and the data signal is written to the memory cell through the wiring GBL and the wiring BL.
  • the precharge line PCL1 is set to high level while the control signal WE is set to high level.
  • the wiring BL is precharged to the precharge potential.
  • both the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 46 are set to VDD/2 to suppress the power consumption due to the through current.
  • the precharge line PCL2 is set to a high level in order to precharge the wiring GBL.
  • the wiring GBL is precharged to the precharge potential.
  • the potentials of the wiring VHH and the wiring VLL are both set to VDD, so that the wiring GBL with a large load can be precharged in a short time.
  • the potential of the wiring WL is set to a high level for charge sharing for balancing the charge held in the memory cell 10 and the charge precharged in the wiring BL.
  • the potentials of the wiring VHH and the wiring VLL that supply the power supply voltage to the sense amplifier 46 are both preferably set to VDD/2 to suppress power consumption due to through current.
  • the control signal RE and the selection signal MUX are set to high level. Current flows through the transistor 52 according to the potential of the wiring BL, and the potential of the wiring GBL changes according to the amount of current.
  • the switching signal CSEL1 is set to low level to prevent the potential fluctuation of the wiring GBL from being affected by the sense amplifier 46.
  • FIG. The wiring VHH or the wiring VLL is the same as in the period T14.
  • the switching signal CSEL1 is set to a high level, and the change in the potential of the wiring GBL is amplified by the bit line pair connected to the sense amplifier 46, so that the data signal written to the memory cell is read.
  • FIG. 23A shows a functional circuit 51A corresponding to the functional circuit 51_A or 51_B shown in FIG.
  • the functional circuit 51A shown in FIG. 23A has transistors 52-55.
  • the transistors 52 to 55 can each be an OS transistor and are illustrated as n-channel transistors.
  • the transistor 52 is a source follower transistor for amplifying the potential of the wiring GBL to a potential corresponding to the potential of the wiring BL in a period in which a data signal is read from the memory cell 10 .
  • the transistor 53 is a transistor that receives a selection signal MUX at its gate and functions as a switch whose ON or OFF state between the source and the drain is controlled according to the selection signal MUX.
  • the transistor 54 is a transistor that receives a control signal WE at its gate and functions as a switch whose ON or OFF state between the source and the drain is controlled according to the control signal WE.
  • the transistor 55 is a transistor that receives a control signal RE at its gate and functions as a switch whose ON or OFF state between the source and the drain is controlled according to the control signal RE.
  • a ground potential GND which is a fixed potential, is applied to the source side of the transistor 55, for example.
  • the functional circuit 51B in FIG. 23B has a configuration in which the connection of one of the source and drain of the transistor 54 is switched from the wiring GBL to one of the source and drain of the transistor 52 .
  • a functional circuit 51C in FIG. 24A corresponds to a configuration in which the transistor 53 is omitted by performing the function of the transistor 53 in the drive circuit 21.
  • the functional circuit 51D in FIG. 24B corresponds to a configuration in which the transistor 55 is omitted.
  • a semiconductor device of one embodiment of the present invention uses an OS transistor with extremely low off-state current as a transistor provided in the memory array 20 .
  • the OS transistor can be stacked over the substrate provided with the driver circuit 21 provided with the Si transistor. Therefore, the same manufacturing process can be repeated in the vertical direction, and the manufacturing cost can be reduced.
  • the memory density can be improved by arranging the transistors included in the memory cell 10 not in the horizontal direction but in the vertical direction, so that the size of the memory device can be reduced.
  • one form of the present invention comprises a functional layer 50 having functional circuitry 51 . Since the functional circuit connects the wiring BL to the gate of the transistor 52, the transistor 52 can function as an amplifier. With this structure, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using a Si transistor. Since circuits such as the sense amplifier 46 using Si transistors can be miniaturized, miniaturization of the memory device can be achieved. In addition, the memory cell 10 can be operated even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.
  • SoC System on Chip
  • chip 1200 includes CPU 1211, GPU 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) to connect with the first surface of the package substrate 1201 as shown in FIG. 25B.
  • a plurality of bumps 1202 are provided on the rear surface of the first surface of the package substrate 1201 and connected to the motherboard 1203 .
  • the mother board 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222 .
  • storage devices such as a DRAM 1221 and a flash memory 1222 .
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221 .
  • the DRAM 1221 can be reduced in power consumption, increased in speed, and increased in capacity.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200 .
  • the aforementioned DOSRAM can be used for the memory.
  • the GPU 1212 is suitable for parallel computation of a large amount of data, and can be used for image processing or sum-of-products operations. By providing an image processing circuit using an OS transistor or a product-sum operation circuit in the GPU 1212, image processing or product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened. , and after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog computation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation unit 1213 may be provided with the sum-of-products calculation circuit.
  • the memory controller 1214 has a circuit functioning as a controller for the DRAM 1221 and a circuit functioning as an interface for the flash memory 1222 .
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used as such an interface.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the circuit (system) can be formed in the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212 , a motherboard 1203 provided with a DRAM 1221 and a flash memory 1222 can be called a GPU module 1204 .
  • the GPU module 1204 Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum operation circuit using the GPU 1212 enables a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recurrent neural network
  • DBM deep Boltzmann machine
  • DBN deep belief network
  • FIG. 26A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted.
  • An electronic component 700 illustrated in FIG. 26A includes a memory device 300 which is one embodiment of the present invention in a mold 711 .
  • FIG. 26A omits part of the description to show the inside of electronic component 700 .
  • Electronic component 700 has lands 712 outside mold 711 . Land 712 is electrically connected to electrode pad 713 , and electrode pad 713 is electrically connected to storage device 300 via wire 714 .
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed board 702 .
  • the memory device 300 has the drive circuit 21 and the memory array 20 .
  • FIG. 26B shows a perspective view of electronic component 730 .
  • Electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • An electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 300 provided on the interposer 731 .
  • Electronic component 730 shows an example in which storage device 300 is used as a high bandwidth memory (HBM).
  • HBM high bandwidth memory
  • an integrated circuit semiconductor device
  • a CPU, GPU, or FPGA can be used for the semiconductor device 735.
  • the package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 can use, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. A plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 also has a function of electrically connecting the integrated circuit provided over the interposer 731 to electrodes provided over the package substrate 732 . For these reasons, the interposer is sometimes called a "rewiring board” or an "intermediate board".
  • through electrodes are provided in the interposer 731 and the integrated circuit and the package substrate 732 are electrically connected using the through electrodes. Also, in the silicon interposer, a TSV (Through Silicon Via) can be used as a through electrode.
  • a silicon interposer is preferably used as the interposer 731 . Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with the resin interposer.
  • HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, an interposer for mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts the HBM.
  • a heat sink may be provided overlapping with the electronic component 730 .
  • a heat sink it is preferable that the heights of the integrated circuits provided over the interposer 731 be uniform.
  • the memory device 300 and the semiconductor device 735 have the same height.
  • Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate.
  • FIG. 26B shows an example in which the electrodes 733 are formed from solder balls.
  • BGA All Grid Array
  • the electrodes 733 may be formed of conductive pins.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of implementation methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package). receipt) is mentioned.
  • SPGA Stablgered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN Quad Flat Non-leaded package
  • the storage device of one embodiment of the present invention is a storage device of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording/playback devices, navigation systems, and game machines). Applicable. It can also be used for image sensors, IoT (Internet of Things), healthcare-related equipment, and the like. Thereby, power saving of the electronic device can be achieved.
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • 27A to 27J and 28A to 28E show how each electronic device includes the electronic component 700 or the electronic component 730 having the storage device described in the previous embodiment. Illustrated.
  • An information terminal 5500 shown in FIG. 27A is a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • the display portion 5511 is provided with a touch panel, and the housing 5510 is provided with buttons.
  • the information terminal 5500 can hold temporary files generated when an application is executed (for example, a cache when using a web browser).
  • FIG. 27B shows an information terminal 5900 that is an example of a wearable terminal.
  • An information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.
  • the wearable terminal can hold temporary files generated when an application is executed, like the information terminal 5500 described above.
  • a desktop information terminal 5300 is shown in FIG. 27C.
  • a desktop information terminal 5300 includes an information terminal main body 5301 , a display section 5302 , and a keyboard 5303 .
  • the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying the storage device of one embodiment of the present invention.
  • smartphones, wearable terminals, and desktop information terminals have been described as electronic devices, but other information terminals include, for example, a PDA (Personal Digital Assistant), a notebook information terminal, and workstations.
  • PDA Personal Digital Assistant
  • FIG. 27D shows an electric refrigerator-freezer 5800 as an example of an appliance.
  • the electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric freezer-refrigerator 5800 is an electric freezer-refrigerator compatible with IoT (Internet of Things).
  • the storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800 .
  • the electric freezer-refrigerator 5800 can transmit and receive information such as foodstuffs stored in the electric freezer-refrigerator 5800 and expiration dates of the foodstuffs to and from an information terminal or the like via the Internet or the like.
  • Electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the storage device of one embodiment of the present invention.
  • an electric refrigerator-freezer was described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washers, dryers, and audiovisual equipment.
  • FIG. 27E shows a portable game machine 5200, which is an example of a game machine.
  • a portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 27F shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 can be said to be a household stationary game machine in particular.
  • a stationary game machine 7500 has a main body 7520 and a controller 7522 .
  • a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit for displaying game images, a touch panel, a stick, a rotary knob, or a slide knob that serves as an input interface other than buttons.
  • the shape of the controller 7522 is not limited to that shown in FIG. 27F, and the shape of the controller 7522 may be changed variously according to the genre of the game.
  • a button can be used as a trigger and a controller shaped like a gun can be used.
  • a controller shaped like a musical instrument, music equipment, or the like can be used.
  • the stationary game machine may not use a controller, but may instead include one or more of a camera, a depth sensor, and a microphone, and be operated by the game player's gestures or voice.
  • the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the storage device of one embodiment of the present invention By applying the storage device of one embodiment of the present invention to the portable game machine 5200 or the stationary game machine 7500, power consumption can be reduced. In addition, due to the low power consumption, heat generation from the circuit can be reduced, and the influence of the heat generation on the circuit itself, the peripheral circuits, and the module can be reduced.
  • FIGS. 27E and 27F a portable game machine and a home-use stationary game machine are described as examples of game machines, but other game machines are installed in entertainment facilities (game centers, amusement parks, etc.), for example. and arcade game machines installed in sports facilities, and pitching machines for batting practice installed in sports facilities.
  • the storage device of one embodiment of the present invention can be applied to automobiles, which are mobile objects, and to the vicinity of the driver's seat of automobiles.
  • FIG. 27G shows an automobile 5700, which is an example of a mobile object.
  • a driver's seat of the automobile 5700 is an instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, and the like. Further, a storage device showing such information may be provided around the driver's seat.
  • the display device can compensate for the blind spots in the driver's seat and the visibility blocked by pillars, etc., and enhance safety. be able to. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be enhanced.
  • the storage device of one embodiment of the present invention can temporarily store information. It can be used to hold general information.
  • the display device may be configured to display temporary information such as road guidance and danger prediction. Also, a configuration may be adopted in which the image of the driving recorder installed in the automobile 5700 is held.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drone), airplanes, and rockets).
  • a storage device of one embodiment of the present invention can be applied to a camera.
  • FIG. 27H shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display portion 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may have a configuration in which a strobe device, a viewfinder, and the like can be attached separately.
  • the storage device of one embodiment of the present invention By applying the storage device of one embodiment of the present invention to the digital camera 6240, power consumption can be reduced. In addition, due to the low power consumption, heat generation from the circuit can be reduced, and the influence of the heat generation on the circuit itself, the peripheral circuits, and the module can be reduced.
  • a storage device of one embodiment of the present invention can be applied to a video camera.
  • FIG. 27I shows a video camera 6300 as an example of an imaging device.
  • a video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, operation switches 6304, a lens 6305, a connection portion 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided on the first housing 6301 and the display section 6303 is provided on the second housing 6302 .
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306 .
  • the video camera 6300 can temporarily hold files generated during encoding.
  • a storage device of one aspect of the present invention can be applied to an implantable cardioverter-defibrillator (ICD).
  • ICD implantable cardioverter-defibrillator
  • FIG. 27J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body with one wire tip placed in the right ventricle and the other wire tip placed in the right atrium. be done.
  • the ICD main body 5400 has a function as a pacemaker, and paces the heart when the heart rate deviates from the prescribed range. In addition, if pacing does not improve the heart rate (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with electric shocks is performed.
  • the ICD body 5400 must constantly monitor heart rate in order to properly pace and deliver shocks. Therefore, the ICD main body 5400 has a sensor for detecting heart rate. In addition, the ICD main body 5400 can store the heart rate data obtained by the sensor or the like, the number of pacing treatments, the time, and the like in the electronic component 700 .
  • the ICD main body 5400 has a plurality of batteries, so that safety can be enhanced. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the rest of the batteries can still function, so the ICD also functions as an auxiliary power source.
  • an antenna capable of transmitting physiological signals may be provided.
  • a system may be configured to monitor various cardiac activity.
  • a storage device of one embodiment of the present invention can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.
  • FIG. 28A shows an expansion device 6100 externally attached to a PC, mounted with a portable chip capable of storing information, as an example of the expansion device.
  • the expansion device 6100 can store information by the chip, for example, by connecting to a PC via a USB (Universal Serial Bus) or the like.
  • FIG. 28A illustrates the expansion device 6100 in a portable form, the expansion device of one aspect of the present invention is not limited to this. It may also be an expansion device in the form of a
  • the expansion device 6100 has a housing 6101 , a cap 6102 , a USB connector 6103 and a substrate 6104 .
  • a substrate 6104 is housed in a housing 6101 .
  • the substrate 6104 is provided with a circuit that drives the memory device or the like of one embodiment of the present invention.
  • substrate 6104 has electronic component 700 and controller chip 6106 mounted thereon.
  • a USB connector 6103 functions as an interface for connecting with an external device.
  • SD card A storage device of one embodiment of the present invention can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.
  • FIG. 28B is a schematic diagram of the appearance of the SD card
  • FIG. 28C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111 , a connector 5112 and a substrate 5113 .
  • a connector 5112 functions as an interface for connecting with an external device.
  • a substrate 5113 is housed in a housing 5111 .
  • a substrate 5113 is provided with a memory device and a circuit for driving the memory device.
  • the electronic component 700 and the controller chip 5115 are attached to the substrate 5113 .
  • the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances. For example, a write circuit, a row driver, a read circuit, and the like included in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 700 .
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided over the substrate 5113 .
  • wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 700.
  • SSD Solid State Drive
  • electronic device such as an information terminal
  • FIG. 28D is a schematic diagram of the appearance of the SSD
  • FIG. 28E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151 , a connector 5152 and a substrate 5153 .
  • a connector 5152 functions as an interface for connecting with an external device.
  • a substrate 5153 is housed in a housing 5151 .
  • a substrate 5153 is provided with a memory device and a circuit for driving the memory device.
  • substrate 5153 has electronic component 700 , memory chip 5155 and controller chip 5156 mounted thereon. By providing the electronic component 700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased.
  • the memory chip 5155 incorporates a work memory.
  • the memory chip 5155 can be a DRAM chip.
  • the controller chip 5156 incorporates a processor, an ECC (Error Check and Correct) circuit, and the like. Note that the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances. For example, the controller chip 5156 may also be provided with a memory functioning as a work memory.
  • ECC Error Check and Correct
  • a computer 5600 shown in FIG. 29A is an example of a large computer.
  • a rack 5610 stores a plurality of rack-mounted computers 5620 .
  • Calculator 5620 may, for example, have the configuration of the perspective view shown in FIG. 29B.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631 .
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are connected to the mother board 5630 respectively.
  • a PC card 5621 shown in FIG. 29C is an example of a processing board including a CPU, GPU, storage device, and the like.
  • the PC card 5621 has a board 5622 .
  • the board 5622 has a connection terminal 5623 , a connection terminal 5624 , a connection terminal 5625 , a semiconductor device 5626 , a semiconductor device 5627 , a semiconductor device 5628 , and a connection terminal 5629 .
  • FIG. 29C illustrates semiconductor devices other than the semiconductor devices 5626, 5627, and 5628; The description of the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the mother board 5630 , and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the mother board 5630 .
  • Examples of standards for the connection terminal 5629 include PCIe.
  • connection terminals 5623 , 5624 , and 5625 can be interfaces for power supply and signal input to the PC card 5621 , for example. Also, for example, an interface for outputting a signal calculated by the PC card 5621 can be used.
  • Standards for the connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface).
  • USB Universal Serial Bus
  • SATA Serial ATA
  • SCSI Serial Computer System Interface
  • the semiconductor device 5626 has a terminal (not shown) for signal input/output, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 are electrically connected. can be connected to
  • the semiconductor device 5627 has a plurality of terminals, and the terminals are electrically connected to the wiring of the board 5622 by, for example, reflow soldering. be able to.
  • Examples of the semiconductor device 5627 include FPGA (Field Programmable Gate Array), GPU, and CPU.
  • the electronic component 730 can be used, for example.
  • the semiconductor device 5628 has a plurality of terminals, and the terminals are electrically connected to the wiring of the board 5622 by, for example, reflow soldering. be able to.
  • Examples of the semiconductor device 5628 include a memory device.
  • the semiconductor device 5628 the electronic component 700 can be used, for example.
  • Computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, it is possible to perform large-scale calculations necessary for artificial intelligence learning and inference.
  • the electronic devices can be made smaller and consume less power. Further, since the memory device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to the heat generation can be reduced. Further, by using the memory device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of electronic equipment can be improved.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • An OS transistor has little change in electrical characteristics due to irradiation with radiation. In other words, since it has high resistance to radiation, it can be suitably used in an environment where radiation may be incident.
  • OS transistors can be suitably used when used in outer space.
  • the OS transistor can be used for a transistor included in a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Radiation includes, for example, X-rays, neutron beams, and the like.
  • Outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.
  • FIG. 30 shows an artificial satellite 6800 as an example of space equipment.
  • Artificial satellite 6800 has fuselage 6801 , solar panel 6802 , antenna 6803 , secondary battery 6805 , and controller 6807 .
  • FIG. 30 illustrates a planet 6804 in outer space.
  • outer space is an environment with a radiation dose that is more than 100 times higher than that on the ground.
  • radiation include electromagnetic radiation (electromagnetic radiation) typified by X-rays and gamma rays, and particle radiation typified by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays. be done.
  • Solar panel 6802 is irradiated with sunlight to generate power necessary for satellite 6800 to operate. However, less power is generated, for example, in situations where the solar panel is not illuminated by sunlight, or where the amount of sunlight illuminated by the solar panel is low. Thus, the power required for satellite 6800 to operate may not be generated.
  • a secondary battery 6805 may be provided in the satellite 6800 so that the satellite 6800 can operate even when the generated power is low. Note that the solar panel is sometimes called a solar cell module.
  • Satellite 6800 may generate a signal.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a receiver located on the ground or other satellite.
  • a receiver located on the ground or other satellite.
  • the position of the receiver that received the signal can be determined.
  • artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800 .
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor that is one embodiment of the present invention is preferably used for the control device 6807 .
  • An OS transistor has less variation in electrical characteristics due to radiation irradiation than a Si transistor. In other words, it has high reliability and can be suitably used even in an environment where radiation may be incident.
  • the artificial satellite 6800 can be configured to have a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight that hits an object on the ground and is reflected.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface by adopting a configuration having a thermal infrared sensor.
  • the artificial satellite 6800 can function as an earth observation satellite, for example.
  • an artificial satellite is used as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
  • the OS transistor can be used as a transistor included in a semiconductor device provided in a nuclear power plant, a radioactive waste disposal site, or a working robot in a disposal site.
  • it can be suitably used for a transistor that constitutes a semiconductor device provided in a remote-controlled robot that is remotely controlled for dismantling nuclear reactor facilities, retrieving nuclear fuel or fuel debris, and conducting field surveys in spaces with a large amount of radioactive materials.

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