WO2023155140A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2023155140A1
WO2023155140A1 PCT/CN2022/076859 CN2022076859W WO2023155140A1 WO 2023155140 A1 WO2023155140 A1 WO 2023155140A1 CN 2022076859 W CN2022076859 W CN 2022076859W WO 2023155140 A1 WO2023155140 A1 WO 2023155140A1
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WO
WIPO (PCT)
Prior art keywords
fan
line
cluster
bundle
sub
Prior art date
Application number
PCT/CN2022/076859
Other languages
English (en)
French (fr)
Inventor
王欣欣
张波
初志文
屈忆
冯翱远
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000218.XA priority Critical patent/CN116917799A/zh
Priority to PCT/CN2022/076859 priority patent/WO2023155140A1/zh
Priority to US18/040,427 priority patent/US20240276803A1/en
Publication of WO2023155140A1 publication Critical patent/WO2023155140A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • organic light-emitting diode Organic Light-Emitting Diode, referred to as OLED
  • OLED Organic Light-Emitting Diode
  • a display panel has a display area, a first fan-out area and a bending area sequentially arranged along a first direction.
  • the display panel includes a plurality of fan-out lines disposed in the first fan-out area.
  • the fan-out routing extends from the side of the first fan-out area close to the display area to the side of the first fan-out area near the bending area, and the fan-out routing includes connected Lead-offs and extensions.
  • the lead-out section is closer to the display area than the extension section.
  • the plurality of fan-out routings include a first routing group and a second routing group arranged side by side along a second direction, and the first routing group and the second routing group are arranged asymmetrically. The first direction intersects the second direction.
  • the first wiring group includes a plurality of first wiring bundles arranged side by side along the second direction.
  • the first wiring bundle closest to the second wiring group among the plurality of first wiring bundles includes a first sub-bundle and a second sub-bundle.
  • the second sub-bundle is closer to the second wiring group than the first sub-bundle.
  • the first beamlet and the second beamlet include connected lead-outs and extensions.
  • the lead-out portion is formed by lead-out sections of multiple fan-out routings of the corresponding sub-bundle.
  • the extension part is formed by extension sections of a plurality of fan-out traces of the corresponding sub-bundle.
  • the distance between the extension portion of the first sub-bundle and the extension portion of the second sub-bundle is greater than the distance between two adjacent fan-out traces in any first trace bundle.
  • the second sub-bundle includes a first wiring cluster and a second wiring cluster arranged side by side along the second direction.
  • the second wire cluster is closer to the second wire group than the first wire cluster.
  • the straight-line length of the fan-out routing is the sum of the straight-line distance between the two ends of the lead-out section of the fan-out routing and the straight-line distance between the two ends of the extension section of the fan-out routing.
  • At least one fanout trace of the second trace cluster has a curved portion, and/or at least one fanout trace of the second trace cluster has a widened portion.
  • the line width of the widened part is larger than the line width of other parts in the corresponding fan-out trace except the widened part.
  • the second wiring cluster includes a first sub-cluster and a second sub-cluster arranged side by side along the second direction.
  • the second subcluster is closer to the second wiring group than the first subcluster.
  • the multiple fanout traces of the first subcluster have curved portions, and/or the multiple fanout traces of the second subcluster have widened portions.
  • the straight line lengths of the curve parts of the multiple fanout traces of the first sub-cluster gradually become shorter; and/or, along the second direction and from the first trace group to the second trace group.
  • the linear lengths of the widened portions of the plurality of fan-out traces in the second sub-cluster gradually become longer.
  • At least one fan-out trace of the first trace cluster has a curved portion.
  • the plurality of fan-out traces of the first trace cluster have curved portions. Along the second direction and from the first routing group to the second routing group, the straight line lengths of the curve portions of the plurality of fanout routings in the first routing group gradually become longer.
  • the curved portion is set on an extension of the corresponding fan-out trace; and/or, the line width of the curved portion is approximately the same as the line width of other parts of the corresponding fan-out trace except for the curved portion equal.
  • the widened portion is arranged on an extension section of the corresponding fan-out trace; and/or, the widened portion is arranged in a straight line.
  • the resistances of the multiple fan-out traces of the second sub-bundle are all within the first preset resistance range; and/or, the second sub-bundle is closest to the second trace
  • the resistance difference between the group of fan-out wires and the fan-out wire closest to the second sub-bundle in the second wire group is within the first preset resistance range.
  • the display panel further has a second fan-out area located on a side of the bending area away from the first fan-out area.
  • the display panel further includes a plurality of first connection lines arranged in the second fan-out area, and the first connection lines extend from a side of the second fan-out area close to the bending area to the second
  • the fan-out area is far away from the side of the bending area, and a first connection line is electrically connected to a fan-out line.
  • the plurality of first connection lines connected by the second sub-bundle From the side of the second fan-out area close to the bending area to the side of the second fan-out area away from the bending area, the plurality of first connection lines connected by the second sub-bundle , gradually approaching the plurality of first connecting lines connected to the first sub-bundle.
  • the display panel further includes a second fan-out area located on a side of the bending area away from the first fan-out area.
  • the display panel further includes a plurality of first connection lines disposed at least in the second fan-out area. Each first connection line extends from a side of the second fan-out area close to the bending area to a side of the second fan-out area away from the bending area, and one first connection line and one Fan-out trace electrical connection.
  • the target first wiring bundle farthest from the second wiring group among the plurality of first wiring bundles is the target first wiring bundle, and the linear lengths of the multiple fanout wirings of the target first wiring bundle gradually become shorter;
  • the target first wiring bundle includes a third sub-bundle and a fourth sub-bundle. The third sub-bundle is farther away from the second wiring group than the fourth sub-bundle.
  • the multiple first connecting wires connected to the multiple fan-out routings of the third sub-bundle form a fifth sub-bundle, and each first connecting wire of the fifth sub-bundle
  • the extended length is greater than its straight length.
  • the extension length of the first connection line is the length of the extension path of the first connection line.
  • the linear length of the first connecting line is the linear distance between the two ends of the first connecting line.
  • At least one first connecting line of the fifth sub-bundle has a broken line part, and the broken line part includes a plurality of line segments that extend in different directions and are connected in sequence; and/or, at least one first connecting line of the fifth sub-bundle
  • the connecting line has a curved portion.
  • the fifth sub-bundle includes a first cluster of connecting wires and a second cluster of connecting wires arranged side by side along the second direction, the first cluster of connecting wires is opposite to the second cluster of connecting wires away from the second routing group; the first connecting wire cluster and the multiple first connecting wire clusters of the second connecting wire cluster have a first broken line portion; the multiple first connecting wire clusters of the first connecting wire cluster The line also has said curved portion.
  • the display panel further includes a test circuit disposed on a side of the second fan-out area away from the bending area, and the first folding line part is located in the second direction of the test circuit.
  • the first fold line part includes a first fold line segment, a second fold line segment and a third fold line segment connected in sequence, and the first fold line segment and the third fold line segment are roughly along the first direction Extending, the second broken line segment extends roughly along the second direction; the first broken line segment is farther away from the second routing group than the third broken line segment; the first broken line segment and the corresponding fan
  • the outgoing line is electrically connected, and the third folded line segment is electrically connected to the test circuit; the first folded line portion of the first connecting wire cluster at least partially surrounds the first folded line portion of the second connecting wire cluster.
  • the curved portion of the first connecting line of the first connecting line cluster is arranged on the first broken line segment of the first broken line portion of the corresponding first connecting line.
  • the plurality of first connecting wire clusters and the second connecting wire cluster The straight line length of the first broken line part of the connecting line gradually becomes shorter; the straight line length of the first broken line part is the sum of the straight line distances between the two ends of the line segments of the first broken line part; and/or, along In the second direction and from the first routing group to the second routing group, the straight line lengths of the curved portions of the plurality of first connecting wires in the first connecting wire cluster gradually become shorter.
  • the fifth sub-bundle further includes a third cluster of connecting wires and a fourth cluster of connecting wires arranged side by side along the second direction, the third cluster of connecting wires is opposite to the fourth connecting wire
  • the cluster is far away from the second routing group; and the third connecting wire cluster and the fourth connecting wire cluster are closer to the second routing relative to the first connecting wire cluster and the second connecting wire cluster group; the multiple first connecting lines of the third connecting line cluster and the fourth connecting line cluster have a second fold line portion; the multiple first connecting lines of the third connecting line cluster also have the curved portion .
  • the display panel further includes a test circuit disposed on a side of the second fan-out area away from the bending area, and the second folding line part is located at the test circuit close to the second fan-out area.
  • the second fold line part includes a fourth fold line segment and a fifth fold line segment connected in sequence, the fourth fold line segment generally extends along the first direction, and the fifth fold line segment generally extends along the extending in the second direction;
  • the fourth folded line segment is electrically connected to the corresponding fan-out routing, and the fifth folded line segment is electrically connected to the test circuit;
  • the second folded line part of the third connecting wire cluster at least partially surrounds The second folded line part of the fourth connecting line cluster.
  • the curved portion of the first connecting line of the third connecting line cluster is arranged on the fourth folded line segment of the second folded line portion of the corresponding first connecting line.
  • the plurality of first wire clusters of the third wire cluster and the fourth wire cluster The straight line length of the second broken line part of the connecting line gradually becomes shorter; the straight line length of the second broken line part is the sum of the straight line distances between the two ends of the line segments of the second broken line part; and/or, along In the second direction and from the first routing group to the second routing group, the straight line lengths of the curved portions of the plurality of first connecting wires in the third connecting wire cluster gradually become shorter.
  • the first connecting wire cluster, the second connecting wire cluster, the third connecting wire cluster along the second direction and from the first routing group to the second routing group, gradually become shorter.
  • the multiple first connecting wires connected to the multiple fan-out routings of the fourth sub-bundle form a sixth sub-bundle, and each of the sixth sub-bundle
  • the extension length of the first connecting line is roughly equal to its straight line length.
  • the sum of the extension lengths of the fan-out routing farthest from the second routing group and the first connection wires connected to it is the first length;
  • the sum of the extension lengths of the fan-out routings of the first routing group and the first connecting wires connected thereto is a second length; the first length is approximately equal to the second length.
  • the sum of the resistances of the fan-out wiring farthest from the second wiring group and the first connection lines connected to it is the first resistance;
  • the sum of the resistances of the fan-out wirings of a wiring group and the first connecting lines connected thereto is a second resistance; the first resistance is approximately equal to the second resistance.
  • a plurality of fans of each first wiring bundle in two adjacent first wiring bundles The straight-line length of the outgoing wiring gradually decreases; among the two adjacent first wiring bundles, at least one fan-out wiring of the first wiring bundle that is relatively far away from the second wiring group has a curved portion; and, the first wiring bundle
  • the fan-out traces with the curved portion in a trace bundle are closer to the second trace group than the other fan-out traces in the first trace bundle.
  • the second routing group includes a plurality of second routing bundles arranged side by side along a second direction; along the second direction and from the second routing group to the first routing group, the linear lengths of the multiple fanout traces of each of the two adjacent second trace bundles gradually decrease; in the two adjacent second trace bundles, the distance between the first At least one fan-out trace of the second trace bundle of the trace group has a curved portion; and, the fan-out trace with the curved portion in the second trace bundle is closer to the other fan-out traces in the second trace bundle Describe the first routing group.
  • the display panel has a second fan-out area located on the side of the bending area away from the first fan-out area; the display panel includes at least a plurality of first connecting lines, the first connecting lines extending from a side of the second fan-out area close to the bending area to a side of the second fan-out area away from the bending area; The display panel further includes a plurality of second connection lines arranged in the bending area, and the second connection lines extend from the side of the bending area close to the first fan-out area to the bending area.
  • One side of the area close to the second fan-out area; one of the fan-out routings, one of the second connection lines and one of the first connection lines are electrically connected in sequence.
  • the display panel further includes a substrate, a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer.
  • the first gate conductive layer is disposed on the substrate.
  • the second gate conductive layer is disposed on a side of the first gate conductive layer away from the substrate.
  • the source-drain conductive layer is disposed on a side of the second gate conductive layer away from the substrate.
  • a part of the fan-out lines in the plurality of fan-out lines is arranged in the first gate conductive layer, and another part of the fan-out lines is arranged in the second gate conductive layer; the plurality of first connection lines A part of the first connecting lines is set in the first gate conductive layer, and another part of the first connecting lines is set in the second gate conductive layer; the plurality of second connecting lines are set in the source-drain conductive layer layer.
  • the display area is roughly rectangular, and the two corners of the display area close to the first fan-out area are arc-shaped corners; the two corners are respectively the first corner and the second corner , the first corner and the first routing group are located on one side of the reference line, the second corner and the second routing group are located on the other side of the reference line; the reference line is along The first direction is a straight line passing through the display area; the arc of the first corner is smaller than the arc of the second corner.
  • a display device including a first display panel.
  • the first display panel is the display panel described in any one of the above embodiments.
  • the display device further includes a second display panel and a rotating shaft.
  • the rotating shaft is arranged on the back side of the second display panel, and the second display panel can be folded along the rotating shaft; wherein, the first display panel is arranged on the back side of the second display panel and is located on the One side of the rotating shaft; the light emitting directions of the first display panel and the second display panel are opposite to each other.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • Fig. 2 is a top structural diagram of a display panel according to some embodiments.
  • Fig. 3 is a sectional view of a display panel shown in Fig. 2 along the section line Z-Z';
  • FIG. 4 is a partial structural diagram of a peripheral area B of a display panel according to some embodiments.
  • Fig. 5 is a structural diagram of a display panel according to some embodiments.
  • FIG. 6A is a partial enlarged view of H of the display panel in FIG. 5;
  • FIG. 6B is a cross-sectional view of the display panel shown in FIG. 6A along the section line A1-A2;
  • FIG. 6C is a cross-sectional view of the display panel shown in FIG. 6A along the section line B1-B2;
  • FIG. 6D is a cross-sectional view of the display panel shown in FIG. 6A along the X direction;
  • FIG. 7A is another structural diagram of a display panel according to some embodiments.
  • 7B is a graph showing the number of data lines and the resistance value according to some embodiments.
  • Fig. 8A is another structural diagram of a display panel according to some embodiments.
  • Fig. 8B is another structural diagram of a display panel according to some embodiments.
  • FIG. 8C is another structural diagram of a display panel according to some embodiments.
  • FIG. 8D is another graph of the number of data lines and the resistance value according to some embodiments.
  • FIG. 9A is a partially enlarged view at J of the display panel in FIG. 8C;
  • Fig. 9B is another graph showing the number of data lines and the resistance value according to some embodiments.
  • FIG. 10 is a partially enlarged view at L of the display panel in FIG. 8C;
  • FIG. 11 is a partially enlarged view at M of the display panel in FIG. 8B;
  • FIG. 12 is another partial enlarged view at M of the display panel in FIG. 8B;
  • FIG. 13 is a partially enlarged view of A2 or A3 of the display panel in FIG. 7A;
  • FIG. 14 is a partially enlarged view of A4 or A5 of the display panel in FIG. 7A .
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel As used herein, “parallel”, “perpendicular”, and “equal” include the stated situation and the situation similar to the stated situation, the range of the similar situation is within the range of acceptable deviation, wherein Acceptable ranges of deviation are as determined by one of ordinary skill in the art taking into account the measurement in question and errors associated with measurement of the particular quantity (ie, limitations of the measurement system).
  • “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; Deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, where the difference between the two that may be equal is less than or equal to 5% of either within acceptable tolerances for approximate equality, for example.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • Some embodiments of the present disclosure provide a display panel and a display device 100 .
  • the display device 100 will be introduced below.
  • the display device 100 may be any device that displays images, whether moving (eg, video) or stationary (eg, still images), and whether text or text. More specifically, it is contemplated that embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or Laptop computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.
  • PDAs personal data assistants
  • laptop computers GPS receivers/navigators
  • MP4 video players camcorders
  • game consoles watches
  • watches clocks
  • calculators TV monitors
  • flat panel displays flat panel displays
  • computer monitors computer monitors
  • automotive displays e.g., odometer displays, etc.
  • navigators e.g., navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, architectural structures, packaging and aesthetic structures ( For example, for a display of an image of a piece of jewelry), etc.
  • displays of camera views e.g., displays of rear-view cameras in vehicles
  • electronic photographs e.g., electronic billboards or signage
  • projectors e.g., architectural structures, packaging and aesthetic structures ( For example, for a display of an image of a piece of jewelry), etc.
  • the display device 100 may be a foldable display device or a common display device (which may be called a flat display device).
  • the display device 100 is a foldable display device.
  • the foldable display device includes a first display panel 110 , a second display panel (not shown in FIG. 1 ) and a rotating shaft 120 .
  • the first display panel 110 is disposed on the back side of the second display panel, and is located on one side of the rotating shaft 120 .
  • the light emitting directions of the first display panel 110 and the second display panel are opposite to each other.
  • the structure of the two sides of the first display panel 110 close to and away from the rotating assembly can present an asymmetrical design.
  • Some embodiments of the present disclosure will be schematically described below by taking the display device 100 as an example of a foldable display device.
  • both the above-mentioned first display panel 110 and the second display panel can be organic light emitting diode (Organic Light Emitting Diode, referred to as OLED) display panel, quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) display panel, etc.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the first display panel 110 has a display area A and a peripheral area B located on at least one side of the display area A.
  • FIG. 2 shows a schematic illustration by taking the peripheral area B enclosing the display area A as an example.
  • the first display panel 110 includes a display substrate 1 and an encapsulation layer 2 for encapsulating the display substrate 1 .
  • the encapsulation layer 2 may be an encapsulation film, or an encapsulation substrate.
  • the encapsulation layer 2 includes a first inorganic film 21, an organic film 22 and a second inorganic film 23, so as to prevent water vapor and oxygen in the external environment from entering the first display panel 110 and damaging the light emitting device 11.
  • the lifespan of the first display panel 110 is shortened due to organic materials.
  • the structure of the display area A of the first display panel 110 close to and away from the rotating assembly also presents an asymmetrical design.
  • design take the reference line K as a line of symmetry, the reference line K is a straight line along the first direction Y and passing through the display area A, the structure of the display area A of the first display panel 110 is asymmetrical, and the display area A is roughly rectangular, hexagon, circle or irregular polygon, the embodiments of the present disclosure are not limited thereto).
  • the display area A of the first display panel 110 is approximately rectangular, and the two corners of the display area A close to the first fan-out area 10 are curved corners.
  • the two corners are respectively a first corner C and a second corner D.
  • the arc of the first corner C is smaller than the arc of the second corner D. It should be noted that the center of the circle corresponding to the arc is on the first display panel 110 .
  • the display area A is an area for displaying images, and the display area A is configured to provide sub-pixels P.
  • the above-mentioned first display panel 110 includes a plurality of sub-pixels P disposed on one side of the substrate 115 and located in the display area A.
  • the plurality of sub-pixels P are arranged in multiple rows and columns, each row of sub-pixels P may include multiple sub-pixels P arranged along the second direction X, and each column of sub-pixels P may include multiple sub-pixels P arranged along the first direction Y.
  • first direction Y and the second direction X cross each other.
  • the included angle between the first direction Y and the second direction X can be selected and set according to actual needs.
  • the included angle between the first direction Y and the second direction X may be 85°, 87°, 89°, 90°, 91° or 92° and so on.
  • the first display panel 110 may further include a plurality of data connection lines DL and a plurality of gate connection lines (not shown in FIG. 2 ).
  • the plurality of gate connection lines extend along the second direction X
  • the plurality of data connection lines DL extend along the first direction Y.
  • the sub-pixels P in the same row may be electrically connected to a gate connection line
  • the sub-pixels P in the same column may be electrically connected to a data connection line DL.
  • both the gate connection line and the data connection line DL are electrically connected to the pixel driving circuit of the sub-pixel P.
  • each sub-pixel P includes a light emitting device 11 disposed on a substrate 115 and a pixel driving circuit 12
  • the pixel driving circuit 12 includes a plurality of thin film transistors 121 .
  • the thin film transistor 121 includes an active layer 1211 , a source 1212 , a drain 1213 and a gate 1214 , and the source 1212 and the drain 1213 are respectively in contact with the active layer 1211 .
  • the light-emitting device 11 includes a first electrode layer 111, a light-emitting functional layer 112, and a second electrode layer 113 arranged in sequence, the first electrode layer 111 and the thin-film transistor as a driving transistor among the plurality of thin-film transistors 121
  • the source 1212 or the drain 1213 of is electrically connected.
  • FIG. 3 the electrical connection between the first electrode layer 111 and the source 1212 of the thin film transistor 121 is schematically illustrated.
  • source 1212 and the drain 1213 can be interchanged, that is, 1212 in FIG. 3 represents the drain, and 1213 in FIG. 3 represents the source.
  • the above-mentioned light-emitting functional layer 112 only includes a light-emitting layer.
  • the luminescent functional layer 112 includes, in addition to the luminescent layer, an electron transport layer (election transporting layer, ETL for short), an electron injection layer (election injection layer, EIL for short), a hole transport layer (hole transporting layer). , HTL for short) and at least one of a hole injection layer (HIL for short).
  • the display substrate 1 further includes a pixel defining layer PDL, the pixel defining layer PDL includes a plurality of opening regions, and one light emitting device 11 is disposed in one opening region.
  • the display substrate 1 further includes a spacer PS disposed between the pixel defining layer PDL and the light emitting layer functional layer 112 .
  • the display substrate 1 further includes a semiconductor layer ACT, a first gate insulating layer GI1 , a first gate conductive layer GATE1 , a second gate insulating layer GI2 , a second gate conductive layer GATE2 , a layer The inter-insulating layer ILD, the first source-drain conductive layer SD1, the first planar layer PLN1, the second source-drain conductive layer SD2, and the second planar layer PLN2.
  • the semiconductor layer ACT, the first gate insulating layer GI1, the first gate conductive layer GATE1, the second gate insulating layer GI2, the second gate conductive layer GATE2, the interlayer insulating layer ILD, the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 are sequentially stacked between the substrate 115 and the first electrode layer 111 .
  • the material of the semiconductor layer ACT includes amorphous silicon, single crystal silicon, polycrystalline silicon, or metal oxide semiconductor material.
  • the material of the semiconductor layer ACT includes Indium Gallium Zinc Oxide (IGZO) and Zinc Oxide (ZnO), and the embodiments of the present disclosure are not limited thereto.
  • the semiconductor layer includes an active layer 1211 of each thin film transistor 121 .
  • the overlapping portions of the first gate conductive layer GATE1 and the semiconductor layer ACT form thin film transistors 121 respectively.
  • the material of the first gate conductive layer GATE1 includes conductive metal.
  • the material of the first gate conductive layer GATE1 includes at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.
  • the first gate conductive layer GATE1 includes the gate 1214 of each thin film transistor 121 and the first plate of the capacitor CST.
  • the first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate conductive layer GATE1 for electrically insulating the semiconductor layer ACT from the first gate conductive layer GATE1 .
  • the material of the first gate insulating layer GI1 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the first gate insulating layer GI1 includes silicon dioxide, and the embodiment of the present disclosure Not limited to this.
  • the overlapping portion of the second gate conductive layer GATE2 and the first gate conductive layer GATE1 forms a capacitor CST.
  • the material of the second gate conductive layer GATE2 includes conductive metal.
  • the material of the second gate conductive layer GATE2 includes at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.
  • the second gate conductive layer GATE2 includes a second plate of the capacitor CST.
  • the second gate insulating layer GI2 is disposed between the first gate conductive layer GATE1 and the second gate conductive layer GATE2 for electrically insulating the first gate conductive layer GATE1 from the second gate conductive layer GATE2 .
  • the material of the second gate insulating layer GI2 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.
  • the material of the second gate insulating layer GI2 includes silicon dioxide, to which embodiments of the present disclosure are not limited.
  • the interlayer dielectric layer ILD is disposed between the first source-drain conductive layer SD1 and the second gate conductive layer GATE2 for electrically insulating the first source-drain conductive layer SD1 from the second gate conductive layer GATE2 .
  • the material of the interlayer dielectric layer ILD includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the second gate insulating layer GI2 includes silicon dioxide, and the embodiment of the present disclosure does not limited to this.
  • the first source-drain conductive layer SD1 is disposed between the interlayer dielectric layer ILD and the first planar layer PLN1.
  • the first source-drain conductive layer SD1 includes conductive metal.
  • the material of the first source-drain conductive layer SD1 includes at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.
  • the first source-drain conductive layer SD1 includes a source 1212 and a drain 1213 of the TFT 121 .
  • the first flat layer PLN1 is disposed between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 for electrically insulating the first source-drain conductive layer SD1 from the second source-drain conductive layer SD2.
  • the material of the first planar layer PLN1 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.
  • the material of the first planarization layer PLN1 includes silicon dioxide, to which embodiments of the present disclosure are not limited.
  • the second source-drain conductive layer SD2 is disposed between the first planar layer PLN1 and the second planar layer PLN2 .
  • the second source-drain conductive layer SD2 includes conductive metal.
  • the material of the second source-drain conductive layer SD2 includes at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.
  • the second source-drain conductive layer SD2 includes at least one of the connection electrode 150 , the initialization signal line 151 and the auxiliary signal line, to which embodiments of the present disclosure are not limited.
  • the second flat layer PLN2 is disposed between the second source-drain conductive layer SD2 and the first electrode layer 111 for electrically insulating the second source-drain conductive layer SD2 from the first electrode layer 111 .
  • the material of the second planar layer PLN2 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.
  • the material of the second planarization layer PLN2 includes silicon dioxide, to which embodiments of the present disclosure are not limited.
  • the peripheral area B is a non-displayed area, and the peripheral area B can be configured to arrange scan driving circuits, circuit traces, binding pins, and the like.
  • the peripheral area B has a first fan-out area 10 , a bending area 20 , a second fan-out area 30 , and an electrostatic protection area 40 sequentially arranged along the first direction Y. , a test area 50 , a third fan-out area 60 and a bonding area 70 .
  • the first fan-out area 10 is provided with a plurality of fan-out lines 101, and each fan-out line 101 extends from the side of the first fan-out area 10 close to the display area A to the first fan-out area 10.
  • the side of the zone 10 is close to the bending zone 20 .
  • the fan-out wiring 101 includes a connected lead-out segment 102 and an extension segment 103 , and the lead-out segment 102 is closer to the display area A than the extension segment 103 .
  • the plurality of fan-out traces 101 include a first trace group 1010 and a second trace group 1020 arranged side by side along the second direction X.
  • the first routing group 1010 and the second routing group 1020 are located on opposite sides of the reference line K.
  • the plurality of fan-out wires 101 may be located on the first gate conductive layer GATE1 and/or the second gate conductive layer GATE2 .
  • a part of the fan-out lines 101 among the plurality of fan-out lines 101 is arranged in the first gate conductive layer GATE1, and another part of the fan-out lines 101 is arranged in the second gate conductive layer GATE2, located in
  • the orthographic projection of the fan-out wiring 101 of the first gate conductive layer GATE1 on the substrate 115 and the orthographic projection of the fan-out wiring 101 of the second gate conductive layer GATE2 on the substrate 115 are at least partially staggered and arranged in a staggered manner, In order to reduce the parasitic capacitance of the fan-out wiring 101 located in the first gate conductive layer GATE1 and the fan-out wiring 101 located in the second gate conductive layer GATE2 .
  • the bending area 20 is provided with a plurality of second connection lines 21 , and each second connection line 21 extends from the side of the bending area 20 close to the first fan-out area 10 to the A side of the bending area 20 close to the second fan-out area 30 ; a fan-out line 101 is electrically connected to a second connection line 21 .
  • a plurality of second connection lines 21 may be located in the second source-drain conductive layer SD2 , reducing the number of metal layers required for the bending region 20 , and making the bending region 20 more flexible.
  • the fan-out wiring 101 located in the second gate conductive layer GATE2 is electrically connected to the second connecting line 21, and can be electrically connected to the second connecting line 21 through the transfer block located in the first source-drain conductive layer SD1. connect.
  • the fan-out line 101 located in the first gate conductive layer GATE1 is electrically connected to the second connection line 21 through the transfer block located in the second gate conductive layer GATE2 and the first source-drain conductive layer SD1.
  • the connecting block is electrically connected to the second connection line 21.
  • the second fan-out area 30 is provided with a plurality of first connection lines 31, and each first connection line 31 extends from the side of the second fan-out area 30 close to the bending area 20 to the second fan-out area 30.
  • the area 30 is away from the side of the bending area 20 , and a first connection line 31 is electrically connected to a fan-out line 101 , and a fan-out line 101 , a second connection line 21 and a first connection line 31 are electrically connected in sequence.
  • the first connection line 31 may be located on the first gate conductive layer GATE1 and/or the second gate conductive layer GATE2.
  • a part of the first connecting lines 31 among the plurality of first connecting lines 31 is arranged in the first gate conductive layer GATE1, and another part of the first connecting lines 31 is arranged in the second gate
  • the orthographic projection of the first connection line 31 located in the first gate conductive layer GATE1 on the substrate 115 is staggered from the orthographic projection of the first connection line 31 located in the second gate conductive layer GATE2 on the substrate 115 set and staggered.
  • the first connection line 31 located in the second gate conductive layer GATE2 is electrically connected to the second connection line 21, and can be connected to the second connection line 21 through the transfer block located in the first source-drain conductive layer SD1. Electrical connection, so as to realize the electrical connection of one fan-out line 101, one second connecting line 21 and one first connecting line 31 in sequence.
  • the first connection line 31 located in the first gate conductive layer GATE1 is electrically connected to the second connection line 21, which can pass through the transfer block located in the second gate conductive layer GATE2 and the first source-drain conductive layer.
  • the transition block of SD1 is electrically connected to the second connection line 21 , so as to realize the electrical connection of one fan-out line 101 , one second connection line 21 and one first connection line 31 in sequence.
  • the electrostatic protection area 40 is provided with an electrostatic discharge circuit.
  • the static discharge circuit is used to dissipate the static electricity generated inside the first display panel 110 to avoid static electricity breakdown.
  • the test area 50 is provided with a test circuit 51 , and the test circuit 51 is electrically connected to the first connection line 31 .
  • the test circuit 51 may be disposed on the second source-drain conductive layer SD2.
  • the test circuit 51 located in the second source-drain conductive layer SD2 is electrically connected to the first connection line 31, and can be electrically connected to the first connection line 31 through a transfer block located in the first source-drain conductive layer SD1. connect.
  • the test circuit 51 located in the second source-drain conductive layer SD2 is electrically connected to the first connection line 31, and can pass through the transfer block located in the first source-drain conductive layer SD1 and the first gate conductive layer GATE1. It is electrically connected to the first connection line 31 .
  • the third fan-out area 60 is provided with a plurality of third connection lines 61, and each third connection line 61 extends from the side of the third fan-out area 60 close to the test area 50 to the third fan-out area. 60 away from the side of the test area 50 , a plurality of third connection lines 61 are electrically connected to the test circuit 51 , and are in one-to-one correspondence with the plurality of first connection lines 31 .
  • the plurality of third connection lines 61 may be located in the first gate conductive layer GATE1 and/or the second gate conductive layer GATE2 .
  • a part of the third connecting lines 61 among the plurality of third connecting lines 61 is arranged in the first gate conductive layer GATE1, and another part of the third connecting lines 61 is arranged in the second gate In the conductive layer GATE2, the orthographic projection of the third connection line 61 located in the first gate conductive layer GATE1 on the substrate 115 is staggered from the orthographic projection of the third connection line 61 located in the second gate conductive layer GATE2 on the substrate 115 set and staggered.
  • the third connection line 61 located on the second gate conductive layer GATE2 is electrically connected to the test circuit 51 , and may be electrically connected to the test circuit 51 through a transfer block located on the first source-drain conductive layer SD1 .
  • the third connection line 61 located in the first gate conductive layer GATE1 is electrically connected to the test circuit 51, and can pass through the transfer block located in the second gate conductive layer GATE2 and the connection line located in the first source-drain conductive layer SD1.
  • the transition block is electrically connected to the test circuit 51 .
  • the binding area 70 is configured to bind a flexible circuit board.
  • the binding area 70 is provided with a plurality of binding pins 71 , one binding pin 71 is electrically connected to a third connection line 61 , or a plurality of binding pins 71 is electrically connected to a third connection line 61 .
  • the binding pin 71 may be located in the second source-drain conductive layer SD2.
  • the third connection line 61 located in the second gate conductive layer GATE2 is electrically connected to the binding pin 71, and can be electrically connected to the binding pin 71 through the transfer block located in the first source-drain conductive layer SD1.
  • the third connecting line 61 located in the first gate conductive layer GATE1 is electrically connected to the binding pin 71, and can pass through the transfer block located in the second gate conductive layer GATE2 and the first source-drain conductive layer.
  • the transition block of SD1 is electrically connected to the binding pin 71 .
  • the binding pin 71 can be located in multiple layers of metal for reducing resistance.
  • the multi-layer metal may include at least two layers of the first conductive source-drain layer SD1 , the second conductive source-drain layer SD2 , the first conductive gate layer GATE1 and the second conductive gate layer GATE2 .
  • the fan-out wires 101 of the first wire group 1010 located in the first fan-out area 10 are relatively different in length and resistance from the fan-out wires 101 of the second wire group 1020 , thus causing transmission to
  • the voltage of the pixel driving circuit 12 varies greatly, resulting in a large difference in the driving current received by the light emitting device 11 , causing the first display panel 110 to produce a problem of uneven display brightness.
  • the length differences of the fan-out traces 101 in areas A1, A2, A3, A4, and A5 are relatively large, so that the resistance values of two fan-out traces 101 in the same area are relatively different.
  • Figure 7B corresponding to the mutation of the resistance values in the regions A1, A2, A3, A4 and A5 in Figure 7A, it can be seen from Figure 7B that the mutation of the resistance values in the regions A1, A2, A3, A4 and A5 is relatively large .
  • some embodiments of the present disclosure provide a display panel, which may be the first display panel 110 described in any of the above-mentioned embodiments. It should be noted that the appearance of the first display panel 110 may be symmetrical or asymmetrical.
  • the first wiring group 1010 includes a plurality of first wiring bundles 1011 arranged side by side along the second direction X.
  • the first The wiring group 1010 includes a plurality of first wiring bundles 1011 , and a group of power signal lines is arranged between two adjacent first wiring bundles 1011 .
  • the embodiment of the present disclosure does not specifically limit the number of the first wiring bundles 1011, which may be set according to actual conditions.
  • the first wire bundle 1011 closest to the second wire group 1020 among the plurality of first wire bundles 1011 includes a first sub-bundle 1012 and a second sub-bundle 1013 .
  • the second sub-bundle 1013 is closer to the second wiring group 1020 than the first sub-bundle 1012 .
  • both the first sub-beam 1012 and the second sub-beam 1013 include a lead-out part 104 and an extension part 105 connected.
  • the lead-out part 104 is formed by the lead-out segments 102 of the plurality of fan-out traces 101 of the corresponding sub-bundle
  • the extension part 105 is formed of the extension segments 103 of the plurality of fan-out traces 101 of the corresponding sub-bundle.
  • the distance D1 between the extension portion 105 of the first sub-bundle 1012 and the extension portion 105 of the second sub-bundle 1013 is greater than two adjacent fan-out paths in any first wiring bundle 1011.
  • the spacing D2 of the lines 101 is greater than two adjacent fan-out paths in any first wiring bundle 1011.
  • the first wiring bundle 1011 closest to the second wiring group 1020 in the first wiring group 1010 is split into the first sub-bundle 1012 and the second sub-bundle 1013, so that The second sub-bundle 1013 is closer to the reference line K, thereby reducing the length of the lead-out section 102 of the second sub-bundle 1013, so that the fan-out wiring 101 of the second sub-bundle 1013 close to the second wiring group 1020 in the first wiring bundle 1011
  • the length is reduced, thereby reducing the fan-out traces 101 of the second sub-bundle 1013 close to the second trace group 1020 in the first trace bundle 1011, and the fan-out traces 101 of the second trace group 1020 close to the first trace group 1010
  • the length difference between the lines 101 that is, to reduce the fan-out traces 101 of the second sub-bundle 1013 close to the second trace group 1020 in the first trace bundle 1011, and the second trace group 1020
  • the resistance curve of the A1 region in FIG. 8D is smoother than the resistance curve of the A1 region in FIG. 7B , and the sudden change of the resistance value is alleviated, so that the fan-out wiring at A1 in FIG. 7A
  • the resistance of 101 is compensated to reduce the large difference in the resistance value of the fan-out line 101 in the area A1 in FIG. 7A .
  • the data lines (including the data connection line DL and the fan-out line Line 101) has an abrupt decrease in resistance, as shown in the A1 region in Figure 8D.
  • the magnitude of the driving current received by the light-emitting device 11 is only related to the constant voltage terminal VDD and the data signal V data , the difference between the data signal V data received by the pixel driving circuit 12 is reduced.
  • the difference of the driving current received by the light emitting device 11 will also be reduced accordingly, so as to improve the problem of non-uniform display brightness of the display panel 110 .
  • the second sub-bundle 1013 includes a first wiring cluster 1014 and a second wiring cluster 1015 arranged side by side along the second direction X, and the second wiring cluster 1015 is opposite to the first The trace cluster 1014 is adjacent to the second trace group 1020 .
  • the linear lengths of the plurality of fan-out routings 101 in the second routing cluster 1015 gradually become longer.
  • the linear lengths of the multiple fan-out traces 101 of the first trace cluster 1014 gradually become shorter.
  • the linear length of the fan-out routing 101 is the sum of the linear distance between the two ends of the lead-out segment 102 of the fan-out routing 101 and the linear distance between the two ends of the extension segment 103 of the fan-out routing 101 .
  • At least one fan-out trace 101 of the first trace cluster 1014 has a curved portion E.
  • the fan-out traces 101 of the first trace cluster 1014 can reduce the difference in trace length between the fan-out traces 101 by setting the curve part E, thereby reducing the fan-out traces 101 of the first trace cluster 1014 corresponding to the difference in resistance between the data lines.
  • the plurality of fan-out traces 101 of the first trace cluster 1014 have a curved portion E.
  • the straight line lengths of the curve portions E of the plurality of fanout wires 101 in the first wire cluster 1014 gradually become longer.
  • the multiple fan-out traces 101 of the first trace cluster 1014 can compensate the difference in the straight-line length of the fan-out traces 101 through the linear length of the curve part E, thereby reducing the number of multiple fan-out traces 101 of the first trace cluster 1014.
  • the difference in resistance between the data lines corresponding to the fan-out lines 101 is the straight line length of the curve part E is the trace length.
  • At least one fanout trace 101 of the second trace cluster 1015 has a curve portion E, so that the fanout trace 101 of the second trace cluster 1015 can be realized by setting the curve portion E The difference in the length of the fan-out wires 101 is reduced, thereby reducing the difference in resistance between the data lines corresponding to the fan-out wires 101 of the second wire cluster 1015 .
  • the second wire cluster 1015 includes a first sub-cluster 1016 and a second sub-cluster 1017 arranged side by side along the second direction X, and the second sub-cluster 1017 is closer to the second wire group 1020 than the first sub-cluster 1016 ;
  • the multiple fan-out traces 101 of the first sub-cluster 1016 have a curved portion E.
  • the straight line lengths of the curve portions E of the plurality of fan-out routings 101 in the first sub-cluster 1016 gradually become shorter.
  • the multiple fan-out traces 101 of the first sub-cluster 1016 can compensate the difference in the straight-line length of the fan-out traces 101 through the straight-line length of the curve part E, thereby reducing the multiple fan-out traces of the first sub-cluster 1016.
  • the difference in resistance between the data lines corresponding to the line 101 is the straight line distance between the two ends of the curved portion E.
  • the above-mentioned curved portion E can be set at the lead-out section 102 of the corresponding fan-out trace 101 , or can be set at the extension section 103 .
  • the above-mentioned curve portion E is set at the extension section 103 of the corresponding fan-out trace 101 .
  • the line width of the curved portion E (the direction of the line width is along the second direction X) may be approximately equal to the line width of other portions of the corresponding fan-out trace 101 except for the curved portion E.
  • the line width of the curve part E may also be different from the line width of other parts of the corresponding fan-out wiring 101 except the curve part E, which may be performed in order to balance the resistance between the data lines corresponding to each fan-out wiring 101. adjustment, which is not specifically limited in the present disclosure.
  • At least one fanout trace 101 of the second trace cluster 1015 has a widened portion F, and the width of the widened portion F is greater than that of the corresponding fanout trace 101 except for the widened portion F. Other than the line width of other parts.
  • the fan-out wires 101 of the second wire cluster 1015 can reduce the resistance difference caused by the difference in wire length between the fan-out wires 101 by setting the widened part F, thereby reducing the second wire cluster 1015 The difference in resistance between the data lines corresponding to each fan-out line 101 .
  • the second wire cluster 1015 includes a first sub-cluster 1016 and a second sub-cluster 1017 arranged side by side along the second direction X, and the second sub-cluster 1017 is closer to the second wire group 1020 than the first sub-cluster 1016 .
  • the plurality of fan-out traces 101 of the second sub-cluster 1017 have widened portions F. Referring to FIG.
  • the linear length of the widened portion F of the multiple fan-out routings 101 of the second sub-cluster 1017 gradually becomes longer.
  • the plurality of fan-out wires 101 of the second sub-cluster 1017 can compensate for the increase in resistance caused by the extension of the linear length of the fan-out wires 101 by widening the portion F to reduce the resistance, thereby reducing Differences in resistance between data lines corresponding to the plurality of fan-out lines 101 of the small first sub-cluster 1016 .
  • the linear length of the widened portion F is the linear distance between the two ends of the widened portion F. As shown in FIG.
  • the above-mentioned widened part F can be arranged on the lead-out section 102 of the corresponding fan-out trace 101 , or can be arranged on the extension section 103 .
  • the above widened portion F is disposed on the extension section 103 of the corresponding fan-out trace 101 .
  • the widened portion F may be arranged in a straight line.
  • the widened portion F can also be arranged in a curved line, and can be adjusted to balance the resistance between the data lines corresponding to each fan-out line 101 , which is not specifically limited in the present disclosure.
  • the resistances of the plurality of fan-out traces 101 of the second sub-bundle 1013 are all within the first preset resistance range;
  • the resistance difference between the fan-out wire 101 and the fan-out wire 101 closest to the second sub-bundle 1013 in the second wire group 1020 is within the first preset resistance range.
  • the resistances of the plurality of fan-out wires 101 of the second sub-bundle 1013 are all within the first preset resistance range.
  • the resistance of the multiple fan-out traces 101 of the second sub-bundle 1013 refers to the resistance of the multiple fan-out traces 101 of the second sub-bundle 1013 corresponding to the data line DL.
  • the first preset resistance value range refers to the resistance range of the plurality of fan-out traces 101 of the second sub-bundle 1013 corresponding to the data line DL.
  • the first preset resistance range is 1050 ⁇ ⁇ 1200 ⁇ .
  • the resistances of the data lines (area A1 ) corresponding to the fan-out lines 101 of the plurality of fan-out lines 101 of the second sub-bundle 1013 are all within 1050 ⁇ ⁇ 1200 ⁇ .
  • the resistance difference between the fan-out trace 101 closest to the second trace group 1020 in the second sub-bundle 1013 and the fan-out trace 101 in the second trace group 1020 closest to the second sub-bundle 1013 is at within a preset resistance range.
  • the resistance difference of the multiple fan-out traces 101 of the second sub-bundle 1013 refers to the resistance difference of the multiple fan-out traces 101 of the second sub-bundle 1013 corresponding to the data line DL.
  • the first preset resistance value range refers to the range of the resistance difference between the multiple fan-out traces 101 of the second sub-bundle 1013 corresponding to the data line DL.
  • the first preset resistance range is 300 ⁇ ⁇ 500 ⁇ .
  • the resistance difference between the fan-out trace 101 closest to the second trace group 1020 in the second sub-bundle 1013 and the fan-out trace 101 closest to the second sub-bundle 1013 in the second trace group 1020 is Within 300 ⁇ 500 ⁇ .
  • the fan-out traces 101 in the A1 area can compensate for the rise through the curved portion E and/or the widened portion F. Increase or decrease the difference in resistance caused by the difference in the length of the fan-out lines 101, so as to reduce the difference in resistance between the data lines corresponding to the multiple fan-out lines 101.
  • the final result is shown in FIG. 9B.
  • the resistance mutation trend in the A1 area is improved, the resistance value is compensated, and the difference in resistance gradually decreases.
  • the multiple first connecting lines 31 connected to the first sub-bundle 1012 are connected to the multiple first connecting lines 31 connected to the second sub-bundle 1013. There is a distance D3 between them.
  • the plurality of first connection lines 31 connected by the second sub-bundle 1013 gradually move toward the second fan-out area 30.
  • a plurality of first connection lines 31 connected by a sub-bundle 1012 are close together to reduce the area occupied by the first connection lines 31 .
  • the first wiring bundle 1011 is the target first wiring bundle 1100 , and the linear lengths of the plurality of fan-out wirings 101 of the target first wiring bundle 1100 gradually become shorter.
  • the target first wiring bundle 1100 includes a third sub-bundle 1101 and a fourth sub-bundle 1102 , and the third sub-bundle 1101 is farther away from the second wiring group 1020 than the fourth sub-bundle 1102 .
  • the extended length of the wire 31 is greater than its straight length.
  • the extension length of the first connection line 31 is the length of the extension path of the first connection line 31
  • the linear length of the first connection line 31 is the linear distance between two ends of the first connection line 31 .
  • At least one first connection line 31 of the fifth sub-bundle 1103 has a broken line portion 310 , and the broken line portion 310 includes a plurality of line segments extending in different directions and connected in sequence. And/or, as shown in FIG. 12 , at least one first connection line 31 of the fifth sub-bundle 1103 has a curved portion E.
  • the line lengths of the multiple fan-out lines 101 of the third sub-bundle 1101 can be compensated for by the broken line portion 310 and/or the curve portion E of the first connection line 31 in the fifth sub-bundle 1103, which is different from that of the second
  • the routing group 1020 is far away from the difference in the routing length of the fan-out routing 101 of the part of the first routing group 1010, that is, to compensate for the data lines corresponding to the multiple fan-out routings 101 of the third sub-bundle 1101, and the second routing group 1101.
  • the portion of the group 1020 away from the first wiring group 1010 fans out the difference in resistance between the data lines corresponding to the wiring 101 , so as to improve the problem of non-uniform display brightness of the display panel 110 .
  • the 1st to 150th data lines in FIG. 8D are the data lines corresponding to the plurality of first connection lines 31 of the fifth sub-bundle 1103, and the broken line part 310 and/or curve part E of the first connection line 31 can make the data lines
  • the resistance value of the 1st to 150th data line increases, reducing the resistance difference between the 1st to 150th data line and the 1951st to 2101st data line, so that the resistance of the 1st to 150th data line is approximately equal to that of the 1951st to 2101st data line.
  • the length of the broken line part 310 and/or the curve part E of the first connection line 31 in the fifth sub-bundle 1103 can also be used to reduce the number of fan-out traces 101 corresponding to the third sub-bundle 1101. The difference in the resistance of the data lines.
  • the fifth sub-bundle 1103 includes a first cluster of connecting wires 1104 and a second cluster of connecting wires 1105 arranged side by side along the second direction X, and the first cluster of connecting wires 1104 is farther away from the second cluster of connecting wires 1105 than the second cluster.
  • Line set 1020 the multiple first connecting lines 31 of the first connecting line cluster 1104 and the second connecting line cluster 1105 have a first fold line portion 3100 , and the multiple first connecting lines 31 of the first connecting line cluster 1104 also have a curved portion E.
  • the straight line length of the broken line portion 3100 gradually becomes shorter.
  • the straight line length of the first broken line portion 3100 is the sum of the straight line distances between the two ends of the line segments of the first broken line portion 3100 .
  • the straight line lengths of the curve portions E of the plurality of first connecting wires 31 in the first connecting wire cluster 1104 gradually become shorter.
  • the curve part E of the plurality of first connection lines 31 of the first connection line cluster 1104 is used to compensate the resistance values of the first to fifty data lines, so that the resistance values of the first to fifty data lines The resistance value rises, so as to reduce the resistance difference between the two sides of the first fan-out area 10 , and at the same time reduce the sudden change in the resistance value between the 1st to 50th data lines with relatively large differences.
  • the first broken line portion 3100 of the plurality of first connecting wires 31 of the second connecting wire cluster 1105 is used to compensate the resistance value of the 50th to 100th data lines and reduce the difference in resistance value.
  • the fifth sub-bundle 1103 further includes a third cluster of connecting wires 1106 and a fourth cluster of connecting wires 1107 arranged side by side along the second direction X, and the third cluster of connecting wires 1106 is opposite to the fourth cluster of connecting wires.
  • the wire cluster 1107 is away from the second wiring group 1020 , and the third connecting wire cluster 1106 and the fourth connecting wire cluster 1107 are closer to the second wiring group 1020 than the first connecting wire cluster 1104 and the second connecting wire cluster 1105 .
  • the multiple first connecting lines 31 of the third connecting line cluster 1106 and the fourth connecting line cluster 1107 have the second folded line portion 3200 , and the multiple first connecting lines 31 of the third connecting line cluster 1106 also have the curved portion E.
  • the straight line length of the broken line portion 3200 gradually becomes shorter.
  • the straight line length of the second broken line portion 3200 is the sum of the straight line distances between the two end points of each line segment of the second broken line portion 3200 .
  • the straight line lengths of the curved portions E of the plurality of first connecting wires 31 in the third connecting wire cluster 1106 gradually become shorter.
  • the curve part E of the plurality of first connecting wires 31 of the third connecting wire cluster 1106 is used to compensate the 101st to 150th data lines, so that the resistance value of the 101st to 150th data lines increases , and approximately equal to the resistance of the 1951st to 2000th data lines.
  • the resistance value difference between the 100th data line and the 101st data line is relatively large, so the resistance value of the 101st data line increases, thereby reducing the difference between the resistance value of the 100th data line and the 100th data line.
  • the lengths and resistances of the data lines respectively located on both sides of the reference line of the display panel are approximately equal, and the pixel driving circuit 12 receives the The voltages are also substantially equal, and the display brightness of the display panel 110 is more uniform.
  • the first connecting wire cluster 1104, the second connecting wire cluster 1105, the third connecting wire cluster 1106 and the fourth connecting wire cluster 1106 gradually become shorter.
  • the first fold line portion 3100 is located on one side of the test circuit 51 in the second direction X.
  • the first folded line part 3100 includes a first folded line segment 3101, a second folded line segment 3102 and a third folded line segment 3103 which are sequentially connected. 3102 generally extends along the second direction X.
  • the first folded line segment 3101 , the second folded line segment 3102 and the third folded line segment 3103 are connected to form a U shape.
  • the first folded line segment 3101 is connected to the corresponding fan-out trace 101
  • the third folded line segment 3103 is connected to the test circuit 51
  • the first folded line segment 3101 is farther away from the second trace group 1020 than the third folded line segment 3103 .
  • the first folded line portion 3100 of the first connecting wire cluster 1104 surrounds the first folded line portion 3100 of the second connecting wire cluster 1105 , so as to prevent the traces of the first connecting wire cluster 1104 from intersecting with the traces of the second connecting wire cluster 1105 .
  • the curved portion E of the first connecting line 31 of the above-mentioned first connecting line cluster 1104 is set on the first broken line segment 3101 of the first broken line portion 3100 of the corresponding first connecting line 31 .
  • the curved portion E of the first connection line 31 of the first connection line cluster 1104 may also be set on the second folded line segment 3102 and/or the third folded line segment 3103 , which is not specifically limited in this embodiment of the present disclosure.
  • the above-mentioned second fold line portion 3200 is located on a side of the test circuit 51 close to the second fan-out area 30 .
  • the second folded line portion 3200 includes a fourth folded line segment 3201 and a fifth folded line segment 3202 connected in sequence, the fourth folded line segment 3201 extends approximately along the first direction Y, and the fifth folded line segment 3202 approximately extends along the second direction X.
  • the fourth folded line segment 3201 and the fifth folded line segment 3202 may be perpendicular to each other and form an L shape.
  • the fourth broken line segment 3201 is connected to the corresponding fan-out routing 101
  • the fifth broken line segment 3202 is connected to the test circuit 51 .
  • the second fold line portion 3200 of the third connection line cluster 1106 surrounds the second fold line portion 3200 of the fourth connection line cluster 1107 .
  • the curved portion E of the first connecting line 31 of the third connecting line group 1106 is set to the fourth folding line segment 3201 of the second folding line portion 3200 of the corresponding first connecting line 31 .
  • the curved portion E of the first connecting line 31 of the third connecting line cluster 1106 may also be set on the fifth folded line segment 3202 , which is not specifically limited in this embodiment of the present disclosure.
  • each first connection line 31 of the six sub-bundles 1108 is approximately equal to its straight line length.
  • the sum of the extension lengths of the fan-out traces 101 farthest from the second trace group 1020 in the first trace group 1010 and the first connecting wires 31 connected thereto is the first length.
  • the sum of the extension lengths of the fan-out traces 101 farthest from the first trace group 1010 in the second trace group 1020 and the first connecting wires 31 connected thereto is the second length.
  • the sum of the resistances of the fan-out wires 101 farthest from the second wire group 1020 and the first connection wires 31 connected thereto is the first resistance.
  • the sum of the resistances of the fan-out wires 101 farthest from the first wire group 1010 in the second wire group 1020 and the resistances of the first connection wires 31 connected thereto is the second resistance.
  • the first length is approximately equal to the second length. That is, the first resistance is approximately equal to the second resistance.
  • the lengths of the data lines located on both sides of the reference line K of the first display panel 110 are approximately equal in length, their resistances are also approximately equal, the voltages received by the pixel driving circuit 12 are also approximately equal, and the display brightness of the display panel 110 is higher. Uniform.
  • each first wiring bundle in the two adjacent first wiring bundles 1011 gradually decrease.
  • At least one fan-out wiring 101 of the first wiring bundle 1011 that is relatively far away from the second wiring group 1020 has a curved portion E , and the fan-out traces 101 with the curved portion E in the first trace bundle 1011 are closer to the second trace group 1020 than other fan-out traces 101 in the first trace bundle 1011 .
  • the difference in the length of the fan-out wires 101 is reduced through the curve part E, thereby reducing the difference in resistance between the data lines corresponding to the fan-out wires 101 of the first wire bundle 1011, corresponding to 7B, the sudden change of the resistance value in the regions A2 and A3 is improved.
  • the resistance values in the regions A2 and A3 are as shown in FIG. 9B , the resistance value curve is smoother, and the sudden change is reduced.
  • the specific shape of the above-mentioned curved portion E may be wave shape, zigzag shape and the like.
  • the length of the fan-out trace 101 of the curved portion E can be made longer.
  • the second wiring group 1020 includes a plurality of second wiring bundles 1021 arranged side by side along the second direction X. Wherein, as shown in FIG. 7A and FIG. 14 , along the second direction X and from the second wiring group 1020 to the first wiring group 1010, each second wiring bundle 1021 in two adjacent second wiring bundles 1021 The linear lengths of the plurality of fan-out traces 101 gradually decrease.
  • At least one fan-out wiring 101 of the second wiring bundle 1021 relatively far away from the first wiring group 1010 has a curved portion E, and the second wiring bundle 1021
  • the fan-out trace 101 with the curve portion E is closer to the first trace group 1010 than the other fan-out traces 101 in the second trace bundle 1021 .
  • the specific shape of the above-mentioned curved portion E may be wave shape, zigzag shape and the like.
  • the length of the fan-out trace 101 of the curved portion E can be made longer.
  • the difference in the length of the fan-out wires 101 is reduced through the curve part E, thereby reducing the difference in resistance between the data lines corresponding to the fan-out wires 101 of the second wire bundle 1011, corresponding to 7B, the sudden change of the resistance value in the A4 and A5 areas is improved.
  • the resistance values of the A4 and A5 areas are shown in FIG. 9B , the resistance value curve is smoother, and the sudden change is reduced.
  • the difference in the wire length between the fan-out wires 101 is compensated by the curve part E, the widened part F and the broken line part 310, so that the resistance between the data lines corresponding to each fan-out wire 101
  • the difference is reduced, the suddenness of the resistance value is reduced, and the curve of the number of data lines and the resistance value is smoother. In this case, the sudden change of the resistance of the data line is reduced.
  • due to the driving current The magnitude of is only related to the constant voltage terminal VDD and the data signal V data , therefore, when the difference of the data signal V data received by the pixel driving circuit 12 decreases, the difference of the driving current received by the light-emitting device 11 will also increase accordingly. is reduced, so as to improve the problem of non-uniform display brightness of the first display panel 110 .

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Abstract

一种显示面板（110）包括显示区（A）、第一扇出区（10）、弯折区（20）和设置于第一扇出区（10）的多条扇出走线（101）。扇出走线（101）包括相连接的引出段（102）和延伸段（103）。多条扇出走线（101）包括第一走线组（1010）和第二走线组（1020），并非对称设置。第一走线组（1010）包括多个第一走线束（1011）。多个第一走线束（1011）中最靠近第二走线组（1020）的第一走线束（1011）包括第一子束（1012）和第二子束（1013）。第一子束（1012）和第二子束（1013）均包括相连接的引出部（104）和延伸部（105）。引出部（104）由相应子束的多条扇出走线（101）的引出段（102）形成。延伸部（105）由相应子束的多条扇出走线（101）的延伸段（103）形成。第一子束（1012）的延伸部（105）和第二子束（1013）的延伸部（105）之间的间距大于任意第一走线束（1011）中相邻两条扇出走线（101）的间距。

Description

一种显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置由于材料和结构具有可弯曲的特性，为产品外观形态的多样性提供了可能，例如曲面显示装置和可折叠显示装置。
发明内容
一方面，提供一种显示面板。所述显示面板具有沿第一方向依次设置的显示区、第一扇出区和弯折区。
所述显示面板包括设置于所述第一扇出区的多条扇出走线。所述扇出走线由所述第一扇出区靠近所述显示区的一侧延伸至所述第一扇出区靠近所述弯折区的一侧，且所述扇出走线包括相连接的引出段和延伸段。所述引出段相对于所述延伸段靠近所述显示区。所述多条扇出走线包括沿第二方向并列设置的第一走线组和第二走线组，所述第一走线组和所述第二走线组非对称设置。所述第一方向与所述第二方向相交。
所述第一走线组包括沿所述第二方向并列设置的多个第一走线束。所述多个第一走线束中最靠近所述第二走线组的第一走线束包括第一子束和第二子束。所述第二子束相对于所述第一子束靠近所述第二走线组。所述第一子束和所述第二子束包括相连接的引出部和延伸部。所述引出部由相应子束的多条扇出走线的引出段形成。所述延伸部由相应子束的多条扇出走线的延伸段形成。沿所述第二方向，所述第一子束的延伸部和所述第二子束的延伸部之间的间距大于任意第一走线束中相邻两条扇出走线的间距。
在一些实施例中，所述第二子束包括沿所述第二方向并列设置的第一走线簇和第二走线簇。所述第二走线簇相对于所述第一走线簇靠近所述第二走线组。沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第二走线簇的多条扇出走线的直线长度逐渐变长。所述扇出走线的直线长度为，所述扇出走线的引出段的两端点之间的直线距离，与所述扇出走线的延伸段的两端点之间的直线距离之和。所述第二走线簇的至少一条扇出走线具有曲线部分，和/或，所述第二走线簇的至少一条扇出走线具有加宽部分。所述加宽部分的线宽大于相应扇出走线中除所述加宽部分以外的其他部分的线宽。
在一些实施例中，所述第二走线簇包括沿所述第二方向并列设置的第一 子簇和第二子簇。所述第二子簇相对于所述第一子簇靠近所述第二走线组。所述第一子簇的多条扇出走线具有曲线部分，和/或，所述第二子簇的多条扇出走线具有加宽部分。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组。所述第一子簇的多条扇出走线的曲线部分的直线长度逐渐变短；和/或，沿所述第二方向且由所述第一走线组指向所述第二走线组。所述第二子簇的多条扇出走线的加宽部分的直线长度逐渐变长。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组。所述第一走线簇的多条扇出走线的直线长度逐渐变短。所述第一走线簇的至少一条扇出走线具有曲线部分。
在一些实施例中，所述第一走线簇的多条扇出走线具有曲线部分。沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一走线簇的多条扇出走线的曲线部分的直线长度逐渐变长。
在一些实施例中，所述曲线部分设置在相应扇出走线的延伸段；和/或，所述曲线部分的线宽与相应扇出走线中除所述曲线部分以外的其他部分的线宽大致相等。
在一些实施例中，所述加宽部分设置在相应扇出走线的延伸段；和/或，所述加宽部分呈直线设置。
在一些实施例中，所述第二子束的多条扇出走线的电阻均在第一预设阻值范围内；和/或，所述第二子束中最靠近所述第二走线组的扇出走线，与所述第二走线组中最靠近所述第二子束的扇出走线的电阻之差在所述第一预设阻值范围内。
在一些实施例中，所述显示面板还具有位于所述弯折区远离所述第一扇出区的一侧的第二扇出区。所述显示面板还包括设置于所述第二扇出区的多条第一连接线，第一连接线由所述第二扇出区靠近所述弯折区的一侧延伸至所述第二扇出区远离所述弯折区的一侧，且一条第一连接线与一条扇出走线电连接。沿所述第二方向，所述第一子束所连接的多条第一连接线，与所述第二子束所连接的多条第一连接线之间具有间距。由所述第二扇出区靠近所述弯折区的一侧至所述第二扇出区远离所述弯折区的一侧，所述第二子束所连接的多条第一连接线，逐渐向所述第一子束所连接的多条第一连接线靠拢。
在一些实施例中，所述显示面板还包括位于所述弯折区远离所述第一扇出区一侧的第二扇出区。所述显示面板还包括至少设置于所述第二扇出区的多条第一连接线。每条第一连接线由所述第二扇出区靠近所述弯折区的一侧 延伸至所述第二扇出区远离所述弯折区的一侧，且一条第一连接线与一条扇出走线电连接。
沿所述第二方向且由所述第一走线组指向所述第二走线组。所述多个第一走线束中最远离所述第二走线组的第一走线束为目标第一走线束，所述目标第一走线束的多条扇出走线的直线长度逐渐变短；所述目标第一走线束包括第三子束和第四子束。所述第三子束相对于所述第四子束远离所述第二走线组。
所述多条第一连接线中与所述第三子束的多条扇出走线连接的多条第一连接线形成第五子束，所述第五子束的每条第一连接线的延伸长度大于其直线长度。所述第一连接线的延伸长度为所述第一连接线的延伸路径的长度。所述第一连接线的直线长度为所述第一连接线的两端点之间的直线距离。所述第五子束的至少一条第一连接线具有折线部分，所述折线部分包括延伸方向不完全相同且依次连接的多个线段；和/或，所述第五子束的至少一条第一连接线具有曲线部分。
在一些实施例中，所述第五子束包括沿所述第二方向并列设置的第一连接线簇和第二连接线簇，所述第一连接线簇相对于所述第二连接线簇远离所述第二走线组；所述第一连接线簇和所述第二连接线簇的多条第一连接线具有第一折线部分；所述第一连接线簇的多条第一连接线还具有所述曲线部分。
在一些实施例中，所述显示面板还包括设置于所述第二扇出区远离所述弯折区一侧的测试电路，所述第一折线部分位于所述测试电路在所述第二方向上的一侧；所述第一折线部分包括依次相连的第一折线段、第二折线段和第三折线段，所述第一折线段和所述第三折线段大致沿所述第一方向延伸，所述第二折线段大致沿所述第二方向延伸；所述第一折线段相对于所述第三折线段远离所述第二走线组；所述第一折线段与相应的扇出走线电连接，所述第三折线段与所述测试电路电连接；所述第一连接线簇的第一折线部分至少部分围绕所述第二连接线簇的第一折线部分。
在一些实施例中，所述第一连接线簇的第一连接线的曲线部分，设置于相应的第一连接线的第一折线部分的第一折线段。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇和所述第二连接线簇的多条第一连接线的第一折线部分的直线长度逐渐变短；所述第一折线部分的直线长度为，所述第一折线部分的各线段的两端点之间的直线距离之和；和/或，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇的多条第一连接线的 曲线部分的直线长度逐渐变短。
在一些实施例中，所述第五子束还包括沿所述第二方向并列设置的第三连接线簇和第四连接线簇，所述第三连接线簇相对于所述第四连接线簇远离所述第二走线组；且所述第三连接线簇和所述第四连接线簇，相对于所述第一连接线簇和所第二连接线簇靠近所述第二走线组；所述第三连接线簇和所述第四连接线簇的多条第一连接线具有第二折线部分；所述第三连接线簇的多条第一连接线还具有所述曲线部分。
在一些实施例中，所述显示面板还包括设置于所述第二扇出区远离所述弯折区一侧的测试电路，所述第二折线部分位于所述测试电路靠近所述第二扇出区的一侧；所述第二折线部分包括依次相连的第四折线段和第五折线段，所述第四折线段大致沿所述第一方向延伸，所述第五折线段大致沿所述第二方向延伸；所述第四折线段与相应的扇出走线电连接，所述第五折线段与所述测试电路电连接；所述第三连接线簇的第二折线部分至少部分围绕所述第四连接线簇的第二折线部分。
在一些实施例中，所述第三连接线簇的第一连接线的曲线部分，设置于相应的第一连接线的第二折线部分的第四折线段。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第三连接线簇和所述第四连接线簇的多条第一连接线的第二折线部分的直线长度逐渐变短；所述第二折线部分的直线长度为，所述第二折线部分的各线段的两端点之间的直线距离之和；和/或，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第三连接线簇的多条第一连接线的曲线部分的直线长度逐渐变短。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇、所述第二连接线簇、所述第三连接线簇和所述第四连接线簇的多条第一连接线的延伸长度逐渐变短。
在一些实施例中，所述多条第一连接线中与所述第四子束的多条扇出走线连接的多条第一连接线形成第六子束，所述第六子束的每条第一连接线的延伸长度大致等于其直线长度。
在一些实施例中，最远离所述第二走线组的扇出走线，与其所连接的第一连接线的延伸长度之和为第一长度；所述第二走线组中最远离所述第一走线组的扇出走线，与其所连接的第一连接线的延伸长度之和为第二长度；所述第一长度与所述第二长度大致相等。
在一些实施例中，最远离所述第二走线组的扇出走线，与其所连接的第 一连接线的电阻之和为第一电阻；所述第二走线组中最远离所述第一走线组的扇出走线，与其所连接的第一连接线的电阻之和为第二电阻；所述第一电阻与所述第二电阻大致相等。
在一些实施例中，沿所述第二方向且由所述第一走线组指向所述第二走线组，相邻两个第一走线束中的每个第一走线束的多条扇出走线的直线长度逐渐减小；所述相邻两个第一走线束中，相对远离所述第二走线组的第一走线束的至少一条扇出走线具有曲线部分；且，所述第一走线束中具有曲线部分的扇出走线相对于所述第一走线束中的其他扇出走线靠近所述第二走线组。
在一些实施例中，所述第二走线组包括沿第二方向并列设置的多个第二走线束；沿所述第二方向且由所述第二走线组指向所述第一走线组，相邻两个第二走线束中的每个第二走线束的多条扇出走线的直线长度逐渐减小；所述相邻两个的第二走线束中，相对远离所述第一走线组的第二走线束的至少一条扇出走线具有曲线部分；且，所述第二走线束中具有曲线部分的扇出走线相对于所述第二走线束中的其他扇出走线靠近所述第一走线组。
在一些实施例中，所述显示面板具有位于所述弯折区远离所述第一扇出区的一侧的第二扇出区；所述显示面板包括至少设置于所述第二扇出区的多条第一连接线，所述第一连接线由所述第二扇出区靠近所述弯折区的一侧延伸至所述第二扇出区远离所述弯折区的一侧；所述显示面板还包括设置于所述弯折区的多条第二连接线，所述第二连接线由所述弯折区靠近所述第一扇出区的一侧延伸至所述弯折区靠近所述第二扇出区的一侧；一条所述扇出走线、一条所述第二连接线和一条所述第一连接线依次电连接。
在一些实施例中，所述显示面板还包括衬底、第一栅导电层、第二栅导电层和源漏导电层。第一栅导电层设置于所述衬底上。第二栅导电层设置于所述第一栅导电层远离所述衬底一侧。源漏导电层设置于所述第二栅导电层远离所述衬底一侧。其中，所述多条扇出走线中的一部分扇出走线设置于所述第一栅导电层中，另一部分扇出走线设置于所述第二栅导电层中；所述多条第一连接线中的一部分第一连接线设置于所述第一栅导电层中，另一部分第一连接线设置于所述第二栅导电层中；所述多条第二连接线设置于所述源漏导电层中。
在一些实施例中，所述显示区大致呈矩形，所述显示区的靠近所述第一扇出区的两个拐角为弧形拐角；所述两个拐角分别为第一拐角和第二拐角，所述第一拐角和所述第一走线组位于参考线的一侧，所述第二拐角和所述第 二走线组位于所述参考线的另一侧；所述参考线为沿所述第一方向且过所述显示区的直线；所述第一拐角的弧度小于所述第二拐角的弧度。
另一方面，提供一种显示装置，包括第一显示面板。所述第一显示面板为上述任一实施例所述的显示面板。
在一些实施例中，显示装置还包括第二显示面板和转轴。转轴设置于所述第二显示面板的背侧，所述第二显示面板可沿所述转轴折叠；其中，所述第一显示面板设置于所述第二显示面板的背侧，且位于所述转轴的一侧；所述第一显示面板和所述第二显示面板的出光方向相背。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示面板的一种俯视结构图；
图3为图2所示的一种显示面板沿剖面线Z-Z＇处的剖面图；
图4为根据一些实施例的显示面板的周边区B局部的结构图；
图5为根据一些实施例的显示面板的一种结构图；
图6A为图5中的显示面板的H处的局部放大图；
图6B为图6A所示的一种显示面板沿剖面线A1-A2处的剖面图；
图6C为图6A所示的一种显示面板沿剖面线B1-B2处的剖面图；
图6D为图6A所示的一种显示面板沿X方向的剖面图；
图7A为根据一些实施例的显示面板的另一种结构图；
图7B为根据一些实施例数据线线数与电阻值的曲线图；
图8A为根据一些实施例的显示面板的又一种结构图；
图8B为根据一些实施例的显示面板的又一种结构图；
图8C为根据一些实施例的显示面板的另一种结构图；
图8D为根据一些实施例数据线线数与电阻值的另一种曲线图；
图9A为图8C中的显示面板的J处的局部放大图；
图9B为根据一些实施例数据线线数与电阻值的又一种曲线图；
图10为图8C中的显示面板的L处的局部放大图；
图11为图8B中的显示面板的M处的一种局部放大图；
图12为图8B中的显示面板的M处的另一种局部放大图；
图13为图7A中的显示面板的A2或A3处的一种局部放大图；
图14为图7A中的显示面板的A4或A5处的一种局部放大图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiment)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示面板及显示装置100。以下对显示装置100进行介绍。
如图1所示，本公开的一些实施例提供了一种显示装置100。该显示装置100可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期实施例可实施在多种电子装置中或与多种电子装置关联，多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、 电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
此外，根据显示装置100能否折叠进行划分，显示装置100可以是可折叠显示装置或普通显示装置(可以称为平面显示装置)。
示例性地，如图1所示，显示装置100为可折叠显示装置。可折叠显示装置包括第一显示面板110、第二显示面板(图1中未示意出)和转轴120。其中，第一显示面板110设置于第二显示面板的背侧，且位于转轴120的一侧。第一显示面板110和第二显示面板的出光方向相背。
此外，为了便于弯折，及避让可折叠显示装置的转动组件(包括上述转轴120)，上述第一显示面板110靠近和远离转动组件的两侧的结构可以呈现不对称的设计。
下面以显示装置100为可折叠显示装置为例，对本公开的一些实施例进行示意性说明。
其中，上述第一显示面板110和第二显示面板均可以为有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板等，本公开对此不做具体限定。
下面以第一显示面板110为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2所示，第一显示面板110具有显示区A和位于显示区A至少一侧的周边区B。附图2以周边区B包围显示区A为例进行示意。
在一些实施例中，如图3所示，第一显示面板110包括显示基板1和用于封装该显示基板1的封装层2。
此处，封装层2可以为封装薄膜，也可以为封装基板。在一些实施例中，该封装层2包括第一无机薄膜21、有机薄膜22和第二无机薄膜23，以避免外界环境中的水汽和氧气进入第一显示面板110内，损伤发光器件11中的有机材料而造成第一显示面板110的寿命缩短。
这里，在第一显示面板110靠近和远离转动组件的两侧的结构呈现不对称的设计的情况下，第一显示面板110的显示区A靠近和远离转动组件的两侧的结构同样呈现不对称的设计(以参考线K为对称线，参考线K为沿第一方向Y且过显示区A的直线，第一显示面板110的显示区A的结构不对称， 该显示区A大致呈矩形、六边形、圆形或不规则的多边形，本公开实施例不限于此)。示例性地，如图1与图2所示，第一显示面板110的显示区A大致呈矩形，显示区A的靠近第一扇出区10的两个拐角为弧形拐角。两个拐角分别为第一拐角C和第二拐角D，第一拐角C的弧度小于第二拐角D的弧度，需要说明的是，该弧度对应的圆心在第一显示面板110上。
其中，显示区A为显示图像的区域，显示区A被配置为设置子像素P。
示例性地，如图2和图3所示，上述第一显示面板110包括设置在衬底115的一侧、且位于显示区A的多个子像素P。该多个子像素P排列为多行和多列，每行子像素P可以包括沿第二方向X排列的多个子像素P，每列子像素P可以包括沿第一方向Y排列的多个子像素P。
此处，第一方向Y和第二方向X相互交叉。第一方向Y和第二方向X之间的夹角可以根据实际需要选择设置。示例性地，第一方向Y和第二方向X之间的夹角可以为85°、87°、89°、90°、91°或92°等。
在一些实施例中，如图2和图3所示，上述第一显示面板110还可以包括多条数据连接线DL和多条栅线连接线(图2中未示意出)。其中，该多条栅连接线沿第二方向X延伸，该多条数据连接线DL沿第一方向Y延伸。同一行子像素P可以与一条栅连接线电连接，同一列子像素P可以与一条数据连接线DL电连接。这里，栅连接线和数据连接线DL均与子像素P的像素驱动电路电连接。
在一些实施例中，如图2和图3所示，每个子像素P均包括设置于衬底115上的发光器件11和像素驱动电路12，像素驱动电路12包括多个薄膜晶体管121。薄膜晶体管121包括有源层1211、源极1212、漏极1213和栅极1214，源极1212和漏极1213分别与有源层1211接触。沿远离衬底115的方向，发光器件11包括依次设置的第一电极层111、发光功能层112以及第二电极层113，第一电极层111和多个薄膜晶体管121中作为驱动晶体管的薄膜晶体管的源极1212或漏极1213电连接。图3中以第一电极层111和薄膜晶体管121的源极1212电连接进行示意。
需要说明的是，上述源极1212和漏极1213可以互换，即图3中的1212表示漏极，图3中的1213表示源极。
在一些实施例中，上述发光功能层112仅包括发光层。在另一些实施例中，发光功能层112除包括发光层外，还包括电子传输层(electiontransporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)和空穴注入层(hole injection layer， 简称HIL)中的至少一个。
在一些实施例中，如图3所示，显示基板1还包括像素界定层PDL，像素界定层PDL包括多个开口区，一个发光器件11设置于一个开口区中。
在一些实施例中，如图3所示，显示基板1还包括隔垫物PS，隔垫物PS设置于像素界定层PDL与发光层功能层112之间。
在一些实施例中，如图3所示，显示基板1还包括半导体层ACT、第一栅绝缘层GI1、第一栅导电层GATE1、第二栅绝缘层GI2、第二栅导电层GATE2、层间绝缘层ILD、第一源漏导电层SD1、第一平坦层PLN1、第二源漏导电层SD2和第二平坦层PLN2。
如图3所示，半导体层ACT、第一栅绝缘层GI1、第一栅导电层GATE1、第二栅绝缘层GI2、第二栅导电层GATE2、层间绝缘层ILD、第一源漏导电层SD1和第二源漏导电层SD2依次层叠设置于衬底115和第一电极层111之间。
其中，半导体层ACT的材料包括非晶硅、单晶硅、多晶硅、或金属氧化物半导体材料。例如，半导体层ACT的材料包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、氧化锌(ZnO)，本公开实施例不限于此。半导体层包括各个薄膜晶体管121的有源层1211。
第一栅导电层GATE1与半导体层ACT交叠部分，分别形成薄膜晶体管121。其中，第一栅导电层GATE1的材料包括导电金属。例如，第一栅导电层GATE1的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。第一栅导电层GATE1包括各个薄膜晶体管121的栅极1214和电容器CST的第一极板。
第一栅绝缘层GI1设置于半导体层ACT和第一栅导电层GATE1之间，用于将半导体层ACT和第一栅导电层GATE1电绝缘。其中，第一栅绝缘层GI1的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种；例如，第一栅绝缘层GI1的材料包括二氧化硅，本公开实施例不限于此。
第二栅导电层GATE2与第一栅导电层GATE1交叠部分，形成电容器CST。其中，第二栅导电层GATE2的材料包括导电金属。例如，第二栅导电层GATE2的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。第二栅导电层GATE2包括电容器CST的第二极板。
第二栅绝缘层GI2设置于第一栅导电层GATE1和第二栅导电层GATE2之间，用于将第一栅导电层GATE1和第二栅导电层GATE2电绝缘。其中，第二栅绝缘层GI2的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中 的任一种。例如，第二栅绝缘层GI2的材料包括二氧化硅，本公开实施例不限于此。
层间介质层ILD设置于第一源漏导电层SD1和第二栅导电层GATE2之间，用于将第一源漏导电层SD1和第二栅导电层GATE2电绝缘。其中，层间介质层ILD的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种；例如，第二栅绝缘层GI2的材料包括二氧化硅，本公开实施例不限于此。
第一源漏导电层SD1设置于层间介质层ILD和第一平坦层PLN1之间。其中，第一源漏导电层SD1包括导电金属。例如，第一源漏导电层SD1的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。第一源漏导电层SD1包括薄膜晶体管121的源极1212和漏极1213。
第一平坦层PLN1设置于第一源漏导电层SD1和第二源漏导电层SD2之间，用于将第一源漏导电层SD1和第二源漏导电层SD2电绝缘。其中，第一平坦层PLN1的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。例如，第一平坦层PLN1的材料包括二氧化硅，本公开实施例不限于此。
第二源漏导电层SD2设置于第一平坦层PLN1和第二平坦层PLN2之间。其中，第二源漏导电层SD2包括导电金属。例如，第二源漏导电层SD2的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。第二源漏导电层SD2包括连接电极150、初始化信号线151和辅助信号线中的至少一者，本公开实施例不限于此。
第二平坦层PLN2设置于第二源漏导电层SD2和第一电极层111之间，用于将第二源漏导电层SD2和第一电极层111电绝缘。其中，第二平坦层PLN2的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。例如，第二平坦层PLN2的材料包括二氧化硅，本公开实施例不限于此。
其中，参阅图2，周边区B为不显示的区域，周边区B可以被配置为设置扫描驱动电路、电路走线和绑定引脚等。
在一些实施例中，如图2与图4所示，周边区B具有沿第一方向Y依次设置的第一扇出区10、弯折区20、第二扇出区30、静电防护区40、测试区50、第三扇出区60和绑定区70。
如图2与图4所示，第一扇出区10设有多条扇出走线101，每条扇出走线101由第一扇出区10靠近显示区A的一侧延伸至第一扇出区10靠近弯折区20的一侧。其中，扇出走线101包括相连接的引出段102和延伸段103，引出段102相对于延伸段103靠近显示区A。
在此基础上，如图5所示，多条扇出走线101包括沿第二方向X并列设置的第一走线组1010和第二走线组1020。第一走线组1010和第二走线组1020位于参考线K相对的两侧。
此外，如图6A所示，上述多条扇出走线101可以位于第一栅导电层GATE1和/或第二栅导电层GATE2。示例性地，如图6D所示，多条扇出走线101中的一部分扇出走线101设置于第一栅导电层GATE1中，另一部分扇出走线101设置于第二栅导电层GATE2中，位于第一栅导电层GATE1的扇出走线101在衬底115上的正投影，与位于第二栅导电层GATE2的扇出走线101在衬底115上的正投影至少部分错开设置，且交错排列，以减少位于第一栅导电层GATE1的扇出走线101和位于第二栅导电层GATE2的扇出走线101的寄生电容。
如图6A所示，在一些实施例中，弯折区20设有多条第二连接线21，每条第二连接线21由弯折区20靠近第一扇出区10的一侧延伸至弯折区20靠近第二扇出区30的一侧；一条扇出走线101与一条第二连接线21电连接。
此处，如图6B所示，多条第二连接线21可以位于第二源漏导电层SD2，减少弯折区20所需设置的金属层，使得弯折区20的柔性更高。
其中，如图6B所示，位于第二栅导电层GATE2的扇出走线101与第二连接线21电连接，可以通过位于第一源漏导电层SD1的转接块与第二连接线21电连接。如图6C所示，位于第一栅导电层GATE1的扇出走线101与第二连接线21电连接，可以通过位于第二栅导电层GATE2的转接块、以及位于第一源漏导电层SD1的转接块与第二连接线21电连接。
如图6A所示，第二扇出区30设有多条第一连接线31，每条第一连接线31由第二扇出区30靠近弯折区20的一侧延伸至第二扇出区30远离弯折区20的一侧，且一条第一连接线31与一条扇出走线101电连接，一条扇出走线101、一条第二连接线21和一条第一连接线31依次电连接。
此处，第一连接线31可以位于第一栅导电层GATE1和/或第二栅导电层GATE2。示例性地，如图6B与图6C所示，多条第一连接线31中的一部分第一连接线31设置于第一栅导电层GATE1中，另一部分第一连接线31设置于第二栅导电层GATE2中，位于第一栅导电层GATE1的第一连接线31在衬底115上的正投影，与位于第二栅导电层GATE2的第一连接线31在衬底115上的正投影错开设置，且交错排列。
其中，如图6B所示，位于第二栅导电层GATE2的第一连接线31与第二连接线21电连接，可以通过位于第一源漏导电层SD1的转接块与第二连接线 21电连接，从而实现一条扇出走线101、一条第二连接线21和一条第一连接线31依次电连接。如图6C所示，位于第一栅导电层GATE1的第一连接线31与第二连接线21电连接，可以通过位于第二栅导电层GATE2的转接块、以及位于第一源漏导电层SD1的转接块与第二连接线21电连接，从而实现一条扇出走线101、一条第二连接线21和一条第一连接线31依次电连接。
如图6A所示，静电防护区40设置有静电释放电路。该静电释放电路用于疏导第一显示面板110内部产生的静电，避免静电击穿。
如图6A所示，测试区50设置有测试电路51，测试电路51与第一连接线31电连接。此处，如图6B所示，该测试电路51可以设置于第二源漏导电层SD2。
其中，如图6B所示，位于第二源漏导电层SD2的测试电路51与第一连接线31电连接，可以通过位于第一源漏导电层SD1的转接块与第一连接线31电连接。如图6C所示，位于第二源漏导电层SD2的测试电路51与第一连接线31电连接，可以通过位于第一源漏导电层SD1的转接块、以及位于第一栅导电层GATE1与第一连接线31电连接。
如图6A所示，第三扇出区60设有多条第三连接线61，每条第三连接线61由第三扇出区60靠近测试区50的一侧延伸至第三扇出区60远离测试区50的一侧，多条第三连接线61与测试电路51电连接接，且与多条第一连接线31一一对应。
其中，如图6A所示，上述多条第三连接线61可以位于第一栅导电层GATE1和/或第二栅导电层GATE2。示例性地，如图6B与图6C所示，多条第三连接线61中的一部分第三连接线61设置于第一栅导电层GATE1中，另一部分第三连接线61设置于第二栅导电层GATE2中，位于第一栅导电层GATE1的第三连接线61在衬底115上的正投影，与位于第二栅导电层GATE2的第三连接线61在衬底115上的正投影错开设置，且交错排列。
其中，如图6B所示，位于第二栅导电层GATE2的第三连接线61与测试电路51电连接，可以通过位于第一源漏导电层SD1的转接块与测试电路51电连接。如图6C所示，位于第一栅导电层GATE1的第三连接线61与测试电路51电连接，可以通过位于第二栅导电层GATE2的转接块、以及位于第一源漏导电层SD1的转接块与测试电路51电连接。
如图6A所示，绑定区70被配置为绑定柔性电路板。绑定区70设置有多个绑定引脚71，一个绑定引脚71与一条第三连接线61电连接，或多个绑定引脚71与一条第三连接线61电连接。
其中，绑定引脚71可以位于第二源漏导电层SD2。如图6B所示，位于第二栅导电层GATE2的第三连接线61与绑定引脚71电连接，可以通过位于第一源漏导电层SD1的转接块与绑定引脚71电连接。如图6C所示，位于第一栅导电层GATE1的第三连接线61与绑定引脚71电连接，可以通过位于第二栅导电层GATE2的转接块、以及位于第一源漏导电层SD1的转接块与绑定引脚71电连接。此外，绑定引脚71可以位于多层金属，用于降低电阻。需要说明的是，多层金属可以包括第一源漏导电层SD1、第二源漏导电层SD2、第一栅导电层GATE1与第二栅导电层GATE2中的至少两层。当有触控层时，可以是第一源漏导电层SD1、第二源漏导电层SD2、第一栅导电层GATE1、第二栅导电层GATE2与触控层至少两层。
相关技术中，如图1所示，在第一显示面板110的显示区A靠近和远离转动组件的两侧的结构同样呈现不对称的设计的情况下，如图5与图7A所示，其对应的第一走线组1010和第二走线组1020相对于参考线K呈现非对称的设置。这样的话，位于第一扇出区10的第一走线组1010的扇出走线101，与第二走线组1020的扇出走线101长度差异比较大，电阻的差异比较大，从而导致传输至像素驱动电路12的电压差异很大，导致发光器件11所接收的驱动电流产生较大的差异，造成第一显示面板110产生显示亮度不均一的问题。
示例性地，如图7A所示，A1、A2、A3、A4与A5区域的扇出走线101的长度差异比较大，从而存在同一区域内的两根扇出走线101的电阻值差异比较大，如图7B所示，对应于图7A中A1、A2、A3、A4与A5区域电阻值突变情况，通过图7B中可以看出，A1、A2、A3、A4与A5区域的电阻值突变比较大。
基于此，如图1所示，本公开的一些实施例所提供的显示面板，该显示面板可以为上述任一实施例所述的第一显示面板110。需要说明的是，第一显示面板110的外观可以为对称或不对称设计。
其中，如图8A所示，第一走线组1010包括沿第二方向X并列设置的多个第一走线束1011，为了提高电源信号线所传输的电源信号的均一性和稳定性，第一走线组1010包括多个第一走线束1011，相邻的两个第一走线束1011之间设有一组电源信号线。本公开实施例对第一走线束1011的数量不做具体限定，具体可以根据实际情况进行设定。多个第一走线束1011中最靠近第二走线组1020的第一走线束1011包括第一子束1012和第二子束1013。第二子束1013相对于第一子束1012靠近第二走线组1020。
如图8B所示，第一子束1012和第二子束1013均包括相连接的引出部 104和延伸部105。引出部104由相应子束的多条扇出走线101的引出段102形成，延伸部105由相应子束的多条扇出走线101的延伸段103形成。沿第二方向X，如图8C所示，第一子束1012的延伸部105和第二子束1013的延伸部105之间的间距D1大于任意第一走线束1011中相邻两条扇出走线101的间距D2。
由上述可知，在本公开的实施例中，将第一走线组1010中最靠近第二走线组1020的第一走线束1011拆分为第一子束1012和第二子束1013，使得第二子束1013更加靠近参考线K，从而减少第二子束1013的引出段102的长度，使得第一走线束1011中靠近第二走线组1020的第二子束1013的扇出走线101的长度减小，从而减小第一走线束1011中靠近第二走线组1020的第二子束1013的扇出走线101，与第二走线组1020靠近第一走线组1010的扇出走线101之间的长度差异，也即减小第一走线束1011中靠近第二走线组1020的第二子束1013的扇出走线101，与第二走线组1020靠近第一走线组1010的扇出走线101之间的电阻的差值。
示例性地，如图8D所示，在图8D中的A1区域电阻值曲线相对图7B中A1区域电阻曲线更加平滑，其电阻值突变情况得到缓和，从而使图7A中的A1处扇出走线101的电阻得到补偿，以降低图7A中A1区域扇出走线101电阻值较大的差值。
在这种情况下，沿第二方向X且由第一走线组1010指向第二走线组1020，从参考线K的一侧到另一侧，数据线(包括数据连接线DL和扇出走线101)的电阻的突变降低，如图8D中所示的A1区域。这样的话，在同一显示面板中，由于发光器件11所接收的驱动电流的大小仅与恒定电压端VDD及数据信号V data相关，因此，在像素驱动电路12接收到的数据信号V data差异减小的情况下，发光器件11所接收的驱动电流的差异也会随之减小，从而改善显示面板110显示亮度不均一的问题。
在一些实施例中，如图9A所示，第二子束1013包括沿第二方向X并列设置的第一走线簇1014和第二走线簇1015，第二走线簇1015相对于第一走线簇1014靠近第二走线组1020。
其中，沿第二方向X且由第一走线组1010指向第二走线组1020，第二走线簇1015的多条扇出走线101的直线长度逐渐变长。第一走线簇1014的多条扇出走线101的直线长度逐渐变短。此处，扇出走线101的直线长度为，扇出走线101的引出段102的两端点之间的直线距离，与扇出走线101的延伸段103的两端点之间的直线距离之和。
在一些实施例中，第一走线簇1014的至少一条扇出走线101具有曲线部分E。这样第一走线簇1014的扇出走线101，可以通过设置曲线部分E来降低扇出走线101之间的走线长度上的差异，从而减小第一走线簇1014的各扇出走线101对应的数据线之间的电阻的差异。
示例性地，第一走线簇1014的多条扇出走线101具有曲线部分E。沿第二方向X且由第一走线组1010指向第二走线组1020，第一走线簇1014的多条扇出走线101的曲线部分E的直线长度逐渐变长。这样的话，第一走线簇1014的多条扇出走线101可以通过曲线部分E的直线长度，来补偿扇出走线101的直线长度上的差异，从而减小第一走线簇1014的多条扇出走线101对应的数据线之间的电阻的差异。此处，曲线部分E的直线长度为曲线部分E为走线长度。
在一些实施例中，如图9A所示，第二走线簇1015的至少一条扇出走线101具有曲线部分E，这样第二走线簇1015的扇出走线101，可以通过设置曲线部分E来降低扇出走线101之间的走线长度上的差异，从而减小第二走线簇1015的各扇出走线101对应的数据线之间的电阻的差异。
示例性地，第二走线簇1015包括沿第二方向X并列设置的第一子簇1016和第二子簇1017，第二子簇1017相对于第一子簇1016靠近第二走线组1020；第一子簇1016的多条扇出走线101具有曲线部分E。
其中，沿第二方向X且由第一走线组1010指向第二走线组1020，第一子簇1016的多条扇出走线101的曲线部分E的直线长度逐渐变短。这样的话，第一子簇1016的多条扇出走线101可以通过曲线部分E的直线长度，来补偿扇出走线101的直线长度上的差异，从而减小第一子簇1016的多条扇出走线101对应的数据线之间的电阻的差异。需要说明的是，曲线部分E的直线长度为曲线部分E两端点之间的直线距离。
其中，上述曲线部分E可以设置在相应扇出走线101的引出段102，也可以设置在延伸段103。示例性地，上述曲线部分E设置在相应扇出走线101的延伸段103。此外，曲线部分E的线宽(线宽的方向沿第二方向X)与相应扇出走线101中除曲线部分E以外的其他部分的线宽可以大致相等。
需要说明的是，曲线部分E的线宽与相应扇出走线101中除曲线部分E以外的其他部分的线宽也可以不同，可以为了平衡各扇出走线101对应的数据线之间的电阻进行调整，本公开对此不做具体限定。
在一些实施例中，如图9A所示，第二走线簇1015的至少一条扇出走线101具有加宽部分F，加宽部分F的线宽大于相应扇出走线101中除加宽部分 F以外的其他部分的线宽。这样第二走线簇1015的扇出走线101，可以通过设置加宽部分F来降低扇出走线101之间的走线长度上的差异所带来电阻差异，从而减小第二走线簇1015的各扇出走线101对应的数据线之间的电阻的差异。
示例性地，第二走线簇1015包括沿第二方向X并列设置的第一子簇1016和第二子簇1017，第二子簇1017相对于第一子簇1016靠近第二走线组1020。第二子簇1017的多条扇出走线101具有加宽部分F。
其中，沿第二方向X且由第一走线组1010指向第二走线组1020，第二子簇1017的多条扇出走线101的加宽部分F的直线长度逐渐变长。这样的话，第二子簇1017的多条扇出走线101可以通过加宽部分F所带来的电阻的降低，来补偿扇出走线101的直线长度的加长所带来的电阻的上升，从而减小第一子簇1016的多条扇出走线101对应的数据线之间的电阻的差异。此处，加宽部分F的直线长度为加宽部分F两端点之间的直线距离。
需要说明的是，上述第二走线簇1015的至少一条扇出走线101具有曲线部分E的实施例，和第二走线簇1015的至少一条扇出走线101具有加宽部分F的实施例以合适的方式任意组合，本公开在此不做具体限定。
其中，上述加宽部分F可以设置在相应扇出走线101的引出段102，也可以设置在延伸段103。示例性地，上述加宽部分F设置在相应扇出走线101的延伸段103。此外，加宽部分F可以呈直线设置。
需要说明的是，加宽部分F也可呈曲线设置，可以为了平衡各扇出走线101对应的数据线之间的电阻进行调整，本公开对此不做具体限定。
在一些实施例中，第二子束1013的多条扇出走线101的电阻均在第一预设阻值范围内；和/或，第二子束1013中最靠近第二走线组1020的扇出走线101，与第二走线组1020中最靠近第二子束1013的扇出走线101的电阻之差在第一预设阻值范围内。
示例性地，第二子束1013的多条扇出走线101的电阻均在第一预设阻值范围内。此处，第二子束1013的多条扇出走线101的电阻指的是，第二子束1013的多条扇出走线101对应数据线DL的电阻。第一预设阻值范围指的是，第二子束1013的多条扇出走线101对应数据线DL的电阻的范围。示例性地，第一预设阻值范围为1050Ω～1200Ω。例如，参阅9B，第二子束1013的多条扇出走线101的扇出走线101对应的数据线(A1区域)的电阻均在1050Ω～1200Ω内。
示例性地，第二子束1013中最靠近第二走线组1020的扇出走线101，与 第二走线组1020中最靠近第二子束1013的扇出走线101的电阻之差在第一预设阻值范围内。此处，第二子束1013的多条扇出走线101的电阻之差指的是，第二子束1013的多条扇出走线101对应数据线DL的电阻之差。第一预设阻值范围指的是，第二子束1013的多条扇出走线101对应数据线DL的电阻之差的范围。示例性地，第一预设阻值范围为300Ω～500Ω。例如，参阅9B，第二子束1013中最靠近第二走线组1020的扇出走线101，与第二走线组1020中最靠近第二子束1013的扇出走线101的电阻之差在300Ω～500Ω内。
综上，如图7A中A1区域的扇出走线101，即第一走线簇1014和第二走线簇1015的扇出走线101，可以通过曲线部分E和/或加宽部分F来补偿升高或降低扇出走线101之间的走线长度上的差异所带来电阻差异，以此减少多条扇出走线101对应的数据线之间的电阻的差异，最终结果如图9B所示，A1区域电阻突变趋势得到改善，电阻值得到补偿，电阻的差异逐渐降低。
在一些实施例中，如图10所示，沿第二方向X，第一子束1012所连接的多条第一连接线31，与第二子束1013所连接的多条第一连接线31之间具有间距D3。
由第二扇出区30靠近弯折区20的一侧至第二扇出区30远离弯折区20的一侧，第二子束1013所连接的多条第一连接线31，逐渐向第一子束1012所连接的多条第一连接线31靠拢，以减小第一连接线31占用的面积。
在一些实施例中，如图11所示，沿第二方向X且由第一走线组1010指向第二走线组1020，多个第一走线束1011中最远离第二走线组1020的第一走线束1011为目标第一走线束1100，目标第一走线束1100的多条扇出走线101的直线长度逐渐变短。目标第一走线束1100包括第三子束1101和第四子束1102，第三子束1101相对于第四子束1102远离第二走线组1020。
其中，多条第一连接线31中与第三子束1101的多条扇出走线101连接的多条第一连接线31形成第五子束1103，第五子束1103的每条第一连接线31的延伸长度大于其直线长度。第一连接线31的延伸长度为第一连接线31的延伸路径的长度，第一连接线31的直线长度为第一连接线31的两端点之间的直线距离。
在此基础上，如图11所示，第五子束1103的至少一条第一连接线31具有折线部分310，折线部分310包括延伸方向不完全相同且依次连接的多个线段。和/或，如图12所示，第五子束1103的至少一条第一连接线31具有曲线部分E。
这样的话，可以通过第五子束1103中的第一连接线31的折线部分310 和/或曲线部分E，来补偿第三子束1101的多条扇出走线101的走线长度，与第二走线组1020远离第一走线组1010的部分扇出走线101的走线长度上的差异，也即补偿第三子束1101的多条扇出走线101对应的数据线，与第二走线组1020远离第一走线组1010的部分扇出走线101对应的数据线之间的电阻差异，从而改善显示面板110显示亮度不均一的问题。
例如，图8D中第1～150根数据线为第五子束1103的多条第一连接线31对应的数据线，第一连接线31的折线部分310和/或曲线部分E可以使得数据线的电阻值上升，缩小第1～150根数据线与第1951～2101根数据线的电阻差异，使得第1～150根数据线与第1951～2101根数据线的电阻大致相等。
此外，还可以通过第五子束1103中的第一连接线31的折线部分310和/或曲线部分E的长短，来减小第三子束1101的多条扇出走线101所对应的多条数据线的电阻的差异。
示例性地，第五子束1103包括沿第二方向X并列设置的第一连接线簇1104和第二连接线簇1105，第一连接线簇1104相对于第二连接线簇1105远离第二走线组1020。其中，第一连接线簇1104和第二连接线簇1105的多条第一连接线31具有第一折线部分3100，第一连接线簇1104的多条第一连接线31还具有曲线部分E。
在此基础上，沿第二方向X且由第一走线组1010指向第二走线组1020，第一连接线簇1104和第二连接线簇1105的多条第一连接线31的第一折线部分3100的直线长度逐渐变短。其中，第一折线部分3100的直线长度为，第一折线部分3100的各线段的两端点之间的直线距离之和。和/或，沿第二方向X且由第一走线组1010指向第二走线组1020，第一连接线簇1104的多条第一连接线31的曲线部分E的直线长度逐渐变短。
如图8D与图12所示，第一连接线簇1104的多条第一连接线31的曲线部分E用于补偿第1～50根数据线的电阻值，使第1～50根数据线的电阻值上升，以此缩小第一扇出区10两侧走线的电阻差异，同时减小第1～50根数据线之间的电阻值发生差异性比较大的突变。
如图8D与图12所示，第二连接线簇1105的多条第一连接线31的第一折线部分3100用于补偿第50～100根数据线的电阻值，降低电阻值的差异。
示例性地，如图12所示，第五子束1103还包括沿第二方向X并列设置的第三连接线簇1106和第四连接线簇1107，第三连接线簇1106相对于第四连接线簇1107远离第二走线组1020，且第三连接线簇1106和第四连接线簇1107，相对于第一连接线簇1104和所第二连接线簇1105靠近第二走线组 1020。其中，第三连接线簇1106和第四连接线簇1107的多条第一连接线31具有第二折线部分3200，第三连接线簇1106的多条第一连接线31还具有曲线部分E。
在此基础上，沿第二方向X且由第一走线组1010指向第二走线组1020，第三连接线簇1106和第四连接线簇1107的多条第一连接线31的第二折线部分3200的直线长度逐渐变短。其中，第二折线部分3200的直线长度为，第二折线部分3200的各线段的两端点之间的直线距离之和。和/或，沿第二方向X且由第一走线组1010指向第二走线组1020，第三连接线簇1106的多条第一连接线31的曲线部分E的直线长度逐渐变短。
参阅图9B和图12所示，第三连接线簇1106的多条第一连接线31的曲线部分E用于补偿第101～150根数据线，使第101～150根数据线的电阻值上升，并与第1951～2000根数据线的电阻大致相等。
如图8D所示，第100根数据线与第101根数据线电阻值差异比较大，因此第101根电阻值上升，从而降低了与第100根数据线的电阻值的差距。
通过图9B可以看出，在第1～100根数据线之间的电阻值得到补偿，突变性降低，相对平滑。
通过上述对第1～150根数据线的电阻进行补偿，这样的话，分别位于显示面板的参考线的两侧边缘的数据线的长度也大致相等，电阻也大致相等，像素驱动电路12接收到的电压也大致相等，显示面板110显示亮度更加均一。
在一些实施例中，沿第二方向X且由第一走线组1010指向第二走线组1020，第一连接线簇1104、第二连接线簇1105、第三连接线簇1106和第四连接线簇1107的多条第一连接线31的延伸长度逐渐变短。
在一些实施例中，如图所示，第一折线部分3100位于测试电路51在第二方向X上的一侧。第一折线部分3100包括依次相连的第一折线段3101、第二折线段3102和第三折线段3103，第一折线段3101和第三折线段3103大致沿第一方向Y延伸，第二折线段3102大致沿第二方向X延伸。例如，第一折线段3101、第二折线段3102和第三折线段3103相连接呈U形。
其中，第一折线段3101与相应的扇出走线101连接，第三折线段3103与测试电路51连接，且第一折线段3101相对于第三折线段3103远离第二走线组1020。第一连接线簇1104的第一折线部分3100围绕第二连接线簇1105的第一折线部分3100，以避免第一连接线簇1104的走线与第二连接线簇1105的走线产生交叉。
在此基础上，如图12所示，上述第一连接线簇1104的第一连接线31的 曲线部分E，设置于相应的第一连接线31的第一折线部分3100的第一折线段3101。
需要说明的是，第一连接线簇1104的第一连接线31的曲线部分E也可以设置在第二折线段3102和/或第三折线段3103，本公开实施例对此不做具体限定。
在一些实施例中，如图12所示，上述第二折线部分3200位于测试电路51靠近第二扇出区30的一侧。第二折线部分3200包括依次相连的第四折线段3201和第五折线段3202，第四折线段3201大致沿第一方向Y延伸，第五折线段3202大致沿第二方向X延伸。这里，第四折线段3201和第五折线段3202可以相垂直，并呈L形。第四折线段3201与相应的扇出走线101连接，第五折线段3202与测试电路51连接。第三连接线簇1106的第二折线部分3200围绕第四连接线簇1107的第二折线部分3200。
在此基础上，如图12所示，第三连接线簇1106的第一连接线31的曲线部分E，设置于相应的第一连接线31的第二折线部分3200的第四折线段3201。
需要说明的是，第三连接线簇1106的第一连接线31的曲线部分E也可以设置在第五折线段3202上，本公开实施例对此不做具体限定。
在一些实施例中，如图11所示，多条第一连接线31中与第四子束1102的多条扇出走线101连接的多条第一连接线31形成第六子束1108，第六子束1108的每条第一连接线31的延伸长度大致等于其直线长度。
参阅图8C，第一走线组1010中最远离第二走线组1020的扇出走线101，与其所连接的第一连接线31的延伸长度之和为第一长度。第二走线组1020中最远离第一走线组1010的扇出走线101，与其所连接的第一连接线31的延伸长度之和为第二长度。最远离第二走线组1020的扇出走线101，与其所连接的第一连接线31的电阻之和为第一电阻。第二走线组1020中最远离第一走线组1010的扇出走线101，与其所连接的第一连接线31的电阻之和为第二电阻。
其中，第一长度与第二长度大致相等。也即，第一电阻与第二电阻大致相等。
这样的话，分别位于第一显示面板110的参考线K的两侧边缘的数据线的长度也大致相等，电阻也大致相等，像素驱动电路12接收到的电压也大致相等，显示面板110显示亮度更加均一。
在一些实施例中，如图8C所示，沿第二方向X且由第一走线组1010指向第二走线组1020，相邻两个第一走线束1011中的每个第一走线束1011的 多条扇出走线101的直线长度逐渐减小。
在此基础上，如图7A与图13所示，相邻两个第一走线束1011中，相对远离第二走线组1020的第一走线束1011的至少一条扇出走线101具有曲线部分E，且第一走线束1011中具有曲线部分E的扇出走线101相对于第一走线束1011中的其他扇出走线101靠近第二走线组1020。
这样，通过该曲线部分E降低扇出走线101之间的走线长度上的差异，从而减小第一走线束1011的各扇出走线101对应的数据线之间的电阻的差异，对应于图7B，使A2与A3区域的电阻值突变情况得到改善，电阻值补偿后，A2与A3区域的电阻值为图9B所示，电阻值曲线更加平滑，突变降低。
需要说明的是，上述曲线部分E的具体形态可以为波浪形、锯齿形等。曲线部分E的形态为波浪形和/或锯齿形时，可以使曲线部分E的扇出走线101长度变长。
在一些实施例中，如图8C所示，第二走线组1020包括沿第二方向X并列设置的多个第二走线束1021。其中，如图7A与图14所示，沿第二方向X且由第二走线组1020指向第一走线组1010，相邻两个第二走线束1021中的每个第二走线束1021的多条扇出走线101的直线长度逐渐减小。
在此基础上，相邻两个的第二走线束1021中，相对远离第一走线组1010的第二走线束1021的至少一条扇出走线101具有曲线部分E，且第二走线束1021中具有曲线部分E的扇出走线101相对于第二走线束1021中的其他扇出走线101靠近第一走线组1010。
需要说明的是，上述曲线部分E的具体形态可以为波浪形、锯齿形等。曲线部分E的形态为波浪形和/或锯齿形时，可以使曲线部分E的扇出走线101长度变长。
这样，通过该曲线部分E降低扇出走线101之间的走线长度上的差异，从而减小第二走线束1011的各扇出走线101对应的数据线之间的电阻的差异，对应于图7B，使A4与A5区域的电阻值突变情况得到改善，电阻值补偿后，A4与A5区域的电阻值为图9B所示，电阻值曲线更加平滑，突变降低。
综上所述，通过曲线部分E、加宽部分F与折线部分310来补偿扇出走线101之间的走线长度上的差异，从而使各扇出走线101对应的数据线之间的电阻的差异减小，电阻值突变性降低，数据线线数与电阻值曲线更加平滑，在这种情况下，数据线的电阻的突变降低，在同一显示面板中，由于发光器件11所接收的驱动电流的大小仅与恒定电压端VDD及数据信号V data相关，因此，在像素驱动电路12接收到的数据信号V data差异减小的情况下，发光器 件11所接收的驱动电流的差异也会随之减小，从而改善第一显示面板110产生显示亮度不均一的问题。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (30)

  1. 一种显示面板，具有沿第一方向依次设置的显示区、第一扇出区和弯折区；
    所述显示面板包括设置于所述第一扇出区的多条扇出走线，所述扇出走线由所述第一扇出区靠近所述显示区的一侧延伸至所述第一扇出区靠近所述弯折区的一侧，且所述扇出走线包括相连接的引出段和延伸段，所述引出段相对于所述延伸段靠近所述显示区；
    所述多条扇出走线包括沿第二方向并列设置的第一走线组和第二走线组，所述第一走线组和所述第二走线组非对称设置；所述第一方向与所述第二方向相交；
    所述第一走线组包括沿所述第二方向并列设置的多个第一走线束，所述多个第一走线束中最靠近所述第二走线组的第一走线束包括第一子束和第二子束，所述第二子束相对于所述第一子束靠近所述第二走线组；
    所述第一子束和所述第二子束包括相连接的引出部和延伸部，所述引出部由相应子束的多条扇出走线的引出段形成，所述延伸部由相应子束的多条扇出走线的延伸段形成；沿所述第二方向，所述第一子束的延伸部和所述第二子束的延伸部之间的间距大于任意第一走线束中相邻两条扇出走线的间距。
  2. 根据权利要求1所述的显示面板，其中，所述第二子束包括沿所述第二方向并列设置的第一走线簇和第二走线簇，所述第二走线簇相对于所述第一走线簇靠近所述第二走线组；
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第二走线簇的多条扇出走线的直线长度逐渐变长；所述扇出走线的直线长度为，所述扇出走线的引出段的两端点之间的直线距离，与所述扇出走线的延伸段的两端点之间的直线距离之和；
    所述第二走线簇的至少一条扇出走线具有曲线部分，和/或，所述第二走线簇的至少一条扇出走线具有加宽部分，所述加宽部分的线宽大于相应扇出走线中除所述加宽部分以外的其他部分的线宽。
  3. 根据权利要求2所述的显示面板，其中，所述第二走线簇包括沿所述第二方向并列设置的第一子簇和第二子簇，所述第二子簇相对于所述第一子簇靠近所述第二走线组；
    所述第一子簇的多条扇出走线具有曲线部分，和/或，所述第二子簇的多条扇出走线具有加宽部分。
  4. 根据权利要求3所述的显示面板，其中，沿所述第二方向且由所述第 一走线组指向所述第二走线组，所述第一子簇的多条扇出走线的曲线部分的直线长度逐渐变短；和/或，
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第二子簇的多条扇出走线的加宽部分的直线长度逐渐变长。
  5. 根据权利要求2～4中任一项所述的显示面板，其中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一走线簇的多条扇出走线的直线长度逐渐变短；
    所述第一走线簇的至少一条扇出走线具有曲线部分。
  6. 根据权利要求5所述的显示面板，其中，所述第一走线簇的多条扇出走线具有曲线部分；
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一走线簇的多条扇出走线的曲线部分的直线长度逐渐变长。
  7. 根据权利要求2～6中任一项所述的显示面板，其中，所述曲线部分设置在相应扇出走线的延伸段；和/或，
    所述曲线部分的线宽与相应扇出走线中除所述曲线部分以外的其他部分的线宽大致相等。
  8. 根据权利要求2～7中任一项所述的显示面板，其中，所述加宽部分设置在相应扇出走线的延伸段；和/或，
    所述加宽部分呈直线设置。
  9. 根据权利要求1～8中任一项所述的显示面板，其中，所述第二子束的多条扇出走线的电阻均在第一预设阻值范围内；和/或，
    所述第二子束中最靠近所述第二走线组的扇出走线，与所述第二走线组中最靠近所述第二子束的扇出走线的电阻之差在所述第一预设阻值范围内。
  10. 根据权利要求1～9中任一项所述的显示面板，所述显示面板还具有位于所述弯折区远离所述第一扇出区的一侧的第二扇出区；
    所述显示面板还包括设置于所述第二扇出区的多条第一连接线，所述第一连接线由所述第二扇出区靠近所述弯折区的一侧延伸至所述第二扇出区远离所述弯折区的一侧，且一条第一连接线与一条扇出走线电连接；
    沿所述第二方向，所述第一子束所连接的多条第一连接线，与所述第二子束所连接的多条第一连接线之间具有间距；
    由所述第二扇出区靠近所述弯折区的一侧至所述第二扇出区远离所述弯折区的一侧，所述第二子束所连接的多条第一连接线，逐渐向所述第一子束所连接的多条第一连接线靠拢。
  11. 根据权利要求1～10中任一项所述的显示面板，所述显示面板还包括位于所述弯折区远离所述第一扇出区一侧的第二扇出区；
    所述显示面板还包括至少设置于所述第二扇出区的多条第一连接线，所述第一连接线由所述第二扇出区靠近所述弯折区的一侧延伸至所述第二扇出区远离所述弯折区的一侧，且一条第一连接线与一条扇出走线电连接；
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述多个第一走线束中最远离所述第二走线组的第一走线束为目标第一走线束，所述目标第一走线束的多条扇出走线的直线长度逐渐变短；所述目标第一走线束包括第三子束和第四子束，所述第三子束相对于所述第四子束远离所述第二走线组；
    所述多条第一连接线中与所述第三子束的多条扇出走线连接的多条第一连接线形成第五子束，所述第五子束的第一连接线的延伸长度大于其直线长度；所述第一连接线的延伸长度为所述第一连接线的延伸路径的长度，所述第一连接线的直线长度为所述第一连接线的两端点之间的直线距离；
    所述第五子束的至少一条第一连接线具有折线部分，所述折线部分包括延伸方向不完全相同且依次连接的多个线段；和/或，所述第五子束的至少一条第一连接线具有曲线部分。
  12. 根据权利要求11所述的显示面板，其中，所述第五子束包括沿所述第二方向并列设置的第一连接线簇和第二连接线簇，所述第一连接线簇相对于所述第二连接线簇远离所述第二走线组；
    所述第一连接线簇和所述第二连接线簇的多条第一连接线具有第一折线部分；
    所述第一连接线簇的多条第一连接线还具有所述曲线部分。
  13. 根据权利要求12所述的显示面板，其中，所述显示面板还包括设置于所述第二扇出区远离所述弯折区一侧的测试电路，所述第一折线部分位于所述测试电路在所述第二方向上的一侧；
    所述第一折线部分包括依次相连的第一折线段、第二折线段和第三折线段，所述第一折线段和所述第三折线段大致沿所述第一方向延伸，所述第二折线段大致沿所述第二方向延伸；
    所述第一折线段相对于所述第三折线段远离所述第二走线组；所述第一折线段与相应的扇出走线电连接，所述第三折线段与所述测试电路电连接；
    所述第一连接线簇的第一折线部分至少部分围绕所述第二连接线簇的第一折线部分。
  14. 根据权利要求13所述的显示面板，其中，所述第一连接线簇的第一连接线的曲线部分，设置于相应的第一连接线的第一折线部分的第一折线段。
  15. 根据权利要求12～14中任一项所述的显示面板，其中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇和所述第二连接线簇的多条第一连接线的第一折线部分的直线长度逐渐变短；所述第一折线部分的直线长度为，所述第一折线部分的各线段的两端点之间的直线距离之和；和/或，
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇的多条第一连接线的曲线部分的直线长度逐渐变短。
  16. 根据权利要求12～15中任一项所述的显示面板，其中，所述第五子束还包括沿所述第二方向并列设置的第三连接线簇和第四连接线簇，所述第三连接线簇相对于所述第四连接线簇远离所述第二走线组；且所述第三连接线簇和所述第四连接线簇，相对于所述第一连接线簇和所第二连接线簇靠近所述第二走线组；
    所述第三连接线簇和所述第四连接线簇的多条第一连接线具有第二折线部分；
    所述第三连接线簇的多条第一连接线还具有所述曲线部分。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括设置于所述第二扇出区远离所述弯折区一侧的测试电路，所述第二折线部分位于所述测试电路靠近所述第二扇出区的一侧；
    所述第二折线部分包括依次相连的第四折线段和第五折线段，所述第四折线段大致沿所述第一方向延伸，所述第五折线段大致沿所述第二方向延伸；
    所述第四折线段与相应的扇出走线电连接，所述第五折线段与所述测试电路电连接；
    所述第三连接线簇的第二折线部分至少部分围绕所述第四连接线簇的第二折线部分。
  18. 根据权利要求17所述的显示面板，其中，所述第三连接线簇的第一连接线的曲线部分，设置于相应的第一连接线的第二折线部分的第四折线段。
  19. 根据权利要求16～18中任一项所述的显示面板，其中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第三连接线簇和所述第四连接线簇的多条第一连接线的第二折线部分的直线长度逐渐变短；所述第二折线部分的直线长度为，所述第二折线部分的各线段的两端点之间的直线距离之和；和/或，
    沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第三连接线簇的多条第一连接线的曲线部分的直线长度逐渐变短。
  20. 根据权利要求16～19中任一项所述的显示面板，其中，沿所述第二方向且由所述第一走线组指向所述第二走线组，所述第一连接线簇、所述第二连接线簇、所述第三连接线簇和所述第四连接线簇的多条第一连接线的延伸长度逐渐变短。
  21. 根据权利要求11～20中任一项所述的显示面板，其中，所述多条第一连接线中与所述第四子束的多条扇出走线连接的多条第一连接线形成第六子束，所述第六子束的每条第一连接线的延伸长度大致等于其直线长度。
  22. 根据权利要求11～21中任一项所述的显示面板，其中，最远离所述第二走线组的扇出走线，与其所连接的第一连接线的延伸长度之和为第一长度；
    所述第二走线组中最远离所述第一走线组的扇出走线，与其所连接的第一连接线的延伸长度之和为第二长度；
    所述第一长度与所述第二长度大致相等。
  23. 根据权利要求11～22中任一项所述的显示面板，其中，最远离所述第二走线组的扇出走线，与其所连接的第一连接线的电阻之和为第一电阻；
    所述第二走线组中最远离所述第一走线组的扇出走线，与其所连接的第一连接线的电阻之和为第二电阻；
    所述第一电阻与所述第二电阻大致相等。
  24. 根据权利要求1～23中任一项所述的显示面板，其中，沿所述第二方向且由所述第一走线组指向所述第二走线组，相邻两个第一走线束中的第一走线束的多条扇出走线的直线长度逐渐减小；
    所述相邻两个第一走线束中，相对远离所述第二走线组的第一走线束的至少一条扇出走线具有曲线部分；且，所述第一走线束中具有曲线部分的扇出走线相对于所述第一走线束中的其他扇出走线靠近所述第二走线组。
  25. 根据权利要求1～24中任一项所述的显示面板，其中，所述第二走线组包括沿第二方向并列设置的多个第二走线束；
    沿所述第二方向且由所述第二走线组指向所述第一走线组，相邻两个第二走线束中的第二走线束的多条扇出走线的直线长度逐渐减小；
    所述相邻两个的第二走线束中，相对远离所述第一走线组的第二走线束的至少一条扇出走线具有曲线部分；且，所述第二走线束中具有曲线部分的扇出走线相对于所述第二走线束中的其他扇出走线靠近所述第一走线组。
  26. 根据权利要求1～25中任一项所述的显示面板，所述显示面板具有位于所述弯折区远离所述第一扇出区的一侧的第二扇出区；所述显示面板包括至少设置于所述第二扇出区的多条第一连接线，所述第一连接线由所述第二扇出区靠近所述弯折区的一侧延伸至所述第二扇出区远离所述弯折区的一侧；
    所述显示面板还包括设置于所述弯折区的多条第二连接线，所述第二连接线由所述弯折区靠近所述第一扇出区的一侧延伸至所述弯折区靠近所述第二扇出区的一侧；
    一条所述扇出走线、一条所述第二连接线和一条所述第一连接线依次电连接。
  27. 根据权利要求26所述的显示面板，所述显示面板还包括：
    衬底；
    设置于所述衬底上的第一栅导电层；
    设置于所述第一栅导电层远离所述衬底一侧的第二栅导电层；
    设置于所述第二栅导电层远离所述衬底一侧的源漏导电层；
    其中，所述多条扇出走线中的一部分扇出走线设置于所述第一栅导电层中，另一部分扇出走线设置于所述第二栅导电层中；
    所述多条第一连接线中的一部分第一连接线设置于所述第一栅导电层中，另一部分第一连接线设置于所述第二栅导电层中；
    所述多条第二连接线设置于所述源漏导电层中。
  28. 根据权利要求1～27中任一项所述的显示面板，其中，所述显示区大致呈矩形，所述显示区的靠近所述第一扇出区的两个拐角为弧形拐角；
    所述两个拐角分别为第一拐角和第二拐角，所述第一拐角和所述第一走线组位于参考线的一侧，所述第二拐角和所述第二走线组位于所述参考线的另一侧；所述参考线为沿所述第一方向且过所述显示区的直线；
    所述第一拐角的弧度小于所述第二拐角的弧度。
  29. 一种显示装置，包括：
    第一显示面板，所述第一显示面板为如权利要求1～28中任一项所述的显示面板。
  30. 根据权利要求29所述的显示装置，还包括：
    第二显示面板；
    转轴，设置于所述第二显示面板的背侧，所述第二显示面板可沿所述转轴折叠；
    其中，所述第一显示面板设置于所述第二显示面板的背侧，且位于所述转轴的一侧；所述第一显示面板和所述第二显示面板的出光方向相背。
PCT/CN2022/076859 2022-02-18 2022-02-18 一种显示面板及显示装置 WO2023155140A1 (zh)

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US20120169578A1 (en) * 2010-12-29 2012-07-05 Chang-Sin Kim Display Panel and Display Apparatus Having the Same
CN109634003A (zh) * 2019-02-21 2019-04-16 厦门天马微电子有限公司 一种显示面板及显示装置
CN111564111A (zh) * 2020-05-29 2020-08-21 上海中航光电子有限公司 一种显示面板和显示装置
CN112768495A (zh) * 2021-01-06 2021-05-07 京东方科技集团股份有限公司 显示基板、显示装置
CN215451419U (zh) * 2021-02-22 2022-01-07 京东方科技集团股份有限公司 显示基板和显示装置

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CN1928676A (zh) * 2005-11-14 2007-03-14 友达光电股份有限公司 电子连接器及其连接方法及电子模块
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US20120169578A1 (en) * 2010-12-29 2012-07-05 Chang-Sin Kim Display Panel and Display Apparatus Having the Same
CN109634003A (zh) * 2019-02-21 2019-04-16 厦门天马微电子有限公司 一种显示面板及显示装置
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