WO2023145316A1 - 半導体装置および半導体モジュール - Google Patents

半導体装置および半導体モジュール Download PDF

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Publication number
WO2023145316A1
WO2023145316A1 PCT/JP2022/047072 JP2022047072W WO2023145316A1 WO 2023145316 A1 WO2023145316 A1 WO 2023145316A1 JP 2022047072 W JP2022047072 W JP 2022047072W WO 2023145316 A1 WO2023145316 A1 WO 2023145316A1
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Prior art keywords
transistor
wiring
electrode
clamping
layer
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PCT/JP2022/047072
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English (en)
French (fr)
Japanese (ja)
Inventor
勲 田古部
浩隆 大嶽
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202280089935.4A priority Critical patent/CN118591889A/zh
Priority to DE112022006551.6T priority patent/DE112022006551T5/de
Priority to JP2023576699A priority patent/JPWO2023145316A1/ja
Publication of WO2023145316A1 publication Critical patent/WO2023145316A1/ja
Priority to US18/782,942 priority patent/US20240379835A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
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    • H10D30/00—Field-effect transistors [FET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D30/80—FETs having rectifying junction gate electrodes
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices and semiconductor modules.
  • a discrete semiconductor device in which a GaN transistor is formed is generally known (see Patent Document 1, for example).
  • a semiconductor device includes a semiconductor substrate, a GaN transistor formed on the semiconductor substrate and including a drain electrode, a source electrode, and a gate electrode; an active clamp circuit including a clamping transistor that is electrically connected and operates based on the rise of the drain-source voltage of the GaN transistor; a drain pad electrically connected to the drain electrode of the GaN transistor; A source pad electrically connected to the source electrode of the GaN transistor, and a gate pad electrically connected to the gate electrode of the GaN transistor.
  • a semiconductor module includes: the semiconductor device; a sealing resin that seals the semiconductor device; a drain terminal exposed from the sealing resin and electrically connected to the drain pad; A source terminal exposed from the sealing resin and electrically connected to the source pad, and a gate terminal exposed from the sealing resin and electrically connected to the gate pad are provided.
  • the above semiconductor device and semiconductor module it is possible to suppress the erroneous turn-on of the GaN transistor when the voltage between the drain and the source of the GaN transistor abruptly changes.
  • FIG. 1 is a schematic plan view of the semiconductor device of the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of part of the semiconductor device cut along line F2-F2 in FIG.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device cut along line F3-F3 in FIG.
  • FIG. 4 is a schematic plan view enlarging a portion of the semiconductor device of FIG. 1 where an active clamp circuit is formed.
  • FIG. 5 is a schematic cross-sectional view of part of the semiconductor device cut along line F5-F5 in FIG.
  • FIG. 6 is a circuit diagram of the semiconductor device of FIG.
  • FIG. 7 is a schematic plan view of the semiconductor module of the first embodiment.
  • FIG. 1 is a schematic plan view of the semiconductor device of the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of part of the semiconductor device cut along line F2-F2 in FIG.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device cut along line F3-
  • FIG. 8 is a schematic cross-sectional view of the semiconductor module cut along line F8-F8 in FIG.
  • FIG. 9 is a graph showing changes in drain-source voltage, gate-source voltage, and gate-source voltage of the clamp transistor of the active clamp circuit of the GaN transistor.
  • FIG. 10 is a schematic plan view showing the internal structure of the semiconductor module of the second embodiment.
  • 11 is a schematic plan view mainly showing the wiring structure of the semiconductor module of FIG. 10.
  • FIG. FIG. 12 is a schematic plan view of a semiconductor module.
  • 13 is a schematic cross-sectional view of the semiconductor module cut along line F13-F13 in FIG. 12.
  • FIG. 14 is a schematic cross-sectional view of the semiconductor module cut along line F14-F14 in FIG. 12.
  • FIG. 12 is a schematic plan view showing the internal structure of the semiconductor module of the second embodiment.
  • 11 is a schematic plan view mainly showing the wiring structure of the semiconductor module of FIG. 10.
  • FIG. 12 is a schematic plan view of a
  • FIG. 15 is a circuit diagram of the semiconductor module of FIG. 12.
  • FIG. FIG. 16 is a schematic cross-sectional view of a pull-down resistor of an active clamp circuit in a modified semiconductor device.
  • FIG. 17 is a schematic cross-sectional view of a pull-down resistor in a modified semiconductor device.
  • FIG. 18 is a circuit diagram of a semiconductor device of a modification. 19 is a schematic plan view enlarging a portion of the semiconductor device of FIG. 18 in which an active clamp circuit is formed.
  • FIG. 20 is a circuit diagram of a semiconductor device of a modification. 21 is a schematic plan view enlarging a portion of the semiconductor device of FIG. 20 where the active clamp circuit is formed.
  • FIG. 22 is a circuit diagram of a semiconductor device of a modification. 23 is an enlarged schematic plan view of a portion of the semiconductor device of FIG. 22 where the active clamp circuit is formed.
  • FIG. 24 is a schematic plan view of a semiconductor module of a modification.
  • FIG. 1 schematically shows a schematic planar structure of a semiconductor device.
  • the semiconductor device 10 includes a semiconductor substrate 11 , a GaN transistor 20 and an active clamp circuit 30 electrically connected to the GaN transistor 20 . Both GaN transistor 20 and active clamp circuit 30 are formed on semiconductor substrate 11 . GaN transistor 20 and active clamp circuit 30 are connected by a wiring layer 40 (see FIG. 3) formed on semiconductor substrate 11 .
  • the semiconductor device 10 is a semiconductor chip on which both the GaN transistor 20 and the active clamp circuit 30 are provided.
  • the thickness direction of the semiconductor substrate 11 is defined as the z-direction, and two directions orthogonal to the z-direction are defined as the x-direction and the y-direction. Also, viewing the semiconductor device 10 from the z-direction is referred to as "plan view”.
  • the semiconductor substrate 11 is formed in a rectangular flat plate shape having a longitudinal direction and a lateral direction in plan view.
  • the lateral direction of the semiconductor substrate 11 is the x direction
  • the longitudinal direction is the y direction.
  • Semiconductor substrate 11 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate material.
  • semiconductor substrate 11 may be a Si substrate.
  • the thickness of semiconductor substrate 11 is, for example, 200 ⁇ m or more and 1500 ⁇ m or less.
  • the length in the longitudinal direction (length in the y direction) of semiconductor substrate 11 is, for example, 2 mm
  • the length in the width direction (length in x direction) of semiconductor substrate 11 is, for example, 4 mm.
  • the semiconductor substrate 11 includes a substrate front surface 11s and a substrate rear surface 11r (both of which are shown in FIG. 2) facing opposite sides in the z-direction.
  • the semiconductor substrate 11 has a first side surface 11a and a second side surface 11b forming side surfaces at both ends in the longitudinal direction (y direction), and third side surfaces 11c and 11c forming side surfaces at both ends in the width direction (x direction). and a fourth side surface 11d.
  • the GaN transistor 20 and the active clamp circuit 30 are formed on the semiconductor substrate 11 side by side in the longitudinal direction (y direction) of the semiconductor substrate 11 .
  • the active clamp circuit 30 is arranged closer to the second side surface 11b with respect to the GaN transistor 20 .
  • the GaN transistor 20 is a high electron mobility transistor (HEMT) using a nitride semiconductor.
  • GaN transistor 20 includes an active region 20T in which the transistor is formed.
  • the active region 20T is formed in a rectangular shape with the y direction as the longitudinal direction and the x direction as the lateral direction.
  • the longitudinal direction of the semiconductor substrate 11 is the y direction and the lateral direction is the x direction in plan view.
  • the short-side direction of 20T and the short-side direction of semiconductor substrate 11 match.
  • the first area of the region where the GaN transistor 20 is formed in the semiconductor substrate 11 is larger than the second area of the region where the active clamp circuit 30 is formed.
  • the first area is greater than twice the second area.
  • the first area is greater than three times the second area.
  • the first area is greater than four times the second area.
  • the first area is greater than five times the second area.
  • the first area is less than or equal to six times the second area.
  • the region of the semiconductor substrate 11 in which the GaN transistor 20 is formed can be defined by the region consisting of the y-direction range and the entire x-direction of the active region 20T in the GaN transistor 20 of the semiconductor substrate 11 in plan view.
  • the region where the active clamp circuit 30 is formed can be defined by the region consisting of the entire region in the x direction between the active region 20T and the second side surface 11b of the semiconductor substrate 11 in plan view.
  • the semiconductor device 10 includes a drain pad 51, a main source pad 52, a sense source pad 53, and a gate pad 54 as electrode pads constituting external electrodes.
  • These pads 51 to 54 are formed in the region where the GaN transistor 20 is formed and exposed to the outside of the semiconductor device 10.
  • FIG. These pads 51-54 are electrically connected to both the GaN transistor 20 and the active clamp circuit 30 via the wiring layer 40 (see FIG. 3).
  • Each of pads 51-54 is made of any conductor material including at least one of copper (Cu), aluminum (Al), AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN). be able to.
  • GaN transistor 20 shown in FIG. 3 includes gate electrode 26 , source electrode 28 and drain electrode 29 .
  • drain pad 51 is electrically connected to drain electrode 29 of GaN transistor 20 .
  • Both main source pad 52 and sense source pad 53 are electrically connected to source electrode 28 of GaN transistor 20 .
  • the main source pad 52 corresponds to the "source pad”.
  • Gate pad 54 is electrically connected to gate electrode 26 of GaN transistor 20 .
  • the drain pad 51 is arranged at a position closer to the third side surface 11c than the center of the semiconductor substrate 11 in the x direction in plan view. In this embodiment, the drain pad 51 is arranged closer to the third side surface 11c than the active region 20T in plan view. The drain pad 51 is formed from the end of the semiconductor substrate 11 closer to the first side surface 11a to the vicinity of the active clamp circuit 30 in the y direction.
  • the main source pad 52, the sense source pad 53, and the gate pad 54 are arranged at positions closer to the fourth side surface 11d than the center of the semiconductor substrate 11 in the x direction in plan view.
  • each of the pads 52 to 54 is arranged closer to the fourth side surface 11d than the active region 20T in plan view.
  • Each pad 52-54 is arranged in a row along the y direction.
  • the gate pad 54, the sense source pad 53, and the main source pad 52 are arranged in this order from the first side surface 11a toward the second side surface 11b.
  • the area of main source pad 52 is larger than the areas of sense source pad 53 and gate pad 54 .
  • the shape and arrangement of the pads 51 to 54 can be changed arbitrarily.
  • FIG. 2 is a cross-sectional view showing an example of a schematic cross-sectional structure of a GaN transistor 20 obtained by cutting the semiconductor device 10 along the F2-F2 cross-sectional indication line of FIG. It should be noted that some hatching lines are omitted from the viewpoint of visibility of the drawing.
  • the GaN transistor 20 is formed on the semiconductor substrate 11.
  • the GaN transistor 20 includes a buffer layer 21 formed on a semiconductor substrate 11 , an electron transit layer 22 forming a main drift layer formed on the buffer layer 21 , and an electron supply layer formed on the electron transit layer 22 . 23 and
  • the buffer layer 21 is located between the semiconductor substrate 11 and the electron transit layer 22 and is made of any material that can alleviate the lattice mismatch between the semiconductor substrate 11 and the electron transit layer 22 .
  • Buffer layer 21 includes one or more nitride semiconductor layers.
  • Buffer layer 21 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and graded AlGaN layers having different aluminum compositions.
  • the buffer layer 21 may be formed by a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. may be configured.
  • buffer layer 21 includes a first buffer layer that is an AlN layer formed on semiconductor substrate 11 and a second buffer layer that is an AlGaN layer formed on the AlN layer.
  • the first buffer layer is, for example, an AlN layer having a thickness of 200 nm
  • the second buffer layer has, for example, a structure in which a plurality of AlGaN layers are laminated.
  • an impurity may be introduced into a part of the buffer layer 21 to make it semi-insulating.
  • the impurity is carbon (C) or iron (Fe), for example, and the impurity concentration can be, for example, 4 ⁇ 10 16 cm ⁇ 3 or more.
  • the electron transit layer 22 is made of a nitride semiconductor, such as a GaN layer.
  • the thickness of the electron transit layer 22 is, for example, 300 nm or more and 2 ⁇ m or less, more preferably 300 nm or more and 400 nm or less. In one example, the thickness of the electron transit layer 22 is 350 nm.
  • an impurity may be introduced into a part of the electron transit layer 22 so that the electron transit layer 22 other than the surface layer region is semi-insulating.
  • the impurity is C, for example, and the concentration of the impurity can be, for example, 1 ⁇ 10 19 cm ⁇ 3 or higher in peak concentration.
  • the electron transit layer 22 can include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer.
  • the C concentration in the C-doped GaN layer can be 9 ⁇ 10 18 cm ⁇ 3 or more and 9 ⁇ 10 19 cm ⁇ 3 or less.
  • the electron supply layer 23 is made of a nitride semiconductor having a bandgap larger than that of the electron transit layer 22, such as an AlGaN layer. Since the bandgap increases as the Al composition increases, the electron supply layer 23, which is an AlGaN layer, has a larger bandgap than the electron transit layer 22, which is a GaN layer.
  • the electron supply layer 23 has a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the electron supply layer 23 has a thickness of 8 nm or more and 15 nm or less.
  • the electron transit layer 22 and the electron supply layer 23 are composed of nitride semiconductors having lattice constants different from each other.
  • the lattice-mismatched junction between the electron transit layer 22 and the electron supply layer 23 gives strain to the electron supply layer 23 , and this strain induces a two-dimensional electron gas (2DEG) 24 in the electron transit layer 22 .
  • the 2DEG 24 spreads in the electron transit layer 22 at a position close to the heterojunction interface between the electron transit layer 22 and the electron supply layer 23 (for example, a distance of several nanometers from the interface). This 2DEG 24 functions as a current path (channel) of the GaN transistor 20 .
  • the GaN transistor 20 includes a gate layer 25 formed partially on the electron supply layer 23, a gate electrode 26 formed on the gate layer 25, a passivation layer 27, a source electrode 28, a drain electrode 29, further includes
  • the passivation layer 27 covers the electron supply layer 23, the gate layer 25, and the gate electrode 26, and has a first opening 27A and a second opening 27B.
  • the passivation layer 27 corresponds to "an insulating layer formed on a semiconductor substrate".
  • the source electrode 28 is in contact with the electron supply layer 23 through the first opening 27A.
  • the drain electrode 29 is in contact with the electron supply layer 23 through the second opening 27B.
  • the gate layer 25 is made of a nitride semiconductor containing acceptor-type impurities.
  • the gate layer 25 is made of any material having a smaller bandgap than the electron supply layer 23, eg an AlGaN layer.
  • the gate layer 25 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities.
  • Acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C.
  • the maximum concentration of acceptor-type impurities in gate layer 25 is, for example, 7 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the GaN transistor 20 depletes the 2DEG 24 in the region immediately below the gate layer 25 by including the gate layer 25 made of a nitride semiconductor containing acceptor-type impurities. This allows the GaN transistor 20 to operate normally off. That is, the GaN transistor 20 is a normally-off transistor.
  • Gate layer 25 includes a bottom surface 25r in contact with electron supply layer 23 and a top surface 25s opposite bottom surface 25r. Gate electrode 26 is formed on upper surface 25 s of gate layer 25 .
  • the gate layer 25 includes a ridge portion 25C including an upper surface 25s on which the gate electrode 26 is formed, and two extension portions (a first extension portion 25A and a second extension portion 25A) extending outside the ridge portion 25C in plan view. 2 extensions 25B).
  • the first extending portion 25A extends from the ridge portion 25C toward the first opening 27A in plan view.
  • the first extending portion 25A is separated from the first opening 27A.
  • the second extending portion 25B extends from the ridge portion 25C toward the second opening 27B in plan view.
  • the second extending portion 25B is separated from the second opening 27B.
  • the ridge portion 25C is located between the first extension portion 25A and the second extension portion 25B and formed integrally with the first extension portion 25A and the second extension portion 25B. Due to the existence of the first extending portion 25A and the second extending portion 25B, the bottom surface 25r of the gate layer 25 has a larger area than the top surface 25s. In the present embodiment, the second extension portion 25B extends longer toward the outside of the ridge portion 25C in plan view than the first extension portion 25A.
  • the ridge portion 25C corresponds to a relatively thick portion of the gate layer 25 and has a thickness of 80 nm or more and 150 nm or less, for example.
  • the thickness of the gate layer 25, particularly the ridge portion 25C, can be determined in consideration of parameters including the gate threshold voltage.
  • gate layer 25 (ridge portion 25C) has a thickness greater than 110 nm.
  • Each of the first extension portion 25A and the second extension portion 25B has a thickness smaller than the thickness of the ridge portion 25C. In one example, each of the first extension portion 25A and the second extension portion 25B has a thickness equal to or less than half the thickness of the ridge portion 25C.
  • each of the extensions 25A, 25B is a flat portion with a substantially constant thickness.
  • substantially constant thickness means that the thickness is within a manufacturing variation (for example, 20%).
  • each extension 25A, 25B may include a tapered portion in a region adjacent to the ridge 25C having a thickness that tapers away from the ridge 25C.
  • Each extending portion 25A, 25B may include a flat portion having a substantially constant thickness in a region more than a predetermined distance away from the ridge portion 25C.
  • the flat portion has a thickness of 5 nm or more and 25 nm or less.
  • the gate electrode 26 formed on the ridge portion 25C is composed of one or more metal layers.
  • An example of a metal layer is a TiN layer.
  • the gate electrode 26 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer.
  • the thickness of gate electrode 26 is, for example, 50 nm or more and 200 nm or less.
  • Gate electrode 26 can form a Schottky junction with gate layer 25 .
  • Each of the first opening 27A and the second opening 27B of the passivation layer 27 is separated from the gate layer 25, and the gate layer 25 is located between the first opening 27A and the second opening 27B. More specifically, the gate layer 25 is located between the first opening 27A and the second opening 27B and closer to the first opening 27A than the second opening 27B.
  • Passivation layer 27 extends along the top surface of electron supply layer 23, the side surfaces and top surface 25s of gate layer 25, and the side surfaces and top surface of gate electrode 26, and thus has a non-flat surface.
  • the source electrode 28 and the drain electrode 29 are composed of one or more metal layers.
  • the metal layer is composed of any combination of, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.
  • At least part of the source electrode 28 is filled in the first opening 27A.
  • At least part of the drain electrode 29 is filled in the second opening 27B.
  • the source electrode 28 is in ohmic contact with the 2DEG 24 immediately below the electron supply layer 23 through the first opening 27A.
  • the drain electrode 29 is in ohmic contact with the 2DEG 24 immediately below the electron supply layer 23 through the second opening 27B.
  • the source electrode 28 includes a source contact portion 28A filled in the first opening 27A and a source field plate portion 28B covering the passivation layer 27.
  • the source field plate portion 28B is formed integrally with the source contact portion 28A.
  • the source field plate portion 28B includes an end portion 28C positioned between the second opening 27B and the gate layer 25 in plan view.
  • Source field plate portion 28B extends from source contact portion 28A to end portion 28C along the surface of passivation layer 27 toward drain electrode 29, but is separated from drain electrode 29. As shown in FIG.
  • Source field plate portion 28B extends along the non-planar surface of passivation layer 27 and thus has a non-planar surface as well.
  • the source field plate portion 28B has a function of alleviating electric field concentration in the vicinity of the edge of the gate electrode 26 when a drain voltage is applied to the drain electrode 29 during zero bias when no gate voltage is applied to the gate electrode 26.
  • FIG. 3 is an enlarged cross-sectional view of mainly the wiring layer 40 and its periphery in the schematic cross-sectional structure of the semiconductor device 10 cut along the F3-F3 cross-sectional indication line of FIG.
  • the connection relationship of the wiring layer 40 is the main part, so the cross-sectional structure of the GaN transistor 20 is simplified compared to the cross-sectional structure of the GaN transistor 20 of FIG.
  • the GaN transistor 20 is provided with a multilayer wiring structure LS.
  • the multilayer wiring structure LS includes, for example, a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4 in order from the top.
  • the multilayer wiring structure LS may further include one or more wiring layers under the fourth wiring layer L4.
  • the first wiring layer L1 corresponds to the "front side wiring layer”
  • the second wiring layer L2 and the third wiring layer L3 correspond to the "middle wiring layer”
  • the fourth wiring layer L4 corresponds to "substrate-side wiring layer".
  • the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 are provided closer to the semiconductor substrate 11 (see FIG. 2) than the first wiring layer L1. It can be said that the fourth wiring layer L4 is provided on the side opposite to the first wiring layer L1 with respect to the second wiring layer L2 and the third wiring layer L3.
  • the first to third wiring layers L1 to L3 are formed on the GaN transistor 20.
  • the fourth wiring layer L4 is formed at a position aligned with the GaN transistor 20 in the z direction. In other words, the GaN transistor 20 is formed on the fourth wiring layer L4.
  • the semiconductor device 10 includes a first insulating layer 12 covering the first wiring layer L1, a second insulating layer 13 covering the second wiring layer L2, a third insulating layer 14 covering the third wiring layer L3, and a third wiring. and a fourth insulating layer 15 provided between the layer L3 and the fourth wiring layer L4.
  • These insulating layers 12 to 15 are made of a material containing silicon oxide (SiO 2 ), silicon nitride (SiN), or the like.
  • a drain pad 51, a main source pad 52, a sense source pad 53, and a gate pad 54 are formed in the first wiring layer L1, which is the uppermost layer of the multilayer wiring structure LS.
  • Each pad 51 to 54 is insulated from each other by the first insulating layer 12 .
  • Each pad 51 - 54 may be at least partially covered by the first insulating layer 12 , and a portion of the top surface of each pad 51 - 54 is exposed through an opening formed in the first insulating layer 12 .
  • the wiring layer 40 includes drain wiring 41 , main source wiring 42 , sense source wiring 43 and gate wiring 44 .
  • the drain wiring 41 is configured to electrically connect the drain pad 51 and the drain electrode 29 of the GaN transistor 20 .
  • Main source wiring 42 is configured to electrically connect main source pad 52 and source electrode 28 of GaN transistor 20 .
  • Sense source wiring 43 is configured to electrically connect sense source pad 53 (see FIG. 1) and source electrode 28 of GaN transistor 20 .
  • the gate wiring 44 is configured to electrically connect the gate pad 54 (see FIG. 1) and the gate electrode 26 of the GaN transistor 20 .
  • the wirings 41 to 44 are formed over the second wiring layer L2 and the third wiring layer L3. Each wiring 41 to 44 is insulated from each other by the second insulating layer 13 and the third insulating layer 14 .
  • Each of the wirings 41 to 44 includes a first wiring portion formed in the second wiring layer L2, a first via extending in the z-direction in the second insulating layer 13, and a second wiring portion formed in the third wiring layer L3. and a second via extending in the z-direction in the third wiring layer L3.
  • the first via is provided on the first wiring portion and exposed from the first wiring layer L1. Therefore, the first vias of the wirings 41 to 44 connect the pads 51 to 54 corresponding to the wirings 41 to 44 and the first wiring section.
  • the second via is provided on the second wiring portion and connected to the first wiring portion.
  • the second via connects the first wiring portion and the second wiring portion.
  • a second via of each wiring 41-44 is connected to each electrode 26, 28, 29 corresponding to each wiring 41-44.
  • Each of the wirings 41-44 can be made of any conductor material including at least one of Cu, Al, AlCu alloy, W, Ti, and TiN.
  • FIG. 4 is an enlarged view of the active clamp circuit 30 of FIG. 1 and its periphery.
  • the wiring of the active clamp circuit 30 and the like are indicated by solid lines.
  • the active clamp circuit 30 includes a clamp transistor 60, a clamp capacitor 31, and a pull-down resistor 32. Active clamp circuit 30 is electrically connected to GaN transistor 20 .
  • the clamping transistor 60 is electrically connected to the GaN transistor 20 . Both the GaN transistor 20 and the clamping transistor 60 are formed side by side in the longitudinal direction (y-direction) of the semiconductor substrate 11 . The clamping transistor 60 is formed closer to the second side surface 11b than the GaN transistor 20 in the y direction.
  • the clamping transistor 60 includes an active region 60T in which a transistor is formed.
  • the active area 60T is a rectangular area having a longitudinal direction and a lateral direction.
  • the active region 60T is formed in a rectangular shape with the x direction being the longitudinal direction and the y direction being the lateral direction.
  • the longitudinal direction of the semiconductor substrate 11 is the y direction
  • the lateral direction is the x direction. Therefore, the longitudinal direction of active region 60T and the longitudinal direction of active region 20T of GaN transistor 20 are perpendicular to each other.
  • the length of the active region 60T in the x direction is longer than the length of the active region 20T of the GaN transistor 20 in the x direction.
  • Each of the x-direction length and the y-direction length of the active region 60T can be changed arbitrarily.
  • FIG. 5 shows a schematic cross-sectional structure of the clamping transistor 60, the clamping capacitor 31, and the pull-down resistor 32 obtained by cutting the semiconductor device 10 along the F5-F5 cross-sectional indication line in FIG.
  • FIG. 5 mainly shows the positions of the clamping transistor 60, the clamping capacitor 31, and the pull-down resistor 32 in the z-direction, and the connection relationship between the clamping transistor 60, the clamping capacitor 31, and the pull-down resistor 32.
  • FIG. Therefore, the cross-sectional structure of the clamping transistor 60 is simplified compared to the cross-sectional structure of the GaN transistor 20 in FIG.
  • the cross-sectional structure of the pull-down resistor 32 in FIG. 5 is simplified compared to the actual cross-sectional structure of the pull-down resistor 32 taken along line F5-F5 in FIG.
  • the clamp transistor 60 has the same configuration as the GaN transistor 20.
  • the clamp transistor 60 includes a buffer layer 21 (see FIG. 2), an electron transit layer 22, an electron supply layer 23, and a passivation layer 27.
  • FIG. Therefore, it can be said that the clamping transistor 60 includes a sub-drift layer (electron transit layer 22 ) made of the same material as the electron transit layer 22 forming the main drift layer of the GaN transistor 20 .
  • the passivation layer 27 includes third and fourth openings that expose the electron supply layer 23 .
  • the clamping transistor 60 has a gate layer 25 formed on the electron supply layer 23 .
  • Each of the third and fourth openings in passivation layer 27 is separated from gate layer 25 of clamping transistor 60, and gate layer 25 is located between the third and fourth openings. Since the clamping transistor 60 includes the gate layer 25 made of a nitride semiconductor containing acceptor-type impurities, the clamping transistor 60 is capable of normally-off operation like the GaN transistor 20 . That is, the clamp transistor 60 is a normally-off transistor.
  • the clamp transistor 60 is provided at a position aligned with the GaN transistor 20 (see FIG. 1) in the z direction.
  • the clamp transistor 60 is formed in the fourth wiring layer L4.
  • clamping transistor 60 is formed on semiconductor substrate 11 . Therefore, the clamping transistor 60 and the GaN transistor 20 can be manufactured simultaneously in a common manufacturing process.
  • the clamping transistor 60 includes a drain electrode 61 , a source electrode 62 and a gate electrode 63 . These electrodes 61-63 are made of the same material as the gate electrode 26, the source electrode 28 and the drain electrode 29 of the GaN transistor 20, for example.
  • At least part of the source electrode 62 is filled in the third opening.
  • the source electrode 62 is in ohmic contact with the 2DEG 24 (see FIG. 2) immediately below the electron supply layer 23 through the third opening.
  • At least part of the drain electrode 61 is filled in the fourth opening.
  • the drain electrode 61 is in ohmic contact with the 2DEG 24 directly below the electron supply layer 23 through the fourth opening.
  • the drain electrode 61 and the source electrode 62 are arranged apart from each other.
  • the gate electrode 63 is arranged between the drain electrode 61 and the source electrode 62 . Although not shown, the gate electrode 63 is formed on the gate layer 25 (see FIG. 2). Gate electrode 63 is covered with passivation layer 27 .
  • the shape and arrangement of the drain electrode 61 , source electrode 62 and gate electrode 63 are the same as the shape and arrangement of the drain electrode 29 , source electrode 28 and gate electrode 26 of the GaN transistor 20 .
  • the shape and arrangement of the drain electrode 61, the source electrode 62, and the gate electrode 63 can be arbitrarily changed. can be different.
  • both the clamping capacitor 31 and the pull-down resistor 32 are formed in a region of the semiconductor substrate 11 different from that of the GaN transistor 20 and the clamping transistor 60 in plan view. More specifically, in plan view, both the clamping capacitor 31 and the pull-down resistor 32 are closer to the third side surface 11c than the clamping transistor 60 in the x direction and closer to the second side surface 11b than the drain pad 51 in the y direction. is formed in the area of When viewed from the longitudinal direction (y direction) of the active region 20T of the GaN transistor 20, both the clamping capacitor 31 and the pull-down resistor 32 are aligned with the drain pad 51 in the lateral direction (x direction) of the active region 20T of the GaN transistor 20. formed in overlapping positions.
  • the clamping capacitor 31 and the pull-down resistor 32 are arranged side by side in the y direction in plan view.
  • the clamping capacitor 31 is formed closer to the drain pad 51 than the pull-down resistor 32 is.
  • the pull-down resistor 32 is formed at the same position as the clamping transistor 60 in the y direction. Therefore, the clamping capacitor 31 is formed closer to the GaN transistor 20 than the clamping transistor 60 in the y direction.
  • the clamping capacitor 31 includes a first electrode 31P and a second electrode 31Q. Both the first electrode 31P and the second electrode 31Q are configured by a plurality of wirings.
  • the first electrode 31P includes a plurality of (two in this embodiment) first wirings extending in the y direction and second wirings extending in the x direction.
  • the two first wirings are arranged apart from each other in the x direction.
  • the second wiring connects the ends of the two first wirings near the first side surface 11a (see FIG. 1) in the x direction.
  • the second electrode 31Q includes a plurality of (two in this embodiment) third wirings extending in the y direction and fourth wirings extending in the x direction.
  • the two third wirings are arranged apart from each other in the x direction.
  • the third wiring is arranged so as to face the first wiring of the first electrode 31P in the x direction.
  • the first wirings and the third wirings are alternately arranged in the x direction.
  • the fourth wiring is arranged closer to the second side surface 11b than the second wiring of the first electrode 31P in the y direction.
  • the fourth wiring connects the ends of the two third wirings closer to the second side surface 11b in the x direction.
  • the clamping capacitor 31 is formed on the passivation layer 27. As shown in FIG. It can also be said that the first electrode 31P and the second electrode 31Q of the clamping capacitor 31 are formed on the passivation layer 27 .
  • the clamping capacitor 31 is formed in the fourth wiring layer L4. In other words, the clamping capacitor 31 is provided at a position aligned with the clamping transistor 60 and the GaN transistor 20 in the z-direction.
  • the electron supply layer 23 is not formed in the region where the clamping capacitor 31 is formed. That is, the passivation layer 27 is formed on the electron transit layer 22 .
  • the clamping capacitor 31 is electrically insulated from the electron transit layer 22 by the passivation layer 27 .
  • Insulating layer 33 is formed on the passivation layer 27 .
  • Insulating layer 33 is made of a material containing SiO 2 , for example.
  • the insulating layer 33 is arranged between the first electrode 31P and the second electrode 31Q.
  • the insulating layer 33 is interposed between the first electrode 31P and the second electrode 31Q. More specifically, the insulating layer 33 is arranged between the first wiring of the first electrode 31P and the third wiring of the second electrode 31Q in the x direction.
  • the thickness of insulating layer 33 is, for example, about 1 ⁇ m.
  • the insulating layer 33 corresponds to a "dielectric layer".
  • the pull-down resistor 32 includes a bellows-shaped connection path 32A.
  • 32 A of connection paths are comprised by 2DEG24 (refer FIG. 2).
  • the 2DEG 24 of the pull-down resistor 32 is formed in a bellows shape in plan view. Therefore, the connection path 32A includes a meandering portion 32B formed in a bellows shape.
  • pull-down resistor 32 includes the resistance component of meandering portion 32B.
  • the resistance component of meandering portion 32B is set according to the length and width of meandering portion 32B. Each of the length and width of meandering portion 32B is set according to the desired resistance value of pull-down resistor 32, for example.
  • the pull-down resistor 32 includes a first terminal 32P and a second terminal 32Q that form both ends of the connection path 32A.
  • the first terminal 32P is electrically connected to the end of the meandering portion 32B near the clamping capacitor 31 .
  • the second terminal 32Q is electrically connected to the end of the meandering portion 32B near the clamping transistor 60 .
  • the first terminal 32P and the second terminal 32Q are electrically connected to each other via the connection path 32A.
  • the first terminal 32P and the second terminal 32Q of the pull-down resistor 32 are provided on the electron supply layer 23. More specifically, the first terminal 32P and the second terminal 32Q are formed on the electron supply layer 23 and are in ohmic contact with the 2DEG 24 (see FIG. 2) immediately below the electron supply layer 23 .
  • the wiring layer 40 has a clamping drain wiring 45 , a clamping source wiring 46 and a clamping gate wiring 47 .
  • the clamping drain wiring 45 is electrically connected to each of the plurality of drain electrodes 61 of the clamping transistor 60 .
  • the drain wiring 45 for clamping is formed in the third wiring layer L3. 1 and 4, for convenience, the clamping drain wiring 45 is arranged closer to the first side surface 11a of the semiconductor substrate 11 than the active region 60T.
  • the drain wiring 45 for clamping is formed in a belt shape with the x direction as the longitudinal direction. This clamping drain wiring 45 indicates a portion that joins a plurality of clamping drain wirings 45 (see FIG. 5) formed on the active region 60T.
  • the clamping source wiring 46 is electrically connected to each of the plurality of source electrodes 62 of the clamping transistor 60 .
  • the clamping source wiring 46 is formed in the third wiring layer L3. 1 and 4, for the sake of convenience, the clamping source wiring 46 is arranged closer to the second side surface 11b of the semiconductor substrate 11 than the active region 60T.
  • the clamping source wiring 46 is formed in a strip shape whose longitudinal direction is the x direction in plan view. This clamping source wiring 46 indicates a portion that joins a plurality of clamping source wirings 46 (see FIG. 5) formed on the active region 60T.
  • the clamping gate wiring 47 is electrically connected to each of the plurality of gate electrodes 63 of the clamping transistor 60 .
  • the clamping gate wiring 47 is formed over the second wiring layer L2 and the third wiring layer L3.
  • the clamping gate wiring 47 is shown as a small rectangular shape adjacent to the active region 60T in the x-direction for the sake of convenience.
  • the wiring layer 40 further includes a first connection wiring 71, a second connection wiring 72, a third connection wiring 73, a fourth connection wiring 74, and a fifth connection wiring 75.
  • Each of first connection wiring 71, second connection wiring 72, third connection wiring 73, fourth connection wiring 74, and fifth connection wiring 75 is formed on semiconductor substrate 11 (see FIG. 2).
  • each of the first connection wiring 71, the second connection wiring 72, the third connection wiring 73, the fourth connection wiring 74, and the fifth connection wiring 75 is arranged in the longitudinal direction (y direction) of the semiconductor substrate 11. It is formed in a region closer to the clamping transistor 60 than the center of the semiconductor substrate 11 in the longitudinal direction.
  • connection wirings 71 to 75 is formed at a position overlapping the region where the active clamp circuit 30 is formed in plan view.
  • the connection wirings 71 to 75 are formed closer to the second side surface 11b than the drain pad 51 or the main source pad 52 in the longitudinal direction (y direction) of the semiconductor substrate 11 .
  • the first connection wiring 71 electrically connects the clamping capacitor 31 and the drain electrode 29 of the GaN transistor 20 (see FIG. 2). More specifically, the first connection wiring 71 connects the second wiring of the first electrode 31P of the clamping capacitor 31 to the end of the drain pad 51 near the clamping capacitor 31 in the y direction. ing. Since the drain pad 51 is electrically connected to the drain electrode 29 of the GaN transistor 20 , it can be said that the first connection wiring 71 is electrically connected to the drain electrode 29 . Note that the first connection wiring 71 may be integrated with the drain wiring 41 . In other words, the drain wiring 41 may include the first connection wiring 71 .
  • the first connection wiring 71 is formed between the clamping capacitor 31 and the drain pad 51 in the y direction. It can also be said that the first connection wiring 71 is formed closer to the third side surface 11c of the semiconductor substrate 11 than the active region 60T of the clamping transistor 60 in plan view. As shown in FIG. 5, the first connection wiring 71 is formed over the second wiring layer L2 and the third wiring layer L3.
  • the second connection wiring 72 electrically connects the second electrode 31Q of the clamping capacitor 31 and the first terminal 32P of the pull-down resistor 32 to the gate electrode 63 of the clamping transistor 60 . More specifically, the second connection wiring 72 electrically connects both the fourth wiring of the second electrode 31Q of the clamping capacitor 31 and the first terminal 32P of the pull-down resistor 32 to the gate electrode 63. . It can be said that the second connection wiring 72 is part of the clamping gate wiring 47 connected to the gate electrode 63 . That is, the clamping gate wiring 47 includes the second connection wiring 72 . As shown in FIG. 5, the second connection wiring 72 is formed over the second wiring layer L2 and the third wiring layer L3.
  • the second connection wiring 72 is formed closer to the third side surface 11c of the semiconductor substrate 11 than the active region 60T.
  • the second connection wiring 72 is formed between the clamping capacitor 31 and the pull-down resistor 32 in the y direction.
  • the second connection wiring 72 is formed in the third wiring layer L3.
  • the third connection wiring 73 electrically connects the second terminal 32 Q of the pull-down resistor 32 and the source electrode 62 of the clamp transistor 60 . It can be said that the third connection wiring 73 is part of the clamping source wiring 46 connected to the source electrode 62 . That is, the clamp source wiring 46 includes the third connection wiring 73 .
  • the third connection wiring 73 is formed in the third wiring layer L3.
  • the third connection wiring 73 is formed closer to the second side surface 11b of the semiconductor substrate 11 than the active region 60T. Further, the third connection wiring 73 is formed so as to protrude from the active region 60T toward the third side surface 11c. As shown in FIG. 5, the third connection wiring 73 is formed in the third wiring layer L3.
  • the fourth connection wiring 74 electrically connects the source electrode 62 of the clamping transistor 60 and the source electrode 28 of the GaN transistor 20 (see FIG. 2). More specifically, the fourth connection wiring 74 connects the clamping source wiring 46 and the end near the clamping capacitor 31 among both ends of the main source pad 52 in the y direction. Since the clamping source wiring 46 is electrically connected to the source electrode 62 of the clamping transistor 60 , it can be said that the fourth connection wiring 74 is electrically connected to the source electrode 62 . Since the main source pad 52 is electrically connected to the source electrode 28 of the GaN transistor 20 , it can be said that the fourth connection wiring 74 is electrically connected to the source electrode 28 .
  • the fourth connection wiring 74 is integrated with the clamping source wiring 46 . Therefore, it can be said that the fourth connection wiring 74 is a part of the clamping source wiring 46 . That is, the clamp source wiring 46 includes the fourth connection wiring 74 .
  • the fourth connection wiring 74 is formed closer to the fourth side surface 11d of the semiconductor substrate 11 than the active region 60T of the clamping transistor 60 in plan view. As shown in FIG. 5, the fourth connection wiring 74 is formed over the second wiring layer L2 and the third wiring layer L3.
  • the fifth connection wiring 75 electrically connects the drain electrode 61 of the clamping transistor 60 and the gate electrode 26 of the GaN transistor 20 (see FIG. 2). More specifically, the fifth connection wiring 75 is electrically connected to the clamping drain wiring 45 and the gate wiring 44 . Since the clamping drain wiring 45 is electrically connected to the drain electrode 61 of the clamping transistor 60 , it can be said that the fifth connection wiring 75 is electrically connected to the drain electrode 61 . Since the gate wiring 44 is electrically connected to the gate electrode 26 of the GaN transistor 20 , it can be said that the fifth connection wiring 75 is electrically connected to the gate electrode 26 . In FIGS. 1 and 4, the gate wiring 44 is shown in a small rectangular shape for the sake of convenience, but it is actually formed over the entire active region 20T. In this embodiment, the fifth connection wiring 75 is integrated with the clamping drain wiring 45 and the gate wiring 44 .
  • the fifth connection wiring 75 is formed between the clamping drain wiring 45 and the main source pad 52 in the y direction.
  • the fifth connection wiring 75 is formed in the third wiring layer L3 (see FIG. 5).
  • Each wiring of the clamping capacitor 31, the first terminal 32P and the second terminal 32Q of the pull-down resistor 32, and each of the connection wirings 71 to 75 are made of, for example, at least one of Cu, Al, AlCu alloy, W, Ti, and TiN. It can be constructed from any conductive material, including In one example, each wiring of the clamping capacitor 31, the first terminal 32P and the second terminal 32Q of the pull-down resistor 32, and each of the connection wirings 71-75 are made of the same conductive material as the wirings 41-44. Can be configured.
  • FIG. 6 shows the circuit configuration of the semiconductor device 10.
  • active clamp circuit 30 is connected to GaN transistor 20 .
  • source electrode 62 of clamping transistor 60 is connected to source electrode 28 of GaN transistor 20 .
  • a drain electrode 61 of the clamping transistor 60 is connected to the gate electrode 26 of the GaN transistor 20 .
  • Clamping capacitor 31 is connected between drain electrode 29 of GaN transistor 20 and gate electrode 63 of clamping transistor 60 .
  • Pull-down resistor 32 is connected between source electrode 62 and gate electrode 63 of clamping transistor 60 .
  • Both the drain electrode 29 of the GaN transistor 20 and the clamping capacitor 31 are connected to the drain pad 51 .
  • the source electrode 28 of the GaN transistor 20, the source electrode 62 of the clamping transistor 60, and the second terminal 32Q of the pull-down resistor 32 are connected to the main source pad 52 and the sense source pad 53, respectively.
  • Both the gate electrode 26 of the GaN transistor 20 and the drain electrode 61 of the clamping transistor 60 are connected to the gate pad 54 .
  • FIG. 8 is a schematic cross-sectional view of the semiconductor module 100 cut along line F8-F8 of FIG.
  • the semiconductor module 100 includes a semiconductor device 10 and a sealing resin 110 that seals the semiconductor device 10 .
  • the sealing resin 110 is made of an insulating resin material. As such a resin material, for example, epoxy resin, acrylic resin, phenol resin, etc. are used.
  • the sealing resin 110 constitutes the outer surface of the semiconductor module 100 .
  • the sealing resin 110 includes a resin front surface 110s and a resin back surface 110r facing opposite sides in the z-direction, and first to fourth resin side surfaces 110a to 110d perpendicular to both the resin front surface 110s and the resin back surface 110r.
  • the resin front surface 110 s faces the same side as the substrate front surface 11 s of the semiconductor substrate 11
  • the resin rear surface 110 r faces the same side as the substrate rear surface 11 r of the semiconductor substrate 11
  • the first resin side surface 110 a faces the same side as the first side surface 11 a of the semiconductor substrate 11
  • the second resin side surface 110 b faces the same side as the second side surface 11 b of the semiconductor substrate 11
  • the third resin side surface 110 c faces the same side as the semiconductor substrate 11 .
  • It faces the same side as the third side face 11 c
  • the fourth resin side face 110 d faces the same side as the fourth side face 11 d of the semiconductor substrate 11
  • the sealing resin 110 is slightly larger than the semiconductor substrate 11 . In this manner, the longitudinal direction of the semiconductor module 100 matches the longitudinal direction of the semiconductor substrate 11 in plan view, and the lateral direction of the semiconductor module 100 matches the lateral direction of the semiconductor substrate 11 .
  • the semiconductor module 100 includes an insulating layer 140 covering the resin surface 110s.
  • Insulating layer 140 is made of any insulating material including, for example, SiO 2 and SiN.
  • Semiconductor module 100 includes drain terminal 121 , main source terminal 122 , sense source terminal 123 , and gate terminal 124 exposed from sealing resin 110 . In this embodiment, these terminals 121 to 124 are exposed from the resin surface 110s and partially formed on the resin surface 110s. Some of the portions of these terminals 121 to 124 formed on the resin surface 110s are covered with an insulating layer 140. As shown in FIG.
  • the insulating layer 140 has a first opening 141 exposing a portion of the drain terminal 121, a second opening 142 exposing a portion of the main source terminal 122, and a portion of the sense source terminal 123. and a fourth opening 144 exposing a portion of the gate terminal 124 .
  • the semiconductor module 100 of this embodiment has a surface-mounted package structure. Note that the insulating layer 140 may be omitted from the semiconductor module 100 .
  • the drain terminal 121 is electrically connected to the drain electrode 29 of the GaN transistor 20 (see FIG. 2). Both the main source terminal 122 and the sense source terminal 123 are electrically connected to the source electrode 28 of the GaN transistor 20 (see FIG. 2). Gate terminal 124 is electrically connected to gate electrode 26 (see FIG. 2) of GaN transistor 20 .
  • the sealing resin 110 includes a first sealing portion 111 that supports the semiconductor substrate 11 and a second sealing portion that seals the semiconductor substrate 11 in cooperation with the first sealing portion 111. 112 and .
  • the first sealing portion 111 includes a resin rear surface 110r, and the second sealing portion 112 includes a resin surface 110s.
  • the semiconductor device 10 is bonded to the first sealing portion 111 with a bonding material AD, for example.
  • the bonding material AD may be a conductive bonding material such as solder paste or silver (Ag) paste, or may be an insulating bonding material such as an epoxy resin adhesive.
  • the semiconductor module 100 includes wires 130 that individually connect the terminals 121-124 and the pads 51-54.
  • the wiring 130 is provided inside the sealing resin 110 .
  • the sealing resin 110 seals the wiring 130 .
  • the wiring 130 is provided between the semiconductor device 10 and the resin surface 110s in the z direction.
  • Wiring 130 is formed of, for example, a metal plate. Note that the configuration of the wiring 130 can be arbitrarily changed. In one example, the wiring 130 may be formed by metal plating.
  • the wiring 130 is shown to have a rectangular cross section in FIG. 8, the cross-sectional shape may be changed as appropriate. For example, it may be shaped to be electrically connected to a portion of each pad 51-54.
  • the wiring 130 includes a drain wiring 131 connecting the drain terminal 121 and the drain pad 51 and a main source wiring 132 connecting the main source terminal 122 and the main source pad 52 .
  • the wiring 130 includes a sense source wiring connecting the sense source terminal 123 and the sense source pad 53 and a gate wiring connecting the gate terminal 124 and the gate pad 54 .
  • the sealing resin 110 includes a first opening 113 exposing part of the drain wiring 131 and a second opening 114 exposing part of the main source wiring 132 .
  • the drain terminal 121 is formed so as to fill the first opening 113 and cover the periphery of the first opening 113 . As a result, the drain terminal 121 is in contact with the drain wiring 131 and is electrically connected to the drain wiring 131 .
  • the main source terminal 122 is formed to fill the second opening 114 and cover the periphery of the second opening 114 . As a result, the main source terminal 122 is in contact with the main source wiring 132 and is thus electrically connected to the main source wiring 132 .
  • the sealing resin 110 includes a third opening exposing part of the sense source wiring and a fourth opening exposing part of the gate wiring.
  • Sense source terminal 123 and gate terminal 124 are formed similarly to drain terminal 121 and main source terminal 122 .
  • Each of these terminals 121-124 and wiring 130 can be made of any conductor material including at least one of Cu, Al, AlCu alloy, W, Ti, and TiN.
  • a semiconductor device without the active clamp circuit 30 is referred to as a "comparison semiconductor device".
  • the comparative semiconductor device has only the GaN transistor 20 .
  • GaN transistor 20 is used, for example, in a DC-DC converter or the like.
  • the voltage between the drain and the source of the GaN transistor 20 abruptly changes during the period from time t1 to time t2 during which the GaN transistor 20 is off. be. This is caused, for example, by the element to which the GaN transistor 20 is connected (eg the coil of a DC-DC converter).
  • the gate-source voltage (gate voltage) of the GaN transistor 20 rises due to the gate-drain parasitic capacitance of the GaN transistor 20 as indicated by the broken line in the middle of FIG.
  • GaN transistor 20 is turned on by the gate-source voltage exceeding the threshold voltage of GaN transistor 20 . That is, in the comparative semiconductor device, the GaN transistor 20 is turned on (erroneously turned on) although it should be turned off.
  • the clamping transistor 60 of this embodiment is configured to operate based on the rise of the drain-source voltage of the GaN transistor 20 . More specifically, the clamping transistor 60 is configured to turn on before the GaN transistor 20 when the drain-source voltage of the GaN transistor 20 sharply changes.
  • the capacitance of the clamping capacitor 31 is set so that the voltage of the second electrode 31Q rises faster than the gate-source voltage of the GaN transistor 20.
  • the capacitance of the clamping capacitor 31 is set smaller than the gate-drain capacitance of the GaN transistor 20 .
  • the threshold voltage of clamping transistor 60 may be set lower than the threshold voltage of GaN transistor 20 .
  • the clamping transistor 60 having such a clamping capacitor 31 connected to the gate electrode 63, the voltage between the gate and the source rises due to the sharp change in the voltage between the drain and the source of the GaN transistor 20.
  • FIG. As a result, the clamping transistor 60 is turned on, so that the gate electrode 26 and the source electrode 28 of the GaN transistor 20 are electrically connected via the clamping transistor 60 .
  • the gate-source voltage of the GaN transistor 20 starts to drop while rising. Therefore, as indicated by the solid line in the middle of FIG. 9, the increase in gate-source voltage of the GaN transistor 20 can be suppressed. This can prevent the GaN transistor 20 from being erroneously turned on.
  • the active clamp circuit 30 is provided for the comparison semiconductor device as a countermeasure against erroneous turn-on, it is conceivable to provide the active clamp circuit 30 on a circuit board outside the comparison semiconductor device.
  • the GaN transistor 20 of the comparative semiconductor device is connected to the active clamp circuit 30 provided on the circuit board through a conductive path such as wiring on the circuit board.
  • the longer the conductive path the greater the parasitic impedance in that conductive path.
  • the parasitic inductance of the conductive path may delay the operation of the active clamp circuit 30 with respect to sharp changes in the drain-source voltage of the GaN transistor 20 . Therefore, a sharp change in the voltage between the drain and the source of the GaN transistor 20 may also increase the voltage between the gate and the source, causing the GaN transistor 20 to turn on erroneously.
  • both the GaN transistor 20 and the active clamp circuit 30 are formed on the semiconductor substrate 11 of this embodiment.
  • the GaN transistor 20 and the active clamp circuit 30 can be electrically connected on the semiconductor substrate 11 .
  • the GaN transistor 20 and the active clamp circuit 30 can be electrically connected within the semiconductor device 10 . Therefore, the conductive path between the GaN transistor 20 and the active clamp circuit 30 becomes shorter than when the active clamp circuit 30 is provided on the circuit board outside the comparative semiconductor device. Therefore, parasitic impedance and parasitic inductance in the conductive path can be reduced. As a result, erroneous turn-on of the GaN transistor 20 can be suppressed.
  • the semiconductor device 10 includes a semiconductor substrate 11, a GaN transistor 20 formed on the semiconductor substrate 11 and including a drain electrode 29, a source electrode 28, and a gate electrode 26, and formed on the semiconductor substrate 11 and An active clamping circuit 30 including a clamping transistor 60 electrically connected to the GaN transistor 20 and operated based on the rise of the drain-source voltage of the GaN transistor 20 and electrically connected to the drain electrode 29 of the GaN transistor 20. , a main source pad 52 electrically connected to the source electrode 28 of the GaN transistor 20 , and a gate pad 54 electrically connected to the gate electrode 26 of the GaN transistor 20 .
  • the clamping transistor 60 can suppress an increase in the gate-source voltage of the GaN transistor 20 when the drain-source voltage of the GaN transistor 20 changes sharply. Therefore, erroneous turn-on of the GaN transistor 20 can be suppressed.
  • the GaN transistor 20 and the active clamp circuit 30 are electrically connected within the semiconductor device 10, the conductive path between the GaN transistor 20 and the active clamp circuit 30 can be shortened. Therefore, the parasitic impedance and parasitic inductance in the conductive path can be reduced, so that erroneous turn-on of the GaN transistor 20 can be further suppressed.
  • the GaN transistor 20 includes an electron transit layer 22 as a main drift layer.
  • the clamp transistor 60 includes an electron transit layer 22 as a sub-drift layer made of the same material as the main drift layer.
  • the GaN transistor 20 and the clamping transistor 60 include the common electron transit layer 22 . Thereby, both the GaN transistor 20 and the clamping transistor 60 can be easily formed on the semiconductor substrate 11 .
  • the active clamp circuit 30 includes a pull-down resistor 32 connected between the source electrode 62 and the gate electrode 63 of the clamp transistor 60, the drain electrode 29 of the GaN transistor 20 and the gate electrode of the clamp transistor 60. and a clamping capacitor 31 connected between 63.
  • the on/off of the clamp transistor 60 is controlled within the semiconductor device 10 instead of being controlled based on a signal from a circuit outside the semiconductor device 10. 10 eliminates the need to add signal pads. Therefore, it is possible to suppress addition of pads to the semiconductor device 10 by the active clamp circuit 30 .
  • both the GaN transistor 20 and the clamping transistor 60 include rectangular active regions 20T and 60T having longitudinal and lateral directions.
  • the GaN transistor 20 and the clamping transistor 60 are arranged side by side in the longitudinal direction (y direction) of the GaN transistor 20 when viewed from the z direction.
  • the longitudinal direction of the active region 20T of the GaN transistor 20 and the longitudinal direction of the active region 60T of the clamping transistor 60 are perpendicular to each other.
  • a clamping capacitor 31 is placed at a position overlapping the drain pad 51 in the lateral direction (x direction) of the active region 20T of the GaN transistor 20 when viewed from the longitudinal direction (y direction) of the active region 20T of the GaN transistor 20. and a pull-down resistor 32 are formed.
  • both the clamping capacitor 31 and the pull-down resistor 32 are formed in regions of the semiconductor substrate 11 other than the active regions 20T and 60T. Therefore, an increase in the area of the semiconductor substrate 11 viewed from the z direction can be suppressed.
  • the semiconductor device 10 includes a first wiring layer L1 in which a drain pad 51, a main source pad 52, a sense source pad 53, and a gate pad 54 are formed, and a semiconductor substrate 11 closer to the first wiring layer L1 than the first wiring layer L1. , and a second wiring layer L2 and a third A wiring layer L3, and a fourth wiring layer L4 provided on the side opposite to the first wiring layer L1 with respect to the second wiring layer L2 and the third wiring layer L3 and having the GaN transistor 20 formed thereon.
  • Clamp transistor 60, clamp capacitor 31, and pull-down resistor 32 are each provided in fourth wiring layer L4.
  • the GaN transistor 20, the clamping transistor 60, the clamping capacitor 31, and the pull-down resistor 32 are formed in a common wiring layer. Therefore, a part of each of the GaN transistor 20, the clamping transistor 60, the clamping capacitor 31, and the pull-down resistor 32 can be made of a common material. Therefore, the semiconductor device 10 can be manufactured easily.
  • the semiconductor module 100 includes the semiconductor device 10, the sealing resin 110 sealing the semiconductor device 10, and the drain terminal 121 exposed from the sealing resin 110 and electrically connected to the drain pad 51. , a main source terminal 122 exposed from the sealing resin 110 and electrically connected to the main source pad 52, and a gate terminal 124 exposed from the sealing resin 110 and electrically connected to the gate pad 54. Prepare.
  • the semiconductor module 100 also includes wiring 130 electrically connecting the semiconductor device 10 and the drain terminal 121 , the main source terminal 122 , and the gate terminal 124 .
  • the drain terminal 121 , the main source terminal 122 , and the gate terminal 124 are exposed from a resin surface 110 s of the sealing resin 110 facing the same side as the substrate surface 11 s of the semiconductor substrate 11 .
  • drain terminal 121, the main source terminal 122, and the gate terminal 124 can be formed at positions overlapping the semiconductor substrate 11 in plan view. Therefore, miniaturization of the semiconductor module 100 can be achieved.
  • drain terminal 121, main source terminal 122 and gate terminal 124 are connected to semiconductor device 10 electrically by wires, for example.
  • a conductive path to the semiconductor device 10 can be shortened. Therefore, parasitic inductance due to the length of the conductive path can be reduced. Parasitic inductance in the conductive path affects the switching characteristics (switching speed) of GaN transistor 20 . Therefore, the switching characteristics of the GaN transistor 20 can be improved by reducing the parasitic inductance.
  • FIG. 10 is a plan view mainly showing an example of the arrangement of semiconductor chips in the internal structure of the semiconductor module 200.
  • FIG. 11 is a plan view mainly showing an example of the configuration of wiring layers in the internal structure of the semiconductor module 200.
  • FIG. 12 is a plan view of the semiconductor module 200.
  • FIG. 13 is a cross-sectional view of the semiconductor module 200 taken along line F13-F13 of FIG. 12.
  • FIG. FIG. 14 is a cross-sectional view of the semiconductor module 200 taken along line F14-F14 in FIG.
  • a semiconductor module 200 includes a plurality of (two in this embodiment) semiconductor devices 10, a driver chip 210 for individually driving the plurality of semiconductor devices 10, and a plurality of semiconductor devices 10 and driver chips. and a sealing resin 220 that seals 210 .
  • both the semiconductor devices 10 and the driver chip 210 in the sealing resin 220 are indicated by solid lines for convenience of explanation.
  • the semiconductor module 200 is formed in a rectangular plate shape.
  • the sealing resin 220 constitutes the outer surface of the semiconductor module 200 . That is, the sealing resin 220 is formed in a rectangular plate shape.
  • the sealing resin 220 includes a resin surface 220s, a resin back surface 220r facing the opposite side of the resin surface 220s (see FIG. 13 for both), and four resin side surfaces intersecting both the resin surface 220s and the resin back surface 220r. 1 to 4 resin side surfaces 220a to 220d.
  • the first to fourth resin side surfaces 220a to 220d are orthogonal to both the resin front surface 220s and the resin back surface 220r.
  • the thickness direction of the sealing resin 220 is defined as the z direction.
  • the shape of the sealing resin 220 in plan view is a rectangular shape having a longitudinal direction and a lateral direction.
  • the longitudinal direction of the sealing resin 220 is the y direction
  • the lateral direction of the sealing resin 220 is the x direction.
  • the first resin side surface 220a and the second resin side surface 220b constitute both end surfaces in the y direction
  • the third resin side surface 220c and the fourth resin side surface 220d constitute both end surfaces in the x direction.
  • the sealing resin 220 is made of an insulating resin material.
  • a resin material for example, epoxy resin, acrylic resin, phenol resin, or the like can be used.
  • each semiconductor device 10 is arranged biased in the y direction with respect to the sealing resin 220 .
  • each semiconductor device 10 is arranged closer to the second resin side surface 220b than the first resin side surface 220a of the sealing resin 220 in plan view.
  • Each semiconductor device 10 is arranged such that the longitudinal direction of the semiconductor substrate 11 is the y direction and the lateral direction of the semiconductor substrate 11 is the x direction.
  • the longitudinal direction of the semiconductor substrate 11 and the longitudinal direction of the sealing resin 220 are aligned, and the lateral direction of the semiconductor substrate 11 and the lateral direction of the sealing resin 220 are aligned.
  • the two semiconductor devices 10 are arranged apart from each other in the lateral direction of the sealing resin 220 .
  • the semiconductor device 10 arranged closer to the third resin side surface 220c will be referred to as “semiconductor device 10A”
  • semiconductor device 10 arranged closer to the fourth resin side surface 220d will be referred to as “semiconductor device 10B”. do.
  • the semiconductor devices 10A and 10B are not distinguished, they are simply referred to as "semiconductor device 10".
  • the driver chip 210 is arranged apart from each semiconductor device 10 in a direction orthogonal to the arrangement direction of each semiconductor device 10 in plan view. More specifically, the driver chip 210 is arranged closer to the first resin side surface 220a than each semiconductor device 10 in the y direction.
  • the y direction corresponds to the "second direction”.
  • Driver chip 210 is formed in a rectangular flat plate shape.
  • the shape of driver chip 210 in plan view is a rectangular shape having a longitudinal direction and a lateral direction. In this embodiment, the driver chip 210 is arranged such that its longitudinal direction is the x direction and its lateral direction is the y direction.
  • the longitudinal direction of the driver chip 210 is perpendicular to both the longitudinal direction of the sealing resin 220 and the longitudinal direction of the semiconductor substrate 11, and the lateral direction of the driver chip 210 is the lateral direction of the sealing resin 220. and perpendicular to the lateral direction of the semiconductor substrate 11 .
  • the driver chip 210 is arranged at a position overlapping each semiconductor device 10 when viewed in the y direction. In this embodiment, the driver chip 210 is arranged in the center of the sealing resin 220 in the x direction. Note that the layout of the driver chip 210 and each semiconductor device 10 can be arbitrarily changed.
  • the driver chip 210 includes a chip front surface 210s and a chip rear surface 210r (see FIG. 14) facing opposite sides in the z-direction.
  • the chip front surface 210s faces the same side as the resin front surface 220s
  • the chip rear surface 210r faces the same side as the resin rear surface 220r.
  • the driver chip 210 includes a semiconductor substrate, a driver circuit 211 formed on the semiconductor substrate and driving each semiconductor device 10, and a plurality of electrode pads 212 electrically connected to the driver circuit 211. Each electrode pad 212 is exposed from the chip surface 210s.
  • FIG. 11 shows the internal structure of a portion of the sealing resin 220 above each semiconductor device 10 and driver chip 210 .
  • each semiconductor device 10 and driver chip 210 are indicated by two-dot chain lines for convenience.
  • the semiconductor module 200 includes wiring layers 230 .
  • the wiring layer 230 includes at least two types of wiring layers: a wiring layer including vias extending in the z-direction and wirings extending in a direction orthogonal to the z-direction, and a wiring layer composed only of vias extending in the z-direction. include.
  • the wiring layer 230 includes drain wirings 231A, 231B, main source wirings 232A, 232B, sense source wirings 233A, 233B, gate wirings 234A, 234B, and a plurality of driver wirings 235 .
  • the drain wiring 231A is electrically connected to the drain pad 51 of the semiconductor device 10A.
  • the drain wiring 231A is composed of, for example, a plurality of vias.
  • the drain wiring 231B is electrically connected to the drain pad 51 of the semiconductor device 10B.
  • the drain wiring 231B includes, for example, a plurality of first vias connected to the drain pad 51, a wiring extending in the y direction and connected to connect the upper surfaces of the plurality of first vias, and a plurality of second vias formed on the wiring. 2 vias.
  • the plurality of second vias are arranged at positions different from the plurality of first vias in plan view. More specifically, the plurality of second vias are arranged closer to the semiconductor device 10A than the plurality of first vias in plan view. In plan view, it can be said that the plurality of second vias are arranged between the semiconductor devices 10A and 10B in the x direction.
  • the main source wiring 232A is electrically connected to the main source pad 52 of the semiconductor device 10A.
  • the main source wiring 232A includes, for example, a plurality of first vias connected to the main source pad 52, a wiring extending in the y-direction connected to connect the upper surfaces of the plurality of first vias, and a plurality of wirings formed on the wiring. and a second via of .
  • the plurality of second vias are arranged at positions different from the plurality of first vias in plan view. More specifically, the plurality of second vias are arranged closer to the semiconductor device 10B than the plurality of first vias in plan view. In plan view, it can be said that the plurality of second vias are arranged between the semiconductor devices 10A and 10B in the x direction. The plurality of second vias are arranged closer to the semiconductor device 10A than the second vias of the drain wiring 231B.
  • the main source wiring 232B is electrically connected to the main source pad 52 of the semiconductor device 10B.
  • the main source wiring 232B is composed of, for example, a plurality of vias.
  • the sense source wiring 233A electrically connects the sense source pad 53 of the semiconductor device 10A and the driver circuit 211.
  • the sense source wiring 233A connects, for example, a first via connected to the sense source pad 53 of the semiconductor device 10A, a second via connected to the electrode pad 212 of the driver chip 210, and the first via and the second via. including wiring;
  • the sense source wiring 233B electrically connects the sense source pad 53 and the driver circuit 211 of the semiconductor device 10B.
  • Sense source wiring 233B connects, for example, a first via connected to sense source pad 53 of semiconductor device 10B, a second via connected to electrode pad 212 of driver chip 210, and the first and second vias. including wiring;
  • the gate wiring 234A electrically connects the gate pad 54 of the semiconductor device 10A and the driver circuit 211.
  • the gate wiring 234A includes, for example, a first via connected to the gate pad 54 of the semiconductor device 10A, a second via connected to the electrode pad 212 of the driver chip 210, and a wiring connecting the first via and the second via. ,including.
  • the gate wiring 234B electrically connects the gate pad 54 of the semiconductor device 10B and the driver circuit 211.
  • the gate wiring 234B includes, for example, a first via connected to the gate pad 54 of the semiconductor device 10B, a second via connected to the electrode pad 212 of the driver chip 210, and a wiring connecting the first via and the second via. ,including.
  • the plurality of driver wirings 235 are individually connected to the plurality of electrode pads 212 of the driver chip 210 .
  • Each driver wiring 235 includes a first via connected to the electrode pad 212 of the driver chip 210, a wiring extending from the upper surface of the first via in a direction perpendicular to the z-direction, and a plurality of second vias formed on the wiring. including vias.
  • the wiring extends outward from the driver chip 210 toward any one of the first resin side surface 220a, the third resin side surface 220c, and the fourth resin side surface 220d in plan view.
  • the semiconductor module 200 includes a drain terminal 241, a source terminal 242, an output terminal 243, and a plurality of driver terminals 244. Each terminal 241 to 244 is exposed from the resin surface 220s.
  • the drain terminal 241, the source terminal 242, and the output terminal 243 are aligned in the y direction and arranged apart from each other in the x direction.
  • the shape of each of the drain terminal 241, the source terminal 242, and the output terminal 243 in plan view is a rectangular shape in which the y direction is the longitudinal direction and the x direction is the lateral direction.
  • the drain terminal 241, the source terminal 242, and the output terminal 243 are arranged in the y-direction so as to be closer to the second resin side surface 220b than the first resin side surface 220a.
  • the drain terminal 241 is arranged at a position overlapping with the semiconductor device 10A
  • the source terminal 242 is arranged at a position overlapping with the semiconductor device 10B
  • the output terminal 243 is located at the x-axis between the semiconductor devices 10A and 10B. located between directions. Note that the layout of the drain terminal 241, the source terminal 242, and the output terminal 243 can be arbitrarily changed.
  • the plurality of driver terminals 244 are arranged to be closer to the first resin side surface 220a than the second resin side surface 220b in the y direction.
  • the plurality of driver terminals 244 are arranged in a row along the first resin side surface 220a, the third resin side surface 220c, and the fourth resin side surface 220d in plan view.
  • the drain terminal 241 is electrically connected to the drain electrode 29 of the semiconductor device 10A through each of a plurality of vias as the drain wiring 231A.
  • Source terminal 242 is electrically connected to source electrode 28 of semiconductor device 10B through each of a plurality of vias as main source wiring 232B.
  • the output terminal 243 connects the source electrode 28 of the semiconductor device 10A and the drain electrode 29 of the semiconductor device 10B through each of the plurality of second vias of the main source wiring 232A and each of the plurality of second vias of the drain wiring 231B. Both are electrically connected.
  • Each driver terminal 244 is electrically connected to the driver circuit 211 through the second via of the corresponding driver wiring 235 .
  • the sealing resin 220 includes a first sealing portion 221, a second sealing portion 222, and a third sealing portion 223.
  • Each of the sealing portions 221-223 is made of the same material, for example.
  • the first sealing portion 221 is a supporting member that supports each semiconductor device 10 and driver chip 210 .
  • Each semiconductor device 10 and each driver chip 210 are bonded to the first sealing portion 221 by, for example, a bonding material AD.
  • the first sealing portion 221 constitutes a resin rear surface 220r.
  • the second sealing portion 222 cooperates with the first sealing portion 221 to seal each semiconductor device 10 and the driver chip 210 .
  • the third sealing portion 223 is provided on the second sealing portion 222 .
  • the third sealing portion 223 forms a resin surface 220s.
  • a drain terminal 241 , a source terminal 242 , an output terminal 243 and a plurality of driver terminals 244 are formed on the third sealing portion 223 .
  • the wiring layer 230 is formed over the second sealing portion 222 and the third sealing portion 223 .
  • the drain wiring 231B and the main source wiring 232A in the wiring layer 230 are formed as follows. That is, the first vias of the drain wiring 231B and the main source wiring 232A pass through the portion of the second sealing portion 222 covering the semiconductor devices 10A and 10B in the z direction.
  • the wirings of the drain wiring 231B and the main source wiring 232A are formed on the second sealing portion 222 . These wirings are covered with the third sealing portion 223 .
  • the second vias of the drain wiring 231B and the main source wiring 232A pass through the third sealing portion 223 in the z-direction.
  • the drain wiring 231A and the main source wiring 232B (both see FIG. 11) of the wiring layer 230 extend in the z direction from the second sealing portion 222 covering the semiconductor devices 10A and 10B.
  • a plurality of vias passing through and a plurality of vias passing through the third sealing portion 223 in the z-direction are included.
  • the sense source wirings 233A and 233B and the gate wirings 234A and 234B (see both FIG. 11) in the wiring layer 230 are formed as follows. That is, the first via of the gate wiring 234A penetrates the portion of the second sealing portion 222 covering the semiconductor device 10A in the z direction. The wiring of the gate wiring 234A is formed on the second sealing portion 222 . This wiring is covered with the third sealing portion 223 . The second via of the gate wiring 234A penetrates the portion of the second sealing portion 222 covering the driver chip 210 in the z-direction.
  • Sense source wirings 233A and 233B and gate wiring 234B have the same connection structure as gate wiring 234A, so detailed description thereof will be omitted.
  • FIG. 15 shows an example of the circuit configuration of the semiconductor module 200. As shown in FIG. For convenience of explanation, the detailed circuit configuration of the driver circuit 211 is omitted.
  • the GaN transistor of the semiconductor device 10A is called “GaN transistor 20A”
  • the GaN transistor of the semiconductor device 10B is called “GaN transistor 20B”.
  • the active clamp circuit 30 of the semiconductor device 10A is referred to as “active clamp circuit 30A”
  • the active clamp circuit 30 of the semiconductor device 10B is referred to as "active clamp circuit 30B”.
  • the GaN transistor 20A and the active clamp circuit 30A are connected, and the GaN transistor 20B and the active clamp circuit 30B are connected.
  • the drain electrode 29 of the GaN transistor 20A is connected to the drain terminal 241, and the source electrode 28 of the GaN transistor 20B is connected to the source terminal 242.
  • a source electrode 28 of GaN transistor 20A is connected to a drain electrode 29 of GaN transistor 20B.
  • Output terminal 243 is connected to node N between source electrode 28 of GaN transistor 20A and drain electrode 29 of GaN transistor 20B.
  • Each of the gate electrodes 26 of the GaN transistors 20A, 20B is connected to the driver circuit 211. Also, each of the source electrodes 28 of the GaN transistors 20A and 20B is connected to the driver circuit 211 .
  • the driver circuit 211 is connected to a plurality of driver terminals 244 .
  • the driver circuit 211 when a control signal for driving the GaN transistors 20A and 20B is input to the driver terminal 244 from an external device, the driver circuit 211 receives the control signal input to the driver circuit 211 through the driver terminal 244. A drive signal for driving the GaN transistors 20A and 20B is generated according to the signal. The driver circuit 211 then outputs drive signals to the gate electrodes 26 of the GaN transistors 20A and 20B. The GaN transistors 20A and 20B are driven ON/OFF complementarily based on the drive signal input to the gate electrode 26 thereof.
  • the semiconductor module 200 includes the semiconductor devices 10A and 10B, the driver chip 210, and the sealing resin 220 that seals both the semiconductor devices 10A and 10B and the driver chip 210.
  • FIG. 1 The semiconductor module 200 includes the semiconductor devices 10A and 10B, the driver chip 210, and the sealing resin 220 that seals both the semiconductor devices 10A and 10B and the driver chip 210.
  • the GaN transistors 20 of the semiconductor devices 10A and 10B and the driver circuit 211 of the driver chip 210 can be electrically connected within the semiconductor module 200. Therefore, compared to the case where the GaN transistors 20 and the driver circuits 211 of the semiconductor devices 10A and 10B are electrically connected by a circuit board outside the semiconductor module 200, the GaN transistors 20 and the driver circuits 211 of the semiconductor devices 10A and 10B can be shortened. Therefore, parasitic impedance and parasitic inductance due to the length of the conductive path can be reduced.
  • the driver chip 210 is spaced apart from the semiconductor devices 10A and 10B in a direction orthogonal to the arrangement direction of the semiconductor devices 10A and 10B in plan view. According to this configuration, compared to the case where the driver chip 210 is arranged adjacent to either of the semiconductor devices 10A and 10B in the arrangement direction of the semiconductor devices 10A and 10B, the gate of the GaN transistor 20 in the semiconductor device 10A is reduced. Variation in the length of the conductive path between the electrode 26 and the driver circuit 211 and the length of the conductive path between the gate electrode 26 of the GaN transistor 20 and the driver circuit 211 in the semiconductor device 10B can be reduced.
  • the sense source pad 53 may be omitted from the semiconductor device 10 .
  • the sense source terminal 123 may be omitted from the semiconductor module 100 in the first embodiment.
  • the configuration of the pull-down resistor 32 can be arbitrarily changed.
  • the pull-down resistor 32 may be modified as in the first modified example shown in FIG. 16 or the second modified example shown in FIG.
  • the pull-down resistor 32 includes a first wiring portion 32PA forming the first terminal 32P, a second wiring portion 32QA forming the second terminal 32Q, and a flat resistor. and a portion 32R.
  • Each wiring part 32PA, 32QA can be made of any conductive material including at least one of Cu, Al, AlCu alloy, W, Ti, and TiN, for example.
  • the resistor portion 32R is formed on the semiconductor substrate 11 (see FIG. 4). More specifically, the resistance section 32R is formed on the passivation layer 27 formed on the semiconductor substrate 11. As shown in FIG. Note that the formation position of the resistance portion 32R is not limited to the passivation layer 27, and may be formed on the insulating layer covering the electron supply layer .
  • the resistance portion 32R is made of a material having a higher resistance value than the first wiring portion 32PA and the second wiring portion 32QA.
  • the resistance section 32R is made of polysilicon, for example.
  • a first wiring portion 32PA and a second wiring portion 32QA are provided on the resistance portion 32R. Both the first wiring portion 32PA and the second wiring portion 32QA are electrically connected to the resistance portion 32R. More specifically, the wiring portions 32PA, 32QA and the resistance portion 32R are in ohmic contact. The first wiring portion 32PA and the second wiring portion 32QA are formed dispersedly at both ends of the resistance portion 32R in the x direction in plan view.
  • the pull-down resistor 32 is composed of a normally-on transistor and configured to include the ON resistance of the normally-on transistor. More specifically, the pull-down resistor 32 includes an electron transit layer 22, an electron supply layer 23, and a passivation layer 27, like the GaN transistor 20 and clamping transistor 60 of each embodiment. On the other hand, pull-down resistor 32 does not include gate layer 25, unlike GaN transistor 20 and clamping transistor 60 of each embodiment.
  • the pull-down resistor 32 electrically connects a first terminal 32P corresponding to the drain electrode, a second terminal 32Q corresponding to the source electrode, a third terminal 32S corresponding to the gate electrode, and the first terminal 32P and the second terminal 32Q. and a connection path 32A (see FIG. 4) that is physically connected.
  • the connection path 32A is formed in a bellows shape as in the first embodiment.
  • a third terminal 32 ⁇ /b>S is formed on the passivation layer 27 .
  • the third terminal 32S is arranged closer to the second terminal 32Q.
  • the pull-down resistor 32 includes a wiring 32C connecting the first terminal 32P and the third terminal 32S.
  • the wiring 32C can be made of any conductive material including at least one of Cu, Al, AlCu alloy, W, Ti, and TiN, for example.
  • the wiring 32C is formed, for example, over the second wiring layer L2 and the third wiring layer L3 (see FIG. 5 for both).
  • the formation positions of the GaN transistor 20 and the clamping transistor 60 in plan view can be arbitrarily changed.
  • the GaN transistor 20 and the clamping transistor 60 may be formed side by side in the lateral direction (x direction) of the semiconductor substrate 11 .
  • the active region 60T of the clamping transistor 60 is formed so that, for example, the y direction is the longitudinal direction and the x direction is the lateral direction.
  • Both the clamping capacitor 31 and the pull-down resistor 32 are formed at positions different from those of the GaN transistor 20 and the clamping transistor 60 in the longitudinal direction (y-direction) of the semiconductor substrate 11, for example, in plan view.
  • both the clamp capacitor 31 and the pull-down resistor 32 overlap the drain pad 51 in the lateral direction (x direction) of the active region 20T when viewed from the longitudinal direction (y direction) of the active region 20T of the GaN transistor 20. It may be formed in a position where it does not. Both the clamping capacitor 31 and the pull-down resistor 32 may be formed at a position closer to the third side surface 11c of the semiconductor substrate 11 than the drain pad 51 in plan view, for example.
  • the formation positions of the clamping capacitor 31 and the pull-down resistor 32 in the thickness direction (z direction) of the semiconductor substrate 11 can be arbitrarily changed.
  • both the clamping capacitor 31 and the pull-down resistor 32 may be formed in the second wiring layer L2.
  • the circuit configuration of the active clamp circuit 30 can be arbitrarily changed.
  • the active clamp circuit 30 may be modified as in the following first to third modified examples.
  • FIG. 18 shows the circuit configuration of the active clamp circuit 30 of the first modified example.
  • the active clamp circuit 30 further includes a capacitor 80 connected between the source electrode 62 and the gate electrode 63 of the clamp transistor 60 .
  • the capacitor 80 is configured to suppress application of a voltage higher than the gate-source rated voltage to the gate electrode 63 of the clamping transistor 60 . Therefore, excessive increase in the gate-source voltage of clamping transistor 60 is suppressed.
  • FIG. 19 shows the configuration of the active clamp circuit 30 of the first modified example on the semiconductor substrate 11.
  • the capacitors 80 are formed at the ends of the second side surface 11b and the third side surface 11c of the semiconductor substrate 11 in plan view.
  • the capacitor 80 is formed at a position closer to the third side surface 11c than the active region 60T of the clamping transistor 60.
  • the capacitor 80 is formed closer to the third side surface 11c than the clamping capacitor 31 in plan view.
  • the capacitor 80 is formed closer to the second side surface 11b than the clamping capacitor 31 is.
  • a capacitor 80 includes a first electrode 81 and a second electrode 82 .
  • the first electrode 81 is electrically connected to the second electrode 31Q of the clamping capacitor 31.
  • the second electrode 82 is electrically connected to the source electrode 62 of the clamping transistor 60 .
  • the configuration of the capacitor 80 is similar to that of the clamping capacitor 31 . Therefore, although not shown, the capacitor 80 is formed in the third wiring layer L3.
  • FIG. 20 shows the circuit configuration of the active clamp circuit 30 of the second modified example.
  • the active clamp circuit 30 further includes a shunt resistor 83 connected between the source electrode 62 and the gate electrode 63 of the clamp transistor 60 .
  • the shunt resistor 83 is configured to suppress application of a voltage higher than the gate-source rated voltage to the gate electrode 63 of the clamping transistor 60 . Therefore, excessive increase in the gate-source voltage of clamping transistor 60 is suppressed.
  • FIG. 21 shows the configuration on the semiconductor substrate 11 of the active clamp circuit 30 of the second modified example.
  • the shunt resistors 83 are formed at the ends of the second side surface 11b and the third side surface 11c of the semiconductor substrate 11 in plan view.
  • the shunt resistor 83 is formed at a position closer to the third side surface 11c than the active region 60T of the clamping transistor 60.
  • the shunt resistor 83 is formed closer to the third side surface 11c than the clamping capacitor 31 in plan view.
  • the shunt resistor 83 is formed closer to the second side surface 11b than the clamping capacitor 31 is.
  • the shunt resistor 83 includes a first terminal 84 and a second terminal 85.
  • the first terminal 84 is electrically connected to the second electrode 31Q of the clamping capacitor 31.
  • a second terminal 85 is electrically connected to the source electrode 62 of the clamping transistor 60 .
  • the configuration of the shunt resistor 83 is similar to that of the pull-down resistor 32 . Therefore, although not shown, the shunt resistor 83 is formed in the third wiring layer L3.
  • FIG. 22 shows the circuit configuration of the active clamp circuit 30 of the third modified example.
  • the active clamp circuit 30 further includes a protection transistor 90 for suppressing malfunction of the clamp transistor 60 .
  • Protection transistor 90 includes a drain electrode 91 , a source electrode 92 and a gate electrode 93 .
  • the protection transistor 90 is connected between the source electrode 62 and the gate electrode 63 of the clamp transistor 60 . More specifically, the drain electrode 91 of the protection transistor 90 is connected to the gate electrode 63 of the clamp transistor 60, and the source electrode 92 of the protection transistor 90 is connected to the source electrode 62 of the clamp transistor 60. .
  • a gate electrode 93 of the protection transistor 90 is connected to the gate pad 54 .
  • the protection transistor 90 is a normally-off transistor.
  • the protection transistor 90 When the GaN transistor 20 is on, the protection transistor 90 is on.
  • the protection transistor 90 connects the gate electrode 63 of the clamping transistor 60 and the source electrode 62 of the clamping transistor 60 . Therefore, protection transistor 90 reliably turns off clamp transistor 60 when GaN transistor 20 is in the on state. As a result, even if noise or the like is applied to the wiring to which the gate electrode 63 of the clamping transistor 60 is connected, it is possible to prevent the GaN transistor 20 from turning off at unintended timing.
  • the protective transistor 90 is turned off when the GaN transistor 20 is turned off. Therefore, the clamping transistor 60 can operate according to the drain-source voltage of the GaN transistor 20 . Thereby, as described in the first embodiment, the clamping transistor 60 can suppress the increase in the gate-source voltage of the GaN transistor 20 .
  • FIG. 23 shows the configuration on the semiconductor substrate 11 of the active clamp circuit 30 of the third modified example.
  • the protection transistor 90 is formed between the active region 20T of the GaN transistor 20 and the active region 60T of the clamp transistor 60 in the y direction.
  • a drain electrode 91 (see FIG. 22) of the protection transistor 90 is electrically connected to the clamping gate wiring 47 .
  • a gate electrode 93 (see FIG. 22) of the protection transistor 90 is electrically connected to the clamping drain wiring 45 .
  • the source electrode 92 (see FIG. 22) of the protection transistor 90 is electrically connected to the clamping source wiring 46 .
  • the protection transistor 90 is formed in the third wiring layer L3. In other words, the protection transistor 90 is formed at the same position as the GaN transistor 20 and the clamp transistor 60 in the z-direction.
  • At least one of the active clamp circuits 30 of the first modification and the second modification may include the protection transistor 90 of the third modification.
  • the semiconductor module 200 was provided with the two semiconductor devices 10, it is not restricted to this.
  • the semiconductor module 200 may have a configuration including one semiconductor device 10.
  • the shape of the sealing resin 220 in plan view is a rectangular shape with the y direction as the longitudinal direction and the x direction as the lateral direction.
  • Semiconductor device 10 and driver chip 210 are arranged apart from each other in the y direction.
  • the semiconductor device 10 is arranged at a position closer to the second resin side surface 220b of the sealing resin 220 than the driver chip 210 in the y direction.
  • the driver chip 210 is arranged closer to the first resin side surface 220a of the sealing resin 220 than the semiconductor device 10 in the y direction.
  • the semiconductor device 10 is arranged so that the longitudinal direction of the semiconductor substrate 11 is the y direction and the lateral direction of the semiconductor substrate 11 is the x direction. Therefore, the longitudinal direction of the semiconductor substrate 11 matches the longitudinal direction of the sealing resin 220 , and the lateral direction of the semiconductor substrate 11 matches the lateral direction of the sealing resin 220 .
  • the driver chip 210 is arranged so that its longitudinal direction is the x direction and its lateral direction is the y direction. Therefore, the longitudinal direction of the driver chip 210 is orthogonal to both the longitudinal direction of the semiconductor substrate 11 and the longitudinal direction of the sealing resin 220 in plan view, and the lateral direction of the driver chip 210 is perpendicular to the longitudinal direction of the semiconductor substrate 11 in plan view. It is orthogonal to both the lateral direction and the lateral direction of the sealing resin 220 .
  • the modified semiconductor module 200 includes a drain terminal 241 , a source terminal 242 and a plurality of driver terminals 244 . That is, the semiconductor module 200 of the modified example does not have the output terminal 243 .
  • the drain terminals 241 and the source terminals 242 are aligned in the y-direction and spaced apart in the x-direction. Both the drain terminal 241 and the source terminal 242 are arranged at positions overlapping the semiconductor device 10 in plan view.
  • the plurality of driver terminals 244 are arranged closer to the first resin side surface 220a than the drain terminal 241 and the source terminal 242 in the y direction. It can be said that the plurality of driver terminals 244 are arranged closer to the first resin side surface 220a than the semiconductor device 10 in the y direction.
  • the modified semiconductor module 200 includes a wiring layer 250 .
  • the wiring layer 250 is made of a conductive material similar to that of the wiring layer 230 (see FIG. 13).
  • the wiring layer 250 includes a drain wiring 251 , a main source wiring 252 , a sense source wiring 253 , a gate wiring 254 and a plurality of driver wirings 255 .
  • the drain wiring 251 electrically connects the drain electrode 29 of the GaN transistor 20 and the drain terminal 241 .
  • the drain wiring 251 is formed by a plurality of vias.
  • the main source wiring 252 electrically connects the source electrode 28 of the GaN transistor 20 and the source terminal 242 .
  • the main source wiring 252 is formed by a plurality of vias.
  • the sense source wiring 253 electrically connects the source electrode 28 of the GaN transistor 20 and the driver circuit 211 of the driver chip 210 .
  • the sense source wiring 253 is configured similarly to the sense source wirings 233A and 233B (see FIG. 13).
  • the gate wiring 254 electrically connects the gate electrode 26 of the GaN transistor 20 and the driver circuit 211 .
  • the gate wiring 254 is configured similarly to the gate wiring 234A (see FIG. 14).
  • the plurality of driver wirings 255 electrically connect the driver circuit 211 and the plurality of driver terminals 244 individually.
  • Each driver wiring 255 is configured in the same manner as the driver wiring 235 (see FIG. 11) of the second embodiment.
  • the number of driver chips 210 can be arbitrarily changed.
  • semiconductor module 200 may include multiple driver chips 210 .
  • the number of driver chips 210 may be changed according to the number of semiconductor devices 10 . For example, when there are two semiconductor devices 10, the number of driver chips 210 is two.
  • the number of semiconductor devices 10 can be arbitrarily changed.
  • the semiconductor module 100 includes multiple semiconductor devices 10 .
  • the semiconductor module 200 includes three or more semiconductor devices 10 .
  • the drain pad 51, the main source pad 52, the sense source pad 53, and the gate pad 54 of the GaN transistor 20, the drain terminal 121, the main source terminal 122, the sense source terminal 123, and It may be electrically connected to the gate terminal 124 by a wire.
  • the terminals 121 to 124 are exposed from the resin rear surface 110r of the sealing resin 110, for example.
  • the drain pads 51 and the main source pads 52 of the semiconductor devices 10A and 10B, the drain terminals 241, the source terminals 242, and the output terminals 243 are individually electrically connected by wires. may be
  • a first member is formed on a second member means that in some embodiments the first member may be placed directly on the second member in contact with the second member, but in other implementations the first member may be disposed directly on the second member. It is contemplated that the configuration allows the first member to be positioned over the second member without contacting the second member. That is, the term “on” does not exclude structures in which another member is formed between the first member and the second member.
  • the z-direction used in the present disclosure does not necessarily have to be the vertical direction, nor does it have to match the vertical direction perfectly.
  • the various structures according to this disclosure are not limited to the z-direction "top” and “bottom” described herein being the vertical “top” and “bottom”.
  • the x-direction may be vertical, or the y-direction may be vertical.
  • references herein to "at least one of A and B" should be understood to mean “A only, or B only, or both A and B.” [Note] Technical ideas that can be grasped from the above embodiment and modifications are described below. It should be noted that for the purpose of aid in understanding and not for the purpose of limitation, the corresponding reference numerals in the embodiments are shown in parentheses for the configurations described in the appendix. Reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.
  • the GaN transistor (20) includes a main drift layer (22), The semiconductor device according to appendix 1, wherein the clamping transistor (60) includes a sub-drift layer (22) made of the same material as the main drift layer (22).
  • said clamping transistor (60) comprises a drain electrode (61), a source electrode (62) and a gate electrode (63); the source electrode (62) of the clamping transistor (60) is electrically connected to the source electrode (28) of the GaN transistor (20), a drain electrode (61) of the clamping transistor (60) is electrically connected to a gate electrode (26) of the GaN transistor (20), The active clamp circuit (30) a pull-down resistor (32) connected between a source electrode (62) and a gate electrode (63) of the clamping transistor (60); and a clamping capacitor (31) connected between the drain electrode (29) of the GaN transistor (20) and the gate electrode (63) of the clamping transistor (60). semiconductor equipment.
  • Appendix 4 The semiconductor device according to appendix 3, further comprising a capacitor (80) connected between a source electrode (62) and a gate electrode (63) of the clamping transistor (60).
  • both the GaN transistor (20) and the clamping transistor (60) have rectangular active regions ( 20T, 60T),
  • the GaN transistor (20) and the clamping transistor (60) are arranged side by side in the longitudinal direction of the GaN transistor (20) when viewed from the thickness direction (z direction) of the semiconductor substrate (11). cage,
  • the longitudinal direction of the active region (20T) of the GaN transistor (20) and the longitudinal direction of the active region (60T) of the clamping transistor (60) are perpendicular to each other. semiconductor equipment.
  • the clamping capacitor (31) includes a first electrode (31P) and a second electrode (31Q)
  • the pull-down resistor (32) includes a first terminal (32P) and a second terminal (32Q), a first connection wiring (71) electrically connecting the first electrode (31P) of the clamping capacitor (31) and the drain electrode (29) of the GaN transistor (20);
  • the second electrode (31Q) of the clamping capacitor (31) and the first terminal (32P) of the pull-down resistor (32) are electrically connected to the gate electrode (63) of the clamping transistor (60).
  • the semiconductor substrate (11) When viewed from the thickness direction (z direction) of the semiconductor substrate (11), the semiconductor substrate (11) is formed in a rectangular shape having a longitudinal direction and a lateral direction, Both the GaN transistor (20) and the clamping transistor (60) are formed side by side in the longitudinal direction of the semiconductor substrate (11), When viewed from the thickness direction (z direction) of the semiconductor substrate (11), the first connection wiring (71), the second connection wiring (72), the third connection wiring (73), the fourth connection wiring (74) and each of the fifth connection wirings (75) is located closer to the clamping transistor (60) than the longitudinal center of the semiconductor substrate (11) in the longitudinal direction of the semiconductor substrate (11).
  • (Appendix 11) a front side wiring layer (L1) in which the drain pad (51), the source pad (52) and the gate pad (53) are formed;
  • a substrate-side wiring layer (L4) provided on the opposite side of the surface-side wiring layer (L1) with respect to the intermediate wiring layers (L2, L3) and having the GaN transistor (20) formed thereon; each of the clamping transistor (60), the clamping capacitor (31), and the pull-down resistor (32) is provided in the substrate-side wiring layer (L4), according to any one of Appendices 8 to 10 The semiconductor device described.
  • the clamping capacitor (31) is a first electrode (31P) and a second electrode (31Q) provided on the insulating layer (27) and separated from each other; and a dielectric layer (33) provided on the insulating layer (27) and interposed between the first electrode (31P) and the second electrode (31Q).
  • the semiconductor device according to .
  • connection path (32A) electrically connecting the drain electrode (29) of the GaN transistor (20) and the source electrode (62) of the clamping transistor (60);
  • the connection path (32A) includes a meandering portion (32B), 13.
  • the pull-down resistor (32) is a first wiring portion (32PA) forming the first terminal (32P); a second wiring portion (32QA) forming a second terminal (32Q); a plate-like resistor portion (32R) formed on the semiconductor substrate (11) and having a resistance value greater than that of the first wiring portion (32PA) and the second wiring portion (32QA); Both the first wiring portion (32PA) and the second wiring portion (32QA) are provided on the resistance portion (32R) and electrically connected to the resistance portion (32R).
  • the semiconductor device according to any one of .
  • Appendix 16 a semiconductor device (10) according to any one of Appendices 1 to 15; a sealing resin (110) for sealing the semiconductor device (10); a drain terminal (121) exposed from the sealing resin (110) and electrically connected to the drain pad (51); a source terminal (122) exposed from the sealing resin (110) and electrically connected to the source pad (52); A semiconductor module (100) comprising a gate terminal (124) exposed from the sealing resin (110) and electrically connected to the gate pad (53).
  • a plurality of the semiconductor devices (10) are provided, A driver chip (210) including a driver circuit (211) for individually driving the plurality of semiconductor devices (10/10A, 10B), 17.
  • the semiconductor module (200) according to Appendix 16, wherein the sealing resin (220) seals the plurality of semiconductor devices (10/10A, 10B) and the driver chip (210).
  • the plurality of semiconductor devices (10/10A, 10B) are arranged in a first direction, 18.
  • Appendix 19 Any one of Appendices 1 to 15, wherein the clamping transistor (60) is configured to turn on before the GaN transistor (20) when the voltage between the drain and the source of the GaN transistor (20) rises. 1.
  • the configuration of the present disclosure is adopted in a Pad-on-Chip structure in which the source pad and the drain pad are provided directly above the HEMT main structure (active region) instead of being laterally pulled out from the HEMT main structure (active region). good too.
  • Each terminal of the GaN transistor and the clamping transistor may be electrically connected within the package in which the semiconductor device is mounted.
  • Drain electrode 30, 30A, 30B... Active clamp circuit 31 Capacitor for clamping 31P... First electrode 31Q... Second electrode 32... Pull-down resistor 32A... Connection Route 32B Meandering portion 32C Wiring 32P First terminal 32PA First wiring portion 32Q Second terminal 32QA Second wiring portion 32R Resistance portion 32S Third terminal 33 Insulating layer 40 Wiring layer 41 Drain Wiring 42 Main source wiring 43 Sense source wiring 44 Gate wiring 45 Clamping drain wiring 46 Clamping source wiring 47 Clamping gate wiring 51 Drain pad 52 Main source pad 53 Sense source pad 54 Gate Pad 60... Clamping transistor 60T... Active region 61... Drain electrode 62... Source electrode 63... Gate electrode 71... First connection wire 72... Second connection wire 73... Third connection wire 74... Fourth connection wire 75...

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  • Junction Field-Effect Transistors (AREA)
PCT/JP2022/047072 2022-01-28 2022-12-21 半導体装置および半導体モジュール Ceased WO2023145316A1 (ja)

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CN202280089935.4A CN118591889A (zh) 2022-01-28 2022-12-21 半导体装置和半导体模块
DE112022006551.6T DE112022006551T5 (de) 2022-01-28 2022-12-21 Halbleiterbauelement und halbleitermodul
JP2023576699A JPWO2023145316A1 (https=) 2022-01-28 2022-12-21
US18/782,942 US20240379835A1 (en) 2022-01-28 2024-07-24 Semiconductor device and semiconductor module

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187726A (ja) * 2013-03-21 2014-10-02 Toshiba Corp 半導体装置
JP2014187543A (ja) * 2013-03-22 2014-10-02 Toyota Motor Corp 半導体装置
US20170243862A1 (en) * 2016-02-23 2017-08-24 Analog Devices, Inc. Apparatus and methods for robust overstress protection in compound semiconductor circuit applications
JP2020188177A (ja) * 2019-05-16 2020-11-19 ローム株式会社 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6671124B2 (ja) 2015-08-10 2020-03-25 ローム株式会社 窒化物半導体デバイス

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187726A (ja) * 2013-03-21 2014-10-02 Toshiba Corp 半導体装置
JP2014187543A (ja) * 2013-03-22 2014-10-02 Toyota Motor Corp 半導体装置
US20170243862A1 (en) * 2016-02-23 2017-08-24 Analog Devices, Inc. Apparatus and methods for robust overstress protection in compound semiconductor circuit applications
JP2020188177A (ja) * 2019-05-16 2020-11-19 ローム株式会社 半導体装置

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