WO2023142908A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023142908A1
WO2023142908A1 PCT/CN2023/070188 CN2023070188W WO2023142908A1 WO 2023142908 A1 WO2023142908 A1 WO 2023142908A1 CN 2023070188 W CN2023070188 W CN 2023070188W WO 2023142908 A1 WO2023142908 A1 WO 2023142908A1
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WIPO (PCT)
Prior art keywords
display area
touch
display
sub
layer
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PCT/CN2023/070188
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English (en)
French (fr)
Inventor
李泽亮
高涛
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023142908A1 publication Critical patent/WO2023142908A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED organic electroluminescence display
  • an embodiment of the present disclosure provides a display substrate, including:
  • a base substrate including a display area, and a non-display area around the display area;
  • a barrier dam located in the non-display area and at least partially surrounding the display area
  • a power line in the non-display area on one side of the display area, the power line includes a first subsection and a second subsection integrally arranged, the first subsection is on the base substrate
  • the orthographic projection substantially coincides with the orthographic projection of the barrier dam on the base substrate, and the orthographic projection of the second subsection on the substrate substrate is substantially coincident with the orthographic projection of the barrier dam on the substrate substrate.
  • the projections do not overlap each other;
  • An anode conductive layer located on the side of the layer where the power line is located away from the base substrate, the anode conductive layer includes a protective structure at least partially located in the non-display area, and the protective structure covers at least the second At least part of the edge of the division.
  • the protection structure completely covers the second subsection.
  • the protection structure covers the edge of the second subsection and exposes the remaining area of the second subsection.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a first source-drain metal layer located between the base substrate and the anode conductive layer, and the power line includes a The first sub-power line of the first source-drain metal layer.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a second source-drain metal layer located between the first source-drain metal layer and the anode conductive layer;
  • the power supply line further includes a second sub-power supply line located on the second source-drain metal layer, and the second sub-power supply line covers at least an edge of the first sub-power supply line.
  • the second sub-power line completely covers the first sub-power line.
  • the second sub-power line covers the edge of the first sub-power line and exposes the rest of the first sub-power line.
  • the protection structure at least covers at least part of the edge of the second subsection in the second sub-power line.
  • the protection structure further covers at least part of the edge of the first subsection.
  • the power lines include a first-level power line and a second-level power line, wherein the protection structure is at the first level A disconnection is provided at a gap between the power line and the second level power line.
  • edges of the first subsection and/or edges of the second subsection include irregular structures.
  • the edge shape of the protection structure is substantially the same as the edge shape of the second subsection.
  • the non-display area includes: a first non-display area for bonding with a chip, and the first non-display area is included in the The encapsulation area and the water-oxygen isolation area are sequentially arranged in the direction of the display area;
  • the barrier dam in the first non-display area is located in the encapsulation area, and the second subsection is located in the encapsulation area and the water-oxygen isolation area.
  • the first non-display area further includes a fan-out area and a binding area, wherein the fan-out area connects the water-oxygen isolation area and said binding region;
  • the power cord further includes a third subsection located in the fan-out area, and the third subsection is integrated with the second subsection.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a flat layer, the flat layer is located between the layer where the power line is located and the anode conductive layer, and the flat layer is located between the The above fan-out area is set on the whole surface.
  • the protective structure further covers at least part of the edge of the third subsection.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a plurality of touch lines located in the non-display area, and the plurality of touch lines are located in the layer where the barrier dam is located away from the One side of the base substrate; at least part of the orthographic projection of the touch line on the base substrate and the orthographic projection of the power line on the base substrate overlap each other, and the protection structure is at least partially located The overlapping regions.
  • the touch wires include conductive winding parts, so that the resistance of each of the touch wires is approximately the same, and the conductive windings
  • the orthographic projection of the portion on the base substrate is located between the orthographic projection of the barrier dam on the base substrate and the display area.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a bridge layer and a touch layer that are insulated from each other, and the bridge layer is located between the layer where the barrier dam is located and the touch layer;
  • the touch control line includes a first sub-touch line and a second sub-touch line electrically connected to each other, wherein the first sub-touch line is located in the bridging layer, and the second sub-touch line is located in the bridging layer. the touch layer.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a plurality of touch electrodes located in the display area, and the touch electrodes are electrically connected to the touch lines;
  • the electrodes include a first sub-touch electrode and a second sub-touch electrode electrically connected to each other, wherein the first sub-touch electrode is located in the bridging layer, and the second sub-touch electrode is located in the touch layer .
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes an insulating layer located between the touch layer and the bridging layer, the insulating layer includes a plurality of through holes, and the through holes connect The first sub-touch electrodes and the second sub-touch electrodes, and the plurality of through holes are evenly distributed in the display area.
  • the plurality of touch electrodes include a plurality of first touch electrodes extending along the first direction, and a plurality of first touch electrodes extending along the second direction.
  • Two touch electrodes; the plurality of touch lines include a plurality of first touch lines and a plurality of second touch lines; wherein, the first touch electrodes are electrically connected to the first touch lines, so The second touch electrodes are electrically connected to the second touch lines.
  • the non-display area includes a first non-display area and a second non-display area opposite to each other, and a third non-display area opposite to each other. and the fourth non-display area, wherein the first non-display area is used for the first non-display area bound to the chip, the third non-display area and the fourth non-display area are respectively connected to the first non-display area area and the second non-display area;
  • the plurality of second touch lines extend from the third non-display area and the fourth non-display area to the first non-display area;
  • first touch lines are bent and extended to the first non-display area through the second non-display area and the third non-display area in sequence, and the rest of the first touch lines are sequentially passed through the second non-display area.
  • the non-display area and the fourth non-display area extend toward the first non-display area, and in the third non-display area and the fourth non-display area, the first touch line is located at the The side of the second touch line away from the display area.
  • the non-display area includes a first non-display area and a second non-display area opposite to each other, and a third non-display area opposite to each other. and the fourth non-display area, wherein the first non-display area is used for the first non-display area bound to the chip, the third non-display area and the fourth non-display area are respectively connected to the first non-display area area and the second non-display area;
  • the plurality of second touch lines are bent from the fourth non-display area to the first non-display area;
  • Part of the first touch lines are bent and extended toward the first non-display area through the second non-display area and the third non-display area in turn, and the rest of the first touch lines are located in the first non-display area. in the display area.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes at least one touch control chip, and the plurality of touch control lines are bound and connected to the touch control chip.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure.
  • Fig. 1 is the electron micrograph of side corrosion of the power line in the related art
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Fig. 3 is an enlarged structural diagram of the Z1 area in Fig. 2;
  • Fig. 4 is an enlarged structural diagram of the Z2 area in Fig. 3;
  • Fig. 5 is a kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 6 is a kind of sectional view along II-II ' line among Fig. 4;
  • FIG. 7 is an electron microscope image of a power cord provided by an embodiment of the present disclosure without side corrosion
  • FIG. 8 is a schematic diagram of a protective structure covering a power cord provided by an embodiment of the present disclosure.
  • Fig. 9 is a kind of sectional view along III-III ' line in Fig. 8;
  • Fig. 10 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 11 is another kind of sectional view along III-III' line among Fig. 8;
  • Fig. 12 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 13 is another kind of sectional view along III-III' line in Fig. 8;
  • FIG. 14 is another schematic diagram of a protective structure covering a power cord provided by an embodiment of the present disclosure.
  • Fig. 15 is a kind of sectional view along IV-IV' line among Fig. 14;
  • Fig. 16 is another enlarged structural diagram of the Z1 area in Fig. 2;
  • Figure 17 is an enlarged structural diagram of the Z3 area in Figure 16;
  • Fig. 18 is a sectional view along V-V' line among Fig. 17;
  • Fig. 19 is another enlarged structural diagram of the Z2 area in Fig. 3;
  • Fig. 20 is another enlarged structural diagram of the Z2 area in Fig. 3;
  • Fig. 21 is a sectional view along VI-VI " in Fig. 20;
  • Fig. 22 is another enlarged structural diagram of the Z2 area in Fig. 3;
  • Fig. 23 is a sectional view along VII-VII" in Fig. 22;
  • Fig. 24 is another enlarged structural diagram of the Z2 area in Fig. 3;
  • FIG. 25 is an electron micrograph of a short circuit between the bridging layer and the power line in the related art.
  • Fig. 26 is a sectional view along line VIII-XIII in Fig. 24;
  • 27 is a schematic diagram of touch electrodes in the present disclosure.
  • Fig. 28 is a schematic diagram of the bridging layer in Fig. 25;
  • FIG. 29 is a schematic diagram of the touch layer in FIG. 25;
  • FIG. 30 is another schematic structural view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 31 is another schematic structural view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 32 is another schematic structural view of a display substrate provided by an embodiment of the present disclosure.
  • Figure 33 is a partial structural schematic diagram of the barrier dam
  • Fig. 34 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 35 is another kind of sectional view along III-III' line in Fig. 8;
  • Fig. 36 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 37 is another kind of sectional view along III-III' line among Fig. 8;
  • Fig. 38 is another kind of sectional view along IV-IV' line among Fig. 14;
  • Fig. 39 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 40 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 41 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 42 is another kind of sectional view along I-I ' line among Fig. 4;
  • Fig. 43 is another kind of sectional view along III-III' line in Fig. 8;
  • Fig. 44 is another kind of sectional view along III-III' line in Fig. 8;
  • Fig. 45 is another kind of sectional view along III-III' line in Fig. 8;
  • Fig. 46 is another kind of sectional view along III-III' line in Fig. 8;
  • Fig. 47 is another kind of sectional view along line IV-IV' among Fig. 14;
  • Fig. 48 is a schematic structural diagram of a sub-pixel in the display area.
  • the OLED display panel in the related art includes a base substrate, and a driving circuit, a light emitting device, a barrier dam and a power supply line arranged on the base substrate, wherein the driving circuit and the light emitting device are located in the display area, and the barrier dam and the power supply line are located in the non-display area. area, and the barrier dam spans the power line.
  • the power line is usually made of the source-drain metal layer of the transistor contained in the driving circuit
  • the barrier dam is usually made of an organic insulating layer located on the side of the driving circuit away from the substrate. In order to form the barrier dam, the organic insulating layer near the barrier dam needs to be removed, resulting in only the inorganic insulating layer covering the power lines near the barrier dam.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 2 to FIG. 6 , including:
  • the base substrate 101 includes a display area AA and a non-display area BB located around the display area AA;
  • the blocking dam 102 is located in the non-display area BB and arranged around the display area AA;
  • the power line 103 in the non-display area BB on the side of the display area AA, the power line 103 includes a first subsection 103a and a second subsection 103b that are integrally arranged, and the orthographic projection of the first subsection 103a on the base substrate 101 roughly coincides with the orthographic projection of the barrier dam 102 on the base substrate 101, and the orthographic projection of the second subsection 103b on the base substrate 101 does not overlap with the orthographic projection of the barrier dam 102 on the base substrate 101;
  • the anode conductive layer 104 is located on the side of the layer where the power line 103 is away from the substrate 101.
  • the anode conductive layer 104 includes a protective structure 1041 at least partially located in the non-display area BB, and the protective structure 1041 covers at least the second subsection 103b. Part of the edge, further, the protection structure 1041 covers at least the edge of the second subsection 103b, which is equivalent to at least the side surface of the protection structure 1041 and the second subsection 103b, and the part of the upper surface adjacent to the side surface (that is, away from the base substrate 101 part of the surface on one side) contact setting.
  • the second subsection 103b of the power line 103 is not covered by the barrier dam 102, and the protection structure 1041 covering at least part of the edge of the second subsection 103b is provided in the present disclosure, Further, a protection structure 1041 covering at least the edge of the second subsection 103b is also included.
  • the protective structure 1041 is located on the anode conductive layer 104, so that the anode of the anode conductive layer 104 and the protective structure 1041 can be prepared by the same etching process, thereby avoiding the etching solution used in the anode etching process. Corrosion of the edge of the second subsection 103b; and, because the first subsection 103a is covered by the barrier dam 102 in the power line 103, so the barrier dam 102 can play a protective role to the first subsection 103a, so that the first subsection 103a is free from It is corroded by the etching solution used in the anode, thus effectively improving the reliability of the packaging and solving the problem of dark spots.
  • the present disclosure also sprays a layer of platinum (Pt) on the power line 103 covered by the protective structure 1041 , and the result is shown in FIG. 7 . It can be seen from FIG. 7 that the platinum (Pt) is not broken on the side of the power line 103 (SD) (the dotted frame area in FIG. 7 ), thus confirming that the protection structure 1041 has well prevented side corrosion.
  • the edge of the second subsection 103b is protected by the protective structure 1041 of the anode conductive layer 104, there is no need to set the inorganic insulating layer used to protect the power line 103 in the related art, thereby saving the cost of the inorganic insulating layer.
  • the mask process reduces the number of film layers, which is conducive to improving production efficiency, reducing production costs, and thinning and thinning the design of products.
  • At least part of the edge of the first subsection 103a may also be provided with a protection structure 1041 to further prevent the first subsection 103a from being corroded by the etching solution used for the anode.
  • the barrier dam 102 may include a first barrier dam 102' and a second barrier dam 102", the second barrier 102 "encloses the first barrier dam 102', and the first barrier dam 102' and the second barrier dam 102" can be a multi-film layer structure, and the multi-film layers are respectively located in the first flat layer (PLN1), the second flat layer (PLN2 ), the pixel definition layer (PDL) and the support layer (PS), to maximize the extension of the water and oxygen invasion path and improve the packaging reliability.
  • PLL first flat layer
  • PDL pixel definition layer
  • PS support layer
  • the barrier dam 102 is not limited to the above-mentioned film layer structure, and can include and The at least one layer structure that the film layer in the display area AA is arranged on the same layer.
  • the barrier dam 102 can also be one, or more than two, and the film layer composition of each barrier dam 102 can be the same or different, and the number of film layers can be the same or Different heights can be the same or different.
  • Barrier dam 102 may be a fully enclosed structure or include partially discontinuous voids.
  • at least one barrier dam 102 of the display substrate is bifurcated to form two sub-dams dam near the first non-display area BB1, and the left and right sides of the barrier dam 102 are Can be substantially symmetrical.
  • at least one blocking dam 102 forms two sub-blocking portions dam between the display area AA and the bending area BD, which is more helpful to prevent the first planar layer ( PLN1 ) from entering the bending area BD.
  • the barrier dams 102 close to the display area AA can be bifurcated to form two sub-dams dam near the first non-display area BB1 .
  • the display substrate includes a first barrier dam 102' and a second barrier dam 102' located on the side away from the display area AA of the first barrier dam 102'.
  • the first barrier dam 102' is close to A portion of the first non-display area BB1 is bifurcated to form two sub-blocking portions dam.
  • the barrier dam 102 is discontinuous in the non-display area, that is, the barrier dam 102 is provided with gaps 1023 in some positions of the non-display area.
  • the barrier dam 102 includes a first barrier segment 1021 and a second barrier segment 1022, the first barrier segment 1021 and the second barrier segment 1022 are arranged at intervals, the gap between the first barrier segment 1021 and the second barrier segment 1022 A gap 1023 is formed between them.
  • the display substrate further includes a buffer portion 1023' located on the side of the first barrier segment 1021 away from the display area AA, and the gap 1023 between the first barrier segment 1021 and the second barrier segment 1022 is opposite to the buffer portion 1023'.
  • Fig. 33 only shows a partial structure of the barrier dam 102.
  • the barrier dam 102 can form gaps 1023 in multiple places, and each gap 1023 can be provided with a buffer portion 1023' on the side away from the display area AA.
  • the two ends of the buffer portion 1023' are bent towards the display area AA, so as to further slow down the overflowing speed of the organic material.
  • the length of the buffer portion 1023' may be greater than the size of the gap 1023 between the first blocking section 1021 and the second blocking section 1022, so as to more effectively slow down the overflow of organic materials.
  • the buffer portion 1023' can be in a wave shape, a straight line shape, a broken line shape, an arc shape, etc.
  • the protective structure 1041 can completely cover the second subsection 103b; or, as shown in FIG. 8 and FIG. 9 , the protection structure 1041 may cover the edge of the second subsection 103b and expose the remaining area of the second subsection 103b. In FIG. 4 , FIG. 5 , FIG. 8 and FIG. 9 , the protection structure 1041 covers the edge of the second subsection 103b, so as to effectively prevent the side corrosion of the second subsection 103b.
  • the anode conductive layer 104 in the related art is a laminated structure composed of indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), and the resistance value of indium tin oxide is relatively large, so the anode conductive layer 104 The larger the covering area of the second subsection 103b by the protection structure 1041 is, the greater the overall resistance of the second subsection 103b and the protection structure 1041 is, and a larger resistance will cause loss of the power signal during transmission.
  • ITO/Ag/ITO indium tin oxide
  • the protection structure 1041 when the protection structure 1041 only covers the edge of the second subsection 103b and exposes the rest of the second subsection 103b, the covering area of the protection structure 1041 can be effectively reduced, thereby facilitating the reduction of the contact between the second subsection 103b and the protection.
  • the overall resistance of the structure 1041 ensures the authenticity of the power signal.
  • the power supply line 103 may include a first sub-power supply line 1031 located on the first source-drain metal layer (SD1).
  • SD1 first source-drain metal layer
  • the second The production of the first sub-power line 1031 can avoid separately setting the film layer of the first sub-power line 1031 , reducing the number of film layers, which is beneficial to the light and thin design of the product.
  • the first source-drain metal layer (SD1) may be a laminated structure composed of titanium/aluminum/titanium (Ti/Al/Ti).
  • the power line 103 may further include a second Source-drain metal layer (SD2); the power line 103 may also include a second sub-power line 1032 located in the second source-drain metal layer (SD2), and the second sub-power line 1032 covers at least part of the first sub-power line 1031 edge.
  • the power line 103 adopts a double-layer structure of the first sub-power line 1031 and the second sub-power line 1032, which is beneficial to reduce the overall resistance of the power line 103 and ensure the authenticity of the power signal.
  • the second source-drain metal layer (SD2) may be a laminated structure composed of titanium/aluminum/titanium (Ti/Al/Ti).
  • FIG. 34 to FIG. 47 it may further include a third source-drain metal layer (SD3) located between the second source-drain metal layer (SD2) and the anode conductive layer 104;
  • the power supply line 103 may further include a third sub-power supply line 1033 located on the third source-drain metal layer (SD3), the third sub-power supply line 1033 covers at least part of the edge of the first sub-power supply line 1031, for example, the third sub-power supply line 1033 covers at least the edge of the first sub-power line 1031 .
  • the power line 103 adopts a double-layer structure of the first sub-power line 1031 and the third sub-power line 1032 (as shown in Figure 34 to Figure 38), or adopts the first sub-power line 1031, the second The three-layer structure of the sub-power line 1033 (as shown in FIG. 39 to FIG. 47 ) is beneficial to reduce the overall resistance of the power line 103 and ensure the authenticity of the power signal.
  • the second sub power line 1032 can completely cover the first sub power line 1031; or, as shown in FIG.
  • the second sub-power line 1032 can cover the edge of the first sub-power line 1031 and expose the rest of the first sub-power line 1031; The overall resistance ensures the authenticity of the power signal.
  • the second sub-power line 1032 can also only cover the position of the second sub-power line 1031 in the second sub-power line 1031, and disconnect the position of the first sub-power line 1031 in the first sub-power line 1031, here No limit.
  • the edge of the second sub-section 103b in the sub-power line 1031 for example, in FIG. 5, the protective structure 1041 completely covers the edge of the second sub-section 103b in the first sub-power line 1031; The edge of the first sub-power line 1031 is covered and the remaining area of the first sub-power line 1031 is exposed.
  • the second sub-power line 1032 covers at least the edge of the first sub-power line 1031.
  • the edge of the second sub-power line 1032 needs to be protected, that is, the protection structure 1041 needs to cover at least the edge of the second sub-power line 1032 .
  • the second sub-power line 1032 completely covers the edge of the first sub-power line 1031; in Figures 12 to 13, the second sub-power line 1032 covers the first sub-power line 1031 and exposes the rest of the first sub-power line 1031 .
  • the protective structure 1041 completely covers the edge of the second subsection 103b in the first sub-power line 1031 and the second sub-power line 1032; in FIG. 11 , FIG. 14 and FIG. 15 , The protection structure 1041 covers the edge of the second sub-section 103b in the second sub-power line 1032 and exposes the remaining area of the second sub-section 103b in the second sub-power line 1032, and in FIGS. 14 and 15 the protection structure 1041 also Part of the non-edge area of the second sub-section 103b in the first sub-power line 1031 is exposed; in FIG. Part of the non-edge area of the second subsection 103b in the sub-power line 1031 .
  • the protective structure 1041 can completely cover the first sub-power line 1031 , the second sub-power line 1032 and the third sub-power line 1033; or, as shown in FIGS. The edge not covered by the third sub-power line 1033 .
  • the structure 1041 covers at least the edge of the first subsection 103a.
  • the protective structure 1041 can also completely cover the edge of the first subsection 103a, or the protective structure 1041 covers the edge of the first subsection 103a and exposes the first subsection 103a.
  • the remaining area of the subsection 103a, that is to say, the protective structure 1041 may be continuously arranged at least at the edges of the first subsection 103a and the second subsection 103b.
  • the continuous arrangement of the protective structure 1041 is beneficial to the production of the protective structure 1041 on the one hand;
  • the protection structure 1041 is added, so that the height of the barrier dam 102 is increased due to the existence of the protection structure 1041, thereby better blocking the intrusion of water and oxygen, and effectively improving the packaging reliability.
  • the power line 103 may include a first-level power line VDD and a second-level power line VSS, wherein, The protection structure 1041 is disconnected at the gap between the first-level power supply line VDD and the second-level power supply line VSS, so as to ensure the independent transmission of the first-level power supply signal and the second-level power supply signal, and avoid the two interfere with each other.
  • the edge of 103b may include an irregular structure (for example, a wavy structure), so as to prolong the intrusion path of water and oxygen and improve packaging reliability.
  • the edge shape of the protective structure 1041 can be roughly the same as the edge shape of the second subsection 103b The same (that is, they may be exactly the same, and there may be errors caused by manufacturing processes, etc.).
  • the edge shape of the protection structure 1041 may also be linear, which is not limited here.
  • the non-display area BB may include: The first non-display area BB1, the first non-display area BB1 includes encapsulation area BB101 and water-oxygen isolation area BB102 arranged in sequence in the direction away from the display area AA; the barrier dam 102 in the first non-display area BB1 is located in the encapsulation area BB101 and the second subsection 103b are located in the packaging area BB101 and the water-oxygen isolation area BB102 to better prevent water and oxygen intrusion and effectively improve packaging reliability.
  • fan-out area BB103 connects water-oxygen isolation area BB102 and binding area BB104; It is integrally arranged with the second subsection 103b, so as to be bound to the chip after extending to the binding area BB104 through the power line 103, so as to realize that the chip provides a power signal for the power line 103.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may further include a flat layer 105 (namely, the above-mentioned second flat layer PLN2), the flat layer 105 is located on the power line 103 is located between the layer and the anode conductive layer 104, and the flat layer 105 is provided on the entire surface of the fan-out region BB103, so as to protect the third subsection 103c through the flat layer 105 and prevent the etching solution used for the anode from causing side effects on the third subsection 103c. corrosion.
  • a flat layer 105 namely, the above-mentioned second flat layer PLN2
  • the flat layer 105 is located on the power line 103 is located between the layer and the anode conductive layer 104
  • the flat layer 105 is provided on the entire surface of the fan-out region BB103, so as to protect the third subsection 103c through the flat layer 105 and prevent the etching solution used for the anode from causing side effects on the
  • the protective structure 1041 can also cover at least the edge of the third subsection 103c, for example, the protective structure 1041 completely covers The edge of the third subsection 103c, or the protective structure 1041 covers the edge of the third subsection 103c and exposes the rest of the third subsection 103c, so that the third subsection 103c is protected by the protective structure 1041, avoiding the engraving of the anode
  • the etching solution causes side corrosion to the third subsection 103c.
  • the layer where the barrier dam 102 is located is away from the side of the base substrate 101 ; at least part of the orthographic projection of the touch line 106 on the base substrate 101 overlaps with the orthographic projection of the power line 103 on the base substrate 101 .
  • the protective structure is at least partially located in the mutually overlapping regions.
  • the power line 103 (SD) in the related art has poor side corrosion, and when the buffer layer (Buffer, BFR) is subsequently deposited, the buffer layer (BFR) will be corroded on the side (as shown in the dotted line box in the figure) will be broken, resulting in a short circuit (Short) between the touch line 106 of the bridge layer (M1) and the power line 103 (SD) after the coating of the bridging layer (M1) on the buffer layer is completed.
  • the protective structure 1041 is used to cover at least the edge of the second subsection 103b to avoid side corrosion of the power line 103 , thus effectively preventing the short circuit between the touch line 106 and the power line 103 .
  • the touch wires 106 include a conductive winding part C, so that the resistance of each touch wire 106 is approximately the same, That is, the resistance difference of each touch wire 106 is within an acceptable range (for example, ⁇ 10%), and the orthographic projection of the conductive winding part C on the base substrate 101 is located at the orthographic projection of the barrier dam 102 on the base substrate 101 and display area AA.
  • the resistance of each touch line 106 can be roughly the same, ensuring that the signal delay (RC delay) effect of each touch line 106 is basically the same, so that The magnitudes of the signals loaded on the touch electrodes 107 electrically connected to 106 are substantially the same, thereby improving the impact of the large resistance difference of each touch line 106 on touch control, which is beneficial to improving touch performance.
  • the conductive winding part C of the present disclosure is disposed in the area between the barrier dam 102 and the display area AA, so that the space inside the barrier dam 102 can be reasonably utilized, so that there is no need to increase the width of the non-display area BB.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may further include a bridge layer (M1) and a touch layer (M2) that are insulated from each other, and the bridge layer (M1 ) is located between the layer where the barrier dam 102 is located and the touch layer (M2);
  • the touch line 106 includes a first sub-touch line 1061 and a second sub-touch line 1062 electrically connected to each other, wherein the first sub-touch line 1061 is located in the bridging layer (M1), and the second sub-touch line 1062 is located in the touch layer (M2).
  • This double-layer wiring method of the touch line 106 can not only effectively reduce the resistance of the touch line 106, but also make the After one layer of wires is partially broken, the continuity of the touch wire 106 can still be ensured through another layer of wires, thereby effectively solving the problem that a single layer of wires is easily broken and causes touch failure.
  • a via hole may be provided in the insulating layer between the bridging layer (M1) and the touch layer (M2) at a preset distance (for example, 100 ⁇ m) in the non-display area BB, so that the touch line 106 The two layers of wiring are electrically connected through the via.
  • FIG. 27 to FIG. The touch line 106 is electrically connected; the touch electrode 107 includes a first sub-touch electrode 1071 and a second sub-touch electrode 1072 electrically connected to each other, wherein the first sub-touch electrode 1071 is located in the bridging layer (M1), and the second The sub-touch electrodes 1072 are located on the touch layer (M2).
  • the double-layer arrangement of the touch electrodes 107 can not only effectively reduce the resistance of the touch electrodes 107, but also make it possible to pass through another layer of touch electrodes 107 after a partial break of one of the sub-touch electrodes 107.
  • a via hole V may be provided in the insulating layer between the bridging layer (M1) and the touch layer (M2) at a predetermined distance (for example, 100 ⁇ m) in the display area AA, so that the first sub-contact The control electrode 1071 and the second sub-touch electrode 1072 are electrically connected through the through hole V.
  • the present disclosure can realize the touch function by using the touch layer (M2) and the bridging layer (M1) in the display substrate, there is no need for an external touch module (TSP), so that the thickness of the display substrate can be reduced, and further Facilitates folding; at the same time, there is no fit tolerance, which can reduce the border width.
  • TSP external touch module
  • FIG. AA in the above-mentioned display substrate provided by the embodiments of the present disclosure, as shown in FIG. AA is evenly distributed to improve the visible afterimage of the through hole V and achieve the effect of eliminating the image on the through hole V.
  • the plurality of touch electrodes 107 may include a plurality of first touch electrodes 107 ′ extending along the first direction Y, and A plurality of second touch electrodes 107" extending along the second direction X; the plurality of touch lines 106 includes a plurality of first touch lines 106' and a plurality of second touch lines 106"; wherein, the first touch The electrode 107' is electrically connected to the first touch line 106', and the second touch electrode 107" is electrically connected to the second touch line 106".
  • the first touch electrodes 107' may be touch drive electrodes (Tx), and the first touch lines 106' are correspondingly touch drive lines;
  • the second The touch electrode 107" can be a touch sensing electrode (Rx), and the second touch line 106" is a touch sensing line accordingly; or, the first touch electrode 107' is a touch sensing electrode, and the first touch line 106 ′ is correspondingly a touch sensing line;
  • the second touch electrode 107 ′′ is a touch driving electrode, and the second touch line 106 ′′ is correspondingly a touch driving line.
  • first touch electrodes 107' extending along the first direction Y are disconnected by the second touch electrodes 107" extending along the second direction X in the same layer. Therefore, in order to ensure that the first touch electrodes 107'
  • the continuity of the disconnected second touch electrodes 107 ′′ can be connected by using the bridging portion BD of the bridging layer ( M1 ).
  • the non-display area BB may include a first non-display area BB1 and a second non-display area BB2 opposite , and the third non-display area BB3 and the fourth non-display area BB4 facing each other, wherein, the first non-display area BB1 is used for the first non-display area BB1 bound with the chip, the third non-display area BB3, the first non-display area BB1
  • the four non-display areas BB4 are respectively connected to the first non-display area BB1 and the second non-display area BB2; when the size of the display substrate is large (for example, the display substrate is a notebook, etc.), more touch electrodes 107 need to be provided, correspondingly More touch lines 106 are needed.
  • the non-display area BB1 extends; some of the first touch lines 106' are folded and extended to the first non-display area BB1 through the second non-display area BB2 and the third non-display area BB3 in sequence, and the rest of the first touch lines 106' are sequentially passed through the second non-display area BB1
  • the second non-display area BB2 and the fourth non-display area BB4 extend toward the first non-display area BB1, and in the third non-display area BB3 and the fourth non-display area BB4, the first touch line 106' is located on the second touch line.
  • the control line 106" is away from the side of the display area AA.
  • a plurality of second touch lines 106" can be folded from the fourth non-display area BB4 to extend to the first non-display area BB1; part of the first touch lines 106' can pass through the second non-display area BB2 and the third non-display area in sequence BB3 is folded and extended toward the first non-display area BB1, and the remaining first touch lines 106' may be located in the first non-display area BB1.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may further include at least one touch chip 108 , and a plurality of touch lines 106 are bonded to the touch chip 108 .
  • the touch chip 108 can be a chip-on-film (COF).
  • the driving circuit layer is located on the base substrate 101 , and a pixel circuit 109 of a sub-pixel is arranged in the driving circuit layer, and the pixel circuit 109 is used to drive the sub-pixel to emit light.
  • the pixel circuit includes a transistor TFT, and may also include a capacitor Cst.
  • the pixel circuit 109 may be a 1T pixel circuit, a 2T1C pixel circuit, a 3T1C pixel circuit, a 4T1C pixel circuit, a 5T1C pixel circuit, a 6T1C pixel circuit or a 7T1C pixel circuit.
  • the light emitting layer EL is located on the side of the driving circuit layer 109 away from the base substrate 101 .
  • the light emitting layer EL may include red sub-pixels R, green sub-pixels G and blue sub-pixels B, but not limited thereto.
  • the red sub-pixel R is used to emit red light
  • the green sub-pixel G is used to emit green light
  • the blue sub-pixel B is used to emit blue light.
  • the light emitting layer EL is an organic light emitting layer.
  • the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B are all OLED (Organic Light Emitting Diode) sub-pixels.
  • the encapsulation layer 110 is located on the side of the light-emitting layer EL away from the base substrate 101 to prevent water and oxygen from corroding the light-emitting layer.
  • the encapsulation layer 110 includes a first inorganic encapsulation layer 1101, an organic encapsulation layer 1102, and a second inorganic encapsulation layer 1103.
  • the first inorganic encapsulation layer 1101 is located on the side of the light-emitting layer EL away from the substrate 101, and the organic encapsulation layer 1102 is located on the first inorganic encapsulation layer 1102.
  • the encapsulation layer 1101 is located on a side away from the base substrate 101
  • the second inorganic encapsulation layer 1103 is located on a side of the organic encapsulation layer 1102 away from the base substrate 101 .
  • the organic encapsulation layer 1102 may be formed using an inkjet printing (IJP) process.
  • the display substrate can also include a cathode CAD, a gate insulating layer GI, a first interlayer dielectric layer ILD1 and a second interlayer dielectric layer ILD2, etc., and other essential components of the display substrate are those of ordinary skill in the art. It should be understood that what is there is not described in detail here, nor should it be used as a limitation to the present disclosure.
  • the present disclosure also provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure, and the display substrate may be a display substrate such as an OLED or a QLED. Since the problem-solving principle of the display device is similar to that of the above-mentioned display substrate, the implementation of the display device can refer to the above-mentioned embodiment of the display substrate, and repeated descriptions will not be repeated.
  • the above-mentioned display devices provided by the embodiments of the present disclosure may be: mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, smart watches, fitness wristbands, personal digital assistants, etc A product or part showing a function.
  • the display device provided by the embodiments of the present disclosure may also include but not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply.
  • a radio frequency unit a radio frequency unit
  • a network module a network module
  • an audio output unit an input unit
  • a sensor a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor a processor
  • a power supply Those skilled in the art can understand that the composition of the above display device does not constitute a limitation on the display device, and the display device may include more or less of the above components,

Abstract

本公开提供的显示基板及显示装置，包括衬底基板，包括显示区、以及位于显示区周围的非显示区；阻挡坝，位于非显示区并至少部分围绕显示区设置；电源线，在显示区一侧的非显示区内，电源线包括一体设置的第一分部和第二分部，第一分部在衬底基板上的正投影与阻挡坝在衬底基板上的正投影大致重合，第二分部在衬底基板上的正投影与阻挡坝在衬底基板上的正投影互不交叠；阳极导电层，位于电源线所在层远离衬底基板的一侧，阳极导电层包括至少部分位于非显示区的保护结构，保护结构至少包覆第二分部的至少部分边缘。

Description

显示基板及显示装置
相关申请的交叉引用
本公开要求在2022年01月26日提交中国专利局、申请号为202210096252.3、申请名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
近年来，有机电致发光显示器(OLED)作为一种新型的平板显示逐渐受到更多的关注。由于其具有主动发光、发光亮度高、分辨率高、视角广、响应速度快、厚度小、低能耗、可柔性化、使用温度范围广、构造及制程较简单等优异特性等特点，应用前景广阔。
发明内容
本公开实施例提供的显示基板及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，包括显示区、以及位于所述显示区周围的非显示区；
阻挡坝，位于所述非显示区并至少部分围绕所述显示区设置；
电源线，在所述显示区一侧的所述非显示区内，所述电源线包括一体设置的第一分部和第二分部，所述第一分部在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影大致重合，所述第二分部在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影互不交叠；
阳极导电层，位于所述电源线所在层远离所述衬底基板的一侧，所述阳 极导电层包括至少部分位于所述非显示区的保护结构，所述保护结构至少包覆所述第二分部的至少部分边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结构完全包覆所述第二分部。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结构包覆所述第二分部的边缘且暴露出所述第二分部的其余区域。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述衬底基板与所述阳极导电层之间的第一源漏金属层，所述电源线包括位于所述第一源漏金属层的第一子电源线。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一源漏金属层与所述阳极导电层之间的第二源漏金属层；
所述电源线还包括位于所述第二源漏金属层的第二子电源线，所述第二子电源线至少包覆所述第一子电源线的边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二子电源线完全包覆所述第一子电源线。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二子电源线包覆所述第一子电源线的边缘且暴露出所述第一子电源线的其余区域。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结构至少包覆所述第二子电源线中所述第二分部的至少部分边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结构还至少包覆所述第一分部的至少部分边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述电源线包括第一电平电源线和第二电平电源线，其中，所述保护结构在所述第一电平电源线和所述第二电平电源线之间的间隙处断开设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一分部的边缘和/或所述第二分部的边缘包括不规则结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结 构的边缘形状与所述第二分部的边缘形状大致相同。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述非显示区包括：用于与芯片绑定的第一非显示区，所述第一非显示区包括在远离所述显示区的方向上依次设置的封装区和水氧隔离区；
在所述第一非显示区内的所述阻挡坝位于所述封装区，所述第二分部位于所述封装区和所述水氧隔离区。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一非显示区还包括扇出区和绑定区，其中，所述扇出区连接所述水氧隔离区和所述绑定区；
所述电源线还包括位于所述扇出区的第三分部，且所述第三分部与所述第二分部一体设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括平坦层，所述平坦层位于所述电源线所在层与所述阳极导电层之间，且所述平坦层在所述扇出区整面设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述保护结构还至少包覆所述第三分部的至少部分边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括多条触控线，位于所述非显示区，所述多条触控线位于所述阻挡坝所在层远离所述衬底基板的一侧；至少部分所述触控线在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影相互交叠，所述保护结构至少部分位于所述相互交叠的区域。
在一些实施例中，在本公开实施例提供的上述显示基板中，至少部分所述触控线包括导电绕线部，以使各条所述触控线的电阻大致相同，所述导电绕线部在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括相互绝缘的桥接层和触控层，所述桥接层位于所述阻挡坝所在层与所述触控层之 间；
所述触控线包括相互电连接的第一子触控线和第二子触控线，其中，所述第一子触控线位于所述桥接层，所述第二子触控线位于所述触控层。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述显示区的多个触控电极，所述触控电极与所述触控线电连接；所述触控电极包括相互电连接的第一子触控电极和第二子触控电极，其中，所述第一子触控电极位于所述桥接层，所述第二子触控电极位于所述触控层。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述触控层和桥接层之间的绝缘层，所述绝缘层包括多个通孔，所述通孔连接所述第一子触控电极和所述第二子触控电极，且所述多个通孔在所述显示区均匀分布。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多个触控电极包括多个沿第一方向延伸的第一触控电极、以及多个沿第二方向延伸的第二触控电极；所述多条触控线包括多条第一触控线和多条第二触控线；其中，所述第一触控电极与所述第一触控线电连接，所述第二触控电极与所述第二触控线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述非显示区包括相对而置的第一非显示区和第二非显示区，以及相对而置的第三非显示区和第四非显示区，其中，所述第一非显示区用于与芯片绑定的第一非显示区，所述第三非显示区、所述第四非显示区分别连接第一非显示区和第二非显示区；
所述多条第二触控线自所述第三非显示区和所述第四非显示区折向所述第一非显示区延伸；
部分所述第一触控线依次经所述第二非显示区和所述第三非显示区折向所述第一非显示区延伸，其余所述第一触控线依次经所述第二非显示区和所述第四非显示区折向所述第一非显示区延伸，且在所述第三非显示区和所述第四非显示区内，所述第一触控线位于所述第二触控线远离所述显示区的一 侧。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述非显示区包括相对而置的第一非显示区和第二非显示区，以及相对而置的第三非显示区和第四非显示区，其中，所述第一非显示区用于与芯片绑定的第一非显示区，所述第三非显示区、所述第四非显示区分别连接第一非显示区和第二非显示区；
所述多条第二触控线自所述第四非显示区折向所述第一非显示区延伸；
部分所述第一触控线依次经所述第二非显示区和所述第三非显示区折向所述第一非显示区延伸，其余所述第一触控线位于所述第一非显示区内。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括至少一个触控芯片，所述多条触控线与所述触控芯片绑定连接。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。
附图说明
图1为相关技术中电源线发生侧面腐蚀的电镜图；
图2为本公开实施例提供的显示基板的一种结构示意图；
图3为图2中Z1区域的一种放大结构图；
图4为图3中Z2区域的一种放大结构图；
图5为沿图4中I-I’线的一种剖面图；
图6为沿图4中II-II’线的一种剖面图；
图7为本公开实施例提供的电源线未发生侧面腐蚀的电镜图；
图8为本公开实施例提供的保护结构包覆电源线的一种示意图；
图9为沿图8中III-III’线的一种剖面图；
图10为沿图4中I-I’线的又一种剖面图；
图11为沿图8中III-III’线的又一种剖面图；
图12为沿图4中I-I’线的又一种剖面图；
图13为沿图8中III-III’线的又一种剖面图；
图14为本公开实施例提供的保护结构包覆电源线的又一种示意图；
图15为沿图14中IV-IV’线的一种剖面图；
图16为图2中Z1区域的又一种放大结构图；
图17为图16中Z3区域的放大结构图；
图18为沿图17中V-V’线的剖面图；
图19为图3中Z2区域的又一种放大结构图；
图20为图3中Z2区域的又一种放大结构图；
图21为沿图20中VI-VI”的剖面图；
图22为图3中Z2区域的又一种放大结构图；
图23为沿图22中VII-VII”的剖面图；
图24为图3中Z2区域的又一种放大结构图；
图25为相关技术中桥接层与电源线短接的电镜图；
图26为沿图24中VIII-XIII”线的剖面图；
图27为本公开中触控电极的示意图；
图28为图25中桥接层的示意图；
图29为图25中触控层的示意图；
图30为本公开实施例提供的显示基板的又一种结构示意图；
图31为本公开实施例提供的显示基板的又一种结构示意图；
图32为本公开实施例提供的显示基板的又一种结构示意图；
图33为阻挡坝的局部结构示意图；
图34为沿图4中I-I’线的又一种剖面图；
图35为沿图8中III-III’线的又一种剖面图；
图36为沿图4中I-I’线的又一种剖面图；
图37为沿图8中III-III’线的又一种剖面图；
图38为沿图14中IV-IV’线的又一种剖面图；
图39为沿图4中I-I’线的又一种剖面图；
图40为沿图4中I-I’线的又一种剖面图；
图41为沿图4中I-I’线的又一种剖面图；
图42为沿图4中I-I’线的又一种剖面图；
图43为沿图8中III-III’线的又一种剖面图；
图44为沿图8中III-III’线的又一种剖面图；
图45为沿图8中III-III’线的又一种剖面图；
图46为沿图8中III-III’线的又一种剖面图；
图47为沿图14中IV-IV’线的又一种剖面图；
图48为显示区中一个子像素的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
相关技术中的OLED显示面板包括衬底基板，以及在衬底基板上设置的驱动电路、发光器件、阻挡坝和电源线，其中驱动电路和发光器件位于显示区，阻挡坝和电源线位于非显示区，且阻挡坝跨越电源线。电源线通常采用 驱动电路中所含晶体管的源漏金属层制作，阻挡坝通常采用位于驱动电路远离衬底基板一侧的有机绝缘层制作。为了形成阻挡坝，需要去除阻挡坝附近的有机绝缘层，导致阻挡坝附近的电源线上仅覆盖有无机绝缘层。在后续制作转接电极(CE，用于连接驱动电路和发光器件)的过程中，需要通过刻蚀工艺形成转接电极(CE)，但该刻蚀工艺会对无机绝缘层造成过刻而暴露出电源线的侧面。发光器件所含阳极(AND)的刻蚀液会与暴露出的电源线侧面接触，造成侧面腐蚀(undercut)，如图1所示。具体地，图1中的铂(Pt)是为了测试电源线(SD)的侧面腐蚀现象而喷涂的。由图1可见，铂(Pt)在电源线(SD)的侧面(图1中虚线框区域)发生了断裂，因此证实了侧面腐蚀的存在。在电源线的侧面被腐蚀后，水氧沿电源线被腐蚀的侧面传入显示区，则会导致封装信赖性失效(GDSX)，出现暗点不良。
为了解决相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图2至图6所示，包括：
衬底基板101，包括显示区AA、以及位于显示区AA周围的非显示区BB；
阻挡坝102，位于非显示区BB并围绕显示区AA设置；
电源线103，在显示区AA一侧的非显示区BB内，电源线103包括一体设置的第一分部103a和第二分部103b，第一分部103a在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影大致重合，第二分部103b在衬底基板101上的正投影与阻挡坝102在衬底基板101上的正投影互不交叠；
阳极导电层104，位于电源线103所在层远离衬底基板101的一侧，阳极导电层104包括至少部分位于非显示区BB的保护结构1041，保护结构1041至少包覆第二分部103b的至少部分边缘，进一步的，保护结构1041至少包覆第二分部103b的边缘，相当于保护结构1041至少与第二分部103b的侧面、以及该侧面邻近的部分上表面(即远离衬底基板101一侧的部分表面)接触设置。
在本公开实施例提供的上述显示基板中，电源线103的第二分部103b未被阻挡坝102覆盖，本公开中设置了至少包覆第二分部103b的至少部分边缘 的保护结构1041，进一步的，还包括至少包覆第二分部103b的边缘的保护结构1041。
在一些实施例中，保护结构1041位于阳极导电层104，使得可通过同一刻蚀工艺制备阳极导电层104的阳极和保护结构1041，从而避免了在阳极的刻蚀工艺过程中所用刻蚀液对第二分部103b边缘的腐蚀；并且，因电源线103中第一分部103a被阻挡坝102覆盖，所以阻挡坝102可对第一分部103a起到保护作用，使得第一分部103a免受阳极所用刻蚀液的腐蚀，从而有效提高了封装信赖性，解决了暗点不良。为了测试电源线103(SD)的是否发生了侧面腐蚀，本公开还在被保护结构1041包覆电源线103上喷涂了一层铂(Pt)，结果如图7所示。由图7可见，铂(Pt)在电源线103(SD)的侧面(图7中虚线框区域)未发生断裂，因此证实了保护结构1041很好地防止了侧面腐蚀。
另外，由于采用阳极导电层104的保护结构1041对第二分部103b的边缘进行了保护，因此，无需设置相关技术中用于保护电源线103的无机绝缘层，由此节省了无机绝缘层的掩膜工艺，且减少了膜层数量，利于提高生产效率，降低生产成本，以及产品的轻薄化设计。
在一些实施例中，第一分部103a的至少部分边缘还可以设置有保护结构1041，进一步使得第一分部103a免受阳极所用刻蚀液的腐蚀。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图6所示，阻挡坝102可以包括第一阻挡坝102’和第二阻挡坝102”，第二阻挡坝102”包围第一阻挡坝102’，第一阻挡坝102’和第二阻挡坝102”可以为多膜层结构，该多膜层分别位于第一平坦层(PLN1)、第二平坦层(PLN2)、像素界定层(PDL)和支撑层(PS)，以最大化延长水氧侵路径，提高封装信赖性。当然，在具体实施时，阻挡坝102不局限与上述膜层结构，可以包括与显示区AA中的膜层同层设置的至少一层结构。阻挡坝102还可以为一个、或多于两个，每个阻挡坝102的膜层组成可以相同或不同，膜层数可以相同或不同，高度可以相同或不同。
阻挡坝102可以为全封闭式结构或包括部分不连续的空隙。在一些实施例中，如图32所示，所述显示基板的至少一个阻挡坝102在靠近第一非显示区BB1的部分分叉形成两个子阻挡部dam，且该阻挡坝102的左右相侧可基本对称。如此至少一个阻挡坝102在显示区AA与弯折区BD之间形成两个子阻挡部dam，更有助于阻止所述第一平坦层(PLN1)进入所述弯折区BD。所述显示基板包括两个或两个以上阻挡坝102时，靠近显示区AA的阻挡坝102在靠近第一非显示区BB1的部分可分叉形成两个子阻挡部dam。图32所示的实施例中，所述显示基板包括第一阻挡坝102’和位于第一阻挡坝102’远离显示区AA一侧的第二阻挡坝102’，第一阻挡坝102’在靠近第一非显示区BB1的部分分叉形成两个子阻挡部dam。
在一些实施例中，所述阻挡坝102在非显示区不连续，也即是阻挡坝102在非显示区一些位置设有缺口1023。如图33所示，所述阻挡坝102包括第一阻挡段1021和第二阻挡段1022，第一阻挡段1021和第二阻挡段1022间隔设置，第一阻挡段1021与第二阻挡段1022之间形成缺口1023。所述显示基板还包括位于第一阻挡段1021远离显示区AA一侧的缓冲部1023’，第一阻挡段1021和第二阻挡段1022之间的缺口1023与缓冲部1023’相对。有机材料在经过第一阻挡段1021和第二阻挡段1022之间的缺口1023流出时速度较快，有机材料从缺口1023处流出后绕过缓冲部1023’，从缓冲部1023’两侧流出，缓冲部1023’可减慢有机材料向外溢出的速度。图33仅示意出了阻挡坝102的部分结构，阻挡坝102可在多个地方形成缺口1023，每一缺口1023远离显示区AA的一侧可分别设有缓冲部1023’。
进一步地，如图33所示，缓冲部1023’的两端部向朝向显示区AA的方向弯折，以进一步减慢有机材料向外溢出的速度。缓冲部1023’的长度可大于第一阻挡段1021和第二阻挡段1022之间的缺口1023的尺寸，以更有效地减慢有机材料向外溢出。缓冲部1023’可呈波浪形、直线型、折线形、弧形等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4和图5所示，保护结构1041可以完全包覆第二分部103b；或者，如图8和图9所示， 保护结构1041可以包覆第二分部103b的边缘且暴露出第二分部103b的其余区域。图4、图5、图8和图9中保护结构1041均对第二分部103b的边缘进行了包覆，从而可有效避免第二分部103b发生侧面腐蚀。并且，因相关技术中阳极导电层104为氧化铟锡/银/氧化铟锡(ITO/Ag/ITO)构成的叠层结构，而氧化铟锡的电阻值较大，因此在位于阳极导电层104的保护结构1041对第二分部103b的包覆面积越大，第二分部103b与保护结构1041的整体电阻越大，较大的电阻会造成电源信号在传输过程中的损耗。因此，在保护结构1041仅包覆第二分部103b的边缘且暴露出第二分部103b的其余区域时，可以有效减少保护结构1041的包覆面积，从而利于降低第二分部103b与保护结构1041的整体电阻，保证电源信号的真实性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图9所示，还可以包括位于衬底基板101与阳极导电层104之间的第一源漏金属层(SD1)，电源线103可以包括位于第一源漏金属层(SD1)的第一子电源线1031。通过将第一子电源线1031设置在第一源漏金属层(SD1)，使得在制作第一源漏金属层(SD1)中的相关结构(例如晶体管的源/漏极)的同时，完成第一子电源线1031的制作，从而可以避免单独设置第一子电源线1031的膜层，减少了膜层数量，利于产品的轻薄化设计。可选地，第一源漏金属层(SD1)可以为钛/铝/钛(Ti/Al/Ti)构成的叠层结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图10至图13所示，还可以包括位于第一源漏金属层(SD1)与阳极导电层104之间的第二源漏金属层(SD2)；电源线103还可以包括位于第二源漏金属层(SD2)的第二子电源线1032，第二子电源线1032至少包覆第一子电源线1031的至少部分边缘。电源线103采用第一子电源线1031和第二子电源线1032的双层结构，利于减小电源线103的整体电阻，保证电源信号的真实性。可选地，第二源漏金属层(SD2)可以为钛/铝/钛(Ti/Al/Ti)构成的叠层结构。
进一步的，在一些实施例中，如图34至图47所示，还可以进一步包括位于第二源漏金属层(SD2)与阳极导电层104之间的第三源漏金属层(SD3)； 电源线103还可以包括位于第三源漏金属层(SD3)的第三子电源线1033，第三子电源线1033至少包覆第一子电源线1031的至少部分边缘，例如第三子电源线1033至少包覆第一子电源线1031的边缘。电源线103采用第一子电源线1031和第三子电源线1032的双层结构(如图34至图38所示)，或采用第一子电源线1031，第二子电源线1032和第三子电源线1033的三层结构(如图39至图47所示)利于减小电源线103的整体电阻，保证电源信号的真实性。在一些实施例中，在本公开实施例提供的上述显示基板中，如图10和图11所示，第二子电源线1032可以完全包覆第一子电源线1031；或者，如图12至图15所示，第二子电源线1032可以包覆第一子电源线1031的边缘且暴露出第一子电源线1031的其余区域；这两种包覆方式均可以有效减小电源线103的整体电阻，保证电源信号的真实性。当然，第二子电源线1032也可以仅包覆在第一子电源线1031中第二分部103b的位置，而在第一子电源线1031中第一分部103a的位置断开，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图9所示，在电源线103仅由第一子电源线1031构成时，保护结构1041至少包覆第一子电源线1031中第二分部103b的边缘；例如在图5中，保护结构1041完全包覆第一子电源线1031中第二分部103b的边缘；又如在图9中，保护结构1041包覆第一子电源线1031的边缘且暴露出第一子电源线1031的其余区域。而如图10至图15所示，电源线103由第一子电源线1031和第二子电源线1032组成时，第二子电源线1032至少包覆第一子电源线1031的边缘，此时为了避免阳极所用刻蚀液腐蚀电源线103的侧面，第二子电源线1032的边缘需要得到保护，即保护结构1041需要至少包覆第二子电源线1032的边缘。具体地，在图10和图11中，第二子电源线1032完全包覆第一子电源线1031的边缘；在图12至图13中，第二子电源线1032包覆第一子电源线1031的边缘且暴露出第一子电源线1031的其余区域。相应地，在图10和图12中，保护结构1041完全包覆第一子电源线1031和第二子电源线1032中第二分部103b的边缘；在图11、图14和图15中，保护结构1041包覆第二子电源线 1032中第二分部103b的边缘且暴露出第二子电源线1032中第二分部103b的其余区域，并且在图14和图15中保护结构1041还暴露出第一子电源线1031中第二分部103b的部分非边缘区域；在图13中，保护结构1041完全包覆第二子电源线1032中第二分部103b的边缘且暴露出第一子电源线1031中第二分部103b的部分非边缘区域。在电源线103由第一子电源线1031和第三子电源线1033组成时，可参考电源线103由第一子电源线1031和第二子电源线1032组成时的相关内容，在此不作赘述。在电源线103由第一子电源线1031、第二子电源线1032和第三子电源线1033组成时，如图39至图42所示，保护结构1041可以完全包覆第一子电源线1031、第二子电源线1032和第三子电源线1033；或者，如图43至图47所示，保护结构1041可以完全包覆第三子电源线1033的边缘、以及第二子电源线1032中未被第三子电源线1033遮挡的边缘。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图16至图18所示，保护结构1041还可以至少包覆第一分部103a的至少部分边缘，可选地，保护结构1041至少包覆第一分部103a的边缘，例如，保护结构1041还可以完全包覆第一分部103a的边缘，或者，保护结构1041包覆第一分部103a的边缘并暴露出第一分部103a的其余区域，也就是说，保护结构1041至少在第一分部103a和第二分部103b的边缘处可以连续设置。保护结构1041的这种设置连续方式，一方面利于保护结构1041的制作；另一方面由于第一分部103a与阻挡坝102层叠设置，因此相当于在阻挡坝102与第一分部103a之间增加了保护结构1041，从而使得阻挡坝102所在位置的高度因保护结构1041的存在而增大，由此可以更好地阻挡水氧入侵，有效提高了封装信赖性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图16所示，电源线103可以包括第一电平电源线VDD和第二电平电源线VSS，其中，保护结构1041在第一电平电源线VDD和第二电平电源线VSS之间的间隙处断开设置，以保障第一电平电源信号和第二电平电源信号的独立传输，避免二者相互干扰。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4、图8、图14、图17和图19所示，第一分部103a的边缘和/或第二分部103b的边缘可以包括不规则结构(例如波浪形结构)，以延长水氧入侵路径，提高封装信赖性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图19所示，为了获得较好的包覆效果，保护结构1041的边缘形状可以与第二分部103b的边缘形状大致相同(即可以完全相同，也可以有因制作工艺等造成的误差)。当然，如图4、图8、图14和图17所示，保护结构1041的边缘形状也可以为直线型，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图4、图8、图14和图17所示，非显示区BB可以包括：用于与芯片绑定的第一非显示区BB1，第一非显示区BB1包括在远离显示区AA的方向上依次设置的封装区BB101和水氧隔离区BB102；在第一非显示区BB1内的阻挡坝102位于封装区BB101，第二分部103b位于封装区BB101和水氧隔离区BB102，以更好地防止水氧入侵，有效提高封装信赖性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图4、图8、图14、图17和图20所示，第一非显示区BB1还可以包括扇出区BB103和绑定区BB104，其中，扇出区BB103连接水氧隔离区BB102和绑定区BB104；电源线103还可以包括位于扇出区BB103的第三分部103c，且第三分部103c与第二分部103b一体设置，以通过电源线103延伸至绑定区BB104后与芯片进行绑定，实现芯片为电源线103提供电源信号。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图20和图21所示，还可以包括平坦层105(即上述第二平坦层PLN2)，该平坦层105位于电源线103所在层与阳极导电层104之间，且平坦层105在扇出区BB103整面设置，以通过平坦层105保护第三分部103c，避免阳极所用刻蚀液对第三分部103c造成侧面腐蚀。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图22和图 23所示，保护结构1041还可以至少包覆第三分部103c的边缘，例如保护结构1041完全包覆第三分部103c的边缘，或者，保护结构1041包覆第三分部103c的边缘并暴露出第三分部103c的其余部分，以通过保护结构1041保护第三分部103c，避免阳极所用刻蚀液对第三分部103c造成侧面腐蚀。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图24所示，还可以包括多条触控线106，位于非显示区BB，多条触控线106位于阻挡坝102所在层远离衬底基板101的一侧；至少部分触控线106在衬底基板101上的正投影与电源线103在衬底基板101上的正投影相互交叠。所述保护结构至少部分位于所述相互交叠的区域。
如图25所示，相关技术中的电源线103(SD)存在侧面腐蚀不良，后续沉积缓冲层(Buffer，BFR)时，缓冲层会(BFR)在侧面腐蚀(如图虚线框所示)处会断裂，导致缓冲层上的桥接层(M1)镀膜完成后，桥接层(M1)的触控线106就会与电源线103(SD)之间发生短接(Short)。但本公开中采用保护结构1041至少包覆第二分部103b的边缘，避免了电源线103发生侧面腐蚀，从而有效防止了触控线106与电源线103短接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，至少部分触控线106包括导电绕线部C，以使各条触控线106的电阻大致相同，即各触控线106的电阻差值在可接受的范围(例如±10％)内，导电绕线部C在衬底基板101上的正投影位于阻挡坝102在衬底基板101上的正投影与显示区AA之间。通过将至少部分触控线106进行绕线设置，可以使各条触控线106的电阻大致相同，保证每条触控线106的信号延迟(RC delay)效果基本一致，从而使得与触控线106电连接的触控电极107上加载信号的大小大致相同，由此改善了各触控线106的电阻差别较大对触控的影响，利于提高触控性能。并且，本公开的导电绕线部C设置在阻挡坝102与显示区AA之间的区域，可以将阻挡坝102内侧的空间合理利用起来，从而不需要增大非显示区BB的宽度。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图24和图 26所示，还可以包括相互绝缘的桥接层(M1)和触控层(M2)，桥接层(M1)位于阻挡坝102所在层与触控层(M2)之间；触控线106包括相互电连接的第一子触控线1061和第二子触控线1062，其中，第一子触控线1061位于桥接层(M1)，第二子触控线1062位于触控层(M2)，触控线106的这种双层布线方式，不但可以有效减小触控线106的电阻，而且可以使得在其中一层走线局部断裂后，仍可通过另一层走线保证触控线106的连续性，从而有效解决了单层走线断裂容易导致触控失效的问题。在一些实施例中，可以在非显示区BB每隔预设距离(例如100μm)在桥接层(M1)和触控层(M2)之间的绝缘层中设置一个通孔，使得触控线106的两层布线经由该通孔电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图27至图29所示，还可以包括位于显示区AA的多个触控电极107，触控电极107与触控线106电连接；触控电极107包括相互电连接的第一子触控电极1071和第二子触控电极1072，其中，第一子触控电极1071位于桥接层(M1)，第二子触控电极1072位于触控层(M2)。触控电极107的这种双层设置方式，不但可以有效减小触控电极107的电阻，而且可以使得在其中一层子触控电极107局部断裂后，仍可通过另一层子触控电极保证触控电极107的连续性，从而有效解决了单层结构的触控电极107断裂容易导致触控失效的问题。在一些实施例中，可以在显示区AA每隔预设距离(例如100μm)在桥接层(M1)和触控层(M2)之间的绝缘层中设置一个通孔V，使得第一子触控电极1071和第二子触控电极1072经由该通孔V电连接。另外，由于本公开通过在显示基板中采用触控层(M2)和桥接层(M1)可以实现触控功能，因此无需外挂触控模组(TSP)，从而可以减小显示基板的厚度，进而有利于折叠；同时没有贴合公差，可减小边框宽度。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图28所示，连接第一子触控电极1071和第二子触控电极1072的多个通孔V可以在显示区AA均匀分布，以改善可被看到的通孔V的残影，实现对通孔V的消影效果。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2所示，多个触控电极107可以包括多个沿第一方向Y延伸的第一触控电极107’、以及多个沿第二方向X延伸的第二触控电极107”；多条触控线106包括多条第一触控线106’和多条第二触控线106”；其中，第一触控电极107’与第一触控线106’电连接，第二触控电极107”与第二触控线106”电连接。
可选地，在本公开实施例提供的上述显示基板中，第一触控电极107’可以为触控驱动电极(Tx)，第一触控线106’相应地为触控驱动线；第二触控电极107”可以为触控感应电极(Rx)，第二触控线106”相应地为触控感应线；或者，第一触控电极107’为触控感应电极，第一触控线106’相应地为触控感应线；第二触控电极107”为触控驱动电极，第二触控线106”相应地为触控驱动线。
由图2可见，沿第一方向Y延伸的第一触控电极107’被同层中沿第二方向X延伸第二触控电极107”断开，因此，为了保证第一触控电极107’的连续性，可采用桥接层(M1)的桥接部BD将断开的第二触控电极107”连接起来。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2和图30所示，非显示区BB可以包括相对而置的第一非显示区BB1和第二非显示区BB2，以及相对而置的第三非显示区BB3和第四非显示区BB4，其中，第一非显示区BB1用于与芯片绑定的第一非显示区BB1，第三非显示区BB3、第四非显示区BB4分别连接第一非显示区BB1和第二非显示区BB2；在显示基板的尺寸较大(例如显示基板为笔记本等)时，需要设置较多的触控电极107，相应地需要较多的触控线106，为了保证窄边框效果，如图30所示，可以设置多条第二触控线106”自第三非显示区BB3和第四非显示区BB4折向第一非显示区BB1延伸；部分第一触控线106’依次经第二非显示区BB2和第三非显示区BB3折向第一非显示区BB1延伸，其余第一触控线106’依次经第二非显示区BB2和第四非显示区BB4折向第一非显示区BB1延伸，且在第三非显示区BB3和第四非显示区BB4内，第一触控线106’位于第二触控线106”远离显示区AA的一侧。在显示基板的尺寸较小(例如显示基板为手机等) 时，需要设置较少的触控电极107，相应地需要较少的触控线106，为了保证窄边框效果，如图2所示，多条第二触控线106”可以自第四非显示区BB4折向第一非显示区BB1延伸；部分第一触控线106’可以依次经第二非显示区BB2和第三非显示区BB3折向第一非显示区BB1延伸，其余第一触控线106’可以位于第一非显示区BB1内。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图31所示，还可以包括至少一个触控芯片108，多条触控线106与触控芯片108绑定连接。触控芯片108可以为覆晶薄膜(COF)。
在一些实施例中，如图48所示，驱动电路层位于衬底基板101上，驱动电路层中设置有子像素的像素电路109，像素电路109用于驱动子像素发光。像素电路包括晶体管TFT，还可以包括电容Cst，例如，像素电路109可以是1T像素电路、2T1C像素电路、3T1C像素电路、4T1C像素电路、5T1C像素电路、6T1C像素电路或7T1C像素电路。
在一些实施例中，如图48所示，发光层EL位于驱动电路层109远离衬底基板101的一侧。发光层EL可包括红色子像素R、绿色子像素G与蓝色子像素B，但不限于此。红色子像素R用于发红光，绿色子像素G用于发绿光，蓝色子像素B用于发蓝光。
在一些实施例中，发光层EL为有机发光层。红色子像素R、绿色子像素G与蓝色子像素B均为OLED(有机发光二极管)子像素。
在一些实施例中，如图48所示，封装层110位于发光层EL远离衬底基板101的一侧，用于阻止水氧侵蚀发光层。封装层110包括第一无机封装层1101、有机封装层1102与第二无机封装层1103，第一无机封装层1101位于发光层EL远离衬底基板101的一侧，有机封装层1102位于第一无机封装层1101远离衬底基板101的一侧，第二无机封装层1103位于有机封装层1102远离衬底基板101的一侧。有机封装层1102可采用喷墨打印(IJP)工艺形成。此外显示基板还可以包括阴极CAD、栅绝缘层GI、第一层间介质层ILD1和第二层间介质层ILD2等，对于显示基板的其它必不可少的组成部分均为本领 域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开还提供了一种显示装置，包括本公开实施例提供的上述显示基板，该显示基板可以为OLED、QLED等显示基板。由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，该显示装置的实施可以参见上述显示基板的实施例，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。本公开实施例提供的显示装置还可以包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的组成并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (26)

  1. 一种显示基板，其中，包括：
    衬底基板，包括显示区、以及位于所述显示区周围的非显示区；
    阻挡坝，位于所述非显示区并至少部分围绕所述显示区设置；
    电源线，在所述显示区一侧的所述非显示区内，所述电源线包括一体设置的第一分部和第二分部，所述第一分部在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影大致重合，所述第二分部在所述衬底基板上的正投影与所述阻挡坝在所述衬底基板上的正投影互不交叠；
    阳极导电层，位于所述电源线所在层远离所述衬底基板的一侧，所述阳极导电层包括至少部分位于所述非显示区的保护结构，所述保护结构至少包覆所述第二分部的至少部分边缘。
  2. 如权利要求1所述的显示基板，其中，所述保护结构完全包覆所述第二分部。
  3. 如权利要求1所述的显示基板，其中，所述保护结构包覆所述第二分部的边缘且暴露出所述第二分部的其余区域。
  4. 如权利要求1～3任一项所述的显示基板，其中，还包括位于所述衬底基板与所述阳极导电层之间的第一源漏金属层，所述电源线包括位于所述第一源漏金属层的第一子电源线。
  5. 如权利要求4所述的显示基板，其中，还包括位于所述第一源漏金属层与所述阳极导电层之间的第二源漏金属层；
    所述电源线还包括位于所述第二源漏金属层的第二子电源线，所述第二子电源线至少包覆所述第一子电源线的边缘。
  6. 如权利要求5所述的显示基板，其中，所述第二子电源线完全包覆所述第一子电源线。
  7. 如权利要求5所述的显示基板，其中，所述第二子电源线包覆所述第一子电源线的边缘且暴露出所述第一子电源线的其余区域。
  8. 如权利要求5～7任一项所述的显示基板，其中，所述保护结构至少包覆所述第二子电源线中所述第二分部的至少部分边缘。
  9. 如权利要求1～8任一项所述的显示基板，其中，所述保护结构还至少包覆所述第一分部的至少部分边缘。
  10. 如权利要求1～9任一项所述的显示基板，其中，所述电源线包括第一电平源线和第二电平电源线，其中，所述保护结构在所述第一电平电源线和所述第二电平电源线之间的间隙处断开设置。
  11. 如权利要求1～10任一项所述的显示基板，其中，所述第一分部的边缘和/或所述第二分部的边缘包括不规则结构。
  12. 如权利要求11所述的显示基板，其中，所述保护结构的边缘形状与所述第二分部的边缘形状大致相同。
  13. 如权利要求1～12任一项所述的显示基板，其中，所述非显示区包括：用于与芯片绑定的第一非显示区，所述第一非显示区包括在远离所述显示区的方向上依次设置的封装区和水氧隔离区；
    在所述第一非显示区内的所述阻挡坝位于所述封装区，所述第二分部位于所述封装区和所述水氧隔离区。
  14. 如权利要求12所述的显示基板，其中，所述第一非显示区还包括扇出区和绑定区，其中，所述扇出区连接所述水氧隔离区和所述绑定区；
    所述电源线还包括位于所述扇出区的第三分部，且所述第三分部与所述第二分部一体设置。
  15. 如权利要求14所述的显示基板，其中，还包括平坦层，所述平坦层位于所述电源线所在层与所述阳极导电层之间，且所述平坦层在所述扇出区整面设置。
  16. 如权利要求15所述的显示基板，其中，所述保护结构还至少包覆所述第三分部的至少部分边缘。
  17. 如权利要求1～16任一项所述的显示基板，其中，还包括多条触控线，位于所述非显示区，所述多条触控线位于所述阻挡坝所在层远离所述衬底基 板的一侧；至少部分所述触控线在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影相互交叠，所述保护结构至少部分位于所述相互交叠的区域。
  18. 如权利要求17所述的显示基板，其中，至少部分所述触控线包括导电绕线部，以使各条所述触控线的电阻大致相同，所述导电绕线部在所述衬底基板上的正投影位于所述阻挡坝在所述衬底基板上的正投影与所述显示区之间。
  19. 如权利要求18所述的显示基板，其中，还包括相互绝缘的桥接层和触控层，所述桥接层位于所述阻挡坝所在层与所述触控层之间；
    所述触控线包括相互电连接的第一子触控线和第二子触控线，其中，所述第一子触控线位于所述桥接层，所述第二子触控线位于所述触控层。
  20. 如权利要求19所述的显示基板，其中，还包括位于所述显示区的多个触控电极，所述触控电极与所述触控线电连接；所述触控电极包括相互电连接的第一子触控电极和第二子触控电极，其中，所述第一子触控电极位于所述桥接层，所述第二子触控电极位于所述触控层。
  21. 如权利要求20所述的显示基板，其中，还包括位于所述触控层和桥接层之间的绝缘层，所述绝缘层包括多个通孔，所述通孔连接所述第一子触控电极和所述第二子触控电极，且所述多个通孔在所述显示区均匀分布。
  22. 如权利要求20或21所述的显示基板，其中，所述多个触控电极包括多个沿第一方向延伸的第一触控电极、以及多个沿第二方向延伸的第二触控电极；所述多条触控线包括多条第一触控线和多条第二触控线；其中，所述第一触控电极与所述第一触控线电连接，所述第二触控电极与所述第二触控线电连接。
  23. 如权利要求22所述的显示基板，其中，所述非显示区包括相对而置的第一非显示区和第二非显示区，以及相对而置的第三非显示区和第四非显示区，其中，所述第一非显示区用于与芯片绑定的第一非显示区，所述第三非显示区、所述第四非显示区分别连接第一非显示区和第二非显示区；
    所述多条第二触控线自所述第三非显示区和所述第四非显示区折向所述第一非显示区延伸；
    部分所述第一触控线依次经所述第二非显示区和所述第三非显示区折向所述第一非显示区延伸，其余所述第一触控线依次经所述第二非显示区和所述第四非显示区折向所述第一非显示区延伸，且在所述第三非显示区和所述第四非显示区内，所述第一触控线位于所述第二触控线远离所述显示区的一侧。
  24. 如权利要求22所述的显示基板，其中，所述非显示区包括相对而置的第一非显示区和第二非显示区，以及相对而置的第三非显示区和第四非显示区，其中，所述第一非显示区用于与芯片绑定的第一非显示区，所述第三非显示区、所述第四非显示区分别连接第一非显示区和第二非显示区；
    所述多条第二触控线自所述第四非显示区折向所述第一非显示区延伸；
    部分所述第一触控线依次经所述第二非显示区和所述第三非显示区折向所述第一非显示区延伸，其余所述第一触控线位于所述第一非显示区内。
  25. 如权利要求17～24任一项所述的显示基板，其中，还包括至少一个触控芯片，所述多条触控线与所述触控芯片绑定连接。
  26. 一种显示装置，其中，包括如权利要求1～25任一项所述的显示基板。
PCT/CN2023/070188 2022-01-26 2023-01-03 显示基板及显示装置 WO2023142908A1 (zh)

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