WO2023142154A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2023142154A1
WO2023142154A1 PCT/CN2022/075329 CN2022075329W WO2023142154A1 WO 2023142154 A1 WO2023142154 A1 WO 2023142154A1 CN 2022075329 W CN2022075329 W CN 2022075329W WO 2023142154 A1 WO2023142154 A1 WO 2023142154A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
numbered
gate
electrically connected
odd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/075329
Other languages
English (en)
French (fr)
Inventor
王选芸
戴超
秦芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/638,112 priority Critical patent/US11749157B2/en
Publication of WO2023142154A1 publication Critical patent/WO2023142154A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the present application provides a display panel and a display device to achieve the technical problem of ultra-low frequency display.
  • the present application provides a display panel, which includes a gate drive circuit and a plurality of rows of pixel circuits, and the gate drive circuit includes odd-numbered gate drive units sequentially cascaded and even-numbered gates sequentially cascaded.
  • Drive unit each row of pixel circuits includes a plurality of pixel circuits, wherein the pixel circuits of odd rows are electrically connected to corresponding odd-numbered gate drive units, and the even-numbered row pixel circuits are electrically connected to corresponding even-numbered gate drive units;
  • the pixel circuit includes a driving transistor and at least one oxide thin film transistor, the gate of the driving transistor is electrically connected to one of the source/drain of the at least one oxide thin film transistor.
  • At least one oxide thin film transistor includes a first transistor, and one of the source/drain of the first transistor is electrically connected to the gate of the driving transistor; the pixel circuit further includes a second transistor and a third transistor.
  • a transistor, one of the source/drain of the second transistor is electrically connected to one of the source/drain of the driving transistor, and the other of the source/drain of the second transistor is connected to the source of the first transistor
  • the other of the /drain is electrically connected, the gate of the second transistor is electrically connected to the output terminal of the Nth-level gate drive unit, and the second transistor is a polysilicon thin film transistor;
  • the source/drain of the third transistor One of them is electrically connected to the other of the source/drain of the first transistor, the gate of the third transistor is electrically connected to the output terminal of the N-2th level gate drive unit, and the third transistor is polysilicon thin film transistor.
  • the pixel circuit further includes a fourth transistor, one of the source/drain of the fourth transistor is electrically connected to the other of the source/drain of the third transistor and connected to the initial signal, and the first The gates of the four transistors are electrically connected to the output end of the Nth-level gate driving unit or the output end of the N-2th level gate driving unit, and the fourth transistor is a polysilicon thin film transistor.
  • At least one oxide thin film transistor includes a first transistor and a second transistor, one of the source/drain of the first transistor is electrically connected to the gate of the driving transistor, and the gate of the first transistor It is electrically connected with the N-2th level gate drive unit, one of the source/drain of the first transistor is connected to the initial signal; one of the source/drain of the second transistor is electrically connected to the gate of the driving transistor The other of the source/drain of the second transistor is electrically connected to one of the source/drain of the driving transistor, and the gate of the second transistor is electrically connected to the Nth-level gate driving unit.
  • one of the odd-numbered row pixel circuits or the even-numbered row pixel circuits sequentially starts to display row by row in the first time period of a frame, and the other one of the odd-numbered row pixel circuits or the even-numbered pixel circuits
  • the progressive display starts sequentially in the second time period of a frame; wherein, the start time of the first time period is earlier than the start time of the second time period.
  • the odd-numbered gate drive units output corresponding odd-numbered row scan signals
  • the even-numbered gate drive units output corresponding even-numbered row scan signals
  • the odd-numbered gate drive units are electrically connected to the odd-numbered row pixel circuits to Provide odd-numbered row scanning signals to corresponding odd-numbered row pixel circuits
  • even-numbered gate drive units are electrically connected to even-numbered row pixel circuits to provide even-numbered row scanning signals to corresponding even-numbered row pixel circuits
  • odd-numbered row scanning signals or even-numbered row scanning signals One of them has a start edge of a pulse sequentially in the third time period of a frame, and the other of the odd line scanning signal or the even line scanning signal has a start of a pulse sequentially in the fourth time period of a frame edge; wherein, the start edge is one of rising edge or falling edge; the start time of the third time period is earlier than or equal to the start time of the fourth time period; and the end time of the fourth time period is earlier than or equal to the first time
  • the start time is one
  • the odd-numbered gate driving unit is used to output corresponding odd-numbered line scanning signals according to the first start signal
  • the even-numbered level gate driving unit is used to output corresponding even-numbered line scanning signals according to the second start signal; Wherein, the phases of the first start signal and the second start signal are different.
  • the display panel is provided with a first frame area, a display area and a second frame area, and the display area is located between the first frame area and the second frame area; the odd-numbered gate units and the even-numbered gate units Both are located in the first frame area or the second frame area.
  • the display panel is provided with a first frame area, a display area and a second frame area, and the display area is located between the first frame area and the second frame area; odd-level gate units are located in the first frame area or In one of the second frame regions, the even-numbered gate units are located in the other of the first frame region or the second frame region.
  • the present application provides a display device, which includes the display panel in at least one embodiment above.
  • At least one oxide thin film transistor is electrically connected to the gate of the driving transistor in the pixel circuit, so that the pixel circuit has low leakage characteristics, and can maintain the driving transistor in the pixel circuit for a long time.
  • the gate potential can realize the low-frequency drive display of the pixel circuit; on this basis, configure one of the odd-numbered row pixel circuits or the even-numbered row pixel circuits, and the other of the odd-numbered row pixel circuits or the even-numbered row pixel circuits in one frame
  • the row-by-row display is started sequentially, so as to lengthen the display time interval between two adjacent rows of pixel circuits to about half a frame time, which can effectively reduce the visual impact on the adjacent two rows of pixel circuits.
  • the brightness difference perception reduces or eliminates the flicker phenomenon of the display, thereby realizing the ultra-low frequency drive display of the display panel or the display device.
  • FIG. 1 is a schematic diagram of a first structure of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of display timing before improvement.
  • FIG. 4 is a schematic diagram of display timing of the display panel shown in FIG. 1 or FIG. 2 .
  • FIG. 5 is a schematic diagram of brightness comparison before and after improvement provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a comparison of brightness change ranges before and after improvement provided by the embodiment of the present application.
  • FIG. 7 is a first circuit schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a second circuit schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 9 is a third circuit schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 10 is a fourth circuit schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • this embodiment provides a display panel, please refer to Figure 1 to Figure 10, as shown in Figure 1, Figure 2 and Figure 7 to Figure 10, the display panel Including a gate drive circuit 20 and multiple rows of pixel circuits, for example, a first row of pixel circuits 11, a second row of pixel circuits 12, a third row of pixel circuits 13, and a fourth row of pixel circuits 14, etc.
  • each row of pixel circuits includes multiple pixel circuits 10
  • multi-row pixel circuits include odd row pixel circuits and even row pixel circuits, wherein the odd row pixel circuits can be, for example, the first row pixel circuits 11, the third row pixel circuits 13, etc., and the even row pixel circuits are, for example It may be the second row of pixel circuits 12, the fourth row of pixel circuits 14, and so on.
  • the gate driving circuit 20 includes odd-numbered gate driving units cascaded in sequence and even-numbered gate driving units cascaded in sequence.
  • the odd-numbered gate driving unit may be the first gate driving unit 21 or the third gate driving unit.
  • the gate drive unit 23, the even-numbered gate drive unit can be the second gate drive unit 22 or the fourth gate drive unit 24;
  • the odd-numbered row pixel circuit is electrically connected to the corresponding odd-numbered gate drive unit, and the even-numbered row pixel circuit
  • the circuit is electrically connected to the corresponding even-numbered gate drive unit; wherein, the pixel circuit 10 includes a drive transistor T1 and at least one oxide thin film transistor, and the gate of the drive transistor is connected to the source/drain of at least one oxide thin film transistor. an electrical connection.
  • the gate of the driving transistor T1 in the pixel circuit 10 is electrically connected to at least one oxide thin film transistor, so that the pixel circuit has low leakage characteristics, and the pixel circuit can be maintained for a long time.
  • the gate potential of the drive transistor in 10 can realize the low-frequency drive display of the pixel circuit 10;
  • the other starts to display line by line in the first time period and the second time period of a frame, so as to lengthen the display time interval between two adjacent rows of pixel circuits to about half a frame time, which can effectively reduce the visual impact.
  • Sensing the brightness difference between two adjacent rows of pixel circuits reduces or eliminates the display flicker phenomenon, thereby realizing the ultra-low frequency drive display of the display panel or display device.
  • At least one oxide thin film transistor may be the transistor T8 shown in FIG. 7 or FIG. 8, or may also be the transistor T3 and the transistor T4 shown in FIG. , transistor T41, transistor T32, transistor T42.
  • one of the odd-numbered row pixel circuits or the even-numbered row pixel circuits sequentially starts displaying row by row in the first time period of a frame, and the other one of the odd-numbered row pixel circuits or the even-numbered pixel circuits
  • the row-by-row display starts sequentially in the second time period of a frame, and each pixel circuit 10 has a low leakage characteristic in a frame; wherein, the start time of the first time period is earlier than the start time of the second time period.
  • the light-emitting time or display time in one frame may include a first time period and a second time period, and in the first time period, the first row of pixel circuits 11, the third row of pixel circuits 13, etc.
  • the row pixel circuits can start displaying or emitting light row by row sequentially; in the second time period, the second row pixel circuit 12 , the fourth row pixel circuit 14 , etc. even-numbered row pixel circuits can start displaying or emitting row row by row sequentially.
  • the second row of pixel circuits 12, the fourth row of pixel circuits 14, and other even-numbered row pixel circuits can start displaying or emitting light row by row; in the second time period, the first row of pixel circuits 11.
  • Pixel circuits in the third row 13 and other odd-numbered row pixel circuits can sequentially start displaying or emitting light row by row. It can be understood that, in this way, the time interval between two adjacent rows of pixel circuits to start displaying or emitting light can be lengthened, which can effectively reduce the visual perception of brightness difference between two adjacent rows of pixel circuits.
  • the odd-numbered gate drive units output corresponding odd-numbered row scan signals
  • the even-numbered gate drive units output corresponding even-numbered row scan signals
  • the odd-numbered gate drive units Electrically connected to odd-numbered row pixel circuits to provide odd-numbered row scanning signals to corresponding odd-numbered pixel circuits
  • even-numbered gate drive units are electrically connected to even-numbered row pixel circuits to provide even-numbered row scanning signals to corresponding even-numbered pixel circuits
  • One of the odd line scanning signal or the even line scanning signal has a pulse start edge in the third time period of a frame, and the other of the odd line scanning signal or the even line scanning signal has a pulse start edge in the fourth period of a frame.
  • start edge of a pulse in the time period in sequence wherein, the start edge is one of rising edge or falling edge; the start time of the third time period is earlier than or equal to the start time of the fourth time period; and the start time of the fourth time period The end time is earlier than or equal to the start time of the first time period.
  • the data writing time in one frame may include a third time period and a fourth time period, and in one frame, the data writing time is before the display time or the light emitting time.
  • Each pulse in each scan signal corresponds to one writing of the data signal, and the start edge of each pulse corresponds to the start writing time of the data signal.
  • the scan signals of odd rows have a start edge of a pulse in sequence, and data signals can be sequentially written into the corresponding pixel circuits of odd rows;
  • the scan signals of even rows have a start edge of a pulse in turn, and data signals can be written into Corresponding even row pixel circuit.
  • the odd-numbered gate driving units may be, for example, the first gate driving unit 21, the third gate driving unit 23, etc.
  • the even-numbered gate driving units may be, for example, It can be the second gate driving unit 22, the fourth gate driving unit 24, etc.
  • the odd-numbered gate driving unit is used to output the corresponding odd-numbered row scanning signal according to the first start signal
  • the even-numbered gate driving unit is used to output the corresponding odd-numbered line scanning signal according to the
  • the second start signal outputs the corresponding even line scan signal; wherein, the first start signal and the second start signal have different phases.
  • the first gate drive unit 21, the third gate drive unit 23 and other odd-numbered gate drive units are sequentially cascaded, and under the control of the first start signal, the The odd-numbered gate drive units control the scanning timing of the output odd-numbered row scan signals; the second gate drive unit 22, the fourth gate drive unit 24, and other even-numbered gate drive units are cascaded in sequence, and at the second start Under the control of the signal, the scanning timing of the even-numbered row scanning signal output can be controlled by the even-numbered gate driving unit. In this way, the scanning timing of the odd-numbered row scanning signals and the scanning timing of the even-numbered row scanning signals can be separately controlled, thereby better realizing the display time interval between two adjacent rows of pixel circuits.
  • the display panel is provided with a first frame area NA1, a display area AA and a second frame area NA2, and the display area AA is located between the first frame area NA1 and the second frame area NA2. ; Both the odd-level gate units and the even-level gate units are located in the first frame area NA1 or the second frame area NA2 .
  • the display panel is provided with a first frame area NA1, a display area AA, and a second frame area NA2, and the display area AA is located between the first frame area NA1 and the second frame area NA2.
  • the odd-level gate units are located in one of the first frame area NA1 or the second frame area NA2, and the even-level gate units are located in the other of the first frame area NA1 or the second frame area NA2.
  • the display panel further includes a plurality of scan lines such as scan line SL1, scan line SL2, scan line SL3, and scan line SL4, etc.
  • the plurality of scan lines include at least one Odd-numbered scanning lines and at least one even-numbered scanning lines
  • the odd-numbered scanning lines can be, for example, scanning lines SL1, scanning lines SL3, etc.
  • the even-numbered scanning lines can be scanning lines SL2, scanning lines SL4, etc., an odd-numbered scanning lines
  • the scanning line is electrically connected to a corresponding odd-numbered gate driving unit
  • an odd-numbered row of pixel circuits is electrically connected to two odd-numbered scanning lines
  • an even-numbered scanning line is electrically connected to a corresponding even-numbered gate driving unit 1.
  • An even-numbered pixel circuit is electrically connected to two even-numbered scanning lines.
  • the display panel further includes a plurality of data lines DL for transmitting data signals, and one data line DL is electrically connected to the pixel circuits 10 in two different columns. and write data signals to the two pixel circuits 10 in the same row in a time-division manner.
  • one data line DL is electrically connected to the pixel circuits 10 in two different columns, which can save the routing number of the data line DL in the display area AA and increase the aperture ratio of the display panel.
  • FIG. 3 it is a schematic diagram of the display timing before improvement.
  • the pixel circuit of row N-2, the pixel circuit of row N-1, the pixel circuit of row N, the pixel circuit of row N+1, The pixel circuits in row N+2 start to display row by row.
  • the display time interval between two adjacent rows of pixel circuits is short, and the brightness difference is relatively large. It is easy to perceive flicker visually, which seriously affects the super Picture quality with low frequency drive display.
  • the display timing of the display panel provided by the above-mentioned embodiments is shown in FIG. 4 .
  • the pixel circuits in the N-1 row, the N+1 row pixel circuits, etc. start to display row by row, and then, the Nth row -2 rows of pixel circuits, Nth row of pixel circuits, N+2th row of pixel circuits, etc. start to display row by row, so that the display time interval between two adjacent rows of pixel circuits can be lengthened, and the visual effect can be weakened
  • the perceived perception reduces or eliminates the perceivable flickering, and then can realize ultra-low frequency drive display, and even support ultra-low frequency drive display under 1Hz.
  • FIG. 6 it is a schematic diagram of the brightness change before and after the improvement provided by the embodiment of the present application.
  • the abscissa in each small picture is used to represent time, and its unit is second; the ordinate is used to represent brightness, and its unit is cd /m2 or nit.
  • the upper left small picture, the upper right small picture and the lower left small picture in Figure 6 are the change of brightness with time before improvement, and the lower right small picture in Figure 6 is the change of brightness with time after improvement. It can be seen from the comparison that the magnitude of the luminance change of the lower right small image is obviously smaller than that of any one of the upper left small image, the upper right small image and the lower left small image.
  • At least one oxide thin film transistor includes a first transistor, and one of the source/drain of the first transistor is electrically connected to the gate of the driving transistor T1;
  • the pixel circuit further includes a second transistor and a third transistor, one of the source/drain of the second transistor is electrically connected to one of the source/drain of the driving transistor T1, and the source/drain of the second transistor The other one is electrically connected to the other of the source/drain of the first transistor, the gate of the second transistor is electrically connected to the output terminal of the Nth-level gate drive unit, and the second transistor is a polysilicon thin film Transistor; one of the source/drain of the third transistor is electrically connected to the other of the source/drain of the first transistor, and the gate of the third transistor is connected to the output of the N-2th stage gate drive unit The terminals are electrically connected, and the third transistor is a polysilicon thin film transistor.
  • the first transistor can be the transistor T8 shown in FIG. 7 or FIG. 8
  • the second transistor can be the transistor T3 shown in FIG. 7 or FIG. 8
  • the third transistor can be the transistor T8 shown in FIG. 7 or FIG. Transistor T4.
  • the output terminal of the gate driving unit of the Nth stage outputs the scan signal Scan(n), and the output terminal of the gate driving unit of the N-2th stage outputs the scanning signal Scan(n ⁇ 2).
  • the pixel circuit further includes a writing transistor T2, one of the source/drain of the writing transistor T2 is electrically connected to the other of the source/drain of the driving transistor T1, and the writing transistor T2 The other of the source/drain of T2 is connected to the data signal Data, and the gate of the writing transistor T2 is electrically connected to the output terminal of the Nth-level gate driving unit.
  • the gate of the driving transistor T1 is only connected to one of the source/drain of the first transistor, which can effectively reduce the gate leakage current of the driving transistor T1; and configure the first transistor as The oxide thin film transistor can further reduce the gate leakage current of the driving transistor T1, and it is easier to maintain the data signal Data after it is written into the gate of the driving transistor T1, so as to ensure that the written data signal Data is more used for driving Transistor T1 is turned on.
  • the pixel circuit may further include a third transistor T4 and a fourth transistor T7, and one of the source/drain of the third transistor T4 is connected to the source/drain of the first transistor.
  • the other of the drains is electrically connected
  • the other of the source/drain of the third transistor T4 is electrically connected to one of the source/drain of the fourth transistor T7 and connected to the initial signal Vint
  • the third The gate of the transistor T4 is connected to the scan signal Scan(n-2)
  • the gate of the fourth transistor T7 is electrically connected to the gate of the writing transistor T2
  • the gate of the second transistor is connected to the scan signal Scan(n) .
  • the pixel circuit may further include a third transistor T4 and a fourth transistor T7, one of the source/drain of the third transistor T4 is connected to the source/drain of the first transistor.
  • the other of the drains is electrically connected to one of the source/drain of the fourth transistor T7, the other of the source/drain of the third transistor T4 is connected to the initial signal Vint, and the gate of the third transistor T4
  • the pole is electrically connected to the gate of the fourth transistor T7 and connected to the scan signal Scan(n ⁇ 2).
  • the pixel circuit may further include a transistor T5, a transistor T6, a light emitting device D1, and a storage capacitor Cst, one of the source/drain of the transistor T5 and the storage capacitor One end of Cst is electrically connected to the positive power supply signal ELVDD, the other end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other of the source/drain of the transistor T5 is connected to the source of the driving transistor T1
  • the other of the drain/drain is electrically connected, one of the source/drain of the transistor T6 is electrically connected to one of the source/drain of the driving transistor T1, and the other of the source/drain of the transistor T6
  • One is electrically connected to the other of the source/drain of the fourth transistor T7 and the anode of the light emitting device D1, the cathode of the light emitting device D1 is connected to the negative power supply signal ELVSS or the zero potential signal,
  • the second transistor, the third transistor T4 , the fourth transistor T7 , the writing transistor T2 , the driving transistor T1 , the transistor T5 and the transistor T6 can all be P-channel thin film transistors, specifically low temperature polysilicon thin film transistors.
  • the first transistor may be an N-channel thin film transistor, specifically a metal oxide thin film transistor, for example, an indium gallium zinc oxide thin film transistor.
  • At least one oxide thin film transistor may include a first transistor and a second transistor, one of the source/drain of the first transistor and the gate of the driving transistor T1
  • the poles are electrically connected, the gate of the first transistor is electrically connected to the N-2th level gate drive unit, and one of the source/drain of the first transistor is connected to the initial signal Vint; the source/drain of the second transistor is connected to the initial signal Vint;
  • One of the drains is electrically connected to the gate of the driving transistor T1, the other of the source/drain of the second transistor is electrically connected to one of the source/drain of the driving transistor T1, and the second transistor
  • the gate is electrically connected with the Nth level gate driving unit.
  • the first transistor may be the transistor T4 shown in FIG. 9
  • the second transistor may be the transistor T3 shown in FIG. 9
  • the first transistor may also be the transistor T41 shown in FIG. 10
  • the second transistor may be the transistor T31 shown in FIG. 10
  • the first transistor may also be the transistor T42 shown in FIG. 10
  • the second transistor may be the transistor T32 shown in FIG. 10 .
  • the gate of the driving transistor T1 is connected to one of the source/drain of the first transistor and one of the source/drain of the second transistor, due to the Both the second transistor and the first transistor use oxide thin film transistors, which can also effectively reduce the gate leakage current of the driving transistor T1, and can also be maintained after the data signal Data is written into the gate of the driving transistor T1, ensuring that the write The input data signal Data is more used to drive the transistor T1 to turn on.
  • the pixel circuit further includes a writing transistor T2, one of the source/drain of the writing transistor T2 is electrically connected to the other of the source/drain of the driving transistor T1, and the source/drain of the writing transistor T2 The other one is connected to the data signal Data, and the second transistor is turned on or off synchronously with the writing transistor T2.
  • the gate of the writing transistor T2 is connected to the scan signal PScan(n), the gate of the second transistor is connected to the scan signal NScan(n), and the gate of the first transistor is connected to the scan signal NScan(n). -2).
  • the pixel circuit may further include a transistor T7, one of the source/drain of the transistor T7 is electrically connected to the other of the source/drain of the first transistor and connected to the initial signal Vint, The gate of the transistor T7 is electrically connected to the gate of the writing transistor T2.
  • the pixel circuit may further include a transistor T5, a transistor T6, a light emitting device D1, and a storage capacitor Cst, one of the source/drain of the transistor T5 and one end of the storage capacitor Cst Electrically connected and connected to the positive power signal ELVDD, the other end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other of the source/drain of the transistor T5 is connected to the source/drain of the driving transistor T1
  • One of the source/drain of the transistor T6 is electrically connected to one of the source/drain of the driving transistor T1, and the other of the source/drain of the transistor T6 is connected to the transistor
  • the other of the source/drain of T7 is electrically connected to the anode of the light emitting device D1, the cathode of the light emitting device D1 is connected to the power negative signal ELVSS or the zero potential signal, and the gate of the transistor T5 is electrically connected to the gate
  • the transistor T4 , the transistor T7 , the writing transistor T2 , the driving transistor T1 , the transistor T5 and the transistor T6 may all be P-channel thin film transistors, specifically low temperature polysilicon thin film transistors.
  • the second transistor and the first transistor may be N-channel thin film transistors, specifically metal oxide thin film transistors, for example, InGaZnO thin film transistors.
  • the pixel circuit shown in FIG. 10 includes two pixel circuits as shown in FIG. 9. The difference from that shown in FIG. 9 is that in FIG. Time-division multiplexing of one data signal Data can reduce the number of data lines and increase the aperture ratio of the display panel.
  • the transistor Tmux1 and the transistor Tmux2 are time-divisionally turned on under the control of the signal Demux1 and the signal Demux2 respectively, and a pulse of the data signal Data can be time-divisionally written into the left and right pixel circuits, thereby reducing the number of data lines. quantity.
  • this embodiment provides a display device, which includes the display panel in at least one embodiment above.
  • At least one oxide thin film transistor is electrically connected to the gate of the driving transistor in the pixel circuit, so that the pixel circuit has low leakage characteristics, and can maintain the drive in the pixel circuit for a long time.
  • the gate potential of the transistor can realize the low-frequency driving display of the pixel circuit;
  • the first time period and the second time period of a frame start to display line by line in order to lengthen the display time interval between two adjacent lines of pixel circuits to about half a frame time, which can effectively reduce the visual impact on two adjacent lines.
  • the brightness difference perception of the pixel circuit reduces or eliminates the flicker phenomenon of the display, thereby realizing the ultra-low frequency driving display of the display panel or the display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示面板及显示装置，该显示面板包括栅极驱动电路(20)和多行像素电路(10)，通过在像素电路(10)中驱动晶体管(T1)的栅极电性连接至少一个氧化物薄膜晶体管，使得像素电路(10)具有低漏电特性的，能够实现像素电路(10)的低频驱动显示；在此基础上，拉长相邻两行像素电路(10)之间的显示时间间隔至半帧时间左右，进而实现了超低频驱动显示。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求越来越高，尤其是智能手机领域，超高频驱动显示、低功耗驱动显示、低频驱动显示以及超低频（10Hz以下）驱动显示都是现阶段和未来的发展需求方向。
但是，现有技术难以实现超低频驱动显示，因此，有必要提出一种可以实现超低频驱动显示的显示面板。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种显示面板及显示装置，以实现超低频显示的技术问题。
 技术解决方案
第一方面，本申请提供一种显示面板，其包括栅极驱动电路和多行像素电路，栅极驱动电路包括依次级联设置的奇数级栅极驱动单元和依次级联设置的偶数级栅极驱动单元；每行像素电路包括多个像素电路，其中，奇数行像素电路与对应的奇数级栅极驱动单元电性连接，偶数行像素电路与对应的偶数级栅极驱动单元电性连接；其中，像素电路包括驱动晶体管和至少一个氧化物薄膜晶体管，驱动晶体管的栅极与至少一个氧化物薄膜晶体管的源极/漏极中的一个电性连接。
在其中一些实施方式中，至少一个氧化物薄膜晶体管包括第一晶体管，第一晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接；像素电路还包括第二晶体管和第三晶体管，第二晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的一个电性连接，第二晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个电性连接，第二晶体管的栅极与第N级栅极驱动单元的输出端电性连接，且第二晶体管为多晶硅薄膜晶体管；第三晶体管的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个电性连接，第三晶体管的栅极与第N-2级栅极驱动单元的输出端电性连接，且第三晶体管为多晶硅薄膜晶体管。
在其中一些实施方式中，像素电路还包括第四晶体管，第四晶体管的源极/漏极的一个与第三晶体管的源极/漏极中的另一个电性连接并接入初始信号，第四晶体管的栅极与第N级栅极驱动单元的输出端或者第N-2级栅极驱动单元的输出端电性连接，且第四晶体管为多晶硅薄膜晶体管。
在其中一些实施方式中，至少一个氧化物薄膜晶体管包括第一晶体管和第二晶体管，第一晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接，第一晶体管的栅极与第N-2级栅极驱动单元电性连接，第一晶体管的源极/漏极中的一个接入初始信号；第二晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接，第二晶体管的源极/漏极中的另一个与驱动晶体管的源极/漏极中的一个电性连接，第二晶体管的栅极与第N级栅极驱动单元电性连接。
在其中一些实施方式中，奇数行像素电路或者偶数行像素电路中的一种在一帧的第一时间段中依次开始逐行显示，奇数行像素电路或者偶数行像素电路中的另一种在一帧的第二时间段中依次开始逐行显示；其中，第一时间段的开始时间早于第二时间段的开始时间。
在其中一些实施方式中，奇数级栅极驱动单元输出对应的奇数行扫描信号，偶数级栅极驱动单元输出对应的偶数行扫描信号；奇数级栅极驱动单元与奇数行像素电路电性连接以提供奇数行扫描信号至对应的奇数行像素电路，偶数级栅极驱动单元与偶数行像素电路电性连接以提供偶数行扫描信号至对应的偶数行像素电路；奇数行扫描信号或者偶数行扫描信号中的一种在一帧的第三时间段中依次具有一个脉冲的开始沿，奇数行扫描信号或者偶数行扫描信号中的另一种在一帧的第四时间段中依次具有一个脉冲的开始沿；其中，开始沿为上升沿或者下降沿中的一个；第三时间段的开始时间早于或者等于第四时间段的开始时间；且第四时间段的结束时间早于或者等于第一时间段的开始时间。
在其中一些实施方式中，奇数级栅极驱动单元用于根据第一起始信号输出对应的奇数行扫描信号，偶数级栅极驱动单元用于根据第二起始信号输出对应的偶数行扫描信号；其中，第一起始信号与第二起始信号的相位不同。
在其中一些实施方式中，显示面板设置有第一边框区、显示区以及第二边框区，显示区位于第一边框区与第二边框区之间；奇数级栅极单元、偶数级栅极单元均位于第一边框区或者第二边框区。
在其中一些实施方式中，显示面板设置有第一边框区、显示区以及第二边框区，显示区位于第一边框区与第二边框区之间；奇数级栅极单元位于第一边框区或者第二边框区中的一个，偶数级栅极单元位于第一边框区或者第二边框区中的另一个。
第二方面，本申请提供一种显示装置，其包括上述至少一实施方式中的显示面板。
 有益效果
本申请提供的显示面板及显示装置，通过在像素电路中驱动晶体管的栅极电性连接至少一个氧化物薄膜晶体管，使得像素电路具有低漏电特性的，可以较长时间保持像素电路中驱动晶体管的栅极电位，能够实现像素电路的低频驱动显示；在此基础上，配置奇数行像素电路或者偶数行像素电路中的一种、奇数行像素电路或者偶数行像素电路中的另一种在一帧的第一时间段、第二时间段中依次开始逐行显示，以拉长相邻两行像素电路之间的显示时间间隔至半帧时间左右，可以有效降低视觉上对相邻两行像素电路的亮度差异感知，减少或者消除了显示的闪烁现象，进而实现了显示面板或者显示装置的超低频驱动显示。
 附图说明
图1为本申请实施例提供的显示面板的第一种结构示意图。
图2为本申请实施例提供的显示面板的第二种结构示意图。
图3为改善前的显示时序示意图。
图4为图1或者图2所示显示面板的显示时序示意图。
图5为本申请实施例提供的改善前后的亮度对比示意图。
图6为本申请实施例提供的改善前后的亮度变化幅度对比示意图。
图7为本申请实施例提供的像素电路的第一种电路原理图。
图8为本申请实施例提供的像素电路的第二种电路原理图。
图9为本申请实施例提供的像素电路的第三种电路原理图。
图10为本申请实施例提供的像素电路的第四种电路原理图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
有鉴于现有技术难以实现超低频显示的技术问题，本实施例提供了一种显示面板，请参阅图1至图10，如图1、图2以及图7至图10所示，该显示面板包括栅极驱动电路20和多行像素电路，例如，第一行像素电路11、第二行像素电路12、第三行像素电路13以及第四行像素电路14等等，每行像素电路包括多个像素电路10，多行像素电路包括奇数行像素电路和偶数行像素电路，其中，奇数行像素电路例如可以为第一行像素电路11、第三行像素电路13等等，偶数行像素电路例如可以为第二行像素电路12、第四行像素电路14等等。栅极驱动电路20包括依次级联设置的奇数级栅极驱动单元和依次级联设置的偶数级栅极驱动单元，例如，奇数级栅极驱动单元可以为第一栅极驱动单元21或者第三栅极驱动单元23，偶数级栅极驱动单元可以为第二栅极驱动单元22或者第四栅极驱动单元24；奇数行像素电路与对应的奇数级栅极驱动单元电性连接，偶数行像素电路与对应的偶数级栅极驱动单元电性连接；其中，像素电路10包括驱动晶体管T1和至少一个氧化物薄膜晶体管，驱动晶体管的栅极与至少一个氧化物薄膜晶体管的源极/漏极中的一个电性连接。
可以理解的是，本实施例提供的显示面板，通过在像素电路10中驱动晶体管T1的栅极电性连接至少一个氧化物薄膜晶体管，使得像素电路具有低漏电特性，可以较长时间保持像素电路10中驱动晶体管的栅极电位，能够实现像素电路10的低频驱动显示；在此基础上，配置奇数行像素电路或者偶数行像素电路中的一种、奇数行像素电路或者偶数行像素电路中的另一种在一帧的第一时间段、第二时间段中依次开始逐行显示，以拉长相邻两行像素电路之间的显示时间间隔至半帧时间左右，可以有效降低视觉上对相邻两行像素电路的亮度差异感知，减少或者消除了显示的闪烁现象，进而实现了显示面板或者显示装置的超低频驱动显示。
其中，至少一个氧化物薄膜晶体管可以为图7或者图8中所示的晶体管T8，或者也可以为图9中所示的晶体管T3、晶体管T4，或者还可以为图10中所示的晶体管T31、晶体管T41、晶体管T32、晶体管T42。
在其中一个实施例中，奇数行像素电路或者偶数行像素电路中的一种在一帧的第一时间段中依次开始逐行显示，奇数行像素电路或者偶数行像素电路中的另一种在一帧的第二时间段中依次开始逐行显示，且每个像素电路10在一帧中具有低漏电特性；其中，第一时间段的开始时间早于第二时间段的开始时间。
需要进行说明的是，一帧中的发光时间或者显示时间可以包括第一时间段和第二时间段，在第一时间段中，第一行像素电路11、第三行像素电路13等等奇数行像素电路可以依次逐行开始显示或者发光；在第二时间段中，第二行像素电路12、第四行像素电路14等等偶数行像素电路可以依次逐行开始显示或者发光。同理，在第一时间段中，第二行像素电路12、第四行像素电路14等等偶数行像素电路可以依次逐行开始显示或者发光；在第二时间段中，第一行像素电路11、第三行像素电路13等等奇数行像素电路可以依次逐行开始显示或者发光。可以理解的是，如此可以拉长相邻两行像素电路之间的开始显示或者发光的时间间隔，能够有效降低视觉上对相邻两行像素电路的亮度差异感知。
在其中一个实施例中，如图1或者图2所示，奇数级栅极驱动单元输出对应的奇数行扫描信号，偶数级栅极驱动单元输出对应的偶数行扫描信号；奇数级栅极驱动单元与奇数行像素电路电性连接以提供奇数行扫描信号至对应的奇数行像素电路，偶数级栅极驱动单元与偶数行像素电路电性连接以提供偶数行扫描信号至对应的偶数行像素电路；奇数行扫描信号或者偶数行扫描信号中的一种在一帧的第三时间段中依次具有一个脉冲的开始沿，奇数行扫描信号或者偶数行扫描信号中的另一种在一帧的第四时间段中依次具有一个脉冲的开始沿；其中，开始沿为上升沿或者下降沿中的一个；第三时间段的开始时间早于或者等于第四时间段的开始时间；且第四时间段的结束时间早于或者等于第一时间段的开始时间。
需要进行说明的是，一帧中的数据写入时间可以包括第三时间段和第四时间段，在一帧中，数据写入时间位于显示时间或者发光时间之前。各扫描信号中的每个脉冲对应一次数据信号的写入，每个脉冲的开始沿对应数据信号的开始写入时间。
可以理解的是，奇数行扫描信号依次具有一个脉冲的开始沿，可以依次写入数据信号至对应的奇数行像素电路；偶数行扫描信号依次具有一个脉冲的开始沿，可以依次写入数据信号至对应的偶数行像素电路。
在其中一个实施例中，如图1或者图2所示，奇数级栅极驱动单元例如可以为第一栅极驱动单元21、第三栅极驱动单元23等等，偶数级栅极驱动单元例如可以为第二栅极驱动单元22、第四栅极驱动单元24等等，奇数级栅极驱动单元用于根据第一起始信号输出对应的奇数行扫描信号，偶数级栅极驱动单元用于根据第二起始信号输出对应的偶数行扫描信号；其中，第一起始信号与第二起始信号的相位不同。
需要进行说明的是，在本实施中，第一栅极驱动单元21、第三栅极驱动单元23等等奇数级栅极驱动单元依次进行级联，在第一起始信号的控制下，可以通过奇数级栅极驱动单元控制输出的奇数行扫描信号的扫描时序；第二栅极驱动单元22、第四栅极驱动单元24等等偶数级栅极驱动单元依次进行级联，在第二起始信号的控制下，可以通过偶数级栅极驱动单元控制输出的偶数行扫描信号的扫描时序。如此便可以分别单独控制奇数行扫描信号的扫描时序、偶数行扫描信号的扫描时序，进而能够更好地实现相邻两行像素电路之间的显示时间间隔。
在其中一个实施例中，如图1所示，显示面板设置有第一边框区NA1、显示区AA以及第二边框区NA2，显示区AA位于第一边框区NA1与第二边框区NA2之间；奇数级栅极单元、偶数级栅极单元均位于第一边框区NA1或者第二边框区NA2。
在其中一个实施例中，如图2所示，显示面板设置有第一边框区NA1、显示区AA以及第二边框区NA2，显示区AA位于第一边框区NA1与第二边框区NA2之间；奇数级栅极单元位于第一边框区NA1或者第二边框区NA2中的一个，偶数级栅极单元位于第一边框区NA1或者第二边框区NA2中的另一个。
在其中一个实施例中，如图1或者图2所示，显示面板还包括多条扫描线例如扫描线SL1、扫描线SL2、扫描线SL3以及扫描线SL4等等，多条扫描线包括至少一奇数条扫描线和至少一偶数条扫描线，其中，奇数条扫描线例如可以为扫描线SL1、扫描线SL3等等，偶数条扫描线可以为扫描线SL2、扫描线SL4等等，一奇数条扫描线与对应的一奇数级栅极驱动单元电性连接、一奇数行像素电路与两个奇数条扫描线电性连接，一偶数条扫描线与对应的一偶数级栅极驱动单元电性连接、一偶数行像素电路与两个偶数条扫描线电性连接。
在其中一个实施例中，如图1或者图2以及图10所示，显示面板还包括多条用于传输数据信号的数据线DL，一数据线DL与两个不同列中的像素电路10电性连接，且分时写入数据信号至位于同一行中的两个像素电路10。
可以理解的是，在本实施例中，一数据线DL与两个不同列中的像素电路10电性连接，可以节省显示区AA内数据线DL的走线数量，提升显示面板的开口率。
如图3所示为改善前的显示时序示意图，在一帧的时间中，第N-2行像素电路、第N-1行像素电路、第N行像素电路、第N+1行像素电路、第N+2行像素电路等等依次逐行开始显示，两个相邻的行像素电路之间的显示时间间隔较短，亮度差异对比大，容易在视觉上感知到闪烁感，严重影响了超低频驱动显示情况下的画质。
上述实施例提供的显示面板的显示时序如图4所示，在一帧的时间中，第N-1行像素电路、第N+1行像素电路等等依次逐行开始显示，然后，第N-2行像素电路、第N行像素电路、第N+2行像素电路等等再依次逐行开始显示，如此可以拉长两个相邻的行像素电路之间的显示时间间隔，弱化视觉上的感知，减少或者消除了所能够感知到的闪烁感，进而能够实现超低频驱动显示，甚至能够支持1Hz下的超低频驱动显示。
如图5所示为改善前后的亮度测试情况，明显地，改善后的亮度测试情况优于改善前的亮度测试情况。
如图6所示为本申请实施例提供的改善前后的亮度变化幅度对比示意图，每幅小图中的横坐标用于表示时间，其单位为秒；纵坐标用于表示亮度，其单位为cd/m²或者nit。其中，图6中左上小图、右上小图以及左下小图均为改善前的亮度随时间变化情况，图6中的右下小图为改善后的亮度随时间变化情况。通过对比可知，右下小图相对于左上小图、右上小图以及左下小图中的任一个，其亮度变化的幅度明显较小。
在其中一个实施例中，如图7或者图8所示，至少一个氧化物薄膜晶体管包括第一晶体管，第一晶体管的源极/漏极中的一个与驱动晶体管T1的栅极电性连接；像素电路还包括第二晶体管和第三晶体管，第二晶体管的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的一个电性连接，第二晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个电性连接，第二晶体管的栅极与第N级栅极驱动单元的输出端电性连接，且第二晶体管为多晶硅薄膜晶体管；第三晶体管的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个电性连接，第三晶体管的栅极与第N-2级栅极驱动单元的输出端电性连接，且第三晶体管为多晶硅薄膜晶体管。
其中，第一晶体管可以为图7或者图8中所示的晶体管T8，第二晶体管可以为图7或者图8中所示的晶体管T3，第三晶体管可以为图7或者图8中所示的晶体管T4。第N级栅极驱动单元的输出端输出扫描信号Scan（n），第N-2级栅极驱动单元的输出端输出扫描信号Scan（n-2）。
在其中一个实施例中，像素电路还包括写入晶体管T2，写入晶体管T2的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个电性连接，写入晶体管T2的源极/漏极中的另一个接入数据信号Data，写入晶体管T2的栅极与第N级栅极驱动单元的输出端电性连接。
可以理解的是，在本实施例中，驱动晶体管T1的栅极仅连接第一晶体管的源极/漏极中的一个，可以有效降低驱动晶体管T1的栅极漏电流；而且配置第一晶体管为氧化物薄膜晶体管，可以进一步减少驱动晶体管T1的栅极漏电流，在数据信号Data写入至驱动晶体管T1的栅极之后更容易得到保持，以确保写入的数据信号Data更多地用于驱动晶体管T1的打开。
在其中一个实施例中，如图7所示，该像素电路还可以包括第三晶体管T4和第四晶体管T7，第三晶体管T4的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个电性连接，第三晶体管T4的源极/漏极中的另一个与第四晶体管T7的源极/漏极中的一个电性连接并接入初始信号Vint，第三晶体管T4的栅极接入扫描信号Scan（n-2），第四晶体管T7的栅极与写入晶体管T2的栅极、第二晶体管的栅极电性连接并接入扫描信号Scan（n）。
在其中一个实施例中，如图8所示，该像素电路还可以包括第三晶体管T4和第四晶体管T7，第三晶体管T4的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个、第四晶体管T7的源极/漏极中的一个电性连接，第三晶体管T4的源极/漏极中的另一个接入初始信号Vint，第三晶体管T4的栅极与第四晶体管T7的栅极电性连接并接入扫描信号Scan（n-2）。
在其中一个实施例中，如图7或者图8所示，该像素电路还可以包括晶体管T5、晶体管T6、发光器件D1以及存储电容Cst，晶体管T5的源极/漏极中的一个与存储电容Cst的一端电性连接并接入电源正信号ELVDD，存储电容Cst的另一端与驱动晶体管T1的栅极电性连接，晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的另一个电性连接，晶体管T6的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的一个电性连接，晶体管T6的源极/漏极中的另一个与第四晶体管T7的源极/漏极中的另一个、发光器件D1的阳极电性连接，发光器件D1的阴极接入电源负信号ELVSS或者零电位信号，晶体管T5的栅极与晶体管T6的栅极、第一晶体管的栅极电性连接并接入发光控制信号EM。
其中，第二晶体管、第三晶体管T4、第四晶体管T7、写入晶体管T2、驱动晶体管T1、晶体管T5以及晶体管T6均可以为P沟道型薄膜晶体管，具体还可以为低温多晶硅薄膜晶体管。第一晶体管可以为N沟道型薄膜晶体管，具体还可以为金属氧化物薄膜晶体管，例如，铟镓锌氧化物薄膜晶体管。
在其中一个实施例中，如图9或者图10所示，至少一个氧化物薄膜晶体管可以包括第一晶体管和第二晶体管，第一晶体管的源极/漏极中的一个与驱动晶体管T1的栅极电性连接，第一晶体管的栅极与第N-2级栅极驱动单元电性连接，第一晶体管的源极/漏极中的一个接入初始信号Vint；第二晶体管的源极/漏极中的一个与驱动晶体管T1的栅极电性连接，第二晶体管的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个电性连接，第二晶体管的栅极与第N级栅极驱动单元电性连接。
其中，在本实施例中，第一晶体管可以为图9中所示的晶体管T4，第二晶体管可以为图9中所示的晶体管T3。第一晶体管也可以为图10中所示的晶体管T41，第二晶体管可以为图10中所示的晶体管T31。第一晶体管也可以为图10中所示的晶体管T42，第二晶体管可以为图10中所示的晶体管T32。
可以理解的是，在本实施例中，驱动晶体管T1的栅极虽然连接了第一晶体管的源极/漏极中的一个和第二晶体管的源极/漏极中的一个，但是，由于第二晶体管、第一晶体管均采用了氧化物薄膜晶体管，其同样可以有效降低驱动晶体管T1的栅极漏电流，在数据信号Data写入至驱动晶体管T1的栅极之后也可以得到保持，能够确保写入的数据信号Data更多地用于驱动晶体管T1的打开。
像素电路还包括写入晶体管T2，写入晶体管T2的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个电性连接，写入晶体管T2的源极/漏极中的另一个接入数据信号Data，第二晶体管与写入晶体管T2同步打开或者关闭。
需要进行说明的是，写入晶体管T2的栅极接入扫描信号PScan（n），第二晶体管的栅极接入扫描信号NScan（n），第一晶体管的栅极接入扫描信号NScan（n-2）。
如图9所示，该像素电路还可以包括晶体管T7，晶体管T7的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个电性连接并接入初始信号Vint，晶体管T7的栅极与写入晶体管T2的栅极电性连接。
在其中一个实施例中，如图9所示，该像素电路还可以包括晶体管T5、晶体管T6、发光器件D1以及存储电容Cst，晶体管T5的源极/漏极中的一个与存储电容Cst的一端电性连接并接入电源正信号ELVDD，存储电容Cst的另一端与驱动晶体管T1的栅极电性连接，晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的另一个电性连接，晶体管T6的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的一个电性连接，晶体管T6的源极/漏极中的另一个与晶体管T7的源极/漏极中的另一个、发光器件D1的阳极电性连接，发光器件D1的阴极接入电源负信号ELVSS或者零电位信号，晶体管T5的栅极与晶体管T6的栅极电性连接并接入发光控制信号EM。
其中，晶体管T4、晶体管T7、写入晶体管T2、驱动晶体管T1、晶体管T5以及晶体管T6可以均为P沟道型薄膜晶体管，具体还可以为低温多晶硅薄膜晶体管。第二晶体管、第一晶体管可以为N沟道型薄膜晶体管，具体还可以为金属氧化物薄膜晶体管，例如，铟镓锌氧化物薄膜晶体管。
在其中一个实施例中，如图10所示的像素电路包括两个如图9所示的像素电路，与图9所示不同的是，在图10中，同行相邻的两个像素电路可以分时复用一个数据信号Data，能够减少数据线的数量，提高显示面板的开口率。
具体地，晶体管Tmux1、晶体管Tmux2分别在信号Demux1、信号Demux2的控制下分时导通，能够将数据信号Data的一个脉冲分时写入至左右两个像素电路中，以此能够减少数据线的数量。
在其中一个实施例中，本实施例提供一种显示装置，其包括上述至少一实施例中的显示面板。
可以理解的是，本实施例提供的显示装置，通过在像素电路中驱动晶体管的栅极电性连接至少一个氧化物薄膜晶体管，使得像素电路具有低漏电特性，可以较长时间保持像素电路中驱动晶体管的栅极电位，能够实现像素电路的低频驱动显示；在此基础上，配置奇数行像素电路或者偶数行像素电路中的一种、奇数行像素电路或者偶数行像素电路中的另一种在一帧的第一时间段、第二时间段中依次开始逐行显示，以拉长相邻两行像素电路之间的显示时间间隔至半帧时间左右，可以有效降低视觉上对相邻两行像素电路的亮度差异感知，减少或者消除了显示的闪烁现象，进而实现了显示面板或者显示装置的超低频驱动显示。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    栅极驱动电路，所述栅极驱动电路包括依次级联设置的奇数级栅极驱动单元和依次级联设置的偶数级栅极驱动单元；和
    多行像素电路，每行所述像素电路包括多个像素电路，其中，奇数行像素电路与对应的奇数级栅极驱动单元电性连接，偶数行像素电路与对应的偶数级栅极驱动单元电性连接；
    其中，所述像素电路包括驱动晶体管和至少一个氧化物薄膜晶体管，所述驱动晶体管的栅极与所述至少一个氧化物薄膜晶体管的源极/漏极中的一个电性连接。
  2. 根据权利要求1所述的显示面板，其中，所述至少一个氧化物薄膜晶体管包括第一晶体管，所述第一晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接；
    所述像素电路还包括：
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的一个电性连接，所述第二晶体管的源极/漏极中的另一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第二晶体管的栅极与第N级栅极驱动单元的输出端电性连接，且所述第二晶体管为多晶硅薄膜晶体管；和
    第三晶体管，所述第三晶体管的源极/漏极中的一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第三晶体管的栅极与第N-2级栅极驱动单元的输出端电性连接，且所述第三晶体管为多晶硅薄膜晶体管。
  3. 根据权利要求2所述的显示面板，其中，所述像素电路还包括第四晶体管，所述第四晶体管的源极/漏极的一个与所述第三晶体管的源极/漏极中的另一个电性连接并接入初始信号，所述第四晶体管的栅极与第N级栅极驱动单元的输出端或者第N-2级栅极驱动单元的输出端电性连接，且所述第四晶体管为多晶硅薄膜晶体管。
  4. 根据权利要求1所述的显示面板，其中，所述至少一个氧化物薄膜晶体管包括：
    第一晶体管，所述第一晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述第一晶体管的栅极与第N-2级栅极驱动单元电性连接，所述第一晶体管的源极/漏极中的一个接入初始信号；和
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述第二晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个电性连接，所述第二晶体管的栅极与第N级栅极驱动单元电性连接。
  5. 根据权利要求1所述的显示面板，其中，所述奇数行像素电路或者所述偶数行像素电路中的一种在一帧的第一时间段中依次开始逐行显示，所述奇数行像素电路或者所述偶数行像素电路中的另一种在所述一帧的第二时间段中依次开始逐行显示；
    其中，所述第一时间段的开始时间早于所述第二时间段的开始时间。
  6. 根据权利要求5所述的显示面板，其中，所述奇数级栅极驱动单元输出对应的奇数行扫描信号，所述偶数级栅极驱动单元输出对应的偶数行扫描信号；所述奇数级栅极驱动单元与所述奇数行像素电路电性连接以提供所述奇数行扫描信号至对应的奇数行像素电路，所述偶数级栅极驱动单元与所述偶数行像素电路电性连接以提供所述偶数行扫描信号至对应的偶数行像素电路；
    所述奇数行扫描信号或者所述偶数行扫描信号中的一种在所述一帧的第三时间段中依次具有一个脉冲的开始沿，所述奇数行扫描信号或者所述偶数行扫描信号中的另一种在所述一帧的第四时间段中依次具有一个脉冲的开始沿；
    其中，所述开始沿为上升沿或者下降沿中的一个；所述第三时间段的开始时间早于或者等于所述第四时间段的开始时间；且所述第四时间段的结束时间早于或者等于所述第一时间段的开始时间。
  7. 根据权利要求6所述的显示面板，其中，所述奇数级栅极驱动单元用于根据第一起始信号输出对应的所述奇数行扫描信号，所述偶数级栅极驱动单元用于根据第二起始信号输出对应的所述偶数行扫描信号；
    其中，所述第一起始信号与所述第二起始信号的相位不同。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板设置有第一边框区、显示区以及第二边框区，所述显示区位于所述第一边框区与所述第二边框区之间；所述奇数级栅极单元、所述偶数级栅极单元均位于所述第一边框区或者所述第二边框区。
  9. 根据权利要求7所述的显示面板，其中，所述显示面板设置有第一边框区、显示区以及第二边框区，所述显示区位于所述第一边框区与所述第二边框区之间；所述奇数级栅极单元位于所述第一边框区或者所述第二边框区中的一个，所述偶数级栅极单元位于所述第一边框区或者所述第二边框区中的另一个。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多条用于传输数据信号的数据线，一数据线与两个不同列中的像素电路电性连接，且分时写入数据信号至位于同一行中的两个像素电路。
  11. 一种显示装置，包括如权利要求1所述的显示面板。
  12. 根据权利要求11所述的显示装置，其中，所述显示面板还包括至少一奇数条扫描线和至少一偶数条扫描线；其中，一奇数条扫描线与对应的一奇数级栅极驱动单元电性连接，一奇数行像素电路与两个奇数条扫描线电性连接；一偶数条扫描线与对应的一偶数级栅极驱动单元电性连接，一偶数行像素电路与两个偶数条扫描线电性连接。
  13. 根据权利要求12所述的显示装置，其中，所述至少一个氧化物薄膜晶体管包括第一晶体管，所述第一晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接；
    所述像素电路还包括：
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的一个电性连接，所述第二晶体管的源极/漏极中的另一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第二晶体管的栅极与第N级栅极驱动单元的输出端电性连接，且所述第二晶体管为多晶硅薄膜晶体管；和
    第三晶体管，所述第三晶体管的源极/漏极中的一个与所述第一晶体管的源极/漏极中的另一个电性连接，所述第三晶体管的栅极与第N-2级栅极驱动单元的输出端电性连接，且所述第三晶体管为多晶硅薄膜晶体管。
  14. 根据权利要求13所述的显示装置，其中，所述像素电路还包括第四晶体管，所述第四晶体管的源极/漏极的一个与所述第三晶体管的源极/漏极中的另一个电性连接并接入初始信号，所述第四晶体管的栅极与第N级栅极驱动单元的输出端或者第N-2级栅极驱动单元的输出端电性连接，且所述第四晶体管为多晶硅薄膜晶体管。
  15. 根据权利要求12所述的显示装置，其中，所述至少一个氧化物薄膜晶体管包括：
    第一晶体管，所述第一晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述第一晶体管的栅极与第N-2级栅极驱动单元电性连接，所述第一晶体管的源极/漏极中的一个接入初始信号；和
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述第二晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个电性连接，所述第二晶体管的栅极与第N级栅极驱动单元电性连接。
  16. 根据权利要求12所述的显示装置，其中，所述奇数行像素电路或者所述偶数行像素电路中的一种在一帧的第一时间段中依次开始逐行显示，所述奇数行像素电路或者所述偶数行像素电路中的另一种在所述一帧的第二时间段中依次开始逐行显示；
    其中，所述第一时间段的开始时间早于所述第二时间段的开始时间。
  17. 根据权利要求16所述的显示装置，其中，所述奇数级栅极驱动单元输出对应的奇数行扫描信号，所述偶数级栅极驱动单元输出对应的偶数行扫描信号；所述奇数级栅极驱动单元与所述奇数行像素电路电性连接以提供所述奇数行扫描信号至对应的奇数行像素电路，所述偶数级栅极驱动单元与所述偶数行像素电路电性连接以提供所述偶数行扫描信号至对应的偶数行像素电路；
    所述奇数行扫描信号或者所述偶数行扫描信号中的一种在所述一帧的第三时间段中依次具有一个脉冲的开始沿，所述奇数行扫描信号或者所述偶数行扫描信号中的另一种在所述一帧的第四时间段中依次具有一个脉冲的开始沿；
    其中，所述开始沿为上升沿或者下降沿中的一个；所述第三时间段的开始时间早于或者等于所述第四时间段的开始时间；且所述第四时间段的结束时间早于或者等于所述第一时间段的开始时间。
  18. 根据权利要求17所述的显示装置，其中，所述奇数级栅极驱动单元用于根据第一起始信号输出对应的所述奇数行扫描信号，所述偶数级栅极驱动单元用于根据第二起始信号输出对应的所述偶数行扫描信号；
    其中，所述第一起始信号与所述第二起始信号的相位不同。
  19. 根据权利要求18所述的显示装置，其中，所述显示面板设置有第一边框区、显示区以及第二边框区，所述显示区位于所述第一边框区与所述第二边框区之间；所述奇数级栅极单元、所述偶数级栅极单元均位于所述第一边框区或者所述第二边框区。
  20. 根据权利要求18所述的显示装置，其中，所述显示面板设置有第一边框区、显示区以及第二边框区，所述显示区位于所述第一边框区与所述第二边框区之间；所述奇数级栅极单元位于所述第一边框区或者所述第二边框区中的一个，所述偶数级栅极单元位于所述第一边框区或者所述第二边框区中的另一个。
PCT/CN2022/075329 2022-01-25 2022-02-07 显示面板及显示装置 Ceased WO2023142154A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/638,112 US11749157B2 (en) 2022-01-25 2022-02-07 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210085674.0A CN114420029B (zh) 2022-01-25 2022-01-25 显示面板及显示装置
CN202210085674.0 2022-01-25

Publications (1)

Publication Number Publication Date
WO2023142154A1 true WO2023142154A1 (zh) 2023-08-03

Family

ID=81277556

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/075329 Ceased WO2023142154A1 (zh) 2022-01-25 2022-02-07 显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN114420029B (zh)
WO (1) WO2023142154A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119446065B (zh) * 2024-12-23 2026-01-30 武汉华星光电半导体显示技术有限公司 显示面板及其驱动方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080058055A (ko) * 2006-12-21 2008-06-25 엘지디스플레이 주식회사 액정표시장치의 구동 회로 및 방법
KR20110138006A (ko) * 2010-06-18 2011-12-26 엘지디스플레이 주식회사 액정 표시장치의 구동장치와 그 구동방법
CN103262148A (zh) * 2011-04-08 2013-08-21 夏普株式会社 扫描信号线驱动电路及具备其的显示装置
CN107492363A (zh) * 2017-09-28 2017-12-19 惠科股份有限公司 一种显示面板的驱动装置及驱动方法
CN110706671A (zh) * 2019-09-24 2020-01-17 深圳市华星光电半导体显示技术有限公司 驱动电路及其驱动方法与应用的显示面板
CN112863426A (zh) * 2021-01-08 2021-05-28 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
US20210201816A1 (en) * 2019-12-31 2021-07-01 Lg Display Co., Ltd. Gate driving circuit and display apparatus comprising the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5058505B2 (ja) * 2006-03-31 2012-10-24 キヤノン株式会社 表示装置
KR100844769B1 (ko) * 2006-11-09 2008-07-07 삼성에스디아이 주식회사 유기전계발광 표시장치의 구동방법
CN101329484B (zh) * 2007-06-22 2010-10-13 群康科技(深圳)有限公司 液晶显示装置之驱动电路及其驱动方法
KR102678548B1 (ko) * 2018-06-19 2024-06-26 삼성디스플레이 주식회사 표시장치
CN209625766U (zh) * 2018-12-03 2019-11-12 深圳市柔宇科技有限公司 显示装置和电子装置
CN112470208A (zh) * 2019-03-28 2021-03-09 京东方科技集团股份有限公司 栅极驱动单元、方法、栅极驱动电路、显示面板和装置
CN111564136B (zh) * 2020-07-16 2020-10-23 武汉华星光电半导体显示技术有限公司 像素电路及驱动方法、显示面板
CN112634833A (zh) * 2021-01-07 2021-04-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示面板
CN112909054A (zh) * 2021-01-26 2021-06-04 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080058055A (ko) * 2006-12-21 2008-06-25 엘지디스플레이 주식회사 액정표시장치의 구동 회로 및 방법
KR20110138006A (ko) * 2010-06-18 2011-12-26 엘지디스플레이 주식회사 액정 표시장치의 구동장치와 그 구동방법
CN103262148A (zh) * 2011-04-08 2013-08-21 夏普株式会社 扫描信号线驱动电路及具备其的显示装置
CN107492363A (zh) * 2017-09-28 2017-12-19 惠科股份有限公司 一种显示面板的驱动装置及驱动方法
CN110706671A (zh) * 2019-09-24 2020-01-17 深圳市华星光电半导体显示技术有限公司 驱动电路及其驱动方法与应用的显示面板
US20210201816A1 (en) * 2019-12-31 2021-07-01 Lg Display Co., Ltd. Gate driving circuit and display apparatus comprising the same
CN112863426A (zh) * 2021-01-08 2021-05-28 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN114420029A (zh) 2022-04-29
CN114420029B (zh) 2023-08-22

Similar Documents

Publication Publication Date Title
CN111508426B (zh) 像素电路及其驱动方法、显示面板
CN115311982A (zh) 显示面板及其驱动方法和显示装置
US10650716B2 (en) Shift register unit, shift register, driving method, display panel and display apparatus
CN111354309A (zh) 显示驱动模组、显示驱动方法和显示装置
WO2021223565A1 (zh) 移位寄存器、驱动方法、驱动控制电路及显示装置
CN115410529A (zh) 像素补偿电路及显示面板
CN114220839B (zh) 显示面板
WO2017193627A1 (zh) 移位寄存器、栅极驱动电路和显示装置
WO2023142043A1 (zh) 显示基板、显示装置、显示基板的制作方法
US20230111763A1 (en) Display panel, method for driving display panel, and display device
CN112735318A (zh) 移位寄存电路及其驱动方法、显示面板及显示装置
CN116597780B (zh) 显示面板及显示装置
CN111402782A (zh) 一种数字驱动像素电路及数字驱动像素的方法
CN118737032A (zh) 一种显示面板及显示装置
CN118471141A (zh) 一种显示面板及显示装置
US11749157B2 (en) Display panel and display device
US20240021118A1 (en) Driving circuit and display panel
US20240321179A1 (en) Display panels including gate driving circuit and display devices including the same
WO2024198436A1 (zh) 像素驱动电路和显示面板
WO2023142154A1 (zh) 显示面板及显示装置
WO2024087402A1 (zh) 像素电路及其驱动方法、以及显示装置
US11386847B2 (en) Organic light emitting diode display device
US11887541B2 (en) Further reduction of power consumption in display device with low-frequency driving
US12260824B2 (en) Pixel driving circuit and display panel
CN119600929A (zh) 显示面板的驱动方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22922978

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22922978

Country of ref document: EP

Kind code of ref document: A1