WO2023141921A1 - 显示基板及其制备方法和显示装置 - Google Patents

显示基板及其制备方法和显示装置 Download PDF

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Publication number
WO2023141921A1
WO2023141921A1 PCT/CN2022/074526 CN2022074526W WO2023141921A1 WO 2023141921 A1 WO2023141921 A1 WO 2023141921A1 CN 2022074526 W CN2022074526 W CN 2022074526W WO 2023141921 A1 WO2023141921 A1 WO 2023141921A1
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Prior art keywords
layer
transistor
base substrate
source
active layer
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PCT/CN2022/074526
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English (en)
French (fr)
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关峰
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京东方科技集团股份有限公司
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Priority to CN202280000099.8A priority Critical patent/CN116941037A/zh
Priority to PCT/CN2022/074526 priority patent/WO2023141921A1/zh
Publication of WO2023141921A1 publication Critical patent/WO2023141921A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the display field, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • a display substrate generally includes a plurality of pixel units arranged in an array.
  • the pixel unit includes a pixel driving circuit and a light emitting element.
  • the pixel driving circuit includes a plurality of transistors and these transistors are located in the same layer structure. Limited by the transistor manufacturing process, it is difficult to further reduce the area occupied by a single transistor on the plane parallel to the substrate, which will make it difficult to further reduce the area occupied by the pixel driving circuit on the plane parallel to the substrate. The resolution of the device is difficult to further improve.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate, a manufacturing method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate and a first transistor layer and a second transistor layer arranged in sequence along a direction away from the base substrate, the first transistor layer includes a first an active layer, the second transistor layer includes a second active layer, at least one insulating layer is disposed between the first active layer and the second active layer;
  • the materials of the first active layer and the second active layer both include low-temperature polysilicon material, and the first active layer includes at least one first channel region and at least one first source-drain doped region, so The second active layer includes at least one second channel region and at least one second source-drain doped region, and the orthographic projection of at least one second source-drain doped region on the base substrate is the same as at least one of the second doped source-drain regions.
  • the orthographic projections of the first source-drain doped region on the base substrate overlap;
  • At least one of the second doped source and drain regions is connected to the corresponding first doped source and drain region through a connection portion filled in the first via hole on the insulating layer.
  • the material of the connection part includes at least two kinds of silicon with different crystallinities and dopant ions for conductorization.
  • the at least two types of silicon with different crystallinities include: amorphous silicon and polycrystalline silicon.
  • the connecting portion has at least 2 doping concentration centers along a direction perpendicular to the base substrate.
  • the slope angle of the first via hole is 30°-75°.
  • the orthographic projection of at least one first channel region on the substrate overlaps with the orthographic projection of at least one second channel region on the substrate.
  • a shielding electrode pattern is disposed between the first active layer and the second active layer;
  • the orthographic projection of the shielding electrode pattern on the base substrate covers a region where the orthographic projections of the first channel region and the second channel region overlap on the base substrate.
  • the first transistor layer further includes:
  • a first gate insulating layer located on a side of the first active layer away from the base substrate
  • the first conductive layer is located on the side of the first gate insulating layer away from the base substrate, and the first conductive layer includes transistors located in the first transistor layer corresponding to the first channel region the grid.
  • the first conductive layer further includes: a first end plate of a capacitor
  • the first transistor layer also includes:
  • the second gate insulating layer is located on the side of the first conductive layer away from the base substrate
  • the second conductive layer is located on a side of the second gate insulating layer away from the base substrate, and the second conductive layer includes a second end plate opposite to the first end plate of the capacitor.
  • the shielding electrode pattern when a shielding electrode pattern is disposed between the first active layer and the second active layer, the shielding electrode pattern is located on the second conductive layer.
  • the second transistor layer further includes:
  • the second buffer layer is located on a side of the second active layer close to the base substrate and in contact with the second active layer.
  • the thickness of the second buffer layer is:
  • the second transistor layer further includes:
  • a third gate insulating layer located on a side of the second active layer away from the base substrate;
  • the third conductive layer is located on the side of the third insulating layer away from the base substrate, and the third conductive layer includes transistors located in the second transistor layer corresponding to the second channel region. grid.
  • the display substrate further includes:
  • the fourth conductive layer is located on the side of the interlayer dielectric layer away from the base substrate, the fourth conductive layer includes: a data line and a conductive connection structure, and the conductive connection structure is connected to the first through a via hole.
  • the display substrate further includes:
  • planarization layer located on a side of the fourth conductive layer away from the base substrate
  • the first electrode layer is located on the side of the planarization layer away from the base substrate, the first electrode layer includes a plurality of first electrodes, and the first electrodes are connected to the corresponding conductive connections through via holes structure to be electrically connected to the corresponding first source-drain doped region or the second source-drain doped region;
  • the first pixel defining layer is located on the side of the first electrode layer away from the base substrate, and a plurality of first pixel accommodation holes are formed on the first pixel defining layer, and the first pixel accommodation holes are connected to the corresponding first electrode;
  • a light-emitting layer including a plurality of electroluminescent patterns, and the electroluminescent patterns are located in the corresponding first pixel receiving holes;
  • the second electrode layer is located on a side of the first pixel defining layer away from the base substrate.
  • the material of the electroluminescent pattern includes: an organic luminescent material or a quantum dot material.
  • the display substrate further includes:
  • an encapsulation layer located on a side of the second electrode layer away from the base substrate;
  • a color-resist layer is located on a side of the packaging layer away from the base substrate, and the color-resist layer includes a plurality of color-resist patterns corresponding to the electroluminescent patterns one-to-one.
  • the material of the electroluminescent pattern includes an organic light-emitting material
  • the display substrate further includes:
  • the light conversion layer is located between the encapsulation layer and the color resistance layer, and the light conversion layer includes a plurality of light conversion color filters corresponding to at least part of the electroluminescence patterns;
  • the material of the light conversion color filter includes quantum dot material.
  • the display substrate includes a plurality of pixel units on the base substrate, and the pixel units include a light emitting element and a pixel driving circuit for driving the light emitting element;
  • the pixel driving circuit includes: a driving transistor configured to output a corresponding driving current to the corresponding light-emitting element according to its own gate-source power supply.
  • the driving transistor is located in the first transistor layer, and the channel region and source-drain doped regions of the driving transistor are located in the first active layer.
  • the pixel driving circuit further includes: a data write transistor, a threshold compensation transistor, a first reset transistor, a second reset transistor, a first light emission control transistor, a second light emission control transistor, and a capacitor;
  • the gate of the data writing transistor is electrically connected to the corresponding gate line, the first pole of the data writing transistor is electrically connected to the corresponding data line, and the second pole of the data writing transistor is connected to the second pole of the driving transistor.
  • the gate of the threshold compensation transistor is electrically connected to the corresponding gate line, the first pole of the threshold compensation transistor is electrically connected to the second pole of the driving transistor, and the second pole of the threshold compensation transistor is connected to the driving transistor. the gate electrical connection of the transistor;
  • the gate of the first reset transistor is electrically connected to the corresponding reset control signal line, the first pole of the first reset transistor is electrically connected to the reset voltage transmission line, and the second pole of the first reset transistor is connected to the drive transistor.
  • the gate of the second reset transistor is electrically connected to the corresponding reset control signal line or gate line
  • the first pole of the second reset transistor is electrically connected to the reset voltage transmission line
  • the second pole of the second reset transistor is electrically connected to the light emitting element.
  • the first electrode is electrically connected;
  • the gate of the first light emission control transistor is electrically connected to the light emission control signal line, the first pole of the first light emission control transistor is electrically connected to the working voltage transmission line, and the second pole of the first light emission control transistor is connected to the driving transistor The first pole is electrically connected;
  • the gate of the second light emission control transistor is electrically connected to the light emission control signal line, the first pole of the second light emission control transistor is connected to the second pole of the driving transistor, and the second pole of the second light emission control transistor is connected to the The first electrode of the light emitting element is electrically connected;
  • the first terminal plate of the capacitor is connected to the gate of the driving transistor, and the second terminal plate of the capacitor is connected to the working voltage transmission line.
  • the data write transistor is located in the first transistor layer, and the channel region and the source-drain doped region of the data write transistor are located in the first active layer;
  • the threshold compensation transistor is located in the first transistor layer, and the channel region and the source-drain doped region of the threshold compensation transistor are located in the first active layer;
  • the first reset transistor is located in the first transistor layer, and the channel region and the source-drain doped region of the first reset transistor are located in the first active layer;
  • the second reset transistor is located in the second transistor layer, and the channel region and the source-drain doped region of the second reset transistor are located in the second active layer;
  • the first light emission control transistor is located in the second transistor layer, and the channel region and source and drain doped regions of the first light emission control transistor are located in the second active layer;
  • the second light emission control transistor is located in the second transistor layer, and the channel region and source-drain doped regions of the second light emission control transistor are located in the second active layer.
  • an embodiment of the present disclosure further provides a display device, which includes: the display substrate as provided in the first aspect above.
  • an embodiment of the present disclosure also provides a method for preparing a display substrate, wherein the display substrate is the display substrate provided in the first aspect above, and the preparation method includes:
  • a first transistor layer is formed on one side of the base substrate, the first transistor layer includes a first active layer, the material of the first active layer includes a low-temperature polysilicon material, and the first active layer includes at least one a first channel region and at least one first source-drain doped region;
  • a second transistor layer is formed on the side of the first transistor layer away from the base substrate, the first transistor layer includes a second active layer, and the first active layer and the second active layer are in between At least one insulating layer is provided, the material of the second active layer includes low-temperature polysilicon material, the second active layer includes at least one second channel region and at least one second source-drain doped region, at least one The orthographic projection of the second source-drain doped region on the substrate overlaps with the orthographic projection of at least one of the first source-drain doped regions on the substrate, and at least one of the first The two doped source and drain regions are connected to the corresponding first doped source and drain regions through the connection portion filled in the first via hole on the insulating layer.
  • the step of forming the first transistor layer includes:
  • first conductive layer on a side of the first gate insulating layer away from the base substrate, the first conductive layer including gates of transistors located in the first transistor layer;
  • the first conductive layer as a mask for doping, perform ion implantation on the first polysilicon pattern, and part of the conductors on the first polysilicon pattern that are not blocked by the first conductive layer Form the first source-drain doped region, and the part of the first polysilicon pattern that is blocked by the first conductive layer serves as the first channel region.
  • the step of forming the second transistor layer includes:
  • the third conductive layer including gates of transistors located in the second transistor layer;
  • the third conductive layer as a mask for doping, perform ion implantation on the second polysilicon pattern, and part of the conductors on the second polysilicon pattern not covered by the third conductive layer Forming the second source-drain doped region and the connecting portion, and the part of the second polysilicon pattern covered by the third conductive layer serving as the second channel region.
  • the step of forming the second transistor layer includes:
  • a patterned photoresist layer is formed on a side of the second polysilicon pattern away from the second polysilicon pattern, and the patterned photoresist layer covers a region where the second channel region is to be formed subsequently And exposing the region where the second source-drain doped region and the connecting portion are to be formed later;
  • the second polysilicon pattern is not covered by the patterned photoresist layer
  • the covered part is conductorized as the second source-drain doped region and the connection part, and the part of the second polysilicon pattern covered by the patterned photoresist layer is used as the second channel region.
  • the step of performing ion implantation on the second polysilicon pattern includes:
  • the ion implantation process is performed by using multiple ion implantation processes, so that the part of the second polysilicon pattern filled in the first via hole is conductorized to form the connection part, and the connection part is perpendicular to the There are at least two doping concentration centers in the direction of the base substrate.
  • the ion beam energy of the ion implantation is 5KeV-90KeV;
  • the ion beam dose of the ion implantation is 1017/cm2-1022/cm2.
  • the step of forming a second polysilicon material thin film on the side of the first transistor layer away from the base substrate it also includes:
  • a second buffer layer is formed on the side of the first transistor layer away from the base substrate, and the thickness of the second buffer layer is:
  • FIG. 1 is a schematic cross-sectional view of a partial area on a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic cross-sectional view of a partial area on a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is another schematic cross-sectional view of a partial area on a display substrate provided by an embodiment of the present disclosure
  • FIG. 4 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a distribution structure of transistors in the pixel driving circuit shown in FIG. 6;
  • FIG. 8 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is another schematic cross-sectional view of a partial area on a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure
  • FIG. 11 is another flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure.
  • 12A-12N are cross-sectional schematic diagrams of intermediate products of display substrates prepared by the preparation method shown in FIG. 11 ;
  • Fig. 13 is another flow chart of the method for preparing a display substrate provided by an embodiment of the present disclosure
  • 14A-14B are schematic cross-sectional views of ion implantation using a patterned photoresist layer.
  • LTPS-TFTs are arranged along the direction parallel to the substrate substrate; that is to say , all low temperature polysilicon thin film transistors are located in the same transistor layer structure; specifically, the active layers of all LTPS-TFTs are arranged in the same layer.
  • LTPS-TFT it is difficult to further reduce the area occupied by a single pixel driving circuit on a plane parallel to the base substrate, and it is difficult to further improve the resolution of the display device.
  • Fig. 1 is a schematic cross-sectional view of a partial area of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a base substrate 1, a first transistor layer and a second transistor layer, and the first transistor layer and the second transistor layer are sequentially arranged along a direction away from the base substrate 1 .
  • the first transistor layer includes a first active layer 2
  • the second transistor layer includes a second active layer 3
  • at least one insulating layer is disposed between the first active layer 2 and the second active layer 3 .
  • the materials of the first active layer 2 and the second active layer 3 both include low-temperature polysilicon material, the first active layer 2 includes at least one first channel region 201 and at least one first source-drain doped region 202, the second The active layer 3 includes at least one second channel region 301 and at least one second source-drain doped region 302, the orthographic projection of the at least one second source-drain doped region 302 on the base substrate 1 and the at least one first source The orthographic projection of the doped drain region 202 on the substrate 1 overlaps, and at least one second doped source and drain region 302 is connected to the corresponding first via hole 401 through the connection portion 302a filled in the first via hole 401 on the insulating layer 4. The source and drain doped regions 202 are connected.
  • the “transistor layer” in the embodiments of the present disclosure refers to the layer structure formed with transistors; the “channel region” is the part with semiconductor characteristics in the active layer, which is used as the active channel of the transistor;
  • the “source-drain doped region” in the disclosed embodiments refers to the part of the active layer that is conductorized by doping, and can be used as the source and drain of the transistor.
  • the channel region and the source-drain doped region belonging to the same active layer may be a low-temperature polysilicon layer integrally formed.
  • the stacking design of the two transistor layer structures and the overlapping of the active layers in the two transistor layer structures that is, the transistors in the pixel driving circuit can be distributed in the two transistor layer structures as required, and The source and drain doped regions of at least two transistors in the pixel driving circuit overlap in the direction perpendicular to the substrate, and this design can reduce the occupied area of the pixel driving circuit on a plane parallel to the substrate .
  • the connected two transistors are respectively arranged on the first transistor layer and the second transistor layer, and the source-drain doped region (that is, the second source-drain doped region 302 ) of one transistor located in the second transistor layer is connected to the first transistor layer
  • One source-drain doped region of the transistor layer namely the first source-drain doped region 202
  • the material of the connection part includes at least two kinds of silicon with different crystallinity and dopant ions for conductorization, that is to say, the connection part and the second source-drain doped region can be based on the doping of the same silicon material film.
  • the process is simultaneously prepared, and at this time, the connection part can be regarded as a part of the second source-drain doped region.
  • the source-drain doped regions of two transistors located in different transistor layers are connected through vias, so there is no need to additionally arrange other conductive structures for electrically connecting the source-drain doped regions of the two transistors , so the wiring space can also be saved to a certain extent, which is beneficial to reducing the area occupied by the pixel driving circuit on the plane parallel to the base substrate.
  • the preparation process of the second active layer 3 is as follows: first, an amorphous silicon ( ⁇ -Si) material film is formed, and the amorphous silicon material film fills the first via hole 401; Technology (ELA) irradiates the amorphous silicon material film with laser to form a polysilicon material film; then the polysilicon material film is patterned (also known as patterning process, usually including photoresist coating, exposure, development, film engraving, etc.
  • ⁇ -Si amorphous silicon
  • ELA irradiates the amorphous silicon material film with laser to form a polysilicon material film
  • the polysilicon material film is patterned (also known as patterning process, usually including photoresist coating, exposure, development, film engraving, etc.
  • the polysilicon pattern fills the first via hole 401; then, as required, ion implantation is performed on a part of the polysilicon pattern to conductorize the corresponding region, and the second via hole 401 is obtained. source layer.
  • the conductorized part of the polysilicon pattern is used as the source-drain doping region and the connection part, and the part of the polysilicon pattern that is not conductorized and maintains semiconductor characteristics is used as a channel region.
  • the conventional ELA process is still adopted, and only It is ensured that the part of the amorphous silicon material film above the active layer is crystallized as completely as possible, while the part of the amorphous silicon material film located in the first via hole may be in a mixed state of amorphous silicon and polysilicon.
  • the part of the polysilicon pattern obtained through the crystallization process and the patterning process, which is located in the via hole needs to be subsequently ion-implanted to achieve conduction, regardless of whether it is amorphous silicon or polysilicon.
  • the material of the connection portion 302a finally filled in the first via hole 401 includes: amorphous silicon, polysilicon and dopant ions for conductorization.
  • the connecting portion 302a has at least 2 doping concentration centers along a direction perpendicular to the base substrate 1 .
  • the part of the polysilicon pattern used to form the second active layer 3 located in the first via hole 401 has a relatively thick thickness, and the ion implantation concentration center range of the single ion implantation process is limited, and the single ion implantation process The implantation process cannot guarantee that the part of the polysilicon pattern located in the first via hole 401 can exhibit better conductivity, so multiple ion implantation processes are used in the implementation of the present disclosure and different ion implantation depths are selected to ensure that the polysilicon pattern is located in the first via hole 401.
  • the formed connecting portion 302 has at least two doping concentration centers along a direction perpendicular to the base substrate 1 .
  • the depth of ion implantation can be adjusted by changing the ion beam energy of ion implantation; generally, without considering other factors, the higher the ion beam energy, the deeper the ion implantation depth, and the formed The center of doping concentration is also deeper.
  • the slope angle ⁇ of the first via hole 401 is 30° ⁇ 75°.
  • the slope angle of the via hole refers to the angle formed by the slope surface used to enclose the via hole in the corresponding structure and the bottom surface of the corresponding structure.
  • the first via hole 401 is a tapered hole, and the diameter of the hole gradually decreases along the direction close to the base substrate 1 , which is beneficial to the formation of polysilicon by laser energy density irradiation during the ELA process.
  • the larger the slope angle ⁇ the steeper the slope of the via hole.
  • the slope angle ⁇ of the first via hole 401 is set to 30° ⁇ 75°.
  • the slope angle is 30°, 45°, 60°, 75°.
  • FIG. 2 is another schematic cross-sectional view of a partial area on the display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the first channel region 201 on the base substrate 1 Orthographic projections of the two channel regions 301 on the base substrate 1 overlap.
  • the overlapping area of the first active layer 2 and the second active layer 3 can be made larger, which is more conducive to reducing the area occupied by the pixel driving circuit on the plane parallel to the base substrate 1 .
  • a shielding electrode pattern 801 is arranged between the first active layer 2 and the second active layer 3; the orthographic projection of the shielding electrode pattern 801 on the substrate 1 covers the first channel region 201 and the second trench
  • the two track regions 301 orthographically project overlapping regions on the base substrate 1 .
  • Fig. 3 is another schematic cross-sectional view of a partial area on the display substrate provided by an embodiment of the present disclosure.
  • the first transistor layer further includes: a first gate insulating layer 5 and a second conductive Layer 8.
  • the first gate insulating layer 5 is located on the side of the first active layer 2 away from the base substrate 1; the first conductive layer 6 is located on the side of the first gate insulating layer 5 away from the base substrate 1, and the first conductive layer 6
  • Each transistor T in the first transistor layer includes a gate g corresponding to the first channel region 201 .
  • a first buffer layer 21 is further disposed between the first active layer 2 and the base substrate 1 .
  • the first conductive layer 6 further includes: a first terminal plate c1 of the capacitor C; the first transistor layer further includes: a second gate insulating layer 7 and a second conductive layer 8 .
  • the second gate insulating layer 7 is located on the side of the first conductive layer 6 away from the base substrate 1; the second conductive layer 8 is located on the side of the second gate insulating layer 7 away from the base substrate 1, and the second conductive layer 8 includes A second end plate c2 arranged opposite to the first end plate c1 of the capacitor C.
  • the shielding electrode pattern 801 when the shielding electrode pattern 801 is disposed between the first active layer 2 and the second active layer 3 , the shielding electrode pattern 801 is located on the second conductive layer 8 .
  • the second transistor layer further includes: a third gate insulating layer 9 and a third conductive layer 10 .
  • the third gate insulating layer 9 is located on the side of the second active layer 3 away from the base substrate 1; the third conductive layer 10 is located on the side of the third gate insulating layer 9 away from the base substrate 1, and the third conductive layer 10
  • Each transistor in the second transistor layer includes a gate g corresponding to the second channel region 301 .
  • the second transistor layer further includes: a second buffer layer 22 , the second buffer layer 22 is located on a side of the second active layer 3 close to the base substrate 1 and is in contact with the second active layer 3 .
  • the setting of the second buffer layer 22 can effectively improve the crystallization effect of the second active layer 3 .
  • a part of the amorphous silicon material film formed during the preparation of the second active layer 3 will cover the surface of the second conductive layer 8, and a part will cover the surface of the second gate insulating layer 7.
  • a part of the amorphous silicon material film formed in the process of preparing the second active layer 3 will cover the surface of the first conductive layer 6, and a part will cover On the surface of the first gate insulating layer 5), that is to say, two different materials are contacted under the amorphous silicon material film; during the crystallization process of the amorphous silicon material film, the amorphous silicon and the conductive layer are in contact with each other. A large difference in crystallization occurs in the amorphous silicon in contact with the gate insulating layer, resulting in a large difference in the formed crystal structure.
  • a layer of second buffer layer 22 used to be in contact with the second active layer 3 is formed before preparing the second active layer 3, so as to ensure that the crystallization process Crystallization uniformity of amorphous silicon at each position.
  • the thickness of the second buffer layer 22 is: Further optionally, the thickness of the second buffer layer 22 is
  • the display substrate further includes: an interlayer dielectric layer 11 and a fourth conductive layer 12 .
  • the interlayer dielectric layer 11 is located on the side of the second transistor layer away from the base substrate 1;
  • the fourth conductive layer 12 is located on the side of the interlayer dielectric layer 11 away from the base substrate 1, and the fourth conductive layer 12 includes: wire (not shown in FIG. 3 ) and a conductive connection structure P, the conductive connection structure P is connected to the first source-drain doped region 202 or the second source-drain doped region 302 through a via hole.
  • the first source-drain doped region 202 and the second source-drain doped region 302 can lead out the source and drain of the transistor through the corresponding conductive connection structure P according to actual circuit needs, so as to facilitate the connection with other transistors.
  • the electrical structure is electrically connected. It should be noted that, in the embodiment of the present disclosure, the doped source and drain regions of each transistor on the display substrate are not provided with a corresponding conductive connection structure P, but are configured according to actual needs.
  • FIG. 3 only 4 transistors T and 1 capacitor C are exemplarily shown, wherein 2 transistors T are located in the first transistor layer, and the other 2 transistors T are located in the second transistor layer.
  • only four conductive connection structures P are shown in FIG. 3 as an example. The situation shown in FIG. 3 is only used as an example, and does not limit the technical solution of the present disclosure.
  • Fig. 4 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes: a planarization layer 13, a first pixel defining layer 15, Light emitting layer, second electrode 17 layers.
  • the planarization layer 13 is located on the side of the fourth conductive layer 12 away from the base substrate 1; the first electrode layer 14 is located on the side of the planarization layer 13 away from the base substrate 1, and the first electrode layer includes a plurality of first electrodes , the first electrode 14 is connected to the corresponding conductive connection structure P through a via hole so as to be electrically connected to the corresponding first source-drain doped region 202 or the second source-drain doped region 302; the first pixel defining layer 15 is located on the first electrode The layer is far away from the side of the base substrate 1, and a plurality of first pixel accommodation holes are formed on the first pixel defining layer 15, and the first pixel accommodation holes are connected to the corresponding first electrodes 14; the light emitting layer includes a plurality of electroluminescent patterns 16.
  • the electroluminescent pattern 16 is located in the corresponding first pixel receiving hole; the second electrode layer is located on the side of the first pixel defining layer 15 away from the base substrate 1, and the second electrode layer includes a second electrode 17, optionally The second electrode 17 is a planar electrode.
  • the first electrode 14 , the electroluminescence pattern 16 in the first pixel accommodation hole corresponding to the first electrode 14 and the second electrode 17 form a light emitting element EL.
  • some functional layer structures can also be arranged according to actual needs, such as electron blocking layer, hole transport layer , electron transport layer, hole blocking layer, etc.
  • the material of the electroluminescence pattern 16 is an organic light emitting material, and at this time, the light emitting element EL has an organic light emitting diode (Organic Light Emitting Diode, OLED for short).
  • OLED Organic Light Emitting Diode
  • the material of the electroluminescence pattern 16 is a quantum dot material
  • the light emitting element EL is a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED for short).
  • the electroluminescence pattern 16 may have a shape in which a plurality of quantum dots are dispersed in a base member.
  • quantum dots can be semiconductor nanocrystals, and can have various shapes such as spherical, conical, multi-armed and/or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplate particles, quantum rods, or Quantum slice.
  • the quantum rods may be quantum dots having an aspect ratio (length-to-diameter ratio) (length:width ratio) of greater than about 1, such as greater than or equal to about 2, greater than or equal to about 3, or greater than or equal to about 5.
  • a quantum rod can have an aspect ratio of about 50 or less, about 30 or less, or about 20 or less.
  • Quantum dots can have, for example, a particle diameter (average maximum particle length for non-spherical shapes) of about 1 nm to about 100 nm, about 1 nm to about 80 nm, about 1 nm to about 50 nm, or about 1 nm to 20 nm, for example.
  • a particle diameter average maximum particle length for non-spherical shapes
  • the energy bandgap of the quantum dots can be controlled according to the size and composition of the quantum dots, and thus the emission wavelength can be controlled.
  • a quantum dot may have a narrow energy bandgap and thus be configured to emit light in a relatively long wavelength region as the size of the quantum dot increases, and a broad energy bandgap as the size of the quantum dot decreases.
  • the bandgap is thus configured to emit light in a relatively short wavelength region.
  • quantum dots may be configured to emit light in a predetermined wavelength region of the visible region according to their size and/or composition.
  • quantum dots can be configured to emit blue light, red light, or green light, and blue light can have a peak emission wavelength ( ⁇ max), for example, in the range of about 430 nm to about 480 nm, and red light can have a peak emission wavelength ( ⁇ max), for example, in the range of about 600 nm to about 650 nm.
  • the peak emission wavelength ( ⁇ max) of , and the green light may have a peak emission wavelength ( ⁇ max) in, for example, about 520 nm to about 560 nm.
  • the average particle size of quantum dots configured to emit blue light can be, for example, less than or equal to about 4.5 nm, and, for example, less than or equal to about 4.3 nm, less than or equal to about 4.2 nm, less than or equal to about 4.1 nm, or less than or equal to about 4.0nm.
  • the average particle size of the quantum dots can be from about 2.0 nm to about 4.5 nm, such as from about 2.0 nm to about 4.3 nm, from about 2.0 nm to about 4.2 nm, from about 2.0 nm to about 4.1 nm, or about 2.0 nm. nm to about 4.0 nm.
  • Quantum dots can have, for example, about 10% or more, about 20% or more, about 30% or more, about 50% or more, about 60% or more, about 70% or more, or about 70% or more. Equivalent to a quantum yield of about 90%.
  • Quantum dots can have a relatively narrow half width (FWHM).
  • FWHM is a width corresponding to a wavelength half of a peak absorption point, and when the FWHM is narrow, it can be configured to emit light in a narrow wavelength region, and high color purity can be obtained.
  • Quantum dots can have, for example, less than or equal to about 50 nm, less than or equal to about 49 nm, less than or equal to about 48 nm, less than or equal to about 47 nm, less than or equal to about 46 nm, less than or equal to about 45 nm, less than or equal to about 44 nm, less than or equal to About 43 nm or less, about 42 nm or less, about 41 nm or less, about 40 nm or less, about 39 nm or less, about 38 nm or less, about 37 nm or less, about 36 nm or less, about 35 nm or less , less than or equal to about 34 nm, less than or equal to about 33 nm, less than or equal to about 32 nm, less than or equal to about 31 nm, less than or equal to about 30 nm, less than or equal to about 29 nm, or less than or equal to about 28 nm.
  • it may have, for example, about 2 nm to about 49 nm, about 2 nm to about 48 nm, about 2 nm to about 47 nm, about 2 nm to about 46 nm, about 2 nm to about 45 nm, about 2 nm to about 44 nm, about 2 nm to about 43 nm, About 2nm to about 42nm, about 2nm to about 41nm, about 2nm to about 40nm, about 2nm to about 39nm, about 2nm to about 38nm, about 2nm to about 37nm, about 2nm to about 36nm, about 2nm to about 35nm, about 2nm FWHM to about 34 nm, about 2 nm to about 33 nm, about 2 nm to about 32 nm, about 2 nm to about 31 nm, about 2 nm to about 30 nm, about 2 nm to about 29 nm, or about 2 nm
  • quantum dots may include II-VI semiconductor compounds, III-V semiconductor compounds, IV-VI semiconductor compounds, IV semiconductor compounds, I-III-VI semiconductor compounds, I-II-IV-VI semiconductor compounds , II-III-V semiconductor compound, or a combination thereof.
  • Group II-VI semiconductor compounds may for example be selected from: binary compounds such as CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, or mixtures thereof; ternary compounds such as CdSeS, CdSeTe, CdSTe , ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnT
  • Group III-V semiconductor compounds can be selected, for example, from binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, or mixtures thereof; ternary compounds such as GaNP, GaNAs , GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb, or mixtures thereof; and quaternary compounds such as GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, or a mixture thereof, but not limited thereto.
  • Group IV-VI semiconductor compounds may for example be selected from: binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, or mixtures thereof; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe , SnPbTe, or mixtures thereof; and quaternary compounds such as, but not limited to, SnPbSSe, SnPbSeTe, SnPbSTe, or mixtures thereof.
  • Group IV semiconductors may be selected from, for example, elemental (unary) semiconductors such as Si, Ge, or mixtures thereof; and binary semiconductor compounds such as SiC, SiGe, and mixtures thereof, but are not limited thereto.
  • the group I-III-VI semiconductor compound may be, for example, CuInSe2, CuInS2, CuInGaSe, CuInGaS, or a mixture thereof, but is not limited thereto.
  • the group I-II-IV-VI semiconductor compound may be, for example, CuZnSnSe, CuZnSnS, or a mixture thereof, but is not limited thereto.
  • the group II-III-V semiconductor compound may include, for example, InZnP, but is not limited thereto.
  • Quantum dots may comprise elemental semiconductors, binary semiconductor compounds, ternary semiconductor compounds, or quaternary semiconductor compounds in substantially uniform concentration or locally varying concentration distributions.
  • the quantum dots may include cadmium (Cd) free quantum dots.
  • Cadmium-free quantum dots are quantum dots that do not include cadmium (Cd).
  • Cadmium (Cd) may cause serious environmental/health problems and is a restricted element under the Restriction of Hazardous Substances (RoHS) in many countries, and thus non-cadmium-based quantum dots may be effectively used.
  • RoHS Hazardous Substances
  • the quantum dot may be a semiconductor compound including zinc (Zn), and at least one of tellurium (Te) and selenium (Se).
  • quantum dots may be Zn-Te semiconductor compounds, Zn-Se semiconductor compounds, and/or Zn-Te-Se semiconductor compounds.
  • the amount of tellurium (Te) in the Zn—Te—Se semiconductor compound may be smaller than that of selenium (Se).
  • the semiconductor compound may have a peak emission wavelength ( ⁇ max) in a wavelength region of less than or equal to about 480 nm, eg, about 430 nm to about 480 nm, and may be configured to emit blue light.
  • the quantum dot may be a semiconductor compound including indium (In), and at least one of zinc (Zn) and phosphorus (P).
  • quantum dots may be In-P semiconductor compounds and/or In-Zn-P semiconductor compounds.
  • the molar ratio of zinc (Zn) to indium (In) may be greater than or equal to about 25.
  • the semiconductor compound may have a peak emission wavelength ( ⁇ max) in a wavelength region of less than about 700 nm, such as about 600 nm to about 650 nm, and may be configured to emit red light.
  • Quantum dots may have a core-shell structure where one quantum dot surrounds another quantum dot.
  • the core and shell of a quantum dot may have an interface, and elements of at least one of the core or shell may have a concentration gradient in the interface, with the concentration of elements of the shell decreasing toward the core.
  • the material composition of the shell of a quantum dot has a higher energy bandgap than the material composition of the core of the quantum dot, and thus the quantum dot may exhibit a quantum confinement effect.
  • Quantum dots can have a quantum dot core and multiple layers of quantum dot shells surrounding the core.
  • the multilayer shell has at least two shells, wherein each shell can be of single composition, alloy, and/or have a concentration gradient.
  • a shell of a multilayer shell farther from the core may have a higher energy bandgap than a shell close to the core, and thus the quantum dot may exhibit a quantum confinement effect.
  • a quantum dot having a core-shell structure may, for example, include: a core including a first semiconductor compound including zinc (Zn), and at least one of tellurium (Te) and selenium (Se); and setting A shell comprising a second semiconducting compound is on at least a portion of the core and has a composition different from that of the core.
  • the first semiconductor compound may be a Zn-Te-Se-based semiconductor compound including zinc (Zn), tellurium (Te), and selenium (Se), for example, a Zn-Se-based semiconductor compound including a small amount of tellurium (Te).
  • Zn zinc
  • Te tellurium
  • Se selenium
  • the molar amount of zinc (Zn) may be higher than that of selenium (Se), and the molar amount of selenium (Se) may be higher than that of tellurium (Te). Molarity.
  • the molar ratio of tellurium (Te) to selenium (Se) may be less than or equal to about 0.05, less than or equal to about 0.049, less than or equal to about 0.048, less than or equal to about 0.047, less than or equal to about 0.045, less than or equal to about 0.044, less than or equal to about 0.043, less than or equal to about 0.042, less than or equal to about 0.041, less than or equal to about 0.04, less than or equal to about 0.039, less than or equal to about 0.035, less than or equal to about 0.03, Less than or equal to about 0.029, Less than or equal to about 0.025, Less than or equal to about 0.024, Less than or equal to about 0.023, Less than or equal to about 0.022, Less than or equal to about 0.021, Less than or equal to about 0.02, Less than or equal to about 0.019, Less than or equal to About 0.0
  • the molar ratio of tellurium (Te) to zinc (Zn) may be less than or equal to about 0.02, less than or equal to about 0.019, less than or equal to about 0.018, less than or equal to about 0.017, less than or equal to about 0.016, about 0.015 or less, about 0.014 or less, about 0.013 or less, about 0.012 or less, about 0.011 or less, or about 0.010 or less.
  • the second semiconductor compound may include, for example, II-VI group semiconductor compounds, III-V group semiconductor compounds, IV-VI group semiconductor compounds, IV group semiconductors, I-III-VI group semiconductor compounds, I-II-IV-VI group semiconductor compounds compound, II-III-V semiconductor compound, or a combination thereof.
  • II-VI group semiconductor compound, III-V group semiconductor compound, IV-VI group semiconductor compound, IV group semiconductor, I-III-VI group semiconductor compound, I-II-IV-VI group semiconductor compound, and II-III- Examples of the group V semiconductor compound are the same as described above.
  • the second semiconductor compound may include zinc (Zn), selenium (Se), and/or sulfur (S).
  • the shell can include ZnSeS, ZnSe, ZnS, or combinations thereof.
  • the shell may include at least one inner shell disposed near the core and an outermost shell disposed at the outermost side of the quantum dot.
  • the inner shell may include ZnSeS, ZnSe, or a combination thereof, and the outermost shell may include ZnS.
  • the shell may have a concentration gradient of one constituent, and for example the amount of sulfur (S) may increase away from the core.
  • a quantum dot having a core-shell structure may include: a core including a third semiconductor compound including indium (In), and at least one of zinc (Zn) and phosphorus (P); A shell of a fourth semiconducting compound having a different composition than the core is over at least a portion of the core and includes.
  • a molar ratio of zinc (Zn) to indium (In) may be greater than or equal to about 25.
  • the molar ratio of zinc (Zn) to indium (In) may be greater than or equal to about 28, greater than or equal to about 29, or greater than or equal to about 30.
  • the molar ratio of zinc (Zn) to indium (In) may be less than or equal to about 55, such as less than or equal to about 50, less than or equal to about 45, less than or equal to About 40 or less, about 35 or less, about 34 or less, about 33 or less, or about 32 or less.
  • the fourth semiconductor compound may include, for example, II-VI group semiconductor compounds, III-V group semiconductor compounds, IV-VI group semiconductor compounds, IV group semiconductors, I-III-VI group semiconductor compounds, I-II-IV-VI group semiconductor compounds compound, II-III-V semiconductor compound, or a combination thereof.
  • II-VI group semiconductor compound, III-V group semiconductor compound, IV-VI group semiconductor compound, IV group semiconductor, I-III-VI group semiconductor compound, I-II-IV-VI group semiconductor compound, and II-III- Examples of the group V semiconductor compound are the same as described above.
  • the fourth semiconductor compound may include zinc (Zn) and sulfur (S) and optionally selenium (Se).
  • the shell can include ZnSeS, ZnSe, ZnS, or combinations thereof.
  • the shell may include at least one inner shell disposed near the core and an outermost shell disposed at the outermost side of the quantum dot. At least one of the inner shell and the outermost shell may include the fourth semiconductor compound ZnS, ZnSe, or ZnSeS.
  • the emissive layer may have a thickness, eg, from about 5 nm to about 200 nm, in the range, eg, from about 10 nm to about 150 nm, eg from about 10 nm to about 100 nm, eg from about 10 nm to about 50 nm.
  • the quantum dots QD contained in the emissive layer EML may be laminated in one or more than one layer, eg two layers. However, embodiments of the inventive concept are not limited thereto, and quantum dots QDs may be laminated into one to ten layers. Quantum dot QDs may be laminated into any suitable number of layers depending on the kind (or type) of quantum dot QDs being used and the desired emission wavelength of light.
  • the quantum dots may have a relatively deep HOMO level, for example, a HOMO level of greater than or equal to about 5.4 eV, within a range such as greater than or equal to about 5.5 eV, such as greater than or equal to about 5.6 eV, such as greater than or equal to About 5.7eV, such as about greater than or equal to about 5.8eV, such as greater than or equal to about 5.9eV, such as greater than or equal to about 6.0eV.
  • a relatively deep HOMO level for example, a HOMO level of greater than or equal to about 5.4 eV, within a range such as greater than or equal to about 5.5 eV, such as greater than or equal to about 5.6 eV, such as greater than or equal to About 5.7eV, such as about greater than or equal to about 5.8eV, such as greater than or equal to about 5.9eV, such as greater than or equal to about 6.0eV.
  • the HOMO energy level of the quantum dot layer 13 may be, for example, from about 5.4 eV to about 7.0 eV, such as from about 5.4 eV to about 6.8 eV, such as from about 5.4 eV to about 6.7 eV, such as from about 5.4 eV to about 6.5 eV, For example about 5.4eV to about 6.3eV, for example about 5.4eV to about 6.2eV, for example about 5.4eV to about 6.1eV, in the range, for example about 5.5eV to about 7.0eV, for example about 5.5eV to about 6.8eV, for example About 5.5eV to about 6.7eV, for example about 5.5eV to about 6.5eV, for example about 5.5eV to about 6.3eV, for example about 5.5eV to about 6.2eV, for example about 5.5eV to about 6.1eV, for example about 5.5eV to about 7.0eV, such as about 5.6eV to
  • Quantum dots can have a relatively shallow LUMO level, for example, less than or equal to about 3.7 eV, in the range of, for example, less than or equal to about 3.6 eV, such as less than or equal to about 3.5 eV, such as less than or equal to about 3.4 eV, such as less than Or equal to about 3.3eV, such as less than or equal to about 3.2eV, such as less than or equal to about 3.0eV.
  • LUMO level for example, less than or equal to about 3.7 eV, in the range of, for example, less than or equal to about 3.6 eV, such as less than or equal to about 3.5 eV, such as less than or equal to about 3.4 eV, such as less than Or equal to about 3.3eV, such as less than or equal to about 3.2eV, such as less than or equal to about 3.0eV.
  • the LUMO level of the quantum dot layer 13 may be from about 2.5eV to about 3.7eV, from about 2.5eV to about 3.6eV, from about 2.5eV to about 3.5eV, from about 2.5eV to about 3.4eV, from about 2.5eV to About 3.3eV, about 2.5eV to about 3.2eV, about 2.5eV to about 3.1eV, about 2.5eV to about 3.0eV, about 2.8eV to about 3.7eV, about 2.8eV to about 3.6eV, about 2.8eV to about 3.5 eV, about 2.8eV to about 3.4eV, about 2.8eV to about 3.3eV, about 2.8eV to about 3.2eV, about 3.0eV to about 3.7eV, about 3.0eV to about 3.6eV, about 3.0eV to about 3.5eV, Or about 3.0eV to about 3.4eV.
  • the quantum dots may have an energy bandgap of about 1.7 eV to about 2.3 eV, or about 2.4 eV to about 2.9 eV.
  • the quantum dot layer 13 can have the following energy band gap: about 1.8eV to about 2.2eV or about 2.4eV to about 2.8eV, in the range, for example, about 1.9eV to about 2.1eV, for example about 2.4 eV to about 2.7eV.
  • the first electrode 14 may be an anode, and in this case, the second electrode 17 is a cathode. In other embodiments, the first electrode 14 may be a cathode, and in this case, the second electrode 17 is an anode.
  • the light-emitting principle of the light-emitting device 13 is: through the circuit connected by the anode and the cathode, the anode is used to inject holes into the light-emitting functional layer 133, and the cathode injects electrons into the light-emitting functional layer 133, and the formed electrons and holes are formed in the light-emitting pattern 133a.
  • Excitons, excitons return to the ground state by radiative transitions, emitting photons.
  • the anode can include a conductor with a high work function such as a metal, a conductive metal oxide, or a combination thereof.
  • the metal can be nickel, platinum, vanadium, chromium, copper, zinc, or gold, or their alloys;
  • the conductive metal oxide can be zinc oxide, indium oxide, tin oxide, indium tin oxide (ITO), indium zinc oxide (IZO) , or fluorine-doped tin oxide; or, the combination of metal and conductive metal oxide can be ZnO and Al, or SnO2 and Sb, ITO/Ag/ITO, but not limited thereto.
  • the cathode may include a conductor such as a metal, a conductive metal oxide, and/or a conductive polymer that has a lower work function than the anode.
  • the cathode may comprise, for example, metals such as aluminum, magnesium, calcium, sodium, potassium, titanium, indium, yttrium, lithium, gadolinium, silver, tin, lead, cesium, barium, etc., or alloys thereof; multilayer structures such as LiF/ Al, Li2O/Al, Liq/Al, LiF/Ca, and BaF2/Ca; conductive metal oxides can be zinc oxide, indium oxide, tin oxide, indium tin oxide (Indium Tin Oxides, ITO), indium zinc oxide (Indium Zinc Oxides, IZO), or fluorine-doped tin oxide, but not limited thereto.
  • the work function of the anode can be higher than that of the cathode, for example, the work function of the anode can be, for example, from about 4.5 eV to about 5.0 eV and the work function of the cathode can be from about 4.0 eV to about 4.7 eV.
  • the work function of the anode may be, for example, from about 4.6 eV to about 4.9 eV, or from about 4.6 eV to about 4.8 eV
  • the work function of the cathode may be, for example, from about 4.0 eV to about 4.6 eV or from about 4.3 eV to about 4.6 eV. eV.
  • the first electrode 14 and the second electrode 17 can be transmissive electrodes, partially transmissive and partially reflective electrodes or reflective electrodes, and the transmissive electrodes or partially transmissive and partially reflective electrodes can include: conductive oxides such as zinc oxide, indium oxide, tin oxide, oxide Indium tin (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide, or a thin layer of metal.
  • the reflective electrode can include: reflective metal, for example: an opaque conductor such as aluminum (Al), silver (Ag), or gold (Au), the first electrode 14 and the second electrode 17 can be a single-layer or multi-layer structure;
  • At least one of the first electrode 14 or the second electrode 17 may be connected to an auxiliary electrode (not shown). If connected to the auxiliary electrode, the resistance of the second electrode 17 can be reduced.
  • the above-mentioned display substrate 1 may be a top emission light emitting substrate or a bottom emission light emitting substrate.
  • the second electrode 17 may be a transmissive electrode, and the first electrode 14 may be a reflective electrode.
  • the first electrode 14 is a transmissive electrode, and the second electrode 17 is a reflective electrode.
  • the display substrate can also be a double-sided emission type light-emitting substrate, and in this case, both the first electrode 14 and the second electrode 17 are transmissive electrodes.
  • the above-mentioned light emitting device 13 may be a "upright” light emitting device or an "inverted” light emitting device.
  • the first electrode 14 is an anode
  • the second electrode 17 is a cathode
  • the first electrode 14 is a cathode and the second electrode 17 is an anode.
  • each light emitting element EL may be the same or different, which is not limited in the present disclosure.
  • an isolation dam 18 is arranged between the first pixel defining layer 15 and the first electrode 14 layer; the isolation dam 18 is arranged between adjacent pixel openings, and the isolation dam 18 is used for depositing Support the mask plate and avoid the problem of color mixing in the process of emitting patterns.
  • FIG. 5 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes a plurality of pixel units located on the base substrate 1, and the pixel unit It includes a light emitting element EL and a pixel driving circuit for driving the light emitting element EL;
  • the pixel driving circuit includes: a driving transistor T1 configured to output a corresponding driving current to the corresponding light emitting element EL according to its own gate-source power supply.
  • the driving transistor T1 is located in the first transistor layer, and the channel region and source-drain doped regions of the driving transistor T1 are located in the first active layer 2 .
  • the electrical characteristics of the driving transistor T1 directly affect the accuracy of the driving current output by the pixel driving circuit, so the quality requirements for the driving transistor T1 are relatively high. Considering that the stability of the manufacturing process of the first transistor layer in the actual display substrate manufacturing process is significantly higher than that of the second transistor layer, it is preferable to design the driving transistor T1 in the first transistor layer in the embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a distribution structure of transistors in the pixel driving circuit shown in FIG. 6 , as shown in FIGS. 5 to 7
  • the pixel driving circuit further includes: a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T6, a second reset transistor T7, a first light emission control transistor T4, a second light emission control transistor T5 and a capacitor C.
  • first pole and second pole of a transistor one of them is the source of the transistor, and the other is the drain of the transistor.
  • the source and drain of a transistor can be interchanged.
  • An exemplary description is given below by taking the first pole s as a source and the second pole d as a drain as an example.
  • the gate of the data writing transistor T2 is electrically connected to the corresponding gate line Gate
  • the first pole s of the data writing transistor T2 is electrically connected to the corresponding data line Data
  • the second pole d of the data writing transistor T2 is connected to the driving
  • the first pole s of the transistor T1 is electrically connected.
  • the gate of the threshold compensation transistor T3 is electrically connected to the corresponding gate line Gate, the first pole s of the threshold compensation transistor T3 is electrically connected to the second pole d of the driving transistor T1, and the second pole d of the threshold compensation transistor T3 is connected to the driving transistor T1.
  • the grid is electrically connected.
  • the gate of the first reset transistor T6 is electrically connected to the corresponding reset control signal line Rst, the first pole s of the first reset transistor T6 is electrically connected to the reset voltage transmission line VINIT, and the second pole d of the first reset transistor T6 is connected to the driving transistor.
  • the gate of T1 is electrically connected.
  • the gate of the second reset transistor T7 is electrically connected to the corresponding reset control signal line Rst or gate line Gate, the first pole s of the second reset transistor T7 is electrically connected to the reset voltage transmission line VINIT, and the second pole s of the second reset transistor T7 d is electrically connected to the first electrode 14 of the light emitting element EL.
  • the gate of the first light emission control transistor T4 is electrically connected to the light emission control signal line EM, the first pole s of the first light emission control transistor T4 is electrically connected to the working voltage transmission line VDD, and the second pole d of the first light emission control transistor T4 is connected to the driving The first pole s of the transistor T1 is electrically connected.
  • the gate of the second light emission control transistor T5 is electrically connected to the light emission control signal line EM, the first pole s of the second light emission control transistor T5 is connected to the second pole d of the drive transistor T1, and the second pole of the second light emission control transistor T5 d is electrically connected to the first electrode 14 of the light emitting element EL.
  • the first end plate c1 of the capacitor C is connected to the gate of the driving transistor T1, and the second end plate c2 of the capacitor C is connected to the working voltage transmission line VDD.
  • the pixel driving circuit shown in FIG. 6 adopts the case of 7T1C (that is, 7 transistors T1-T7 and 1 capacitor C), which is only used as an example and does not limit the technical solution of the present disclosure.
  • the technical solutions of the present disclosure are applicable to pixel driving circuits with any structure.
  • the data writing transistor T2 is located in the first transistor layer, and the channel region and source-drain doped regions of the data writing transistor T2 are located in the first active layer 2 .
  • the threshold compensation transistor T3 is located in the first transistor layer, and the channel region and source-drain doped regions of the threshold compensation transistor T3 are located in the first active layer 2 .
  • the first reset transistor T6 is located in the first transistor layer, and the channel region and the source-drain doped region of the first reset transistor T6 are located in the first active layer 2 .
  • the second reset transistor T7 is located in the second transistor layer, and the channel region and the source-drain doped region of the second reset transistor T7 are located in the second active layer 3 .
  • the first light emission control transistor T4 is located in the second transistor layer, and the channel region and source and drain doped regions of the first light emission control transistor T4 are located in the second active layer 3 .
  • the second light emission control transistor T5 is located in the second transistor layer, and the channel region and source and drain doped regions of the second light emission control transistor T5 are located in the second active layer 3 .
  • the second reset transistor T7 and the second light emission control transistor T5 are both electrically connected to the first electrode 14 of the light emitting element EL
  • the second reset transistor T7 and the second light emission control transistor T5 are arranged on the second transistor layer closer to the first electrode 14 layer, so as to reduce the second electrode d of the second reset transistor T7 and the second pole d of the second light emission control transistor T5 as much as possible.
  • the distance between the electrode d and the first electrode 14 of the light emitting element EL is beneficial to wiring design.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are controlled by the same light emission control signal line EM, for the convenience of wiring, the first light emission control transistor T4 is also disposed on the second transistor layer.
  • the number of transistors arranged in the first transistor layer and the second transistor layer is closer, it is more beneficial to increase the overlapping area of the first active layer 2 and the second active layer 3, and it is more beneficial to the pixel driving circuit.
  • the area occupied by the plane parallel to the base substrate 1 is reduced, so the three transistors of the first light emission control transistor T4, the second light emission control transistor T5 and the second reset transistor T7 in the pixel driving circuit are arranged at the second
  • three transistors, namely the data writing transistor T2, the threshold compensation transistor T3, and the first reset transistor T6, are provided in the first transistor layer.
  • the 4 transistors in the pixel driving circuit are set on the first transistor layer, and the other 3 transistors in the pixel driving circuit are set on the second transistor layer, so that the number of transistors set in the first transistor layer and the second transistor layer is close to .
  • At least one of the data writing transistor T2, the threshold compensation transistor T3 and the first reset transistor T6 can also be set in the second transistor layer according to actual needs, and the second reset transistor T7, the first light emitting transistor At least one of the control transistor T4 and the second light emission control transistor T5 is disposed on the first transistor layer, and these situations should also belong to the protection scope of the present disclosure.
  • the first transistor layer includes at least one transistor in the pixel driving circuit
  • the second transistor layer includes at least one transistor in the pixel driving circuit
  • the gate line Gate, the light emission control signal line EM and the reset control signal line Rst can be selectively arranged on the first conductive layer 6 or the third conductive layer 10 respectively, and the reset voltage transmission line VINIT can be arranged on the second conductive layer.
  • the conductive layer 8 and the working voltage transmission line VDD can be disposed on the fourth conductive layer 12 .
  • first pole s of the second light emission control transistor T5 is connected to the second pole d of the driving transistor T1 through the part (that is, the connection part) Q1 located in the first via hole 401
  • the second The first pole s of the reset transistor T7 is connected to the first pole s of the first reset transistor T6 through a part (ie, the connecting portion) Q2 located in the first via hole 401 .
  • the following conductive connection structure P is provided in the fourth conductive layer 12:
  • the conductive connection structure provided for the drive transistor T1 includes: a conductive connection structure P5 (not shown in FIG. 5 ) connected to the gate of the drive transistor T1 through a via hole, and connected to the first pole s of the drive transistor T1 through a via hole
  • the conductive connection structure P4 is connected to the conductive connection structure P6 of the second pole d of the driving transistor T1 through a via hole,
  • the conductive connection structure provided for the data write transistor T2 includes: a conductive connection structure P2 connected to the first pole s of the data write transistor T2 through a via hole.
  • the conductive connection structure provided for the threshold compensation transistor T3 includes: a conductive connection structure P7 connected to the first pole s of the threshold compensation transistor T3 through a via hole, and a conductive connection structure P7 connected to the second pole d of the threshold compensation transistor T3 through a via hole Structure P8.
  • the conductive connection structure provided for the first light emission control transistor T4 includes: a conductive connection structure P1 connected to the first pole s of the first light emission control transistor T4 through a via hole, and a second pole s connected to the first light emission control transistor T4 through a via hole.
  • the conductive connection structure P3 of the diode d includes: a conductive connection structure P1 connected to the first pole s of the first light emission control transistor T4 through a via hole, and a second pole s connected to the first light emission control transistor T4 through a via hole.
  • the conductive connection structure provided for the second light emission control transistor T5 includes: a conductive connection structure P10 connected to the second pole d of the second light emission control transistor T5 through a via hole.
  • the conductive connection structure provided for the first reset transistor T6 includes: a conductive connection structure P9 connected to the second pole d of the second light emission control transistor T5 through a via hole.
  • the conductive connection structure provided for the first reset transistor T6 includes: a conductive connection structure P11 connected to the second pole d of the second light emission control transistor T5 through a via hole.
  • the conductive connection structure P3 is connected to the conductive connection structure P4, the conductive connection structure P5, the conductive connection structure P8 are connected to the conductive connection structure P9, the conductive connection structure P5 is connected to the conductive connection structure P6, and the conductive connection structure P10 is connected to the conductive connection structure P11 , the conductive connection structure P11 is connected to the first electrode 14 of the light emitting element EL.
  • the situation that the above-mentioned fourth conductive layer 12 includes the conductive connection structures P1 - P11 is only an optional implementation in the present disclosure, and this solution is only used as an example, and it will not limit the technical solution of the present disclosure.
  • FIG. 8 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes: an encapsulation layer 30 and a color-resist layer 19 .
  • the encapsulation layer 30 is located on the side of the second electrode 17 away from the base substrate 1, and the encapsulation layer 30 can play a role in encapsulating the light-emitting element; the encapsulation layer 30 can be a single-layer structure or an organic encapsulation layer and an inorganic encapsulation layer. A multilayer structure formed by alternately stacking layers.
  • the color-resist layer 19 is located on the side of the encapsulation layer 30 away from the substrate 1 , and the color-resist layer 19 includes a plurality of color-resist patterns 1901r, 1901g, 1901b corresponding to the electroluminescent patterns 16 one-to-one.
  • the color resist layer 19 may further include a black matrix 1902 .
  • the light-emitting element EL is a white OLED capable of emitting white light
  • the plurality of color-resist patterns include a red color-resist pattern 1901r, a green color-resist pattern 1901g, and a blue color-resist pattern 1901b.
  • the color resistance pattern 1901r is red
  • the green color resistance pattern 1901g is green
  • the blue color resistance pattern 1901b is blue.
  • the display substrate can be used for color display.
  • the plurality of light emitting elements include red QLEDs capable of emitting red light, green QLEDs emitting green light, and blue QLEDs emitting blue light
  • the plurality of color-resisting patterns include red color-resisting patterns corresponding to the red QLEDs 1901r, the green color resistance pattern 1901g corresponding to the green QLED, and the blue color resistance pattern 1901b corresponding to the blue QLED.
  • the setting of each color resistance pattern 1901r, 1901g, and 1901b can improve the light purity of the pixel unit, which is conducive to improving The display color gamut of the product.
  • FIG. 9 is another schematic cross-sectional view of a part of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes: a light conversion layer, the light conversion layer is located between the encapsulation layer 30 and the color resistance layer 19, and the light conversion layer includes a plurality of light conversion color filters 31r corresponding to at least part of the electroluminescence pattern 16, 31g, wherein the light conversion color filters 31r and 31g can generate light of other colors under the excitation of the light emitted by the light emitting element.
  • the material of the light conversion color filters 31r, 31g includes quantum dot material.
  • the structure located between the first electrode 14 and the base substrate 1 in the embodiment of the present disclosure is referred to as the driving function layer 32 structure.
  • the driving function layer 32 structure located between the base substrates 1 .
  • the display substrate further includes a second pixel defining layer 20, and a second pixel receiving hole is provided on the second pixel defining layer 20, and the second pixel receiving hole corresponds to the first pixel receiving hole one by one, and the light conversion color
  • the membrane is located in the corresponding second pixel receiving hole.
  • a reflective metal layer (not shown) may be provided on the side walls surrounding the second receiving hole to increase the amount of light emitted.
  • all light emitting elements EL are OLEDs capable of emitting blue light;
  • the light conversion color filter includes a red light conversion color filter 31r capable of converting blue light into red light and a green light conversion color filter capable of converting blue light into green light 31g; wherein, the material of the red light conversion color filter 31r includes a red light quantum dot material, and the material of the green light conversion color filter 31g includes a green light quantum dot material.
  • the display substrate is also provided with a transparent pattern 31b (generally made of transparent resin material), the transparent pattern 31b is also located in the corresponding second pixel receiving hole, and the transparent pattern 31b can transmit blue light through.
  • the color resist layer 19 includes a red color resist pattern 1901r corresponding to the red light conversion color film 31r, a green color resist pattern 1901g corresponding to the green light conversion color film 31g, and a blue color resist pattern 1901b corresponding to the transparent pattern 31b.
  • the above-mentioned structure formed by combining quantum dot material and OLED is a QD-OLED structure.
  • an embodiment of the present disclosure also provides a method for preparing a display substrate, which can be used to prepare the display substrate provided in the previous embodiment.
  • a method for preparing a display substrate which can be used to prepare the display substrate provided in the previous embodiment.
  • the structure of the display substrate please refer to the previous embodiment. content, which will not be repeated here.
  • FIG. 10 is a flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 10 , the method for preparing a display substrate includes:
  • Step S101 forming a first transistor layer on one side of the base substrate.
  • the first transistor layer includes a first active layer
  • the material of the first active layer includes a low-temperature polysilicon material
  • the first active layer includes at least one first channel region and at least one first source-drain doped region.
  • Step S102 forming a second transistor layer on a side of the first transistor layer away from the base substrate.
  • the first transistor layer includes a second active layer, at least one insulating layer is arranged between the first active layer and the second active layer, the material of the second active layer includes a low-temperature polysilicon material, and the second active layer
  • the layer includes at least one second channel region and at least one second source-drain doping region, wherein the orthographic projection of the at least one second source-drain doping region on the substrate is the same as that of the at least one first source-drain doping region on the substrate
  • the orthographic projections on the base substrate overlap, and at least one second source-drain doping region is connected to the corresponding first source-drain doping region through a connection portion filled in the first via hole on the insulating layer.
  • the stacking design of the two transistor layer structures and the overlapping of the active layers in the two transistor layer structures that is, the transistors in the pixel driving circuit can be distributed in the two transistor layer structures as required, and The source and drain doped regions of at least two transistors in the pixel driving circuit overlap in the direction perpendicular to the substrate, and this design can reduce the occupied area of the pixel driving circuit on a plane parallel to the substrate .
  • FIG. 11 is another flow chart of a method for preparing a display substrate provided by an embodiment of the present disclosure.
  • FIGS. 12A to 12N are schematic cross-sectional views of an intermediate product of a display substrate prepared by the method shown in FIG. 11 , as shown in FIGS. 11 to 12N , this preparation method can be used to prepare the display substrate shown in Figure 4, the preparation method includes:
  • Step S201 forming a first buffer layer on one side of the base substrate.
  • the material of the first buffer layer 21 may include at least one of silicon oxide and silicon nitride.
  • Step S202 forming a first polysilicon material film on the side of the first buffer layer away from the base substrate, and patterning the first polysilicon material film to obtain a first polysilicon pattern.
  • step S202 firstly, a thin film of amorphous silicon material is formed on the side of the first buffer layer 21 away from the base substrate 1, with a thickness of Then dehydrogenation treatment and ELA laser crystallization treatment are performed on the amorphous silicon material film in sequence, so that the amorphous silicon material film is transformed into a polysilicon material film; then the polysilicon material film is patterned by a patterning process to obtain the first polysilicon material film. Crystal silicon pattern 2a.
  • Step S203 forming a first gate insulating layer on a side of the first polysilicon pattern away from the substrate.
  • Step S204 forming a first conductive layer on a side of the first gate insulating layer away from the base substrate.
  • the first conductive layer 6 includes the gate g of each transistor located in the first transistor layer; of course, the first conductive layer 6 may also include other conductive structures, such as the first end plate c1 of the capacitor C, Gate lines (not shown), light emission control signal lines (not shown), reset control signal lines (not shown) and the like.
  • the material of the first conductive layer 6 can be conductive materials such as metal materials (such as molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, etc.), metal alloys, etc., which can be selected according to actual requirements.
  • Step S205 using the first conductive layer as a mask for doping, performing ion implantation on the first polysilicon pattern.
  • the part of the first polysilicon pattern 2a not covered by the first conductive layer 6 is conductorized as the first source-drain doped region 202, and the first polysilicon pattern 2a is covered by the first The part covered by the conductive layer 6 is used as the first channel region 201 , so as to obtain the first active layer 2 .
  • the first polysilicon pattern 2a is ion-implanted using the first conductive layer 6 as a mask for doping, so there is no need to prepare an additional mask for doping, which can effectively shorten the production cycle and reduce production costs. cost.
  • Step S206 forming a second gate insulating layer on the side of the first conductive layer away from the base substrate.
  • Step S207 forming a second conductive layer on a side of the second gate insulating layer away from the base substrate.
  • the second conductive layer 8 may include a second end plate c2 of the capacitor C, a shielding electrode pattern 801 , a reset voltage transmission line (not shown) and the like.
  • the material of the second conductive layer 8 can be conductive materials such as metal material, metal alloy.
  • Step S208 forming a second buffer layer on the side of the second conductive layer away from the base substrate.
  • a second buffer material film is formed on the side of the second conductive layer 8 away from the base substrate 1, and then the second buffer material film, the second gate insulating layer 7, and the first gate insulating layer 7 are patterned by a patterning process.
  • the insulating layer 5 is patterned to form the required first via hole 401 .
  • the material of the second buffer layer 22 may include at least one of silicon oxide, silicon nitride, and aluminum oxide.
  • the thickness of the second buffer layer 22 is: In the embodiment of the present disclosure, the arrangement of the second buffer layer 22 can effectively improve the crystallization effect in the subsequent preparation of the second active layer.
  • Step S209 forming a second polysilicon material film on the side of the second buffer layer away from the base substrate, and patterning the second polysilicon material film to obtain a second polysilicon pattern.
  • step S202 an amorphous silicon material film is first formed on the side of the second buffer layer 22 away from the base substrate 1; then the amorphous silicon material film is sequentially subjected to dehydrogenation treatment and ELA laser crystallization treatment, so that the amorphous silicon material film is converted into a polysilicon material film; then the polysilicon material film is patterned by a patterning process to obtain a second polysilicon pattern 3a, and the second polysilicon pattern 3a fills the first via hole 401.
  • Step S210 forming a third gate insulating layer on the side of the second polysilicon pattern away from the substrate.
  • Step S211 forming a third conductive layer on a side of the third gate far away from the substrate.
  • the third conductive layer 10 includes the gate g of each transistor located in the second transistor layer; of course, the third conductive layer 10 may also include other conductive structures, such as gate lines (not shown), light emitting control signal lines (not shown), reset control signal lines (not shown), and the like.
  • the material of the third conductive layer 10 may be conductive materials such as metal materials and metal alloys.
  • Step S212 using the third conductive layer as a mask for doping, performing ion implantation on the second polysilicon pattern.
  • the part of the second polysilicon pattern 3a not covered by the third conductive layer 10 is conductorized as the second source-drain doped region 302 and the connecting portion 302a, and the second polysilicon pattern The part of 3a covered by the third conductive layer 10 is used as the second channel region 301, so as to obtain the first active layer 2.
  • the second polysilicon pattern 3a is ion-implanted using the third conductive layer 10 as a mask for doping, so there is no need to prepare an additional mask for doping, which can effectively shorten the production cycle and reduce production costs. cost.
  • the implantation process performs ion implantation treatment, so that the part of the second polysilicon pattern 3a located in the first via hole is conductorized to form a connection part 302a, which has at least 2 centers of doping concentration.
  • the ion implantation depth can be adjusted by changing the ion beam energy of ion implantation; generally, without considering other factors, the higher the ion beam energy, the deeper the ion implantation depth, and the formed doping The center of concentration is also deeper.
  • the ion beam energy of ion implantation is 5KeV ⁇ 90KeV, such as 5KeV, 15KeV, 25KeV, 35KeV, 45KeV, 55KeV, 65KeV, 75KeV, 85KeV, 90KeV;
  • the ion beam dose of ion implantation It is 1017/cm2 ⁇ 1022/cm2, such as 1017/cm2, 1018/cm2, 1019/cm2, 1020/cm2, 1021/cm2, 1022/cm2.
  • Step S213 forming an interlayer dielectric layer on the side of the third conductive layer away from the base substrate.
  • first form an interlayer dielectric material film and then pattern the interlayer dielectric material film to form a structure that can be connected to the corresponding structure (such as the gate of some transistors, source and drain doped regions) at the designed position. etc.), and obtain the pattern of the interlayer dielectric layer 11.
  • Step S214 forming a fourth conductive layer on the side of the interlayer dielectric layer away from the base substrate.
  • the fourth conductive layer 12 includes a data line (not shown) and a conductive connection structure P. As shown in FIG. Of course, the fourth conductive layer 12 may also include other conductive structures, such as working voltage transmission lines (not shown).
  • the material of the fourth conductive layer 12 can be a conductive material such as a metal material, a metal alloy, etc., which can be selected according to actual requirements
  • Step S215 forming a planarization layer on the side of the fourth conductive layer away from the base substrate.
  • planarization material film is formed, and then the planarization material film is patterned through a patterning process to obtain a planarization layer 13 .
  • the material of the planarization layer 13 may be an organic resin material with a thickness of 1 ⁇ m ⁇ 3 ⁇ m.
  • Step S216 forming a first electrode layer on the planarization layer away from the base substrate.
  • the first electrode layer includes a first electrode 14 .
  • the material of the first electrode layer can be a conductive material such as a metal material, a metal alloy, etc., which can be selected according to actual requirements.
  • Step S217 forming a first pixel defining layer and an isolation dam on the side of the first electrode layer away from the base substrate.
  • a first pixel receiving hole is formed on the first pixel defining layer 15 .
  • the material of the first pixel defining layer 15 may be an organic resin material with a thickness of 1 ⁇ m ⁇ 3 ⁇ m.
  • Isolation dams 18 are disposed between adjacent pixel openings, and the isolation dams 18 are used to support the mask during the process of depositing light-emitting patterns into the pixel openings and avoid color mixing problems.
  • the luminous pattern is located in the corresponding first pixel accommodation hole; wherein, the material of the electroluminescent pattern 16 can be an organic luminescent material or a quantum dot material.
  • Step S219 forming a second electrode layer on the side of the electroluminescent pattern away from the base substrate.
  • the second electrode layer includes a second electrode 17 , and the second electrode 17 is a planar electrode.
  • the material of the second electrode 17 may be a transparent conductive material, such as indium tin oxide, indium gallium zinc oxide, and the like.
  • FIG. 13 is another flow chart of a method for preparing a display substrate provided by an embodiment of the present disclosure.
  • FIGS. 14A to 14B are schematic cross-sectional views of ion implantation using a patterned photoresist layer, as shown in FIG. 13 .
  • the flow chart provided in FIG. 13 includes steps S201 to S209 in FIG. 12 , added steps S209 a , added steps S209 b , steps S210 , S211 , and steps S213 to S219 in FIG. 12 .
  • steps S201-S209, step S210, step S211, step S213-step S219 please refer to the previous description of the flow chart shown in Figure 12, and will not repeat them here. Only the newly added step S209a and the newly added step S209b will be described in detail below.
  • Step S209a forming a patterned photoresist layer on the side of the second polysilicon pattern away from the second polysilicon pattern.
  • the photoresist used in the photoresist layer in the embodiment of the present disclosure may be a positive photoresist or a negative photoresist, which is not limited in the present disclosure.
  • Step S209b using the patterned photoresist layer as a mask for doping, performing ion implantation on the second polysilicon pattern 3a.
  • the part of the second polysilicon pattern 3a that is not covered by the patterned photoresist layer is conductorized as the second source-drain doped region 302 and the connection Not 302a, the part of the second polysilicon pattern 3a covered by the patterned photoresist layer is used as the second channel region 301 to obtain the second active layer 3 .
  • the patterned photoresist layer 40 is stripped by a stripping process.
  • the portion of the second polysilicon pattern 3a located in the via hole has a relatively thick thickness
  • multiple ionization can be used.
  • the implantation process performs ion implantation treatment, so that the part of the second polysilicon pattern 3a located in the first via hole 401 is conductorized and the connection part 302a formed after it is formed has at least 2 centers of doping concentration.
  • the first conductive layer 6 when preparing the first active layer 2, may not be used as a mask for doping to perform ion implantation, but the method as described in step S209a and step S209b may be used.
  • the illustrated patterned photoresist layer is used as a mask for doping to perform ion implantation.
  • an embodiment of the present disclosure further provides a display device, which includes the display substrate in any one of the above embodiments.
  • the display device provided in this embodiment can be any product or component with a display function such as a flexible wearable device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be regarded as limitations on the present invention.
  • the display device may also include various types of display devices, such as liquid crystal display devices, organic electroluminescent display devices (such as OLED display devices, QLED display devices, and QD-OLED display devices), which are not limited here.
  • display devices such as liquid crystal display devices, organic electroluminescent display devices (such as OLED display devices, QLED display devices, and QD-OLED display devices), which are not limited here.

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Abstract

本公开实施例提供了一种显示基板，包括：衬底基板和沿远离衬底基板的方向依次设置的第一晶体管层和第二晶体管层，第一晶体管层包括第一有源层，第二晶体管层包括第二有源层，第一有源层与第二有源层之间设置有至少一层绝缘层；第一有源层和第二有源层的材料均包括低温多晶硅材料，第一有源层包括第一沟道区和第一源漏掺杂区，第二有源层包括第二沟道区和第二源漏掺杂区，至少一个第二源漏掺杂区在衬底基板上的正投影与至少一个第一源漏掺杂区在衬底基板上的正投影存在交叠，至少一个第二源漏掺杂区通过填充于绝缘层上第一过孔内的连接部与对应的第一源漏掺杂区相连。本公开实施例还提供了一种显示基板的制备方法和显示装置。

Description

显示基板及其制备方法和显示装置 技术领域
本公开涉及显示领域，特别涉及一种显示基板及其制备方法和显示装置。
背景技术
随着显示技术的不断发展，显示产品的分辨率不断提升。目前，显示基板一般包括有呈阵列排布的多个像素单元，像素单元包括像素驱动电路和发光元件，像素驱动电路包括多个晶体管且这些晶体管位于同一层结构中。受限于晶体管制备工艺，单个晶体管在平行于衬底基板的平面上所占用面积难以进一步减小，这会使得像素驱动电路在平行于衬底基板的平面上所占用面积难以进一步减小，显示装置的分辨率难以进一步提升。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提出了一种显示基板及其制备方法和显示装置。
第一方面，本公开实施例提供了一种显示基板，包括：衬底基板和沿远离衬底基板的方向依次设置的第一晶体管层和第二晶体管层，所述第一晶体管层包括第一有源层，所述第二晶体管层包括第二有源层，所述第一有源层与所述第二有源层之间设置有至少一层绝缘层；
所述第一有源层和所述第二有源层的材料均包括低温多晶硅材料，所述第一有源层包括至少一个第一沟道区和至少一个第一源漏掺杂区，所述第二有源层包括至少一个第二沟道区和至少一个第二源漏掺杂区，至少一个所述第二源漏掺杂区在所述衬底基板上的正投影与至少一个所述第一源漏掺杂区在所述衬底基板上的正投影存在交叠；
至少一个所述第二源漏掺杂区通过填充于所述绝缘层上第一过孔 内的连接部与对应的所述第一源漏掺杂区相连。
在一些实施例中，所述连接部的材料包括至少两种不同结晶度的硅和导体化用掺杂离子。
在一些实施例中，所述至少两种不同结晶度的硅包括：非晶硅和多晶硅。
在一些实施例中，所述连接部在沿垂直于所述衬底基板的方向上具有至少2个掺杂浓度中心。
在一些实施例中，所述第一过孔的坡度角为30°～75°。
在一些实施例中，至少一个所述第一沟道区在所述衬底基板上的正投影与至少一个所述第二沟道区在所述衬底基板上的正投影存在交叠。
在一些实施例中，所述第一有源层和所述第二有源层之间设置有屏蔽电极图形；
所述屏蔽电极图形在所述衬底基板上的正投影，覆盖所述第一沟道区和所述第二沟道区二者在所述衬底基板上正投影相交叠的区域。
在一些实施例中，所述第一晶体管层还包括：
第一栅绝缘层，位于所述第一有源层远离所述衬底基板的一侧；
第一导电层，位于所述第一栅绝缘层远离所述衬底基板的一侧，所述第一导电层包括位于所述第一晶体管层的各晶体管与所述第一沟道区相对应的栅极。
在一些实施例中，所述第一导电层还包括：电容的第一端板；
所述第一晶体管层还包括：
第二栅绝缘层，位于所述第一导电层远离所述衬底基板的一侧
第二导电层，位于所述第二栅绝缘层远离所述衬底基板的一侧，所述第二导电层包括与所述电容的第一端板相对设置的第二端板。
在一些实施例中，在所述第一有源层和所述第二有源层之间设置有屏蔽电极图形时，所述屏蔽电极图形位于所述第二导电层。
在一些实施例中，所述第二晶体管层还包括：
第二缓冲层，位于所述第二有源层靠近所述衬底基板的一侧且与所述第二有源层相接触。
在一些实施例中，所述第二缓冲层的厚度为：
Figure PCTCN2022074526-appb-000001
在一些实施例中，所述第二晶体管层还包括：
第三栅绝缘层，位于所述第二有源层远离所述衬底基板的一侧；
第三导电层，位于所述第三绝缘层远离所述衬底基板的一侧，所述第三导电层包括位于所述第二晶体管层的各晶体管与所述第二沟道区相对应的栅极。
在一些实施例中，所述显示基板还包括：
层间介质层，位于所述第二晶体管层远离所述衬底基板的一侧；
第四导电层，位于所述层间介质层远离所述衬底基板的一侧，所述第四导电层包括：数据线和导电连接结构，所述导电连接结构通过过孔连接至所述第一源漏掺杂区或所述第二源漏掺杂区。
在一些实施例中，所述显示基板还包括：
平坦化层，位于所述第四导电层远离所述衬底基板的一侧；
第一电极层，位于所述平坦化层远离所述衬底基板的一侧，所述第一电极层包括多个第一电极，所述第一电极通过过孔连接至对应的所述导电连接结构以与对应的所述第一源漏掺杂区或所述第二源漏掺杂区电连接；
第一像素界定层，位于所述第一电极层远离所述衬底基板的一侧，所述第一像素界定层上形成有多个第一像素容纳孔，所述第一像素容纳孔连通至对应的所述第一电极；
发光层，包括多个电致发光图形，所述电致发光图形位于对应的所述第一像素容纳孔内；
第二电极层，位于所述第一像素界定层远离所述衬底基板的一侧。
在一些实施例中，所述电致发光图形的材料包括：有机发光材料 或量子点材料。
在一些实施例中，所述显示基板还包括：
封装层，位于所述第二电极层远离所述衬底基板的一侧；
色阻层，位于所述封装层远离所述衬底基板的一侧，所述色阻层包括与所述电致发光图形一一对应的多个色阻图形。
在一些实施例中，所述电致发光图形的材料包括有机发光材料，所述显示基板还包括：
所述光转换层，位于所述封装层和所述色阻层之间，所述光转换层包括与至少部分所述电致发光图形一一对应的多个光转换彩膜；
所述光转换彩膜的材料包括量子点材料。
在一些实施例中，所述显示基板包括位于所述衬底基板上的多个像素单元，所述像素单元包括发光元件和用于驱动所述发光元件的像素驱动电路；
所述像素驱动电路包括：驱动晶体管，所述驱动晶体管配置为根据自身的栅源电源向对应的所述发光元件输出相应的驱动电流。
在一些实施例中，所述驱动晶体管位于所述第一晶体管层，所述驱动晶体管的沟道区和源漏掺杂区位于所述第一有源层。
在一些实施例中，所述像素驱动电路还包括：数据写入晶体管、阈值补偿晶体管、第一复位晶体管、第二复位晶体管、第一发光控制晶体管、第二发光控制晶体管和电容；
所述数据写入晶体管的栅极与对应的栅线电连接，所述数据写入晶体管的第一极与对应的数据线电连接，所述数据写入晶体管的第二极与驱动晶体管的第一极电连接；
所述阈值补偿晶体管的栅极与对应的栅线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接；
所述第一复位晶体管的栅极与对应的复位控制信号线电连接，所述第一复位晶体管的第一极与复位电压传输线电连接，所述第一复位 晶体管的第二极与驱动晶体管的栅极电连接；
所述第二复位晶体管的栅极与对应的复位控制信号线或栅线电连接，第二复位晶体管的第一极与复位电压传输线电连接，第二复位晶体管的第二极与所述发光元件的第一电极电连接；
所述第一发光控制晶体管的栅极与发光控制信号线电连接，所述第一发光控制晶体管的第一极与工作电压传输线电连接，所述第一发光控制晶体管的第二极与驱动晶体管的第一极电连接；
所述第二发光控制晶体管的栅极与发光控制信号线电连接，所述第二发光控制晶体管的第一极与驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件的第一电极电连接；
所述电容的第一端板与所述驱动晶体管的栅极连接，所述电容的第二端板与所述工作电压传输线连接。
在一些实施例中，所述数据写入晶体管位于所述第一晶体管层，所述数据写入晶体管的沟道区和源漏掺杂区位于第一有源层；
所述阈值补偿晶体管位于所述第一晶体管层，所述阈值补偿晶体管的沟道区和源漏掺杂区位于所述第一有源层；
所述第一复位晶体管位于所述第一晶体管层，所述第一复位晶体管的沟道区和源漏掺杂区位于所述第一有源层；
所述第二复位晶体管位于所述第二晶体管层，所述第二复位晶体管的沟道区和源漏掺杂区位于所述第二有源层；
所述第一发光控制晶体管位于所述第二晶体管层，所述第一发光控制晶体管的沟道区和源漏掺杂区位于所述第二有源层；
所述第二发光控制晶体管位于所述第二晶体管层，所述第二发光控制晶体管的沟道区和源漏掺杂区位于所述第二有源层。
第二方面，本公开实施例还提供了一种显示装置，其中，包括：如上述第一方面中提供的所述显示基板。
第三方面，本公开实施例还提供了一种显示基板的制备方法，其中，所述显示基板为上述第一方面中提供的所述显示基板，所述制备 方法包括：
在衬底基板的一侧形成第一晶体管层，所述第一晶体管层包括第一有源层，所述第一有源层的材料包括低温多晶硅材料，所述第一有源层包括至少一个第一沟道区和至少一个第一源漏掺杂区；
在所述第一晶体管层远离衬底基板的一侧形成第二晶体管层，所述第一晶体管层包括第二有源层，所述第一有源层与所述第二有源层之间设置有至少一层绝缘层，所述第二有源层的材料包括低温多晶硅材料，所述第二有源层包括至少一个第二沟道区和至少一个第二源漏掺杂区，至少一个所述第二源漏掺杂区在所述衬底基板上的正投影与至少一个所述第一源漏掺杂区在所述衬底基板上的正投影存在交叠，至少一个所述第二源漏掺杂区通过填充于所述绝缘层上第一过孔内的连接部与对应的所述第一源漏掺杂区相连。
在一些实施例中，所述形成第一晶体管层的步骤包括：
在衬底基板的一侧形成第一多晶硅材料薄膜，并对所述第一多晶硅材料薄膜进行图形化，得到第一多晶硅图形；
在所述第一多晶硅图形远离所述衬底基板的一侧形成第一栅绝缘层；
在所述第一栅绝缘层远离所述衬底基板的一侧形成第一导电层，所述第一导电层包括位于所述第一晶体管层的各晶体管的栅极；
以所述第一导电层作为掺杂用掩模，对所述第一多晶硅图形进行离子注入处理，所述第一多晶硅图形上未被所述第一导电层所遮挡的部分导体化作为所述第一源漏掺杂区，所述第一多晶硅图形上被所述第一导电层遮挡的部分作为第一沟道区。
在一些实施例中，所述形成第二晶体管层的步骤包括：
在所述第一晶体管层远离衬底基板的一侧形成第二多晶硅材料薄膜，并对所述第二多晶硅材料薄膜进行图形化，得到第二多晶硅图形，所述第二多晶硅图形填充所述第一过孔；
在所述第二多晶硅图形远离所述衬底基板的一侧形成第三栅绝缘 层；
在所述第三栅绝缘层远离所述衬底基板的一侧形成第三导电层，所述第三导电层包括位于所述第二晶体管层的各晶体管的栅极；
以所述第三导电层作为掺杂用掩模，对所述第二多晶硅图形进行离子注入处理，所述第二多晶硅图形上未被所述第三导电层所覆盖的部分导体化作为所述第二源漏掺杂区和所述连接部，所述第二多晶硅图形上被所述第三导电层覆盖的部分作为第二沟道区。
在一些实施例中，所述形成第二晶体管层的步骤包括：
在所述第一晶体管层远离衬底基板的一侧形成第二多晶硅材料薄膜，并对所述第二多晶硅材料薄膜进行图形化，得到第二多晶硅图形，所述第二多晶硅图形填充所述第一过孔；
在所述第二多晶硅图形远离所述第二多晶硅图形的一侧形成图形化光刻胶层，所述图形化光刻胶层覆盖后续待形成所述第二沟道区的区域且露出后续待形成所述第二源漏掺杂区和所述连接部的区域；
以所述图形化光刻胶层作为掺杂用掩模，对所述第二多晶硅图形进行离子注入处理，所述第二多晶硅图形上未被所述图形化光刻胶层所覆盖的部分被导体化作为所述第二源漏掺杂区和所述连接部，所述第二多晶硅图形上被所述图形化光刻胶层覆盖的部分作为第二沟道区。
在一些实施例中，对所述第二多晶硅图形进行离子注入处理的步骤包括：
采用多次离子注入工艺进行离子注入处理，以使得所述第二多晶硅图形填充于所述第一过孔内的部分被导体化形成所述连接部，且所述连接部在沿垂直于所述衬底基板的方向上具有至少2个掺杂浓度中心。
在一些实施例中，所述离子注入的离子束能量为5KeV～90KeV；
所述离子注入的离子束剂量为1017/cm2～1022/cm2。
在一些实施例中，在所述第一晶体管层远离衬底基板的一侧形成 第二多晶硅材料薄膜的步骤之前，还包括：
在所述第一晶体管层远离衬底基板的一侧形成第二缓冲层，所述第二缓冲层的厚度为：
Figure PCTCN2022074526-appb-000002
附图说明
图1为本公开实施例所提供显示基板上部分区域的一种截面示意图；
图2为本公开实施例所提供显示基板上部分区域的另一种截面示意图；
图3为本公开实施例所提供显示基板上部分区域的又一种截面示意图；
图4为本公开实施例所提供显示基板上部分区域的再一种截面示意图；
图5为本公开实施例所提供显示基板上部分区域的再一种截面示意图；
图6为本公开实施例中像素驱动电路的一种电路结构示意图；
图7为图6所示像素驱动电路内各晶体管的一种分布结构示意图；
图8为本公开实施例所提供显示基板上部分区域的再一种截面示意图；
图9为本公开实施例所提供显示基板上部分区域的再一种截面示意图；
图10为本公开实施例提供显示基板的制备方法的一种流程图；
图11为本公开实施例提供的显示基板的制备方法的另一种流程图；
图12A～12N为采用图11所示制备方法制备显示基板的中间产品截面示意图；
图13为本公开实施例提供的显示基板的制备方法的又一种流程 图；
图14A～图14B为采用图案化光刻胶层进行离子注入处理的一种截面示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种显示基板及其制备方法和显示装置进行详细描述。
在相关技术所涉及的低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)薄膜晶体管(Thin Film Transistor，简称TFT)型显示基板中，所有LTPS-TFT沿平行于衬底基板的方向布置；也就是说，所有低温多晶硅薄膜晶体管位于同一晶体管层结构中；具体地，所有LTPS-TFT的有源层同层设置。受限于LTPS-TFT的制备工艺，单个像素驱动电路在平行于衬底基板的平面上所占用面积难以进一步减小，显示装置的分辨率难以进一步提升。
为有效改善相关技术中存在的上述技术问题，本公开提供了相应的解决方案。
图1为本公开实施例所提供显示基板上部分区域的一种截面示意图，如图1所示，该显示基板包括：衬底基板1、第一晶体管层和第二晶体管层，第一晶体管层和第二晶体管层沿远离衬底基板1的方向依次设置。其中，第一晶体管层包括第一有源层2，第二晶体管层包括第二有源层3，第一有源层2与第二有源层3之间设置有至少一层绝缘层。
第一有源层2和第二有源层3的材料均包括低温多晶硅材料，第一有源层2包括至少一个第一沟道区201和至少一个第一源漏掺杂区202，第二有源层3包括至少一个第二沟道区301和至少一个第二源漏掺杂区302，至少一个第二源漏掺杂区302在衬底基板1上的正投影与至少一个第一源漏掺杂区202在衬底基板1上的正投影存在交叠，至少一个第二源漏掺杂区302通过填充于绝缘层4上第一过孔401内 的连接部302a与对应的第一源漏掺杂区202相连。
需要说明的是，本公开实施例中的“晶体管层”是指形成有晶体管的层结构；“沟道区”为所属有源层内具有半导体特性的部分，作为晶体管的有源沟道；本公开实施例中的“源漏掺杂区”为所属有源层内通过掺杂被导体化的部分，可作为晶体管的源极和漏极。其中，属于同一有源层的沟道区和源漏掺杂区可以为一体形成的低温多晶硅层。
在本公开实施例中，两个晶体管层结构的层叠设计且两个晶体管层结构内的有源层存在交叠，即像素驱动电路内的晶体管可以根据需要分布于两个晶体管层结构内，且像素驱动电路内的至少两个晶体管的源漏掺杂区会存在在垂直衬底基板的方向存在交叠，通过该设计可使得像素驱动电路在平行于衬底基板的平面上所占用面积减小。
与此同时，像素驱动电路内不可避免的需要两个晶体管的源漏极进行电连接(后面将结合具体示例做详细描述)，在本公开实施例中可根据实际需要，将源漏极需要电连接的两个晶体管分别布置于第一晶体管层和第二晶体管层，且将其中位于第二晶体管层的一个晶体管的源漏掺杂区(即第二源漏掺杂区302)与位于第一晶体管层的一个晶体管源漏掺杂区(即第一源漏掺杂区202)通过绝缘层4上的第一过孔401相连，以实现该两个晶体管的源漏极的电连接。在一些实施例中，连接部的材料包括至少两种不同结晶度的硅和导体化用掺杂离子，也就是说，连接部和第二源漏掺杂区可以基于同一硅材料薄膜的掺杂工艺进行同时制备，此时连接部可看作是第二源漏掺杂区的一部分。在本公开实施例中，位于不同晶体管层的两个晶体管的源漏掺杂区通过过孔相连，因而无需额外再布置用于将两个晶体管的源漏掺杂区进行电连接的其他导电结构，故也能够在一定程度上节省布线空间，有利于减小像素驱动电路在平行于衬底基板的平面上所占用面积。
在本公开实施例中，第二有源层3的制备过程如下：首先形成非晶硅(α-Si)材料薄膜，非晶硅材料薄膜填充第一过孔401；然后对采用准分子激光退火技术(ELA)对非晶硅材料薄膜进行激光照射， 以形成多晶硅材料薄膜；接着对多晶硅材料薄膜进行图形化工艺(也称为构图工艺，通常包括光刻胶涂敷、曝光、显影、薄膜刻蚀、光刻胶剥离等工艺)，得到多晶硅图形，多晶硅图形填充第一过孔401；再接着，根据需要对多晶硅图形上的部分区域进行离子注入以对相应区域进行导体化，得到第二有源层。此时，多晶硅图形上被导体化的部分作为源漏掺杂区和连接部，多晶硅图形上未被导体化且保持半导体特性的部分作为沟道区。
一般地，在对位于过孔内具有较厚厚度的非晶硅进行结晶处理以形成多晶硅的过程中，往往需要采用复杂的结晶工艺来保证过孔内的非晶硅尽可能多的结晶(例如采用多次ELA工艺并选择不同焦深以提升非晶硅的结晶量)；这会导致结晶工艺的工艺时长过长、耗能过高。
在本申请中，在制备第二有源层3的过程中，在对用于形成第二有源层3的非晶硅材料薄膜进行结晶处理过程中，仍是采用常规的ELA工艺，仅需保证非晶硅材料薄膜位于有源层上方的部分尽可能的完全结晶，而位于非晶硅材料薄膜位于第一过孔内的部分可以为非晶硅和多晶硅的混合状态。这是因为，在本公开实施例中，经过结晶工艺、图形化工艺得到的多晶硅图形，其位于过孔内的部分后续需要进行离子注入处理以实现导通化，而无论是非晶硅还是多晶硅通过离子注入处理实现重掺杂后，均可具备良好的欧姆接触且具有较低电阻值。故在本公开实施例中，最终填充于第一过孔401内的连接部302a的材料包括：非晶硅、多晶硅和导体化用掺杂离子。通过上述设计，可有效缩短第二有源层3的制备工艺时长以及减少工艺耗能。
在一些实施例中，连接部302a在沿垂直于衬底基板1的方向上具有至少2个掺杂浓度中心。在本公开实施例中，用于形成第二有源层3的多晶硅图形位于第一过孔401内的部分具有较厚厚度，而单次离子注入过程的离子注入浓度中心范围有限，单次离子注入工艺无法保证多晶硅图形位于第一过孔401内的部分能够呈现出较佳的导电性，故本公开实施中采用多次离子注入工艺且选择不同离子注入深度，以保证多晶硅图形位于第一过孔401内的部分且在不同深度处均能形成 有效重掺杂，从而保证导电性能。此时，所形成的连接部302在沿垂直于衬底基板1的方向上具有至少2个掺杂浓度中心。在实际应用中，可通过改变离子注入的离子束能量来调整离子注入的深度；一般地，在不考虑其他因素的情况下，离子束能量越高，则离子注入的深度越深，所形成的掺杂浓度中心也越深。
在一些实施例中，第一过孔401的坡度角β为30°～75°。其中，过孔的坡度角是指相应结构中用于围成该过孔的坡面与相应结构的底面所形成的夹角。在本公开实施例中，第一过孔401为锥形孔，在沿靠近衬底基板1的方向上孔径逐渐缩小，有利于ELA工艺过程中激光能量密度照射形成多晶硅。其中，坡度角β越大，则表明过孔的坡面越陡。在第一过孔401底部的孔径一定的情况下，坡度角β越大，则第一过孔401顶部的孔径越小，此时第一过孔401在平行于衬底基板1的平面上所占用面积越小；然而当坡度角β过大时，则后续所形成用于制备第二有源层3的非晶硅材料薄膜难以覆盖第一过孔401的坡面，容易出现断裂。故综合考量过孔尺寸以及第二有源层3的断裂风险，在本公开实施例中第一过孔401的坡度角β设置为30°～75°。例如坡度角为30°、45°、60°、75°。
图2为本公开实施例所提供显示基板上部分区域的另一种截面示意图，如图2所示，在一些实施例中，第一沟道区201在衬底基板1上的正投影与第二沟道区301在衬底基板1上的正投影存在交叠。通过该设计，可使得第一有源层2与第二有源层3的交叠面积更大，此时更有利于像素驱动电路在平行于衬底基板1的平面上所占用面积的减小。
进一步地，第一有源层2和第二有源层3之间设置有屏蔽电极图形801；屏蔽电极图形801在衬底基板1上的正投影，覆盖第一沟道区201和第二沟道区301二者在衬底基板1上正投影相交叠的区域。在本公开实施例中，通过在垂直于衬底基板1方向上存在交叠的两个沟道区之间设置屏蔽电极图形801，可有效避免该两个沟道区所属晶体管的内部电场相互干扰。
图3为本公开实施例所提供显示基板上部分区域的又一种截面示意图，如图3所示，在一些实施例中，第一晶体管层还包括：第一栅绝缘层5和第二导电层8。其中，第一栅绝缘层5位于第一有源层2远离衬底基板1的一侧；第一导电层6位于第一栅绝缘层5远离衬底基板1的一侧，第一导电层6包括位于第一晶体管层的各晶体管T与第一沟道区201相对应的栅极g。
在一些实施例中，在第一有源层2和衬底基板1之间还设置有第一缓冲层21。
在一些实施例中，第一导电层6还包括：电容C的第一端板c1；第一晶体管层还包括：第二栅绝缘层7和第二导电层8。其中，第二栅绝缘层7位于第一导电层6远离衬底基板1的一侧；第二导电层8位于第二栅绝缘层7远离衬底基板1的一侧，第二导电层8包括与电容C的第一端板c1相对设置的第二端板c2。
在一些实施例中，在第一有源层2和第二有源层3之间设置有屏蔽电极图形801时，屏蔽电极图形801位于第二导电层8。
在一些实施例中，第二晶体管层还包括：第三栅绝缘层9和第三导电层10。其中，第三栅绝缘层9位于第二有源层3远离衬底基板1的一侧；第三导电层10位于第三栅绝缘层9远离衬底基板1的一侧，第三导电层10包括位于第二晶体管层的各晶体管与第二沟道区301相对应的栅极g。
在一些实施例中，第二晶体管层还包括：第二缓冲层22，第二缓冲层22位于第二有源层3靠近衬底基板1的一侧且与第二有源层3相接触。其中，第二缓冲层22的设置可有效提升第二有源层3的结晶效果。具体地，当没有设置缓冲层时，在制备第二有源层3过程中所形成的非晶硅材料薄膜一部分会覆盖在第二导电层8表面，一部分会覆盖在第二栅绝缘层7表面(当不存在第二导电层8和第二栅绝缘层7时，在制备第二有源层3过程中所形成的非晶硅材料薄膜一部分会覆盖在第一导电层6表面，一部分会覆盖在第一栅绝缘层5表面)，也就是说，非晶硅材料薄膜下方接触有两种不同材料；在对非晶硅材料 薄膜进行结晶处理过程中，与导电层相接触的非晶硅和与栅绝缘层相接触的非晶硅的发生较大的晶化差异，从而导致所形成的晶体结构有较大差异。为有效改善上述问题，在本公开实施例中，在制备第二有源层3之前先形成一层用于与第二有源层3相接触的第二缓冲层22，以保证结晶处理过程中各位置非晶硅的晶化均一性。
在一些实施例中，第二缓冲层22的厚度为：
Figure PCTCN2022074526-appb-000003
进一步可选地，第二缓冲层22的厚度为
Figure PCTCN2022074526-appb-000004
在一些实施例中，显示基板还包括：层间介质层11和第四导电层12。其中，层间介质层11，位于第二晶体管层远离衬底基板1的一侧；第四导电层12位于层间介质层11远离衬底基板1的一侧，第四导电层12包括：数据线(图3中未示出)和导电连接结构P，导电连接结构P通过过孔连接至第一源漏掺杂区202或第二源漏掺杂区302。
在本公开实施例中第一源漏掺杂区202和第二源漏掺杂区302可根据实际电路需要，通过对应的导电连接结构P将晶体管的源极和漏极引出，以方便与其他电学结构进行电连接。需要说明的是，在本公开实施例中，并非显示基板上的每个晶体管的源漏掺杂区均配置有对应的导电连接结构P，而是根据实际需要来配置的。
需要说明的是，图3中仅示例性画出4个晶体管T和1个电容C，且其中2个晶体管T位于第一晶体管层，另外2个晶体管T位于第二晶体管层的情况。另外，附图3中也仅示例性画出了4个导电连接结构P。图3所示情况，仅起到示例性作用，其不会对本公开的技术方案产生限制。
图4为本公开实施例所提供显示基板上部分区域的再一种截面示意图，如图4所示，在一些实施例中，显示基板还包括：平坦化层13、第一像素界定层15、发光层、第二电极17层。
其中，平坦化层13位于第四导电层12远离衬底基板1的一侧；第一电极14层位于平坦化层13远离衬底基板1的一侧，第一电极层包括多个第一电极，第一电极14通过过孔连接至对应的导电连接结构P以与对应的第一源漏掺杂区202或第二源漏掺杂区302电连接；第 一像素界定层15位于第一电极层远离衬底基板1的一侧，第一像素界定层15上形成有多个第一像素容纳孔，第一像素容纳孔连通至对应的第一电极14；发光层包括多个电致发光图形16，电致发光图形16位于对应的第一像素容纳孔内；第二电极层位于第一像素界定层15远离衬底基板1的一侧，第二电极层包括第二电极17，可选地第二电极17为面状电极。
在本公开实施例中，第一电极14、第一电极14所对应第一像素容纳孔内的电致发光图形16和第二电极17构成发光元件EL。当然，在第一电极14与电致发光图形16之间、电致发光图形16与第二电极17之间还可以根据实际需要来设置一些功能性层结构，例如电子阻挡层、空穴传输层、电子传输层、空穴阻挡层等。
在一些实施例中，电致发光图形16的材料为有机发光材料，此时发光元件EL有有机发光二极管(Organic Light Emitting Diode，简称OLED)。
在另一些实施例中，电致发光图形16的材料为量子点材料，此时发光元件EL为量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)。
具体地，电致发光图形16可以具有其中多个量子点分散在基体部件中的形状。其中，量子点可为半导体纳米晶体，并且可具有多种形状例如球形、锥形、多臂和/或立方形的纳米颗粒、纳米管、纳米线、纳米纤维、纳米板颗粒、量子棒、或量子片。在这里，量子棒可为具有大于约1、例如大于或等于约2、大于或等于约3、或者大于或等于约5的纵横比(长径比)(长度:宽度比)的量子点。例如，量子棒可具有小于或等于约50、小于或等于约30、或者小于或等于约20的纵横比。
量子点可具有，例如，例如约1nm至约100nm、约1nm至约80nm、约1nm至约50nm、或约1nm至20nm的颗粒直径(对于非球形形状，平均最大颗粒长度)。
可根据量子点的尺寸和组成控制量子点的能带隙，且因此可控制发光波长。例如，当量子点的尺寸增加时，量子点可具有窄的能带隙 且因此配置成发射在相对长的波长区域中的光，而当量子点的尺寸减小时，量子点可具有宽的能带隙且因此配置成发射在相对短的波长区域中的光。例如，量子点可根据其尺寸和/或组成而配置成发射在可见光区域的预定波长区域中的光。例如，量子点可配置成发射蓝光、红光、或绿光，并且蓝光可具有例如在约430nm至约480nm中的峰值发射波长(λ最大)，红色光可具有例如在约600nm至约650nm中的峰值发射波长(λ最大)，且绿光可具有例如在约520nm至约560nm中的峰值发射波长(λ最大)。
例如，配置成发射蓝光的量子点的平均颗粒尺寸可例如小于或等于约4.5nm、和例如小于或等于约4.3nm、小于或等于约4.2nm、小于或等于约4.1nm、或者小于或等于约4.0nm。在范围内，例如，量子点的平均颗粒尺寸可为约2.0nm至约4.5nm、例如约2.0nm至约4.3nm、约2.0nm至约4.2nm、约2.0nm至约4.1nm、或约2.0nm至约4.0nm。
量子点可具有例如大于或等于约10％、大于或等于约20％、大于或等于约30％、大于或等于约50％、大于或等于约60％、大于或等于约70％、或者大于或等于约90％的量子产率。
量子点可具有相对窄的半宽度(FWHM)。在这里，FWHM为对应于峰值吸收点的一半的波长的宽度，并且当FWHM较窄时，可配置成发射在较窄波长区域中的光，并且可获得较高的色纯度。量子点可具有例如小于或等于约50nm、小于或等于约49nm、小于或等于约48nm、小于或等于约47nm、小于或等于约46nm、小于或等于约45nm、小于或等于约44nm、小于或等于约43nm、小于或等于约42nm、小于或等于约41nm、小于或等于约40nm、小于或等于约39nm、小于或等于约38nm、小于或等于约37nm、小于或等于约36nm、小于或等于约35nm、小于或等于约34nm、小于或等于约33nm、小于或等于约32nm、小于或等于约31nm、小于或等于约30nm、小于或等于约29nm、或者小于或等于约28nm的FWHM。在范围内，其可具有例如约2nm至约49nm、约2nm至约48nm、约2nm至约47nm、约2nm至约46nm、约2nm至约45nm、约2nm至约44nm、约2nm至约43nm、约2nm至约42nm、 约2nm至约41nm、约2nm至约40nm、约2nm至约39nm、约2nm至约38nm、约2nm至约37nm、约2nm至约36nm、约2nm至约35nm、约2nm至约34nm、约2nm至约33nm、约2nm至约32nm、约2nm至约31nm、约2nm至约30nm、约2nm至约29nm、或约2nm至约28nm的FWHM。
例如，量子点可包括II-VI族半导体化合物、III-V族半导体化合物、IV-VI族半导体化合物、IV族半导体、I-III-VI族半导体化合物、I-II-IV-VI族半导体化合物、II-III-V族半导体化合物、或其组合。II-VI族半导体化合物可例如选自：二元化合物例如CdSe、CdTe、ZnS、ZnSe、ZnTe、ZnO、HgS、HgSe、HgTe、MgSe、MgS、或其混合物；三元化合物例如CdSeS、CdSeTe、CdSTe、ZnSeS、ZnSeTe、ZnSTe、HgSeS、HgSeTe、HgSTe、CdZnS、CdZnSe、CdZnTe、CdHgS、CdHgSe、CdHgTe、HgZnS、HgZnSe、HgZnTe、MgZnSe、MgZnS、或其混合物；和四元化合物例如HgZnTeS、CdZnSeS、CdZnSeTe、CdZnSTe、CdHgSeS、CdHgSeTe、CdHgSTe、HgZnSeS、HgZnSeTe、HgZnSTe、或其混合物，但不限于此。III-V族半导体化合物可例如选自：二元化合物例如GaN、GaP、GaAs、GaSb、AlN、AlP、AlAs、AlSb、InN、InP、InAs、InSb、或其混合物；三元化合物例如GaNP、GaNAs、GaNSb、GaPAs、GaPSb、AlNP、AlNAs、AlNSb、AlPAs、AlPSb、InNP、InNAs、InNSb、InPAs、InPSb、或其混合物；和四元化合物例如GaAlNP、GaAlNAs、GaAlNSb、GaAlPAs、GaAlPSb、GaInNP、GaInNAs、GaInNSb、GaInPAs、GaInPSb、InAlNP、InAlNAs、InAlNSb、InAlPAs、InAlPSb、或其混合物，但不限于此。IV-VI族半导体化合物可例如选自：二元化合物例如SnS、SnSe、SnTe、PbS、PbSe、PbTe、或其混合物；三元化合物例如SnSeS、SnSeTe、SnSTe、PbSeS、PbSeTe、PbSTe、SnPbS、SnPbSe、SnPbTe、或其混合物；和四元化合物例如SnPbSSe、SnPbSeTe、SnPbSTe、或其混合物，但不限于此。IV族半导体可例如选自：单质(一元)半导体例如Si、Ge、或其混合物；和二元半导体化合物例如SiC、SiGe、和其混合物，但不限于此。I-III-VI族半导体化合物可为例如CuInSe2、CuInS2、CuInGaSe、CuInGaS、或其混合物，但不限于此。I-II-IV-VI 族半导体化合物可为例如CuZnSnSe、CuZnSnS、或其混合物，但不限于此。II-III-V族半导体化合物可包括例如InZnP，但不限于此。
量子点可以基本上均匀的浓度或局部不同的浓度分布包括单质半导体、二元半导体化合物、三元半导体化合物、或四元半导体化合物。
例如，量子点可包括无镉(Cd)量子点。无镉量子点是不包括镉(Cd)的量子点。镉(Cd)可引起严重的环境/健康问题和是在多个国家中按照有害物质限制指令(RoHS)的被限制的元素，且因此非镉基量子点可被有效地使用。
作为实例，量子点可为包括锌(Zn)、以及碲(Te)和硒(Se)的至少一种的半导体化合物。例如，量子点可为Zn-Te半导体化合物、Zn-Se半导体化合物、和/或Zn-Te-Se半导体化合物。例如，Zn-Te-Se半导体化合物中的碲(Te)的量可小于硒(Se)的量。半导体化合物可具有在小于或等于约480nm、例如约430nm至约480nm的波长区域中的峰值发射波长(λ最大)，并且可配置成发射蓝色光。
例如，量子点可为包括铟(In)、以及锌(Zn)和磷(P)的至少一种的半导体化合物。例如，量子点可为In-P半导体化合物和/或In-Zn-P半导体化合物。例如，在In-Zn-P半导体化合物中，锌(Zn)对铟(In)的摩尔比可大于或等于约25。半导体化合物可具有在小于约700nm、例如约600nm至约650nm的波长区域中的峰值发射波长(λ最大)，并且可配置成发射红色光。
量子点可具有芯-壳结构，其中一个量子点围绕另一量子点。例如，量子点的芯和壳可具有界面，并且在界面中的芯或壳的至少一个的元素可具有浓度梯度，其中壳的元素的浓度朝着芯降低。例如，量子点的壳的材料组成具有比量子点的芯的材料组成高的能带隙，且由此量子点可呈现出量子限制效应。
量子点可具有一个量子点芯和围绕芯的多层量子点壳。在这里，多层壳具有至少两个壳，其中各壳可为单一组成、合金、和/或具有浓度梯度者。
例如，多层壳的远离芯的壳可具有比靠近芯的壳高的能带隙，且 由此量子点可呈现出量子限制效应。
例如，具有芯-壳结构的量子点可例如包括：芯，芯包括第一半导体化合物，第一半导体化合物包括锌(Zn)、以及碲(Te)和硒(Se)的至少一种；以及设置在芯的至少一部分上并且具有与芯的组成不同的组成的包括第二半导体化合物的壳。
例如，第一半导体化合物可为包括锌(Zn)、碲(Te)和硒(Se)的基于Zn-Te-Se的半导体化合物，例如，包括少量的碲(Te)的基于Zn-Se的半导体化合物，例如，由ZnTexSe1-x表示的半导体化合物，其中x大于约0且小于或等于0.05。
例如，在基于Zn-Te-Se的第一半导体化合物中，锌(Zn)的摩尔量可高于硒(Se)的摩尔量，且硒(Se)的摩尔量可高于碲(Te)的摩尔量。例如，在第一半导体化合物中，碲(Te)对硒(Se)的摩尔比可小于或等于约0.05、小于或等于约0.049、小于或等于约0.048、小于或等于约0.047、小于或等于约0.045、小于或等于约0.044、小于或等于约0.043、小于或等于约0.042、小于或等于约0.041、小于或等于约0.04、小于或等于约0.039、小于或等于约0.035、小于或等于约0.03、小于或等于约0.029、小于或等于约0.025、小于或等于约0.024、小于或等于约0.023、小于或等于约0.022、小于或等于约0.021、小于或等于约0.02、小于或等于约0.019、小于或等于约0.018、小于或等于约0.017、小于或等于约0.016、小于或等于约0.015、小于或等于约0.014、小于或等于约0.013、小于或等于约0.012、小于或等于约0.011、或者小于或等于约0.01。例如，在第一半导体化合物中，碲(Te)对锌(Zn)的摩尔比可小于或等于约0.02、小于或等于约0.019、小于或等于约0.018、小于或等于约0.017、小于或等于约0.016、小于或等于约0.015、小于或等于约0.014、小于或等于约0.013、小于或等于约0.012、小于或等于约0.011、或者小于或等于约0.010。
第二半导体化合物可包括例如II-VI族半导体化合物、III-V族半导体化合物、IV-VI族半导体化合物、IV族半导体、I-III-VI族半导体化合物、I-II-IV-VI族半导体化合物、II-III-V族半导体化合物、或其 组合。II-VI族半导体化合物、III-V族半导体化合物、IV-VI族半导体化合物、IV族半导体、I-III-VI族半导体化合物、I-II-IV-VI族半导体化合物、和II-III-V族半导体化合物的实例与以上面描述的相同。
例如，第二半导体化合物可包括锌(Zn)、硒(Se)、和/或硫(S)。例如，壳可包括ZnSeS、ZnSe、ZnS、或其组合。例如，壳可包括靠近芯设置的至少一个内壳和设置在量子点的最外侧处的最外面的壳。内壳可包括ZnSeS、ZnSe、或其组合，且最外面的壳可包括ZnS。例如，壳可具有一种成分的浓度梯度，和例如硫(S)的量可随着离开芯而增加。
例如，具有芯-壳结构的量子点可包括：芯，芯包括第三半导体化合物，第三半导体化合物包括铟(In)、以及锌(Zn)和磷(P)的至少一种；以及设置在芯的至少一部分上并且包括具有与芯不同的组成的第四半导体化合物的壳。
在基于In-Zn-P的第三半导体化合物中，锌(Zn)对铟(In)的摩尔比可大于或等于约25。例如，在基于In-Zn-P的第三半导体化合物中，锌(Zn)对铟(In)的摩尔比可大于或等于约28、大于或等于约29、或者大于或等于约30。例如，在基于In-Zn-P的第三半导体化合物中，锌(Zn)对铟(In)的摩尔比可小于或等于约55、例如小于或等于约50、小于或等于约45、小于或等于约40、小于或等于约35、小于或等于约34、小于或等于约33、或者小于或等于约32。
第四半导体化合物可包括例如II-VI族半导体化合物、III-V族半导体化合物、IV-VI族半导体化合物、IV族半导体、I-III-VI族半导体化合物、I-II-IV-VI族半导体化合物、II-III-V族半导体化合物、或其组合。II-VI族半导体化合物、III-V族半导体化合物、IV-VI族半导体化合物、IV族半导体、I-III-VI族半导体化合物、I-II-IV-VI族半导体化合物、和II-III-V族半导体化合物的实例与以上描述的相同。
例如，第四半导体化合物可包括锌(Zn)和硫(S)以及任选地硒(Se)。例如，壳可包括ZnSeS、ZnSe、ZnS、或其组合。例如，壳可包括靠近芯设置的至少一个内壳和设置在量子点的最外侧处的最外面的壳。内 壳和最外面的壳的至少一个可包括第四半导体化合物ZnS、ZnSe、或ZnSeS。
发射层可具有如下的厚度：例如约5nm至约200nm，在范围内，例如约10nm至约150nm、例如约10nm至约100nm、例如约10nm至约50nm。包含在发射层EML中的量子点QD可以被层压成一个或多于一个的层，例如：两个层。然而，本发明构思的实施方案不限于此，并且量子点QD可以被层压成一个至十个层。取决于被使用的量子点QD的种类(或类型)以及光的期望发射波长，量子点QD可以被层压成任何合适数量的层。
量子点可具有相对深的HOMO能级，例如，如下的HOMO能级：大于或等于约5.4eV，在范围内，例如大于或等于约5.5eV、例如大于或等于约5.6eV、例如大于或等于约5.7eV、例如约大于或等于约5.8eV、例如大于或等于约5.9eV、例如大于或等于约6.0eV。在范围内，量子点层13的HOMO能级可为例如约5.4eV至约7.0eV、例如约5.4eV至约6.8eV、例如约5.4eV至约6.7eV、例如约5.4eV至约6.5eV、例如约5.4eV至约6.3eV、例如约5.4eV至约6.2eV、例如约5.4eV至约6.1eV，在范围内，例如约5.5eV至约7.0eV、例如约5.5eV至约6.8eV、例如约5.5eV至约6.7eV、例如约5.5eV至约6.5eV、例如约5.5eV至约6.3eV、例如约5.5eV至约6.2eV、例如约5.5eV至约6.1eV、例如约5.5eV至约7.0eV、例如约5.6eV至约6.8eV、例如约5.6eV至约6.7eV、例如约5.6eV至约6.5eV、例如约5.6eV至约6.3eV、例如约5.6eV至约6.2eV、例如约5.6eV至约6.1eV，在范围内，例如约5.7eV至约7.0eV、例如约5.7eV至约6.8eV、例如约5.7eV至约6.7eV、例如约5.7eV至约6.5eV、例如约5.7eV至约6.3eV、例如约5.7eV至约6.2eV、例如约5.7eV至约6.1eV，在范围内，例如约5.8eV至约7.0eV、例如约5.8eV至约6.8eV、例如约5.8eV至约6.7eV、例如约5.8eV至约6.5eV、例如约5.8eV至约6.3eV、例如约5.8eV至约6.2eV、例如约5.8eV至约6.1eV，在范围内，例如约6.0eV至约7.0eV、例如约6.0eV至约6.8eV、例如约6.0eV至约6.7eV、例如约6.0eV至约6.5eV、例如约6.0eV至约6.3eV、例如约6.0eV至约6.2eV。
量子点可具有相对浅的LUMO能级，例如，小于或等于约3.7eV，在范围内，例如小于或等于约3.6eV、例如小于或等于约3.5eV、例如小于或等于约3.4eV、例如小于或等于约3.3eV、例如小于或等于约3.2eV、例如小于或等于约3.0eV。在范围内，量子点层13的LUMO能级可为约2.5eV至约3.7eV、约2.5eV至约3.6eV、约2.5eV至约3.5eV、约2.5eV至约3.4eV、约2.5eV至约3.3eV、约2.5eV至约3.2eV、约2.5eV至约3.1eV、约2.5eV至约3.0eV、约2.8eV至约3.7eV、约2.8eV至约3.6eV、约2.8eV至约3.5eV、约2.8eV至约3.4eV、约2.8eV至约3.3eV、约2.8eV至约3.2eV、约3.0eV至约3.7eV、约3.0eV至约3.6eV、约3.0eV至约3.5eV、或约3.0eV至约3.4eV。
量子点可具有约1.7eV至约2.3eV或约2.4eV至约2.9eV的能带隙。在范围内，例如，量子点层13可具有如下的能带隙：约1.8eV至约2.2eV或约2.4eV至约2.8eV，在范围内，例如约1.9eV至约2.1eV、例如约2.4eV至约2.7eV。
在一些实施例中，第一电极14可以为阳极，此时，第二电极17为阴极。在另一些实施例中，第一电极14可以为阴极，此时，第二电极17为阳极。
该发光器件13的发光原理为：通过阳极和阴极连接的电路，利用阳极向发光功能层133注入空穴，阴极向发光功能层133注入电子，所形成的电子和空穴在发光图案133a中形成激子，激子通过辐射跃迁回到基态，发出光子。
在一些实施例中，阳极可包括具有高的功函数的导体例如金属、导电金属氧化物、或其组合。金属可以是镍、铂、钒、铬、铜、锌、或金、或其合金；导电金属氧化物可以是氧化锌、氧化铟、氧化锡、氧化铟锡(ITO)、氧化铟锌(IZO)、或氟掺杂氧化锡；或者，金属和导电金属氧化物的组合可以是ZnO和Al、或SnO2和Sb、ITO/Ag/ITO，但不限于此。
阴极可包括具有比阳极低的功函数的导体例如金属、导电金属氧化物、和/或导电聚合物。阴极可包括，如，金属可以是铝、镁、钙、 钠、钾、钛、铟、钇、锂、钆、银、锡、铅、铯、钡等、或其合金；多层结构例如LiF/Al、Li2O/Al、Liq/Al、LiF/Ca、和BaF2/Ca；导电金属氧化物可以是氧化锌、氧化铟、氧化锡、氧化铟锡(Indium Tin Oxides，ITO)、氧化铟锌(Indium Zinc Oxides，IZO)、或氟掺杂氧化锡，但不限于此。
阳极的功函可高于阴极的功函，例如，阳极的功函可为例如约4.5eV至约5.0eV且阴极的功函可为约4.0eV至约4.7eV。在该范围内，阳极的功函可为例如约4.6eV至约4.9eV或约4.6eV至约4.8eV，且阴极的功函可为例如约4.0eV至约4.6eV或约4.3eV至约4.6eV。
第一电极14和第二电极17可以是透射电极、部分透过部分反射电极或反射电极，透射电极或部分透过部分反射电极可以包括：导电氧化物例如氧化锌、氧化铟、氧化锡、氧化铟锡(ITO)、氧化铟锌(IZO)、或氟掺杂氧化锡，或者金属薄层。反射电极可以包括：反射金属，例如：不透明导体例如铝(Al)、银(Ag)、或金(Au)，第一电极14和第二电极17可以是单层或多层结构；
第一电极14或第二电极17的至少一者可以与辅助电极(未示出)连接。如果与辅助电极连接，可以减小第二电极17的电阻。
在一些实施例中，上述显示基板1可以为顶发射型发光基板或底发射型发光基板。
在显示基板为顶发射型发光基板的情况下，第二电极17可以为透射电极，第一电极14可以为反射电极。在显示基板为底发射型发光基板的情况下，第一电极14为透射电极，第二电极17为反射电极。
当然，在一些实施例中，该显示基板还可以为双面发射型发光基板，此时，第一电极14和第二电极17均为透射电极。
在另一些实施例中，上述发光器件13可以为“正置”式发光器件或“倒置”式发光器件。
在发光器件13为“正置”式发光器件的情况下，第一电极14为阳极，第二电极17为阴极。在发光器件13为“倒置”式发光器件的情况下，第一电极14为阴极，第二电极17为阳极。
在本公开实施例中，各发光元件EL所发出的光可以相同也可以不同，本公开对此不作限定。
在一些实施例中，在第一像素界定层15和第一电极14层之间设置有隔离坝18；隔离坝18设置在相邻像素开口之间，隔离坝18用于在向像素开口内沉积发光图形的工序中支撑掩膜版以及避免出现混色的问题。
图5为本公开实施例所提供显示基板上部分区域的再一种截面示意图，如图5所示，在一些实施例中，显示基板包括位于衬底基板1上的多个像素单元，像素单元包括发光元件EL和用于驱动发光元件EL的像素驱动电路；像素驱动电路包括：驱动晶体管T1，驱动晶体管T1配置为根据自身的栅源电源向对应的发光元件EL输出相应的驱动电流。
在一些实施例中，驱动晶体管T1位于第一晶体管层，驱动晶体管T1的沟道区和源漏掺杂区位于第一有源层2。在本公开实施例中，驱动晶体管T1的电学特性直接影响了像素驱动电路所输出驱动电流的精准度，故对于驱动晶体管T1的质量要求较高。考虑到实际显示基板制备过程中第一晶体管层的制备工序稳定性明显高于第二晶体管层的制备工序稳定性，故本公开实施例中优选将驱动晶体管T1设计在第一晶体管层。
图6为本公开实施例中像素驱动电路的一种电路结构示意图，图7为图6所示像素驱动电路内各晶体管的一种分布结构示意图，如图5至图7所示，在一些实施例中，像素驱动电路还包括：数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6、第二复位晶体管T7、第一发光控制晶体管T4、第二发光控制晶体管T5和电容C。
在下面描述中，晶体管的“第一极”和“第二极”，二者中之一为晶体管的源极，另一为晶体管的漏极。一般情况下，晶体管的源极和漏极可以互换。下面以第一极s为源极、第二极d为漏极为例进行示例性描述。
其中，数据写入晶体管T2的栅极与对应的栅线Gate电连接，数 据写入晶体管T2的第一极s与对应的数据线Data电连接，数据写入晶体管T2的第二极d与驱动晶体管T1的第一极s电连接。
阈值补偿晶体管T3的栅极与对应的栅线Gate电连接，阈值补偿晶体管T3的第一极s与驱动晶体管T1的第二极d电连接，阈值补偿晶体管T3的第二极d与驱动晶体管T1的栅极电连接。
第一复位晶体管T6的栅极与对应的复位控制信号线Rst电连接，第一复位晶体管T6的第一极s与复位电压传输线VINIT电连接，第一复位晶体管T6的第二极d与驱动晶体管T1的栅极电连接。
第二复位晶体管T7的栅极与对应的复位控制信号线Rst或栅线Gate电连接，第二复位晶体管T7的第一极s与复位电压传输线VINIT电连接，第二复位晶体管T7的第二极d与发光元件EL的第一电极14电连接。
第一发光控制晶体管T4的栅极与发光控制信号线EM电连接，第一发光控制晶体管T4的第一极s与工作电压传输线VDD电连接，第一发光控制晶体管T4的第二极d与驱动晶体管T1的第一极s电连接。
第二发光控制晶体管T5的栅极与发光控制信号线EM电连接，第二发光控制晶体管T5的第一极s与驱动晶体管T1的第二极d连接，第二发光控制晶体管T5的第二极d与发光元件EL的第一电极14电连接。
电容C的第一端板c1与驱动晶体管T1的栅极连接，电容C的第二端板c2与工作电压传输线VDD连接。
需要说明的是，图6中所示像素驱动电路采用7T1C(即7个晶体管T1～T7和1个电容C)的情况，该情况仅起到示例性作用，其不对本公开的技术方案产生限制，本公开的技术方案适用于任意结构的像素驱动电路。
再次参见图5所示，在一些实施例中，数据写入晶体管T2位于第一晶体管层，数据写入晶体管T2的沟道区和源漏掺杂区位于第一有源层2。
阈值补偿晶体管T3位于第一晶体管层，阈值补偿晶体管T3的沟道区和源漏掺杂区位于第一有源层2。
第一复位晶体管T6位于第一晶体管层，第一复位晶体管T6的沟道区和源漏掺杂区位于第一有源层2。
第二复位晶体管T7位于第二晶体管层，第二复位晶体管T7的沟道区和源漏掺杂区位于第二有源层3。
第一发光控制晶体管T4位于第二晶体管层，第一发光控制晶体管T4的沟道区和源漏掺杂区位于第二有源层3。
第二发光控制晶体管T5位于第二晶体管层，第二发光控制晶体管T5的沟道区和源漏掺杂区位于第二有源层3。
在本公开实施例中，考虑到第二复位晶体管T7的第二极d以及第二发光控制晶体管T5的第二极d均与发光元件EL的第一电极14电连接，故将第二复位晶体管T7和第二发光控制晶体管T5设置于更靠近于第一电极14层的第二晶体管层，以尽可能的减小第二复位晶体管T7的第二极d以及第二发光控制晶体管T5的第二极d与发光元件EL的第一电极14之间的距离，有利于布线设计。同时，鉴于第一发光控制晶体管T4与第二发光控制晶体管T5受控于同一发光控制信号线EM，为方便布线，也将第一发光控制晶体管T4设置于第二晶体管层。
此外，考虑到第一晶体管层和第二晶体管层所设置晶体管数量越接近，则越有利于第一有源层2和第二有源层3的交叠区域面积增加，越有利于像素驱动电路在平行于衬底基板1的平面上所占用面积的减小，故在将像素驱动电路内第一发光控制晶体管T4、第二发光控制晶体管T5和第二复位晶体管T7该3个晶体管设置在第二晶体管层的情况下，将数据写入晶体管T2、阈值补偿晶体管T3和第一复位晶体管T6该3个晶体管设置在第一晶体管层。此时，像素驱动电路内的4个晶体管设置在第一晶体管层，像素驱动电路内的另外3个晶体管设置在第二晶体管层，以使得第一晶体管层和第二晶体管层所设置晶体管数量接近。
当然，本公开实施例中，也可根据实际需要将数据写入晶体管T2、 阈值补偿晶体管T3第一复位晶体管T6中至少之一设置于第二晶体管层，将第二复位晶体管T7、第一发光控制晶体管T4、第二发光控制晶体管T5中至少之一设置于第一晶体管层，这些情况也应属于本公开的保护范围。在本公开实施例中，仅需保证第一晶体管层包括像素驱动电路内的至少一个晶体管，且第二晶体管层包括像素驱动电路内的至少一个晶体管即可，具体情况此处不再一一举例描述。
在本公开实施例中，栅线Gate、发光控制信号线EM和复位控制信号线Rst可分别选择性的设置在第一导电层6或第三导电层10，复位电压传输线VINIT可设置在第二导电层8，工作电压传输线VDD可设置在第四导电层12。
参见图5和图7所示，其中第二发光控制晶体管T5的第一极s通过位于第一过孔401内的部分(即连接部)Q1与驱动晶体管T1的第二极d相连，第二复位晶体管T7的第一极s通过位于第一过孔401内的部分(即连接部)Q2与第一复位晶体管T6的第一极s相连。
继续参见图5和图7所示，在第四导电层12内设置有如下导电连接结构P：
针对驱动晶体管T1所设置的导电连接结构包括：通过过孔连接至驱动晶体管T1的栅极的导电连接结构P5(图5中未示出)，通过过孔连接至驱动晶体管T1的第一极s的导电连接结构P4，通过过孔连接至驱动晶体管T1的第二极d的导电连接结构P6，
针对数据写入晶体管T2所设置的导电连接结构包括：通过过孔连接至数据写入晶体管T2的第一极s的导电连接结构P2。
针对阈值补偿晶体管T3所设置的导电连接结构包括：通过过孔连接至阈值补偿晶体管T3的第一极s的导电连接结构P7，通过过孔连接至阈值补偿晶体管T3的第二极d的导电连接结构P8。
针对第一发光控制晶体管T4所设置的导电连接结构包括：通过过孔连接至第一发光控制晶体管T4的第一极s的导电连接结构P1，通过过孔连接至第一发光控制晶体管T4的第二极d的导电连接结构P3。
针对第二发光控制晶体管T5所设置的导电连接结构包括：通过过 孔连接至第二发光控制晶体管T5的第二极d的导电连接结构P10。
针对第一复位晶体管T6所设置的导电连接结构包括：通过过孔连接至第二发光控制晶体管T5的第二极d的导电连接结构P9。
针对第一复位晶体管T6所设置的导电连接结构包括：通过过孔连接至第二发光控制晶体管T5的第二极d的导电连接结构P11。
其中，导电连接结构P3和导电连接结构P4相连，导电连接结构P5、导电连接结构P8和导电连接结构P9相连，导电连接结构P5和导电连接结构P6相连，导电连接结构P10和导电连接结构P11相连，导电连接结构P11与发光元件EL的第一电极14相连。
当然，上述第四导电层12包括导电连接结构P1～P11的情况仅为本公开中的一种可选实施方案，该方案仅起到示例性作用，其不会对本公开的技术方案产生限制。
图8为本公开实施例所提供显示基板上部分区域的再一种截面示意图，如图8所示，在一些实施例中，显示基板还包括：封装层30和色阻层19。其中，封装层30位于第二电极17远离衬底基板1的一侧，封装层30可起到对发光元件进行封装的作用；封装层30可以为单层结构也可以为有机封装层和无机封装层层叠交替设置而形成的多层结构。色阻层19位于封装层30远离衬底基板1的一侧，色阻层19包括与电致发光图形16一一对应的多个色阻图形1901r、1901g、1901b。此外，色阻层19还可以包括黑矩阵1902。
作为一个示例，发光元件EL为能够发出白光的白光OLED，多个色阻图形包括红色色阻图形1901r、绿色色阻图形1901g和蓝色色阻图形1901b，此时白光OLED发出的白光在经过红色色阻图形1901r后呈红色，在经过绿色色阻图形1901g后呈绿色，在经过蓝色色阻图形1901b后呈蓝色。此时，显示基板可用于进行彩色显示。
作为另一个示例，多个发光元件包括能够发出红光的红光QLED、发出绿光的绿光QLED和发出蓝光的蓝光QLED，多个色阻图形包括与红光QLED相对应的红色色阻图形1901r、与绿光QLED相对应的绿色色阻图形1901g和与蓝光QLED相对应的蓝色色阻图形1901b， 此时各色阻图形1901r、1901g、1901b的设置可以提升像素单元的出光纯度，有利于提升产品的显示色域。
图9为本公开实施例所提供显示基板上部分区域的再一种截面示意图，如图9所示，在一些实施例中，电致发光图形16的材料包括有机发光材料(即发光元件为OLED)，显示基板还包括：光转换层，光转换层位于封装层30和色阻层19之间，光转换层包括与至少部分电致发光图形16一一对应的多个光转换彩膜31r、31g，其中光转换彩膜31r、31g能够在发光元件所发出光的激发下产生其他颜色光。
在一些实施例中，光转换彩膜31r、31g的材料包括量子点材料。
需要说明的是，为方便描述将本公开实施例中位于第一电极14与衬底基板1之间的结构称为驱动功能层32结构，对于图8和图9中位于第一电极14与衬底基板1之间的驱动功能层32的具体结构，可参见前面实施例中的描述，此处不再最少。
在一些实施例中，显示基板还包括第二像素界定层20，第二像素界定层20上设置有第二像素容纳孔，第二像素容纳孔与第一像素容纳孔一一对应，光转换彩膜位于对应的第二像素容纳孔内。可选地，可在围成第二容纳孔的侧壁设置反光金属层(未示出)以提升出光量。
作为一个示例，所有发光元件EL为能够发出蓝光的OLED；光转换彩膜包括能够将蓝光转换为红光的红光光转换彩膜31r和能够将蓝光转换为绿光的绿光光转换彩膜31g；其中，红光光转换彩膜31r的材料包括红光量子点材料，绿光光转换彩膜31g的材料包括绿光量子点材料。此外，显示基板中还设置有透明图形31b(材料一般选用透明树脂材料)，透明图形31b也位于对应的第二像素容纳孔内，透明图形31b可使得蓝光透射穿过。色阻层19包括与红光光转换彩膜31r相对对应的红色色阻图形1901r、与绿光光转换彩膜31g绿色色阻图形1901g和与透明图形31b相对应的蓝色色阻图形1901b。上述由量子点材料与OLED相结合所形成的结构为QD-OLED结构。
基于同一发明构思，本公开实施例还提供了一种显示基板的制备方法，该制备方法可用于制备前面实施例所提供的显示基板，对于该 显示基板结构上的描述可参见前面实施例中的内容，此处不再赘述。
图10为本公开实施例提供显示基板的制备方法的一种流程图，如图10所示，该显示基板制备方法包括：
步骤S101、在衬底基板的一侧形成第一晶体管层。
其中，第一晶体管层包括第一有源层，第一有源层的材料包括低温多晶硅材料，第一有源层包括至少一个第一沟道区和至少一个第一源漏掺杂区。
步骤S102、在第一晶体管层远离衬底基板的一侧形成第二晶体管层。
其中，第一晶体管层包括第二有源层，第一有源层与第二有源层之间设置有至少一层绝缘层，第二有源层的材料包括低温多晶硅材料，第二有源层包括至少一个第二沟道区和至少一个第二源漏掺杂区，其中至少一个第二源漏掺杂区在衬底基板上的正投影与至少一个第一源漏掺杂区在衬底基板上的正投影存在交叠，至少一个第二源漏掺杂区通过填充于绝缘层上第一过孔内的连接部与对应的第一源漏掺杂区相连。
在本公开实施例中，两个晶体管层结构的层叠设计且两个晶体管层结构内的有源层存在交叠，即像素驱动电路内的晶体管可以根据需要分布于两个晶体管层结构内，且像素驱动电路内的至少两个晶体管的源漏掺杂区会存在在垂直衬底基板的方向存在交叠，通过该设计可使得像素驱动电路在平行于衬底基板的平面上所占用面积减小。
图11为本公开实施例提供的显示基板的制备方法的另一种流程图，图12A～12N为采用图11所示制备方法制备显示基板的中间产品截面示意图，如图11至图12N所示，该制备方法可用于制备图4中所示显示基板，该制备方法包括：
步骤S201、在衬底基板的一侧形成第一缓冲层。
其中，第一缓冲层21的材料可包括氧化硅和氮化硅中至少之一。
步骤S202、在第一缓冲层远离衬底基板的一侧形成第一多晶硅材 料薄膜，并对第一多晶硅材料薄膜进行图形化，得到第一多晶硅图形。
参见图12A所示，在步骤S202中，首先在第一缓冲层21远离衬底基板1的一侧形成非晶硅材料薄膜，厚度为
Figure PCTCN2022074526-appb-000005
然后对非晶硅材料薄膜依次进行脱氢处理和ELA激光晶化处理，以使得非晶硅材料薄膜转变为多晶硅材料薄膜；接着采用图形化工艺对多晶硅材料薄膜进行图形化，以得到第一多晶硅图形2a。
步骤S203、在第一多晶硅图形远离衬底基板的一侧形成第一栅绝缘层。
步骤S204、在第一栅绝缘层远离衬底基板的一侧形成第一导电层。
参见图12B所示，第一导电层6包括位于第一晶体管层的各晶体管的栅极g；当然，第一导电层6内还可以包括其他导电结构，例如电容C的第一端板c1、栅线(未示出)、发光控制信号线(未示出)和复位控制信号线(未示出)等。可选地，第一导电层6的材料可以为金属材料(例如钼、铝、银、铜、钛、铂、钨等)、金属合金等导电材料，可以根据实际要求选择。
步骤S205、以第一导电层作为掺杂用掩模，对第一多晶硅图形进行离子注入处理。
参见图12B和12C所示，第一多晶硅图形2a上未被第一导电层6所遮挡的部分导体化作为第一源漏掺杂区202，第一多晶硅图形2a上被第一导电层6遮挡的部分作为第一沟道区201，从而得到第一有源层2。
在本公开实施例中，以第一导电层6作为掺杂用掩模对第一多晶硅图形2a进行离子注入处理，因而无需额外制备掺杂用掩模，可有效缩短生产周期、降低生产成本。
步骤S206、在第一导电层远离衬底基板的一侧形成第二栅绝缘层。
步骤S207、在第二栅绝缘层远离衬底基板的一侧形成第二导电层。
参见图12D所示，第二导电层8可包括电容C的第二端板c2、屏蔽电极图形801、复位电压传输线(未示出)等。第二导电层8的材 料可以为金属材料、金属合金等导电材料。
步骤S208、在第二导电层远离衬底基板的一侧形成第二缓冲层。
参见图12E所示，首先在第二导电层8远离衬底基板1的一侧形成第二缓冲材料薄膜，然后通过图形化工艺对第二缓冲材料薄膜、第二栅绝缘层7、第一栅绝缘层5进行图形化处理，形成所需的第一过孔401。
其中，第二缓冲层22的材料可包括氧化硅、氮化硅、氧化铝中至少之一。在一些实施例中，第二缓冲层22的厚度为：
Figure PCTCN2022074526-appb-000006
在本公开实施例中，第二缓冲层22的设置可有效提升后续制备第二有源层过程中的结晶效果。
步骤S209、在第二缓冲层远离衬底基板的一侧形成第二多晶硅材料薄膜，并对第二多晶硅材料薄膜进行图形化，得到第二多晶硅图形。
参见图12F所示，在步骤S202中，首先在第二缓冲层22远离衬底基板1的一侧形成非晶硅材料薄膜；然后对非晶硅材料薄膜依次进行脱氢处理和ELA激光晶化处理，以使得非晶硅材料薄膜转变为多晶硅材料薄膜；接着采用图形化工艺对多晶硅材料薄膜进行图形化，以得到第二多晶硅图形3a，第二多晶硅图形3a填充第一过孔401。
步骤S210、在第二多晶硅图形远离衬底基板的一侧形成第三栅绝缘层。
步骤S211、在第三栅绝远离衬底基板的一侧形成第三导电层。
参见图12G所示，第三导电层10包括位于第二晶体管层的各晶体管的栅极g；当然，第三导电层10内还可以包括其他导电结构，例如栅线(未示出)、发光控制信号线(未示出)和复位控制信号线(未示出)等。可选地，第三导电层10的材料可以为金属材料、金属合金等导电材料。
步骤S212、以第三导电层作为掺杂用掩模，对第二多晶硅图形进行离子注入处理。
参见图12G和图12H所示，第二多晶硅图形3a上未被第三导电 层10所覆盖的部分导体化作为第二源漏掺杂区302和连接部302a，第二多晶硅图形3a上被第三导电层10覆盖的部分作为第二沟道区301，从而得到第一有源层2。
在本公开实施例中，以第三导电层10作为掺杂用掩模对第二多晶硅图形3a进行离子注入处理，因而无需额外制备掺杂用掩模，可有效缩短生产周期、降低生产成本。
在一些实施例中，考虑到第二多晶硅图形3a位于过孔内的部分具有较厚厚度，为保证第二多晶硅图形3a位于过孔内的部分的导电性，可采用多次离子注入工艺进行离子注入处理，以使得第二多晶硅图形3a位于第一过孔内的部分在被导体化后所形成的连接部302a，其在沿垂直于衬底基板1的方向上具有至少2个掺杂浓度中心。具体地，可通过改变离子注入的离子束能量来调整离子注入的深度；一般地，在不考虑其他因素的情况下，离子束能量越高，则离子注入的深度越深，所形成的掺杂浓度中心也越深。
可选地，在进行离子注入处理过程中，离子注入的离子束能量为5KeV～90KeV，例如5KeV、15KeV、25KeV、35KeV、45KeV、55KeV、65KeV、75KeV、85KeV、90KeV；离子注入的离子束剂量为1017/cm2～1022/cm2，例如1017/cm2、1018/cm2、1019/cm2、1020/cm2、1021/cm2、1022/cm2。
步骤S213、在第三导电层远离衬底基板的一侧形成层间介质层。
参见图12I所示，首先形成层间介质材料薄膜，然后对层间介质材料薄膜进行图形化，以在所设计位置形成能够连通至对应结构(例如某些晶体管的栅极、源漏掺杂区等)的第二过孔402，并得到层间介质层11的图形。
步骤S214、在层间介质层远离衬底基板的一侧形成第四导电层。
参见图12J所示，第四导电层12包括数据线(未示出)和导电连接结构P。当然，第四导电层12内还可以包括其他导电结构，例如工作电压传输线(未示出)等。可选地，第四导电层12的材料可以为金属材料、金属合金等导电材料，可以根据实际要求选择
步骤S215、在第四导电层远离衬底基板的一侧形成平坦化层。
参见图12K所示，首先形成平坦化材料薄膜，然后通过图形化工艺对平坦化材料薄膜进行图形化，得到平坦化层13。其中，平坦化层13的材料可以为有机树脂材料，厚度为1μm～3μm。
步骤S216、在平坦化层远离衬底基板的形成第一电极层。
参见图12L所示，第一电极层包括第一电极14。可选地，第一电极层的材料可以为金属材料、金属合金等导电材料，可以根据实际要求选择。
步骤S217、在第一电极层远离衬底基板的一侧形成第一像素界定层和隔离坝。
参见图12M所示，第一像素界定层15上形成第一像素容纳孔。其中，第一像素界定层15的材料可以为有机树脂材料，厚度为1μm～3μm。
隔离坝18设置在相邻像素开口之间，隔离坝18用于在向像素开口内沉积发光图形的工序中支撑掩膜版以及避免出现混色的问题。
步骤S218、在第一像素容纳孔内形成电致发光图形。
参见图12N所示，发光图形位于对应的第一像素容纳孔内；其中，电致发光图形16的材料可以为有机发光材料，也可以为量子点材料。
步骤S219、在电致发光图形远离衬底基板的一侧形成第二电极层。
参见图4所示，第二电极层包括第二电极17，第二电极17为面状电极。其中，第二电极17的材料可以为透明导电材料，例如氧化铟锡、氧化铟镓锌等。
图13为本公开实施例提供的显示基板的制备方法的又一种流程图，图14A～图14B为采用图案化光刻胶层进行离子注入处理的一种截面示意图，如图13所示，图13所提供的流程图包括图12中的步骤S201～步骤S209、新增步骤S209a、新增步骤S209b、图12中的步骤S210、步骤S211、步骤S213～步骤S219。对于步骤S201～步骤S209、步骤S210、步骤S211、步骤S213～步骤S219的具体描述，可参见前 面对图12所示流程图的描述内容，此处不再赘述。下面仅对新增步骤S209a和新增步骤S209b进行详细描述。
步骤S209a、在第二多晶硅图形远离第二多晶硅图形的一侧形成图形化光刻胶层。
参见图14A所示，首先在第二多晶硅图形3a远离第二多晶硅图形3a的一侧涂覆光刻胶层，然后通过曝光、掩模、显影工艺对光刻胶层进行图形化，以得到图形化光刻胶层40；其中，图形化光刻胶层40覆盖后续待形成第二沟道区的区域且露出后续待形成第二源漏掺杂区和连接部的区域。
需要说明的是，本公开实施例中的光刻胶层所采用的光刻胶可以为正性光刻胶，也可以为负性光刻胶，本公开对此不做限定。
步骤S209b、以图形化光刻胶层作为掺杂用掩模，对第二多晶硅图形3a进行离子注入处理。
参见图14A和图14B所示，在离子注入处理过程中，第二多晶硅图形3a上未被图形化光刻胶层所覆盖的部分被导体化作为第二源漏掺杂区302和连接不302a，第二多晶硅图形3a上被图形化光刻胶层覆盖的部分作为第二沟道区301，得到第二有源层3。在完成第二有源层3的制备后，通过剥离工艺将图形化光刻胶层40剥离。
在一些实施例中，考虑到第二多晶硅图形3a位于过孔内的部分具有较厚厚度，为保证第二多晶硅图形3a位于过孔内的部分的导电性，可采用多次离子注入工艺进行离子注入处理，以使得第二多晶硅图形3a位于第一过孔401内的部分被导体化后所形成的连接部302a，其在沿垂直于衬底基板1的方向上具有至少2个掺杂浓度中心。对于可采用多次离子注入工艺进行离子注入处理的相关描述，可参见前面实施例中的内容，此处不再赘述。
需要说明的是，在本公开实施例中在制备第一有源层2时，也可以不使用第一导电层6作为掺杂用掩模进行离子注入，而是采用如步骤S209a和步骤S209b所示的利用图形化光刻胶层作为掺杂用掩模进行离子注入。
基于同一发明构思，本公开实施例还提供了一种显示装置，该显示装置包括上述任一实施例中的显示基板。需要说明的是，本实施例提供的显示装置可以为：柔性可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
进一步地，显示装置还可以包括多种类型的显示装置，例如液晶显示装置、有机电致发光显示装置(例如OLED显示装置、QLED显示装置、QD-OLED显示装置)，在此不做限定。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (30)

  1. 一种显示基板，包括：衬底基板和沿远离衬底基板的方向依次设置的第一晶体管层和第二晶体管层，所述第一晶体管层包括第一有源层，所述第二晶体管层包括第二有源层，所述第一有源层与所述第二有源层之间设置有至少一层绝缘层；
    所述第一有源层和所述第二有源层的材料均包括低温多晶硅材料，所述第一有源层包括至少一个第一沟道区和至少一个第一源漏掺杂区，所述第二有源层包括至少一个第二沟道区和至少一个第二源漏掺杂区，至少一个所述第二源漏掺杂区在所述衬底基板上的正投影与至少一个所述第一源漏掺杂区在所述衬底基板上的正投影存在交叠；
    至少一个所述第二源漏掺杂区通过填充于所述绝缘层上第一过孔内的连接部与对应的所述第一源漏掺杂区相连。
  2. 根据权利要求1所述的显示基板，其特征在于，所述连接部的材料包括至少两种不同结晶度的硅和导体化用掺杂离子。
  3. 根据权利要求2所述的显示基板，其中，所述至少两种不同结晶度的硅包括：非晶硅和多晶硅。
  4. 根据权利要求2所述的显示基板，其中，所述连接部在沿垂直于所述衬底基板的方向上具有至少2个掺杂浓度中心。
  5. 根据权利要求1至4中任一所述的显示基板，其中，所述第一过孔的坡度角为30°～75°。
  6. 根据权利要求1所述的显示基板，其中，至少一个所述第一沟 道区在所述衬底基板上的正投影与至少一个所述第二沟道区在所述衬底基板上的正投影存在交叠。
  7. 根据权利要求6所述的显示基板，其中，所述第一有源层和所述第二有源层之间设置有屏蔽电极图形；
    所述屏蔽电极图形在所述衬底基板上的正投影，覆盖所述第一沟道区和所述第二沟道区二者在所述衬底基板上正投影相交叠的区域。
  8. 根据权利要求1至7中任一所述的显示基板，其中，所述第一晶体管层还包括：
    第一栅绝缘层，位于所述第一有源层远离所述衬底基板的一侧；
    第一导电层，位于所述第一栅绝缘层远离所述衬底基板的一侧，所述第一导电层包括位于所述第一晶体管层的各晶体管与所述第一沟道区相对应的栅极。
  9. 根据权利要求8所述的显示基板，其中，所述第一导电层还包括：电容的第一端板；
    所述第一晶体管层还包括：
    第二栅绝缘层，位于所述第一导电层远离所述衬底基板的一侧
    第二导电层，位于所述第二栅绝缘层远离所述衬底基板的一侧，所述第二导电层包括与所述电容的第一端板相对设置的第二端板。
  10. 根据权利要求9所述的显示基板，其中，在所述第一有源层和所述第二有源层之间设置有屏蔽电极图形时，所述屏蔽电极图形位于所述第二导电层。
  11. 根据权利要求1至9中任一所述的显示基板，其中，所述第 二晶体管层还包括：
    第二缓冲层，位于所述第二有源层靠近所述衬底基板的一侧且与所述第二有源层相接触。
  12. 根据权利要求11所述的显示基板，其中，所述第二缓冲层的厚度为：
    Figure PCTCN2022074526-appb-100001
  13. 根据权利要求1至12中任一所述的显示基板，其中，所述第二晶体管层还包括：
    第三栅绝缘层，位于所述第二有源层远离所述衬底基板的一侧；
    第三导电层，位于所述第三绝缘层远离所述衬底基板的一侧，所述第三导电层包括位于所述第二晶体管层的各晶体管与所述第二沟道区相对应的栅极。
  14. 根据权利要求1至13中任一所述的显示基板，其中，所述显示基板还包括：
    层间介质层，位于所述第二晶体管层远离所述衬底基板的一侧；
    第四导电层，位于所述层间介质层远离所述衬底基板的一侧，所述第四导电层包括：数据线和导电连接结构，所述导电连接结构通过过孔连接至所述第一源漏掺杂区或所述第二源漏掺杂区。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板还包括：
    平坦化层，位于所述第四导电层远离所述衬底基板的一侧；
    第一电极层，位于所述平坦化层远离所述衬底基板的一侧，所述第一电极层包括多个第一电极，所述第一电极通过过孔连接至对应的所述导电连接结构以与对应的所述第一源漏掺杂区或所述第二源漏掺 杂区电连接；
    第一像素界定层，位于所述第一电极层远离所述衬底基板的一侧，所述第一像素界定层上形成有多个第一像素容纳孔，所述第一像素容纳孔连通至对应的所述第一电极；
    发光层，包括多个电致发光图形，所述电致发光图形位于对应的所述第一像素容纳孔内；
    第二电极层，位于所述第一像素界定层远离所述衬底基板的一侧。
  16. 根据权利要求15所述的显示基板，其中，所述电致发光图形的材料包括：有机发光材料或量子点材料。
  17. 根据权利要求15或16所述的显示基板，其中，所述显示基板还包括：
    封装层，位于所述第二电极层远离所述衬底基板的一侧；
    色阻层，位于所述封装层远离所述衬底基板的一侧，所述色阻层包括与所述电致发光图形一一对应的多个色阻图形。
  18. 根据权利要求17所述的显示基板，其中，所述电致发光图形的材料包括有机发光材料，所述显示基板还包括：
    所述光转换层，位于所述封装层和所述色阻层之间，所述光转换层包括与至少部分所述电致发光图形一一对应的多个光转换彩膜；
    所述光转换彩膜的材料包括量子点材料。
  19. 根据权利要求1至18所述的显示基板，其中，所述显示基板包括位于所述衬底基板上的多个像素单元，所述像素单元包括发光元件和用于驱动所述发光元件的像素驱动电路；
    所述像素驱动电路包括：驱动晶体管，所述驱动晶体管配置为根 据自身的栅源电源向对应的所述发光元件输出相应的驱动电流。
  20. 根据权利要求19所述的显示基板，其中，所述驱动晶体管位于所述第一晶体管层，所述驱动晶体管的沟道区和源漏掺杂区位于所述第一有源层。
  21. 根据权利要求19或20所述的显示基板，其中，所述像素驱动电路还包括：数据写入晶体管、阈值补偿晶体管、第一复位晶体管、第二复位晶体管、第一发光控制晶体管、第二发光控制晶体管和电容；
    所述数据写入晶体管的栅极与对应的栅线电连接，所述数据写入晶体管的第一极与对应的数据线电连接，所述数据写入晶体管的第二极与驱动晶体管的第一极电连接；
    所述阈值补偿晶体管的栅极与对应的栅线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述第一复位晶体管的栅极与对应的复位控制信号线电连接，所述第一复位晶体管的第一极与复位电压传输线电连接，所述第一复位晶体管的第二极与驱动晶体管的栅极电连接；
    所述第二复位晶体管的栅极与对应的复位控制信号线或栅线电连接，第二复位晶体管的第一极与复位电压传输线电连接，第二复位晶体管的第二极与所述发光元件的第一电极电连接；
    所述第一发光控制晶体管的栅极与发光控制信号线电连接，所述第一发光控制晶体管的第一极与工作电压传输线电连接，所述第一发光控制晶体管的第二极与驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与发光控制信号线电连接，所述第二发光控制晶体管的第一极与驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件的第一电极电连接；
    所述电容的第一端板与所述驱动晶体管的栅极连接，所述电容的 第二端板与所述工作电压传输线连接。
  22. 根据权利要求21所述的显示基板，其中，所述数据写入晶体管位于所述第一晶体管层，所述数据写入晶体管的沟道区和源漏掺杂区位于第一有源层；
    所述阈值补偿晶体管位于所述第一晶体管层，所述阈值补偿晶体管的沟道区和源漏掺杂区位于所述第一有源层；
    所述第一复位晶体管位于所述第一晶体管层，所述第一复位晶体管的沟道区和源漏掺杂区位于所述第一有源层；
    所述第二复位晶体管位于所述第二晶体管层，所述第二复位晶体管的沟道区和源漏掺杂区位于所述第二有源层；
    所述第一发光控制晶体管位于所述第二晶体管层，所述第一发光控制晶体管的沟道区和源漏掺杂区位于所述第二有源层；
    所述第二发光控制晶体管位于所述第二晶体管层，所述第二发光控制晶体管的沟道区和源漏掺杂区位于所述第二有源层。
  23. 一种显示装置，其中，包括：如上述权利要求1至22中任一所述显示基板。
  24. 一种显示基板的制备方法，其中，所述显示基板为权利要求1至22中任一所述显示基板，所述制备方法包括：
    在衬底基板的一侧形成第一晶体管层，所述第一晶体管层包括第一有源层，所述第一有源层的材料包括低温多晶硅材料，所述第一有源层包括至少一个第一沟道区和至少一个第一源漏掺杂区；
    在所述第一晶体管层远离衬底基板的一侧形成第二晶体管层，所述第一晶体管层包括第二有源层，所述第一有源层与所述第二有源层之间设置有至少一层绝缘层，所述第二有源层的材料包括低温多晶硅材料，所述第二有源层包括至少一个第二沟道区和至少一个第二源漏 掺杂区，至少一个所述第二源漏掺杂区在所述衬底基板上的正投影与至少一个所述第一源漏掺杂区在所述衬底基板上的正投影存在交叠，至少一个所述第二源漏掺杂区通过填充于所述绝缘层上第一过孔内的连接部与对应的所述第一源漏掺杂区相连。
  25. 根据权利要求24所述的制备方法，其中，所述形成第一晶体管层的步骤包括：
    在衬底基板的一侧形成第一多晶硅材料薄膜，并对所述第一多晶硅材料薄膜进行图形化，得到第一多晶硅图形；
    在所述第一多晶硅图形远离所述衬底基板的一侧形成第一栅绝缘层；
    在所述第一栅绝缘层远离所述衬底基板的一侧形成第一导电层，所述第一导电层包括位于所述第一晶体管层的各晶体管的栅极；
    以所述第一导电层作为掺杂用掩模，对所述第一多晶硅图形进行离子注入处理，所述第一多晶硅图形上未被所述第一导电层所遮挡的部分导体化作为所述第一源漏掺杂区，所述第一多晶硅图形上被所述第一导电层遮挡的部分作为第一沟道区。
  26. 根据权利要求24所述的制备方法，其中，所述形成第二晶体管层的步骤包括：
    在所述第一晶体管层远离衬底基板的一侧形成第二多晶硅材料薄膜，并对所述第二多晶硅材料薄膜进行图形化，得到第二多晶硅图形，所述第二多晶硅图形填充所述第一过孔；
    在所述第二多晶硅图形远离所述衬底基板的一侧形成第三栅绝缘层；
    在所述第三栅绝缘层远离所述衬底基板的一侧形成第三导电层，所述第三导电层包括位于所述第二晶体管层的各晶体管的栅极；
    以所述第三导电层作为掺杂用掩模，对所述第二多晶硅图形进行 离子注入处理，所述第二多晶硅图形上未被所述第三导电层所覆盖的部分导体化作为所述第二源漏掺杂区和所述连接部，所述第二多晶硅图形上被所述第三导电层覆盖的部分作为第二沟道区。
  27. 根据权利要求24所述的制备方法，其特征在于，所述形成第二晶体管层的步骤包括：
    在所述第一晶体管层远离衬底基板的一侧形成第二多晶硅材料薄膜，并对所述第二多晶硅材料薄膜进行图形化，得到第二多晶硅图形，所述第二多晶硅图形填充所述第一过孔；
    在所述第二多晶硅图形远离所述第二多晶硅图形的一侧形成图形化光刻胶层，所述图形化光刻胶层覆盖后续待形成所述第二沟道区的区域且露出后续待形成所述第二源漏掺杂区和所述连接部的区域；
    以所述图形化光刻胶层作为掺杂用掩模，对所述第二多晶硅图形进行离子注入处理，所述第二多晶硅图形上未被所述图形化光刻胶层所覆盖的部分被导体化作为所述第二源漏掺杂区和所述连接部，所述第二多晶硅图形上被所述图形化光刻胶层覆盖的部分作为第二沟道区。
  28. 根据权利要求26或27所述的制备方法，其中，对所述第二多晶硅图形进行离子注入处理的步骤包括：
    采用多次离子注入工艺进行离子注入处理，以使得所述第二多晶硅图形填充于所述第一过孔内的部分被导体化形成所述连接部，且所述连接部在沿垂直于所述衬底基板的方向上具有至少2个掺杂浓度中心。
  29. 根据权利要求28所述的制备方法，其中，所述离子注入的离子束能量为5KeV～90KeV；
    所述离子注入的离子束剂量为1017/cm2～1022/cm2。
  30. 根据权利要求26至29中任一所述的制备方法，其特征在于，在所述第一晶体管层远离衬底基板的一侧形成第二多晶硅材料薄膜的步骤之前，还包括：
    在所述第一晶体管层远离衬底基板的一侧形成第二缓冲层，所述第二缓冲层的厚度为：
    Figure PCTCN2022074526-appb-100002
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6614054B1 (en) * 2000-11-27 2003-09-02 Lg.Philips Lcd Co., Ltd. Polysilicon thin film transistor used in a liquid crystal display and the fabricating method
CN110211974A (zh) * 2019-06-12 2019-09-06 厦门天马微电子有限公司 一种阵列基板、显示面板及阵列基板的制造方法
CN111863837A (zh) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6614054B1 (en) * 2000-11-27 2003-09-02 Lg.Philips Lcd Co., Ltd. Polysilicon thin film transistor used in a liquid crystal display and the fabricating method
CN110211974A (zh) * 2019-06-12 2019-09-06 厦门天马微电子有限公司 一种阵列基板、显示面板及阵列基板的制造方法
CN111863837A (zh) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板

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