WO2023134016A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023134016A1
WO2023134016A1 PCT/CN2022/082243 CN2022082243W WO2023134016A1 WO 2023134016 A1 WO2023134016 A1 WO 2023134016A1 CN 2022082243 W CN2022082243 W CN 2022082243W WO 2023134016 A1 WO2023134016 A1 WO 2023134016A1
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Prior art keywords
peltier effect
temperature
substrate
type well
well region
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PCT/CN2022/082243
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English (en)
French (fr)
Inventor
章恒嘉
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长鑫存储技术有限公司
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Publication of WO2023134016A1 publication Critical patent/WO2023134016A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D23/00—Control of temperature
    • G05D23/19—Control of temperature characterised by the use of electric means
    • G05D23/20—Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
  • the P or N-type bottom is mainly formed on the wafer through ion implantation, and then various devices are formed, such as all circuits of dynamic random access memory (DRAM) are prepared on the wafer of.
  • Cell retention time Retention Time refers to the length of time that a storage device can keep data relatively intact. It is an important process parameter of a storage device. The length of cell retention time directly affects the reliability of a storage device. How to prolong the storage device Cell retention time becomes an urgent problem to be solved.
  • a semiconductor structure and a method of fabricating the same are provided.
  • one aspect of the present disclosure provides a method for fabricating a semiconductor structure, including:
  • the first surface of the substrate is formed with a semiconductor device
  • the Peltier effect device is used to reduce the temperature of the semiconductor device, the second surface is opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface, The exothermic end of the Peltier effect device is away from the first surface.
  • a plurality of semiconductor devices are formed on the first surface of the substrate, and a plurality of Peltier effect devices are formed on the second surface of the substrate, and the plurality of Peltier effect devices correspond to the plurality of semiconductor devices one by one, wherein, At least part of the Peltier effect device is located within the substrate.
  • the method for preparing a semiconductor structure further includes:
  • a temperature control circuit is formed on the surface of the Peltier effect device close to the first surface, which is used to detect the actual device temperature of the semiconductor device, and control the opening and closing of the Peltier effect device according to the actual device temperature.
  • the method for preparing a semiconductor structure further includes:
  • a selection circuit is formed on the surface of the Peltier effect device close to the first surface, the selection circuit is electrically connected to the Peltier effect device, and the selection circuit is configured to control the opening and closing of the Peltier effect device in different regions according to the actual device temperature .
  • the semiconductor device includes a memory chip, the memory chip includes a plurality of memory modules, and the Peltier effect devices are arranged correspondingly to the memory modules.
  • the temperature control circuit is used to detect the actual module temperature of the storage module, and control the turn-on and turn-off of the Peltier effect device according to the actual module temperature.
  • the storage module includes multiple storage arrays, and the Peltier effect devices are arranged corresponding to the storage arrays.
  • the temperature control circuit is used to detect the actual array temperature of the memory array, and control the turn on and turn off of the Peltier effect device according to the actual array temperature.
  • Peltier device group several adjacent Peltier effect devices corresponding to the same storage array are called a Peltier device group, and the signal control line of the temperature control circuit is located between adjacent Peltier device groups to control Turning on and off of Peltier effect devices in a Peltier device group.
  • the Peltier effect devices in the Peltier device group are uniformly arranged, hexagonally arranged, or arranged densely on the outside and sparsely on the inside.
  • At least two Peltier effect devices are connected in series or at least two Peltier effect devices are connected in parallel.
  • forming a Peltier effect device on the second surface of the substrate includes:
  • N-type well region and a P-type well region in the substrate are respectively formed on the second surface of the substrate;
  • a trench is formed between the N-type well region and the P-type well region, and the depth of the trench is equal to the implantation depth of the N-type well region and the P-type well region;
  • first metal layer whose top is higher than the second surface, and the first metal layer is respectively in contact with the N-type well region and the P-type well region;
  • An insulating layer is formed on the upper surface of the first metal layer, and the upper surface of the insulating layer is flush with the second surface;
  • the second metal layer is formed on the upper surface of the N-type well region, and the third metal layer is formed on the upper surface of the P-type well region.
  • the second metal layer is used for connecting the power supply voltage, and the third metal layer is used for connecting the control voltage.
  • another aspect of the present disclosure discloses a semiconductor structure comprising:
  • the semiconductor device is formed on the first surface of the substrate.
  • the Peltier effect device is located on the second surface of the substrate.
  • the Peltier effect device is used to reduce the temperature of the semiconductor device.
  • the second surface is opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface.
  • the exothermic end of the Peltier effect device is away from the first surface.
  • a plurality of semiconductor devices are formed on the first surface of the substrate, and a plurality of Peltier effect devices are formed on the second surface of the substrate, and the plurality of Peltier effect devices correspond to the plurality of semiconductor devices one by one, wherein, At least part of the Peltier effect device is located within the substrate.
  • the semiconductor structure further comprises:
  • the temperature control circuit located on the surface of the Peltier effect device close to the first surface, is used to detect the actual device temperature of the semiconductor device, and control the opening and closing of the Peltier effect device according to the actual device temperature.
  • the semiconductor structure further comprises:
  • the selection circuit is located on the surface of the Peltier effect device close to the first surface, the selection circuit is electrically connected to the Peltier effect device, and the selection circuit is configured to control the opening and closing of the Peltier effect device in different regions according to the actual device temperature .
  • the semiconductor device includes a memory chip, the memory chip includes a plurality of memory modules, and the Peltier effect devices are arranged correspondingly to the memory modules.
  • the temperature control circuit is used to detect the actual module temperature of the storage module, and control the turn-on and turn-off of the Peltier effect device according to the actual module temperature.
  • the storage module includes a plurality of storage arrays, and the Peltier effect devices are arranged correspondingly to the storage arrays; the temperature control circuit is used to detect the actual array temperature of the storage array, and control the Peltier effect according to the actual array temperature Turn on and turn off the effect device.
  • Peltier device group several adjacent Peltier effect devices corresponding to the same storage array are called a Peltier device group, and the signal control line of the temperature control circuit is located between adjacent Peltier device groups to control Turning on and off of Peltier effect devices in a Peltier device group.
  • the Peltier effect devices in the Peltier device group are uniformly arranged, hexagonally arranged, or arranged densely on the outside and sparsely on the inside.
  • At least two Peltier effect devices are connected in series or at least two Peltier effect devices are connected in parallel.
  • the Peltier effect device comprises:
  • An N-type well region is located in the substrate, and the N-type well region is close to the second surface of the substrate;
  • the P-type well region is located in the substrate, and the P-type well region is close to the second surface of the substrate;
  • the first metal layer is located between the N-type well region and the P-type well region, and is in contact with the N-type well region and the P-type well region, and the bottom of the first metal layer is in contact with the bottom of the N-type well region and the P-type well region. are flush with each other, and the top of the first metal layer is lower than the second surface;
  • the insulating layer is located on the upper surface of the first metal layer, and the upper surface of the insulating layer is flush with the second surface;
  • the second metal layer is located on the upper surface of the N-type well region and is used for connecting the power supply voltage
  • the third metal layer is located on the upper surface of the P-type well region and is used for connecting the control voltage.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • a semiconductor device is formed on the first surface of the substrate, a Peltier effect device is formed on the second surface opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface, The heat release end of the Peltier effect device is far away from the first surface, and the temperature of the semiconductor device can be reduced through the Peltier effect device, thereby eliminating the influence of the temperature generated during the working process of the semiconductor structure on the performance of the semiconductor structure.
  • the semiconductor structure is a storage device, the influence of temperature on the cell storage time is eliminated, the cell storage time of the semiconductor structure is prolonged, the risk of storage failure is reduced, and the reliability of the semiconductor structure is improved.
  • a semiconductor device is formed on the first surface of the substrate, a Peltier effect device is formed on the second surface opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface, and the Peltier effect device
  • the exothermic end of the patch effect device is far away from the first surface, and the temperature of the semiconductor device can be reduced through the Peltier effect device, thereby eliminating the influence of the temperature generated during the working process of the semiconductor structure on the performance of the semiconductor structure.
  • the semiconductor structure is a storage device, the influence of temperature on the cell storage time is eliminated, the cell storage time of the semiconductor structure is prolonged, the risk of storage failure is reduced, and the reliability of the semiconductor structure is improved.
  • FIG. 1 is a schematic flow diagram of a method for preparing a semiconductor structure in an embodiment
  • FIG. 2 is a schematic cross-sectional view of the semiconductor structure in the first embodiment
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure in a second embodiment
  • FIG. 4 is a schematic cross-sectional view of a semiconductor structure in a third embodiment
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure in a fourth embodiment
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure in a fifth embodiment
  • FIG. 7 is a schematic top view of the storage array in the first embodiment
  • FIG. 8 is a schematic top view of the storage array in the second embodiment
  • FIG. 9 is a schematic top view of the storage array in the third embodiment.
  • Fig. 10 is a schematic flow chart of forming a Peltier effect device in an embodiment
  • FIG. 11 is a schematic cross-sectional view of a semiconductor structure after trench formation in an embodiment
  • FIG. 12 is a schematic cross-sectional view of the semiconductor structure after forming the first metal layer in an embodiment corresponding to FIG. 11;
  • FIG. 13 is a schematic cross-sectional view of a semiconductor structure after forming an insulating layer in an embodiment corresponding to FIG. 12;
  • FIG. 14 is a schematic cross-sectional view of the semiconductor structure after step S210 in an embodiment corresponding to FIG. 13 .
  • first, second, etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • a first side could be termed a second side, and, similarly, a second side could be termed a first side, without departing from the scope of the present disclosure.
  • Both the first side and the second side are surfaces of the substrate, but they are not the same surface of the substrate.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • plural means at least two, such as two, three, etc., unless otherwise specifically defined.
  • severeal means at least one, such as one, two, etc., unless otherwise specifically defined.
  • the cell retention time refers to the length of time that the storage device can keep data intact, and is an important process parameter of the storage device. The shorter the cell retention time, the higher the risk of failure of the storage device to save data, and the higher the reliability of the storage device. How to prolong the cell storage time of the storage device and reduce the risk of data storage failure of the storage device has become an urgent problem to be solved.
  • FIG. 1 is a schematic flow diagram of a method for preparing a semiconductor structure in an embodiment. As shown in FIG. 1 , in an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, including:
  • a substrate is provided, and a semiconductor device is formed on a first surface of the substrate, that is, a device layer of a semiconductor device is formed on the first surface of the substrate.
  • the substrate can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), on insulator Silicon germanium (SiGeOI) and germanium on insulator (GeOI), etc.
  • SOI silicon on insulator
  • SSOI silicon on insulator
  • S-SiGeOI silicon germanium on insulator
  • SiGeOI silicon germanium
  • germanium on insulator GeOI
  • a Peltier effect device is formed on the second surface of the substrate, the second surface of the substrate is opposite to the first surface of the substrate, and the Peltier effect device has a heat absorption end and a heat release end, wherein the heat absorption end is close to On the first surface of the substrate, the heat release end is away from the first surface of the substrate, that is, the heat release end is close to the second surface of the substrate, and the temperature of the semiconductor device can be reduced through the Peltier effect device.
  • a semiconductor device is formed on the first surface of the substrate, a Peltier effect device is formed on the second surface opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface, The heat release end of the Peltier effect device is far away from the first surface, and the temperature of the semiconductor device can be reduced through the Peltier effect device, thereby eliminating the influence of the temperature generated during the working process of the semiconductor structure on the performance of the semiconductor structure.
  • the semiconductor structure is a storage device, the influence of temperature on the cell storage time is eliminated, the cell storage time of the semiconductor structure is prolonged, the risk of storage failure is reduced, and the reliability of the semiconductor structure is improved.
  • Fig. 2 is a schematic cross-sectional view of the semiconductor structure in the first embodiment.
  • a plurality of semiconductor devices 104 are formed on the first surface of the substrate 102, and a plurality of Peltier devices are formed on the second surface of the substrate 102.
  • the effect devices 106 correspond one-to-one to the plurality of Peltier effect devices 106 and the plurality of semiconductor devices 104 , wherein at least some of the Peltier effect devices 106 are located in the substrate 102 .
  • a Peltier effect device 106 is set corresponding to a semiconductor device 104. Exemplarily, as shown in FIG.
  • a Peltier effect device 1 corresponds to a semiconductor device A
  • a Peltier effect device 2 corresponds to a semiconductor device B
  • the Peltier effect device 3 corresponds to the semiconductor device C, and the temperature of the semiconductor device can be reduced by the Peltier effect device corresponding to the semiconductor device.
  • Fig. 3 is a schematic cross-sectional view of the semiconductor structure in the second embodiment.
  • the preparation method of the semiconductor structure further includes: forming a temperature control circuit 108 on the surface of the Peltier effect device 106 close to the first surface , the temperature control circuit 108 is used to detect the actual device temperature of the semiconductor device 104, and control the on and off of the Peltier effect device 106 according to the actual device temperature.
  • the temperature control circuit 106 detects the actual device temperature of the semiconductor device 104 in real time or after a certain period of time, and controls the Peltier effect device 106 to start working (open) when the actual device temperature is greater than or equal to the preset device temperature, thereby reducing
  • the device temperature of the semiconductor device 104 when the actual device temperature is less than the preset device temperature, the Peltier effect device 106 is controlled to stop working (turn off)
  • the preset device temperature refers to the critical temperature that will affect the performance of the semiconductor device
  • exemplary Yes the preset device temperature refers to the critical temperature that will affect the storage time of the memory device unit.
  • the temperature control circuit 108 can take the semiconductor device 104 as a whole, detect the overall actual device temperature of the semiconductor device 104, and then according to the overall actual device temperature The temperature controls the opening and closing of all Peltier effect devices 106. This method is simple to operate and requires less temperature data to be processed; the temperature control circuit 108 can also detect the actual device temperature of each semiconductor device 104, and then control the temperature according to the actual device temperature. The turn-on and turn-off of the Peltier effect device 106 corresponding to the semiconductor device 104 requires more temperature data to be processed, and the temperature control accuracy is higher.
  • the temperature control circuit 108 is formed on the second side of the substrate 102 flush with the Peltier effect device 106 .
  • the temperature control circuit 108 may also be formed in the substrate 102 close to the semiconductor device 104 , and the actual device temperature detected by the temperature control circuit 108 is closer to the real temperature of the semiconductor device 104 .
  • the method for preparing the semiconductor structure further includes: forming a selection circuit 110 on the surface of the Peltier effect device 106 close to the first surface, selecting The circuit 110 is electrically connected to the Peltier effect device 106, and the selection circuit 110 is configured to turn on and off the Peltier effect device 106 according to the actual device temperature.
  • the selection circuit 110 is configured to control the on and off of the Peltier effect device 106 in different regions according to the actual device temperature, through which the excessive loss of electric energy can be avoided and the purpose of saving energy can be achieved.
  • the selection circuit 110 controls the on and off of the Peltier effect device 106 corresponding to the region where the semiconductor device 104 is located according to the actual device temperature of the semiconductor device 104 .
  • the selection circuit 110 is located in a region between the Peltier effect device 106 and the temperature control circuit 108 .
  • the selection circuit 110 is located in a region between the temperature control circuit 108 and the first surface of the substrate 102 .
  • the selection circuit 110 can be formed on the second surface of the substrate 102 and be flush with the Peltier effect device 106 or lower than the second surface of the substrate 102, that is, between the selection circuit 110 and the first surface of the substrate 102 The distance between is equal to or greater than the distance between the Peltier effect device 106 and the first surface of the substrate 102 .
  • FIG. 5 is a schematic top view of the semiconductor structure in the fourth embodiment.
  • the semiconductor device 104 includes a memory chip
  • the memory chip includes a plurality of memory modules 202
  • the Peltier effect device 106 corresponds to the memory module 202 set up.
  • one semiconductor device 104 corresponds to a plurality of Peltier effect devices 106, which can accurately and rapidly lower the temperature of the memory chip.
  • the temperature control circuit 108 is used to detect the actual module temperature of the storage module 202, and control the turn-on and turn-off of the Peltier effect device 106 according to the actual module temperature. Specifically, the temperature control circuit 108 detects the actual module temperature of each storage module 202 in the memory chip, and controls the Peltier effect device corresponding to the storage module 202 when the actual module temperature of the storage module 202 is greater than or equal to the preset module temperature 106 starts to work (open), and then reduces the module temperature of storage module 202, when the actual module temperature of storage module 202 is less than preset module temperature, controls the Peltier effect device 106 corresponding to storage module 202 to stop working (turn off) , the preset module temperature refers to the critical temperature that will affect the storage time of the storage module 202 units.
  • the temperature of each memory module 202 in the memory chip can be precisely controlled, the influence of temperature on the unit storage time can be eliminated, the unit storage time of the memory chip can be prolonged, the risk of storage failure can be reduced, and the reliability of the memory chip can be improved. . At the same time, excessive loss of electric energy is avoided to achieve the purpose of saving energy.
  • FIG. 6 is a schematic top view of the semiconductor structure in the fifth embodiment.
  • the storage module 202 includes a plurality of storage arrays 204 , and the Peltier effect devices 106 are arranged corresponding to the storage arrays 204 .
  • the Peltier effect device 106 is set in one-to-one correspondence with the storage array 204, that is, one Peltier effect device 106 corresponds to one storage array 204, and the opening and closing of each Peltier effect device 106 can reduce or The temperature of the corresponding storage array 204 is not changed.
  • the temperature control circuit 108 is used to detect the actual array temperature of the storage array 204, and control the turn on and turn off of the Peltier effect device 106 according to the actual array temperature. Specifically, the temperature control circuit 108 detects the actual array temperature of each storage array 204 in the storage module 202, and controls the Peltier effect corresponding to the storage array 204 when the actual array temperature of the storage array 204 is greater than or equal to the preset array temperature The device 106 starts to work (open), and then reduces the array temperature of the storage array 204, when the actual array temperature of the storage array 204 is less than the preset array temperature, the Peltier effect device 106 corresponding to the storage array 204 is controlled to stop working (turn off ), the preset array temperature refers to the critical temperature that will affect the storage time of the storage array 204 units.
  • the temperature of each storage array 204 in the storage module 202 can be precisely controlled, the influence of the temperature on the storage time of the unit can be eliminated, the storage time of the unit of the storage module 202 can be extended, the risk of storage failure can be reduced, and the storage module 202 can be improved. reliability. At the same time, excessive loss of electric energy is avoided to achieve the purpose of saving energy.
  • FIG. 7 is a schematic top view of the storage array in the first embodiment. As shown in FIG. 7, as an example, several adjacent Peltier effect devices 106 corresponding to the same storage array 204 are called a Peltier device group 206 , through this setting, the temperature of the storage array 204 can be lowered accurately and quickly.
  • the signal control lines of the temperature control circuit 108 are located between adjacent Peltier device groups 206 to control the on and off of the Peltier effect devices 106 in the Peltier device groups 206 .
  • the temperature control circuit 108 controls each Peltier effect device 106 in the storage array 204 to be turned on and off according to the actual array temperature, and this setting eliminates the influence of the control signal transmission time difference on the temperature control.
  • the Peltier effect devices 106 in the Peltier device group 206 are uniformly arranged, and this arrangement has a simple manufacturing process and improves production efficiency.
  • Fig. 8 is a schematic top view of the storage array in the second embodiment, as shown in Fig. 8, as an example, each Peltier effect device 106 in the Peltier device group 206 is arranged in a hexagonal arrangement, and the Peltier effect device 106 can be improved by this arrangement.
  • the effect device 106 temperature controls the coverage efficiency.
  • FIG. 9 is a schematic top view of the storage array in the third embodiment.
  • the Peltier effect devices 106 in the Peltier device group 206 are arranged densely on the outside and sparsely on the inside.
  • the periphery of the storage array 204 is easily affected by temperature, and the precision of temperature control can be improved and the temperature of the storage array 204 can be lowered rapidly through the annularly distributed Peltier effect devices 106 that are denser on the outside and sparser on the inside.
  • Peltier effect devices 106 in the Peltier device group 206 are connected in series or at least two Peltier effect devices 106 are connected in parallel.
  • Fig. 10 is a schematic flow diagram of forming a Peltier effect device in an embodiment
  • Fig. 11 is a schematic cross-sectional view of a semiconductor structure after forming a trench in an embodiment
  • Fig. 12 is a schematic diagram of forming a first metal layer in an embodiment corresponding to Fig. 11
  • Figure 13 is a schematic cross-sectional view of the semiconductor structure after forming an insulating layer in an embodiment corresponding to Figure 12
  • Figure 14 is a schematic cross-sectional view of the semiconductor structure after step S210 in an embodiment corresponding to Figure 13, as shown in 10.
  • forming the Peltier effect device 106 on the second surface of the substrate 102 includes:
  • a substrate 102 is provided, and a device layer 112 (semiconductor device) is formed on the first surface of the substrate 102.
  • the method for preparing a semiconductor structure further includes: forming a solidified layer on the upper surface of the device layer 112. layer 114 , by curing the layer 114 , the influence of the external environment on the device layer 112 can be avoided.
  • the method for preparing the semiconductor structure further includes: performing thinning treatment on the second surface of the substrate 102.
  • an N-type well region 302 and a P-type well region 304 located in the substrate 102 are respectively formed on the second surface of the substrate 102 .
  • the N-type well region 302 and the P-type well region 304 may be formed by an ion implantation process. Exemplarily, the implantation depths of the N-type well region 302 and the P-type well region 304 are the same.
  • a plurality of Peltier effect devices 106 are formed on the second surface of the substrate 102, and the manufacturing method of the semiconductor structure further includes: forming an isolation structure 306 on the second surface of the substrate, and the isolation structure 306 is isolated from the second surface of the substrate 102 Several active regions arranged at intervals are formed, and Peltier effect devices 106 are formed in the active regions.
  • a trench 308 is formed between the N-type well 302 and the P-type well region 304, wherein the depth of the trench 308 is equal to the implantation depth of the N-type well region 302 and the P-type well region 304; that is, the trench 308
  • the bottoms of the N-type well region 302 and the bottom of the P-type well region are respectively flush with each other.
  • the trench 308 is filled with a first metal layer 310 whose top is higher than the second surface.
  • the first metal layer 310 is respectively in contact with the N-type well region 302 and the P-type well region 304 .
  • Layer 310 may act as a heat sink for Peltier effect device 106 .
  • the first metal layer 310 does not fill the trench 308 , that is, the distance between the first metal layer 310 and the first surface of the substrate 102 is smaller than the distance between the opening of the trench 308 and the first surface of the substrate 102 .
  • the constituent materials of the first metal layer 310 include metal materials, alloy materials, and polysilicon materials, such as metal copper, metal aluminum, metal gold, metal silver, metal titanium, metal tungsten, titanium nitride, polysilicon, and the like.
  • an insulating layer 312 is formed on the upper surface of the first metal layer 310 , and the upper surface of the insulating layer 312 is flush with the second surface; that is, the insulating layer 312 fills the trench 308 .
  • the constituent materials of the insulating layer 312 include nitrides and oxides, such as silicon nitride and silicon dioxide.
  • the second metal layer 314 is formed on the upper surface of the N-type well region 302, and the third metal layer 316 is formed on the upper surface of the P-type well region 306, the second metal layer 314 is used to connect the power supply voltage, and the third metal layer 316 is formed on the upper surface of the P-type well region 306
  • the metal layer 316 is used to connect the control voltage.
  • the second metal layer 314 and the third metal layer 316 are separated by the insulating layer 312 , and the second metal layer 314 and the third metal layer 316 can be used as heat dissipation terminals of the Peltier effect device 106 .
  • the constituent materials of the second metal layer 314 and the third metal layer 316 include metal materials, alloy materials, and polysilicon materials, such as metal copper, metal aluminum, metal gold, metal silver, metal titanium, metal tungsten, and titanium nitride. , polysilicon, etc.
  • the constituent materials of the first metal layer 310, the second metal layer 314, and the third metal layer 316 are the same.
  • steps in the flow charts of FIG. 1 and FIG. 10 are shown sequentially according to the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Fig. 1 and Fig. 10 may include a plurality of sub-steps or stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, these sub-steps or The execution order of the stages is not necessarily performed sequentially, but may be executed alternately or alternately with at least a part of other steps or substeps of other steps or stages.
  • an embodiment of the present disclosure provides a semiconductor structure, including: a substrate 102 and a Peltier effect device 106, a semiconductor device 104 is formed on the first surface of the substrate 102; the Peltier effect device 106 is located on the substrate 102 The second side, the Peltier effect device 106 is used to reduce the temperature of the semiconductor device 104, the second side is set opposite to the first side, the heat-absorbing end of the Peltier effect device 106 is close to the first side, and the Peltier effect device 106 The exothermic end is away from the first surface.
  • the semiconductor device 104 is formed on the first surface of the substrate 102 , that is, the device layer of the semiconductor device 104 is formed on the first surface of the substrate.
  • the substrate 102 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), Silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the constituent material of the substrate 102 is selected from single crystal silicon.
  • the Peltier effect device 106 is located on the second surface of the substrate, and the second surface of the substrate is opposite to the first surface of the substrate.
  • the Peltier effect device 106 has a heat absorption end and a heat release end, wherein the heat absorption end is close to the substrate 102
  • the first surface of the substrate 102 has a heat dissipation end far away from the first surface, that is, the second surface of the heat dissipation end is close to the substrate 102 , and the temperature of the semiconductor device 104 can be reduced by the Peltier effect device 106 .
  • a semiconductor device is formed on the first surface of the substrate, a Peltier effect device is formed on the second surface opposite to the first surface, and the heat-absorbing end of the Peltier effect device is close to the first surface, and the Peltier effect device
  • the exothermic end of the patch effect device is far away from the first surface, and the temperature of the semiconductor device can be reduced through the Peltier effect device, thereby eliminating the influence of the temperature generated during the working process of the semiconductor structure on the performance of the semiconductor structure.
  • the semiconductor structure is a storage device, the influence of temperature on the cell storage time is eliminated, the cell storage time of the semiconductor structure is prolonged, the risk of storage failure is reduced, and the reliability of the semiconductor structure is improved.
  • a plurality of semiconductor devices 104 are formed on the first surface of the substrate 102, and a plurality of Peltier effect devices 106 are formed on the second surface of the substrate 102, and the plurality of Peltier effect devices 106 and the plurality of semiconductor devices 106 are formed on the second surface of the substrate 102.
  • semiconductor devices 104 There is a one-to-one correspondence between semiconductor devices 104 , wherein at least some of the Peltier effect devices 106 are located in the substrate 102 .
  • a Peltier effect device 106 is set correspondingly to a semiconductor device 104. Exemplarily, as shown in FIG.
  • a Peltier effect device 1 corresponds to a semiconductor device A
  • a Peltier effect device 2 corresponds to a semiconductor device B
  • the Peltier effect device 3 corresponds to the semiconductor device C, and the temperature of the semiconductor device can be reduced by the Peltier effect device corresponding to the semiconductor device.
  • the semiconductor structure also includes:
  • the temperature control circuit 108 located on the surface of the Peltier effect device 106 close to the first surface, is used to detect the actual device temperature of the semiconductor device 104, and control the opening and closing of the Peltier effect device 106 according to the actual device temperature. Specifically, the temperature control circuit 106 detects the actual device temperature of the semiconductor device 104 in real time or after a certain period of time, and controls the Peltier effect device 106 to start working (open) when the actual device temperature is greater than or equal to the preset device temperature, thereby reducing The device temperature of the semiconductor device 104, when the actual device temperature is less than the preset device temperature, the Peltier effect device 106 is controlled to stop working (turn off), the preset device temperature refers to the critical temperature that will affect the performance of the semiconductor device, exemplary Yes, the preset device temperature refers to the critical temperature that will affect the storage time of the memory device unit.
  • the temperature control circuit 108 can take the semiconductor device 104 as a whole, detect the overall actual device temperature of the semiconductor device 104, and then according to the overall actual device temperature The temperature controls the opening and closing of all Peltier effect devices 106. This method is simple to operate and requires less temperature data to be processed; the temperature control circuit 108 can also detect the actual device temperature of each semiconductor device 104, and then control the temperature according to the actual device temperature. The turn-on and turn-off of the Peltier effect device 106 corresponding to the semiconductor device 104 requires more temperature data to be processed, and the temperature control accuracy is higher.
  • the temperature control circuit 108 is located on the second side of the substrate 102 and is flush with the Peltier effect device 106 . In other embodiments, the temperature control circuit 108 is located in the substrate 102 close to the semiconductor device 104 , and the actual device temperature detected by the temperature control circuit 108 is closer to the real temperature of the semiconductor device 104 by setting the temperature control circuit 108 .
  • the semiconductor structure further includes:
  • the selection circuit 110 is located on the surface of the Peltier effect device 106 close to the second surface, the selection circuit 110 is electrically connected to the Peltier effect device 106, and the selection circuit 110 is configured to control the Peltier effect device in different regions according to the actual device temperature 106 on and off.
  • the selection circuit 110 is configured to control the on and off of the Peltier effect device 106 in different regions according to the actual device temperature, through which the excessive loss of electric energy can be avoided and the purpose of saving energy can be achieved.
  • the selection circuit 110 controls the on and off of the Peltier effect device 106 corresponding to the region where the semiconductor device 104 is located according to the actual device temperature of the semiconductor device 104 .
  • the selection circuit 110 is located in a region between the Peltier effect device 106 and the temperature control circuit 108 .
  • the selection circuit 110 is located in a region between the temperature control circuit 108 and the first surface of the substrate 102 .
  • the selection circuit 110 is located on the second surface of the substrate 102 and is flush with the Peltier effect device 106 or lower than the second surface of the substrate 102, that is, between the selection circuit 110 and the first surface of the substrate 102 The distance is equal to or greater than the distance between the Peltier effect device 106 and the first surface of the substrate 102 .
  • the semiconductor device includes a memory chip
  • the memory chip includes a plurality of memory modules 202
  • the Peltier effect device 106 is arranged correspondingly to the memory modules 202 .
  • one semiconductor device 104 corresponds to a plurality of Peltier effect devices 106, which can accurately and rapidly lower the temperature of the memory chip.
  • the temperature control circuit 108 is used to detect the actual module temperature of the storage module 202, and control the turn-on and turn-off of the Peltier effect device 106 according to the actual module temperature. Specifically, the temperature control circuit 108 detects the actual module temperature of each storage module 202 in the memory chip, and controls the Peltier effect device corresponding to the storage module 202 when the actual module temperature of the storage module 202 is greater than or equal to the preset module temperature 106 starts to work (open), and then reduces the module temperature of storage module 202, when the actual module temperature of storage module 202 is less than preset module temperature, controls the Peltier effect device 106 corresponding to storage module 202 to stop working (turn off) , the preset module temperature refers to the critical temperature that will affect the storage time of the storage module 202 units.
  • the temperature of each memory module 202 in the memory chip can be precisely controlled, the influence of temperature on the unit storage time can be eliminated, the unit storage time of the memory chip can be prolonged, the risk of storage failure can be reduced, and the reliability of the memory chip can be improved. . At the same time, excessive loss of electric energy is avoided to achieve the purpose of saving energy.
  • the storage module 202 includes a plurality of storage arrays 204 , and the Peltier effect devices 106 are arranged corresponding to the storage arrays 204 .
  • the Peltier effect device 106 is set in one-to-one correspondence with the storage array 204, that is, one Peltier effect device 106 corresponds to one storage array 204, and the opening and closing of each Peltier effect device 106 can reduce or The temperature of the corresponding storage array 204 is not changed.
  • the temperature control circuit 108 is used to detect the actual array temperature of the storage array 204, and control the turn on and turn off of the Peltier effect device 106 according to the actual array temperature. Specifically, the temperature control circuit 108 detects the actual array temperature of each storage array 204 in the storage module 202, and controls the Peltier effect corresponding to the storage array 204 when the actual array temperature of the storage array 204 is greater than or equal to the preset array temperature The device 106 starts to work (open), and then reduces the array temperature of the storage array 204, when the actual array temperature of the storage array 204 is less than the preset array temperature, the Peltier effect device 106 corresponding to the storage array 204 is controlled to stop working (turn off ), the preset array temperature refers to the critical temperature that will affect the storage time of the storage array 204 units.
  • the temperature of each storage array 204 in the storage module 202 can be precisely controlled, the influence of the temperature on the storage time of the unit can be eliminated, the storage time of the unit of the storage module 202 can be extended, the risk of storage failure can be reduced, and the storage module 202 can be improved. reliability. At the same time, excessive loss of electric energy is avoided to achieve the purpose of saving energy.
  • Peltier device group 206 As shown in FIG. 7, as an example, several adjacent Peltier effect devices 106 corresponding to the same storage array 204 are called a Peltier device group 206, and by this setting, the storage array 204 can be accurately and quickly reduced. temperature.
  • the signal control lines of the temperature control circuit 108 are located between adjacent Peltier device groups 206 to control the on and off of the Peltier effect devices 106 in the Peltier device groups 206 .
  • the temperature control circuit 108 controls each Peltier effect device 106 in the storage array 204 to be turned on and off according to the actual array temperature, and this setting eliminates the influence of the control signal transmission time difference on the temperature control.
  • the Peltier effect devices 106 in the Peltier device group 206 are uniformly arranged, and this arrangement has a simple manufacturing process and improves production efficiency.
  • the Peltier effect devices 106 in the Peltier device group 206 are arranged in a hexagonal arrangement, through which the temperature control coverage efficiency of the Peltier effect devices 106 can be improved.
  • the Peltier effect devices 106 in the Peltier device group 206 are arranged densely on the outside and sparsely on the inside.
  • the periphery of the storage array 204 is easily affected by temperature, and the precision of temperature control can be improved and the temperature of the storage array 204 can be lowered rapidly through the annularly distributed Peltier effect devices 106 that are denser on the outside and sparser on the inside.
  • Peltier effect devices 106 in the Peltier device group 206 are connected in series or at least two Peltier effect devices 106 are connected in parallel.
  • the Peltier effect device 106 includes: an N-type well region 302, a P-type well region 304, a first metal layer 310, an insulating layer 312, a second metal layer 314 and a third metal layer 316 .
  • the N-type well region 302 is located in the substrate 102 and is close to the second surface of the substrate 102 ; the P-type well region 304 is located in the substrate 102 and the P-type well region 304 is close to the second surface of the substrate 102 .
  • a device layer 112 (semiconductor device) is formed on the first surface of the substrate 102. It can be understood that the semiconductor structure also includes: a cured layer 114, located on the upper surface of the device layer 112, which can prevent the external environment from affecting the device layer 112 by the cured layer 114. Impact. Exemplarily, the implantation depths of the N-type well region 302 and the P-type well region 304 are the same.
  • the first metal layer 310 is located between the N-type well region 302 and the P-type well region 304, and is in contact with the N-type well region 302 and the P-type well region 304, and the bottom of the first metal layer 310 is in contact with the N-type well region 302, The bottom of the P-type well region 304 is flush, and the top of the first metal layer 310 is lower than the second surface.
  • the first metal layer 310 can serve as a heat sink of the Peltier effect device 106 .
  • the first metal layer 310 does not fill the trench 308 , that is, the distance between the first metal layer 310 and the first surface of the substrate 102 is smaller than the distance between the opening of the trench 308 and the first surface of the substrate 102 .
  • the constituent materials of the first metal layer 310 include metal materials, alloy materials, and polysilicon materials, such as metal copper, metal aluminum, metal gold, metal silver, metal titanium, metal tungsten, titanium nitride, polysilicon, and the like.
  • the insulating layer 312 is located on the upper surface of the first metal layer 310 , and the upper surface of the insulating layer 312 is flush with the second surface; that is, the insulating layer 312 fills the trench 308 .
  • the constituent materials of the insulating layer 312 include nitrides and oxides, such as silicon nitride and silicon dioxide.
  • the second metal layer 314 is located on the upper surface of the N-type well region 301 and is used for connecting the power supply voltage; the third metal layer 316 is located on the upper surface of the P-type well region 304 and is used for connecting the control voltage.
  • the second metal layer 314 and the third metal layer 316 are separated by the insulating layer 312 , and the second metal layer 314 and the third metal layer 316 can be used as a heat release terminal of the Peltier effect device 106 .
  • the constituent materials of the second metal layer 314 and the third metal layer 316 include metal materials, alloy materials, and polysilicon materials, such as metal copper, metal aluminum, metal gold, metal silver, metal titanium, metal tungsten, and titanium nitride. , polysilicon, etc.
  • the constituent materials of the first metal layer 310 , the second metal layer 314 and the third metal layer 316 are the same.
  • a plurality of Peltier effect devices 106 are formed on the second surface of the substrate 102, and the semiconductor structure further includes: an isolation structure 306 located on the second surface of the substrate 102, and the isolation structure 306 isolates several The active regions are arranged at intervals, and Peltier effect devices 106 are formed in the active regions.

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Abstract

本公开涉及一种半导体结构及其制备方法。该方法包括：提供基底，基底的第一面形成有半导体器件；于基底的第二面形成帕尔贴效应器件，帕尔贴效应器件用于降低半导体器件的温度，第二面与第一面相对设置，帕尔帖效应器件的吸热端靠近第一面，帕尔帖效应器件的放热端远离第一面。通过帕尔贴效应器件可以降低半导体器件的温度，进而消除半导体结构工作过程中产生的温度对半导体结构的性能的影响。当半导体结构为存储器件时，消除温度对单元保存时间的影响，延长了半导体结构的单元保存时间，降低了保存失败的风险，提高了半导体结构的可靠性。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开要求于2022年01月17日提交中国专利局、申请号为202210047991.3的中国专利的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
在集成电路器件制作过程中，主要是在晶圆上透过离子注入形成P或N型底部，进而形成各种器件，例如动态随机存取存储器(DRAM)的所有电路都在晶圆上制备完成的。单元保存时间(Retention Time)指的是存储器件能够比较完好的保持数据的时间长度，是存储器件的一个重要工艺参数，单元保存时间的长短直接影响到存储器件的可靠性，如何延长存储器件的单元保存时间成为亟需解决的问题。
发明内容
根据本公开的各种实施例，提供一种半导体结构及其制备方法。
根据一些实施例，本公开一方面提供一种半导体结构的制备方法，包括：
提供基底，基底的第一面形成有半导体器件；及
于基底的第二面形成帕尔贴效应器件，帕尔贴效应器件用于降低半导体器件的温度，第二面与第一面相对设置，帕尔帖效应器件的吸热端靠近第一面，帕尔帖效应器件的放热端远离第一面。
根据一些实施例，基底的第一面形成有多个半导体器件，基底的第二面形成有多个帕尔贴效应器件，多个帕尔贴效应器件与多个半导体器件一一对应，其中，至少部分帕尔贴效应器件位于基底内。
根据一些实施例，半导体结构的制备方法还包括：
于帕尔贴效应器件靠近第一面的表面上形成温度控制电路，用于检测半导体器件的实 际器件温度，并根据实际器件温度控制帕尔贴效应器件的开启和关断。
根据一些实施例，半导体结构的制备方法还包括：
于帕尔贴效应器件靠近第一面的表面上形成选择电路，选择电路与帕尔贴效应器件电连接，选择电路被配置以根据实际器件温度分区域控制帕尔贴效应器件的开启和关断。
根据一些实施例，半导体器件包括存储芯片，存储芯片包括多个存储模块，帕尔贴效应器件与存储模块对应设置。
根据一些实施例，温度控制电路用于检测存储模块的实际模块温度，并根据实际模块温度控制帕尔贴效应器件的开启和关断。
根据一些实施例，存储模块包括多个存储阵列，帕尔贴效应器件与存储阵列对应设置。
根据一些实施例，温度控制电路用于检测存储阵列的实际阵列温度，并根据实际阵列温度控制帕尔贴效应器件的开启和关断。
根据一些实施例，与同一存储阵列对应的若干个相邻的帕尔贴效应器件称为一个帕尔贴器件组，温度控制电路的信号控制线位于相邻帕尔贴器件组之间，以控制帕尔贴器件组中帕尔贴效应器件的开启和关断。
根据一些实施例，帕尔贴器件组中各帕尔贴效应器件为均匀排布、六方排布或外密内疏排布。
根据一些实施例，帕尔贴器件组中各帕尔贴效应器件中至少有两个帕尔贴效应器件之间串联或至少有两个帕尔贴效应器件之间并联。
根据一些实施例，于基底的第二面形成帕尔贴效应器件包括：
于基底的第二面分别形成位于基底中的N型阱区和P型阱区；
于N型阱区P型阱区之间形成沟槽，沟槽的深度等于N型阱区和P型阱区的注入深度；
于沟槽中填充形成顶部高于第二面的第一金属层，第一金属层分别与N型阱区、P型阱区相接触；
于第一金属层的上表面形成绝缘层，绝缘层的上表面与第二面相齐平；及
分别于N型阱区的上表面形成第二金属层、于P型阱区的上表面形成第三金属层，第二金属层用于连接电源电压，第三金属层用于连接控制电压。
根据一些实施例，本公开的另一方面公开了一种半导体结构，包括：
基底，基底的第一面形成有半导体器件；及
帕尔贴效应器件，位于基底的第二面，帕尔贴效应器件用于降低半导体器件的温度，第二面与第一面相对设置，帕尔帖效应器件的吸热端靠近第一面，帕尔帖效应器件的放热 端远离第一面。
根据一些实施例，基底的第一面形成有多个半导体器件，基底的第二面形成有多个帕尔贴效应器件，多个帕尔贴效应器件与多个半导体器件一一对应，其中，至少部分帕尔贴效应器件位于基底内。
根据一些实施例，半导体结构还包括：
温度控制电路，位于帕尔贴效应器件靠近第一面的表面上，用于检测半导体器件的实际器件温度，并根据实际器件温度控制帕尔贴效应器件的开启和关断。
根据一些实施例，半导体结构还包括：
选择电路，位于帕尔贴效应器件靠近第一面的表面上，选择电路与帕尔贴效应器件电连接，选择电路被配置以根据实际器件温度分区域控制帕尔贴效应器件的开启和关断。
根据一些实施例，半导体器件包括存储芯片，存储芯片包括多个存储模块，帕尔贴效应器件与存储模块对应设置。
根据一些实施例，温度控制电路用于检测存储模块的实际模块温度，并根据实际模块温度控制帕尔贴效应器件的开启和关断。
根据一些实施例，存储模块包括多个存储阵列，帕尔贴效应器件与存储阵列对应设置；温度控制电路用于检测存储阵列的实际阵列温度，并根据所述实际阵列温度控制所述帕尔贴效应器件的开启和关断。
根据一些实施例，与同一存储阵列对应的若干个相邻的帕尔贴效应器件称为一个帕尔贴器件组，温度控制电路的信号控制线位于相邻帕尔贴器件组之间，以控制帕尔贴器件组中帕尔贴效应器件的开启和关断。
根据一些实施例，帕尔贴器件组中各帕尔贴效应器件为均匀排布、六方排布或外密内疏排布。
根据一些实施例，帕尔贴器件组中各帕尔贴效应器件中至少有两个帕尔贴效应器件之间串联或至少有两个帕尔贴效应器件之间并联。
根据一些实施例，帕尔贴效应器件包括：
N型阱区，位于基底中，N型阱区靠近基底的第二面；
P型阱区，位于基底中，P型阱区靠近基底的第二面；
第一金属层，位于N型阱区和P型阱区之间，且与N型阱区、P型阱区相接触，第一金属层的底部与N型阱区、P型阱区的底部相齐平，第一金属层的顶部低于第二面；
绝缘层，位于第一金属层的上表面，绝缘层的上表面与第二面相齐平；
第二金属层，位于N型阱区的上表面，用于连接电源电压；及
第三金属层，位于P型阱区的上表面，用于连接控制电压。
本公开实施例可以/至少具有以下优点：
上述半导体结构的制备方法中，基底的第一面形成有半导体器件，与第一面相对设置的第二面形成有帕尔贴效应器件，帕尔贴效应器件的吸热端靠近第一面，帕尔贴效应器件的放热端远离第一面，通过帕尔贴效应器件可以降低半导体器件的温度，进而消除半导体结构工作过程中产生的温度对半导体结构的性能的影响。当半导体结构为存储器件时，消除温度对单元保存时间的影响，延长了半导体结构的单元保存时间，降低了保存失败的风险，提高了半导体结构的可靠性。
上述半导体结构的中，基底的第一面形成有半导体器件，与第一面相对设置的第二面形成有帕尔贴效应器件，帕尔贴效应器件的吸热端靠近第一面，帕尔贴效应器件的放热端远离第一面，通过帕尔贴效应器件可以降低半导体器件的温度，进而消除半导体结构工作过程中产生的温度对半导体结构的性能的影响。当半导体结构为存储器件时，消除温度对单元保存时间的影响，延长了半导体结构的单元保存时间，降低了保存失败的风险，提高了半导体结构的可靠性。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中半导体结构的制备方法的流程示意图；
图2为第1实施例中半导体结构的剖面示意图；
图3为第2实施例中半导体结构的剖面示意图；
图4为第3实施例中半导体结构的剖面示意图；
图5为第4实施例中半导体结构的剖面示意图；
图6为第5实施例中半导体结构的剖面示意图；
图7为第1实施例中存储阵列的俯视示意图；
图8为第2实施例中存储阵列的俯视示意图；
图9为第3实施例中存储阵列的俯视示意图；
图10为一实施例中形成帕尔贴效应器件的流程示意图；
图11为一实施例中形成沟槽后半导体结构的剖面示意图；
图12为图11对应的一实施例中形成第一金属层后半导体结构的剖面示意图；
图13为图12对应的一实施例中形成绝缘层后半导体结构的剖面示意图；
图14为图13对应的一实施例中步骤S210之后半导体结构的剖面示意图。
附图标记说明：
102、基底；104、半导体器件；106、帕尔贴效应器件；108、温度控制电路；110、选择电路；112、器件层；114、固化层；202、存储模块；204、存储阵列；206、帕尔贴器件组；302、N型阱区；304、P型阱区；306、隔离结构；308、沟槽；310、第一金属层；312、绝缘层；314、第二金属层；316、第三金属层。
具体实施方式
为了便于理解本公开实施例，下面将参照相关附图对本公开实施例进行更全面的描述。附图中给出了本公开实施例的首选实施例。但是，本公开实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开实施例的技术领域的技术人员通常理解的含义相同。本文中在本公开实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本公开实施例的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本公开实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开实施例的限制。
可以理解，本公开所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本公开的范围的情况下，可以将第一面称为第二面，且类似地，可将第二面称为第一面。第一面和第二面两者都是基底的表面，但其不是基底的同一表面。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。在本公开的描述中，“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定。
单元保存时间(retention time)是指存储器件能够完好的保持数据的时间长度，是存储器件的一个重要工艺参数，单元保存时间越短存储器件保存数据失败的风险越高，存储器件的可靠性越差，如何延长存储器件的单元保存时间，降低存储器件保存数据失败的风险成为亟需解决的问题。
图1为一实施例中半导体结构的制备方法的流程示意图，如图1所示，在本公开的一实施例中，提供了一种半导体结构的制备方法，包括：
S102，提供第一面形成有半导体器件的基底。
具体的，提供基底，基底的第一面形成有半导体器件，即基底的第一面形成有半导体器件的器件层。该基底可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，基底的构成材料选用单晶硅。
S104，于基底的第二面形成帕尔贴效应器件。
具体的，在基底的第二面形成帕尔贴效应器件，基底的第二面与基底的第一面相对设置，帕尔帖效应器件具有吸热端和放热端，其中，吸热端靠近基底的第一面，放热端远离基底的第一面，即放热端靠近基底的第二面，通过帕尔贴效应器件可以降低半导体器件的温度。
上述半导体结构的制备方法中，基底的第一面形成有半导体器件，与第一面相对设置的第二面形成有帕尔贴效应器件，帕尔贴效应器件的吸热端靠近第一面，帕尔贴效应器件的放热端远离第一面，通过帕尔贴效应器件可以降低半导体器件的温度，进而消除半导体结构工作过程中产生的温度对半导体结构的性能的影响。当半导体结构为存储器件时，消除温度对单元保存时间的影响，延长了半导体结构的单元保存时间，降低了保存失败的风险，提高了半导体结构的可靠性。
图2为第1实施例中半导体结构的剖面示意图，如图2所示，作为示例，基底102的第一面形成有多个半导体器件104，基底102的第二面形成有多个帕尔贴效应器件106，多个帕尔贴效应器件106与多个半导体器件104一一对应，其中，至少部分帕尔贴效应器 件106位于基底102内。具体的，一个帕尔贴效应器件106与一个半导体器件104对应设置，示例性的，如图2所示，帕尔贴效应器件1和半导体器件A对应，帕尔贴效应器件2和半导体器件B对应，帕尔贴效应器件3和半导体器件C对应，通过与半导体器件对应的帕尔贴效应器件可以降低该半导体器件的温度。
图3为第2实施例中半导体结构的剖面示意图，如图3所示，作为示例，半导体结构的制备方法还包括：于帕尔贴效应器件106靠近第一面的表面上形成温度控制电路108，温度控制电路108用于检测半导体器件104的实际器件温度，并根据实际器件温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路106实时或间隔一段时间后检测半导体器件104的实际器件温度，在实际器件温度大于或等于预设器件温度时，控制帕尔贴效应器件106开始工作(开启)，进而降低半导体器件104的器件温度，在实际器件温度小于预设器件温度时，控制帕尔贴效应器件106停止工作(关断)，预设器件温度指的是会影响半导体器件性能的临界温度，示例性的，预设器件温度指的是会影响存储器件单元保存时间的临界温度。可以理解的是，当基底102第一面的半导体器件104的数量大于1时，温度控制电路108可以将半导体器件104作为一个整体，检测半导体器件104整体的实际器件温度，然后根据整体的实际器件温度控制所有帕尔贴效应器件106的开启和关断，该方式操作简单，需要处理的温度数据较少；温度控制电路108也可以检测各半导体器件104的实际器件温度，然后根据实际器件温度控制与半导体器件104对应的帕尔贴效应器件106的开启和关断，该方式需要处理的温度数据较多，控制温度的精度更高。作为示例，温度控制电路108形成于基底102的第二面且与帕尔贴效应器件106相齐平。在其他实施例中，温度控制电路108也可以形成在靠近半导体器件104的基底102中，通过该设置温度控制电路108检测到的实际器件温度更接近半导体器件104的真实温度。
图4为第3实施例中半导体结构的剖面示意图，如图4示，作为示例，半导体结构的制备方法还包括：于帕尔贴效应器件106靠近第一面的表面上形成选择电路110，选择电路110与帕尔贴效应器件106电连接，选择电路110被配置以根据实际器件温度帕尔贴效应器件106的开启和关断。示例性的，选择电路110被配置以根据实际器件温度分区域控制帕尔贴效应器件106的开启和关断，通过该设置可以避免电能的过度损耗，达到节约能源的目的。例如，选择电路110根据半导体器件104的实际器件温度控制与半导体器件104所在区域对应的帕尔贴效应器件106的开启和关断。
继续参考图4，作为示例，选择电路110位于帕尔贴效应器件106与温度控制电路108之间的区域。
作为示例，选择电路110位于温度控制电路108与基底102第一表面之间的区域。在其他实施例中，选择电路110可以形成于基底102的第二面且与帕尔贴效应器件106相齐平或低于基底102的第二面，即选择电路110与基底102第一面之间的距离等于或大于帕尔贴效应器件106与基底102第一面之间的距离。
图5为第4实施例中半导体结构的俯视示意图，如图5所示，作为示例，半导体器件104包括存储芯片，存储芯片包括多个存储模块202，帕尔贴效应器件106与存储模块202对应设置。此时，一个半导体器件104与多个帕尔贴效应器件106对应，可以精确、快速的降低存储芯片的温度。
作为示例，温度控制电路108用于检测存储模块202的实际模块温度，并根据实际模块温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路108检测存储芯片中各存储模块202的实际模块温度，并在存储模块202的实际模块温度大于或等于预设模块温度时，控制与存储模块202对应的帕尔贴效应器件106开始工作(开启)，进而降低存储模块202的模块温度，在存储模块202的实际模块温度小于预设模块温度时，控制与存储模块202对应的帕尔贴效应器件106停止工作(关断)，预设模块温度指的是会影响存储模块202单元保存时间的临界温度。通过该设置，可以在精确控制存储芯片中各存储模块202的温度，消除温度对单元保存时间的影响，延长了存储芯片的单元保存时间，降低了保存失败的风险，提高了存储芯片的可靠性。同时避免电能的过度损耗，达到节约能源的目的。
图6为第5实施例中半导体结构的俯视示意图，如图6所示，作为示例，存储模块202包括多个存储阵列204，帕尔贴效应器件106与存储阵列204对应设置。示例性的，帕尔贴效应器件106与存储阵列204一一对应设置，即一个帕尔贴效应器件106对应一个存储阵列204，通过每个帕尔贴效应器件106的开启和关断可以降低或不改变与其对应的存储阵列204的温度。
作为示例，温度控制电路108用于检测存储阵列204的实际阵列温度，并根据实际阵列温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路108检测存储模块202中各存储阵列204的实际阵列温度，并在存储阵列204的实际阵列温度大于或等于预设阵列温度时，控制与存储阵列204对应的帕尔贴效应器件106开始工作(开启)，进而降低存储阵列204的阵列温度，在存储阵列204的实际阵列温度小于预设阵列温度时，控制与存储阵列204对应的帕尔贴效应器件106停止工作(关断)，预设阵列温度指的是会影响存储阵列204单元保存时间的临界温度。通过该设置，可以在精确控制存储模块202 中各存储阵列204的温度，消除温度对单元保存时间的影响，延长了存储模块202的单元保存时间，降低了保存失败的风险，提高了存储模块202的可靠性。同时避免电能的过度损耗，达到节约能源的目的。
图7为第1实施例中存储阵列的俯视示意图，如图7所示，作为示例，与同一存储阵列204对应的若干个相邻的帕尔贴效应器件106称为一个帕尔贴器件组206，通过该设置可以精确、快速的降低存储阵列204的温度。
继续参考图7，作为示例，温度控制电路108的信号控制线位于相邻帕尔贴器件组206之间，以控制帕尔贴器件组206中帕尔贴效应器件106的开启和关断。具体的，温度控制电路108根据实际阵列温度控制存储阵列204中各帕尔贴效应器件106开启和关断的，通过该设置消除了控制信号传输时间差异对温度控制的影响。
继续参考图7，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为均匀排布，该设置制作工艺简单，提高了生产效率。
图8为第2实施例中存储阵列的俯视示意图，如图8所示，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为六方排布，通过该设置可以提高帕尔贴效应器件106温控覆盖面效率。
图9为第3实施例中存储阵列的俯视示意图，如图9所示，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为外密内疏排布。存储阵列204外周易受温度影响，通过外密内疏的环状分布的帕尔贴效应器件106可以提高温度控制的精度，快速的降低存储阵列204的温度。
作为示例，帕尔贴器件组206中各帕尔贴效应器件106中至少有两个帕尔贴效应器件106之间串联或至少有两个帕尔贴效应器件106之间并联。
图10为一实施例中形成帕尔贴效应器件的流程示意图，图11为一实施例中形成沟槽后半导体结构的剖面示意图，图12为图11对应的一实施例中形成第一金属层后半导体结构的剖面示意图，图13为图12对应的一实施例中形成绝缘层后半导体结构的剖面示意图，图14为图13对应的一实施例中步骤S210之后半导体结构的剖面示意图，如图10、图11、图12、图13、图14所示，作为示例，于基底102的第二面形成帕尔贴效应器件106包括：
S202，于基底的第二面分别形成N型阱区和P型阱区。
如图11所示，首先，提供基底102，基底102的第一面形成有器件层112(半导体器件)，可以理解的是，半导体结构的制备方法还包括：于器件层112的上表面形成固化层114，通过固化层114可以避免外部环境对器件层112的影响。可以理解的是，半导体结 构的制备方法还包括：对基底102的第二面进行减薄处理。然后，在基底102的第二面分别形成位于基底102中的N型阱区302和P型阱区304，具体的，可以通过离子注入工艺形成N型阱区302和P型阱区304。示例性的，N型阱区302和P型阱区304的注入深度相同。
作为示例，基底102的第二面形成有多个帕尔贴效应器件106，半导体结构的制备方法还包括：于基底的第二面形成隔离结构306，隔离结构306于基底102的第二面隔离出若干间隔排布的有源区，帕尔贴效应器件106形成于有源区中。
S204，于N型阱区、P型阱区之间形成沟槽。
继续参考图11，于N型阱302和P型阱区304之间形成沟槽308，其中，沟槽308的深度等于N型阱区302和P型阱区304的注入深度；即沟槽308的底部分别与N型阱区302的底部以及P型阱区的底部相齐平。
S206，于沟槽中填充形成第一金属层。
如图12所示，于沟槽308中填充形成顶部高于第二面的第一金属层310，第一金属层310分别与N型阱区302、P型阱区304相接触，第一金属层310可以作为帕尔贴效应器件106的吸热端。具体的，第一金属层310未填满沟槽308，即第一金属层310与基底102的第一面之间的距离小于沟槽308开口位置与基底102第一面之间的距离。示例性的，第一金属层310的构成材料包括金属材料、合金材料、多晶硅材料，例如金属铜、金属铝、金属金、金属银、金属钛、金属钨、氮化钛、多晶硅等。
S208，于第一金属层的上表面形成绝缘层。
如图13所示，在第一金属层310的上表面形成绝缘层312，绝缘层312的上表面与第二面相齐平；即绝缘层312填满沟槽308。示例性的，绝缘层312的构成材料包括氮化物、氧化物，例如氮化硅、二氧化硅。
S210，分别于N型阱区的上表面形成第二金属层、于P型阱区的上表面形成第三金属层。
如图14，分别于N型阱区302的上表面形成第二金属层314、于P型阱区306的上表面形成第三金属层316，第二金属层314用于连接电源电压，第三金属层316用于连接控制电压。第二金属层314和第三金属层316之间通过绝缘层312隔离，第二金属层314和第三金属层316可以作为帕尔贴效应器件106的放热端。示例性的，第二金属层314和第三金属层316的构成材料包括金属材料、合金材料、多晶硅材料，例如金属铜、金属铝、金属金、金属银、金属钛、金属钨、氮化钛、多晶硅等。作为示例，第一金属层310、第 二金属层314和第三金属层316的构成材料相同。
应该理解的是，虽然图1、图10的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、图10中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
如图2所示，本公开实施例提供一种半导体结构，包括：基底102和帕尔贴效应器件106，基底102的第一面形成有半导体器件104；帕尔贴效应器件106位于基底102的第二面，帕尔贴效应器件106用于降低半导体器件104的温度，第二面与第一面相对设置，帕尔帖效应器件106的吸热端靠近第一面，帕尔帖效应器件106的放热端远离第一面。
具体的，基底102的第一面形成有半导体器件104，即基底的第一面形成有半导体器件104的器件层。该基102底可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，基底102的构成材料选用单晶硅。帕尔贴效应器件106位于基底的第二面，基底的第二面与基底的第一面相对设置，帕尔帖效应器件106具有吸热端和放热端，其中，吸热端靠近基底102的第一面，放热端远离基底102的第一面，即放热端靠近基底102的第二面，通过帕尔贴效应器件106可以降低半导体器件104的温度。
上述半导体结构的中，基底的第一面形成有半导体器件，与第一面相对设置的第二面形成有帕尔贴效应器件，帕尔贴效应器件的吸热端靠近第一面，帕尔贴效应器件的放热端远离第一面，通过帕尔贴效应器件可以降低半导体器件的温度，进而消除半导体结构工作过程中产生的温度对半导体结构的性能的影响。当半导体结构为存储器件时，消除温度对单元保存时间的影响，延长了半导体结构的单元保存时间，降低了保存失败的风险，提高了半导体结构的可靠性。
如图2所示，作为示例，基底102的第一面形成有多个半导体器件104，基底102的第二面形成有多个帕尔贴效应器件106，多个帕尔贴效应器件106与多个半导体器件104一一对应，其中，至少部分帕尔贴效应器件106位于基底102内。具体的，一个帕尔贴效应器件106与一个半导体器件104对应设置，示例性的，如图2所示，帕尔贴效应器件1 和半导体器件A对应，帕尔贴效应器件2和半导体器件B对应，帕尔贴效应器件3和半导体器件C对应，通过与半导体器件对应的帕尔贴效应器件可以降低该半导体器件的温度。
如图3所示，作为示例，半导体结构还包括：
温度控制电路108，位于帕尔贴效应器件106靠近第一面的表面上，用于检测半导体器件104的实际器件温度，并根据实际器件温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路106实时或间隔一段时间后检测半导体器件104的实际器件温度，在实际器件温度大于或等于预设器件温度时，控制帕尔贴效应器件106开始工作(开启)，进而降低半导体器件104的器件温度，在实际器件温度小于预设器件温度时，控制帕尔贴效应器件106停止工作(关断)，预设器件温度指的是会影响半导体器件性能的临界温度，示例性的，预设器件温度指的是会影响存储器件单元保存时间的临界温度。可以理解的是，当基底102第一面的半导体器件104的数量大于1时，温度控制电路108可以将半导体器件104作为一个整体，检测半导体器件104整体的实际器件温度，然后根据整体的实际器件温度控制所有帕尔贴效应器件106的开启和关断，该方式操作简单，需要处理的温度数据较少；温度控制电路108也可以检测各半导体器件104的实际器件温度，然后根据实际器件温度控制与半导体器件104对应的帕尔贴效应器件106的开启和关断，该方式需要处理的温度数据较多，控制温度的精度更高。作为示例，温度控制电路108位于基底102的第二面且与帕尔贴效应器件106相齐平。在其他实施例中，温度控制电路108位于靠近半导体器件104的基底102中，通过该设置温度控制电路108检测到的实际器件温度更接近半导体器件104的真实温度。
如图4示，作为示例，半导体结构还包括：
选择电路110，位于帕尔贴效应器件106靠近第二面的表面上，选择电路110与帕尔贴效应器件106电连接，选择电路110被配置以根据实际器件温度分区域控制帕尔贴效应器件106的开启和关断。示例性的，选择电路110被配置以根据实际器件温度分区域控制帕尔贴效应器件106的开启和关断，通过该设置可以避免电能的过度损耗，达到节约能源的目的。例如，选择电路110根据半导体器件104的实际器件温度控制与半导体器件104所在区域对应的帕尔贴效应器件106的开启和关断。
继续参考图4，作为示例，选择电路110位于帕尔贴效应器件106与温度控制电路108之间的区域。
作为示例，选择电路110位于温度控制电路108与基底102第一表面之间的区域。在其他实施例中，选择电路110位于基底102的第二面且与帕尔贴效应器件106相齐平或低 于基底102的第二面，即选择电路110与基底102第一面之间的距离等于或大于帕尔贴效应器件106与基底102第一面之间的距离。
如图5所示，作为示例，半导体器件包括存储芯片，存储芯片包括多个存储模块202，帕尔贴效应器件106与存储模块202对应设置。此时，一个半导体器件104与多个帕尔贴效应器件106对应，可以精确、快速的降低存储芯片的温度。
作为示例，温度控制电路108用于检测存储模块202的实际模块温度，并根据实际模块温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路108检测存储芯片中各存储模块202的实际模块温度，并在存储模块202的实际模块温度大于或等于预设模块温度时，控制与存储模块202对应的帕尔贴效应器件106开始工作(开启)，进而降低存储模块202的模块温度，在存储模块202的实际模块温度小于预设模块温度时，控制与存储模块202对应的帕尔贴效应器件106停止工作(关断)，预设模块温度指的是会影响存储模块202单元保存时间的临界温度。通过该设置，可以在精确控制存储芯片中各存储模块202的温度，消除温度对单元保存时间的影响，延长了存储芯片的单元保存时间，降低了保存失败的风险，提高了存储芯片的可靠性。同时避免电能的过度损耗，达到节约能源的目的。
如图6所示，作为示例，存储模块202包括多个存储阵列204，帕尔贴效应器件106与存储阵列204对应设置。示例性的，帕尔贴效应器件106与存储阵列204一一对应设置，即一个帕尔贴效应器件106对应一个存储阵列204，通过每个帕尔贴效应器件106的开启和关断可以降低或不改变与其对应的存储阵列204的温度。
作为示例，温度控制电路108用于检测存储阵列204的实际阵列温度，并根据实际阵列温度控制帕尔贴效应器件106的开启和关断。具体的，温度控制电路108检测存储模块202中各存储阵列204的实际阵列温度，并在存储阵列204的实际阵列温度大于或等于预设阵列温度时，控制与存储阵列204对应的帕尔贴效应器件106开始工作(开启)，进而降低存储阵列204的阵列温度，在存储阵列204的实际阵列温度小于预设阵列温度时，控制与存储阵列204对应的帕尔贴效应器件106停止工作(关断)，预设阵列温度指的是会影响存储阵列204单元保存时间的临界温度。通过该设置，可以在精确控制存储模块202中各存储阵列204的温度，消除温度对单元保存时间的影响，延长了存储模块202的单元保存时间，降低了保存失败的风险，提高了存储模块202的可靠性。同时避免电能的过度损耗，达到节约能源的目的。
如图7所示，作为示例，与同一存储阵列204对应的若干个相邻的帕尔贴效应器件 106称为一个帕尔贴器件组206，通过该设置可以精确、快速的降低存储阵列204的温度。
继续参考图7，作为示例，温度控制电路108的信号控制线位于相邻帕尔贴器件组206之间，以控制帕尔贴器件组206中帕尔贴效应器件106的开启和关断。具体的，温度控制电路108根据实际阵列温度控制存储阵列204中各帕尔贴效应器件106开启和关断的，通过该设置消除了控制信号传输时间差异对温度控制的影响。
继续参考图7，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为均匀排布，该设置制作工艺简单，提高了生产效率。
如图8所示，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为六方排布，通过该设置可以提高帕尔贴效应器件106温控覆盖面效率。
如图9所示，作为示例，帕尔贴器件组206中各帕尔贴效应器件106为外密内疏排布。存储阵列204外周易受温度影响，通过外密内疏的环状分布的帕尔贴效应器件106可以提高温度控制的精度，快速的降低存储阵列204的温度。
作为示例，帕尔贴器件组206中各帕尔贴效应器件106中至少有两个帕尔贴效应器件106之间串联或至少有两个帕尔贴效应器件106之间并联。
如图14所示，作为示例，帕尔贴效应器件106包括：N型阱区302、P型阱区304、第一金属层310、绝缘层312、第二金属层314和第三金属层316。
N型阱区302位于基底102中，N型阱区302靠近基底102的第二面；P型阱区304位于基底102中，P型阱区304靠近基底102的第二面。基底102的第一面形成有器件层112(半导体器件)，可以理解的是，半导体结构还包括：固化层114，位于器件层112的上表面，通过固化层114可以避免外部环境对器件层112的影响。示例性的，N型阱区302和P型阱区304的注入深度相同。
第一金属层310位于N型阱区302和P型阱区304之间，且与N型阱区302、P型阱区304相接触，第一金属层310的底部与N型阱区302、P型阱区304的底部相齐平，第一金属层310的顶部低于第二面。第一金属层310可以作为帕尔贴效应器件106的吸热端。具体的，第一金属层310未填满沟槽308，即第一金属层310与基底102的第一面之间的距离小于沟槽308开口位置与基底102第一面之间的距离。示例性的，第一金属层310的构成材料包括金属材料、合金材料、多晶硅材料，例如金属铜、金属铝、金属金、金属银、金属钛、金属钨、氮化钛、多晶硅等。
绝缘层312位于第一金属层310的上表面，绝缘层312的上表面与第二面相齐平；即绝缘层312填满沟槽308。示例性的，绝缘层312的构成材料包括氮化物、氧化物，例如 氮化硅、二氧化硅。
第二金属层314位于N型阱区301的上表面，用于连接电源电压；第三金属层316位于P型阱区304的上表面，用于连接控制电压。第二金属层314和第三金属层316之间通过绝缘层312隔离，第二金属层314和第三金属层316可以作为帕尔贴效应器件106的放热端。示例性的，第二金属层314和第三金属层316的构成材料包括金属材料、合金材料、多晶硅材料，例如金属铜、金属铝、金属金、金属银、金属钛、金属钨、氮化钛、多晶硅等。作为示例，第一金属层310、第二金属层314和第三金属层316的构成材料相同。
作为示例，基底102的第二面形成有多个帕尔贴效应器件106，半导体结构还包括：隔离结构306，位于基底102的第二面，隔离结构306于基底102的第二面隔离出若干间隔排布的有源区，帕尔贴效应器件106形成于有源区中。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (23)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底的第一面形成有半导体器件；及
    于所述基底的第二面形成帕尔贴效应器件，所述帕尔贴效应器件用于降低所述半导体器件的温度，所述第二面与所述第一面相对设置，所述帕尔帖效应器件的吸热端靠近所述第一面，所述帕尔帖效应器件的放热端远离所述第一面。
  2. 根据权利要求1所述的制备方法，其中，所述基底的第一面形成有多个半导体器件，所述基底的第二面形成有多个帕尔贴效应器件，多个所述帕尔贴效应器件与多个所述半导体器件一一对应，其中至少部分所述帕尔贴效应器件位于所述基底内。
  3. 根据权利要求1所述的制备方法，其中，还包括：
    于所述帕尔贴效应器件靠近所述第一面的表面上形成温度控制电路，用于检测所述半导体器件的实际器件温度，并根据所述实际器件温度控制所述帕尔贴效应器件的开启和关断。
  4. 根据权利要求3所述的制备方法，其中，还包括：
    于所述帕尔贴效应器件靠近所述第一面的表面上形成选择电路，所述选择电路与所述帕尔贴效应器件电连接，所述选择电路被配置以根据所述实际器件温度分区域控制所述帕尔贴效应器件的开启和关断。
  5. 根据权利要求3所述的制备方法，其中，所述半导体器件包括存储芯片，所述存储芯片包括多个存储模块，所述帕尔贴效应器件与所述存储模块对应设置。
  6. 根据权利要求5所述的制备方法，其中，所述温度控制电路用于检测所述存储模块的实际模块温度，并根据所述实际模块温度控制所述帕尔贴效应器件的开启和关断。
  7. 根据权利要求5所述的制备方法，其中，所述存储模块包括多个存储阵列，所述帕尔贴效应器件与所述存储阵列对应设置。
  8. 根据权利要求7所述的制备方法，其中，所述温度控制电路用于检测所述存储阵列的实际阵列温度，并根据所述实际阵列温度控制所述帕尔贴效应器件的开启和关断。
  9. 根据权利要求8所述的制备方法，其中，与同一存储阵列对应的若干个相邻的帕尔贴效应器件称为一个帕尔贴器件组，所述温度控制电路的信号控制线位于相邻帕尔贴器件组之间，以控制所述帕尔贴器件组中帕尔贴效应器件的开启和关断。
  10. 根据权利要求7所述的制备方法，其中，所述帕尔贴器件组中各所述帕尔贴效应器件为均匀排布、六方排布或外密内疏排布。
  11. 根据权利要求7所述的制备方法，其中，所述帕尔贴器件组中各所述帕尔贴效应器件中至少有两个帕尔贴效应器件之间串联或至少有两个帕尔贴效应器件之间并联。
  12. 根据权利要求1所述的制备方法，其中，所述于所述基底的第二面形成帕尔贴效应器件包括：
    于所述基底的第二面分别形成位于基底中的N型阱区和P型阱区；
    于所述N型阱区和所述P型阱区之间形成沟槽，所述沟槽的深度等于所述N型阱区和所述P型阱区的注入深度；
    于所述沟槽中填充形成顶部高于所述第二面的第一金属层，所述第一金属层分别与所述N型阱区、所述P型阱区相接触；
    于所述第一金属层的上表面形成绝缘层，所述绝缘层的上表面与所述第二面相齐平；及
    分别于所述N型阱区的上表面形成第二金属层、于所述P型阱区的上表面形成第三金属层，所述第二金属层用于连接电源电压，所述第三金属层用于连接控制电压。
  13. 一种半导体结构，包括：
    基底，所述基底的第一面形成有半导体器件；及
    帕尔贴效应器件，位于所述基底的第二面，所述帕尔贴效应器件用于降低所述半导体器件的温度，所述第二面与所述第一面相对设置，所述帕尔帖效应器件的吸热端靠近所述第一面，所述帕尔帖效应器件的放热端远离所述第一面。
  14. 根据权利要求13所述的半导体结构，其中，所述基底的第一面形成有多个半导体器件，所述基底的第二面形成有多个帕尔贴效应器件，多个所述帕尔贴效应器件与多个所述半导体器件一一对应，其中至少部分所述帕尔贴效应器件位于所述基底内。
  15. 根据权利要求13所述的半导体结构，其中，还包括：
    温度控制电路，位于所述帕尔贴效应器件靠近所述第一面的表面上，用于检测所述半导体器件的实际器件温度，并根据所述实际器件温度控制所述帕尔贴效应器件的开启和关断。
  16. 根据权利要求15所述的半导体结构，其中，还包括：
    选择电路，位于所述帕尔贴效应器件靠近所述第一面的表面上，所述选择电路与所述帕尔贴效应器件电连接，所述选择电路被配置以根据所述实际器件温度分区域控制所述帕尔贴效应器件的开启和关断。
  17. 根据权利要求15所述的半导体结构，其中，所述半导体器件包括存储芯片，所述 存储芯片包括多个存储模块，所述帕尔贴效应器件与所述存储模块对应设置。
  18. 根据权利要求17所述的半导体结构，其中，所述温度控制电路用于检测所述存储模块的实际模块温度，并根据所述实际模块温度控制所述帕尔贴效应器件的开启和关断。
  19. 根据权利要求17所述的半导体结构，其中，所述存储模块包括多个存储阵列，所述帕尔贴效应器件与所述存储阵列对应设置；所述温度控制电路用于检测所述存储阵列的实际阵列温度，并根据所述实际阵列温度控制所述帕尔贴效应器件的开启和关断。
  20. 根据权利要求19所述的半导体结构，其中，与同一存储阵列对应的若干个相邻的帕尔贴效应器件称为一个帕尔贴器件组，所述温度控制电路的信号控制线位于相邻帕尔贴器件组之间，以控制所述帕尔贴器件组中帕尔贴效应器件的开启和关断。
  21. 根据权利要求19所述的半导体结构，其中，所述帕尔贴器件组中各所述帕尔贴效应器件为均匀排布、六方排布或外密内疏排布。
  22. 根据权利要求19所述的半导体结构，其中，所述帕尔贴器件组中各所述帕尔贴效应器件中至少有两个帕尔贴效应器件之间串联或至少有两个帕尔贴效应器件之间并联。
  23. 根据权利要求13所述的半导体结构，其中，所述帕尔贴效应器件包括：
    N型阱区，位于所述基底中，所述N型阱区靠近所述基底的第二面；
    P型阱区，位于所述基底中，所述P型阱区靠近所述基底的第二面；
    第一金属层，位于所述N型阱区和所述P型阱区之间，且与所述N型阱区、所述P型阱区相接触，所述第一金属层的底部与所述N型阱区、所述P型阱区的底部相齐平，所述第一金属层的顶部高于所述第二面；
    绝缘层，位于所述第一金属层的上表面，所述绝缘层的上表面与所述第二面相齐平；
    第二金属层，位于所述N型阱区的上表面，用于连接电源电压；及
    第三金属层，位于所述P型阱区的上表面，用于连接控制电压。
PCT/CN2022/082243 2022-01-17 2022-03-22 半导体结构及其制备方法 WO2023134016A1 (zh)

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