WO2023133972A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2023133972A1
WO2023133972A1 PCT/CN2022/078070 CN2022078070W WO2023133972A1 WO 2023133972 A1 WO2023133972 A1 WO 2023133972A1 CN 2022078070 W CN2022078070 W CN 2022078070W WO 2023133972 A1 WO2023133972 A1 WO 2023133972A1
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layer
region
barrier layer
work function
dielectric layer
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PCT/CN2022/078070
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English (en)
French (fr)
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李晓杰
钱大憨
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长鑫存储技术有限公司
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Priority to US17/845,119 priority Critical patent/US11978643B2/en
Publication of WO2023133972A1 publication Critical patent/WO2023133972A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • HKMG High k Metal Gate
  • the film stack structure is subjected to high-temperature annealing treatment, It is used to reduce the defects of the metal gate, but in the metal gate process, the barrier layer in the film stack structure will affect the formation of the high dielectric constant metal gate, which will lead to a higher threshold voltage, which will affect the semiconductor device performance.
  • the purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art, and provide a semiconductor device and its manufacturing method.
  • the semiconductor manufacturing method can change the ratio of metal elements and non-metal elements in different barrier film layers, and optimize the semiconductor Processing process.
  • a semiconductor device manufacturing method comprising:
  • the substrate comprising an array region and a peripheral region, the peripheral region comprising a first region and a second region;
  • first dielectric layer sequentially forming a first dielectric layer, a second dielectric layer, a first barrier layer, a first work function layer and a second barrier layer on the substrate;
  • a second work function layer, a third barrier layer and a first conductive layer are sequentially formed on the substrate. layer;
  • the ratio of the metal element content to the non-metal element content in the first barrier layer is smaller than the ratio of the metal element content to the non-metal element content in the second barrier layer and the third barrier layer.
  • a semiconductor device comprising:
  • a substrate comprising an array region and a peripheral region comprising a first region and a second region;
  • a second dielectric layer located on the first dielectric layer and on the array region, and interfacial interaction occurs in the interface between the first dielectric layer and the second dielectric layer;
  • the ratio of the metal element content to the non-metal element content in the barrier layer is greater than 1.
  • the semiconductor device manufacturing method provided by the present disclosure in the manufacturing process of the semiconductor device, because different barrier film layers are in different positions in the stacked film layer structure, they play different roles, by changing the different barrier film layers
  • the ratio of the content of metal elements and non-metal elements can achieve different process effects.
  • the ratio of metal elements and non-metal elements in the barrier layer is large, the resistance of the barrier layer is reduced, and it is easier to capture oxygen atoms, and at the same time it will increase the work.
  • the difficulty of metal diffusion in the function layer when the ratio of metal elements and non-metal elements in the barrier layer is small, the resistance of the barrier layer increases, and the metal in the work function layer diffuses more easily.
  • different barrier layers have different The content ratio of metal elements and non-metal elements can optimize the semiconductor processing process in the semiconductor manufacturing process;
  • the semiconductor device manufacturing method provided by the present disclosure can control the diffusion of atoms in the work function layer to the dielectric layer by changing the ratio of metal elements and non-metal elements in the barrier layer, and then control the different dielectric properties in the dielectric layer.
  • the interfacial interaction between the film layers can stabilize the voltage threshold of the transistor in the semiconductor device, thereby achieving the purpose of improving the performance of the semiconductor device.
  • FIG. 1 is a schematic diagram of a manufacturing process of a semiconductor device manufacturing method in an exemplary embodiment of the present disclosure.
  • FIGS. 2 to 10 are schematic diagrams of film layer stacking of a semiconductor structure of a semiconductor manufacturing method in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic flowchart of a first film layer removal method in the first region of a semiconductor device manufacturing method in an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic flowchart of a heat treatment method of a semiconductor device manufacturing method in an exemplary embodiment of the present disclosure.
  • 301 the first barrier layer
  • 302 the second barrier layer
  • 501 first conductive layer
  • 502 second conductive layer
  • 600 isolation layer
  • A the first area
  • B the second area
  • N1 first N area
  • N2 second N area
  • P1 the first P area
  • P2 the second P area
  • PR photoresist
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • CMOS Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
  • CMOS includes NMOS (Negative channel Metal Oxide Semiconductor, N-type metal oxide semiconductor) area and PMOS (Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) area, and shallow trench isolation (STI (Shallow Trench Isolation) structure, with the miniaturization of semiconductor devices and the requirements of gate performance, a metal gate is formed.
  • STI Shallow Trench Isolation
  • the barrier layer since the barrier layer has different functions as different layers in the stacked film structure, the barrier layer will affect the high dielectric constant metal gate semiconductor
  • the performance of the device has an impact, therefore, based on the influence of different ratios of metal elements and non-metal elements in the barrier layer on the manufacturing process of high dielectric constant semiconductor devices, a semiconductor device and its manufacturing method are proposed to optimize The manufacturing process of high dielectric constant semiconductor devices improves the performance of semiconductor devices.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, as shown in FIG. 1 , the method includes:
  • Step S10 providing a substrate 100, the substrate 100 includes an array area 10 and a peripheral area 20, and the peripheral area 20 includes a first area A and a second area B;
  • Step S20 sequentially forming a first dielectric layer 201, a second dielectric layer 202, a first barrier layer 301, a first work function layer 401, and a second barrier layer 302 on the substrate 100;
  • Step S30 After removing the second barrier layer 302 in the first region A and the first work function layer 401 in the first region A, the second work function layer 402, the third barrier layer 303 and the first conductive layer 401 are sequentially formed on the substrate 100. layer 501;
  • Step S40 performing heat treatment on the substrate 100, so that the atoms in the second work function layer 402 in the first region A diffuse into the second dielectric layer 202, so that the atoms in the first work function layer 402 in the second region B Atoms in the work function layer 401 diffuse into the second dielectric layer 202, and interfacial interaction occurs between the second dielectric layer 202 and the first dielectric layer 201;
  • Step S50 removing the first conductive layer 501, the third barrier layer 303, the second work function layer 402, and the first barrier layer 301 in the first region A, and removing the first conductive layer 501 in the array region 10 and the second region B , the third barrier layer 303, the second work function layer 402, the second barrier layer 302, the first work function layer 401 and the first barrier layer 301;
  • Step S60 Forming the fourth barrier layer 304 and the second conductive layer 502 on the first region A and the second region B; wherein, the ratio of the content of metal elements to the content of non-metal elements in the first barrier layer 301 is smaller than that of the second barrier layer 302 and in the third barrier layer 303, the ratio of the metal element content to the non-metal element content.
  • the present disclosure adopts different ratios of metal elements and non-metal elements in different barrier layers value, in the process of process treatment, using the different proportions of different elements can play a different role in the process, taking the barrier layer as a titanium nitride layer as an example, in the case of a large proportion of titanium nitrogen in the titanium nitride layer , the resistance of the titanium nitride layer decreases, the oxygen capture ability is higher, and the atoms in the work function layer above or below the titanium nitride layer are difficult to diffuse; the ratio of titanium to nitrogen in the titanium nitride layer is When it is small, the resistance value of the titanium nitride layer increases, and the atoms in the work function layer above or below the titanium nitride layer are easy to diffuse.
  • the semiconductor processing engineering In different barrier layers, different ratios of metal elements and non-metal elements are used to control the diffusion of atoms in the work function layer into the dielectric layer, and then control the interface between different dielectric film layers in the dielectric layer Interact with each other to stabilize the voltage threshold of the transistor in the semiconductor device, optimize the processing technology of the semiconductor device, and improve the performance of the semiconductor device.
  • FIG. 2 to FIG. 10 respectively representatively show several steps of an exemplary embodiment of a semiconductor structure manufacturing method, a schematic diagram of a film layer stack structure of a semiconductor structure, and the following will be combined with the above-mentioned appended
  • the figure illustrates in detail the process steps of the semiconductor device manufacturing method proposed in the present disclosure.
  • step S10 the substrate 100 is provided, the substrate 100 includes the array area 10 and the peripheral area 20 , the peripheral area 20 includes the first area A and the second area B.
  • the semiconductor device manufacturing method provided by the present disclosure includes an array region 10 and a peripheral region 20 on a substrate 100, and the peripheral region 20 includes a first region A and a second region B.
  • a plurality of shallow trench isolation structures are formed inside the substrate 100. After the trench 101 is formed in the substrate 100, an isolation material can be filled in the trench 101 to form a shallow trench isolation structure.
  • the isolation material can include nitrogen At least one of silicon oxide, silicon oxide or silicon carbonitride, which is not specifically limited here, and by embedding the storage structure 102 in the array region 10, the storage structure 102 includes at least a gate isolation layer 1021 and a gate conductive layer 1022, The material of the gate isolation layer 1021 may include at least one of silicon nitride, silicon oxide or silicon carbonitride, and the material of the gate conductive layer 1022 may include at least one of tungsten, titanium nitride or polysilicon.
  • the specific layers of the storage structure 102 are determined according to the actual structure, and the storage structure 102 is used for writing, erasing or storing data.
  • the peripheral area 20 includes a first region A and a second region B, the first region A includes an N region forming an N-type device, the N region includes a first N region N1 and a second N region N2, and the second region B includes a P The P region of the type device, the P region includes a first P region P1 and a second P region P2.
  • the substrate 100 may be silicon or other semiconductor materials, and the disclosure does not specifically limit the material of the substrate 100 .
  • step S20 the first dielectric layer 201 , the second dielectric layer 202 , the first barrier layer 301 , the first work function layer 401 and the second barrier layer 302 are sequentially formed on the substrate 100 .
  • the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401 and the second barrier layer 302 are deposited on the substrate 100, wherein, The thickness of the first dielectric layer 201 in the second N region N2 is greater than the thickness of the first dielectric layer 201 in the first N region N1, and the thickness of the first dielectric layer 201 in the second P region P2 is greater than that of the first P region P1 The thickness of the first dielectric layer 201.
  • first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401 and the second barrier layer 302 Before forming the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401 and the second barrier layer 302 on the substrate 100, it is also necessary to form Strain layer 203; form the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401 and the second barrier layer 302 on the substrate 100, and form them sequentially on the substrate 100 in the array region 10
  • the barrier material layer 1011 and the isolation layer 600; the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401 and the second barrier layer 302 are formed on the substrate 100, and the array area 10 is removed
  • the first dielectric layer 201 of the array area 10 can be removed by etching, which can include dry etching or wet etching, and the specific
  • the material of the first dielectric layer 201 can be silicon oxide, silicon oxynitride and other materials
  • the material of the second dielectric layer 202 (HK layer) can be hafnium silicon oxynitride, barium strontium titanate, strontium titanate, barium strontium tantalate, etc. material
  • the dielectric constant of the second dielectric layer 202 is greater than the dielectric constant of the first dielectric layer 201
  • the material of the strain layer 203 can be germanium silicon compound, namely SiGe
  • the material of the isolation layer 600 can be silicon nitride , silicon oxide and other materials
  • the materials of the above-mentioned film layer in the present disclosure include but are not limited thereto, and are not specifically limited in the present disclosure.
  • the material deposition of the work function layer in the first region A is mainly lanthanum oxide (LaO), and the material of the work function layer in the second region B (P1 region and P2 region) is mainly aluminum oxide ( AlO), wherein the first work function layer 401 is an aluminum oxide layer, after the second dielectric layer 202 is formed on the first area A and the second area B, the first work function layer is deposited on the first area A and the second area B
  • the first functional layer 401 may be an aluminum oxide layer, and a first barrier layer 301 and a second barrier layer 302 are respectively deposited below and above the first functional layer 401, wherein the first barrier layer 301 and the second barrier layer
  • the material of layer 302 may be titanium nitride (TiN), thallium nitride, etc., but is not limited to the above materials.
  • the dielectric layer 202 acts as a barrier, and the first barrier layer 301 is deposited between the first work function layer 401 and the second dielectric layer 202.
  • the present disclosure enables the ratio value of the metal element and the non-metal element in the first barrier layer 301 to be set to be less than 1, and the ratio range value can include 0.5-0.95 to improve
  • the diffusion ability of atoms in the work function layer taking the first barrier layer 301 as a titanium nitride layer as an example, the ratio of titanium to nitrogen in the first barrier layer 301 can be set to 0.8, that is, the first barrier layer 301 is a nitrogen-rich layer , in the subsequent processing technology, the atoms in the first work function layer 401 are easier to diffuse through the titanium nitride layer with a titanium-to-nitrogen ratio of 0.8.
  • the ratio of metal elements and non-metal elements in the first barrier layer 301 in the present disclosure is less than 1, and the range may be 0.5-0.95, but the disclosure does not specifically limit the above ratio range, which can be selected according to actual use requirements.
  • step S30 after removing the second barrier layer 302 in the first region A and the first work function layer 401 in the first region A, the second work function layer 402 and the third barrier layer 303 are sequentially formed on the substrate 100 and the first conductive layer 501.
  • the specific removal method is as follows:
  • Step S301 forming a photoresist PR covering the first region A, and patterning the first photoresist PR;
  • Step S302 using the patterned photoresist PR to etch and remove the second barrier layer 302 and the first work function layer 401 in the first region A.
  • the first region A is etched using photoresist PR to remove the second barrier layer 302 and the first work function layer 401, wherein the etching method can be dry etching , wet etching, or a combination of dry etching and wet etching, the specific etching method can be selected according to actual needs, and is not specifically limited in the present disclosure.
  • the etching method can be dry etching , wet etching, or a combination of dry etching and wet etching, the specific etching method can be selected according to actual needs, and is not specifically limited in the present disclosure.
  • the second work function layer 402 As shown in FIG. 7 , after the first region A is etched to remove the second barrier layer 302 and the first work function layer 401, the second work function layer 402, the third barrier layer 303 and the first work function layer 401 are sequentially formed on the substrate 100.
  • the conductive layer 501 wherein the material of the second work function layer 402 can be a lanthanum oxide layer, after the above steps, in the first region A, the second work function layer 402 is located between the first barrier layer 301 and the third barrier layer 303 Between, in the second region B, the second work function layer 402 is located between the second barrier layer 302 and the third barrier layer 303, and the first conductive layer 501 is deposited on the third barrier layer 303, the first conductive layer 501
  • the material can be undoped polysilicon (poly).
  • a first barrier layer 301 is disposed below the second work function layer 402 (LaO layer),
  • the ratio of titanium and nitrogen in the first barrier layer 301 is selected to be 0.8
  • a third barrier layer is arranged between the second work function layer 402 (LaO layer) and the first conductive layer 501 303.
  • the ratio of titanium to nitrogen in the third barrier layer 303 is set to 1.2, which is a titanium-rich layer.
  • the third barrier layer 303 Since the third barrier layer 303 The content of metal elements in the medium is higher than that of non-metal elements, the energy of capturing oxygen is higher, the resistance value is reduced, and the atoms in the work function layer are not easy to diffuse. In the subsequent processing technology, the atoms located on both sides of the third barrier layer 303 Atoms in the first work function layer 401 and the second work function layer 402 are difficult to diffuse and act as barriers.
  • the ratio of titanium nitrogen in the first barrier layer 301 is set to 0.8, and the titanium nitrogen in the second barrier layer 302 and the third barrier layer 303
  • the ratio is set to 1.2
  • the ratio of metal elements to non-metallic elements in the second barrier layer 302 and the third barrier layer 303 is greater than 1, the ability of the barrier layer to capture oxygen increases, the resistance decreases, and the metal in the work function layer diffuses becomes difficult
  • the ratio of metal element to non-metal element content in the first barrier layer 301 is less than 1, the resistance in the barrier layer increases, the metal diffusion in the work function layer becomes easier, and in the second region B, each film layer The function is as described above, and will not be repeated here.
  • the ratio of the metal element content to the non-metal element content in the first barrier layer 301 is smaller than the ratio of the metal element content to the non-metal element content in the second barrier layer 302 and the third barrier layer 303, and the first barrier layer
  • the ratio of the metal element content to the non-metal element content in the layer 301 is less than 1
  • the ratio of the metal element content to the non-metal element content in the second barrier layer 302 and the third barrier layer 303 is greater than 1.
  • the ratio range of the metal element content and the non-metal content in the medium includes 0.5-0.95
  • the ratio range of the metal element content and the non-metal element content in the second barrier layer 302 and the third barrier layer 303 includes 1.05-1.5
  • the present disclosure includes but does not include Limited to the values in the above range, the ratio of the content of metal elements and non-metal elements in the barrier layer can be determined according to the needs of actual use.
  • step S40 heat treatment is performed on the substrate 100, so that the atoms in the second work function layer 402 in the first region A diffuse into the second dielectric layer 202, so that the atoms in the first work function layer 402 in the second region B Atoms in the work function layer 401 diffuse into the second dielectric layer 202 and interface interaction occurs between the second dielectric layer 202 and the first dielectric layer 201 .
  • Dipole interaction is an interaction between polar molecules, that is, one end of a polar molecule with a part of positive charge is connected to another molecule with a positive charge.
  • Dipole interaction is an interaction between polar molecules, that is, one end of a polar molecule with a part of positive charge is connected to another molecule with a positive charge.
  • the attraction between one end of some negative charges, polar molecules produce dipole moments due to uneven charge distribution, and when polar molecules are close to each other, it will cause electrical attraction.
  • the preferred heat treatment process adopts the RTA (Rapid Thermal Anneal, rapid thermal treatment) process to heat treat the substrate 100, as shown in FIG. 12 , the heat treatment method includes:
  • Step S401 injecting the first gas and keeping it at the first temperature for a first preset time
  • Step S402 Introduce a second gas, and at the same time raise the first temperature to a second temperature within a second preset time;
  • Step S403 annealing treatment, keeping for a third preset time.
  • the first preset time is greater than the second preset time and the third preset time, and the second preset time is less than the third preset time, that is, the minimum of the above three preset times
  • the first preset time is the second preset time, the third preset time, and the first preset time
  • the first gas includes an inert gas
  • the second gas includes an oxidizing gas
  • the flow rate of the first gas is greater than the flow rate of the second gas.
  • the first gas can be inert gases such as nitrogen and helium
  • the flow range of the first gas includes 10000-3000 sccm (standard ml/min)
  • the second gas can be an oxidizing gas such as oxygen
  • the second The gas flow range includes 300-1000 sccm, wherein the flow rate of the first gas is greater than the flow rate of the second gas
  • the first temperature range includes 300°C-800°C
  • the second temperature range includes 400°C-1500°C
  • the heating rate can be 50°C/S-150°C/S
  • the first preset time can be 10S-30S (seconds)
  • the second preset time can be 3.3S-7.3S
  • the third preset time The preset time may be 5S-15S, wherein the preset time in descending order is the second preset time, the third preset time, and the first preset time.
  • the first gas may be fed, the first gas is nitrogen, the flow rate of the nitrogen gas is 20000 sccm, and the temperature at the first temperature is maintained for the first preset time, the first temperature can be The temperature is 550°C, the first preset time can be 20S; and then the second gas can be fed, the second gas can be oxygen, and 650 sccm of oxygen can be passed through, while the first gas can be kept at 20000 sccm, and the first gas can be nitrogen, so that the temperature can be changed from The first temperature is raised to the second temperature, the first temperature can be 550°C, the second temperature can be 950°C, the heating rate can be 75°C/S, and the heating time is the second preset time, that is, the heating time (second preset Set the time) to be about 5.3S; perform peak annealing treatment on the substrate 100, keep the temperature value at the second temperature for the third preset time, the second temperature may be 950°C, and the third preset
  • step S50 the first conductive layer 501, the third barrier layer 303, the second work function layer 402 and the first barrier layer 301 in the first region A are removed, and the array region 10 and the second barrier layer in the second region B are removed.
  • the substrate 100 is subjected to a high-temperature rapid heat treatment process.
  • the first conductive layer 501, the third barrier layer 303, the second work function layer 402, and the first barrier layer 301 in the first region A are removed,
  • the first conductive layer 501 , the third barrier layer 303 , the second work function layer 402 , the second barrier layer 302 , the first work function layer 401 and the first barrier layer 301 in the array region 10 and the second region B are removed simultaneously.
  • step S60 step S60: forming the fourth barrier layer 304 and the second conductive layer 502 on the first region A and the second region B.
  • the ratio of the metal element content to the non-metal element content in the fourth barrier layer 304 is the same as the ratio of the metal element content to the non-metal element content in the second barrier layer 302 and the third barrier layer 303 .
  • step S10-step S50 deposit and form a fourth barrier layer 304 on the first region A and the second region B, and deposit a second conductive layer 502 on the fourth barrier layer 304, wherein , the ratio of the content of metal elements and non-metal elements in the fourth barrier layer 304 needs to be greater than 1, because the role of the fourth barrier layer 304 is to capture more oxygen elements, and at the same time it can ensure that the metal is difficult to diffuse, for example, the fourth barrier layer 304 is a titanium nitride layer, and the ratio of titanium to nitrogen can be 1.2, which can ensure that the fourth barrier layer 304 can prevent the diffusion of metal elements in other film layers after the metal gate is formed in the semiconductor device.
  • the ratio of the metal element content and the non-metal element content in the fourth barrier layer 304 can be the same as the ratio of the metal element content and the non-metal element content in the second barrier layer 302, which can simplify the processing process of the semiconductor device and save processing. time and improve processing efficiency.
  • the ratio of metal elements to non-metal elements in the fourth barrier layer 304 is greater than 1, wherein the ratio of metal elements to non-metal elements can range from 1.05 to 1.5, but the disclosure does not specifically limit the range of the above ratios .
  • the second conductive layer 502 can be a doped polysilicon layer, or other materials suitable for semiconductor film layers, which is not specifically limited in this disclosure.
  • first barrier layer 301, second barrier layer 302, third barrier layer 303 and fourth barrier layer 304 can be deposited by PVD (Physical Vapor Deposition, physical vapor deposition), wherein the physical vapor deposition method includes: vacuum Evaporation, sputtering coating, arc plasma coating, ion coating and molecular beam epitaxy and other methods, the preferred method of the present disclosure is RFPVD (Radio Frequency Physical Vapor Deposition, radio frequency physical vapor deposition) for metal elements in each barrier film layer and The adjustment of the proportion of non-metallic elements is not limited to this method.
  • PVD Physical Vapor Deposition, physical vapor deposition
  • RFPVD Radio Frequency Physical Vapor Deposition, radio frequency physical vapor deposition
  • the functions of different barrier layers are further enhanced, for example, the work function near the barrier layer
  • the ratio of the content of metal elements to non-metal elements can be adjusted to less than 1, making it easier for the metal elements in the layer to diffuse.
  • the metal elements in the barrier layer can be Adjusting the ratio of the content of the non-metallic element to greater than 1 makes the ability of the barrier layer to capture oxygen elements stronger, and the atoms in the work function layer are not easy to diffuse.
  • different ratios are selected according to different barrier layer functions. It can optimize semiconductor processing technology and improve device performance.
  • the present disclosure also provides a semiconductor device, which is manufactured using the above semiconductor device manufacturing method. As shown in FIG. Layer 502.
  • the substrate 100 includes an array area 10 and a peripheral area 20, and the peripheral area 20 includes a first area A and a second area B; the first dielectric layer 201 is located on the peripheral area 20; the second dielectric layer 202 is located on the first dielectric layer 201 And on the array region 10, interfacial interaction occurs in the interface between the first dielectric layer 201 and the second dielectric layer 202; the barrier layer 304 is located on the second dielectric layer 202; the conductive layer 502 is located on the barrier layer 304; wherein, the barrier The ratio of metal element content to non-metal element content in layer 304 is greater than 1.
  • the first dielectric layer 201 may be a silicon oxide layer
  • the second dielectric layer 202 may be a hafnium oxynitride silicon layer (HK layer)
  • the dielectric constant of the second dielectric layer 202 is greater than that of the first dielectric layer 201
  • the barrier layer 304 can be a silicon nitride layer
  • the conductive layer 502 can be a doped polysilicon layer, but the materials of the film layers in the present disclosure include but are not limited to the above-mentioned materials, and appropriate materials can be selected according to the structure and processing engineering of the actual semiconductor device. The disclosure is not specifically limited.
  • the semiconductor device provided by the present disclosure is manufactured using the above-mentioned semiconductor manufacturing method.
  • the barrier layer with different content ratios of metal elements and non-metal elements is used for processing, so that the function of the barrier layer is further optimized, and the high The processing technology of the dielectric constant metal gate, the performance of the semiconductor device has been further improved.

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Abstract

一种半导体器件制造方法包括：基底外围区的第一区域及第二区域(步骤S10)；在第一区域形成第一层叠结构，在阵列区和第二区域形成第二层叠结构(步骤S20及S30)；热处理基底，使功函数层中的原子扩散至第二介质层中，第二介质层与第一介质层发生界面相互作用(步骤S40)；去除第一层叠结构至第二介质层，去除第二层叠结构至第二介质层(步骤S50)；形成第四阻挡层和第二导电层；第一阻挡层中金属元素含量与非金属元素含量的比例小于第二阻挡层中及第三阻挡层中金属元素含量和非金属元素含量的比例(步骤S60)。本公开通过改变不同的阻挡膜层中的金属元素和非金属元素含量的比例，优化了半导体加工过程，提升了半导体器件的性能。

Description

半导体器件及其制造方法
交叉引用
本公开要求于2022年1月12日提交的申请号为202210032039.6，名称为“半导体器件及其制造方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件及其制造方法。
背景技术
高介电常数金属栅极(HKMG，High k Metal Gate)堆叠工艺已经在45nm工艺节点引入，用以解决传统栅极所面临的技术障碍。
现有的高介电常数金属栅极半导体器件的工艺流程中，通常在高介电常数金属栅极膜层堆叠的过程中，在各个膜层堆叠后，对膜层堆叠结构进行高温退火处理，用以减少金属栅极的缺陷，但在金属栅极制程中，膜层堆叠结构中的阻挡层会对高介电常数金属栅极的形成产生影响，会导致阈值电压较高，从而影响半导体器件的性能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供了一种半导体器件及其制造方法，该半导体制造方法可以改变不同的阻挡膜层中的金属元素和非金属元素含量的比例，优化了半导体加工过程。
根据本公开的一个方面，提供了一种半导体器件制造方法，该方法包括：
提供基底，所述基底包括阵列区和外围区，所述外围区包括第一区 域及第二区域；
在所述基底上依次形成第一介质层、第二介质层、第一阻挡层、第一功函数层及第二阻挡层；
去除所述第一区域的所述第二阻挡层及所述第一区域的所述第一功函数层后，在所述基底上依次形成第二功函数层、第三阻挡层及第一导电层；
对所述基底进行热处理，以使所述第一区域中的第二功函数层中的原子扩散至所述第二介质层中，使所述第二区域中的第一功函数层中的原子扩散至所述第二介质层中，并在所述第二介质层与所述第一介质层之间发生界面相互作用；
去除所述第一区域的所述第一导电层、所述第三阻挡层、所述第二功函数层及所述第一阻挡层，且去除所述阵列区和所述第二区域的所述第一导电层、所述第三阻挡层、所述第二功函数层、所述第二阻挡层、所述第一功函数层及所述第一阻挡层；
于所述第一区域和所述第二区域上形成第四阻挡层和第二导电层；
其中，所述第一阻挡层中金属元素含量与非金属元素含量的比例小于所述第二阻挡层中及所述第三阻挡层中金属元素含量和非金属元素含量的比例。
根据本公开的另一个方面，提供了一种半导体器件，包括：
基底，所述基底包括阵列区和外围区，所述外围区包括第一区域及第二区域；
第一介质层，位于所述外围区上；
第二介质层，位于所述第一介质层上和所述阵列区上，所述第一介质层和所述第二介质层之间的界面中发生界面相互作用；
阻挡层，位于所述第二介质层上；
导电层，位于所述阻挡层上；
其中，所述阻挡层中金属元素含量和非金属元素含量的比例大于1。
本公开提供的半导体器件制造方法，在半导体器件的制作过程中，由于不同的阻挡膜层处于堆叠膜层结构中不同的位置时，所起到的作用是不同的，通过改变不同阻挡膜层中金属元素和非金属元素含量的比例， 达到不同的工艺效果，在阻挡层中金属元素和非金属元素含量的比例较大时，阻挡层的电阻减小，更容易捕获氧原子，同时会增加功函数层的金属扩散难度，在阻挡层中金属元素和非金属元素含量的比例较小时，阻挡层的电阻增大，功函数层的金属更容易扩散，利用上述特性，使不同的阻挡层具有不同的金属元素和非金属元素含量比例，在半导体制造过程中，可以优化半导体的加工工艺过程；
另一方面，本公开提供的半导体器件制造方法可以通过改变阻挡层中金属元素和非金属元素的比例，控制功函数层中的原子向介质层中的扩散，进而控制介质层中的不同的介质膜层之间的产生的界面相互作用，以达到稳定半导体器件中晶体管的电压阈值，从而达到提升半导体器件性能的目的。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开示例性实施例中的一种半导体器件制造方法的制造流程示意图。
图2至图10为本公开示例性实施例中的一种半导体制作方法的半导体结构的膜层堆叠示意图。
图11为本公开示例性实施例中的一种半导体器件制造方法的第一区域中的第一次膜层去除方法流程示意图。
图12为本公开示例性实施例中的一种半导体器件制造方法的热处理方法流程示意图。
其中，附图标记说明如下：
10：阵列区；20：外围区；
100：基底；101：沟槽；1011：阻挡材料层；
102：存储结构；1021：栅隔离层；
1022：栅导电层；201：第一介质层；
202：第二介质层；203：应变层；
301：第一阻挡层；302：第二阻挡层；
303：第三阻挡层；304：第四阻挡层；
401：第一功函数层；402：第二功函数层；
501：第一导电层；502：第二导电层；600：隔离层；
A：第一区域；B：第二区域；
N1：第一N区；N2：第二N区；
P1：第一P区；P2：第二P区；
PR：光刻胶。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，所述附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构、系统和步骤。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中所述的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或 多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在DRAM(Dynamic Random Access Memory，动态随机存取存储器)中，现有的高介电常数金属栅极半导体器件的工艺流程，以CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件为例，CMOS包括NMOS(Negative channel Metal Oxide Semiconductor，N型金属氧化物半导体)区及PMOS(Positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)区，NMOS区和PMOS区之间形成有浅沟槽隔离(STI，Shallow Trench Isolation)结构，随着半导体器件的微缩化及栅极性能的要求，形成了金属栅极。为进一步提高半导体器件的性能，现有技术中在形成金属栅极结构后，对器件进行高温退火处理，如进行1000℃尖峰退火(spike annealing)，可以减少金属栅极缺陷。
但在上述的高介电常数金属栅极半导体器件的制程中，由于阻挡层作为在堆叠层膜结构中的不同层膜具有不同的功能，因此阻挡层继会对高介电常数金属栅极半导体器件的性能产生影响，因此，本公开基于阻挡层中不同的金属元素和非金属元素比例对高介电常数半导体器件的制造工艺的影响，提出了一种半导体器件及其制造方法，用以优化高介电常数半导体器件的制造工艺过程，提高半导体器件的性能。
本公开提供的半导体器件制造方法是以应用于动态随机存取存储器为例进行说明的，本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体结构中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的半导体结构的制作方法的原理的范围内。
本公开实施方式提供了一种半导体器件制造方法，如图1所示，该方法包括：
步骤S10：提供基底100，基底100包括阵列区10和外围区20，外围区20包括第一区域A及第二区域B；
步骤S20：在基底100上依次形成第一介质层201、第二介质层202、第一阻挡层301、第一功函数层401及第二阻挡层302；
步骤S30：去除第一区域A的第二阻挡层302及第一区域A的第一功函数层401后，在基底100上依次形成第二功函数层402、第三阻挡层303及第一导电层501；
步骤S40：对基底100进行热处理，以使所述第一区域A中的第二功函数层402中的原子扩散至所述第二介质层202中，使所述第二区域B中的第一功函数层401中的原子扩散至所述第二介质层202中，并在所述第二介质层202与所述第一介质层201之间发生界面相互作用；
步骤S50：去除第一区域A的第一导电层501、第三阻挡层303、第二功函数层402及第一阻挡层301，且去除阵列区10和第二区域B的第一导电层501、第三阻挡层303、第二功函数层402、第二阻挡层302、第一功函数层401及第一阻挡层301；
步骤S60：于第一区域A和第二区域B上形成第四阻挡层304和第二导电层502；其中，第一阻挡层301中金属元素含量与非金属元素含量的比例小于第二阻挡层302中及第三阻挡层303中金属元素含量和非金属元素含量的比例。
通过上述加工工艺流程，区别于现有技术方案中不同的阻挡层中的金属元素和非金属元素采用不变的比例值，本公开在不同的阻挡层采用不同的金属元素与非金属元素的比例值，在工艺处理的流程中，利用不同元素含量比例的不同，可以起到不同的工艺作用，以阻挡层为氮化钛层为例，在氮化钛层中钛氮比例值较大的情况下，此氮化钛层的电阻减小，氧俘获能力较高，位于此氮化钛层的上方或下方的功函数层中的原子很难进行扩散；在氮化钛层中钛氮比例值较小的情况下，此氮化钛层的电阻值增大，位于此氮化钛层的上方或下方的功函数层中的原子容易进行扩散，基于阻挡层的上述特性，在半导体的加工工程中在不同的阻挡层使用不同的金属元素与非金属元素的比例值，控制功函数层中的原子向介质层中的扩散，进而控制介质层中的不同的介质膜层之间的产生的界面相互作用，以达到稳定半导体器件中晶体管的电压阈值，优化半导体器件的加工工艺，提高半导体器件的性能。
结合图2至图10，图2至图10分别代表性地示出了半导体结构的制作方法的一示例性实施方式的几个步骤中，半导体结构的膜层堆叠结构示意图，下面将结合上述附图，对本公开提出的半导体器件制造方法的工艺步骤进行详细说明。
其中，在步骤S10中，提供基底100，基底100包括阵列区10和外围区20，外围区20包括第一区域A及第二区域B。
如图2所示，本公开提供的半导体器件制造方法，以CMOS器件为例，在基底100上包括阵列区10和外围区20，外围区20包括第一区域A及第二区域B，通过在基底100内部形成多个浅沟槽隔离结构，浅沟槽隔离结构是在基底100内形成沟槽101后，可在沟槽101内填充隔离材料以形成浅沟槽隔离结构，隔离材料可以包括氮化硅、氧化硅或碳氮化硅中的至少一种，在此不做特殊限定，并通过在阵列区10埋入存储结构102，存储结构102至少包括栅隔离层1021和栅导电层1022，栅隔离层1021的材料可以包括氮化硅、氧化硅或碳氮化硅中的至少一种，栅导电层1022的材料可以包括钨、氮化钛或多晶硅中的至少一种。但存储结构102的具体层膜根据实际结构确定，存储结构102用于写入、擦除或存储数据。
外围区20包括包括第一区域A及第二区域B，第一区域A包括形成N型器件的N区，N区包括第一N区N1和第二N区N2，第二区域B包括形成P型器件的P区，P区包括第一P区P1和第二P区P2。
基底100可以是硅或者其它半导体材料，本公开对基底100的材料不做特殊限定。
其中，在步骤S20中，在基底100上依次形成第一介质层201、第二介质层202、第一阻挡层301、第一功函数层401及第二阻挡层302。
如图2、图3及图4所示，在基底100上沉积第一介质层201和第二介质层202、第一阻挡层301、第一功函数层401及第二阻挡层302，其中，第二N区N2中的第一介质层201的厚度大于第一N区N1中的第一介质层201的厚度，第二P区P2中的第一介质层201的厚度大于第一P区P1的第一介质层201的厚度。
在基底100上形成第一介质层201和第二介质层202、第一阻挡层 301、第一功函数层401及第二阻挡层302之前，还需要在第一P区P1的基底100上形成应变层203；在基底100上形成第一介质层201和第二介质层202、第一阻挡层301、第一功函数层401及第二阻挡层302，在阵列区10的基底100上依次形成阻挡材料层1011和隔离层600；在基底100上形成第一介质层201和第二介质层202、第一阻挡层301、第一功函数层401及第二阻挡层302，去除阵列区10中的第一介质层201，其中，去除阵列区10的第一介质层201可采用刻蚀法，可包括干法刻蚀或湿法刻蚀，可根据实际加工工艺选择具体的刻蚀方法。
第一介质层201的材料可以是氧化硅、氮氧化硅等材料，第二介质层202(HK层)的材料可以为氮氧化铪硅、钛酸锶钡、钛酸锶、钽酸锶钡等材料，且第二介电层的202的介电常数大于第一介电层201的介电常数，应变层203的材料可以为锗硅化合物，即SiGe，隔离层600的材料可以是氮化硅、氧化硅等材料，本公开的上述膜层的材料包括但不限于此，本公开不做具体限定。
在第一区域A(N1区和N2区)中功函数层的材料沉积主要为氧化镧(LaO)，在第二区域B(P1区和P2区)中功函数层的材料主要是氧化铝(AlO)，其中，第一功函数层401为氧化铝层，在第一区域A和第二区域B上形成第二介质层202后，在第一区域A和第二区域B上沉积第一功函数层401，第一函数层401可以为氧化铝层，并在第一函数层401的下方和上方分别沉积第一阻挡层301和第二阻挡层302，其中第一阻挡层301和第二阻挡层302的材料可以为氮化钛(TiN)、氮化铊等，但并不限于上述材料。
由于在第一功函数层401中包含金属氧化物，在后续的处理工艺中，需要对功函数层中的氧元素和金属元素的扩散能力进行考量，为了将第一功函数层401与第二介质层202进行阻挡，在第一功函数层401与第二介质层202之间沉积有第一阻挡层301，由于第一阻挡层301需要对功函数层中的原子具有扩散作用，为了增加第一阻挡层301对功函数层的原子的扩散能力，本公开使第一阻挡层301中的金属元素和非金属元素的比例值设置可以为小于1，比例范围值可以包括0.5-0.95，以提高功函数层中原子的扩散能力，以第一阻挡层301为氮化钛层为例，可将第 一阻挡层301中钛与氮的比例设置为0.8，即第一阻挡层301为富氮层，在后续的加工工艺中，第一功函数层401中的原子更容易通过钛氮比例为0.8的氮化钛层进行扩散。
本公开中的第一阻挡层301中金属元素和非金属元素含量的比例小于1，其范围可以为0.5-0.95，但本公开对上述比例范围不做具体限定，可以根据实际使用需求进行选择。
其中，在步骤S30中，去除第一区域A的第二阻挡层302及第一区域A的第一功函数层401后，在基底100上依次形成第二功函数层402、第三阻挡层303及第一导电层501。
由于第一区域A(N1区和N2区)的功函数层主要以氧化镧(LaO)为主，因此对于第一区域A来说，需要将第一功函数层401和第二阻挡层302去除,如图11所示，具体去除方法如下：
步骤S301：形成覆盖第一区域A的光刻胶PR，图案化第一光刻胶PR；
步骤S302：利用图案化后的光刻胶PR刻蚀去除第一区域A的第二阻挡层302及第一功函数层401。
如图5所示和图6所示，采用光刻胶PR对第一区域A进行刻蚀，去除第二阻挡层302和第一功函数层401，其中，刻蚀法可采用干法刻蚀、湿法刻蚀或者干法刻蚀和湿法刻蚀结合，具体刻蚀方法可根据实际需求进行选择，本公开不做具体限定。
如图7所示，对第一区域A进行刻蚀去除第二阻挡层302及第一功函数层401后，在基底100上依次形成第二功函数层402、第三阻挡层303及第一导电层501，其中，第二功函数层402的材料可以为氧化镧层，经过上述步骤后，在第一区域A，第二功函数层402位于第一阻挡层301和第三阻挡层303之间，在第二区域B，第二功函数层402位于第二阻挡层302和第三阻挡层303之间，并且在第三阻挡层303上沉积有第一导电层501，第一导电层501的材料可以为无掺杂多晶硅(poly)。
在本公开中，以阻挡层为氮化钛层为例，在第一区域A(N1区和N2区)内，第二功函数层402(LaO层)的下方设置有第一阻挡层301，为了使功函数层中的原子容易发生扩散，选择第一阻挡层301中钛氮比 例为0.8，在第二功函数层402(LaO层)与第一导电层501之间设置有第三阻挡层303，为了防止第二功函数层402(LaO层)向上扩散到第一导电层501中，将第三阻挡层303中钛氮比例设置为1.2，即为富钛层，由于第三阻挡层303中金属元素含量较非金属元素含量高，俘获氧元素的能量较高，电阻值减小，功函数层中的原子不易发生扩散，在后续加工工艺中，使得位于第三阻挡层303两侧的第一功函数层401与第二功函数层402中的的原子很难发生扩散，起到阻挡的作用。
在第二区域B(P1区和P2区)内，由上至下依次为第一导电层501、第三阻挡层303、第二功函数层402、第二阻挡层302、第一功函数层401及第一阻挡层301，与上述第一区域A的加工工艺原理类似，将第一阻挡层301中的钛氮比例设置为0.8，第二阻挡层302中及第三阻挡层303中钛氮比例设置为1.2，在第二阻挡层302及第三阻挡层303金属元素与非金属元素含量的比例大于1时，阻挡层俘获氧元素的能力增加，电阻减小，功函数层中的金属扩散变难，在第一阻挡层301金属元素与非金属元素含量的比例小于1时，阻挡层中电阻增大，功函数层中的金属扩散变得容易，在第二区域B中各个膜层的作用如上文所述，此处不再赘述。
在本公开中，第一阻挡层301中金属元素含量与非金属元素含量的比例小于第二阻挡层302中及第三阻挡层303中金属元素含量和非金属元素含量的比例，且第一阻挡层301中金属元素含量与非金属元素含量的比例小于1，第二阻挡层302中及第三阻挡层303中金属元素含量和非金属元素含量的比例大于1，进一步的，第一阻挡层301中金属元素含量和非金属含量的比例范围包括0.5-0.95，第二阻挡层302及第三阻挡层303中的金属元素含量和非金属元素含量的比例范围包括1.05-1.5，本公开包括但不限于上述范围值，可以根据实际使用需要确定阻挡层中金属元素与非金属元素含量的比例。
其中，在步骤S40中，对所述基底100进行热处理，以使第一区域A中的第二功函数层402中的原子扩散至第二介质层202中，使第二区域B中的第一功函数层401中的原子扩散至第二介质层202中，并在第二介质层202与第一介质层201之间发生界面相互作用。
如图8所示，在基底100上形成上述膜层后，对基底100进行热处理，以使第一介质层201和第二介质层202之间的界面发生界面相互作用，例如使第一介质层201和第二介质层202之间的界面发生偶极相互作用，偶极相互作用是极性分子间的一种相互作用，即一个极性分子带有部分正电荷的一端与另一分子带有部分负电荷的一端之间的吸引作用，极性分子因电荷分布不均时产生偶极矩，在极性分子相互靠近时，会造成电性吸引。
本公开提供的半导体制造方法中，优选的热处理工艺采用RTA(Rapid Thermal Anneal，快速热处理)工艺对基底100进行热处理，如图12所示，热处理方法包括：
步骤S401：通入第一气体并在第一温度下保持第一预设时间；
步骤S402：通入第二气体，同时在第二预设时间内使第一温度升至第二温度；
步骤S403：退火处理，保持第三预设时间。
在商户数步骤S401至步骤S403中，第一预设时间大于第二预设时间和第三预设时间，第二预设时间小于第三预设时间，即上述三种预设时间的由小到大依次为第二预设时间、第三预设时间、第一预设时间；第一气体包括惰性气体，第二气体包括氧化性气体，第一气体的流量大于第二气体的流量。
在上述热处理工艺流程中，第一气体可以为氮气、氦气等惰性气体，第一气体的流量范围包括10000-3000sccm(标准毫升/分钟)，第二气体可以为氧气等氧化性气体，第二气体的流量范围包括300-1000sccm，其中，第一气体的流量大于第二气体的流量；第一温度值范围包括300℃-800℃，第二温度范围包括400℃-1500℃，升温速率可以为50℃/S-150℃/S，其中，第二温度大于第一温度；第一预设时间可以为10S-30S(秒)，第二预设时间可以为3.3S-7.3S，第三预设时间可以为5S-15S，其中，预设时间由小到大依次为第二预设时间、第三预设时间、第一预设时间。
具体的，在热处理工艺中，可以为通入第一气体，第一气体为氮气，通入氮气的流量为20000sccm，并在第一温度下的温度下保持第一预设时间，第一温度可以为550℃，第一预设时间可以为20S；再通入第二气 体，第二气体可以为氧气，通过氧气650sccm，同时保持通入第一气体20000sccm，第一气体可以为氮气，使温度由第一温度升温至第二温度，第一温度可以为550℃，第二温度可以为950℃，升温速率可以为75℃/S，升温时间为第二预设时间，即升温时间(第二预设时间)约为5.3S；对基底100进行尖峰退火处理，温度值在第二温度保持第三预设时间，第二温度可以为950℃，第三预设时间可以为10S，同时保持通入第一气体(氮气)20000sccm，通入第二气体(氧气)650sccm。
需要说明的是，上述的热处理工艺步骤中的各个参数数值仅为示例性，具体的处理步骤中各个参数数值的选择可以根据实际工艺需求确定，本公开不做具体限定。
其中，在步骤S50中，去除第一区域A的第一导电层501、第三阻挡层303、第二功函数层402及第一阻挡层301，且去除阵列区10和第二区域B的第一导电层501、第三阻挡层303、第二功函数层402、第二阻挡层302、第一功函数层401及第一阻挡层301。
如图9所示，对基底100进行高温快速热处理工艺，快速热处理后，去除第一区域A的第一导电层501、第三阻挡层303、第二功函数层402及第一阻挡层301，同时去除阵列区10和第二区域B的第一导电层501、第三阻挡层303、第二功函数层402、第二阻挡层302、第一功函数层401及第一阻挡层301。
其中，在步骤S60中，步骤S60：于第一区域A和第二区域B上形成第四阻挡层304和第二导电层502。其中，第四阻挡层304中金属元素含量与非金属元素含量的比例与第二阻挡层302中及第三阻挡层303中金属元素含量和非金属元素含量的比例相同。
在步骤S10-步骤S50完成后，如图10所示，在第一区域A和第二区域B上沉积形成第四阻挡层304，并在第四阻挡层304上沉积第二导电层502，其中，第四阻挡层304中金属元素和非金属元素含量的比例需要大于1，由于第四阻挡层304的作用是需要俘获更多的氧元素，同时可以保证金属难以扩散，例如，第四阻挡层304为氮化钛层，钛氮比例可以为1.2，这样可以保证在半导体器件形成金属栅极后，第四阻挡层304可以防止其它膜层中金属元素的扩散。
第四阻挡层304中的金属元素含量和非金属元素含量的比例与第二阻挡层302中的金属元素含量和非金属元素含量的比例可以相同，这样可以简化半导体器件的加工工艺过程，节省加工时间，提高加工效率。
此外，第四阻挡层304中金属元素和非金属元素含量的比例大于1，其中，金属元素和非金属元素含量的比例范围可以为1.05-1.5，但本公开对上述比例的范围不进行具体限定。
第二导电层502可以为掺杂多晶硅层，或是其它适用于半导体膜层的材料，本公开不做具体限定。
上述的第一阻挡层301、第二阻挡层302、第三阻挡层303及第四阻挡层304均可采用PVD(Physical Vapor Deposition，物理气相沉积)进行沉积，其中，物理气相沉积法包括：真空蒸镀、溅射镀膜、电弧等离子体镀、离子镀膜和分子束外延等方法，本公开优选的方法为RFPVD(Radio Frequency Physical Vapor Deposition，射频物理气相沉积)进行各个阻挡膜层中的金属元素与非金属元素的比例的调节，但并不限于此种方法。
本公开提供的半导体器件制造方法，在半导体加工工艺中，通过调节不同阻挡层中金属元素和非金属元素含量的比例，使得不同的阻挡层的功能进一步增强，例如，在阻挡层附近的功函数层需要增加扩散能力时，可以将金属元素与非金属元素含量的比例调整至小于1，使得中的金属元素更加容易发生扩散，在需要增加阻挡层的阻挡作用时，可以将阻挡层中金属元素与非金属元素含量的比例调整至大于1，使得阻挡层俘获氧元素的能力变强，功函数层中的原子不易进行扩散，在半导体加工过程中，根据不同的阻挡层功能选择不同的比例，可以优化半导体加工工艺，提供器件性能。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体器件制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开还提供了一种半导体器件，运用上述的半导体器件制造方法 进行制造，如图9所示，该半导体器件包括基底100、第一介质层201、第二介质层202、阻挡层304和导电层502。
其中，基底100包括阵列区10和外围区20，外围区20包括第一区域A及第二区域B；第一介质层201位于外围区20上；第二介质层202位于第一介质层201上和阵列区10上，第一介质层201和第二介质层202之间的界面中发生界面相互作用；阻挡层304位于第二介质层202上；导电层502位于阻挡层304上；其中，阻挡层304中金属元素含量和非金属元素含量的比例大于1。
其中，第一介质层201可以为氧化硅层，第二介质层202可以为氮氧化铪硅层(HK层)，第二介质层202的介电常数大于第一介质层201的介电常数，阻挡层304可以为氮化硅层，导电层502可以为掺杂多晶硅层，但本公开膜层的材料包括但不限于上述材料，可以根据实际半导体器件的结构和加工工程选择适当的材料，本公开不做具体限定。
本公开提供的半导体器件运用上述的半导体制作方法进行制造，在加工过程中，运用金属元素与非金属元素含量比例不同的阻挡层进行加工，使得阻挡层的功能得到了进一步的优化，优化了高介电常数金属栅极的加工工艺，半导体器件的性能得到了进一步的提升。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种半导体器件制造方法，包括：
    提供基底，所述基底包括阵列区和外围区，所述外围区包括第一区域及第二区域；
    在所述基底上依次形成第一介质层、第二介质层、第一阻挡层、第一功函数层及第二阻挡层；
    去除所述第一区域的所述第二阻挡层及所述第一区域的所述第一功函数层后，在所述基底上依次形成第二功函数层、第三阻挡层及第一导电层；
    对所述基底进行热处理，以使所述第一区域中的第二功函数层中的原子扩散至所述第二介质层中，使所述第二区域中的第一功函数层中的原子扩散至所述第二介质层中，并在所述第二介质层与所述第一介质层之间发生界面相互作用；
    去除所述第一区域的所述第一导电层、所述第三阻挡层、所述第二功函数层及所述第一阻挡层，且去除所述阵列区和所述第二区域的所述第一导电层、所述第三阻挡层、所述第二功函数层、所述第二阻挡层、所述第一功函数层及所述第一阻挡层；
    于所述第一区域和所述第二区域上形成第四阻挡层和第二导电层；
    其中，所述第一阻挡层中金属元素含量与非金属元素含量的比例小于所述第二阻挡层中及所述第三阻挡层中金属元素含量和非金属元素含量的比例。
  2. 根据权利要求1所述的半导体器件制造方法，其中，所述第一阻挡层中金属元素含量与非金属元素含量的比例小于1，所述第二阻挡层中及所述第三阻挡层中金属元素含量和非金属元素含量的比例大于1。
  3. 根据权利要求2所述的半导体器件制造方法，其中，所述第一阻挡层中金属元素含量和非金属含量的比例范围包括0.5-0.95，所述第二阻挡层及所述第三阻挡层中的金属元素含量和非金属元素含量的比例范围包括1.05-1.5。
  4. 根据权利要求1所述的半导体器件制造方法，其中，所述第四阻挡层中金属元素含量和非金属元素含量的比例大于1。
  5. 根据权利要求1所述的半导体器件制造方法，其中，所述第四阻挡层中的金属元素含量和非金属元素含量的比例与所述第二阻挡层中的金属元素含量和非金属元素含量的比例相同。
  6. 根据权利要求1所述的半导体器件制造方法，其中，在所述第一区域内，功函数层中的原子扩散发生在所述第二功函数层与所述第二介质层之间，在所述第二区域内，功函数层中的原子扩散发生在所述第一功函数层与所述第二介质层之间。
  7. 根据权利要求1所述的半导体器件制造方法，其中，所述第一区域包括形成N型器件的N区，所述N区包括第一N区和第二N区；所述第二区域包括形成P型器件的P区，所述P区包括第一P区和第二P区。
  8. 根据权利要求7所述的半导体器件制造方法，其中，所述第二N区的所述第一介质层的厚度大于所述第一N区的所述第一介质层的厚度，所述第二P区的所述第一介质层的厚度大于所述第一P区的所述第一介质层的厚度。
  9. 根据权利要求8所述的半导体器件制造方法，其中，所述在所述基底上依次形成第一介质层、第二介质层、第一阻挡层、第一功函数层及第二阻挡层前，包括：
    在所述第一P区的所述基底上形成应变层。
  10. 根据权利要求1所述的半导体器件制造方法，其中，所述第二介质层的介电常数大于所述第一介质层的介电常数。
  11. 根据权利要求1所述的半导体器件制造方法，其中，所述在所述基底上依次形成第二功函数层、第三阻挡层及第一导电层，还包括：
    去除所述第二区域的第二功函数层及第三阻挡层，在所述基底上形成第一导电层。
  12. 根据权利要求1所述的半导体器件制造方法，其中，所述在所述基底上依次形成第一介质层、第二介质层、第一阻挡层、第一功函数层及第二阻挡层之前，还包括：
    在所述阵列区的所述基底上依次形成阻挡材料层和隔离层。
  13. 根据权利要求1所述的半导体器件制造方法，其中，所述在所 述基底上依次形成第一介质层、第二介质层、第一阻挡层、第一功函数层及第二阻挡层，还包括：
    去除所述阵列区的所述第一介质层。
  14. 根据权利要求1所述的半导体器件制造方法，其中，所述对所述基底进行热处理，包括：
    通入第一气体并在第一温度下保持第一预设时间；
    通入第二气体，同时在第二预设时间内将所述第一温度升至第二温度；
    退火处理，保持第三预设时间。
  15. 根据权利要求14所述的半导体器件制造方法，其中，所述第一预设时间大于所述第二预设时间和所述第三预设时间，所述第二预设时间小于所述第三预设时间。
  16. 根据权利要求14所述的半导体器件制造方法，其中，所述第一气体包括惰性气体，所述第二气体包括氧化性气体，所述第一气体的流量大于所述第二气体的流量。
  17. 根据权利要求1所述的半导体器件制造方法，其中，所述去除所述第一区域的所述第二阻挡层及所述第一区域的所述第一功函数层，包括：
    形成覆盖所述基底的光刻胶，图案化所述光刻胶；
    利用图案化后的光刻胶刻蚀去除所述第一区域的所述第二阻挡层及所述第一功函数层。
  18. 一种半导体器件，包括：
    基底，所述基底包括阵列区和外围区，所述外围区包括第一区域及第二区域；
    第一介质层，位于所述外围区上；
    第二介质层，位于所述第一介质层上和所述阵列区上，所述第一介质层和所述第二介质层之间的界面中发生界面相互作用；
    阻挡层，位于所述第二介质层上；
    导电层，位于所述阻挡层上；
    其中，所述阻挡层中金属元素含量和非金属元素含量的比例大于1。
  19. 根据权利要求18所述的半导体器件，其中，所述第二介质层的介电常数大于所述第一介质层的介电常数。
PCT/CN2022/078070 2022-01-12 2022-02-25 半导体器件及其制造方法 WO2023133972A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090048189A (ko) * 2007-11-09 2009-05-13 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조방법
CN102299155A (zh) * 2010-06-22 2011-12-28 中国科学院微电子研究所 一种半导体器件及其制造方法
CN104377236A (zh) * 2013-08-16 2015-02-25 中国科学院微电子研究所 一种栅堆叠及其制造方法
CN109728078A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN112635401A (zh) * 2019-09-24 2021-04-09 长鑫存储技术有限公司 晶体管的形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090048189A (ko) * 2007-11-09 2009-05-13 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조방법
CN102299155A (zh) * 2010-06-22 2011-12-28 中国科学院微电子研究所 一种半导体器件及其制造方法
CN104377236A (zh) * 2013-08-16 2015-02-25 中国科学院微电子研究所 一种栅堆叠及其制造方法
CN109728078A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN112635401A (zh) * 2019-09-24 2021-04-09 长鑫存储技术有限公司 晶体管的形成方法

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