WO2023133941A1 - Structure semi-conductrice et procédé de fabrication associé - Google Patents

Structure semi-conductrice et procédé de fabrication associé Download PDF

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Publication number
WO2023133941A1
WO2023133941A1 PCT/CN2022/073930 CN2022073930W WO2023133941A1 WO 2023133941 A1 WO2023133941 A1 WO 2023133941A1 CN 2022073930 W CN2022073930 W CN 2022073930W WO 2023133941 A1 WO2023133941 A1 WO 2023133941A1
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WO
WIPO (PCT)
Prior art keywords
bit line
layer
dielectric layer
substrate
line contact
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PCT/CN2022/073930
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English (en)
Chinese (zh)
Inventor
王景皓
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长鑫存储技术有限公司
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Publication of WO2023133941A1 publication Critical patent/WO2023133941A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.
  • a semiconductor structure such as a memory, includes an active area and a bit line layer on the active area, and the bit line layer is connected to the active area through a bit line plug.
  • a conventional method for forming a bit line plug includes: etching a certain depth downward from the surface of the active region to form a groove, and then filling the groove with conductive material to form a bit line plug.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • a substrate includes an active region defined by an isolation structure, the active region includes a bit line contact therein, the bit line contact and the isolation structure have a surface flush with the surface of the substrate flat top surface;
  • first dielectric layer on the substrate, the first dielectric layer covering at least the bit line contact portion and the isolation structure;
  • a bit line plug material layer is formed on the top surface of the bit line contact part and the part of the top surface of the isolation structure, and the upper surface of the bit line plug material layer is in contact with the first dielectric layer. flush with the upper surface;
  • bit line plug material layer and a part of the bit line contact portion are removed to form a bit line plug and a bit line contact region.
  • performing an etching process on the first dielectric layer includes:
  • a patterned mask layer is formed on the first dielectric layer; using the patterned mask layer as a mask, an etching process is performed on the first dielectric layer to form an opening, and the opening exposes the The top surface of the bit line contact and the portion of the top surface of the isolation structure.
  • forming a bit line plug material layer on the top surface of the bit line contact includes:
  • the substrate includes a storage area and a peripheral area; forming a first dielectric layer on the substrate includes:
  • the first dielectric layer is simultaneously formed on the storage area and the peripheral area.
  • bit line plug material layer on the top surface of the bit line contact portion further comprising: forming a first gate material layer on the peripheral region.
  • forming a first gate material layer on the peripheral region includes:
  • the oxide layer on the storage area is removed.
  • the method before removing part of the bit line plug material layer and part of the bit line contact, the method further includes:
  • bit line material layer is in contact with the bit line plug material layer
  • removing a portion of the bit line plug material layer and a portion of the bit line contact portion includes:
  • bit line capping layer and the bit line layer as a mask, perform a self-aligned etching process to remove the bit line plug material layer and the bit line contact portion not covered by the bit line layer to form bit line plugs and bit line contact areas.
  • the manufacturing method further includes: forming a third dielectric layer on the substrate, the third dielectric layer fills the gap and covers the side surface of the bit line layer and the upper surface and the upper surface of the bit line capping layer. side surface.
  • the material of the first dielectric layer includes at least one of silicon oxide and silicon nitride; the material of the second dielectric layer includes silicon nitride; the material of the third dielectric layer includes nitrogen Silicon.
  • An embodiment of the present disclosure also provides a semiconductor structure, including:
  • a substrate comprising an active region defined by isolation structures, the active region comprising a bitline contact region therein, the bitline contact region having a top surface flush with a surface of the substrate;
  • first dielectric layer located on the surface of the substrate, the first dielectric layer covers at least part of the isolation structure
  • bit line plug located in the first dielectric layer, the bit line plug is in contact with the top surface of the bit line contact region, and the upper surface of the bit line plug is in contact with the first dielectric layer The upper surface of the layer is flush.
  • the material of the bit line plug includes titanium nitride.
  • the semiconductor structure further includes: a bit line layer and a bit line capping layer disposed on the bit line layer, and the bit line layer is contact-connected to the bit line plug.
  • the bit line layer includes a first conductive layer and a second conductive layer disposed on the first conductive layer.
  • the first conductive layer includes a titanium nitride layer
  • the second conductive layer includes a tungsten layer
  • a third dielectric layer is disposed between the isolation structure and the bit line contact region, and between the first dielectric layer and the bit line plug.
  • the third dielectric layer also covers the side surfaces of the bit line layer and the upper surface and side surfaces of the bit line capping layer.
  • the material of the first dielectric layer includes at least one of silicon oxide and silicon nitride; the material of the bit line capping layer includes silicon nitride; the material of the third dielectric layer includes nitrogen Silicon.
  • the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate includes an active region defined by an isolation structure, and the active region includes bits A line contact part, the bit line contact part and the isolation structure have a top surface flush with the surface of the substrate; a first dielectric layer is formed on the substrate, and the first dielectric layer covers at least the the bit line contact portion and the isolation structure; performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure; A bit line plug material layer is formed on the top surface of the bit line contact part and the part of the top surface of the isolation structure, and the upper surface of the bit line plug material layer is connected to the upper surface of the first dielectric layer.
  • bit line plug material layer in the process of forming the bit line plug material layer, the bit line contact part and the surrounding part of the bit line contact part located in the substrate are not etched downward. structure, so that the finally formed bit line plug is located on the top surface of the bit line contact region, so that the bit line plug has a thinner thickness, which can reduce the parasitic capacitance in the semiconductor structure.
  • FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • a semiconductor structure such as a memory, includes an active area and a bit line layer on the active area, and the bit line layer is connected to the active area through a bit line plug.
  • the step of forming the bit line plug in the related art mainly includes: first, forming a thick oxide layer on the substrate; then, forming an opening on the thick oxide layer, the opening exposing the active region; The opening etches the active region down to a certain depth to form a groove; then, fills the groove and the opening with a conductive material; finally, removes the thick oxide layer and the conductive material to form the bit line plug.
  • the conductive material is polysilicon.
  • the depth of the opening and the groove is relatively large, so that when the conductive material is filled to form a bit line plug, pores are likely to be generated;
  • the thickness of the bit line plug is thicker, which will increase the parasitic capacitance in the semiconductor structure;
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, please refer to FIG. 1 for details. As shown, the method includes the following steps:
  • Step 101 providing a substrate, the substrate includes an active region defined by an isolation structure, a bit line contact is included in the active area, and the bit line contact and the isolation structure have a connection with the substrate surface flush with the top surface;
  • Step 102 forming a first dielectric layer on the substrate, the first dielectric layer covering at least the bit line contact portion and the isolation structure;
  • Step 103 performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure;
  • Step 104 forming a bit line plug material layer on the top surface of the bit line contact part and the part of the top surface of the isolation structure, the upper surface of the bit line plug material layer is connected with the first The upper surface of a dielectric layer is flush;
  • Step 105 removing part of the bit line plug material layer and part of the bit line contact portion to form a bit line plug and a bit line contact region.
  • the bit line contact part and the surrounding part of the bit line contact part located in the substrate are not etched downward. structure, so that the finally formed bit line plug is located on the top surface of the bit line contact region, so that the bit line plug has a thinner thickness, which can reduce the parasitic capacitance in the semiconductor structure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure can be used to form a dynamic random access memory (DRAM). But not limited thereto, any semiconductor structure with bit line plugs can be manufactured using the methods provided by the embodiments of the present disclosure.
  • DRAM dynamic random access memory
  • FIG. 2 to 15b are process flow diagrams of semiconductor structures provided by embodiments of the present disclosure; wherein, FIG. 2 is a schematic top view, and FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a , Fig. 11a, Fig. 12a, Fig. 13a, Fig. 14a, Fig. 15a are schematic cross-sectional structure diagrams taken along the line AA' of Fig. 2 for each process step, Fig. 3b, Fig. 4b, Fig. 5b, Fig. 6b, Fig. 7b, Fig. 8b , FIG. 9b, FIG. 10b, FIG. 11b, FIG. 12b, FIG.
  • FIG. 13b, FIG. 14b, and FIG. 15b are schematic cross-sectional structural diagrams taken along the line BB' of FIG. 2 for each process step.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to FIG. 2 to FIG. 15 b .
  • step 101 is performed, as shown in FIG. 2 to FIG. 3 b , a substrate 20 is provided, the substrate 20 includes an active area AA defined by an isolation structure 201, and the active area AA includes a bit line contact portion 202 , the bit line contact portion 202 and the isolation structure 201 have top surfaces S1 , S2 flush with the surface of the substrate 20 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 20 includes a storage region SR and a peripheral region PR, and an active region defined by an isolation structure 201 is disposed in the storage region SR and the peripheral region PR. AA. In some embodiments, the active areas AA are arranged parallel to each other in the storage area SR.
  • the material of the isolation structure 201 may include one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride) and oxynitrides (such as silicon oxynitride).
  • the substrate 20 is further provided with word lines WL, the number of the word lines WL is multiple, and the multiple word lines WL extend in the storage region SR along the same direction, so The bit line contact portion 202 is located between two adjacent word lines WL.
  • the material of the word line WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination.
  • the substrate 20 further includes an insulating structure 205 burying the word line WL, and the material of the insulating structure 205 includes but not limited to nitride, such as silicon nitride.
  • the word line WL is separated from the substrate 20 by a first gate dielectric layer 204 .
  • the material of the first gate dielectric layer 204 includes but not limited to oxide, such as silicon oxide.
  • the active area AA located in the storage area SR further includes storage node contacts 203 located at both ends of the active area AA, the storage node contacts 203 are connected to the bit line contacts 202 separated by the word line WL and the insulating structure 205 .
  • the storage node contact portion 203 and the bit line contact portion 202 may be formed on the top of the active region AA by means of ion implantation.
  • the conductivity type of the storage node contact portion 203 and the bit line contact portion 202 is the same, such as n-type. Understandably, when the storage node contact portion 203 and the bit line contact portion 202 are n-type doped, the substrate 20 below the storage node contact portion 203 and the bit line contact portion 202 has p type doping.
  • step 102 is performed, as shown in FIGS. Structure 201.
  • forming the first dielectric layer 21 on the substrate 20 includes: simultaneously forming the first dielectric layer 21 on the storage region SR and the peripheral region PR. Specifically, the first dielectric layer 21 covers the active area AA, the isolation structure 201 and the insulation structure 205 .
  • the first dielectric layer 21 can be formed on the substrate 20 by atomic layer deposition (ALD), chemical vapor deposition (CVD) and other processes.
  • the material of the first dielectric layer 21 includes at least one of silicon oxide and silicon nitride.
  • the first dielectric layer 21 may have a multilayer structure.
  • the first dielectric layer 21 includes a silicon oxide sublayer and a silicon nitride sublayer, and the silicon nitride sublayer is formed on the silicon oxide sublayer. layer above.
  • step 103 is performed, as shown in FIGS. 5a to 6b, an etching process is performed on the first dielectric layer 21 to expose the top surface S1 of the bit line contact portion 202 and the isolation structure 201 Part of the top surface S3.
  • performing an etching process on the first dielectric layer 21 includes:
  • an etching process is performed on the first dielectric layer 21 to form an opening T, and the opening T exposes the top surface S1 of the bit line contact portion 202 And the part of the top surface S3 of the isolation structure 201 , as shown in FIG. 6 a to FIG. 6 b .
  • the patterned mask layer 22 is removed.
  • the patterned mask layer 22 is a photoresist layer.
  • a photoresist layer instead of the thick oxide layer mentioned in the related art has at least the following technical effects: on the one hand, the first dielectric layer 21 and the substrate 20 will not be damaged when the photoresist layer is removed on the other hand, remove the patterned mask layer 22 before filling the opening T with the conductive material 23 (see FIGS.
  • the conductive material 23 needs to be filled with a shallow , which is beneficial to reduce the porosity of the conductive material 23 in the opening T; in addition, when the opening T is formed, the bit line contact portion 202 and the surrounding bit line contact portion are not etched downward. 202 of the isolation structure 201 and the insulation structure 205, so that the opening T has a relatively shallow depth, which further reduces the porosity of the conductive material 23 in the opening T, and the process is simple and saves The manufacturing cost of the semiconductor structure.
  • the opening T also exposes part of the top surface of the insulating structure 205 , as shown in FIG. 6 b .
  • the opening T exposes the top surface S1 of the bit line contact portion 202 and part of the top surface of the insulating structure 205 and the isolation structure 201 surrounding the bit line contact portion 202, so that subsequent formation
  • the bit line plug material layer 23a (see FIG. 8a to FIG. 8b ) has the maximum contact area with the bit line contact portion 202, reducing the bit line plug 23b (see FIG. 11a to FIG. 11b ) and bit line formed subsequently.
  • Contact resistance between wire contact areas 202a see Figures 11a-11b).
  • step 104 is performed, as shown in FIGS. 7a to 8b, a bit line plug material is formed on the top surface S1 of the bit line contact portion 202 and the part of the top surface S3 of the isolation structure 201 Layer 23a, the upper surface of the bit line plug material layer 23a is flush with the upper surface of the first dielectric layer 21 .
  • bit line plug material layer 23a is formed on the top surface S1 of the bit line contact portion 202, including:
  • the upper surface of the bit line plug material layer 23a is in contact with the first The upper surface of the dielectric layer 21 is flush, as shown in FIGS. 8 a to 8 b.
  • the conductive material 23 can be formed on the substrate 20 by a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • the first dielectric layer 21 and the conductive material 23 above the opening T are removed by dry etching or chemical mechanical polishing.
  • the conductive material 23 is titanium nitride, which has better conductivity than the polysilicon mentioned in the related art, so that the finally formed bit line plug 23b (see FIG. 11a to FIG. 11b) and the bit line contact region 202a (see FIGS. 11a-11b ) have a smaller contact resistance.
  • the conductive material 23 may also be other materials with good electrical conductivity, for example, tungsten, tungsten nitride, titanium and so on.
  • bit line plug material layer 23a on the top surface S1 of the bit line contact portion 202, further comprising: forming a first gate material layer 26 on the peripheral region PR, As shown in Figure 9a to Figure 12b.
  • the first gate material layer 26 is formed on the peripheral region PR, including:
  • the oxide layer 24 covers the first dielectric layer 21, as shown in FIGS. 9a to 9b;
  • the oxide layer 24 on the storage region SR is removed, as shown in FIGS. 12a to 12b.
  • a first gate material layer 26 is also formed on the oxide layer 24 of the storage region SR.
  • the first gate material layer 26 on the peripheral region PR before forming the first gate material layer 26 on the peripheral region PR, it further includes forming a second gate dielectric material layer 25 on the peripheral region PR.
  • the material of the second gate dielectric material layer 25 includes oxide, such as silicon oxide.
  • the material of the first gate material layer 26 includes but not limited to polysilicon. In a specific embodiment, after forming the first gate material layer 26 on the peripheral region PR, it further includes doping the first gate material layer 26 on the peripheral region PR to improve the The electrical conductivity of the first gate material layer 26 is described above.
  • step 105 is performed, as shown in FIG. 14a to FIG. 14b , part of the bit line plug material layer 23a and part of the bit line contact portion 202 are removed to form a bit line plug 23b and a bit line contact region 202a.
  • the method before removing part of the bit line plug material layer 23a and part of the bit line contact portion 202, the method further includes: forming a bit line material layer 27 on the substrate 20, The bit line material layer 27 is in contact with the bit line plug material layer 23a, and a second dielectric layer 28 is formed on the bit line material layer 27, as shown in FIGS. 13a to 13b; The second dielectric layer 28 is used to form a bit line capping layer 28a; the bit line material layer 27 is etched to form a bit line layer 27a, as shown in FIGS. 14a to 14b.
  • the bit line material layer 27 and the second dielectric layer 28 are also formed on the peripheral region PR, as shown in FIG.
  • a gate capping layer 28b is formed, and a second gate layer 27b is etched while forming the bit line layer 27a, as shown in FIG. 14b.
  • removing part of the bit line plug material layer 23a and part of the bit line contact portion 202 includes: using the bit line capping layer 28a and the bit line layer 27a as a mask , performing a self-aligned etching process to remove the bit line plug material layer 23a and the bit line contact portion 202 not covered by the bit line layer 27a to form a bit line plug 23b and a bit line contact region 202a.
  • the first gate material layer 26 and the second gate dielectric material layer 25 are etched to form the first gate. electrode layer 26a and the second gate dielectric layer 25a. But not limited thereto, the first gate layer 26 a and the second gate dielectric layer 25 a may not be formed simultaneously with the bit line plug 23 b and the bit line contact region 202 a.
  • the second dielectric layer 28 and the bit line material layer 27 may be etched from top to bottom along a direction perpendicular to the substrate 20 in the same process to form the bit line capping layer 28a , the bit line layer 27a, and then continue to etch the bit line plug material layer 23a and the bit line contact portion 202 using the bit line capping layer 28a and the bit line layer 27a as a mask to form the bit line The bit line plug 23b and the bit line contact region 202a.
  • the bit line material layer 27 includes a first sub-layer 271 and a second sub-layer 272 disposed on the first sub-layer 271 .
  • the etching the bit line material layer 27 to form the bit line layer 27a includes: etching the second sub-layer 272 to form a second conductive layer 272a; etching the first sub-layer 271 to form a first conductive layer 271a.
  • the etching and forming the second gate layer 27b while etching the bit line layer 27a includes: etching the second sublayer 272 to form a second gate conductive layer 272b; etching the first sublayer 271 to form a first gate conductive layer 271b.
  • the material of the first sub-layer 271 includes but not limited to titanium nitride
  • the material of the second sub-layer 272 includes but not limited to tungsten
  • the material of the second dielectric layer 28 includes but not limited to nitride, such as silicon nitride.
  • the manufacturing method further includes: forming a third dielectric layer 29 on the substrate 20, the third dielectric layer 29 fills the gap and covers the side surface of the bit line layer 27a and the The upper and side surfaces of the bit line capping layer 28a form a protection structure.
  • the third dielectric layer 29 also covers the gate capping layer 28b, the second gate layer 27b, the first gate layer 26a, the second gate dielectric layer 25a located on the peripheral region PR. formed gate stack.
  • the formation method of the third dielectric layer 29 includes but not limited to atomic layer deposition (ALD).
  • the material of the third dielectric layer 29 includes but not limited to nitride, such as silicon nitride.
  • a storage node contact plug will be formed above the storage node contact portion 203, and filling the gap with the third dielectric layer 29 can reduce the size of the bit line contact region 202a, the The parasitic capacitance between the bit line plug 23b and the storage node contact portion 203 and part of the storage node contact plug.
  • bit line contact portion 202 and surrounding areas of the bit line contact portion 202 are not etched downward.
  • the isolation structure 201 and the insulating structure 205 make the finally formed bit line plug 23b located on the top surface of the bit line contact region 202a, so that the bit line plug 23b has a relatively thin thickness, which can Reduce parasitic capacitance within semiconductor structures.
  • An embodiment of the present disclosure also provides a semiconductor structure, as shown in FIG. 2 and FIG. 15a to FIG.
  • the source area AA includes a bit line contact area 202a, the bit line contact area 202a has a top surface flush with the surface of the substrate 20; the first dielectric layer 21 is located on the surface of the substrate 20 , the first dielectric layer 21 covers at least part of the isolation structure 201; the bit line plug 23b is located in the first dielectric layer 21, and the bit line plug 23b is connected to the bit line contact region 202a. contact with the top surface, and the upper surface of the bit line plug 23 b is flush with the upper surface of the first dielectric layer 21 .
  • the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
  • the substrate is a silicon substrate, which may be doped or undoped.
  • the substrate 20 includes a storage region SR and a peripheral region PR, and an active region defined by an isolation structure 201 is disposed in the storage region SR and the peripheral region PR. AA. In some embodiments, the active areas AA are arranged parallel to each other in the storage area SR.
  • the material of the isolation structure 201 may include one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride) and oxynitrides (such as silicon oxynitride).
  • the first dielectric layer 21 is located on the storage region SR.
  • the material of the first dielectric layer 21 includes at least one of silicon oxide and silicon nitride.
  • the first dielectric layer 21 may have a multilayer structure.
  • the first dielectric layer 21 includes a silicon oxide sublayer and a silicon nitride sublayer, and the silicon nitride sublayer is formed on the silicon oxide sublayer. layer above.
  • the substrate 20 is further provided with word lines WL, the number of the word lines WL is multiple, and the multiple word lines WL extend in the storage region SR along the same direction, so The bit line contact region 202a is located between two adjacent word lines WL.
  • the material of the word line WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination.
  • the substrate 20 further includes an insulating structure 205 burying the word line WL, and the material of the insulating structure 205 includes but not limited to nitride, such as silicon nitride.
  • the word line WL is separated from the substrate 20 by a first gate dielectric layer 204 .
  • the material of the first gate dielectric layer 204 includes but not limited to oxide, such as silicon oxide.
  • the active area AA located in the storage area SR further includes storage node contact portions 203 located at both ends of the active area AA, and the storage node contact portion 203 is connected to the bit line contact area 202a separated by the word line WL and the insulating structure 205 .
  • the storage node contact portion 203 and the bit line contact region 202a may be formed on the top of the active region AA by ion implantation.
  • the conductivity type of the storage node contact portion 203 and the bit line contact region 202a is the same, such as n-type. It can be understood that when the storage node contact portion 203 and the bit line contact region 202a are n-type doped, the substrate 20 below the storage node contact portion 203 and the bit line contact region 202a has p type doping.
  • the material of the bit line plug 23b includes titanium nitride, which has better electrical conductivity than polysilicon mentioned in the related art, and can effectively reduce the contact between the bit line plug 23b and The contact resistance between the bit line contact regions 202a.
  • the bit line plug 23b can also be made of other materials with good electrical conductivity, for example, tungsten, tungsten nitride, titanium, and the like.
  • the semiconductor structure further includes: a bit line layer 27a and a bit line capping layer 28a disposed on the bit line layer 27a, the bit line layer 27a is in contact with the bit line plug 23b .
  • the bit line layer 27a includes a first conductive layer 271a and a second conductive layer 272a disposed on the first conductive layer 271a.
  • the first conductive layer 271a includes a titanium nitride layer
  • the second conductive layer 272a includes a tungsten layer.
  • the material of the bit line capping layer 28a includes silicon nitride.
  • a third dielectric layer 29 is disposed between the isolation structure 201 and the bit line contact region 202a, and between the first dielectric layer 21 and the bit line plug 23b.
  • a storage node contact plug will be formed on the storage node contact portion 203 later, and the third dielectric layer 29 can reduce the size of the bit line contact region 202a, the bit line plug 23b and The parasitic capacitance between the storage node contact portion 203 and part of the storage node contact plug.
  • the third dielectric layer 29 also covers the side surfaces of the bit line layer 27 a and the upper surface and side surfaces of the bit line capping layer 28 a to form a protection structure.
  • the material of the third dielectric layer 29 includes but not limited to nitride, such as silicon nitride.
  • the semiconductor structure further includes a second gate dielectric layer 25a, a first gate layer, and a second gate dielectric layer 25a stacked in the peripheral region PR from bottom to top in a direction perpendicular to the substrate 20.
  • 26a, a second gate layer 27b and a gate capping layer 28b, the second gate dielectric layer 25a is in contact with the active region AA.
  • the second gate layer 27b includes a first gate conductive layer 271b and a second gate conductive layer 272b, and the first gate conductive layer 271b is inscribed with the first gate conductive layer 271a.
  • the second gate conductive layer 272b and the second conductive layer 272a are formed by etching the same material layer; the gate capping layer 28b and the bit line capping layer 28a are etched the same Layers of material are formed.
  • the third dielectric layer 29 also covers the second gate dielectric layer 25a, the first gate layer 26a, the side surfaces of the second gate layer 27b and the gate The upper surface and side surfaces of the cover layer 28b.
  • the material of the first gate layer 26 a includes doped or undoped polysilicon.
  • the material of the second gate dielectric layer 25a includes oxide, such as silicon oxide.
  • bit line plug is located in the first dielectric layer, and the upper surface of the bit line plug is flush with the upper surface of the first dielectric layer, that is, the bit line The plug is located on the top surface of the bit line contact region, and the bit line plug has a relatively thin thickness, which can reduce parasitic capacitance in the semiconductor structure.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure semi-conductrice et un procédé de fabrication associé. Le procédé de fabrication comprend : la fourniture d'un substrat (20), le substrat (20) comprenant une région active (AA) définie par une structure d'isolation (201), la région active (AA) comprenant une partie de contact de ligne de bits (202), et la partie de contact de ligne de bits (202) et la structure d'isolation (201) ayant des surfaces supérieures qui affleurent la surface du substrat (20) ; la formation d'une première couche diélectrique (21) sur le substrat (20), la première couche diélectrique (21) recouvrant au moins la partie de contact de ligne de bits (202) et la structure d'isolation (201) ; la réalisation d'un processus de gravure sur la première couche diélectrique (21) pour exposer la surface supérieure de la partie de contact de ligne de bits (202) et une partie de la surface supérieure de la structure d'isolation (201) ; la formation d'une couche de matériau de fiche de ligne de bits (23a) sur la surface supérieure de la partie de contact de ligne de bits (202) et la partie de la surface supérieure de la structure d'isolation (201), la surface supérieure de la couche de matériau de fiche de ligne de bits (23a) affleurant la surface supérieure de la première couche diélectrique (21) ; et le retrait d'une partie de la couche de matériau de fiche de ligne de bits (23a) et d'une partie de la partie de contact de ligne de bits (202) pour former une fiche de ligne de bits (23b) et une région de contact de ligne de bits (202a).
PCT/CN2022/073930 2022-01-13 2022-01-26 Structure semi-conductrice et procédé de fabrication associé WO2023133941A1 (fr)

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CN202210047074.5A CN114400205A (zh) 2022-01-13 2022-01-13 一种半导体结构及其制造方法

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080299760A1 (en) * 2007-02-28 2008-12-04 Elpida Memory, Inc. Method for manufacturing a semiconductor device
US20120205805A1 (en) * 2011-02-16 2012-08-16 Chan Sun Hyun Semiconductor device and method of manufacturing the same
CN112864087A (zh) * 2021-01-08 2021-05-28 长鑫存储技术有限公司 半导体结构及其制作方法
CN113035871A (zh) * 2021-03-04 2021-06-25 长鑫存储技术有限公司 半导体结构及其制造方法
CN113629145A (zh) * 2020-05-09 2021-11-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080299760A1 (en) * 2007-02-28 2008-12-04 Elpida Memory, Inc. Method for manufacturing a semiconductor device
US20120205805A1 (en) * 2011-02-16 2012-08-16 Chan Sun Hyun Semiconductor device and method of manufacturing the same
CN113629145A (zh) * 2020-05-09 2021-11-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112864087A (zh) * 2021-01-08 2021-05-28 长鑫存储技术有限公司 半导体结构及其制作方法
CN113035871A (zh) * 2021-03-04 2021-06-25 长鑫存储技术有限公司 半导体结构及其制造方法

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