WO2023133941A1

WO2023133941A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2023133941A1
Application number: PCT/CN2022/073930
Authority: WO
Inventors: 王景皓
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-13
Filing date: 2022-01-26
Publication date: 2023-07-20
Also published as: CN114400205A

Abstract

A semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a substrate (20), wherein the substrate (20) comprises an active region (AA) defined by an isolation structure (201), the active region (AA) comprises a bit line contact portion (202), and the bit line contact portion (202) and the isolation structure (201) have top surfaces that are flush with the surface of the substrate (20); forming a first dielectric layer (21) on the substrate (20), the first dielectric layer (21) at least covering the bit line contact portion (202) and the isolation structure (201); performing an etching process on the first dielectric layer (21) to expose the top surface of the bit line contact portion (202) and part of the top surface of the isolation structure (201); forming a bit line plug material layer (23a) on the top surface of the bit line contact part (202) and the part of the top surface of the isolation structure (201), the upper surface of the bit line plug material layer (23a) being flush with the upper surface of the first dielectric layer (21); and removing part of the bit line plug material layer (23a) and part of the bit line contact portion (202) to form a bit line plug (23b) and a bit line contact region (202a).

Description

A kind of semiconductor structure and its manufacturing method

related cross-references

This disclosure is based on the Chinese patent application with the application number 202210047074.5, the filing date is January 13, 2022, and the title of the invention is "a semiconductor structure and its manufacturing method", and claims the priority of the Chinese patent application. The Chinese patent The entire content of the application is hereby incorporated by reference into this disclosure.

technical field

The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

A semiconductor structure, such as a memory, includes an active area and a bit line layer on the active area, and the bit line layer is connected to the active area through a bit line plug. A conventional method for forming a bit line plug includes: etching a certain depth downward from the surface of the active region to form a groove, and then filling the groove with conductive material to form a bit line plug.

However, the electrical performance of the bit line plug formed by the above-mentioned conventional method is poor.

Contents of the invention

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

A substrate is provided, the substrate includes an active region defined by an isolation structure, the active region includes a bit line contact therein, the bit line contact and the isolation structure have a surface flush with the surface of the substrate flat top surface;

forming a first dielectric layer on the substrate, the first dielectric layer covering at least the bit line contact portion and the isolation structure;

performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure;

A bit line plug material layer is formed on the top surface of the bit line contact part and the part of the top surface of the isolation structure, and the upper surface of the bit line plug material layer is in contact with the first dielectric layer. flush with the upper surface;

A part of the bit line plug material layer and a part of the bit line contact portion are removed to form a bit line plug and a bit line contact region.

In some embodiments, performing an etching process on the first dielectric layer includes:

A patterned mask layer is formed on the first dielectric layer; using the patterned mask layer as a mask, an etching process is performed on the first dielectric layer to form an opening, and the opening exposes the The top surface of the bit line contact and the portion of the top surface of the isolation structure.

In some embodiments, forming a bit line plug material layer on the top surface of the bit line contact includes:

forming a conductive material on the substrate, the conductive material filling the opening and covering the first dielectric layer;

removing the first dielectric layer and the conductive material above the opening to obtain the bit line plug material layer, the upper surface of the bit line plug material layer and the upper surface of the first dielectric layer flush.

In some embodiments, the substrate includes a storage area and a peripheral area; forming a first dielectric layer on the substrate includes:

The first dielectric layer is simultaneously formed on the storage area and the peripheral area.

In some embodiments, after forming the bit line plug material layer on the top surface of the bit line contact portion, further comprising: forming a first gate material layer on the peripheral region.

In some embodiments, forming a first gate material layer on the peripheral region includes:

forming an oxide layer on the substrate, the oxide layer covering the first dielectric layer;

removing the first dielectric layer and the oxide layer on the peripheral region;

forming a first gate material layer on the peripheral region;

The oxide layer on the storage area is removed.

In some embodiments, before removing part of the bit line plug material layer and part of the bit line contact, the method further includes:

forming a bit line material layer on the substrate, the bit line material layer is in contact with the bit line plug material layer;

forming a second dielectric layer on the bit line material layer;

Etching the second dielectric layer to form a bit line capping layer; etching the bit line material layer to form a bit line layer.

In some embodiments, removing a portion of the bit line plug material layer and a portion of the bit line contact portion includes:

Using the bit line capping layer and the bit line layer as a mask, perform a self-aligned etching process to remove the bit line plug material layer and the bit line contact portion not covered by the bit line layer to form bit line plugs and bit line contact areas.

In some embodiments, there is a gap on both sides of the bit line plug and the bit line contact region, and the gap is formed by removing part of the bit line plug material layer and part of the bit line contact part. of;

The manufacturing method further includes: forming a third dielectric layer on the substrate, the third dielectric layer fills the gap and covers the side surface of the bit line layer and the upper surface and the upper surface of the bit line capping layer. side surface.

In some embodiments, the material of the first dielectric layer includes at least one of silicon oxide and silicon nitride; the material of the second dielectric layer includes silicon nitride; the material of the third dielectric layer includes nitrogen Silicon.

An embodiment of the present disclosure also provides a semiconductor structure, including:

a substrate comprising an active region defined by isolation structures, the active region comprising a bitline contact region therein, the bitline contact region having a top surface flush with a surface of the substrate;

a first dielectric layer located on the surface of the substrate, the first dielectric layer covers at least part of the isolation structure;

a bit line plug located in the first dielectric layer, the bit line plug is in contact with the top surface of the bit line contact region, and the upper surface of the bit line plug is in contact with the first dielectric layer The upper surface of the layer is flush.

In some embodiments, the material of the bit line plug includes titanium nitride.

In some embodiments, the semiconductor structure further includes: a bit line layer and a bit line capping layer disposed on the bit line layer, and the bit line layer is contact-connected to the bit line plug.

In some embodiments, the bit line layer includes a first conductive layer and a second conductive layer disposed on the first conductive layer.

In some embodiments, the first conductive layer includes a titanium nitride layer, and the second conductive layer includes a tungsten layer.

In some embodiments, a third dielectric layer is disposed between the isolation structure and the bit line contact region, and between the first dielectric layer and the bit line plug.

In some embodiments, the third dielectric layer also covers the side surfaces of the bit line layer and the upper surface and side surfaces of the bit line capping layer.

In some embodiments, the material of the first dielectric layer includes at least one of silicon oxide and silicon nitride; the material of the bit line capping layer includes silicon nitride; the material of the third dielectric layer includes nitrogen Silicon.

The semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, wherein, the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate includes an active region defined by an isolation structure, and the active region includes bits A line contact part, the bit line contact part and the isolation structure have a top surface flush with the surface of the substrate; a first dielectric layer is formed on the substrate, and the first dielectric layer covers at least the the bit line contact portion and the isolation structure; performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure; A bit line plug material layer is formed on the top surface of the bit line contact part and the part of the top surface of the isolation structure, and the upper surface of the bit line plug material layer is connected to the upper surface of the first dielectric layer. flush; removing part of the bit line plug material layer and part of the bit line contact portion to form a bit line plug and a bit line contact region. In the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, in the process of forming the bit line plug material layer, the bit line contact part and the surrounding part of the bit line contact part located in the substrate are not etched downward. structure, so that the finally formed bit line plug is located on the top surface of the bit line contact region, so that the bit line plug has a thinner thickness, which can reduce the parasitic capacitance in the semiconductor structure.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

2 to 15b are process flow charts of the semiconductor structure provided by the embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. , adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Whereas a second element, component, region, layer or section is discussed, it does not indicate that the present disclosure necessarily presents a first element, component, region, layer or section.

Spatial terms such as "below...", "below...", "below", "below...", "on...", "above" and so on, can be used here for convenience are used in description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

A semiconductor structure, such as a memory, includes an active area and a bit line layer on the active area, and the bit line layer is connected to the active area through a bit line plug. The step of forming the bit line plug in the related art mainly includes: first, forming a thick oxide layer on the substrate; then, forming an opening on the thick oxide layer, the opening exposing the active region; The opening etches the active region down to a certain depth to form a groove; then, fills the groove and the opening with a conductive material; finally, removes the thick oxide layer and the conductive material to form the bit line plug. Typically, the conductive material is polysilicon.

There are at least the following problems in the method provided by the above-mentioned related art: First, the depth of the opening and the groove is relatively large, so that when the conductive material is filled to form a bit line plug, pores are likely to be generated; The thickness of the bit line plug is thicker, which will increase the parasitic capacitance in the semiconductor structure; third, when removing the thick oxide layer and the conductive material in the opening, it is difficult to achieve a completely uniform etching depth, which will damage the substrate in the substrate. structure; Fourth, the conductivity of polysilicon is poor, and the contact resistance between the bit line plug and the active area is relatively large.

Based on this, the following technical solutions of the disclosed embodiments are proposed:

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, please refer to FIG. 1 for details. As shown, the method includes the following steps:

Step 101, providing a substrate, the substrate includes an active region defined by an isolation structure, a bit line contact is included in the active area, and the bit line contact and the isolation structure have a connection with the substrate surface flush with the top surface;

Step 102, forming a first dielectric layer on the substrate, the first dielectric layer covering at least the bit line contact portion and the isolation structure;

Step 103, performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure;

Step 104, forming a bit line plug material layer on the top surface of the bit line contact part and the part of the top surface of the isolation structure, the upper surface of the bit line plug material layer is connected with the first The upper surface of a dielectric layer is flush;

Step 105 , removing part of the bit line plug material layer and part of the bit line contact portion to form a bit line plug and a bit line contact region.

In the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, in the process of forming the bit line plug material layer, the bit line contact part and the surrounding part of the bit line contact part located in the substrate are not etched downward. structure, so that the finally formed bit line plug is located on the top surface of the bit line contact region, so that the bit line plug has a thinner thickness, which can reduce the parasitic capacitance in the semiconductor structure.

The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure can be used to form a dynamic random access memory (DRAM). But not limited thereto, any semiconductor structure with bit line plugs can be manufactured using the methods provided by the embodiments of the present disclosure.

The specific implementation manners of the present disclosure will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of illustration, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

2 to 15b are process flow diagrams of semiconductor structures provided by embodiments of the present disclosure; wherein, FIG. 2 is a schematic top view, and FIG. 3a, FIG. 4a, FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a , Fig. 11a, Fig. 12a, Fig. 13a, Fig. 14a, Fig. 15a are schematic cross-sectional structure diagrams taken along the line AA' of Fig. 2 for each process step, Fig. 3b, Fig. 4b, Fig. 5b, Fig. 6b, Fig. 7b, Fig. 8b , FIG. 9b, FIG. 10b, FIG. 11b, FIG. 12b, FIG. 13b, FIG. 14b, and FIG. 15b are schematic cross-sectional structural diagrams taken along the line BB' of FIG. 2 for each process step. The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to FIG. 2 to FIG. 15 b .

First, step 101 is performed, as shown in FIG. 2 to FIG. 3 b , a substrate 20 is provided, the substrate 20 includes an active area AA defined by an isolation structure 201, and the active area AA includes a bit line contact portion 202 , the bit line contact portion 202 and the isolation structure 201 have top surfaces S1 , S2 flush with the surface of the substrate 20 .

The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI A compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

As shown in FIG. 2 , in one embodiment, the substrate 20 includes a storage region SR and a peripheral region PR, and an active region defined by an isolation structure 201 is disposed in the storage region SR and the peripheral region PR. AA. In some embodiments, the active areas AA are arranged parallel to each other in the storage area SR. The material of the isolation structure 201 may include one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride) and oxynitrides (such as silicon oxynitride).

In one embodiment, the substrate 20 is further provided with word lines WL, the number of the word lines WL is multiple, and the multiple word lines WL extend in the storage region SR along the same direction, so The bit line contact portion 202 is located between two adjacent word lines WL. The material of the word line WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination.

In one embodiment, the substrate 20 further includes an insulating structure 205 burying the word line WL, and the material of the insulating structure 205 includes but not limited to nitride, such as silicon nitride. In some embodiments, the word line WL is separated from the substrate 20 by a first gate dielectric layer 204 . The material of the first gate dielectric layer 204 includes but not limited to oxide, such as silicon oxide.

In one embodiment, the active area AA located in the storage area SR further includes storage node contacts 203 located at both ends of the active area AA, the storage node contacts 203 are connected to the bit line contacts 202 separated by the word line WL and the insulating structure 205 .

Here, the storage node contact portion 203 and the bit line contact portion 202 may be formed on the top of the active region AA by means of ion implantation. In a specific embodiment, the conductivity type of the storage node contact portion 203 and the bit line contact portion 202 is the same, such as n-type. Understandably, when the storage node contact portion 203 and the bit line contact portion 202 are n-type doped, the substrate 20 below the storage node contact portion 203 and the bit line contact portion 202 has p type doping.

Next, step 102 is performed, as shown in FIGS. Structure 201.

In one embodiment, forming the first dielectric layer 21 on the substrate 20 includes: simultaneously forming the first dielectric layer 21 on the storage region SR and the peripheral region PR. Specifically, the first dielectric layer 21 covers the active area AA, the isolation structure 201 and the insulation structure 205 .

The first dielectric layer 21 can be formed on the substrate 20 by atomic layer deposition (ALD), chemical vapor deposition (CVD) and other processes. In one embodiment, the material of the first dielectric layer 21 includes at least one of silicon oxide and silicon nitride. The first dielectric layer 21 may have a multilayer structure. In a specific embodiment, the first dielectric layer 21 includes a silicon oxide sublayer and a silicon nitride sublayer, and the silicon nitride sublayer is formed on the silicon oxide sublayer. layer above.

Next, step 103 is performed, as shown in FIGS. 5a to 6b, an etching process is performed on the first dielectric layer 21 to expose the top surface S1 of the bit line contact portion 202 and the isolation structure 201 Part of the top surface S3.

Specifically, performing an etching process on the first dielectric layer 21 includes:

Forming a patterned mask layer 22 on the first dielectric layer 21, as shown in FIGS. 5a to 5b;

Using the patterned mask layer 22 as a mask, an etching process is performed on the first dielectric layer 21 to form an opening T, and the opening T exposes the top surface S1 of the bit line contact portion 202 And the part of the top surface S3 of the isolation structure 201 , as shown in FIG. 6 a to FIG. 6 b .

Referring to FIGS. 6 a to 6 b again, in one embodiment, after the opening T is formed, the patterned mask layer 22 is removed. Optionally, the patterned mask layer 22 is a photoresist layer. Using a photoresist layer instead of the thick oxide layer mentioned in the related art has at least the following technical effects: on the one hand, the first dielectric layer 21 and the substrate 20 will not be damaged when the photoresist layer is removed on the other hand, remove the patterned mask layer 22 before filling the opening T with the conductive material 23 (see FIGS. 7a to 7b ), so that the conductive material 23 needs to be filled with a shallow , which is beneficial to reduce the porosity of the conductive material 23 in the opening T; in addition, when the opening T is formed, the bit line contact portion 202 and the surrounding bit line contact portion are not etched downward. 202 of the isolation structure 201 and the insulation structure 205, so that the opening T has a relatively shallow depth, which further reduces the porosity of the conductive material 23 in the opening T, and the process is simple and saves The manufacturing cost of the semiconductor structure.

In an embodiment, the opening T also exposes part of the top surface of the insulating structure 205 , as shown in FIG. 6 b . In other words, the opening T exposes the top surface S1 of the bit line contact portion 202 and part of the top surface of the insulating structure 205 and the isolation structure 201 surrounding the bit line contact portion 202, so that subsequent formation The bit line plug material layer 23a (see FIG. 8a to FIG. 8b ) has the maximum contact area with the bit line contact portion 202, reducing the bit line plug 23b (see FIG. 11a to FIG. 11b ) and bit line formed subsequently. Contact resistance between wire contact areas 202a (see Figures 11a-11b).

Next, step 104 is performed, as shown in FIGS. 7a to 8b, a bit line plug material is formed on the top surface S1 of the bit line contact portion 202 and the part of the top surface S3 of the isolation structure 201 Layer 23a, the upper surface of the bit line plug material layer 23a is flush with the upper surface of the first dielectric layer 21 .

Specifically, a bit line plug material layer 23a is formed on the top surface S1 of the bit line contact portion 202, including:

Forming a conductive material 23 on the substrate 20, the conductive material 23 filling the opening T and covering the first dielectric layer 21, as shown in FIGS. 7a to 7b;

removing the first dielectric layer 21 and the conductive material 23 above the opening T to obtain the bit line plug material layer 23a, the upper surface of the bit line plug material layer 23a is in contact with the first The upper surface of the dielectric layer 21 is flush, as shown in FIGS. 8 a to 8 b.

The conductive material 23 can be formed on the substrate 20 by a chemical vapor deposition (CVD) process. Optionally, after filling the opening T with the conductive material 23, the first dielectric layer 21 and the conductive material 23 above the opening T are removed by dry etching or chemical mechanical polishing. . In one embodiment, the conductive material 23 is titanium nitride, which has better conductivity than the polysilicon mentioned in the related art, so that the finally formed bit line plug 23b (see FIG. 11a to FIG. 11b) and the bit line contact region 202a (see FIGS. 11a-11b ) have a smaller contact resistance. But not limited thereto, the conductive material 23 may also be other materials with good electrical conductivity, for example, tungsten, tungsten nitride, titanium and so on.

In one embodiment, after forming the bit line plug material layer 23a on the top surface S1 of the bit line contact portion 202, further comprising: forming a first gate material layer 26 on the peripheral region PR, As shown in Figure 9a to Figure 12b.

Specifically, the first gate material layer 26 is formed on the peripheral region PR, including:

Forming an oxide layer 24 on the substrate 20, the oxide layer 24 covers the first dielectric layer 21, as shown in FIGS. 9a to 9b;

removing the first dielectric layer 21 and the oxide layer 24 on the peripheral region PR, as shown in FIGS. 10a to 10b;

forming a first gate material layer 26 on the peripheral region PR, as shown in FIGS. 11a to 11b;

The oxide layer 24 on the storage region SR is removed, as shown in FIGS. 12a to 12b.

Please refer to FIG. 11a to FIG. 12b again; in one embodiment, while the first gate material layer 26 is formed on the peripheral region PR, a first gate material layer 26 is also formed on the oxide layer 24 of the storage region SR. Gate material layer 26, as shown in FIGS. 11a to 11b; before removing the oxide layer 24 on the storage region SR, remove the first gate material layer 26 on the storage region SR , as shown in Figure 12a to Figure 12b.

Continuing to refer to FIG. 11 a to FIG. 11 b , in one embodiment, before forming the first gate material layer 26 on the peripheral region PR, it further includes forming a second gate dielectric material layer 25 on the peripheral region PR. The material of the second gate dielectric material layer 25 includes oxide, such as silicon oxide.

The material of the first gate material layer 26 includes but not limited to polysilicon. In a specific embodiment, after forming the first gate material layer 26 on the peripheral region PR, it further includes doping the first gate material layer 26 on the peripheral region PR to improve the The electrical conductivity of the first gate material layer 26 is described above.

Finally, step 105 is performed, as shown in FIG. 14a to FIG. 14b , part of the bit line plug material layer 23a and part of the bit line contact portion 202 are removed to form a bit line plug 23b and a bit line contact region 202a.

In one embodiment, before removing part of the bit line plug material layer 23a and part of the bit line contact portion 202, the method further includes: forming a bit line material layer 27 on the substrate 20, The bit line material layer 27 is in contact with the bit line plug material layer 23a, and a second dielectric layer 28 is formed on the bit line material layer 27, as shown in FIGS. 13a to 13b; The second dielectric layer 28 is used to form a bit line capping layer 28a; the bit line material layer 27 is etched to form a bit line layer 27a, as shown in FIGS. 14a to 14b. In some embodiments, the bit line material layer 27 and the second dielectric layer 28 are also formed on the peripheral region PR, as shown in FIG. A gate capping layer 28b is formed, and a second gate layer 27b is etched while forming the bit line layer 27a, as shown in FIG. 14b.

Continuing to refer to FIG. 14a to FIG. 14b , removing part of the bit line plug material layer 23a and part of the bit line contact portion 202 includes: using the bit line capping layer 28a and the bit line layer 27a as a mask , performing a self-aligned etching process to remove the bit line plug material layer 23a and the bit line contact portion 202 not covered by the bit line layer 27a to form a bit line plug 23b and a bit line contact region 202a. In some embodiments, while etching to form the bit line plug 23b and the bit line contact region 202a, the first gate material layer 26 and the second gate dielectric material layer 25 are etched to form the first gate. electrode layer 26a and the second gate dielectric layer 25a. But not limited thereto, the first gate layer 26 a and the second gate dielectric layer 25 a may not be formed simultaneously with the bit line plug 23 b and the bit line contact region 202 a.

In an actual process, the second dielectric layer 28 and the bit line material layer 27 may be etched from top to bottom along a direction perpendicular to the substrate 20 in the same process to form the bit line capping layer 28a , the bit line layer 27a, and then continue to etch the bit line plug material layer 23a and the bit line contact portion 202 using the bit line capping layer 28a and the bit line layer 27a as a mask to form the bit line The bit line plug 23b and the bit line contact region 202a.

In one embodiment, the bit line material layer 27 includes a first sub-layer 271 and a second sub-layer 272 disposed on the first sub-layer 271 . The etching the bit line material layer 27 to form the bit line layer 27a includes: etching the second sub-layer 272 to form a second conductive layer 272a; etching the first sub-layer 271 to form a first conductive layer 271a. The etching and forming the second gate layer 27b while etching the bit line layer 27a includes: etching the second sublayer 272 to form a second gate conductive layer 272b; etching the first sublayer 271 to form a first gate conductive layer 271b. In a specific embodiment, the material of the first sub-layer 271 includes but not limited to titanium nitride, and the material of the second sub-layer 272 includes but not limited to tungsten. The material of the second dielectric layer 28 includes but not limited to nitride, such as silicon nitride.

As shown in FIG. 14b, there are gaps on both sides of the bit line plug 23b and the bit line contact region 202a, and the gap is to remove part of the bit line plug material layer 23a and part of the bit line contact portion 202; in some embodiments, forming the gap further includes removing a portion of the isolation structure 201 located under the bit line plug material layer 23a; as shown in FIG. 15a to FIG. 15b, in a In an embodiment, the manufacturing method further includes: forming a third dielectric layer 29 on the substrate 20, the third dielectric layer 29 fills the gap and covers the side surface of the bit line layer 27a and the The upper and side surfaces of the bit line capping layer 28a form a protection structure. It can be understood that the third dielectric layer 29 also covers the gate capping layer 28b, the second gate layer 27b, the first gate layer 26a, the second gate dielectric layer 25a located on the peripheral region PR. formed gate stack. The formation method of the third dielectric layer 29 includes but not limited to atomic layer deposition (ALD). The material of the third dielectric layer 29 includes but not limited to nitride, such as silicon nitride.

In an actual process, a storage node contact plug will be formed above the storage node contact portion 203, and filling the gap with the third dielectric layer 29 can reduce the size of the bit line contact region 202a, the The parasitic capacitance between the bit line plug 23b and the storage node contact portion 203 and part of the storage node contact plug.

It can be seen that, in the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, in the process of forming the bit line plug material layer 23a, the bit line contact portion 202 and surrounding areas of the bit line contact portion 202 are not etched downward. The isolation structure 201 and the insulating structure 205 make the finally formed bit line plug 23b located on the top surface of the bit line contact region 202a, so that the bit line plug 23b has a relatively thin thickness, which can Reduce parasitic capacitance within semiconductor structures.

It should be noted that those skilled in the art can make possible changes between the sequence of the above steps without departing from the protection scope of the present disclosure.

An embodiment of the present disclosure also provides a semiconductor structure, as shown in FIG. 2 and FIG. 15a to FIG. The source area AA includes a bit line contact area 202a, the bit line contact area 202a has a top surface flush with the surface of the substrate 20; the first dielectric layer 21 is located on the surface of the substrate 20 , the first dielectric layer 21 covers at least part of the isolation structure 201; the bit line plug 23b is located in the first dielectric layer 21, and the bit line plug 23b is connected to the bit line contact region 202a. contact with the top surface, and the upper surface of the bit line plug 23 b is flush with the upper surface of the first dielectric layer 21 .

In one embodiment, the first dielectric layer 21 is located on the storage region SR. The material of the first dielectric layer 21 includes at least one of silicon oxide and silicon nitride. The first dielectric layer 21 may have a multilayer structure. In a specific embodiment, the first dielectric layer 21 includes a silicon oxide sublayer and a silicon nitride sublayer, and the silicon nitride sublayer is formed on the silicon oxide sublayer. layer above.

In one embodiment, the substrate 20 is further provided with word lines WL, the number of the word lines WL is multiple, and the multiple word lines WL extend in the storage region SR along the same direction, so The bit line contact region 202a is located between two adjacent word lines WL. The material of the word line WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination.

In one embodiment, the active area AA located in the storage area SR further includes storage node contact portions 203 located at both ends of the active area AA, and the storage node contact portion 203 is connected to the bit line contact area 202a separated by the word line WL and the insulating structure 205 .

Here, the storage node contact portion 203 and the bit line contact region 202a may be formed on the top of the active region AA by ion implantation. In a specific embodiment, the conductivity type of the storage node contact portion 203 and the bit line contact region 202a is the same, such as n-type. It can be understood that when the storage node contact portion 203 and the bit line contact region 202a are n-type doped, the substrate 20 below the storage node contact portion 203 and the bit line contact region 202a has p type doping.

In one embodiment, the material of the bit line plug 23b includes titanium nitride, which has better electrical conductivity than polysilicon mentioned in the related art, and can effectively reduce the contact between the bit line plug 23b and The contact resistance between the bit line contact regions 202a. But not limited thereto, the bit line plug 23b can also be made of other materials with good electrical conductivity, for example, tungsten, tungsten nitride, titanium, and the like.

In one embodiment, the semiconductor structure further includes: a bit line layer 27a and a bit line capping layer 28a disposed on the bit line layer 27a, the bit line layer 27a is in contact with the bit line plug 23b . In a specific embodiment, the bit line layer 27a includes a first conductive layer 271a and a second conductive layer 272a disposed on the first conductive layer 271a. In a more specific embodiment, the first conductive layer 271a includes a titanium nitride layer, and the second conductive layer 272a includes a tungsten layer. The material of the bit line capping layer 28a includes silicon nitride.

In one embodiment, a third dielectric layer 29 is disposed between the isolation structure 201 and the bit line contact region 202a, and between the first dielectric layer 21 and the bit line plug 23b. In an actual process, a storage node contact plug will be formed on the storage node contact portion 203 later, and the third dielectric layer 29 can reduce the size of the bit line contact region 202a, the bit line plug 23b and The parasitic capacitance between the storage node contact portion 203 and part of the storage node contact plug. In some embodiments, the third dielectric layer 29 also covers the side surfaces of the bit line layer 27 a and the upper surface and side surfaces of the bit line capping layer 28 a to form a protection structure. The material of the third dielectric layer 29 includes but not limited to nitride, such as silicon nitride.

In one embodiment, the semiconductor structure further includes a second gate dielectric layer 25a, a first gate layer, and a second gate dielectric layer 25a stacked in the peripheral region PR from bottom to top in a direction perpendicular to the substrate 20. 26a, a second gate layer 27b and a gate capping layer 28b, the second gate dielectric layer 25a is in contact with the active region AA. In some embodiments, the second gate layer 27b includes a first gate conductive layer 271b and a second gate conductive layer 272b, and the first gate conductive layer 271b is inscribed with the first gate conductive layer 271a. The second gate conductive layer 272b and the second conductive layer 272a are formed by etching the same material layer; the gate capping layer 28b and the bit line capping layer 28a are etched the same Layers of material are formed.

In one embodiment, the third dielectric layer 29 also covers the second gate dielectric layer 25a, the first gate layer 26a, the side surfaces of the second gate layer 27b and the gate The upper surface and side surfaces of the cover layer 28b. The material of the first gate layer 26 a includes doped or undoped polysilicon. The material of the second gate dielectric layer 25a includes oxide, such as silicon oxide.

In summary, the bit line plug is located in the first dielectric layer, and the upper surface of the bit line plug is flush with the upper surface of the first dielectric layer, that is, the bit line The plug is located on the top surface of the bit line contact region, and the bit line plug has a relatively thin thickness, which can reduce parasitic capacitance in the semiconductor structure.

It should be noted that the above descriptions are only optional embodiments of the present disclosure, and are not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure, etc. , should be included within the protection scope of the present disclosure.

Claims

A method of fabricating a semiconductor structure, comprising:

A substrate is provided, the substrate includes an active region defined by an isolation structure, the active region includes a bit line contact therein, the bit line contact and the isolation structure have a surface flush with the surface of the substrate flat top surface;

forming a first dielectric layer on the substrate, the first dielectric layer covering at least the bit line contact portion and the isolation structure;

performing an etching process on the first dielectric layer to expose the top surface of the bit line contact portion and part of the top surface of the isolation structure;

A bit line plug material layer is formed on the top surface of the bit line contact part and the part of the top surface of the isolation structure, and the upper surface of the bit line plug material layer is in contact with the first dielectric layer. flush with the upper surface;

A part of the bit line plug material layer and a part of the bit line contact portion are removed to form a bit line plug and a bit line contact region.
The manufacturing method according to claim 1, wherein performing an etching process on the first dielectric layer comprises:

A patterned mask layer is formed on the first dielectric layer; using the patterned mask layer as a mask, an etching process is performed on the first dielectric layer to form an opening, and the opening exposes the The top surface of the bit line contact and the portion of the top surface of the isolation structure.
The manufacturing method according to claim 2, wherein forming a bit line plug material layer on the top surface of the bit line contact portion comprises:

forming a conductive material on the substrate, the conductive material filling the opening and covering the first dielectric layer;

removing the first dielectric layer and the conductive material above the opening to obtain the bit line plug material layer, the upper surface of the bit line plug material layer and the upper surface of the first dielectric layer flush.
The manufacturing method according to claim 1, wherein the substrate includes a storage area and a peripheral area; forming a first dielectric layer on the substrate comprises:

The first dielectric layer is simultaneously formed on the storage area and the peripheral area.
The manufacturing method according to claim 4, wherein, after forming a bit line plug material layer on the top surface of the bit line contact portion, further comprising: forming a first gate material layer on the peripheral region .
The manufacturing method according to claim 5, wherein forming the first gate material layer on the peripheral region comprises:

forming an oxide layer on the substrate, the oxide layer covering the first dielectric layer;

removing the first dielectric layer and the oxide layer on the peripheral region;

forming a first gate material layer on the peripheral region;

The oxide layer on the storage area is removed.
The manufacturing method according to claim 4, wherein, before removing part of the bit line plug material layer and part of the bit line contact part, the method further comprises:

forming a bit line material layer on the substrate, the bit line material layer is in contact with the bit line plug material layer;

forming a second dielectric layer on the bit line material layer;

Etching the second dielectric layer to form a bit line capping layer; etching the bit line material layer to form a bit line layer.
The manufacturing method according to claim 7, wherein removing part of the bit line plug material layer and part of the bit line contact part comprises:

Using the bit line capping layer and the bit line layer as a mask, perform a self-aligned etching process to remove the bit line plug material layer and the bit line contact portion not covered by the bit line layer to form bit line plugs and bit line contact areas.
The manufacturing method according to claim 8, wherein there are gaps on both sides of the bit line plug and the bit line contact region, and the gap is to remove part of the bit line plug material layer and part of the bit line plug material layer. The bit line contact part is formed;

The manufacturing method further includes: forming a third dielectric layer on the substrate, the third dielectric layer fills the gap and covers the side surface of the bit line layer and the upper surface and the upper surface of the bit line capping layer. side surface.
The manufacturing method according to claim 9, wherein the material of the first dielectric layer comprises at least one of silicon oxide and silicon nitride; the material of the second dielectric layer comprises silicon nitride; the third The material of the dielectric layer includes silicon nitride.
A semiconductor structure comprising:

a substrate comprising an active region defined by isolation structures, the active region comprising a bitline contact region therein, the bitline contact region having a top surface flush with a surface of the substrate;

a first dielectric layer located on the surface of the substrate, the first dielectric layer covers at least part of the isolation structure;

a bit line plug located in the first dielectric layer, the bit line plug is in contact with the top surface of the bit line contact region, and the upper surface of the bit line plug is in contact with the first dielectric layer The upper surface of the layer is flush.
The semiconductor structure of claim 11, wherein the material of the bit line plug comprises titanium nitride.
The semiconductor structure according to claim 11, wherein the semiconductor structure further comprises: a bit line layer and a bit line capping layer disposed on the bit line layer, the bit line layer is in contact with the bit line plug connect.
The semiconductor structure of claim 13, wherein the bit line layer comprises a first conductive layer and a second conductive layer disposed on the first conductive layer.
The semiconductor structure of claim 14, wherein the first conductive layer comprises a titanium nitride layer and the second conductive layer comprises a tungsten layer.
The semiconductor structure according to claim 13, wherein a third dielectric layer is disposed between the isolation structure and the bit line contact region, and between the first dielectric layer and the bit line plug.
The semiconductor structure according to claim 16, wherein the third dielectric layer also covers the side surfaces of the bit line layer and the upper surface and side surfaces of the bit line capping layer.
The semiconductor structure according to claim 17, wherein the material of the first dielectric layer comprises at least one of silicon oxide and silicon nitride; the material of the bit line capping layer comprises silicon nitride; the third The material of the dielectric layer includes silicon nitride.