WO2023132232A1 - 固体撮像素子、及び電子機器 - Google Patents

固体撮像素子、及び電子機器 Download PDF

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Publication number
WO2023132232A1
WO2023132232A1 PCT/JP2022/046904 JP2022046904W WO2023132232A1 WO 2023132232 A1 WO2023132232 A1 WO 2023132232A1 JP 2022046904 W JP2022046904 W JP 2022046904W WO 2023132232 A1 WO2023132232 A1 WO 2023132232A1
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WIPO (PCT)
Prior art keywords
vertical signal
signal line
row
pixels
selection
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Ceased
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PCT/JP2022/046904
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English (en)
French (fr)
Japanese (ja)
Inventor
和彦 村岡
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to DE112022006310.6T priority Critical patent/DE112022006310T5/de
Priority to JP2023572411A priority patent/JPWO2023132232A1/ja
Priority to CN202280087024.8A priority patent/CN118476239A/zh
Priority to US18/724,337 priority patent/US12483811B2/en
Publication of WO2023132232A1 publication Critical patent/WO2023132232A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction

Definitions

  • the present disclosure relates to a solid-state imaging device that captures an image of a subject, and an electronic device.
  • object contour information can be calculated as difference information between pixels.
  • This contour information is important information in object shape recognition and the like.
  • this contour information is generally generated by arithmetic operations by digital circuits or software.
  • digital circuits or software since the amount of data of an image is large, the amount of circuits in a digital circuit increases, resulting in an increase in the chip area of the solid-state imaging device and an increase in power consumption.
  • implementation by software causes a decrease in the frame rate due to delays in calculation, and requires a high-speed processor, leading to an increase in power consumption.
  • the present disclosure provides a solid-state imaging device and an electronic device capable of generating difference information between pixels at high speed while suppressing an increase in the amount of circuitry.
  • a first analog-digital converter having a first analog-digital converter circuit and a second analog-digital converter circuit and a second analog-digital converter having a third analog-digital converter circuit a conversion unit;
  • the first analog-to-digital conversion circuit is connected to a first vertical signal line and a second vertical signal line via a first switch circuit;
  • the second analog-to-digital conversion circuit is connected to a third vertical signal line and a fourth vertical signal line via a second switch circuit;
  • the third analog-to-digital conversion circuit is connected to the second vertical signal line and a signal line different from the first vertical signal line, the second vertical signal line, and the fourth vertical signal line via a third switch circuit.
  • a solid-state imaging device is provided in which the first analog-to-digital converter and the second analog-to-digital converter are arranged on the same end side of the pixel array section.
  • the different signal line may be the third vertical signal line.
  • the different signal lines may be signal lines that supply predetermined signal values.
  • the first selection unit has a plurality of switch circuits including the first switch circuit and a second switch circuit
  • the second selection unit has a plurality of switch circuits including the third switch circuit
  • the first analog-to-digital conversion unit includes a plurality of analog-to-digital conversion circuits corresponding to the plurality of switch circuits included in the first selection circuit, including the first analog-to-digital conversion circuit and the second analog-to-digital conversion circuit
  • the second analog-to-digital conversion section may have a plurality of analog-to-digital conversion circuits corresponding to a plurality of switch circuits included in the second selection circuit, including the third analog-to-digital conversion circuit.
  • each of the plurality of switch circuits included in the first selection unit is connected to two of the plurality of vertical signal lines in a predetermined order according to the arrangement order; each of the plurality of switch circuits included in the second selection unit is connected to two of the plurality of vertical signal lines in a predetermined order according to the arrangement order;
  • the left one of the two vertical signal lines is the right vertical signal line of the two vertical signal lines in any one of the plurality of switch circuits included in the first selection circuit.
  • the right one of the two vertical signal lines is the left vertical signal line of the two vertical signal lines in any one of the plurality of switch circuits included in the first selection circuit.
  • Each of the plurality of switch circuits included in the first selection unit has (2n ⁇ 1) ((n is 1 to M/2, M is an even number) vertical signal line from the left, and (2n) connected to two vertical signal lines and
  • Each of the plurality of switch circuits included in the second selection section may be connected to two lines, the (2n)th vertical signal line from the left and the (2n+1)th vertical signal line, depending on the arrangement order.
  • Each of the plurality of switch circuits included in the second selection section has two switches, the ((n ⁇ 1) ⁇ 8+m+4)-th vertical signal line from the left and the (n ⁇ 8+m)-th vertical signal line, according to the arrangement order. It may be connected to a book.
  • Each of the plurality of switch circuits of the first selection unit is ((n ⁇ 1) ⁇ 4+m) (n is 1 to M/4, M is a multiple of 4, m is 1 to 2) connected to two of the th vertical signal line and the ((n ⁇ 1) ⁇ 4+m+2) th vertical signal line,
  • Each of the plurality of switch circuits included in the second selection section has two switches, the ((n ⁇ 1) ⁇ 4+m+2)-th vertical signal line from the left and the (n ⁇ 4+m)-th vertical signal line, according to the arrangement order. It may be connected to a book.
  • each of the switch circuits included in the first selection unit alternately selects the left vertical signal line and the right vertical signal line of the two vertical signal lines
  • Each of the switch circuits included in the second selection section may alternately select the right vertical signal line and the left vertical signal line of the two vertical signal lines.
  • each of the switch circuits included in the first selection unit selects one of the left vertical signal line and the right vertical signal line of the two vertical signal lines
  • Each of the switch circuits included in the second selection section may select a vertical signal line on the same side of the two vertical signal lines as the switch circuit included in the first selection circuit.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels in the first row when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit; When selecting the right vertical signal line of the two signal lines, the pixels in the second row different from the first row may be electrically connected.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, When the left vertical signal line of the two signal lines of the switch circuit of the first selection unit is selected, the pixels of the first row and the second row different from the first row are electrically connected. death, When the right vertical signal line of the two signal lines is selected, a third row different from the first row and the second row, and a third row different from the first row, the second row, and the third row The fourth row of pixels may be electrically connected.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels in the first row when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit; electrically connecting the pixels of the first row and the third row separated by one row when the right vertical signal line of the two signal lines is selected; next, electrically connecting the pixels in the second row adjacent to the first row when selecting the left vertical signal line of the two signal lines; Next, when selecting the right vertical signal line of the two signal lines, the pixels in the fourth row separated by one row from the second row may be electrically connected.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels of the first to fourth rows when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit; When selecting the right vertical signal line of the two signal lines, the pixels in the fifth to eighth rows, which are different from the first to fourth rows, may be electrically connected.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, When the left vertical signal line of the two signal lines of the switch circuit of the first selection unit is selected, the pixels of a predetermined one row among the first to fourth rows are electrically connected. , When the vertical signal line on the right side of the two signal lines is selected, it is possible to electrically connect the pixels in a predetermined row out of the fifth to eighth rows different from the first to fourth rows. good.
  • the pixel array section may have pixels in a Bayer array.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix,
  • the pixels are a photoelectric conversion element unit that generates a current corresponding to the amount of received light by photoelectric conversion; a transfer transistor having a drain connected to the cathode of the photoelectric conversion element; a reset transistor having a source connected to the source of the transfer transistor; an amplification transistor having a gate connected to the source of the transfer transistor; a floating diffusion connected to the gate of the amplification transistor; a selection transistor having a drain connected to the amplification transistor source and a source connected to any one of the first to fourth vertical signal lines.
  • the pixel array section has pixels in a Bayer array,
  • the vertical signal line may be electrically connected to a floating diffusion connected to four pixels forming the Bayer array.
  • a solid-state imaging device according to claim 1; and an optical system for causing light to enter the pixel array section.
  • FIG. 1 is a block diagram showing a configuration example of an embodiment of a digital camera to which the present technology is applied;
  • FIG. FIG. 4 is a diagram showing an example of an image captured by a digital camera;
  • FIG. 2 is a block diagram showing a configuration example of the image sensor in FIG. 1;
  • FIG. 4 is a diagram showing a configuration example of a pixel array section;
  • FIG. 4 is a diagram showing an example of a circuit in a pixel array section;
  • FIG. 4 is a diagram showing a state in which signals of green pixels in the first row are acquired;
  • FIG. 10 is a diagram showing a state in which signals of green pixels on the second row are acquired;
  • FIG. 10 is a diagram showing a state in which signals of green pixels on the third row are acquired;
  • FIG. 4 is a diagram showing a circuit configuration example of a basic unit of a pixel;
  • FIG. 4 is a diagram showing a circuit configuration example of an AD converter;
  • FIG. 4 is a diagram specifically showing an example of difference processing;
  • FIG. 8 is a diagram showing an example of difference processing in an AD converter of pixel values of green pixels in the first row and green pixels in the second row;
  • 4 is a time chart showing an example of differential processing from time t10 to t21;
  • FIG. 10 is a diagram showing an example of difference processing in a pixel array unit according to the second embodiment;
  • FIG. 10 is a diagram showing an example of difference processing in a pixel array unit according to the second embodiment;
  • FIG. 10 is a diagram showing an example of difference processing in a pixel array unit according to the second embodiment;
  • FIG. 10 is a diagram showing an example
  • FIG. 5 is a diagram showing an example of a circuit of a pixel array section according to the second embodiment
  • FIG. 10 is a diagram showing a circuit configuration example of a basic unit of a pixel according to the second embodiment
  • 4 is a time chart showing an example of difference processing from time t40 to time t51
  • FIG. 11 is a diagram showing an example of odd-numbered row difference processing in a pixel array unit according to the third embodiment
  • FIG. 7 is a diagram showing an example of differential processing for even rows in the pixel array unit
  • FIG. 11 is a diagram showing an example of a circuit of a pixel array section according to the third embodiment;
  • FIG. 11 is a time chart showing an example of differential processing from time t10 to t21 according to the third embodiment;
  • FIG. 11 is a time chart including an example of differential processing from time t21 to t24 according to the third embodiment;
  • 4 is a time chart showing an example of difference processing from time t10 to t21 for even rows;
  • FIG. 9 is a time chart showing an example of differential processing from time t10 to t21 according to the second control method; A time chart including an example of difference processing from time t21 to t24 according to the second control method.
  • FIG. 11 is a time chart including an example of difference processing for odd-numbered last lines according to the second control method;
  • FIG. 11 is a time chart showing an example of difference processing from time t30 to time t41 according to the second control method;
  • FIG. 11 is a time chart including an example of differential processing from time t36 to time t44 according to the second control method;
  • FIG. 11 is a time chart including an example of difference processing for even-numbered last lines according to the second control method;
  • FIG. 11 is a diagram showing an example of difference processing by the first control method in the pixel array section according to the fourth embodiment;
  • FIG. 11 is a diagram showing an example of differential processing by a second control method in a pixel array section according to the fourth embodiment;
  • FIG. 11 is a diagram showing a circuit configuration example of a basic pixel group in a Bayer array according to the fourth embodiment;
  • FIG. 11 is a time chart showing an example of differential processing from time t10 to t21 according to the fourth embodiment;
  • FIG. FIG. 11 is a time chart including an example of differential processing from time t22 to time t24 according to the fourth embodiment;
  • FIG. 11 is a time chart including an example of differential processing of the last line according to the fourth embodiment
  • FIG. 9 is a time chart showing an example of difference processing from time t10 to time t21 according to the second control;
  • 9 is a time chart including an example of difference processing of the last line according to the second control;
  • solid-state imaging device and an electronic device will be described with reference to the drawings.
  • the solid-state imaging device and the main components of the electronic device will be mainly described below, the solid-state imaging device and the electronic device may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.
  • FIG. 1 is a block diagram showing a configuration example of an embodiment of a digital camera to which the present technology is applied. Note that the digital camera 100 can capture both still images and moving images.
  • the digital camera 100 has an optical system 1, an image sensor 2, a memory 3, a signal processing section 4, an output section 5, and a control section 6.
  • a digital camera according to this embodiment corresponds to an electronic device.
  • the optical system 1 has, for example, a zoom lens (not shown), a focus lens, an aperture, and the like, and allows external light to enter the image sensor 2 .
  • the image sensor 2 is, for example, a solid-state imaging device such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. to output
  • the memory 3 temporarily stores image data output by the image sensor 2 .
  • FIG. 2 is a diagram showing an example of an image captured by the digital camera 100.
  • FIG. FIG. 2A is a general captured image, which can be captured as a color image or a monochrome image.
  • FIG. 2B is a difference image generated by using the difference information between pixels in FIG. 2A as contour information.
  • FIG. 2C is a binary image obtained by subjecting the pixel values in FIG. 2B to threshold processing and binarizing them.
  • a difference image may be called a contour image.
  • the difference image in FIG. 2B expresses the amount of difference in multiple values. Therefore, the image gives a thin impression.
  • the binary image shown in FIG. 2C is generated. This gives a more visually emphasized impression.
  • an object recognition algorithm it is common to extract only the contours that are important for recognition by inserting edge extraction processing in the preceding stage. Therefore, in the object recognition algorithm, for example, by using the binary image of FIG. 2C, the processing of unimportant information is reduced, and the computational burden of recognition is reduced. This is the same when using AI or the like, and it is possible to perform recognition with less computational resources.
  • the signal processing unit 4 performs processing such as noise removal and white balance adjustment as signal processing using the image data stored in the memory 3, and supplies it to the output unit 5.
  • the output unit 5 outputs image data from the signal processing unit 4 .
  • the signal processing unit 4 can also perform object recognition using an object recognition algorithm. This object recognition algorithm can use a binary image that outlines the object. In this case, since the binary image is converted into a smaller amount of data by converting it into a binary image, it is possible to reduce the processing weight of the object recognition algorithm of the signal processing unit 4 .
  • the output unit 5 outputs the recognition result of the signal processing unit 4.
  • the output unit 5 also has a display (not shown) made up of, for example, a liquid crystal or the like, and displays an image corresponding to the image data from the signal processing unit 4 as a so-called through image.
  • the output unit 5 has a driver (not shown) for driving a recording medium such as a semiconductor memory, a magnetic disk, an optical disk, etc., and records the image data from the signal processing unit 4 on the recording medium.
  • the control unit 6 can control the digital camera 100 to capture a general captured image or to capture a difference image.
  • This control section 6 controls each block constituting the digital camera in accordance with the user's operation or the like.
  • the image sensor 2 receives incident light from the optical system 1, and depending on the incident light, image data of general imaging (see FIG. 2A) or difference image data (see FIG. 2A). 2B) is output.
  • the image sensor 2 can also output a binary image (see FIG. 2C).
  • the image data, difference image data, and binary image data output by the image sensor 2 are supplied to the memory 3 and stored. At least one of the image data, difference image data, and binary image data stored in the memory 3 is subjected to signal processing by the signal processing unit 4, and the resulting image data is supplied to the output unit 5. output as
  • FIG. 3 is a block diagram showing a configuration example of the image sensor 2 in FIG. 3, the image sensor 2 includes a pixel control section 8, a pixel array section 10, a first selection section 12, a first AD conversion section 14, a second selection section 16, a second AD conversion section 18, and an image processing section. It comprises a unit 20 and an output interface 22 .
  • the pixel control unit 8 controls the image sensor 2 under the control of the control unit 6 (see FIG. 1).
  • the pixel control unit 8 sequentially scans the pixel array unit 10 in the row direction and controls imaging. It also controls the first selection unit 12, the first AD conversion unit 14, the second selection unit 16, and the second AD conversion unit 18 to generate image data of general imaging or differential image data.
  • a first selection drive line Sel_L (see FIG. 5, which will be described later) is connected between the first selection section 12 and the pixel control section 8, and a , and the second selection drive line Sel_R (see FIG. 5, which will be described later).
  • the pixel control section 8 outputs a selector control signal (left) (SEL_L) through a first selection drive line Sel_L and a selector control signal (right) (SEL_R) through a second selection drive line Sel_R. Note that in this embodiment, the selector control signal (left) and the selector control signal (right) may be referred to as selection control signals.
  • SEL_L when SEL_L is "0", it means a signal for selecting the left vertical signal line, and when SEL_L is "1", it means a signal for selecting the right vertical signal line.
  • SEL_R when SEL_R is '0', it means a signal for selecting the left vertical signal line, and when SEL_L is '1', it means a signal for selecting the right vertical signal line.
  • SEL_L and SEL_R are controlled to have different values.
  • SEL_L and SEL_R are controlled to have the same value. Note that SEL_L and SEL_R mean selection of the left or right vertical signal line depending on their values, and thus have left-right directionality, for example.
  • FIG. 4 is a diagram showing a configuration example of the pixel array section 10.
  • the basic pixel unit G10 is a Bayer array and is composed of a pixel with a red filter (R), a pixel with two green filters (G), and each pixel with a blue filter (B).
  • the pixel array section 10 has N ⁇ M photoelectric conversion elements (N and M are integers equal to or greater than 1) that perform photoelectric conversion, and functions as a solid-state imaging element that captures an image.
  • a pixel with a red filter is simply called a red pixel
  • a pixel with a green filter is simply called a green pixel
  • a pixel with a blue filter is simply called a blue pixel.
  • the image sensor 2 according to the present embodiment in addition to normal color photography, detects the pixel value difference between obliquely adjacent green pixels as indicated by a double-headed arrow D10. It is possible to calculate A detailed configuration example of the pixel array unit 10 will be described later. Also, the image sensor 2 according to the present embodiment will be described using red, green, and blue pixels as an example, but the present invention is not limited to this. For example, differences can be similarly extracted from monochrome pixels and red, green, blue, and white pixels (RGB-White pixels).
  • the Bayer array which is the color filter array of a general image sensor
  • green is emphasized and the number of red and blue pixels is less than the number of green pixels. This is due to allocating many green pixels since human vision is sensitive to green.
  • the image sensor 2 uses obliquely adjacent green pixels in order to extract the contour of an object.
  • this difference value is called contour information. That is, in the present embodiment, the diagonal direction of the green pixel, the difference from the upper left, and the difference value from the upper right are obtained and used as the difference image.
  • the first selection unit 12 selects ((2n ⁇ 1), (2n)) (n is 1 to M/2) adjacent vertical signals of the plurality of vertical signals of the pixel array unit 10 .
  • One of a combination of two signal lines is selected, and the signal of the selected signal line is output to the first AD converter 14 .
  • the number of vertical signals in the pixel array section 10 is, for example, 1 to M (for example, M is an even number).
  • the first selection unit 12 selects even-numbered vertical signals when the selector control signal (left) (SEL_L) is “1", that is, at high level. Also, odd-numbered vertical signals are selected when the selector control signal (left) (SEL_L) is "0", that is, at low level.
  • the first selection section 12 alternately selects adjacent vertical signals.
  • the first selection unit 12 selects a combination of two adjacent signal lines such as ((2n ⁇ 1), (2n)) (n is 1 to M/2). always selects the (2n-1) (n is 1 to M/2)th signal line.
  • the selector control signal (left) (SEL_L) is always "0", that is, at low level.
  • the first AD converter 14 performs differential processing using the two image signals supplied in time series from the first selector 12, and converts them into digital image data. That is, when generating a difference image, the first AD conversion unit 14 uses the signals of (2n ⁇ 1) (n is 1 to M/2) and the signals of (2n) (n is 1 to M/2). ) is converted into a digital signal.
  • the first AD converter 14 when generating a normal image, the first AD converter 14 generates the difference between the (2n-1)th signal lines (n is 1 to M/2). That is, when generating a normal image, the first AD converter 14 converts the difference value between the offset component signal transmitted in time series and the pixel signal into a digital signal. A detailed configuration example of the first AD converter 14 will also be described later.
  • a second selection unit 16 selects a combination of two adjacent signal lines ((2n), (2n+1)) (n is 1 to (M/2)) among a plurality of vertical signals of the pixel array unit 10. One of them is selected, and the signal of the selected signal line is output to the second AD converter 18 .
  • the second selection unit 16 selects the odd-numbered vertical signal when the selector control signal (right) (SEL_R) is "0", that is, at a low level, and selects the odd-numbered vertical signal (VSL) as the selector control signal. (Right) Select when (SEL_R) is "1", ie high level.
  • the second selection unit 16 when the second selection unit 16 generates a normal image, for example, ((2n), (2n+1)) (n is 1 to M/2) among combinations of two adjacent signal lines (2n) Always select the (n is 1 to M/2)th signal line.
  • a normal image for example, ((2n), (2n+1)) (n is 1 to M/2) among combinations of two adjacent signal lines (2n) Always select the (n is 1 to M/2)th signal line.
  • the rector control (left) (SEL_R) when generating a normal image, the rector control (left) (SEL_R) is always a "0" selection signal.
  • the second AD converter 18 performs differential processing using the two image signals supplied in time series from the second selector 16, and converts them into digital image data. That is, when generating a differential image, the second AD conversion unit 18 uses (2n) (n is 1 to M/2) signal line signals and (2n+1) (n is 1 to M/2) signal line signals. The difference value between the signal on the signal line and the signal line is converted into a digital signal.
  • the second AD converter 18 when generating a normal image, the second AD converter 18 generates the difference between the (2n)th (n is 1 to M/2) signal lines. That is, when generating a normal image, the second AD converter 18 converts the difference value between the offset component signal transmitted in time series and the pixel signal into a digital signal. A detailed configuration example of the second AD converter 18 will also be described later.
  • the AD conversion section is divided into two, the first AD conversion section 14 and the second AD conversion section 18 .
  • the total number of AD converters corresponds to the number of vertical signal lines VSL.
  • the configuration of a general sensor and the number of AD converters are configured to be the same. It is possible to calculate the difference of the pixel values between. In particular, in this embodiment, the pixel value difference between obliquely adjacent green pixels is calculated.
  • the image processing unit 20 can perform general image processing such as noise reduction processing on the image data after AD conversion by the first AD conversion unit 14 and the second AD conversion unit 18 .
  • general image processing such as noise reduction processing on the image data after AD conversion by the first AD conversion unit 14 and the second AD conversion unit 18 .
  • the image processing unit 20 performs difference processing, since the AD conversion unit is divided into the first AD conversion unit 14 and the second AD conversion unit 18, it is necessary to match the conventional image output and format. , the data column (left) and the data column (right) can be alternately rearranged.
  • the image processing unit 20 also performs threshold processing on the difference image to generate a binary image. This threshold value may be set in advance or may be set according to a user's operation or the like.
  • the output interface 22 supplies the image data supplied from the image processing section 20 to, for example, the memory 3 (see FIG. 1).
  • FIG. 5 shows circuits of the pixel array section 10, the selector array (first selection section 12 and second selection section 16), and the AD conversion section (first AD conversion section 14 and second AD conversion section 18). It is a figure which shows an example. In addition, although the number of pixels is described as 8 ⁇ 8 for the sake of simplicity, the number is not limited to this.
  • Each pixel of the pixel array section 10 is exposed to light through each of the R/G/B color filters as described above.
  • the pixel control unit 8 controls pixel shutter/floating diffusion (FD) transfer/reading (reading) by means of control wires that are wired in the horizontal direction of the pixel array unit 10 . and other controls. Control lines for control are shared in the horizontal direction, and row addresses (vertical addresses) are assigned from bottom to top.
  • the vertical signal line VSL arranged in the vertical direction connects each pixel arranged in the column direction of the pixel array section 10, the first AD conversion section 14 and the second AD conversion section 18 to the first selection section 12, and through the second selection unit 16 .
  • first AD conversion section 14 or the second AD conversion section 18 is electrically connected to each of the vertical signal lines VSL via the first selection section 12 and the second selection section 16 .
  • being electrically connected means being in a state in which a signal can be transmitted.
  • the first selection section 12 and the second selection section 16 select one of the adjacent vertical signal lines VSL. That is, the first selection unit 12 is composed of a plurality of selectors SEL11-14. Two adjacent signal lines ((2n ⁇ 1), (2n)) (n is 1 to M/2) are connected in order to the selectors SEL11 to SEL14.
  • the second selection unit 16 is composed of a plurality of selectors SEL21-24. Two adjacent signal lines ((2n), (2n+1)) (n is 1 to M/2) are connected in order to the selectors SEL21 to SEL24.
  • the first AD converter 14 has a plurality of AD converters ADC11-14.
  • a plurality of AD converters ADC11-14 are connected to corresponding selectors SEL11-14.
  • the second AD converter 18 has a plurality of AD converters ADC21-24.
  • a plurality of AD converters ADC21-24 are connected to corresponding selectors SEL21-24.
  • the AD converter according to this embodiment corresponds to the analog-to-digital conversion circuit.
  • the first AD converter 14 corresponds to the first analog-to-digital converter
  • the second AD converter 18 corresponds to the second analog-to-digital converter.
  • the pixel control unit 8 maintains, for example, the selection control signals SEL_L and SEL_R at low level, that is, at a value of 0 in the case of normal shooting. Thereby, each of the first selection units 12 and the second selection unit 16 selects the left vertical signal line VSL. More specifically, the signal on the vertical signal line VSL1 goes to ADC11, the signal on the vertical signal line VSL2 goes to ADC21, the signal on the vertical signal line VSL3 goes to ADC12, the signal on the vertical signal line VSL4 goes to ADC22, and the signal on the vertical signal line VSL5 goes to ADC22. A signal is input to ADC13, a signal on vertical signal line VSL6 is input to ADC23, a signal on vertical signal line VSL7 is input to ADC14, and a signal on vertical signal line VSL8 is input to ADC28.
  • one AD converter corresponds to one vertical signal line.
  • SEL_L and SEL_R are maintained at a low level, ie, a value of 0, the configuration is the same as that of a normal image sensor.
  • selectors SEL11-14 and selectors SEL21-24 select the vertical signal line in the same direction, that is, the left vertical signal line. .
  • selectors SEL11-14 and the selectors SEL21-24 correspond to switch circuits.
  • FIG. 6 is a diagram showing a state in which signals of green pixels on the first row are acquired.
  • FIG. 7 is a diagram showing a state in which signals of green pixels on the second row are acquired.
  • FIG. 8 is a diagram showing a state in which signals of green pixels on the third row are acquired.
  • the difference value of green pixels is used.
  • the image control unit 8 selects only the control wire 1 (control wires 1) and deselects the control wires 2 to 8 (control wires 2 to 8). As a result, only the pixels in the row of control line 1 are electrically connected to each vertical signal line VSL.
  • the data of the green pixel (the leftmost green pixel) connected to the signal line VSL2 of the control line 1 is input to the AD converter ADC11 and the AD converter ADC21.
  • Data of the green pixel (the second green pixel from the left) connected to the signal line VSL4 of the control line 1 is input to the AD converter ADC12 and the AD converter ADC22.
  • green pixel data connected to the signal line VSL6 is input to the AD converter ADC13 and the AD converter ADC23.
  • green pixel data connected to the signal line VSL8 is input to the AD converter ADC14 and the AD converter ADC24.
  • the AD converters ADC11-14 and ADC21-24 apply auto zero (details will be described later) to set the level of the signal value of the first input green pixel as the reference value of each ADC, that is, the value of 0.
  • the image control unit 8 next selects only the control line 2 and deselects the control lines 1, 3 to 8. Thereby, only the pixel data of the row of the control line 2 is electrically connected to each vertical signal line.
  • SEL_L is 0, all selectors SEL11-14 of the first selection unit 12 select the vertical signal line VSL indicated by 0 (left), and transfer the signal of the selected vertical signal line VSL to the first AD. Output to the conversion unit 14 .
  • SEL_R is 1, all the selectors SEL21 to 24 of the second selection unit 1 select the VSL line indicated by 1 (right), and convert the signal of the selected vertical signal line to the second AD conversion unit 18. output to
  • the data of the green pixel (the leftmost green pixel) connected to the signal line VSL1 of the control line 2 is input to the AD converter ADC11.
  • Data of the green pixel (the second green pixel from the left) connected to the signal line VSL3 of the control line 2 is input to the AD converter ADC12 and the AD converter ADC21.
  • green pixel data connected to the signal line VSL5 is input to the AD converter ADC13 and the AD converter ADC23.
  • green pixel data connected to the signal line VSL7 is input to the AD converter ADC14 and the AD converter ADC24.
  • AD converters ADC11-14 and AD converters ADC21-24 perform AD conversion.
  • the green image data of the first and second rows are read out.
  • the AD converters ADC11 to ADC14 convert the difference value between the green pixel on the first row and the upper left green pixel on the second row with respect to the green pixel on the first row into a digital signal.
  • the AD converters ADC21 to ADC24 convert the difference value between the green pixel on the first row and the upper right green pixel on the second row with respect to the green pixel on the first row into a digital signal.
  • the green pixel connected to the right end vertical signal line VSL8 can also be processed in the same manner.
  • the difference value with the upper left can be obtained from the AD converter ADC14, since there is no signal line VSL on the right, a dummy signal is sent to the image control unit 8 (see FIG. 3) via the dummy signal line.
  • a dummy signal is sent to the image control unit 8 (see FIG. 3) via the dummy signal line.
  • the AD converter ADC24 since the AD converter ADC24 becomes invalid data, it may be discarded.
  • the AD converter ADC24 at the time of differential processing may be connected to the ground (GND) or the like.
  • the dummy signal is, for example, a predetermined signal value, but is not limited to this.
  • the differential AD conversion of the green pixels in the second and third rows can be started in a state in which the differential AD conversion of the green pixels in the first and second rows has ended. That is, as shown in FIG. 7, the leftmost green pixel in the second row is input to ADC11, and the second green pixel is input to ADC12, ADC21, and so on. AZ (auto zero) is performed in this state, and the pixel value is stored in each ADC as a reference value.
  • the image control unit 8 selects only the control line 3 (vertical address 3) and deselects the control lines 1, 2, 4-8. As a result, only the pixel data of the row of the control line 3 is electrically connected to each vertical signal line.
  • the signal output from each pixel may be referred to as pixel data.
  • AD converters ADC11-14 and AD converters ADC21-24 perform AD conversion.
  • the green image data of the second and third rows are read out.
  • the AD converters ADC11 to ADC14 convert the difference value between the green pixel on the second row and the upper right green pixel on the third row to the green pixel on the second row into a digital signal.
  • the AD converters ADC21 to ADC24 convert the difference value between the green pixel on the second row and the upper left green pixel on the third row with respect to the green pixel on the second row into a digital signal.
  • FIG. 9 is a diagram showing a circuit configuration example of the pixel basic unit G10.
  • the pixel basic unit G10 has four pixels PX11, PX12, 21, and 22.
  • the pixel PX11 includes a photodiode PD, a transfer transistor SW1, a reset transistor SW2, an amplification transistor AMP, a selection transistor SW3, and a rotating diffusion FD.
  • the pixel PX11 is a red pixel
  • the pixels PX12 and PX21 are green pixels
  • the pixel PX22 is a blue pixel.
  • a photodiode (photoelectric conversion element) PD generates a current corresponding to the amount of light received by photoelectric conversion.
  • the photodiode PD has an anode connected to the ground (GND) and a cathode connected to the drain of the transfer transistor SW1.
  • Various control signals are input to the pixel PX11 from the image control unit 8 via the signal lines Trg1, Rst1, and Se1l. That is, the bundle of signal lines Trg1, Rst1, and Sel1 corresponds to the control wires 1 (see FIG. 5).
  • a signal line TRG1 for transmitting a transfer gate signal is connected to the gate of the transfer transistor SW1.
  • the source of the transfer transistor SW1 is connected to the connection point between the source of the reset transistor SW2 and the gate of the amplification transistor AMP.
  • This connection point constitutes a floating diffusion FD, which is a capacitor for accumulating signal charges.
  • the transfer transistor SW1 is turned on when a high-level transfer signal TRG1 is input to its gate through the signal line Trg1, and transfers signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiode PD to the floating diffusion FD. do.
  • signal charges here, photoelectrons
  • “on” may be referred to as the connected state
  • “off” may be referred to as the non-connected state.
  • a signal line Rst1 for transmitting a reset signal is connected to the gate of the reset transistor SW2, and a constant voltage source VSS is connected to the drain.
  • the reset transistor SW2 is turned on when a high-level reset signal RST1 is input to its gate through the signal line Rst1, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the reset transistor SW2 is turned off to form a predetermined potential barrier between the floating diffusion FD and the constant voltage source VSS.
  • the amplification transistor AMP has a gate connected to the floating diffusion FD, a drain connected to the constant voltage source VSS, and a source connected to the drain of the selection transistor SW3.
  • the selection transistor SW3 has a gate connected to the signal line Sel1 and a source connected to the vertical signal line VSL1.
  • the selection transistor SW3 is turned on when a high-level control signal SEL1 (an address signal (vertical address signal) or a select signal) is input to the gate through the signal line Sel1, and a low-level control signal SEL1 is input to the gate through the signal line Sel1. is turned off.
  • SEL1 an address signal (vertical address signal) or a select signal
  • the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL1.
  • a voltage output from each pixel through the vertical signal line VSL1 is output to the AD converter ADC11 or 21 (see FIG. 5).
  • Other pixels have the same configuration as the pixel PX11, and description thereof is omitted.
  • FIG. 10 is a diagram showing a circuit configuration example of the AD converter ADC11. As shown in FIG. 10, the AD converter ADC11 includes a plurality of AZ units 40 and 42, a comparator 44, and a counter .
  • the DAC section 30 is a DA converter and has a counter (not shown) inside.
  • the DAC unit 30 outputs a voltage value corresponding to the counter value while decrementing.
  • the AZ units 40 and 42 adjust the voltage of the signal input during the period (not shown) instructed by the auto-zero circuit mechanism of the image control unit 8 to the AZ reference voltage, and adjust the voltage of the input signal and the voltage of the output. Preserve the offset with And it is possible to continue to maintain the voltage offset beyond the indicated period. More specifically, the AZ section 40 holds the input voltage from the DAC section 30 and the offset voltage of the output voltage for the indicated period. The AZ unit 42 holds the input voltage from the selector SEL11, that is, the vertical signal line VLS1 or 2, and the offset voltage of the output voltage during the designated period.
  • the comparator 44 compares the output voltage after passing through the AZ section 40 of the DAC section 30, that is, the output voltage of the AZ section 40, and the output voltage after passing through the AZ section 42 of the selector SEL11, that is, the output voltage of the AZ section 42. Then, the comparator 44 inverts the output value when the output voltage of the AZ section 40 falls below the voltage of the output voltage of the AZ section 42 .
  • the counter 46 starts counting from the beginning of the ADC period and stops when the output of the comparator is inverted.
  • the value of the stopped counter becomes digital data, which is the result of AD conversion.
  • the other AD converters ADC12-14, 21-24 have the same configuration as the AD converter ADC11, and the description thereof is omitted.
  • the circuit configuration of the AD converter ADC11 is equivalent to that of a general image sensor circuit. Therefore, it is also possible to acquire a normal shot image.
  • the AZ unit 42 holds the offset voltage between the input voltage from the selector SEL11, that is, the vertical signal line VLS1, and the output voltage during the designated period. Then, the input voltage, which is the image signal from the VLS1, is offset-corrected and then output. That is, in the case of normal imaging, the AD converter ADC11 AD-converts the image signal that is input after the offset component with the first input voltage that is the offset component as the zero reference point.
  • FIG. 11 is a diagram specifically showing an example of difference processing in the AD converter ADC11 between the pixel values of the green pixels (first pixels) on the first row and the green pixels (second pixels) on the second row.
  • the vertical axis indicates the state change, the AZ reference voltage, the voltage of the VSL line after passing through the AZ section 42, the voltage of the DAC section 30 after passing through the AZ section 40, and the ADC counter of the counter section 46, and the horizontal axis indicates time.
  • . 12 is a diagram equivalent to FIG. 11.
  • FIG. 11 shows the case where the output voltage of the green pixel PX21 (second pixel) is lower than the output voltage of the green pixel PX12 (first pixel), and FIG. 12 shows the case where the output voltage of the green pixel PX21 (second pixel) is higher than the output voltage of the green pixel PX12 (first pixel). That is, FIG. 11 shows an example in which the second pixel is darker, and FIG. 12 shows an example in which the second pixel is brighter.
  • the output of the floating diffusion FD of the green pixel PX12 (first pixel) in the first row and the select transistor SW3 between the vertical signal line VSL1 are electrically connected.
  • the output voltage (pixel signal) of the first pixel is output to the vertical signal line VSL1.
  • the output voltage of the DAC section 30 and the voltage level of the vertical signal line VSL1 are matched with the AZ reference voltage by the auto-zero mechanisms of the AZ sections 40 and 42, respectively.
  • the output voltage of the first pixel is adjusted to the zero reference for AD conversion.
  • the AZ units 40 and 42 continue to hold their respective offset values.
  • the output value of the green pixel PX21 (second pixel) is output to the vertical signal line VSL2.
  • the AZ unit 42 outputs the output voltage of the green pixel PX21 (second pixel) while holding the offset value. Accordingly, in the “AD conversion state”, the AZ section 42 outputs the difference value between the output voltage of the first pixel and the output voltage of the second pixel to the comparator 44 .
  • the AZ unit 40 corrects the reference voltage output by the DAC unit 30 from a predetermined initial value to a predetermined final value according to the counter, and corrects the reference voltage by using the offset value held by the comparator. 44. Thereby, the AZ unit 40 adjusts the reference voltage to the zero reference for AD conversion.
  • the comparator 44 inverts the output value at the second point in time when the output voltage of the AZ section 40 falls below the voltage of the output voltage of the AZ section 42 .
  • the ADC counter of the counter unit 46 counts the second time point after the first time point when outputting the reference voltage is started, and converts it into a digital value. As shown in FIG. 11, before the reference voltage coincides with the AZ reference voltage, it is negative. That is, it indicates that the output voltage of the green pixel PX21 (second pixel) is lower than the output voltage of the green pixel PX12 (first pixel).
  • the reference voltage is after the point in time when it matches the AZ reference voltage, it indicates positive. That is, it indicates that the output voltage of the green pixel PX21 (second pixel) is higher than the output voltage of the green pixel PX12 (first pixel).
  • the signal of the vertical signal line VSL (after passing through AZ) changes twice during the period of the "auto zero (AZ) state". It shows how the FD of the pixel is selected from the state in which there is no FD.
  • the second and subsequent differential AD conversions since the FD of the second pixel is operated from the selected state, there is only one change.
  • FIG. 13 is a time chart showing an example of differential processing from time t10 to t21
  • FIG. 14 is a time chart including an example of differential processing from time t22 to t24
  • FIG. 15 is an example of differential processing for the last line.
  • is a time chart including The vertical axis indicates signals RST8, TRG8, SEL8, . . . RST1, TRG1, SEL1, AD converter state State, and selection signals SEL_L and SEL_R from the top, and the horizontal axis indicates time.
  • “0" (left) in the selection signals SEL_L and SEL_R is called low level
  • "1" (right) is called high level.
  • the signals RST1 and SEL_L first go high at time t10.
  • the reset transistor SW2 of the pixels in the first row is turned on when the high-level reset signal RST1 is input to the gate through the signal line Rst1, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal SEL1 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. At this time, the amplified potential of the floating diffusion FD is such that SEL_L is at high level and SEL_R is at low level, so green pixels in the first row are selected. Then, they are output to the corresponding AD converters ADC11-14, 21-24 (see FIG. 6).
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the green pixels in the first row to the reference value (zero value). do. Henceforth, the AZ circuit saves this offset amount.
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. At this time, the amplified potential of the floating diffusion FD has SEL_L at low level and SEL_R at high level, so the green pixels in the second row are selected. Then, they are output to the corresponding AD converters ADC11-14, 21-24 (see FIG. 7).
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t15 and t16 (see FIGS. 11 and 12). In this way, the AD converters ADC11-14, 21-24 perform AD conversion and output data of the difference between the green pixels in the first row and the second row.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the green pixels in the second row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the non-pixels in the first row to the reference value (zero value). set.
  • the AZ circuit saves this offset amount.
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. At this time, the amplified potential of the floating diffusion FD has SEL_L at low level and SEL_R at high level, so the green pixels in the third row are selected. Then, they are output to the corresponding AD converters ADC11-14, 21-24 (see FIG. 8).
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t19 and t20 (see FIGS. 11 and 12). In this manner, the AD converters ADC11 to ADC14, 21 to 24 perform AD conversion and output the difference between the green pixels in the second row and the third row as data.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the green pixels in the third row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. As for the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level, so the green pixels in the fourth row are selected. Then, they are output to the corresponding AD converters ADC11-14, 21-24.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t23 and t24 (see FIGS. 11 and 12).
  • the AD converters ADC11 to ADC14, 21 to 24 perform AD conversion and output the difference between the green pixels in the third row and the fourth row as data.
  • each differential AD conversion can be operated continuously. Therefore, it is possible to contribute to shortening of the stabilization waiting time (settling time) after the control.
  • the auto-zeroing by the FD on the 7th row ends. (FD reset on line 8)
  • the signals RST8 and SEL_R become high level, and SEL_L becomes low level.
  • the reset transistor SW2 of the pixel on the eighth row is turned on when the high-level reset signal RST8 is input to the gate through the signal line Rst8, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal SEL8 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level, so the green pixels in the eighth row are selected. Then, they are output to the corresponding AD converters ADC11-14, 21-24.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t32 and t33 (see FIGS. 11 and 12). In this way, the AD converters ADC11-14, 21-24 perform AD conversion and output data of the difference between the green pixels in the 7th row and the 8th row. Then, the signal SEL8 is set to low level to end the AD conversion.
  • the image sensor 2 includes the AD conversion unit 14 having the AD converter ADC11 and the AD converter ADC12, and the second AD conversion unit 18 having the AD converter ADC21, AD converter ADC11 is connected to vertical signal line VSL1 and vertical signal line VSL2 via selector SEL11, AD converter ADC12 is connected to vertical signal line VSL3 and vertical signal line VSL4 via selector SEL12, and AD converter ADC21 is connected to vertical signal line VSL3 and vertical signal line VSL4 via selector SEL12.
  • the selectors SEL11 and SEL12 are connected to the first selected drive line Sel_L
  • the selector SEL21 is connected to the second selected drive line Sel_R. It was supposed to be connected.
  • the selectors SEL11, 12, 21 select the vertical signal lines VSL1, VSL3, VSL3, respectively, and then select the vertical signal lines VSL2, VSL2, VSL4, respectively, the AD converter ADC11 and the AD converter ADC11 are arranged in one row.
  • the difference between the green pixel in the second row and the upper left green pixel in the second row can be calculated, and the AD converter ADC21 calculates the difference between the green pixel in the first row and the upper right green pixel in the second row. can be calculated.
  • the selectors SEL11, 12 and 21 select the vertical signal lines VSL1, VSL2 and VSL3 respectively, normal images can be captured. With such a configuration, the same number of AD converters as the vertical signal lines VSL can capture a differential image and a normal image. Further, by arranging the AD conversion section 14 and the second AD conversion section 18 on the same end side of the pixel array 10, wiring can be simplified compared to the case of arranging them on both ends.
  • the electronic device according to the second embodiment is different from the electronic device according to the first embodiment in that it can calculate a difference value between red and blue pixels. Differences from the electronic device according to the first embodiment will be described below.
  • FIG. 16 is a diagram showing an example of difference processing in the pixel array section 10 according to the second embodiment.
  • the difference processing according to the present embodiment it is possible to perform difference processing between basic pixel groups G10 in the Bayer array.
  • the 2 ⁇ 2 basic pixel group G10 on the 1st and 2nd rows is subjected to difference processing between the same colors of the diagonally upper basic pixel group G10 on the 3rd and 4th rows.
  • FIG. 17 is a diagram showing an example of circuits of the pixel array section 10, the first selection section 12a, the first AD conversion section 14a, the second selection section 16a, and the second AD conversion section 18a according to the second embodiment.
  • the number of pixels is described as 8 ⁇ 8 or 10 ⁇ 8 for the sake of simplicity, the number is not limited to this.
  • the first selection unit 12a has selection units SEL11 to SEL18.
  • the first selection unit 12a selects (((n ⁇ 1) ⁇ 8+m), ((n ⁇ 1) ⁇ 8+m+4)) (n is 1 to M/ 4, m selects one of the combination of the two signal lines 1 to 4), and outputs the signal of the selected signal line to the first AD converter 14a.
  • the number of vertical signals (VSL) in the pixel array section 10 is, for example, 1 to M (eg, M is a multiple of 8).
  • the first selection unit 12a selects the ((n ⁇ 1) ⁇ 8+m)-th vertical signal line VSL with the selector control signal (left) (SEL_L) being a “0” selection signal. Select if Also, the ((n ⁇ 1) ⁇ 8+m+4)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal.
  • the first selection unit 12a alternately selects signals of vertical signals (VSL) skipping three lines.
  • the first AD converter 14a has AD converters ADC11-18.
  • AD converters ADC11-18 are connected to corresponding selectors SEL11-18, respectively.
  • the second selection unit 16a has selection units SEL21-28.
  • the first selection unit 12a selects ((n ⁇ 1) ⁇ 8+m+4, (n ⁇ 8+m)) (n is 1 to M/4, m is 1 to 1) among a plurality of vertical signals (VSL) of the pixel array unit 10. 4) Select one of the combination of the two signal lines, and output the signal of the selected signal line to the second AD converter 18a.
  • the number of vertical signals (VSL) in the pixel array section 10 is, for example, 1 to M (eg, M is a multiple of 8).
  • the second selection unit 16a selects the ((n ⁇ 1) ⁇ 8+m+4)-th vertical signal line VSL so that the selector control signal (right) (SEL_R) is a “0” selection signal. Select if Also, the (n ⁇ 8+m)-th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • the first selection unit 16a alternately selects three vertical signals (VSL).
  • the second AD converter 18a has AD converters ADC21-28.
  • AD converters ADC21-28 are connected to corresponding selectors SEL21-28, respectively.
  • the AD converters ADC 11 to 18 and 21 to 28 of the first AD conversion unit 14a and the second AD conversion unit 18a also correspond to each vertical signal line VSL to configure the AD converter ADC. This is twice the number of AD converters ADC according to the embodiment.
  • the first selection unit 12a and the second selection unit 16a connect the vertical signal lines VSL connected to the pixels separated by one basic pixel group G10, that is, the vertical signal lines VSL separated by three It has a structure that connects between
  • the circuit structure is divided into two groups of the first selection unit 12a and the first AD conversion unit 14a and the second selection unit 16a and the second AD conversion unit 18a. do.
  • the image control unit 8 selects the control lines 1 and 2 (control wires 1, 2) and deselects the control lines 3 to 10 (control wires 3 to 10). This connects the pixels in the first and second rows to the vertical signal line VSL.
  • the pixel data connected to VSL1, VSL2, VSL3 and VSL4 are input to AD converters ADC11, 12, 13 and 14 in order.
  • pixel data connected to VSL9, VSL10, VSL11 and VSL12 are input to AD converters ADC21, 22, 23 and 24 in order.
  • the same data is also input to AD converters ADC15, 16, 17 and 18 in order.
  • AZ auto zero
  • the image control unit 8 selects the control lines 3 and 4 and deselects the control lines 1, 2, 5-10. Thereby, only the pixel data of the rows of the control lines 3 and 4 are connected to each VSL (vertical signal line).
  • pixel data connected to VSL5, VSL6, VSL7, and VSL8 are input to AD converters ADC11, 12, 13, and 14 in order.
  • Pixel data connected to VSL5, VSL6, VSL7 and VSL8 are connected to AD converters ADC21, 22, 23 and 24 in order, and pixel data connected to VSL13, VSL14, VSL15 and VSL16 are connected to ADC15, ADC16, ADC17 and ADC18 in order.
  • pixel data is input.
  • the AD converters ADC11-18, 21-24 perform AD conversion, so that ADC11, ADC12, ADC13, and ADC14 are the same color in units of 2 ⁇ 2 pixels, and the difference from the upper right corner, ADC21, ADC22, and ADC23 , ADC24 can obtain the difference between the same color in 2 ⁇ 2 pixel units and the upper left diagonal, and the ADC15, ADC16, ADC17, and ADC18 can obtain the difference between the same color in 2 ⁇ 2 pixel units and the upper right diagonal.
  • This series of operations affects all pixels and ADCs, and by repeating them, it is possible to obtain a same-color difference image in units of 2 ⁇ 2 pixels for the entire screen. Since the ADC25, ADC26, ADC27, and ADC28 are located at the right end, the difference from the VSL on the right cannot be obtained, so processing such as discarding AD-converted data is possible.
  • FIG. 18 is a diagram showing a circuit configuration example of the pixel basic unit G10 according to the second embodiment.
  • the pixel PX11 includes a photodiode PD, a transfer transistor SW1, a reset transistor SW2, an amplification transistor AMP, a selection transistor SW3, and a rotating diffusion FD.
  • the basic unit G10 of pixels according to the second embodiment differs from the basic unit G10 of pixels according to the first embodiment in that vertically aligned pixels in the same column are connected to different vertical signal lines VSL. That is, the sources of the select transistors SW3 of the pixel PX11 and the pixel PX21 are connected to different vertical signal lines VSL1 and VSL2, respectively.
  • the sources of the selection transistors SW3 of the pixels PX12 and PX22 are connected to different vertical signal lines VSL3 and VSL4, respectively. Since the vertical signal VSL is twice as large as the pixel basic unit G10 according to the first embodiment, it is possible to simultaneously AD-convert two lines that do not conflict with each other. The subsequent operation and the like are the same as those of the pixel basic unit G10 according to the first embodiment, so description thereof will be omitted.
  • FIG. 19 is a time chart showing an example of differential processing from time t40 to t51
  • FIG. 20 is a time chart including an example of differential processing from time t51 to t44
  • FIG. 21 is an example of differential processing for the last line.
  • the horizontal axis represents time. It is different from the difference processing example of the image sensor 2 according to the first embodiment in that two rows are controlled simultaneously and that the difference between the same colors in units of 2 ⁇ 2 pixels is output.
  • signals RST1, RST2 and SEL_R go high at time t40.
  • the reset transistors SW2 of the pixels on the 1st and 2nd rows are turned on when the high-level reset signal RST1 is input to their gates through the signal line Rst1, and reset the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signals RST1 and RST2 become low level, and the set transistor SW2 is disconnected. Then, the signals TRG1 and TRG2 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the first and second rows are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • signals SEL1 and SEL2 become high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. As a result, the AD converters ADC11-14 are electrically connected to the vertical signal lines VSL1-4, the AD converters ADC15-ADC18 are electrically connected to the vertical signal lines VSL9-12, and pixel data is input to each AD converter.
  • the AD converters ADC21-24 are electrically connected to the vertical signal lines VSL9-12, the AD converters ADC25-ADC28 are electrically connected to the dummy, and the pixel data is transferred to each AD converter. to enter.
  • the AD converters ADC25 to ADC28 are not used in the second example because they are positioned at the right end and the vertical signal line VSL does not exist on the right side. It should be noted that it is also possible to omit the selection units SEL25 to SEL28 instead of the dummy signal.
  • the AZ units 40 and 42 of the AD converters ADC11-18 and 25-25 execute AZ (auto zero) to set the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST3 and RST4 become low level, and the set transistor SW2 is disconnected. Then, the signals TRG3 and TRG4 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the 3rd and 4th rows are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • signals SEL3 and SEL4 become high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level. Thereby, the AD converters ADC11 to ADC14 are electrically connected to VSL5 to VSL8, the AD converters ADC15 to ADC18 are electrically connected to VSL13 to VSL16, and the data of each pixel are input to each AD converter.
  • AD converters ADC21 to ADC24 are electrically connected to VSL5 to VSL8, AD converters ADC25 to ADC28 are electrically connected to VSL13 to VSL16, and data of respective pixels are input to each AD converter. At this time, the AD conversion of each AD converter ADC is performed, and the difference between the same colors in the first and second rows and the third and fourth rows is output as data.
  • the AD converters ADC11 to ADC14 are electrically connected to VSL5 to VSL8, the AD converters ADC15 to ADC18 are electrically connected to VSL13 to VSL16, and the data of each pixel are input to each AD converter.
  • AD converters ADC21 to ADC24 are electrically connected to VSL5 to VSL8, AD converters ADC25 to ADC28 are electrically connected to VSL13 to VSL16, and data of respective pixels are input to each AD converter.
  • the AZ units 40, 42 of the AD converters ADC11-18, 21-28 execute AZ (auto zero) to set a new reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • signals SEL5 and SEL6 become high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. Thereby, the AD converters ADC11 to ADC14 are electrically connected to the vertical signal lines VSL1 to 4, the ADC15 to ADC18 are electrically connected to the vertical signal lines VSL9 to 12, and the data of each pixel is input to each AD converter.
  • AD conversion ADC21 to ADC24 are connected to VSL9 to VSL12
  • AD conversion ADC25 to ADC28 are connected to dummy, and the data of each pixel is input to each ADC.
  • A/D conversion is performed to output the data of the differences between the same colors in the 2 ⁇ 2 pixel units of the 3rd, 4th, and 5th, 6th rows.
  • the AZ units 40, 42 of the AD converters ADC11-18, 21-28 execute AZ (auto zero) to set a new reference value (zero value).
  • signals SEL7 and SEL8 become high level.
  • the potentials of the FDs of the seventh and eighth rows are amplified by the AMP and output to the vertical signal line VSL.
  • SEL_L is set to high level
  • SEL_R is set to low level.
  • the AD converters ADC11-14 are electrically connected to the vertical signal lines VSL5-VSL8, the AD converters ADC15-ADC18 are electrically connected to the vertical signal lines VSL13-VSL16, and the data of each pixel is input to each AD converter. .
  • AD converters ADC21-24 are electrically connected to vertical signal lines VSL5-8
  • AD converters ADC25-ADC28 are electrically connected to vertical signal lines VSL13-VSL16
  • the data of each pixel is input to each AD converter.
  • AD conversion is performed in each AD converter, and the difference between the same color pixels in the 5th and 6th rows and the 7th and 8th rows of 2 ⁇ 2 pixel units is output as data.
  • the selection signals SEL_L and SEL_R are controlled to be inverted each time. Further, when the number of pixels in the vertical direction of the pixel array section 10 is expanded, such control of differential AD conversion is repeated.
  • signals SEL7 and SEL8 are at high level, SEL_L is at low level, and SEL_R is at high level. Therefore, the AZ units 40, 42 of the AD converters ADC11-18, 21-28 execute AZ (auto zero) to set a new reference value (zero value).
  • the signals RST9 and RST10 go low, and the reset transistor SW2 is disconnected. Then, the signals TRG9 and 10 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the 9th and 10th rows are transferred to the floating diffusion FD.
  • signals SEL9 and SEL10 go high.
  • the potentials of the FDs of the 9th and 10th rows are amplified by the signals SEL9 and SEL10 and output to the vertical signal line VSL.
  • SEL_L and SEL_R are inverted, and difference data is obtained in the same way as before. Since it is the last row and there is no next differential AD conversion, the SE signals SEL9 and SEL10 are set to low level to end the AD conversion.
  • the first selector 12a selects the ((n ⁇ 1) ⁇ 8+m)-th vertical signal line VSL so that the selector control signal (left) (SEL_L) is “0”. Select if it is a selection signal. Also, the ((n ⁇ 1) ⁇ 8+m+4)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal.
  • the second selection unit 16a selects the ((n ⁇ 1) ⁇ 8+m)-th vertical signal line VSL when the selector control signal (right) (SEL_R) is a “0” selection signal. do.
  • the ((n ⁇ 1) ⁇ 8+m+4)-th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • SEL_R selector control signal
  • the pixels in each two rows of the pixel array section 10 are electrically connected to the vertical signal line VSL in order, and the values of SEL_L and SEL_R are alternately controlled so that each pixel in the basic unit G10 is can calculate the difference with each pixel in the basic unit G10 on the upper left or on the upper right.
  • the electronic device according to the third embodiment is different from the electronic device according to the first embodiment in that the differential value between red and blue pixels can be calculated by sequentially reading out odd-numbered rows or even-numbered rows. Differences from the electronic device according to the first embodiment will be described below.
  • FIG. 22 is a diagram showing an example of odd-numbered row difference processing in the pixel array unit 10 according to the third embodiment.
  • the difference processing according to the present embodiment it is possible to perform difference processing between basic pixel groups G10 in the Bayer array.
  • the 2 ⁇ 2 basic pixel group G10 (on the 1st and 2nd rows) is subjected to difference processing between the same colors of the diagonally upper basic pixel group G10 on the 3rd and 4th rows. , green pixels can be subtracted.
  • FIG. 23 is a diagram showing an example of even-numbered row differential processing in the pixel array unit 10 according to the third embodiment.
  • the difference processing according to the present embodiment it is possible to perform difference processing between basic pixel groups G10 in the Bayer array.
  • the 2 ⁇ 2 basic pixel group G10 (on the 1st and 2nd rows) is subjected to difference processing between the same colors of the diagonally upper basic pixel group G10 on the 3rd and 4th rows. , it is possible to perform differential processing of blue pixels.
  • FIG. 24 is a diagram showing an example of circuits of the pixel array section 10, the first selection section 12b, the first AD conversion section 14b, the second selection section 16b, and the second AD conversion section 18b according to the third embodiment.
  • the number of pixels is described as 8 ⁇ 8 or 10 ⁇ 8 for the sake of simplicity, the number is not limited to this.
  • the first selector 12b has selectors SEL11 to SEL14.
  • the first selection unit 12b selects (((n ⁇ 1) ⁇ 4+m), ((n ⁇ 1) ⁇ 4+m+2)) (n is 1 to M/ 4, m selects one of the combination of the two signal lines 1 to 2), and outputs the signal of the selected signal line to the first AD converter 14b.
  • VSL vertical signals
  • the first selection unit 12b selects the ((n ⁇ 1) ⁇ 4+m)-th vertical signal line VSL with the selector control signal (left) (SEL_L) being a “0” selection signal. Select if Also, the ((n ⁇ 1) ⁇ 4+m+2)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal.
  • the first selection unit 12b alternately selects signals of vertical signals (VSL) skipping one line.
  • the first AD converter 14b has AD converters ADC11-14.
  • AD converters ADC11-14 are connected to corresponding selectors SEL11-14, respectively.
  • the second selection unit 16b has selection units SEL21-24.
  • the first selection unit 12b selects (((n ⁇ 1) ⁇ 4+m+2), (n ⁇ 4+m)) (n is 1 to M/4, m is One of the combinations of the two signal lines 1 to 2) is selected, and the signal of the selected signal line is output to the second AD converter 18b.
  • the second selection unit 16b selects the ((n ⁇ 1) ⁇ 4+m+2)-th vertical signal line VSL so that the selector control signal (right) (SEL_R) is a “0” selection signal. Select if Also, the ((n ⁇ 1) ⁇ 4+m+4))th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • the first selection unit 16b alternately selects signals of vertical signals (VSL) skipping one line.
  • the second AD converter 18b has AD converters ADC21-24.
  • AD converters ADC21-24 are connected to corresponding selectors SEL21-24, respectively.
  • the circuit structure is divided into two groups of the first selection unit 12b and the first AD conversion unit 14b and the second selection unit 16b and the second AD conversion unit 18b. do.
  • the image control unit 8 selects control wire 1 (control wires 1) and deselects control wires 2 to 10 (control wires 2 to 10). Thereby, the pixels in the first row are connected to the vertical signal line VSL.
  • pixel data electrically connected to VSL1 and VSL2 are input to AD converters ADC11 and ADC12 in order.
  • pixel data electrically connected to VSL5 and VSL6 are input to AD converters ADC 21 and 22 in order.
  • the same data is also input to the AD converters ADC13 and 14 in order.
  • auto zero (AZ) to the AD converters ADC11-18 and 21-24, the level of the signal voltage output by the pixel in question is set to the reference value of each ADC, that is, the value of 0.
  • the image control unit 8 selects the control line 3 and deselects the control lines 1, 2, 4-10. Thereby, only the pixel data of the row of the control line 3 is connected to each VSL (vertical signal line).
  • pixel data electrically connected to VSL3 and VSL4 are input to AD converters ADC11 and 12 in order.
  • Pixel data electrically connected to VSL3 and VSL4 are input to AD converters ADC21 and 22, and pixel data electrically connected to VSL7 and VSL8 are input to ADC13 and ADC14, respectively.
  • the AD converters ADC11 to 14 and 21 to 24 perform AD conversion, so that the ADC11 and ADC12 are the same color in units of 2 ⁇ 2 pixels and the difference from the upper right corner, and the ADC13 and ADC14 are the same color in units of 2 ⁇ 2 pixels. You can get the difference from the upper right corner with .
  • the differential data in the screen is obtained by repeating the odd-numbered rows over the entire pixel array, such as the difference between the 3rd to 5th rows. This makes it possible to generate difference data between a red pixel and a green pixel on the same row as the red pixel.
  • FIG. FIG. 25 is a time chart showing an example of differential processing from time t10 to t21
  • FIG. 26 is a time chart including an example of differential processing from time t21 to t24
  • FIG. 4 is a time chart including a processing example
  • the vertical axis represents signals RST10, TRG10, SEL10, . . . RST1, TRG1, SEL1, the AD converter state State, and signals SEL_L and SEL_R from the top
  • the horizontal axis represents time. This differs from the example of differential processing of the image sensor 2 according to the first embodiment in that it processes each odd-numbered row. Further, when performing the example of differential processing for odd rows, the signals on the control lines for even rows are all maintained at the low level.
  • the signals RST1 and SEL_L first go high at time t10.
  • the reset transistor SW2 of the pixels in the first row is turned on when the high-level reset signal RST1 is input to the gate through the signal line Rst1, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST1 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels in the first row are transferred to the floating diffusion FD.
  • the signal SEL1 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • the AD converters ADC11, 12 are electrically connected to the vertical signal lines VSL1, 2, the AD converters ADC13, 14 are electrically connected to the vertical signal lines VSL5, 6, and the data of each pixel is transferred to each AD input to the converter. Since SEL_R is 1 (High), the AD converters ADC21 and 22 are electrically connected to the vertical signal lines VSL5 and 6, the AD converters ADC23 and 24 are connected to dummy, and the data of each pixel is Input to the AD converter.
  • each AD converter executes AZ (auto zero) during the period of time t12 to t13 to set the pixel data of the first row to the reference value (zero value).
  • AZ auto zero
  • the signals RST3 and SEL_R go low, and SEL_L goes high.
  • the reset transistor SW2 of the pixel on the third row is turned on when the high-level reset signal RST2 is input to the gate through the signal line Rst2, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST3 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG3 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels in the third row are transferred to the floating diffusion FD.
  • the signal SEL3 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • the AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is transferred to each AD. input to the converter.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and the data of each pixel is Input to the AD converter.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t15 and t16.
  • the AD converters ADC11 to ADC14, 21 to 24 perform AD conversion and perform difference processing between the red and green pixels in the first and third rows alternately.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixel data of the third row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST5 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the pixel on the fifth row is turned on when the high-level reset signal RST3 is input to the gate through the signal line Rst3, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST3 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG5 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the fifth row are transferred to the floating diffusion FD.
  • the signal SEL5 goes high at time t19. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level.
  • AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL1 and 2
  • the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL5 and 6, and the data of each pixel is Input to the AD converter.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL5 and 6
  • AD converters ADC23 and 24 are electrically connected to dummy, and data of respective pixels or dummy signals are transmitted to respective AD converters.
  • each AD converter performs AD conversion.
  • Difference information is important in the field of recognition because shapes are important.
  • the shape can also be determined by color. Therefore, it can be used for recognition that emphasizes color.
  • a three-dimensional ranging technique that projects a color texture pattern makes it possible to output the changing points of the color pattern at high speed and with low power consumption. In addition, it becomes possible to contribute to improvement in the recognition speed of the system and reduction in power consumption.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixels in the fifth row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST7 and SEL_L go high, and SEL_R goes low.
  • the reset transistor SW2 of the pixel on the seventh row is turned on when the high-level reset signal RST7 is input to the gate through the signal line Rst7, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST7 becomes low level, and the reset transistor SW2 is disconnected. Then, the signal TRG7 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the 7 pixels in the 7th row are transferred to the floating diffusion FD.
  • the signal SEL7 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • AD converters ADC11 and 12 are electrically connected to vertical signal lines VSL1 and 2, As a result, the AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is converted to each AD conversion signal. input to the device.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and data of respective pixels are converted into respective AD converters. input to the device.
  • each AD converter performs AD conversion to generate difference data between pixels of the same color between the 2 ⁇ 2 pixel units G10 on the fifth and seventh rows.
  • the levels of SEL_L and SEL_R are controlled to be inverted each time.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixels in the seventh row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST9 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the pixel on the ninth row is turned on when the high-level reset signal RST9 is input to the gate through the signal line Rst9, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST9 becomes low level, and the reset transistor SW2 is disconnected. Then, the signal TRG9 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the 9 pixels in the 9th row are transferred to the floating diffusion FD.
  • the signal SEL9 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is converted to each AD conversion signal. input to the device.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and data of respective pixels are converted into respective AD converters. input to the device.
  • each AD converter performs AD conversion to generate differential data between pixels of the same color between the 2 ⁇ 2 pixel units G10 on the 7th and 9th rows.
  • FIG. FIG. 28 is a time chart showing an example of differential processing from time t10 to t21
  • FIG. 29 is a time chart including an example of differential processing from time t21 to t24
  • FIG. 4 is a time chart including a processing example
  • the vertical axis represents signals RST10, TRG10, SEL10, . . . RST1, TRG1, SEL1, the AD converter state State, and signals SEL_L and SEL_R from the top
  • the horizontal axis represents time. 25 to 27 in that the processing is performed for each even-numbered row. Further, when performing the example of differential processing for even rows, the signals on the control lines for odd rows are all maintained at the low level.
  • the signals RST2 and SEL_L first go high at time t10.
  • the reset transistor SW2 of the pixels in the second row is turned on when the high-level reset signal RST2 is input to the gate through the signal line Rst2, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST2 goes low and the set transistor SW2 is disconnected. Then, the signal TRG1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels in the second row are transferred to the floating diffusion FD.
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • the AD converters ADC11, 12 are electrically connected to the vertical signal lines VSL1, 2, the AD converters ADC13, 14 are electrically connected to the vertical signal lines VSL5, 6, and the data of each pixel is transferred to each AD input to the converter. Since SEL_R is 1 (High), the AD converters ADC21 and 22 are electrically connected to the vertical signal lines VSL5 and 6, the AD converters ADC23 and 24 are connected to dummy, and the data of each pixel is Input to the AD converter.
  • each AD converter executes AZ (auto zero) during the period of time t12 to t13 to set the pixel data of the second row to the reference value (zero value).
  • AZ auto zero
  • the signals RST4 and SEL_R go low, and SEL_L goes high.
  • the reset transistor SW2 of the pixel on the fourth row is turned on when the high-level reset signal RST4 is input to the gate through the signal line Rst4, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST4 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG4 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels in the fourth row are transferred to the floating diffusion FD.
  • the signal SEL4 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • the AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is transferred to each AD. input to the converter.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and the data of each pixel is Input to the AD converter.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t15 and t16.
  • the AD converters ADC11-14, 21-24 perform AD conversion and perform difference processing between the green and blue pixels in the second and fourth rows alternately.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixel data of the third row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST6 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the pixel on the sixth row is turned on when the high-level reset signal RST6 is input to the gate through the signal line Rst6, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST6 goes low and the set transistor SW2 is disconnected. Then, the signal TRG6 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the sixth row are transferred to the floating diffusion FD.
  • the signal SEL6 goes high at time t19. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level.
  • AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL1 and 2
  • the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL5 and 6, and the data of each pixel is Input to the AD converter.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL5 and 6
  • AD converters ADC23 and 24 are electrically connected to dummy, and data of respective pixels or dummy signals are transmitted to respective AD converters.
  • each AD converter performs AD conversion. As described above, in this embodiment, it is possible to extract the difference in the diagonal direction of the same color in the 2 ⁇ 2 pixel unit G10.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixels in the fifth row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST8 and SEL_L go high, and SEL_R goes low.
  • the reset transistor SW2 of the pixel on the eighth row is turned on when the high-level reset signal RST8 is input to the gate through the signal line Rst7, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST8 becomes low level, and the reset transistor SW2 is disconnected. Then, the signal TRG8 becomes high level. As a result, the signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the eight pixels in the eighth row are transferred to the floating diffusion FD.
  • the signal SEL8 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is converted to each AD conversion signal. input to the device.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and data of respective pixels are converted into respective AD converters. input to the device.
  • each AD converter performs AD conversion to generate difference data between pixels of the same color between the 2 ⁇ 2 pixel units G10 on the 6th and 8th rows.
  • the levels of SEL_L and SEL_R are controlled to be inverted each time.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the pixels in the seventh row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST10 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the pixel on the 10th row is turned on when the high-level reset signal RST10 is input to the gate through the signal line Rst10, and resets the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the signal RST10 becomes low level, and the reset transistor SW2 is disconnected. Then, the signal TRG10 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD of the pixels on the 10th row are transferred to the floating diffusion FD.
  • the signal SEL10 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level.
  • AD converters ADC11 and 12 are electrically connected to the vertical signal lines VSL3 and VSL4, the AD converters ADC13 and 14 are electrically connected to the vertical signal lines VSL7 and VSL8, and the data of each pixel is converted to each AD conversion signal. input to the device.
  • AD converters ADC21 and 22 are electrically connected to vertical signal lines VSL3 and 4
  • AD converters ADC23 and 24 are electrically connected to vertical signal lines VSL7 and VSL8, and data of respective pixels are converted into respective AD converters. input to the device.
  • each AD converter performs AD conversion to generate difference data between pixels of the same color between the 2 ⁇ 2 pixel units G10 on the 8th and 10th rows.
  • the second control method of the third embodiment differs from the first control method of the third embodiment only in the timing chart.
  • the first control method only the odd rows are read out and AD-converted once, and then the even rows are read out and AD-converted in the same procedure. Therefore, the exposure timing differs between the odd-numbered rows and the even-numbered rows.
  • the second control method is different in that the procedure up to the reading of the even rows (charge transfer to the FD) is simultaneously performed while the reading of the odd rows and AD conversion are being performed. Therefore, it is possible to match the exposure timings of the odd-numbered rows and the even-numbered rows. As a result, it is possible to suppress artifacts due to differences in the exposure timing of the moving subject.
  • the charges on the even rows are read out at the same time to transfer the charges of the pixels to the FD.
  • the charge transferred to the FD is AD-converted without performing the pixel transfer.
  • FIG. 31 to 33 show AD conversion processing for odd rows and charge transfer processing to FDs for even rows
  • FIGS. 34 to 34 show AD conversion processing for even rows.
  • the vertical axis represents signals RST10, TRG10, SEL10, . . . RST1, TRG1, SEL1, the AD converter state State, and signals SEL_L and SEL_R from the top
  • the horizontal axis represents time. This differs from the example of differential processing of the image sensor 2 according to the first embodiment in that it processes each odd-numbered row. Further, when performing the example of differential processing for odd rows, the signals on the control lines for even rows are all maintained at the low level. Differences from the first control method of the third embodiment will be mainly described below.
  • FIG. 31 is a time chart showing an example of differential processing from time t10 to t21 according to the second control method
  • FIG. FIG. 33 is a time chart including an example of difference processing for the odd last row according to the second control method.
  • FIG. 34 is a time chart showing an example of differential processing from time t30 to t41 according to the second control method
  • FIG. FIG. 36 is a time chart including an example of differential processing of even-numbered last rows according to the second control method.
  • signals RST1, RST2 and SEL_L go high at time t10.
  • the reset transistors SW2 of the pixels on the 1st and 2nd rows are turned on when the high-level reset signal RST1 is input to their gates through the signal line Rst1, and reset the floating diffusion FD to the voltage of the constant voltage source VSS.
  • the accumulated signal charges (here, photoelectrons) of even rows are transferred to the floating diffusion FD from time t17 to t19, time t21 to t23, and time t22 to t27. is different from control method 1.
  • the subsequent processing is the same as that of the control method 1, so the description is omitted.
  • FIGS. 34 to 36 show AD conversion processing for even-numbered rows, corresponding to the processing in FIGS. 28 to 30, respectively.
  • the accumulated signal charges (here, photoelectrons) of even rows has already been transferred to the floating diffusion FD. Therefore, the processes of FIGS. 34 to 36 are different from the processes shown in FIGS. 28 to 30 in that the signal charges accumulated in even rows are not transferred to the floating diffusion FD.
  • the subsequent processing is the same as that of the control method 1, so the description is omitted.
  • the first selector 12b selects the ((n ⁇ 1) ⁇ 4+m)-th vertical signal line VSL so that the selector control signal (left) (SEL_L) is “0”. Select if it is a selection signal. Also, the ((n ⁇ 1) ⁇ 4+m+2)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal.
  • the second selection unit 16b selects the ((n ⁇ 1) ⁇ 4+m+2)-th vertical signal line VSL when the selector control signal (right) (SEL_R) is a “0” selection signal. do.
  • the ((n ⁇ 1) ⁇ 4+m+4))th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • SEL_R selector control signal
  • the pixels in the odd-numbered rows of the pixel array section 10 are electrically connected to the vertical signal line VSL in order, and the values of SEL_L and SEL_R are controlled to alternately differ from each other. Differences between red pixels and green pixels between odd-numbered rows in the upper left or upper right basic unit G10 can be calculated.
  • the pixels in the even rows of the pixel array section 10 are electrically connected to the vertical signal line VSL in order, and the values of SEL_L and SEL_R are alternately controlled so that each pixel in the basic unit G10 is Differences between green pixels and blue pixels between even-numbered rows in the upper left or upper right basic unit G10 can be calculated.
  • the electronic device according to the fourth embodiment differs from the electronic device according to the first embodiment in that the FD is shared by the basic pixel unit G10 of 2 pixels horizontally and 2 pixels vertically. Differences from the electronic device according to the first embodiment will be described below.
  • FIG. 37 is a diagram showing an example of differential processing by the first control method in the pixel array section 10 according to the fourth embodiment.
  • the difference processing according to this embodiment it is possible to perform difference processing between basic pixel groups G10 in the Bayer array.
  • One shared FD is arranged in the basic pixel group G10. Therefore, in the differential processing by the first control method, the accumulated charges of 2 ⁇ 2 pixels in the basic pixel group G10 are added by the FD to perform the differential processing.
  • the difference information generation process is performed between the basic pixel group G10. As a result, difference information is generated between the basic pixel group G10 in the left and right oblique directions.
  • FIG. 38 is a diagram showing an example of differential processing by the second control method in the pixel array section 10 according to the fourth embodiment.
  • the second control method performs difference processing for each color component. For example, it is assumed that only the accumulated charges of the red pixels are transferred to the FD, and the difference information generation processing is performed between the basic pixel group G10. As a result, difference information of red pixels is generated between the basic pixel group G10 in the left and right oblique directions. By repeating the same process as for the red pixel for the green pixel and the blue pixel, difference information for each of the green pixel and the blue pixel is generated between the basic pixel group G10 in the left and right oblique directions. In the second control method, it is also possible to add two green pixels and perform difference processing. This makes it possible to shorten the time required for difference processing.
  • FIG. 39 is a diagram showing an example of circuits of the pixel array section 10, the first selection section 12c, the first AD conversion section 14c, the second selection section 16c, and the second AD conversion section 18c according to the fourth embodiment.
  • the number of pixels is described as 8 ⁇ 8 or 10 ⁇ 8 for the sake of simplicity, the number is not limited to this.
  • the first selector 12c has selectors SEL11 to SEL14.
  • the first selection unit 12c selects (((n ⁇ 1) ⁇ 2+m), ((n ⁇ 1) ⁇ 2+m+1)) (n is 1 to M/ 2, m selects one of a combination of two adjacent signal lines from 1 to 2), and outputs the signal of the selected signal line to the first AD converter 14c.
  • VSL vertical signals
  • the first selection unit 12c selects the ((n ⁇ 1) ⁇ 2+m)-th vertical signal line VSL with the selector control signal (left) (SEL_L) being a “0” selection signal. Select if Also, the ((n ⁇ 1) ⁇ 2+m+1)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal. When generating a differential image in this manner, the first selection unit 12c alternately selects adjacent vertical signals (VSL).
  • the first AD converter 14c has AD converters ADC11-14.
  • AD converters ADC11-14 are connected to corresponding selectors SEL11-14, respectively.
  • the second selection unit 16c has selection units SEL21 to SEL24.
  • the first selection unit 12c selects (((n ⁇ 1) ⁇ 2+m+1), ((n ⁇ 1) ⁇ 4+m+2))) (n is 1 to M) among the plurality of vertical signals (VSL) of the pixel array unit 10. /4, where m is 1 to 2), one of the combinations of two adjacent signal lines is selected, and the signal of the selected signal line is output to the second AD converter 18c.
  • the second selection unit 16c selects the ((n ⁇ 1) ⁇ 2+m+1)-th vertical signal line VSL so that the selector control signal (right) (SEL_R) is a “0” selection signal. Select if Also, the ((n ⁇ 1) ⁇ 4+m+2)))th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • the first selection unit 16b alternately selects adjacent vertical signals (VSL).
  • the second AD converter 18c has AD converters ADC21-24.
  • AD converters ADC21-24 are connected to corresponding selectors SEL21-24, respectively.
  • the circuit structure is divided into two groups of the first selection unit 12c and the first AD conversion unit 14c and the second selection unit 16c and the second AD conversion unit 18c. do.
  • the FD is shared by the basic pixel group G10 composed of 2 horizontal pixels by 2 vertical pixels.
  • the basic pixel group G10 composed of 2 horizontal pixels by 2 vertical pixels.
  • the number of vertical signal lines (VSL) used for reading is also reduced, the number of AD converters is also reduced and the size of the circuit can be reduced.
  • the number of pixels that can be AD-converted at one time decreases, and the frame rate decreases.
  • the selection section SEL is provided between the adjacent vertical signal lines VSL in order to acquire the oblique difference. These are divided into two groups to control the direction of the selection portion SEL.
  • the image control unit 8 selects the control line 1 (control wires 1) and deselects the control lines 2 to (control wires 2 to).
  • the basic pixel group of the first row is connected to the vertical signal line VSL.
  • the arrangement of the basic pixel group G10 in the row direction is called one row, and the arrangement in the column direction is called one column. Therefore, the control line 1 controls a plurality of basic pixel groups G10 arranged in one row.
  • the data of the basic pixel group G10 electrically connected to VSL1 is input to the AD converter ADC11.
  • pixel data electrically connected to VSL3 are input to AD converters ADC12, 21.
  • Pixel data of the basic pixel group G10 in the row of the control wire 1 (control wires 1) is input to other AD converters in a similar procedure.
  • auto zero (AZ) to the AD converters ADC11 to 14 and 21 to 24
  • the level of the signal voltage output by the basic pixel group G10 is set to the reference value of each ADC, that is, the value of 0. .
  • the image control unit 8 selects the control line 2 and deselects the control lines 1, 3 to 5. Thereby, the pixel data in the basic pixel group G10 in the row of the control line 2 is electrically connected to each VSL (vertical signal line).
  • AD converters ADC11-14 and 21-24 perform AD conversion in this state.
  • the ADC 11 and ADC 12 can acquire the difference from the upper right corner in units of 2 ⁇ 2 pixels
  • the ADC 21 can acquire the difference from the upper left corner in units of 2 ⁇ 2 pixels.
  • FIG. 40 is a diagram showing a circuit configuration example of the basic pixel group G10 of the Bayer array according to the fourth embodiment.
  • the basic pixel group G10 includes a plurality of pixels PX11, 12, 21, 22, a reset transistor SW2, an amplification transistor AMP, a selection transistor SW3, and a floating diffusion FD.
  • Pixel PX11 is a red pixel
  • pixels PX12 and PX21 are green pixels
  • pixel PX22 is a blue pixel.
  • the basic operations of the reset transistor SW2, the amplification transistor AMP, the selection transistor SW3, and the floating diffusion FD are the same as the circuit configuration of the basic pixel group G10 according to the first embodiment, so description thereof will be omitted.
  • Each of the pixels PX11, 12, 21 and 22 has photodiodes PD1 to PD4 and transfer transistors SW1_1, 1_2, 1_3 and 1_4.
  • Sources of the transfer transistors SW1_1, 1_2, 1_3, and 1_4 are connected to the floating diffusion FD, and drains are connected to the photodiodes PD1 to PD4, respectively.
  • Gates of transfer transistors SW1_1, 1_2, 1_3, and 1_4 are connected to control lines Trg1_1, 1_2, 1_3, and 1_4.
  • control wires 1 is configured as a bundle of control lines Trg1_1, 1_2, 1_3, 1_4, SEL1, and RST1.
  • a high level signal is applied to the gate of any one of the transfer transistors SW1_1, 1_2, 1_3 and 1_4 via one of the control lines Trg1_1, 1_2, 1_3 and 1_4.
  • a high level signal is applied to the gate of any one of the transfer transistors SW1_1, 1_2, 1_3 and 1_4 via one of the control lines Trg1_1, 1_2, 1_3 and 1_4.
  • a high level signal is applied to the gate of the transfer transistor SW1_1 via the control line Trg1_1. This makes it possible to transfer only the accumulated charge in the photodiode PD1 to the floating diffusion FD. Other pixels can similarly transfer only the accumulated charge to the floating diffusion FD.
  • FIG. 41 is a time chart showing an example of differential processing from time t10 to t21 according to the fourth embodiment
  • FIG. 42 is a time chart including an example of differential processing from time t22 to t24 according to the fourth embodiment
  • FIG. 43 is a time chart including an example of difference processing for the last line according to the fourth embodiment.
  • the signals RST1 and SEL_R first go high at time t10.
  • the reset transistor SW2 of the basic pixel group G10 on the first row is turned on when the high-level reset signal RST1 is input to the gate through the signal line Rst1, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST1 becomes low level, and the set transistor SW2 is disconnected. Then, the signals TRG1_1 to 1_4 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 to PD4 of the pixels in the basic pixel group G10 are respectively transferred to the floating diffusion FD and added.
  • signal charges here, photoelectrons
  • the signal SEL1 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. Thereby, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, and the AD converters ADC12 and 21 are connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 to a reference value (zero value). set.
  • the AZ circuit saves this offset amount.
  • the signals RST2 and SEL_R go low, and SEL_L goes high.
  • the reset transistor SW2 of the basic pixel group G10 on the second row is turned on when the high-level reset signal RST2 is input to the gate through the signal line Rst2, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST2 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG4 becomes high level. Then, the signals TRG1_1 to 1_4 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 to PD4 of the pixels in the basic pixel group G10 are respectively transferred to the floating diffusion FD and added.
  • signal charges here, photoelectrons
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. Thereby, the AD converters ADC11 and 21 are electrically connected to the vertical signal line VSL2, and the AD converter ADC12 is electrically connected to the vertical signal line VSL4. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t15 and t16.
  • the AD converters ADC11-14, 21-24 perform AD conversion and output data of the difference between the basic pixel groups G10 on the first and second rows.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the second row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST3 and SEL_R become high level, and SEL_L becomes low level.
  • the reset transistor SW2 of the basic pixel group G10 on the third row is turned on when the high-level reset signal RST3 is input to the gate through the signal line Rst3, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST3 becomes low level, and the set transistor SW2 is disconnected.
  • the signals TRG3_1 to TRG3_4 become high level.
  • the signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 to PD4 of the basic pixel group G10 on the third row are transferred to the floating diffusion FD and added.
  • the signal SEL3 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. As a result, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, the AD converter ADC12 is electrically connected to the vertical signal line VSL3, and the data of each basic pixel group G10 is input to each AD converter. be. Also, since SEL_R is at high level, the AD converter ADC21 is electrically connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t19 and t20.
  • the AD converters ADC11-14, 21-24 perform AD conversion and output data of the difference between the basic pixel group G10 of the second and third rows.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the third row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signal RST4 becomes low level, and the reset transistor SW2 is disconnected. Then, the signals TRG4_1 to TRG4_4 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 to PD4 of the basic pixel group G10 on the fourth row are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • the signal SEL4 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level. As a result, the AD converters ADC11 and 21 are electrically connected to the vertical signal line VSL2, and the AD converter ADC12 is electrically connected to the vertical signal line VSL4. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t23 and t24.
  • the AD converters ADC11 to ADC14, 21 to 24 perform AD conversion and output data of differences between the basic pixel groups G10 on the third and fourth rows. In this way, since the difference in brightness information is extracted by adding four pixels, it is possible to obtain a difference image in 1/4 the time and 1/4 the power consumption of normal image output.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the fourth row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST5 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the basic pixel group G10 on the fifth row is turned on when the high-level reset signal RST3 is input to the gate through the signal line Rst3, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST3 becomes low level, and the set transistor SW2 is disconnected. Then, the signals TRG5_1 to 5_4 become high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 to PD4 of the basic pixel group G10 on the fifth row are transferred to the floating diffusion FD and added.
  • signal charges here, photoelectrons
  • the signal SEL5 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. As a result, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, the AD converter ADC12 is electrically connected to the vertical signal line VSL3, and the data of each basic pixel group G10 is input to each AD converter. be. Also, since SEL_R is at high level, the AD converter ADC21 is electrically connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t27 and t28.
  • the AD converters ADC11-14, 21-24 perform AD conversion and output data of the difference between the basic pixel group G10 in the fourth and fifth rows.
  • the signal SEL5 is set to low level to end the AD conversion.
  • FIG. 44 is a time chart showing an example of differential processing from time t10 to t21 relating to the second control
  • FIG. 45 is a time chart including an example of differential processing from time t22 to t24 relating to the second control
  • FIG. 46 is a time chart including an example of difference processing for the last line according to the second control.
  • the second control example corresponds to the color of the first control example.
  • the circuit configuration is the same as that of the first control example, but the control method is different.
  • the signals RST1 and SEL_R first go high at time t10.
  • the reset transistor SW2 of the basic pixel group G10 on the first row is turned on when the high-level reset signal RST1 is input to the gate through the signal line Rst1, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST1 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG1_1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 (corresponding to red pixels) of the pixels in the basic pixel group G10 are transferred to the floating diffusion FD and added.
  • signal charges here, photoelectrons
  • the signal SEL1 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. Thereby, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, and the AD converters ADC12 and 21 are connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 to a reference value (zero value). set.
  • the AZ circuit saves this offset amount.
  • the signals RST2 and SEL_R go low, and SEL_L goes high.
  • the reset transistor SW2 of the basic pixel group G10 on the second row is turned on when the high-level reset signal RST2 is input to the gate through the signal line Rst2, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST2 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG1_1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 of the pixels in the basic pixel group G10 are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • the signal SEL2 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. Thereby, the AD converters ADC11 and 21 are electrically connected to the vertical signal line VSL2, and the AD converter ADC12 is electrically connected to the vertical signal line VSL4. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t15 and t16.
  • the AD converters ADC11 to ADC14, 21 to 24 perform AD conversion and output data of differences between the red pixels of the basic pixel group G10 on the first and second rows.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the second row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST3 and SEL_R become high level, and SEL_L becomes low level.
  • the reset transistor SW2 of the basic pixel group G10 on the third row is turned on when the high-level reset signal RST3 is input to the gate through the signal line Rst3, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST3 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG3_1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 of the basic pixel group G10 on the third row are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • the signal SEL3 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. As a result, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, the AD converter ADC12 is electrically connected to the vertical signal line VSL3, and the data of each basic pixel group G10 is input to each AD converter. be. Also, since SEL_R is at high level, the AD converter ADC21 is electrically connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t19 and t20. In this way, the AD converters ADC11-14, 21-24 perform AD conversion and output data of differences between red pixels in the basic pixel group G10 on the second and third rows.
  • the AZ units 40 and 42 of the AD converters ADC11-14 and 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the third row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signal RST4 becomes low level, and the reset transistor SW2 is disconnected. Then, the signal TRG4_1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 of the basic pixel group G10 on the fourth row are transferred to the floating diffusion FD.
  • the signal SEL4 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at high level and SEL_R is at low level. As a result, the AD converters ADC11 and 21 are electrically connected to the vertical signal line VSL2, and the AD converter ADC12 is electrically connected to the vertical signal line VSL4. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t23 and t24.
  • the AD converters ADC11-14, 21-24 perform AD conversion and output data of differences between the red pixels of the basic pixel group G10 on the third and fourth rows. In this way, since the difference in brightness information is extracted by adding four pixels, it is possible to obtain a difference image in 1/4 the time and 1/4 the power consumption of normal image output.
  • the AZ units 40, 42 of the AD converters ADC11-14, 21-24 execute AZ (auto zero) to set the output signal of the basic pixel group G10 on the fourth row to the reference value (zero value). Henceforth, the AZ circuit saves this offset amount.
  • the signals RST5 and SEL_R go high, and SEL_L goes low.
  • the reset transistor SW2 of the basic pixel group G10 on the fifth row is turned on when the high-level reset signal RST3 is input to the gate through the signal line Rst3, and resets the floating diffusion FD to the voltage of the constant voltage source VSS. .
  • the signal RST5 becomes low level, and the set transistor SW2 is disconnected. Then, the signal TRG5_1 becomes high level. As a result, signal charges (here, photoelectrons) accumulated by photoelectric conversion of the photodiodes PD1 of the basic pixel group G10 on the fifth row are transferred to the floating diffusion FD.
  • signal charges here, photoelectrons
  • the signal SEL5 becomes high level. Accordingly, when the selection transistor SW3 is turned on, the amplification transistor AMP amplifies the voltage of the floating diffusion FD and outputs it to the vertical signal line VSL. In the amplified potential of the floating diffusion FD at this time, SEL_L is at low level and SEL_R is at high level. As a result, the AD converter ADC11 is electrically connected to the vertical signal line VSL1, the AD converter ADC12 is electrically connected to the vertical signal line VSL3, and the data of each basic pixel group G10 is input to each AD converter. be. Also, since SEL_R is at high level, the AD converter ADC21 is electrically connected to the vertical signal line VSL3. Other AD converters are electrically connected to the vertical signal line VSL according to the same rule.
  • the AD converters ADC11-14, 21-24 perform AD conversion between times t27 and t28.
  • the AD converters ADC11-14, 21-24 perform AD conversion and output data of differences between red pixels in the basic pixel group G10 on the fourth and fifth rows.
  • the signal SEL5 is set to low level to end the AD conversion.
  • Difference processing between blue pixels can be performed by moving TRG*_4 instead of TRG*_1 of the signal shown in the timing chart of the second control example.
  • TRG*_4 instead of TRG*_1 of the signal shown in the timing chart of the second control example.
  • two pixels, TRG*_2 and TRG*_3 are moved at the same time instead of TRG*_1, thereby adding two pixels and acquiring the difference.
  • the sensitivity is doubled compared to the acquisition of green pixels individually, and an image can be acquired in one time.
  • Such a driving method is useful when taking a color difference image.
  • the FD is shared by the basic pixel unit G10 consisting of two horizontal pixels and two vertical pixels.
  • the first selection unit 12c selects the ((n ⁇ 1) ⁇ 2+m)-th vertical signal line VSL when the selector control signal (left) (SEL_L) is a “0” selection signal.
  • the ((n ⁇ 1) ⁇ 2+m+1)th vertical signal line VSL is selected when the selector control signal (left) (SEL_L) is a “1” selection signal.
  • the second selection unit 16c selects the ((n ⁇ 1) ⁇ 2+m+1)-th vertical signal line VSL when the selector control signal (right) (SEL_R) is a “0” selection signal. do.
  • the ((n ⁇ 1) ⁇ 4+m+2)))th vertical signal line VSL is selected when the selector control signal (right) (SEL_R) is a “1” selection signal.
  • SEL_R selector control signal
  • the pixels in every four rows of the pixel array section 10 are electrically connected to the vertical signal line VSL in order, and the values of SEL_L and SEL_R are controlled so as to alternately differ from each other. It is possible to calculate the difference between the added value and the added value of each pixel in the basic unit G10 on the upper left or on the upper right.
  • pixels in a predetermined row out of the four rows of the pixel array section 10 are electrically connected to the vertical signal line VSL in order, and the values of SEL_L and SEL_R are alternately controlled to change the basic unit G10. , and the difference between each pixel in the upper left or upper right basic unit G10 can be calculated.
  • This technology can be configured as follows.
  • the solid-state imaging device wherein the first analog-digital conversion section and the second analog-digital conversion section are arranged on the same end side of the pixel array section.
  • the solid-state imaging device includes a plurality of analog-to-digital conversion circuits corresponding to a plurality of switch circuits included in the second selection circuit, including the third analog-to-digital conversion circuit.
  • each of the plurality of switch circuits included in the first selection unit is connected to two of the plurality of vertical signal lines in a predetermined order according to the arrangement order; each of the plurality of switch circuits included in the second selection unit is connected to two of the plurality of vertical signal lines in a predetermined order according to the arrangement order;
  • the left one of the two vertical signal lines is the right vertical signal line of the two vertical signal lines in any one of the plurality of switch circuits included in the first selection circuit.
  • the right one of the two vertical signal lines is the left vertical signal line of the two vertical signal lines in any one of the plurality of switch circuits included in the first selection circuit.
  • Each of the plurality of switch circuits included in the first selection unit has (2n ⁇ 1) ((n is 1 to M/2, M is an even number) vertical signal line from the left, and (2n) connected to two vertical signal lines and Each of the plurality of switch circuits included in the second selection unit is connected to two of the (2n)-th vertical signal line and the (2n+1)-th vertical signal line from the left according to the arrangement order, (5 ).
  • Each of the plurality of switch circuits of the first selection unit is ((n ⁇ 1) ⁇ 4+m) (n is 1 to M/4, M is a multiple of 4, m is 1 to 2) connected to two of the th vertical signal line and the ((n ⁇ 1) ⁇ 4+m+2) th vertical signal line,
  • Each of the plurality of switch circuits included in the second selection section has two switches, the ((n ⁇ 1) ⁇ 4+m+2)-th vertical signal line from the left and the (n ⁇ 4+m)-th vertical signal line, according to the arrangement order.
  • the solid-state imaging device according to (5) which is connected to a book.
  • each of the switch circuits included in the first selection unit alternately selects the left vertical signal line and the right vertical signal line of the two vertical signal lines
  • each of the switch circuits included in the first selection unit selects one of the left vertical signal line and the right vertical signal line of the two vertical signal lines,
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels in the first row when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit;
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, When the left vertical signal line of the two signal lines of the switch circuit of the first selection unit is selected, the pixels of the first row and the second row different from the first row are electrically connected. death, When the right vertical signal line of the two signal lines is selected, a third row different from the first row and the second row, and a third row different from the first row, the second row, and the third row.
  • the solid-state imaging device according to (5), wherein the pixels in the fourth row are electrically connected.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels in the first row when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit; electrically connecting the pixels of the first row and the third row separated by one row when the right vertical signal line of the two signal lines is selected; next, electrically connecting the pixels in the second row adjacent to the first row when selecting the left vertical signal line of the two signal lines;
  • the method according to (5) wherein when the right vertical signal line of the two signal lines is selected, the second row and the fourth row spaced apart by one row are electrically connected to each other.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, electrically connecting the pixels of the first to fourth rows when selecting the left vertical signal line of the two signal lines of the switch circuit of the first selection unit;
  • the solid-state imaging device according to (5) wherein when the right vertical signal line of the two signal lines is selected, the pixels in the fifth to eighth rows, which are different from the first to fourth rows, are electrically connected. element.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix, When the left vertical signal line of the two signal lines of the switch circuit of the first selection unit is selected, the pixels of a predetermined one row among the first to fourth rows are electrically connected. , When selecting the vertical signal line on the right side of the two signal lines, electrically connecting the pixels of a predetermined row out of the fifth to eighth rows different from the first to fourth rows, ( 5) The solid-state imaging device according to the above.
  • the pixel array unit is composed of a plurality of pixels arranged in a matrix,
  • the pixels are a photoelectric conversion element unit that generates a current corresponding to the amount of received light by photoelectric conversion; a transfer transistor having a drain connected to the cathode of the photoelectric conversion element; a reset transistor having a source connected to the source of the transfer transistor; an amplification transistor having a gate connected to the source of the transfer transistor; a floating diffusion connected to the gate of the amplification transistor; A selection transistor having a drain connected to the amplification transistor source and a source connected to one of the first to fourth vertical signal lines.
  • the pixel array section has pixels in a Bayer array,
  • 1 optical system
  • 2 image sensor (solid-state imaging device)
  • 12, 12a, 12b, 12c first selection section
  • 14, 14a, 14b, 14c first AD conversion section
  • 16, 16a, 16b, 16c first 2 selection unit
  • 18, 18a, 18b, 18c second AD conversion unit
  • 100 electronic device
  • AMP amplification transistor
  • FD floating diffusion
  • PD photodiode (photoelectric conversion element section)
  • SEL11 to 18, 21 to 28 selector (switch circuit)
  • SW1 transfer transistor
  • SW2 reset transistor
  • SW3 selection transistor
  • VSL vertical signal line.

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  • Transforming Light Signals Into Electric Signals (AREA)
PCT/JP2022/046904 2022-01-05 2022-12-20 固体撮像素子、及び電子機器 Ceased WO2023132232A1 (ja)

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CN202280087024.8A CN118476239A (zh) 2022-01-05 2022-12-20 固态成像元件和电子设备
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