WO2023130803A1 - 一种背接触式硅异质结太阳能电池及其制备方法 - Google Patents

一种背接触式硅异质结太阳能电池及其制备方法 Download PDF

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WO2023130803A1
WO2023130803A1 PCT/CN2022/126485 CN2022126485W WO2023130803A1 WO 2023130803 A1 WO2023130803 A1 WO 2023130803A1 CN 2022126485 W CN2022126485 W CN 2022126485W WO 2023130803 A1 WO2023130803 A1 WO 2023130803A1
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layer
electrode
region
doped layer
doped
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PCT/CN2022/126485
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French (fr)
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蔡永安
王志强
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隆基绿能科技股份有限公司
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Definitions

  • the invention relates to the technical field of solar cell manufacturing, in particular to a back-contact silicon heterojunction solar cell and a preparation method thereof.
  • Back-contact silicon heterojunction solar cells not only have the characteristics of high opening voltage and high fill factor of heterojunction solar cells, but also have the advantages of less shading and high current of back-contact solar cells. At present, 26.7% of the laboratory Photoelectric conversion efficiency is one of the technical routes of high concern for commercial solar cells in the future.
  • the back-contact silicon heterojunction solar cell has an N region and a P region on the backlight surface.
  • N region and the P region In the preparation process of the N region and the P region, it usually requires multiple photolithography processes, multiple mask processes, and multiple wet chemical etching processes. Multiple processes, such as multiple cleaning processes, are alternately performed to realize the isolation of the N area and the P area on the backlight surface of the battery, and the process is very complicated.
  • the object of the present invention is to provide a back-contact silicon heterojunction solar cell and a preparation method thereof, so as to simplify the process.
  • the present invention provides the following technical solutions:
  • the present invention provides a method for preparing a back-contact silicon heterojunction solar cell, comprising: providing a substrate, the first surface of the substrate has a first region, a second region and an isolation region, and the isolation region separates the first a first region and a second region; a first mask is fixed on the substrate, and the first mask covers the second region and the isolation region, so that the first region is exposed; the stacked first doped layer and the first doped layer are sequentially formed in the first region Electrode; peel off the first mask; fix the second mask on the exposed surface of the first electrode, the second mask covers the first electrode and the isolation region, so that the second region is exposed; in the second region, a stack of second doped The impurity layer and the second electrode, the conductivity types of the first doped layer and the second doped layer are different; peeling off the second mask, wherein both the first mask and the second mask are polymer tapes.
  • the second region and the isolation region are covered by the first mask, and the first doped layer and the first doped layer are continuously completed on the first region not covered.
  • the fabrication of the electrode is to complete the fabrication of a doped conductive region, such as one of the P region and the N region; after that, the first mask is peeled off to expose the second region and the isolation region, and then the second region is covered by the second mask.
  • the isolation region and the first doped layer and the first electrode that have been fabricated on the first region are continuously completed on the second region that is not covered, and the second doped layer and the second electrode are completed, and another The production of a doped conductive region, such as the other of the P region and the N region.
  • the second mask is peeled off, at this time, no film layer is formed on the isolation region, and the natural isolation of the two doped conductive regions is realized.
  • the isolation of the P region and the N region can be naturally formed during the process of manufacturing the first doped layer, the first electrode, the second doped layer, and the second electrode, without the need for a separate wet chemical etching process Or a laser etching process separates the P region from the N region.
  • the preparation of the N area can be completed in a separate process, which is more independent in process, and the process adopted is simpler.
  • each film layer in the P area and N area can be controlled independently, independently designed, and the preparation flexibility is higher, and the parameters of each film layer can be conveniently adjusted according to the demand.
  • a step is further included: forming a first transparent conductive layer on the first doped layer; and/or, After forming the second doped layer in the second region and before forming the second electrode, a step is further included: forming a second transparent conductive layer on the second doped layer.
  • the first electrode and the first doped layer are electrically connected through the first transparent conductive layer
  • the second electrode and the second doped layer are electrically connected through the second transparent conductive layer. Due to the low mobility of electrons and holes in the doped layer and poor lateral conductivity, it is not conducive to the collection of photogenerated carriers. Therefore, the carrier is collected vertically through the transparent conductive layer and transported to the electrode, which can improve the collection and transmission efficiency of photogenerated carriers, and the contact between the electrode and the transparent conductive layer is easier to achieve ohmic contact than the contact between the electrode and the doped layer, thereby Carrier loss can be reduced.
  • the transparent conductive layer can reduce optical reflection and increase the incident rate of solar light.
  • the first doped layer, the first electrode, the second doped layer, the second electrode, the first transparent conductive layer and a second transparent conductive layer are possible implementations.
  • the first doped layer and the second doped layer are deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD for short);
  • CVD chemical Vapor Deposition
  • the first transparent conductive layer, the second transparent conductive layer, the first electrode and the second electrode are low-temperature deposition methods, and the process difficulty is relatively low, and the mask in this application can withstand the required temperature.
  • the first doped layer and the second doped layer are doped amorphous silicon layers or doped microcrystalline silicon layers, and the thickness of the first doped layer and the second doped layer is 2nm- 50nm; and/or, the first transparent conductive layer and the second transparent conductive layer are tin-doped indium oxide layer, tungsten-doped indium oxide layer, aluminum-doped zinc oxide layer or gallium-doped zinc oxide layer, the first transparent conductive layer and the second The thickness of the transparent conductive layer is 40nm-200nm; and/or, the material of the first electrode and the second electrode is one or more combinations of silver, nickel, aluminum, tin, copper, the first electrode and the second electrode The thickness is 3 ⁇ m to 30 ⁇ m.
  • the material and thickness of each film layer are selected according to the process and function requirements.
  • the thicknesses of the first doped layer and the second doped layer are the same or different; the thicknesses of the first transparent conductive layer and the second transparent conductive layer are the same or different; the thicknesses of the first electrode and the second electrode same or different thickness.
  • the first doped layer, the first transparent conductive layer and the first electrode formed on the first region are completed in a single process
  • the second formed on the second region The doped layer, the second transparent conductive layer and the second electrode are completed in another separate process, and the processing of the film layers in the first region and the second region is independent of each other, so it can be independently processed according to the process and function requirements. Adjusting the thickness of each film layer in the first area and the second area can correspond to the same or different, and the process is more flexible.
  • a step is further included: forming a first passivation layer on the first surface of the substrate.
  • the interface defects of the substrate are reduced through the first passivation layer, thereby reducing the recombination of carriers caused by the defects, and improving the photoelectric conversion efficiency.
  • the first passivation layer is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer.
  • the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer Through the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer, the dangling bonds can be effectively hydrogenated and surface defects can be reduced, thereby significantly improving the minority carrier lifetime, increasing the open circuit voltage, and finally improving the photoelectric conversion efficiency.
  • both the first mask and the second mask have a base film and an adhesive layer
  • the material of the base film is extended polypropylene, uniaxially stretched polypropylene, biaxially stretched polypropylene, polyethylene, One or more combinations of polyester fiber, polyvinyl chloride, polyethylene terephthalate, polyolefin, polyimide
  • the material of the adhesive layer is water glue, oil glue, hot melt glue, natural rubber , synthetic rubber, silica gel, acrylic glue, polyisobutylene, and one or more combinations of polyurethane
  • the thickness of the first mask and the second mask is 2 ⁇ m-40 ⁇ m.
  • the base film and the adhesive layer are made of materials with low cost, and the material of the base film has high impact resistance, strong mechanical properties, resistance to various organic solvents and acid and alkali corrosion, and meets the requirements of Mask use requirements are met.
  • the mask has a certain supporting strength and the function of easy separation, can be pasted and fixed on the film layer, can withstand the low temperature deposition process, and the mask is not cut when the laser is patterned, when placing the mask, due to the mask has A certain degree of hardness facilitates precise positioning of mask patterns and film layers.
  • the peeling of the first mask and the second mask adopts one or more combinations of pyrolytic separation, ultraviolet light irradiation separation, and mechanical separation. Choose the appropriate stripping method according to the different adhesive layers of the mask.
  • the present invention also provides a back-contact silicon heterojunction solar cell, which is prepared by the preparation method described in any one of the above. Since the back-contact silicon heterojunction solar cell is obtained by the preparation method in the present application, it has the same technical effect as the preparation method, and will not be repeated here.
  • the present invention also provides a back-contact silicon heterojunction solar cell, comprising: a substrate, the first surface of the substrate has a first region, a second region and an isolation region, and the first region and the second region are separated by the isolation region.
  • Two areas the first doped layer located in the first area; the first electrode located on the surface of the first doped layer, the projection of the first electrode on the first surface coincides with the projection of the first doped layer on the first surface;
  • the conductivity types of the first doped layer and the second doped layer are different; the second electrode located on the surface of the second doped layer, the projection of the second electrode on the first surface is the same as that of the second doped layer.
  • the projections of the doped layer on the first surface coincide.
  • the first doped layer and the first electrode stacked on the first region are isolated from the second doped layer and the second electrode stacked on the second region by the isolation region, and the first The projections of the doped layer and the first electrode on the first surface coincide, and the projections of the second doped layer and the second electrode on the first surface coincide, that is, the electrode completely covers the surface of the doped layer, and the width of the electrode and the doped layer Equal, compared with the existing electrode formed by screen printing, the width of the electrode is smaller than the doped layer, the width of the electrode in this application is larger, which increases the vertical transmission of carriers to the area of the electrode, and the photoelectric conversion efficiency higher.
  • the back-contact silicon heterojunction solar cell further includes a first passivation layer located on the first surface of the substrate; the first doped layer and the second doped layer are located away from the first passivation layer the surface of the substrate.
  • the interface defects of the substrate are reduced through the passivation layer, thereby reducing the recombination of carriers caused by the defects, and improving the photoelectric conversion efficiency.
  • the first passivation layer is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer.
  • the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer Through the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer, the dangling bonds can be effectively hydrogenated and surface defects can be reduced, thereby significantly improving the minority carrier lifetime, increasing the open circuit voltage, and finally improving the photoelectric conversion efficiency.
  • the back-contact silicon heterojunction solar cell further includes: a first transparent conductive layer located between the first doped layer and the first electrode, and the projection of the first transparent conductive layer on the first surface It coincides with the projection of the first doped layer on the first surface; and/or, the second transparent conductive layer located between the second doped layer and the second electrode, the projection of the second transparent conductive layer on the first surface is the same as that of the first transparent conductive layer. The projections of the two doped layers on the first surface coincide.
  • the first electrode and the first doped layer are electrically connected through the first transparent conductive layer
  • the second electrode and the second doped layer are electrically connected through the second transparent conductive layer. Due to the low mobility of electrons and holes in the doped layer and poor lateral conductivity, it is not conducive to the collection of photogenerated carriers. Therefore, carriers are collected vertically through the transparent conductive layer and transported to the electrode.
  • the transparent conductive layer can reduce optical reflection at the same time, and the contact between the electrode and the transparent conductive layer is easier to achieve ohmic contact than the contact between the electrode and the doped layer, thereby improving the conductivity. efficiency.
  • the thicknesses of the first doped layer and the second doped layer are the same or different; the thicknesses of the first transparent conductive layer and the second transparent conductive layer are the same or different; the thicknesses of the first electrode and the second electrode same or different thickness.
  • the first doped layer, the first transparent conductive layer and the first electrode formed on the first region and the second doped layer and the second transparent conductive layer formed on the second region It is independent from the second electrode, and the thickness and parameters of each film layer in the first region and the second region can be independently adjusted according to the process and functional requirements.
  • the back-contact silicon heterojunction solar cell further includes: a second passivation layer located on the second surface of the substrate, the second surface is set opposite to the first surface; Surface anti-reflection layer.
  • the second surface of the substrate has better passivation effect and anti-reflection effect.
  • 1-6 are schematic diagrams of the manufacturing process of a back-contact silicon heterojunction solar cell provided by an embodiment of the present invention.
  • FIGS. 7-12 are schematic diagrams of the manufacturing process of another back-contact silicon heterojunction solar cell provided by the embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a back-contact silicon heterojunction solar cell provided by an embodiment of the present invention.
  • Reference numerals 100-substrate, 101-first region, 102-second region, 103-isolation region, 201-first passivation layer, 202-second passivation layer, 301-first doped layer, 302 -Second doped layer, 401-first transparent conductive layer, 402-second transparent conductive layer, 501-first electrode, 502-second electrode, 600-anti-reflection layer, 700-first mask, 800- second mask.
  • the back-contact silicon heterojunction solar cell has an N region and a P region on the backlight surface.
  • N region and the P region In the preparation process of the N region and the P region, it usually requires multiple photolithography processes, multiple mask processes, and multiple wet chemical etching processes. Multiple processes, such as multiple cleaning processes, are alternately performed to realize the isolation of the N area and the P area on the backlight surface of the battery, and the process is very complicated.
  • an embodiment of the present invention provides a method for preparing a back-contact silicon heterojunction solar cell, which includes the following steps:
  • a substrate 100 is provided.
  • the substrate 100 has a first surface and a second surface opposite to each other.
  • the first surface is the backlight surface of the substrate 100
  • the second surface is the light incident surface of the substrate 100 .
  • the substrate 100 can be an n-type crystalline silicon wafer or a p-type crystalline silicon wafer.
  • the first surface and the second surface of the substrate 100 may also have functional structures such as a passivation layer.
  • the first surface has a first region 101, a second region 102 and an isolation region 103, the first region 101 and the second region 102 are separated by the isolation region 103, wherein the first region 101 and the second region 102 are respectively used to Forming film layers of different conductivity types, such as forming P regions and N regions, if the first region 101 is used to form the P region, then the second region 102 is used to form the N region, or if the first region 101 is used to form the N region, Then the second region 102 is used to form the P region, and the isolation region 103 is used to isolate the N region and the P region to realize insulation.
  • different conductivity types such as forming P regions and N regions
  • a first mask 700 is fixed on the first surface of the substrate 100 , the first mask 700 covers the second region 102 and the isolation region 103 , so that the first region 101 is exposed.
  • the first mask 700 serves to only cover the second region 102 and the isolation region 103 .
  • the first mask 700 is a polymer adhesive tape, which can be pasted and fixed on the first surface, and can be peeled off from the first surface later.
  • step S300 as shown in FIG. 2 , the stacked first doped layer 301 and the first electrode 501 are successively formed on the exposed surface of the first region 101, that is, the first doped layer is only formed on the surface of the first region 101 first. 301, and then form a first electrode 501 on the exposed surface of the first doped layer 301.
  • the first region 101 is an N region
  • the first doped layer 301 is an N-type doped layer, specifically an N-type doped amorphous silicon layer or an N-type doped microcrystalline silicon layer.
  • the first doped layer 301 is a P-type doped layer, specifically a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.
  • the thickness of the first doped layer 301 is 2nm-50nm, preferably 5nm-10nm, specifically 5nm, 6nm, 7nm, 8nm, 9nm, 10nm or the like.
  • the material of the first electrode 501 can be one or more combinations of silver, nickel, aluminum, tin and copper, and the thickness of the first electrode 501 is 3 ⁇ m to 30 ⁇ m, specifically 3 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, etc.
  • step S400 as shown in FIG. 3 , the first mask 700 is peeled off. Because in the process of forming the first doped layer 301 and the first electrode 501 in step S200, the corresponding film layer will also be formed on the first mask 700, therefore, after the first mask 700 is peeled off, it is deposited on the first The materials on the surface of the mask 700 are stripped off together, leaving only the film layer on the first region 101 to form the first doped layer 301 and the first electrode 501. At this time, the second region 102 and the isolation region 103 are exposed again.
  • a second mask 800 is fixed on the exposed surface of the first electrode 501, and the second mask 800 covers the first electrode 501 and the isolation region 103, so that the second region 102 remains exposed. That is, at this time, the outermost layer of the first region 101 is the exposed first electrode 501, and the first doped layer 301 has been completely covered by the first electrode 501. Therefore, the second mask 800 blocks the first electrode 501 on the first region 101. An electrode 501 , and shields the isolation region 103 again.
  • the second mask 800 is also a polymer tape, which can be pasted and fixed on the surface of the first electrode 501 and the isolation region 103 , and can be peeled off later.
  • step S600 as shown in FIG. 5 , the stacked second doped layer 302 and the second electrode 502 are successively formed in the second region 102, that is, the second doped layer 302 is first formed on the surface of the second region 102, and then The exposed surface of the second doped layer 302 forms the second electrode 502 .
  • the conductivity types of the first doped layer 301 and the second doped layer 302 are different. If the first region 101 is an N region, the first doped layer 301 is an N-type doped layer. A crystalline silicon layer or an N-type doped microcrystalline silicon layer.
  • the second region 102 is a P region
  • the second doped layer 302 is a P-type doped layer, which may specifically be a P-type doped amorphous silicon layer. layer or P-type doped microcrystalline silicon layer.
  • the first region 101 is a P region
  • the first doped layer 301 is a P type doped layer
  • the second region 102 is an N region
  • the second doped layer 302 is an N type doped layer.
  • the thickness of the second doped layer 302 is 2nm-50nm, preferably 5nm-10nm, specifically 5nm, 6nm, 7nm, 8nm, 9nm, 10nm or the like.
  • the material of the second electrode 502 can be one or more combinations of silver, nickel, aluminum, tin, and copper, and the thickness of the second electrode 502 is 3 ⁇ m to 30 ⁇ m, specifically 3 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, etc.
  • step S700 the second mask 800 is peeled off. Since in the process of forming the second doped layer 302 and the second electrode 502 in step S600, corresponding film layers will also be formed on the second mask 800, after the second mask 800 is peeled off, the second mask The film layers on the surface of 800 are peeled off together, leaving only the film layer on the second region 102 to form the second doped layer 302 and the second electrode 502. At this time, the first electrode 501 and the isolation region 103 are exposed again, and the process is completed. Fabrication of the P and N regions of the first surface.
  • the second region 102 and the isolation region 103 are covered by the first mask 700, and the first doped layer is continuously completed on the unshielded first region 101. 301 and the first electrode 501, to complete the fabrication of a doped conductive region, such as one of the P region and the N region; after that, the first mask 700 is peeled off to expose the second region 102 and the isolation region 103, Next, the isolation region 103 and the first doped layer 301 and the first electrode 501 that have been fabricated on the first region 101 are covered by the second mask 800, and the second region 102 that is not covered is continuously completed.
  • the fabrication of the second doped layer 302 and the second electrode 502 completes fabrication of another doped conductive region, such as the other of the P region and the N region.
  • the second mask 800 is peeled off, and the isolation region 103 is shielded twice by the first mask 700 and the second mask 800, and no conductive film layer will be formed in the isolation region.
  • the first electrode 501 and the second doped layer 302, the second electrode 502, the natural isolation of the two doped conductive regions is realized. It can be seen that through this preparation method, the isolation of the P region and the N region can be naturally formed, and there is no need to separate the P region and the N region through a photoresist process, a wet chemical etching process or a laser etching process.
  • each film layer in the P area and N area can be controlled independently, independently designed, and the preparation flexibility is higher, and the parameters of each film layer can be conveniently adjusted according to the demand.
  • step S300 after the first doped layer 301 is formed in the first region 101 in step S300 and before the first electrode 501 is formed, a step is further included: A first transparent conductive layer 401 is formed on the doped layer 301 . That is, in step S300 , the stacked first doped layer 301 , first transparent conductive layer 401 and first electrode 501 are sequentially formed on the surface of the first region 101 .
  • step S600 after the second doped layer 302 is formed in the second region 102 in step S600 and before the second electrode 502 is formed, a step is further included: forming a second transparent conductive layer on the second doped layer 302 402. That is, in step S600 , the second doped layer 302 , the second transparent conductive layer 402 and the second electrode 502 are sequentially formed in the second region 102 .
  • the first transparent conductive layer 401 can be formed only in the conductive film layer in the first region 101, and the second transparent conductive layer 402 is not provided in the second region 102; or only formed in the conductive film layer in the second region 102
  • the second transparent conductive layer 402, and the first transparent conductive layer 401 is not provided in the first region 101; or the first transparent conductive layer 401 and the second transparent conductive layer 402 are respectively formed in the first region 101 and the second region 102.
  • the first electrode 501 and the first doped layer 301 are electrically connected through the first transparent conductive layer 401, and the second electrode 502 and the second doped layer 302 are connected through the second transparent conductive layer 402.
  • Conductive connection Due to the low mobility of electrons and holes in the doped layer and poor lateral conductivity, it is not conducive to the collection of photogenerated carriers. Therefore, carriers are collected longitudinally through the transparent conductive layer and transported to the electrode.
  • the transparent conductive layer can reduce optical reflection at the same time, and it is easier to achieve ohmic contact when the electrode is in contact with the transparent conductive layer than when the electrode is directly in contact with the doped layer, thereby improving conduction efficiency.
  • the bonding strength between the electrode and the doped layer can also be improved through the transparent conductive layer.
  • both the first transparent conductive layer 401 and the second transparent conductive layer 402 are TCO layers, which can be specifically ITO (tin-doped indium oxide) layer, IWO (tungsten-doped indium oxide) layer, AZO (aluminum-doped zinc oxide) layer or GZO (gallium-doped zinc oxide) layer, etc.
  • the thickness of the first transparent conductive layer 401 and the second transparent conductive layer 402 can be 40nm-200nm, preferably 50nm-100nm, specifically 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.
  • the material and thickness of the transparent conductive layer are selected according to requirements.
  • Substrate 100 such as the surface of a silicon substrate, has a large number of dangling bonds, and the minority carriers excited by light are easily captured by the dangling bonds and recombined after reaching the surface, thereby reducing the efficiency of the cell. Therefore, the passivation layer reduces the generation of interface defects of the substrate , thereby reducing the recombination of carriers caused by defects and improving the photoelectric conversion efficiency.
  • the first passivation layer 201 is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer.
  • the thickness of the first passivation layer 201 is 5nm ⁇ 10nm, specifically 5nm, 6nm, 7nm, 8nm, 9nm, 10nm.
  • the first passivation layer 201 is deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD for short).
  • CVD chemical Vapor Deposition
  • each film layer is optimized.
  • one or more of the physical vapor deposition (Physical Vapor Deposition, referred to as PVD) method and the chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) method The seed deposition forms the first doped layer 301 , the first electrode 501 , the second doped layer 302 , the second electrode 502 , the first transparent conductive layer 401 and the second transparent conductive layer 402 .
  • physical vapor deposition can be thermal evaporation, electron beam evaporation, sputtering, and the like.
  • the chemical vapor deposition method can be plasma-enhanced chemical vapor deposition (PECVD), which has good film quality.
  • the CVD method and the PVD method are both low-temperature deposition methods, the working temperature of the CVD method is usually 200°C to 250°C, and the working temperature of the PVD method is usually 250°C to 450°C. Therefore, the process is relatively difficult.
  • the membrane is able to withstand the required temperature.
  • the first doped layer 301 and the second doped layer 302 are deposited by chemical vapor deposition (CVD); the first transparent conductive layer 401, 302 are deposited by physical vapor deposition (PVD) The second transparent conductive layer 402 , the first electrode 501 and the second electrode 502 .
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the first set of process equipment completes the film layer preparation in the first area 101 alone, and the first set of process equipment continues sequentially along the process sequence.
  • CVD equipment and PVD equipment are arranged.
  • the number of PVD equipment depends on the number of different film layers prepared. Since different film layers use different materials, the preparation of each film layer corresponds to different PVD equipment.
  • the first set of process equipment includes one CVD equipment and two PVD equipment. Adjacent equipment can be connected through a vacuum box with an inlet and outlet or a vacuum connection channel.
  • the first doped layer 301 is deposited in the CVD equipment, the first transparent conductive layer 401 is deposited in the first PVD equipment, and the first electrode 501 is deposited in the second PVD equipment to complete the film layer preparation of the first region 101 .
  • the deposition time of the first doped layer 301 is flexibly adjusted according to the deposition thickness of the first doped layer 301, and the deposition time is controlled by controlling the residence time of the substrate 100 in the CVD equipment, Usually the required time can be about 5min; Similarly, the deposition time for forming the first transparent conductive layer 401 in the first PVD equipment is usually about 2min, and the deposition time for forming the first electrode 501 in the second PVD equipment The time is about 5 minutes.
  • the second set of process equipment is used to complete the film layer preparation in the second area 102 alone.
  • the second set of process equipment is successively arranged with CVD equipment and PVD equipment along the process sequence.
  • the number of PVD equipment varies according to the number of different film layers prepared.
  • the preparation of each film layer corresponds to different PVD equipment.
  • the second set of process equipment includes one CVD equipment and two PVD equipment. Adjacent equipment can be connected through a vacuum box with an inlet and outlet or a vacuum connection channel.
  • the second doped layer 302 is deposited in the CVD device, the second transparent conductive layer 402 is deposited in the first PVD device, and the second electrode 502 is deposited in the second PVD device to complete the film layer preparation of the second region 102 .
  • the second transparent conductive layer 402 is deposited in the first PVD device, and the second electrode 502 is deposited in the second PVD device to complete the film layer preparation of the second region 102 .
  • only one PVD device is required.
  • the deposition time of the second doped layer 302 is flexibly adjusted according to the deposition thickness of the second doped layer 302, which can be different from the deposition thickness of the first doped layer 301 and controlled independently,
  • the deposition time is controlled by controlling the moving time of the substrate 100 in the CVD equipment, usually the required time can be about 5 minutes; similarly, the deposition time of the second transparent conductive layer 402 in the first PVD equipment is usually about 2 minutes , the deposition time of the second electrode 502 in the second PVD equipment is about 5 minutes.
  • the integration of CVD equipment and PVD equipment through a vacuum box or a vacuum channel can reduce vacuum breaking links, reduce pollution in the production process, and reduce transfer time.
  • the entire preparation process is continuous and the production efficiency is improved. Of course, if there is no need to prepare the second transparent conductive layer 402, only one PVD device is required.
  • the thicknesses of the first doped layer 301 and the second doped layer 302 are the same or different; the thicknesses of the first transparent conductive layer 401 and the second transparent conductive layer 402 are the same or different; the first electrode 501 and the second electrode 502 have the same or different thicknesses.
  • the second region 102 since the first doped layer 301, the first transparent conductive layer 401 and the first electrode 501 formed on the first region 101 are completed in a separate process, the second region 102 The second doped layer 302, the second transparent conductive layer 402 and the second electrode 502 formed on the above are completed in another separate process, and the processing of the film layers of the first region 101 and the second region 102 is independent of each other, Therefore, the thicknesses of the film layers in the first region 101 and the second region 102 can be independently adjusted according to the process and functional requirements, and can be the same or different, making the process more flexible.
  • the first doped layer 301 and the second doped layer have the same thickness, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
  • the thickness of the first doped layer 301 is 5nm, and the thickness of the second doped layer 302 is 8nm; the thickness of the first doped layer 301 is 6nm, and the thickness of the second doped layer 302 is 9nm;
  • the layer 301 has a thickness of 7 nm and the second doped layer 302 has a thickness of 10 nm.
  • the first transparent conductive layer 401 and the second transparent conductive layer 402 have the same thickness, which are 50nm, 60nm, 70nm, 80nm, 90nm or 100nm; or the thickness of the first transparent conductive layer 401 is 50nm, and the second transparent conductive layer
  • the thickness of the conductive layer 402 is 80nm; the thickness of the first transparent conductive layer 401 is 60nm, and the thickness of the second transparent conductive layer 402 is 90nm; the thickness of the first transparent conductive layer 401 is 70nm, and the thickness of the second transparent conductive layer 402 is 100nm.
  • the first electrode 501 and the second electrode 502 have the same thickness, 3 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m or 30 ⁇ m.
  • the thickness of the first electrode 501 is 5 ⁇ m, and the thickness of the second electrode is 20 ⁇ m; the thickness of the first electrode 501 is 10 ⁇ m, and the thickness of the second electrode is 25 ⁇ m; the thickness of the first electrode 501 is 15 ⁇ m, and the thickness of the second electrode is 30 ⁇ m.
  • both the first mask 700 and the second mask 800 have a base film and an adhesive layer
  • the material of the base film is extended polypropylene (CPP), uniaxially oriented polypropylene (OPP), biaxially Oriented polypropylene (BOPP), polyethylene (PE), polyester fiber (PET), polyvinyl chloride (PVC), polyethylene terephthalate (PET), polyolefin (PO), polyimide
  • the material of the adhesive layer is one or more combinations of water glue, oil glue, hot melt glue, natural rubber, and synthetic rubber.
  • the base film of the mask is extended polypropylene (CPP), and the adhesive layer is water glue; or, the base film of the mask is uniaxially stretched polypropylene (OPP), and the adhesive layer is oil glue; or, the mask
  • the base film of the film is biaxially oriented polypropylene (BOPP), and the adhesive layer is hot melt adhesive; or, the base film of the mask is polyethylene (PE), and the adhesive layer is natural rubber; or, the base film of the mask is polyester Ester fiber (PET), the glue layer is synthetic rubber; or, the base film of the mask is polyvinyl chloride (PVC), the glue line is water glue; or, the base film of the mask is extended polypropylene (CPP) and unidirectional It is a composition of stretched polypropylene (OPP), and the material of the glue layer is a composition of natural rubber and synthetic rubber. It is not limited to the mask composition forms listed in this embodiment.
  • the base film and the adhesive layer are made of low-cost materials, and the material of the base film has high impact resistance, strong mechanical properties, and resistance to various organic solvents and acid and alkali corrosion, it meets the requirements for the use of the mask. Not prone to corrosion damage.
  • the mask has a certain supporting strength and the function of easy separation, can be pasted and fixed on the film layer, can withstand the low temperature deposition process, and the mask is not cut when the laser is patterned, when placing the mask, due to the mask has A certain degree of hardness facilitates the precise alignment of the mask pattern and the film layer, the three-layer structure on the first region 101 made by the first mask 700, and the three-layer structure on the second region made by the second mask 800 1.
  • the width error of the isolation region 103 can reach ⁇ 0.05 ⁇ m.
  • the thickness of the first mask 700 and the second mask 800 is 2 ⁇ m-40 ⁇ m. According to mask requirements, select a mask with an appropriate thickness, specifically 2 ⁇ m, 3 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m.
  • the material of the first electrode 501 and the second electrode 502 may be one or more combinations of silver, nickel, aluminum, tin, and copper.
  • the peeling of the first mask 700 and the second mask 800 adopts one or more combinations of pyrolytic separation, ultraviolet light irradiation separation, and mechanical separation. Choose the appropriate stripping method according to the different adhesive layers of the mask. In these ways, the first mask 700 and the second mask 800 can easily and conveniently tear the film from the surface of the film layer. Of course, if there is a residual mask after tearing off the film, it can be cleaned through a cleaning process.
  • the embodiment of the present invention provides a specific manufacturing process of a back-contact silicon heterojunction solar cell:
  • Step 1 Taking an n-type crystalline silicon wafer as a silicon substrate as an example for illustration, the n-type crystalline silicon wafer (n-c-Si) is subjected to surface texture cleaning to form a pyramid structure and remove surface contamination impurities.
  • the silicon substrate 10 is an n-type double-sided polished Czochralski single crystal silicon wafer with a thickness of 180 ⁇ m, a resistivity of 0.3 ⁇ cm, and a minority carrier lifetime of 1000 ⁇ s.
  • a mixed solution of 2% NaOH and isopropanol solution (IPA) is used for texturing on one or both sides of the silicon wafer at a temperature of 83°C.
  • the RCA standard cleaning method to clean the surface of the silicon wafer to remove surface contamination impurities.
  • remove the surface oxide layer with 1% hydrofluoric acid solution If it is double-sided velvet, after the velvet cleaning of the backlight surface is completed, the backlight surface should be polished. If it is one-sided velvet, it can be velvet on the light incident side, but not on the back light side.
  • Step 3 As shown in FIG. 7 , lamination and pasting the laser-patterned first mask 700 on the first passivation layer 201 on the backlight surface, and the first mask 700 shields the P region and the isolation region, The N region is exposed. Of course, the N region and the isolation region can also be blocked to expose the P region.
  • the base film material of the first mask 700 is uniaxially oriented polypropylene (OPP), and the material of the adhesive layer is synthetic rubber.
  • the thickness of the first mask 700 is 5 ⁇ m.
  • Step 4 As shown in FIG. 8 , deposit a 2nm-50nm n-type a-Si:H doped layer (namely the first doped layer 301 ) on the N region by CVD method, specifically 5nm-10nm.
  • the power density of the power supply is 0.027W/cm 2 , the pressure is 100Pa, and the substrate temperature is 200°C.
  • Step 6 As shown in FIG. 8 , deposit a first electrode 501 with a thickness of 3 ⁇ m to 30 ⁇ m on the surface of the first transparent conductive layer 401 in the N region by PVD method, and the material may be copper, aluminum or the like.
  • Step 7 As shown in FIG. 9 , tear off the first mask 700 to complete the preparation of the film layer of the N region.
  • Step 8 As shown in FIG. 10 , lamination and pasting the laser-patterned second mask 800 on the first electrode 501 and the isolation region 103 to cover the completed N region and the isolation region 103 to expose the P district.
  • the material of the base film of the second mask 800 is uniaxially oriented polypropylene (OPP), and the material of the adhesive layer is synthetic rubber.
  • the thickness of the second mask 800 is 5 ⁇ m.
  • Step 9 As shown in FIG. 11 , deposit a 2nm-50nm P-type a-Si:H doped layer (that is, the second doped layer 302 ) on the P region by CVD method, specifically 5nm-10nm.
  • the power density of the power supply is 0.027W/cm 2
  • the pressure is 70Pa
  • the substrate temperature is 200°C.
  • Step 11 As shown in FIG. 11 , deposit a second electrode 502 with a thickness of 3 ⁇ m to 30 ⁇ m on the surface of the second transparent conductive layer 402 in the P region by PVD method, and the material can be copper, aluminum, or the like.
  • Step 12 As shown in FIG. 12 , the second mask 800 is torn off to complete the preparation of the film layer of the P region, and the P region and the N region are naturally isolated.
  • the second passivation layer 202 and the anti-reflection layer 600 formed on the second surface of the substrate 100, that is, the light incident surface, can be completed simultaneously in the second step, the second passivation layer 202 and the first passivation layer
  • the process of layer 201 can be the same, and the antireflection layer 600 is a silicon nitride antireflection layer.
  • the embodiment of the present invention also provides a back-contact silicon heterojunction solar cell, which is prepared by using the preparation method described in any of the above embodiments. Since the back-contact silicon heterojunction solar cell is obtained by the preparation method in the present application, it has the same technical effect as the preparation method, and will not be repeated here.
  • the present invention also provides a back-contact silicon heterojunction solar cell, including:
  • a substrate 100, the first surface of the substrate 100 has a first region 101, a second region 102 and an isolation region 103, and the first region 101 and the second region 102 are separated by the isolation region 103;
  • the first electrode 501 located on the surface of the first doped layer 301, the projection of the first electrode 501 on the first surface coincides with the projection of the first doped layer 301 on the first surface;
  • the projection of the second electrode 502 on the first surface coincides with the projection of the second doped layer 302 on the first surface.
  • the first doped layer 301 and the first electrode 501 stacked on the first region 101 and the second doped layer 302 and the second electrode 502 stacked on the second region 102 pass through the isolation region 103 isolated, and the projections of the first doped layer 301 and the first electrode 501 on the first surface coincide, and the projections of the second doped layer 302 and the second electrode 502 on the first surface coincide, that is, the electrodes completely cover the doped layer.
  • the width of the electrode is equal to that of the doped layer. Compared with the existing electrodes formed by screen printing, the width of the electrode is smaller than that of the doped layer. The width of the electrode in this application is larger, which increases the longitudinal direction of the carriers. The area transmitted to the electrode has higher photoelectric conversion efficiency.
  • the back-contact silicon heterojunction solar cell further includes a first passivation layer 201 on the first surface of the substrate 100 .
  • the first doped layer and the second doped layer are located on the surface of the first passivation layer away from the substrate.
  • the interface defects of the substrate 100 are reduced through the first passivation layer 201 , thereby reducing the recombination of carriers caused by the defects, and improving the photoelectric conversion efficiency.
  • the first passivation layer 201 is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer.
  • the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer Through the intrinsic amorphous silicon layer and intrinsic microcrystalline silicon layer, the dangling bonds can be effectively hydrogenated and surface defects can be reduced, thereby significantly improving the minority carrier lifetime, increasing the open circuit voltage, and finally improving the photoelectric conversion efficiency.
  • the back contact silicon heterojunction solar cell further includes:
  • the first electrode 501 and the first doped layer 301 are electrically connected through the first transparent conductive layer 401, and the second electrode 502 and the second doped layer 302 are connected through the second transparent conductive layer. 402 conductive connection. Due to the low mobility of electrons and holes in the doped layer and poor lateral conductivity, it is not conducive to the collection of photogenerated carriers. Therefore, carriers are collected vertically through the transparent conductive layer and transported to the electrode.
  • the transparent conductive layer can reduce optical reflection at the same time, and the contact between the electrode and the transparent conductive layer is easier to achieve ohmic contact than the contact between the electrode and the doped layer, thereby improving the conductivity. efficiency.
  • the projected dimensions of the first doped layer 301, the first transparent conductive layer 401 and the first electrode 501 on the first surface of the first region 101 are consistent, and the second doped layer 302, the second transparent conductive layer 401 of the second region 102
  • the projected dimensions of the layer 402 and the second electrode 502 on the first surface are consistent. In this way, the vertical transport of carriers is improved, and the photoelectric conversion efficiency is improved.
  • the thicknesses of the first doped layer 301 and the second doped layer 302 are the same or different; the thicknesses of the first transparent conductive layer 401 and the second transparent conductive layer 402 are the same or different; the first electrode 501 and the second electrode 502 have the same or different thicknesses.
  • the first doped layer 301 , the first transparent conductive layer 401 and the first electrode 501 formed on the first region 101 and the second doped layer 302 formed on the second region 102 since the first doped layer 301 , the first transparent conductive layer 401 and the first electrode 501 formed on the first region 101 and the second doped layer 302 formed on the second region 102 , The second transparent conductive layer 402 and the second electrode 502 are independent of each other, and the thickness and parameters of each film layer in the first region 101 and the second region 102 can be independently adjusted according to the process and functional requirements.
  • the back-contact silicon heterojunction solar cell also includes:
  • a second passivation layer 202 located on the second surface of the substrate 100, the second surface is disposed opposite to the first surface;
  • the anti-reflection layer 600 located on the surface of the second passivation layer 202 .
  • the second surface of the substrate 100 has better passivation effect and anti-reflection effect.
  • the width of the P region is 400 ⁇ m-600 ⁇ m; the width of the N region is 300 ⁇ m-500 ⁇ m; the width of the isolation region is 70 ⁇ m-120 ⁇ m.
  • the width represents a dimension in a plane parallel to the first surface and in a direction from the P region to the N region.
  • the width of the P region can be 400 ⁇ m, 450 ⁇ m, 500 ⁇ m, 550 ⁇ m, 600 ⁇ m, etc.; the width of the N region can be 300 ⁇ m, 350 ⁇ m, 400 ⁇ m, 450 ⁇ m, 500 ⁇ m, etc.; the width of the isolation region can be 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, 100 ⁇ m, 110 ⁇ m, 120 ⁇ m wait.
  • An appropriate width is selected according to the requirements of the process, which is not specifically limited here.
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative effort.
  • references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

本发明公开一种背接触式硅异质结太阳能电池及其制备方法，涉及太阳能电池制造领域，用于解决太阳能电池制备工艺复杂的问题。该制备方法通过第一掩膜遮住第二区域和隔离区域，在第一区域上完成第一掺杂层和第一电极的制作；之后，将第一掩膜剥离，再通过第二掩膜遮住隔离区域和第一区域，在第二区域上连续完成第二掺杂层和第二电极的制作，之后，将第二掩膜剥离，隔离区域没有形成任何膜层。该制备方法能够自然形成P区和N区的隔离，不需要单独通过光刻工序、湿化学刻蚀工艺或激光刻蚀工艺将P区和N区隔离，大大简化了制备工艺。本发明提供的背接触式硅异质结太阳能电池采用本发明中的制备方法制备得到。

Description

一种背接触式硅异质结太阳能电池及其制备方法
本申请要求在2022年1月7日提交中国专利局、申请号为202210016391.0、发明名称为“一种背接触式硅异质结太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及太阳能电池制造技术领域，尤其涉及一种背接触式硅异质结太阳能电池及其制备方法。
背景技术
背接触式硅异质结太阳能电池既具有异质结太阳能电池高开压、高填充因子的特点，又具有背接触式太阳能电池遮光少、高电流的优势，目前已经实现了26.7％的实验室光电转换效率，是未来商业化太阳电池高度关注的技术路线之一。
背接触式硅异质结太阳能电池在背光面具有N区和P区，在N区和P区的制备过程中，通常需要多次光刻工序、多次掩膜工序、多次湿化学刻蚀工序、多次清洗工序等多个工序交替进行，以实现电池背光面N区和P区的隔离，工艺过程非常复杂。
发明内容
本发明的目的在于提供一种背接触式硅异质结太阳能电池及其制备方法，以简化工艺。
为实现上述目的，本发明提供以下技术方案：
第一方面，本发明提供一种背接触式硅异质结太阳能电池的制备方法，包括：提供一基底，基底的第一表面具有第一区域、第二区域和隔离区域，通过隔离区域间隔第一区域和第二区域；在基底上固定第一掩膜，第一掩膜覆盖第二区域和隔离区域，使第一区域裸露；在第一区域先后形成层叠的第一掺杂层和第一电极；剥离第一掩膜；在第一电极裸露的表面固定第二掩膜，第二掩膜覆盖第一电极和隔离区域，使第二区域裸露；在第二区域先后形成层叠的第二掺杂层和第二电极，第一掺杂层和第二掺杂层的导电类型不同； 剥离第二掩膜，其中，第一掩膜和第二掩膜均为聚合物胶带。
采用上述技术方案的情况下，在基底的第一表面上，通过第一掩膜遮住第二区域和隔离区域，在未被遮住的第一区域上连续完成第一掺杂层和第一电极的制作，完成一种掺杂导电区的制作，如P区和N区中的一种；之后，将第一掩膜剥离，露出第二区域和隔离区域，接下来通过第二掩膜遮住隔离区域和已经在第一区域上制作好的第一掺杂层和第一电极，在未被遮住的第二区域上连续完成第二掺杂层和第二电极的制作，完成另一种掺杂导电区的制作，如P区和N区中的另一种。之后，将第二掩膜剥离，此时，隔离区域上没有形成任何膜层，实现了两个掺杂导电区的自然隔离。可见，通过该制备方法，能够在制作第一掺杂层、第一电极以及第二掺杂层、第二电极的过程自然形成P区和N区的隔离，不需要单独通过湿化学刻蚀工艺或激光刻蚀工艺将P区和N区隔离开。且整个制作过程中，可以单独一个流程完成P区的制备后，再单独一个流程完成N区的制备，工艺上更加独立，采用的流程更加简单，相比于现有的多次光刻工序、多次掩膜工序、多次湿化学刻蚀工序、多次清洗工序等多个工序交替进行，大大简化了制备工艺。且P区和N区的各膜层能够单独控制，独立设计，制备灵活性更高，能够根据需求方便调整各膜层参数。
在一些可能的实施方式中，在第一区域形成第一掺杂层之后，且形成第一电极之前，还包括步骤：在第一掺杂层上形成第一透明导电层；和/或，在第二区域形成第二掺杂层之后，且形成第二电极之前，还包括步骤：在第二掺杂层上形成第二透明导电层。
采用上述技术方案情况下，第一电极与第一掺杂层之间通过第一透明导电层导电连接，第二电极与第二掺杂层之间通过第二透明导电层导电连接。由于掺杂层的电子与空穴迁徙率较低，且横向导电性较差，不利于光生载流子的收集。因此通过透明导电层纵向收集载流子并向电极传输，可以提高光生载流子的收集和传输效率，且电极与透明导电层接触相比于电极与掺杂层接触更容易实现欧姆接触，从而可以减少载流子损耗。另外，透明导电层可以减少光学反射，提高太阳能光入射率。
在一些可能的实施方式中，通过物理气相沉积方法和化学气相沉积方法中的一种或多种沉积形成第一掺杂层、第一电极、第二掺杂层、第二电极、第一透明导电层和第二透明导电层。
在一些可能的实施方式中，通过化学气相沉积(Chemical Vapor  Deposition，简称CVD)方法沉积形成第一掺杂层、第二掺杂层；通过物理气相沉积(Physical Vapor Deposition，简称PVD)方法沉积形成第一透明导电层、第二透明导电层、第一电极和第二电极。CVD方法和PVD方法均为低温沉积方法，工艺难度较低，本申请中的掩膜能够承受所需要的温度。
在一些可能的实施方式中，第一掺杂层和第二掺杂层为掺杂非晶硅层或掺杂微晶硅层，第一掺杂层和第二掺杂层的厚度为2nm-50nm；和/或，第一透明导电层和第二透明导电层为掺锡氧化铟层、掺钨氧化铟层、掺铝氧化锌层或掺镓氧化锌层，第一透明导电层和第二透明导电层的厚度为40nm～200nm；和/或，第一电极和第二电极的材质为银、镍、铝、锡、铜中的一种或多种组合，第一电极和第二电极的厚度为3μm～30μm。
采用上述技术方案的情况下，各膜层的材质和厚度根据工艺和功能需要选择。
在一些可能的实施方式中，第一掺杂层与第二掺杂层的厚度相同或不同；第一透明导电层与第二透明导电层的厚度相同或不同；第一电极与第二电极的厚度相同或不同。
采用上述技术方案的情况下，由于在第一区域上形成的第一掺杂层、第一透明导电层和第一电极是在一个单独的流程中完成的，在第二区域上形成的第二掺杂层、第二透明导电层和第二电极是在另一个单独的流程中完成的，及第一区域和第二区域的膜层的加工相互独立，因此，可以根据工艺和功能需要，独立调整第一区域和第二区域各膜层的厚度，可以对应相同或不同，工艺更加灵活。
在一些可能的实施方式中，在提供一基底之后，且在基底上固定第一掩膜之前，还包括步骤：在所述基底的第一表面形成第一钝化层。
采用上述技术方案的情况下，通过第一钝化层减少基底的界面缺陷，进而减少由于缺陷导致的载流子的复合，提高光电转换效率。
在一些可能的实施方式中，第一钝化层为本征非晶硅层或本征微晶硅层。通过本征非晶硅层和本征微晶硅层，可以有效地将悬挂键氢化并降低表面缺陷，从而显著提高少子寿命，增加开路电压，最终提高光电转换效率。
在一些可能的实施方式中，第一掩膜和第二掩膜均具有基膜和胶层，基膜的材质为延聚丙烯、单向拉伸聚丙烯、双向拉伸聚丙烯、聚乙烯、聚酯纤维、聚氯乙烯、聚对苯二甲酸乙二酯、聚烯烃、聚酰亚胺中的一种或多种组合；胶层的材质为水胶、油胶、热熔胶、天然橡胶、合成橡胶、硅胶、亚克 力胶、聚异丁烯、和聚氨酯中的一种或多种组合；第一掩膜和第二掩膜的厚度为2μm-40μm。
采用上述技术方案的情况下，基膜和胶层均选用成本较低的材质，且基膜的材质具有较高的耐冲击性，机械性质强韧，抗多种有机溶剂和酸碱腐蚀，满足了掩膜使用要求。且掩膜具有一定的支撑强度和方便分离的功能，可以粘贴固定于膜层上，能够承受低温沉积工艺，且掩膜在激光进行图案化时不切断，在放置掩膜时，由于掩膜有一定的硬度，方便掩膜图案与膜层的精确定位。
在一些可能的实施方式中，第一掩膜和第二掩膜的剥离采用热解分离、紫外光照射分离、机械分离中的一种或多种组合。根据掩膜的胶层的不同选择合适的剥离方式。
第二方面，本发明还提供一种背接触式硅异质结太阳能电池，采用如以上任一项所述的制备方法制备得到。由于该背接触式硅异质结太阳能电池采用本申请中的制备方法得到，因此具有与制备方法相同的技术效果，在此不再赘述。
第三方面，本发明还提供一种背接触式硅异质结太阳能电池，包括：基底，基底的第一表面具有第一区域、第二区域和隔离区域，通过隔离区域间隔第一区域和第二区域；位于第一区域的第一掺杂层；位于第一掺杂层表面的第一电极，第一电极在第一表面的投影与第一掺杂层在第一表面的投影重合；位于第二区域的第二掺杂层，第一掺杂层和第二掺杂层的导电类型不同；位于第二掺杂层表面的第二电极，第二电极在第一表面的投影与第二掺杂层在第一表面的投影重合。
采用上述技术方案的情况下，第一区域上层叠形成的第一掺杂层和第一电极，与第二区域上层叠形成的第二掺杂层和第二电极通过隔离区域隔离，且第一掺杂层和第一电极在第一表面的投影重合，第二掺杂层和第二电极在第一表面的投影重合，即电极完全覆盖了掺杂层的表面，电极与掺杂层的宽度相等，相比于现有的电极通过丝网印刷而成，电极的宽度小于掺杂层，本申请中的电极宽度更大，增大了载流子的纵向传输至电极的面积，光电转化效率更高。
在一些可能的实施方式中，背接触式硅异质结太阳能电池还包括位于基底的第一表面的第一钝化层；第一掺杂层和第二掺杂层位于第一钝化层远离基底的表面。
采用上述技术方案的情况下，通过钝化层减少基底的界面缺陷，进而减少由于缺陷导致的载流子的复合，提高光电转换效率。
在一些可能的实施方式中，第一钝化层为本征非晶硅层或本征微晶硅层。通过本征非晶硅层和本征微晶硅层，可以有效地将悬挂键氢化并降低表面缺陷，从而显著提高少子寿命，增加开路电压，最终提高光电转换效率。
在一些可能的实施方式中，背接触式硅异质结太阳能电池还包括：位于第一掺杂层和第一电极之间的第一透明导电层，第一透明导电层在第一表面的投影与第一掺杂层在第一表面的投影重合；和/或，位于第二掺杂层和第二电极之间的第二透明导电层，第二透明导电层在第一表面的投影与第二掺杂层在第一表面的投影重合。
采用上述技术方案的情况下，第一电极与第一掺杂层之间通过第一透明导电层导电连接，第二电极与第二掺杂层之间通过第二透明导电层导电连接。由于掺杂层的电子与空穴迁徙率较低，且横向导电性较差，不利于光生载流子的收集。因此通过透明导电层纵向收集载流子并向电极传输，透明导电层同时可以减少光学反射，且电极与透明导电层接触相比于电极与掺杂层接触更容易实现欧姆接触，从而提高了导电效率。
在一些可能的实施方式中，第一掺杂层与第二掺杂层的厚度相同或不同；第一透明导电层与第二透明导电层的厚度相同或不同；第一电极与第二电极的厚度相同或不同。
采用上述技术方案的情况下，由于在第一区域上形成的第一掺杂层、第一透明导电层和第一电极与在第二区域上形成的第二掺杂层、第二透明导电层和第二电极相互独立，可以根据工艺和功能需要，独立调整第一区域和第二区域各膜层的厚度和参数。
在一些可能的实施方式中，背接触式硅异质结太阳能电池还包括：位于基底的第二表面的第二钝化层，第二表面与第一表面相背设置；位于第二钝化层表面的减反层。
采用上述技术方案的情况下，使得基底的第二表面具有较好的钝化效果和减反射效果。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图6为本发明实施例提供的一种背接触式硅异质结太阳能电池的制作过程示意图；
图7-图12为本发明实施例提供的另一种背接触式硅异质结太阳能电池的制作过程示意图；
图13为本发明实施例提供的一种背接触式硅异质结太阳能电池的结构示意图。
附图标记：100-基底、101-第一区域、102-第二区域、103-隔离区域、201-第一钝化层、202-第二钝化层、301-第一掺杂层、302-第二掺杂层、401-第一透明导电层、402-第二透明导电层、501-第一电极、502-第二电极、600-减反层、700-第一掩膜、800-第二掩膜。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
背接触式硅异质结太阳能电池在背光面具有N区和P区，在N区和P区的制备过程中，通常需要多次光刻工序、多次掩膜工序、多次湿化学刻蚀工序、多次清洗工序等多个工序交替进行，以实现电池背光面N区和P区的隔离，工艺过程非常复杂。
为解决上述问题，本发明实施例提供一种背接触式硅异质结太阳能电池的制备方法，包括以下步骤：
步骤S100，提供一基底100，基底100具有相背的第一表面和第二表面，第一表面为基底100的背光面，第二表面为基底100的入光面。基底100可以为n型晶体硅片或p型晶体硅片。当然，基底100的第一表面和第二表面上也可以具有钝化层等功能结构。第一表面具有第一区域101、第二区域102和隔离区域103，通过隔离区域103间隔第一区域101和第二区域102，其中，第一区域101和第二区域102分别用于在其上形成不同导电类型的膜层，如形成P区和N区，如果第一区域101用于形成P区，则第二区域102用于形成N区，或者如果第一区域101用于形成N区，则第二区域102用于形成P区，隔离区域103用于将N区和P区隔离，实现绝缘。
步骤S200，如图1所示，在基底100的第一表面上固定第一掩膜700，第一掩膜700覆盖第二区域102和隔离区域103，使第一区域101裸露。第一掩膜700起到仅遮挡第二区域102和隔离区域103的作用，第一掩膜700为聚合物胶带，能够粘贴固定于第一表面上，后续可以从第一表面剥离。
步骤S300，如图2所示，在裸露的第一区域101的表面先后形成层叠的第一掺杂层301和第一电极501，即先仅在第一区域101的表面形成第一掺杂层301，再在第一掺杂层301裸露的表面形成第一电极501。如果第一区域101为N区，则第一掺杂层301为N型掺杂层，具体可以为N型的掺杂非晶硅层或N型的掺杂微晶硅层。如果第一区域101为P区，则第一掺杂层301为P型掺杂层，具体可以为P型掺杂非晶硅层或P型掺杂微晶硅层。第一掺杂层301的厚度为2nm-50nm，优选为5nm～10nm，具体可以为5nm、6nm、7nm、8nm、9nm、10nm等。第一电极501的材质可以为银、镍、铝、锡、铜中的一种或多种组合，第一电极501的厚度为3μm～30μm，具体可以为3μm、5μm、10μm、15μm、20μm、25μm、30μm等。
步骤S400，如图3所示，剥离第一掩膜700。由于在步骤S200中形成第一掺杂层301和第一电极501的过程中，第一掩膜700上也会形成相应的膜层，因此，将第一掩膜700剥离后，沉积在第一掩膜700表面的材料一起被剥离去除，仅保留位于第一区域101上的膜层，形成第一掺杂层301和第一电极501，此时，第二区域102和隔离区域103重新裸露。
步骤S500，如图4所示，在第一电极501裸露的表面固定第二掩膜 800，第二掩膜800覆盖第一电极501和隔离区域103，使第二区域102保持裸露。即此时第一区域101的最外层为裸露的第一电极501，第一掺杂层301已经被第一电极501完全覆盖，因此，通过第二掩膜800遮挡第一区域101上的第一电极501，并再次遮挡隔离区域103。第二掩膜800同样为聚合物胶带，能够粘贴固定于第一电极501和隔离区域103的表面，并可以后续剥离。
步骤S600，如图5所示，在第二区域102先后形成层叠的第二掺杂层302和第二电极502，即先在第二区域102的表面形成第二掺杂层302，再在第二掺杂层302裸露的表面形成第二电极502。第一掺杂层301和第二掺杂层302的导电类型不同，如果第一区域101为N区，则第一掺杂层301为N型掺杂层，具体可以为N型的掺杂非晶硅层或N型的掺杂微晶硅层，对应的，第二区域102为P区，则第二掺杂层302为P型掺杂层，具体可以为P型的掺杂非晶硅层或P型的掺杂微晶硅层。如果第一区域101为P区，第一掺杂层301为P型掺杂层，对应的，第二区域102为N区，第二掺杂层302为N型掺杂层。第二掺杂层302的厚度为2nm-50nm，优选为5nm～10nm，具体可以为5nm、6nm、7nm、8nm、9nm、10nm等。第二电极502的材质可以为银、镍、铝、锡、铜中的一种或多种组合，第二电极502的厚度为3μm～30μm，具体可以为3μm、5μm、10μm、15μm、20μm、25μm、30μm等。
步骤S700，如图6所示，剥离第二掩膜800。由于在步骤S600中形成第二掺杂层302和第二电极502的过程中，第二掩膜800上也会形成相应的膜层，因此，将第二掩膜800剥离后，第二掩膜800表面的膜层一起被剥离去除，仅保留位于第二区域102上的膜层，形成第二掺杂层302和第二电极502，此时，第一电极501和隔离区域103重新裸露，完成第一表面的P区和N区的制作。
通过上述技术方案可知，在基底100的第一表面上，通过第一掩膜700遮住第二区域102和隔离区域103，在未被遮住的第一区域101上连续完成第一掺杂层301和第一电极501的制作，完成一种掺杂导电区的制作，如P区和N区中的一种；之后，将第一掩膜700剥离，露出第二区域102和隔离区域103，接下来通过第二掩膜800遮住隔离区域103和已经在第一区域101 上制作好的第一掺杂层301和第一电极501，在未被遮住的第二区域102上连续完成第二掺杂层302和第二电极502的制作，完成另一种掺杂导电区的制作，如P区和N区中的另一种。之后，将第二掩膜800剥离，隔离区域103通过第一掩膜700和第二掩膜800的先后两次遮挡，均不会在隔离区域形成任何导电膜层，在制作第一掺杂层301、第一电极501以及第二掺杂层302、第二电极502的过程中，实现了两个掺杂导电区的自然隔离。可见，通过该制备方法，能够自然形成P区和N区的隔离，不需要单独通过光刻胶工序、湿化学刻蚀工艺或激光刻蚀工艺将P区和N区隔离操作。且整个制作过程中，可以单独一个流程完成P区的制备后，再单独一个流程完成N区的制备，工艺上更加独立，采用的流程更加简单，相比于现有的多次光刻工序、多次掩膜工序、多次湿化学刻蚀工序、多次清洗工序等多个工序交替进行，大大简化了制备工艺，提高了加工效率。且P区和N区的各膜层能够单独控制，独立设计，制备灵活性更高，能够根据需求方便调整各膜层参数。
如图8所示，进一步地，在一些可能的实施方式中，在步骤S300中的第一区域101形成第一掺杂层301之后，且形成第一电极501之前，还包括步骤：在第一掺杂层301上形成第一透明导电层401。即在步骤S300中，在第一区域101的表面先后形成层叠的第一掺杂层301、第一透明导电层401和第一电极501。
和/或，
如图11所示，在步骤S600中的第二区域102形成第二掺杂层302之后，且形成第二电极502之前，还包括步骤：在第二掺杂层302上形成第二透明导电层402。即在步骤S600中，在第二区域102先后形成层叠的第二掺杂层302、第二透明导电层402和第二电极502。
具体地，可以仅在第一区域101的导电膜层中形成第一透明导电层401，而第二区域102不设置第二透明导电层402；或者仅在第二区域102的导电膜层中形成第二透明导电层402，而第一区域101不设置第一透明导电层401；或者第一区域101和第二区域102分别形成第一透明导电层401和第二透明导电层402。
采用上述技术方案情况下，第一电极501与第一掺杂层301之间通过第 一透明导电层401导电连接，第二电极502与第二掺杂层302之间通过第二透明导电层402导电连接。由于掺杂层的电子与空穴迁徙率较低，且横向导电性较差，不利于光生载流子的收集。因此通过透明导电层纵向收集载流子并向电极传输，透明导电层同时可以减少光学反射，且电极与透明导电层接触相比于电极直接与掺杂层接触更容易实现欧姆接触，从而提高了导电效率。此外，通过透明导电层还可以提高电极与掺杂层的结合强度。
其中，第一透明导电层401和第二透明导电层402均为TCO层，具体可以为ITO(掺锡氧化铟)层、IWO(掺钨氧化铟)层、AZO(掺铝氧化锌)层或GZO(掺镓氧化锌)层等。第一透明导电层401和第二透明导电层402的厚度可以为40nm～200nm，优选为50nm～100nm，具体可以为50nm、60nm、70nm、80nm、90nm、100nm等。透明导电层的材质和厚度根据需要选择。
如图7所示，进一步地，在一些可能的实施方式中，在步骤S100中的提供一基底100之后，且在步骤S200中的基底100上固定第一掩膜700之前，还包括步骤：在基底100的第一表面形成第一钝化层201。基底100，如硅衬底表面存在大量的悬挂键，光照激发的少数载流子到达表面后容易被悬挂键俘获而复合，从而降低电池效率，因此，通过钝化层减少基底的界面缺陷的产生，进而减少由于缺陷导致的载流子的复合，提高光电转换效率。
作为优化，在本实施例中，第一钝化层201为本征非晶硅层或本征微晶硅层。第一钝化层201的厚度为5nm～10nm，具体可以为5nm、6nm、7nm、8nm、9nm、10nm。通过化学气相沉积(Chemical Vapor Deposition，简称CVD)方法沉积形成第一钝化层201。通过本征非晶硅层和本征微晶硅层，可以有效地将悬挂键氢化并降低表面缺陷，从而显著提高少子寿命，增加开路电压，最终提高光电转换效率。
进一步地，对各膜层的形成进行优化，在本实施例中，通过物理气相沉积(Physical Vapor Deposition，简称PVD)方法和化学气相沉积(Chemical Vapor Deposition，简称CVD)方法中的一种或多种沉积形成第一掺杂层301、第一电极501、第二掺杂层302、第二电极502、第一透明导电层401和第二透明导电层402。其中，物理气相沉积可以为热蒸镀、电子束蒸镀、 溅射等。化学气相沉积方法可以为等离子体增强化学的气相沉积法(PECVD)，成膜质量好，当然也可以为其他化学气相沉积方法，如热丝化学气相沉积方法(hotwire-CVD)、低压力化学气相沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)。由于CVD方法和PVD方法均为低温沉积方法，CVD方法的工作温度通常为200℃～250℃，PVD方法的工作温度通常为250℃～450℃，因此，工艺难度较低，本申请中的掩膜能够承受所需要的温度。
具体地，在本实施例中，通过化学气相沉积(CVD)方法沉积形成第一掺杂层301、第二掺杂层302；通过物理气相沉积(PVD)方法沉积形成第一透明导电层401、第二透明导电层402、第一电极501和第二电极502。
在进行第一区域101和第二区域102的膜层制备时，可以采用两套流程设备，第一套流程设备单独完成第一区域101的膜层制备，第一套流程设备沿工艺顺序依次连续布置有CVD设备和PVD设备，PVD设备的数量根据制备的不同膜层的数量而定，由于不同的膜层采用的材料不同，因此，每个膜层的制备对应不同的PVD设备。例如，当第一区域101依次沉积第一掺杂层301、第一透明导电层401和第一电极501时，则第一套流程设备包括一个CVD设备和两个PVD设备。相邻的设备可以通过具有进出口的真空箱或真空连接通道连接。在CVD设备内沉积第一掺杂层301，在第一个PVD设备内沉积第一透明导电层401，在第二个PVD设备内沉积第一电极501，完成第一区域101的膜层制备。整个第一区域101的膜层制备过程中，第一掺杂层301的沉积时间根据第一掺杂层301的沉积厚度灵活调整，通过控制基底100在CVD设备中的停留时间来控制沉积时间，通常所需要的时间可以为5min左右；同理地，在第一个PVD设备中形成第一透明导电层401的沉积时间通常为2min左右，在第二个PVD设备中形成第一电极501的沉积时间为5min左右。可见，将CVD设备和PVD设备通过真空箱或真空通道集成在一起，可以减少破真空环节，减少了制作过程的污染，减少转运时间，整个制备过程连续，提高了制备效率。当然，如果不需要制备第一透明导电层，则只需要一个PVD设备即可。
之后，采用第二套流程设备单独完成第二区域102的膜层制备，第二套流程设备沿工艺顺序依次连续布置有CVD设备和PVD设备，PVD设备的 数量根据制备的不同膜层的数量而定，由于不同的膜层采用的材料不同，因此，每个膜层的制备对应不同的PVD设备。例如，当第二区域102依次沉积第二掺杂层302、第二透明导电层402和第二电极502时，则第二套流程设备包括一个CVD设备和两个PVD设备。相邻的设备可以通过具有进出口的真空箱或真空连接通道连接。在CVD设备内沉积第二掺杂层302，在第一个PVD设备内沉积第二透明导电层402，在第二个PVD设备内沉积第二电极502，完成第二区域102的膜层制备。当然，如果不需要制备第二透明导电层402，则只需要一个PVD设备即可。整个第二区域102的膜层制备过程中，第二掺杂层302的沉积时间根据第二掺杂层302的沉积厚度灵活调整，可以与第一掺杂层301的沉积厚度不同，独立控制，通过控制基底100在CVD设备中的移动时间来控制沉积时间，通常所需要的时间可以为5min左右；同理地，第二透明导电层402在第一个PVD设备中的沉积时间通常为2min左右，第二电极502在第二个PVD设备中的沉积时间为5min左右。可见，将CVD设备和PVD设备通过真空箱或真空通道集成在一起，可以减少破真空环节，减少了制作过程的污染，减少转运时间，整个制备过程连续，提高了制备效率。当然，如果不需要制备第二透明导电层402，则只需要一个PVD设备即可。
进一步的，在本实施例中，第一掺杂层301与第二掺杂层302的厚度相同或不同；第一透明导电层401与第二透明导电层402的厚度相同或不同；第一电极501与第二电极502的厚度相同或不同。
采用上述技术方案的情况下，由于在第一区域101上形成的第一掺杂层301、第一透明导电层401和第一电极501是在一个单独的流程中完成的，在第二区域102上形成的第二掺杂层302、第二透明导电层402和第二电极502是在另一个单独的流程中完成的，及第一区域101和第二区域102的膜层的加工相互独立，因此，可以根据工艺和功能需要，独立调整第一区域101和第二区域102各膜层的厚度，可以对应相同或不同，工艺更加灵活。
例如，第一掺杂层301和第二掺杂层的厚度相同，均为5nm、6nm、7nm、8nm、9nm或10nm。或者第一掺杂层301的厚度为5nm，第二掺杂层302的厚度为8nm；第一掺杂层301的厚度为6nm，第二掺杂层302的厚度为的9nm；第一掺杂层301的厚度为7nm，第二掺杂层302的厚度为10nm。
同理地，第一透明导电层401与第二透明导电层402的厚度相同，均为50nm、60nm、70nm、80nm、90nm或100nm；或者第一透明导电层401的厚度为50nm，第二透明导电层402的厚度为80nm；第一透明导电层401的厚度为60nm，第二透明导电层402的厚度为90nm；第一透明导电层401的厚度为70nm，第二透明导电层402的厚度为100nm。
同理地，第一电极501余第二电极502的厚度相同，均为3μm、5μm、10μm、15μm、20μm、25μm或30μm。或者，第一电极501的厚度为5μm，第二电极的厚度为20μm；第一电极501的厚度为10μm，第二电极的厚度为25μm；第一电极501的厚度为15μm，第二电极的厚度为30μm。
在一些可能的实施方式中，第一掩膜700和第二掩膜800均具有基膜和胶层，基膜的材质为延聚丙烯(CPP)、单向拉伸聚丙烯(OPP)、双向拉伸聚丙烯(BOPP)、聚乙烯(PE)、聚酯纤维(PET)、聚氯乙烯(PVC)、聚对苯二甲酸乙二酯(PET)、聚烯烃(PO)、聚酰亚胺(PI)中的一种或多种组合；胶层的材质为水胶、油胶、热熔胶、天然橡胶、合成橡胶中的一种或多种组合。
示例性的，掩膜的基膜为延聚丙烯(CPP)，胶层为水胶；或者，掩膜的基膜为单向拉伸聚丙烯(OPP)，胶层为油胶；或者，掩膜的基膜为双向拉伸聚丙烯(BOPP)，胶层为热熔胶；或者，掩膜的基膜为聚乙烯(PE)，胶层为天然橡胶；或者，掩膜的基膜为聚酯纤维(PET)，胶层为合成橡胶；或者，掩膜的基膜为聚氯乙烯(PVC)，胶层为水胶；或者，掩膜的基膜为延聚丙烯(CPP)和单向拉伸聚丙烯(OPP)的组合物，胶层的材质为天然橡胶和合成橡胶的组合物等。并不局限于本实施例所列举的掩膜组成形式。
由于基膜和胶层均选用成本较低的材质，且基膜的材质具有较高的耐冲击性，机械性质强韧，抗多种有机溶剂和酸碱腐蚀，满足了掩膜了使用要求，不容易发生腐蚀损坏。且掩膜具有一定的支撑强度和方便分离的功能，可以粘贴固定于膜层上，能够承受低温沉积工艺，且掩膜在激光进行图案化时不切断，在放置掩膜时，由于掩膜有一定的硬度，方便掩膜图案与膜层的精确对位，通过第一掩膜700做的第一区域101上的三层结构、通 过第二掩膜800做的第二区域上的三层结构、隔离区域103的宽度误差能够达到±0.05μm。
在本实施例中，第一掩膜700和第二掩膜800的厚度为2μm-40μm。根据掩膜需求，选择合适厚度的掩膜，具体可以为2μm、3μm、5μm、10μm、15μm、20μm、25μm、30μm、35μm、40μm。
在本实施例中，第一电极501和第二电极502的材质可以为银、镍、铝、锡、铜中的一种或多种组合。
在本实施例中，第一掩膜700和第二掩膜800的剥离采用热解分离、紫外光照射分离、机械分离中的一种或多种组合。根据掩膜的胶层的不同选择合适的剥离方式。第一掩膜700和第二掩膜800通过这些方式能够容易和方便地从膜层表面撕膜。当然，如果撕膜后，存在残留掩膜，可以通过清洗工序进行清洗处理。
如图7-图12所示，本发明实施例提供了一种具体的背接触式硅异质结太阳能电池的制作过程：
第一步：以n型晶体硅片为硅衬底为例进行说明，对n型晶体硅片(n-c-Si)进行表面制绒清洗以形成金字塔结构和除其表面污染杂质。具体的，硅衬底10为n型双面抛光的直拉单晶硅片，厚度为180μm，电阻率为0.3Ω·cm，少子寿命1000μs。使用2％NaOH和异丙醇溶液(IPA)的混合溶液进行硅片单面或双面制绒，温度为83℃。然后，采用RCA标准清洗方法对硅片进行表面清洗，清除表面污染杂质。接下来，用1％的氢氟酸溶液去除表面氧化层。如果是双面制绒，则在背光面完成制绒清洗后，对背光面进行抛光处理。如果是单面制绒，则可以在入光面制绒，而背光面不制绒。
第二步：如图7所示，在n型晶体硅片的背光面通过CVD方法沉积5nm-10nm本征i-a-Si:H薄膜层(即第一钝化层201)，其中，本征i-a-Si:H薄膜层，通过反应气体SiH 4和H 2沉积制得，其中H 2/SiH 4＝3/1，电源功率密度为0.020W/cm 2，压力为70Pa，衬底温度为200℃。
第三步：如图7所示，将已经激光图案化的第一掩膜700层压粘贴固定于背光面的第一钝化层201上，且第一掩膜700遮挡P区和隔离区域，露出N区。当然，也可以遮挡N区和隔离区域，露出P区。第一掩膜700的基膜 材质为单向拉伸聚丙烯(OPP)，胶层的材质为合成橡胶。第一掩膜700的厚度为5μm。
第四步：如图8所示，在N区通过CVD方法沉积2nm-50nm的n型a-Si:H掺杂层(即第一掺杂层301)，具体可以为5nm～10nm。其中，n型a-Si:H掺杂层通过反应气体SiH 4、H 2和PH 3沉积制得，其中H 2/SiH 4＝5，PH 3/SiH 4＝0.03。电源功率密度为0.027W/cm 2，压力为100Pa，衬底温度为200℃。
第五步：如图8所示，在N区的第一掺杂层表面通过PVD方法沉积40nm～200nm的ITO层(第一透明导电层401)，具体可以为80nm。向PVD沉积设备中充入Ar和O 2，O 2/Ar＝0.025，压力0.5Pa，硅衬底温度为室温。
第六步：如图8所示，在N区的第一透明导电层401表面通过PVD方法沉积3μm～30μm的第一电极501，材料可以为铜、铝等。
第七步：如图9所示，将第一掩膜700撕掉，完成N区的膜层的制备。
第八步：如图10所示，将已经激光图案化的第二掩膜800层压粘贴固定于第一电极501和隔离区域103上，遮挡已经做好的N区和隔离区域103，露出P区。第二掩膜800的基膜材质为单向拉伸聚丙烯(OPP)，胶层的材质为合成橡胶。第二掩膜800的厚度为5μm。
第九步：如图11所示，在P区通过CVD方法沉积2nm-50nm的P型a-Si:H掺杂层(即第二掺杂层302)，具体可以为5nm～10nm。其中，P型a-Si:H掺杂层，通过反应气体SiH 4、H 2和B 2H 6，其中H 2/SiH 4＝5，B 2H 6/SiH 4＝0.02。电源功率密度为0.027W/cm 2，压力为70Pa，衬底温度为200℃。
第十步：如图11所示，在P区的第二掺杂层表面通过PVD方法沉积40nm～200nm的ITO层(第二透明导电层402)，具体可以为80nm。向PVD沉积设备中充入Ar和O 2，O 2/Ar＝0.025，压力0.5Pa，硅衬底温度为室温。
第十一步：如图11所示，在P区的第二透明导电层402表面通过PVD方法沉积3μm～30μm的第二电极502，材料可以为铜、铝等。
第十二步：如图12所示，将第二掩膜800撕掉，完成P区的膜层的制备，P区和N区天然隔离。
如图13所示，基底100的第二表面，即入光面形成的第二钝化层202 和减反层600可以在第二步中同时完成，第二钝化层202与第一钝化层201的工艺可以相同，减反层600为氮化硅减反层。
基于以上任一实施例所描述的制备方法，本发明实施例还提供一种背接触式硅异质结太阳能电池，采用如以上任一实施例所描述的制备方法制备得到。由于该背接触式硅异质结太阳能电池采用本申请中的制备方法得到，因此具有与制备方法相同的技术效果，在此不再赘述。
如图6所示，在本实施例中，本发明还提供一种背接触式硅异质结太阳能电池，包括：
基底100，基底100的第一表面具有第一区域101、第二区域102和隔离区域103，通过隔离区域103间隔第一区域101和第二区域102；
位于第一区域101的第一掺杂层301；
位于第一掺杂层301表面的第一电极501，第一电极501在第一表面的投影与第一掺杂层301在第一表面的投影重合；
位于第二区域102的第二掺杂层302，第一掺杂层301和第二掺杂层302的导电类型不同；
位于第二掺杂层302表面的第二电极502，第二电极502在第一表面的投影与第二掺杂层302在第一表面的投影重合。
由上述技术方案可知，第一区域101上层叠形成的第一掺杂层301和第一电极501，与第二区域102上层叠形成的第二掺杂层302和第二电极502通过隔离区域103隔离，且第一掺杂层301和第一电极501在第一表面的投影重合，第二掺杂层302和第二电极502在第一表面的投影重合，即电极完全覆盖了掺杂层的表面，电极与掺杂层的宽度相等，相比于现有的电极通过丝网印刷而成，电极的宽度小于掺杂层，本申请中的电极宽度更大，增大了载流子的纵向传输至电极的面积，光电转化效率更高。
如图12所示，进一步地，在本实施例中，背接触式硅异质结太阳能电池还包括位于基底100的第一表面的第一钝化层201。第一掺杂层和第二掺杂层位于第一钝化层远离基底的表面。通过第一钝化层201减少基底100的界面缺陷，进而减少由于缺陷导致的载流子的复合，提高光电转换效率。
作为优化，第一钝化层201为本征非晶硅层或本征微晶硅层。通过本征非晶硅层和本征微晶硅层，可以有效地将悬挂键氢化并降低表面缺陷，从 而显著提高少子寿命，增加开路电压，最终提高光电转换效率。
如图12所示，进一步地，在本实施例中，背接触式硅异质结太阳能电池还包括：
位于第一掺杂层301和第一电极501之间的第一透明导电层401，第一透明导电层401在第一表面的投影与第一掺杂层301在第一表面的投影重合；和/或，
位于第二掺杂层302和第二电极502之间的第二透明导电层402，第二透明导电层402在第一表面的投影与第二掺杂层302在第一表面的投影重合。
采用上述技术方案的情况下，第一电极501与第一掺杂层301之间通过第一透明导电层401导电连接，第二电极502与第二掺杂层302之间通过第二透明导电层402导电连接。由于掺杂层的电子与空穴迁徙率较低，且横向导电性较差，不利于光生载流子的收集。因此通过透明导电层纵向收集载流子并向电极传输，透明导电层同时可以减少光学反射，且电极与透明导电层接触相比于电极与掺杂层接触更容易实现欧姆接触，从而提高了导电效率。
且第一区域101的第一掺杂层301、第一透明导电层401和第一电极501在第一表面上的投影尺寸一致，第二区域102的第二掺杂层302、第二透明导电层402和第二电极502在第一表面上的投影尺寸一致。如此，提高了载流子的纵向传输，提高了光电转化效率。
进一步地，在本实施例中，第一掺杂层301与第二掺杂层302的厚度相同或不同；第一透明导电层401与第二透明导电层402的厚度相同或不同；第一电极501与第二电极502的厚度相同或不同。
采用上述技术方案的情况下，由于在第一区域101上形成的第一掺杂层301、第一透明导电层401和第一电极501与在第二区域102上形成的第二掺杂层302、第二透明导电层402和第二电极502相互独立，可以根据工艺和功能需要，独立调整第一区域101和第二区域102各膜层的厚度和参数。
如图13所示，进一步地，背接触式硅异质结太阳能电池还包括：
位于基底100的第二表面的第二钝化层202，第二表面与第一表面相背设置；
位于第二钝化层202表面的减反层600。
采用上述技术方案的情况下，使得基底100的第二表面具有较好的钝化效果和减反射效果。
在本实施例中，P区宽度为400μm～600μm；N区宽度为300μm～500μm；隔离区域的宽度为70μm-120μm。其中，宽度表示在平行于第一表面的平面内，且由P区指向N区的方向上的尺寸。具体地，P区宽度可以为400μm、450μm、500μm、550μm、600μm等；N区宽度为300μm、350μm、400μm、450μm、500μm等；隔离区域的宽度为70μm、80μm、90μm、100μm、110μm、120μm等。根据工艺需要选择合适的宽度，在此并不做具体限定。
本申请提供的背接触式硅异质结太阳能电池的详细描述可参见本申请制备方法中的描述，并不做赘述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若 干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (17)

  1. 一种背接触式硅异质结太阳能电池的制备方法，其特征在于，包括：
    提供一基底，所述基底的第一表面具有第一区域、第二区域和隔离区域，通过所述隔离区域间隔所述第一区域和所述第二区域；
    在所述基底上固定第一掩膜，所述第一掩膜覆盖所述第二区域和所述隔离区域，使所述第一区域裸露；
    在所述第一区域先后形成层叠的第一掺杂层和第一电极；
    剥离所述第一掩膜；
    在所述第一电极裸露的表面固定第二掩膜，所述第二掩膜覆盖所述第一电极和所述隔离区域，使所述第二区域裸露；
    在所述第二区域先后形成层叠的第二掺杂层和第二电极，所述第一掺杂层和所述第二掺杂层的导电类型不同；
    剥离所述第二掩膜，其中，所述第一掩膜和所述第二掩膜均为聚合物胶带。
  2. 根据权利要求1所述的制备方法，其特征在于，在所述第一区域形成第一掺杂层之后，且形成第一电极之前，还包括步骤：在所述第一掺杂层上形成第一透明导电层；和/或，
    在所述第二区域形成第二掺杂层之后，且形成第二电极之前，还包括步骤：在所述第二掺杂层上形成第二透明导电层。
  3. 根据权利要求2所述的制备方法，其特征在于，通过物理气相沉积方法和化学气相沉积方法中的一种或多种沉积形成所述第一掺杂层、所述第一电极、所述第二掺杂层、所述第二电极、所述第一透明导电层和所述第二透明导电层。
  4. 根据权利要求3所述的制备方法，其特征在于，通过化学气相沉积方法形成所述第一掺杂层、所述第二掺杂层；通过物理气相沉积方法形成所述第一透明导电层、第二透明导电层、第一电极和所述第二电极。
  5. 根据权利要求2所述的制备方法，其特征在于，所述第一掺杂层和所述第二掺杂层为掺杂非晶硅层或掺杂微晶硅层，所述第一掺杂层和所述第二掺杂层的厚度为2nm-50nm；和/或，
    所述第一透明导电层和所述第二透明导电层为掺锡氧化铟层、掺钨氧化铟层、掺铝氧化锌层或掺镓氧化锌层，所述第一透明导电层和所述第二透明导电层的厚度为40nm～200nm；和/或，
    所述第一电极和所述第二电极的材质为银、镍、铝、锡、铜中的一种或多种组合，所述第一电极和所述第二电极的厚度为3μm～30μm。
  6. 根据权利要求2所述的制备方法，其特征在于，所述第一掺杂层与所述第二掺杂层的厚度相同或不同；
    所述第一透明导电层与所述第二透明导电层的厚度相同或不同；
    所述第一电极与所述第二电极的厚度相同或不同。
  7. 根据权利要求1所述的制备方法，其特征在于，在提供一基底之后，且在所述基底上固定第一掩膜之前，还包括步骤：在所述基底的第一表面形成第一钝化层。
  8. 根据权利要求7所述的制备方法，其特征在于，所述第一钝化层为本征非晶硅层或本征微晶硅层。
  9. 根据权利要求1～8任一项所述的制备方法，其特征在于，所述第一掩膜和所述第二掩膜均具有基膜和胶层，所述基膜的材质为延聚丙烯、单向拉伸聚丙烯、双向拉伸聚丙烯、聚乙烯、聚酯纤维、聚氯乙烯、聚对苯二甲酸乙二酯、聚烯烃、聚酰亚胺中的一种或多种组合；所述胶层的材质为水胶、油胶、热熔胶、天然橡胶、合成橡胶、硅胶、亚克力胶、聚异丁烯、和聚氨酯中的一种或多种组合；
    所述第一掩膜和所述第二掩膜的厚度为2μm-40μm。
  10. 根据权利要求1所述的制备方法，其特征在于，所述第一掩膜和所述第二掩膜的剥离采用热解分离、紫外光照射分离、机械分离中的一种或多种组合。
  11. 一种背接触式硅异质结太阳能电池，其特征在于，采用如权利要求1-10任一项所述的制备方法制备得到。
  12. 一种背接触式硅异质结太阳能电池，其特征在于，包括：
    基底，所述基底的第一表面具有第一区域、第二区域和隔离区域，通过所述隔离区域间隔所述第一区域和所述第二区域；
    位于所述第一区域的第一掺杂层；
    位于所述第一掺杂层表面的第一电极，所述第一电极在所述第一表面的投影与所述第一掺杂层在所述第一表面的投影重合；
    位于所述第二区域的第二掺杂层，所述第一掺杂层和所述第二掺杂层的导电类型不同；
    位于所述第二掺杂层表面的第二电极，所述第二电极在所述第一表面的 投影与所述第二掺杂层在所述第一表面的投影重合。
  13. 根据权利要求12所述的背接触式硅异质结太阳能电池，其特征在于，还包括位于所述基底的第一表面的第一钝化层；所述第一掺杂层和所述第二掺杂层位于所述第一钝化层远离所述基底的表面。
  14. 根据权利要求13所述的背接触式硅异质结太阳能电池，其特征在于，所述第一钝化层为本征非晶硅层或本征微晶硅层。
  15. 根据权利要求12所述的背接触式硅异质结太阳能电池，其特征在于，还包括：
    位于所述第一掺杂层和所述第一电极之间的第一透明导电层，所述第一透明导电层在所述第一表面的投影与所述第一掺杂层在所述第一表面的投影重合；和/或，
    位于所述第二掺杂层和所述第二电极之间的第二透明导电层，所述第二透明导电层在所述第一表面的投影与所述第二掺杂层在所述第一表面的投影重合。
  16. 根据权利要求15所述的背接触式硅异质结太阳能电池，其特征在于，所述第一掺杂层与所述第二掺杂层的厚度相同或不同；
    所述第一透明导电层与所述第二透明导电层的厚度相同或不同；
    所述第一电极与所述第二电极的厚度相同或不同。
  17. 根据权利要求12-16任一项所述的背接触式硅异质结太阳能电池，其特征在于，还包括：
    位于所述基底的第二表面的第二钝化层，所述第二表面与所述第一表面相背设置；
    位于所述第二钝化层表面的减反层。
PCT/CN2022/126485 2022-01-07 2022-10-20 一种背接触式硅异质结太阳能电池及其制备方法 WO2023130803A1 (zh)

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