WO2023130796A1 - 编码配置的方法和装置 - Google Patents

编码配置的方法和装置 Download PDF

Info

Publication number
WO2023130796A1
WO2023130796A1 PCT/CN2022/125641 CN2022125641W WO2023130796A1 WO 2023130796 A1 WO2023130796 A1 WO 2023130796A1 CN 2022125641 W CN2022125641 W CN 2022125641W WO 2023130796 A1 WO2023130796 A1 WO 2023130796A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
sequence
error correction
forward error
mother code
Prior art date
Application number
PCT/CN2022/125641
Other languages
English (en)
French (fr)
Inventor
吴徐明
罗成先
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023130796A1 publication Critical patent/WO2023130796A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0028—Formatting
    • H04L1/003—Adaptive formatting arrangements particular to signalling, e.g. variable amount of bits

Definitions

  • the present application relates to the field of optical communication, and more particularly, to a method and device for encoding configuration.
  • ONU optical network units
  • OLT optical line terminal
  • FEC forward error correction
  • OSNR optical signal-to-noise ratio
  • the FEC coding method is defined between the OLT and the ONU based on the maximum possible link loss, and a unified FEC coding is used.
  • some ONUs have a large link loss to the OLT, and some ONUs have a small link loss to the OLT.
  • FEC coding is usually expensive or complicated. , will cause a certain amount of waste.
  • the present application provides a coding configuration method and device, which are helpful to realize flexible configuration of forward error correction code word information.
  • a method for encoding configuration includes: the optical network unit receives first information, and the first information is used to indicate the change amount of the forward error correction codeword information relative to the first forward error correction mother code; the optical network unit determines the forward error correction code according to the first information. Wrong word information.
  • the technical solution provided by this application helps to realize the flexible configuration of the FEC codeword information by indicating the change amount of the FEC codeword information relative to the first FEC mother code.
  • the above method before receiving the first information, further includes: the optical network unit sends capability report information, and the capability report information is used to indicate the forward correction supported by the optical network unit
  • the error mother code, the forward error correction mother code supported by the optical network unit includes the first forward error correction mother code.
  • the optical line terminal determines the first FEC mother code among the FEC mother codes supported by the optical network unit, and can process the first FEC mother code, so as to determine the Forward error correction codeword information of the optical network unit. Furthermore, the codeword information defined by the standard is not required, which helps to realize the flexible configuration of the forward error correction codeword information.
  • the above method before sending the capability report information, the above method further includes: the optical network unit receives capability query information, and the capability query information is used to query the forward correction supported by the optical network unit Wrong parent code.
  • the first information includes second information
  • the second information indicates that the payload information of the forward error correction codeword information is relative to the first forward error correction codeword information through a bit sequence.
  • the change amount of the payload information of the mother code is a bit sequence.
  • the bit sequence of the second information includes the first sequence, and the value of the first sequence is 0, which is used to represent the first forward error correction corresponding to the first sequence
  • the 256 or 128 bits of the mother code are truncated; at this time, the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 1, which is used to represent the first forward sequence corresponding to the second sequence
  • the 256 or 128 bits of the error correction mother code are not truncated.
  • the bit sequence of the second information includes the first sequence, and the value corresponding to the first sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are truncated;
  • the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are not truncated. short handle.
  • one bit of the bit sequence corresponds to one column (half column) of the mother code matrix, and corresponds to 256 (128) bits of code word information of the mother code.
  • the first information further includes third information, and the third information indicates that the check bit information of the forward error correction codeword information is relative to the first forward error correction codeword information through a bit sequence.
  • the change amount of the check information of the wrong mother code is a bit sequence.
  • the bit sequence of the third information includes a third sequence, and the value corresponding to the third sequence is 0, which is used to indicate that the first FEC corresponding to the third sequence
  • the 256 or 128 bits of the wrong mother code are punctured; at this time, the bit sequence of the third information can also include the fourth sequence, and the value corresponding to the fourth sequence is 1, which is used to represent the first sequence corresponding to the fourth sequence.
  • the 256 or 128 bits of the FEC mother code are not punctured.
  • the bit sequence of the third information includes a third sequence, and the value corresponding to the third sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the third sequence are punctured;
  • the bit sequence of the third information may also include a fourth sequence, and the value corresponding to the fourth sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the fourth sequence are not modified. Hole punching.
  • the specific forward error correction codeword information is represented by a bit sequence, and the first forward error correction mother code can be processed in units of one column or a half column of the encoded matrix to obtain the forward error correction codeword information.
  • the error codeword information helps to realize the flexible configuration of the forward error correction codeword information.
  • the first information includes a first value, indicating that the payload information of the first forward error correction mother code is truncated according to the first order, and the Mth bit is obtained.
  • M is obtained by multiplying the first value by 256 or 128.
  • the first information includes a second value indicating that the check bit information of the first forward error correction mother code is obtained by puncturing N bits in a second order
  • the check bit information of the forward error correction codeword information, N is obtained by multiplying the second value by 256 or 128.
  • the technical solution of the present application uses numerical values to represent the processing of the mother code matrix corresponding to the first forward error correction mother code to obtain specific forward error correction codeword information, which helps to realize the forward error correction codeword information Flexible configuration.
  • first order and/or the second order include from back to front or from front to back.
  • the first information further includes fourth information, and the first
  • the fourth information is used to indicate that the first information takes effect.
  • the first information is carried in a first message, and the first message includes at least one of the following: a physical layer operation management and maintenance PLOAM message, an optical network terminal management control interface OMCI message, and an operation management and maintenance OAM message.
  • a method for encoding configuration Including: the optical line terminal determines the first information, the first information is used to indicate the change amount of the forward error correction codeword information relative to the first forward error correction mother code, the optical line terminal sends the first information to the optical network unit, wherein , the first information is used by the optical network unit to determine forward error correction codeword information.
  • the technical solution provided by this application helps to realize the flexible configuration of the FEC codeword information by indicating the change amount of the FEC codeword information relative to the first FEC mother code.
  • the above method before sending the first information, further includes: the optical line terminal receives capability report information, and the capability report information is used to indicate the forward correction supported by the optical network unit.
  • the optical line terminal receives capability report information
  • the capability report information is used to indicate the forward correction supported by the optical network unit.
  • Error mother code the FEC mother code supported by the optical network unit includes the first FEC mother code.
  • the optical line terminal determines the first FEC mother code among the FEC mother codes supported by the optical network unit, and can process the first FEC mother code, so as to determine the Forward error correction codeword information of the optical network unit. Furthermore, the codeword information defined by the standard is not required, which helps to realize the flexible configuration of the forward error correction codeword information.
  • the above method before receiving the capability report information, the above method further includes: the optical line terminal sends capability query information, and the capability query information is used to query the forward correction information supported by the optical network unit. Wrong parent code.
  • the first information includes second information
  • the second information indicates that the payload information of the forward error correction codeword information is relative to the first forward error correction codeword information through a bit sequence.
  • the change amount of the payload information of the mother code is a bit sequence.
  • the bit sequence of the second information includes the first sequence, and the value of the first sequence is 0, which is used to represent the first forward error correction corresponding to the first sequence
  • the 256 or 128 bits of the mother code are truncated; at this time, the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 1, which is used to represent the first forward sequence corresponding to the second sequence
  • the 256 or 128 bits of the error correction mother code are not truncated.
  • the bit sequence of the second information includes the first sequence, and the value corresponding to the first sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are truncated;
  • the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are not truncated. short handle.
  • one bit of the bit sequence corresponds to one column (half column) of the mother code matrix, and corresponds to 256 (128) bits of code word information of the mother code.
  • the first information further includes third information, and the third information indicates that the check bit information of the forward error correction codeword information is relative to the first forward error correction codeword information through a bit sequence.
  • the bit sequence of the third information includes a third sequence, and the value corresponding to the third sequence is 0, which is used to indicate that the first FEC corresponding to the third sequence
  • the 256 or 128 bits of the wrong mother code are punctured; at this time, the bit sequence of the third information can also include the fourth sequence, and the value corresponding to the fourth sequence is 1, which is used to represent the first sequence corresponding to the fourth sequence.
  • the 256 or 128 bits of the FEC mother code are not punctured.
  • the bit sequence of the third information includes a fourth sequence, and the value corresponding to the fourth sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the fourth sequence are punctured;
  • the bit sequence of the third information may also include a fourth sequence, and the value corresponding to the fourth sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the fourth sequence are not modified. Hole punching.
  • the specific forward error correction codeword information is represented by a bit sequence, and the first forward error correction mother code can be processed in units of one column or a half column of the encoded matrix to obtain the forward error correction codeword information.
  • the error codeword information helps to realize the flexible configuration of the forward error correction codeword information.
  • the first information includes a first value, indicating that the payload information of the first forward error correction mother code is truncated according to the first order, and the Mth bit is obtained.
  • M is obtained by multiplying the first value by 256 or 128.
  • the first information includes a second value indicating that the check bit information of the first forward error correction mother code is obtained by puncturing N bits in a second order
  • the check bit information of the forward error correction codeword information, N is obtained by multiplying the second value by 256 or 128.
  • the technical solution of the present application uses numerical values to represent the processing of the mother code matrix corresponding to the first forward error correction mother code to obtain specific forward error correction codeword information, which helps to realize the forward error correction codeword information Flexible configuration.
  • first order and/or the second order include from back to front or from front to back.
  • the first information further includes fourth information, where the fourth information is used to indicate that the first information takes effect.
  • the first information is carried in a first message, and the first message includes at least one of the following: a physical layer operation management and maintenance PLOAM message, an optical network terminal management control interface OMCI message, and an operation management and maintenance OAM message.
  • an encoding configuration device configured to include: a transceiver unit, configured to receive first information, and the first information is used to indicate the amount of change of forward error correction codeword information relative to the first forward error correction mother code; a processing unit, configured to according to the first A piece of information identifies the forward error correction codeword information.
  • the transceiver unit is also used to send capability report information, and the capability report information is used to indicate the forward error correction mother code supported by the optical network unit, and the optical network unit supports
  • the FEC mother code includes a first FEC mother code.
  • the transceiver unit is further configured to receive capability query information, and the capability query information is used to query the FEC mother code supported by the optical network unit.
  • an encoding configuration device includes: a processing unit, used to determine the first information, and the first information is used to indicate the change amount of the forward error correction code word information relative to the first forward error correction mother code; Send the first information.
  • the transceiver unit is also used to receive capability report information, and the capability report information is used to indicate the forward error correction mother code supported by the optical network unit, and the FEC supported by the optical network unit
  • the FEC mother code includes a first FEC mother code.
  • the transceiver unit is further configured to send capability query information, and the capability query information is used to query the FEC mother code supported by the optical network unit.
  • a communication device including: a processor; the processor is configured to be coupled with a memory, and after reading an instruction in the memory, execute the method according to any one of the above aspects according to the instruction.
  • the communication device may be the optical network unit entity in the above-mentioned first aspect, or a device including the above-mentioned optical network unit entity; or, the communication device may be the optical line terminal entity in the above-mentioned second aspect, or include the above-mentioned optical line terminal Physical device.
  • the communications device further includes a memory, where the memory is configured to store necessary program instructions and data.
  • the communication device is a chip or a chip system.
  • the communication device when it is a system-on-a-chip, it may consist of chips, or may include chips and other discrete devices.
  • a communication device including: a processor and an interface circuit; the interface circuit is used to receive a computer program or instruction and transmit it to the processor; the processor is used to execute the computer program or instruction, so that the communication device performs As in the method of the first aspect or the second aspect above.
  • the communication device is a chip or a chip system.
  • the billing device when it is a system-on-a-chip, it may consist of chips, or may include chips and other discrete devices.
  • a communication system including the optical network unit described in the first aspect and the second aspect, and an optical line terminal.
  • the optical network unit is configured to execute the method described in the first aspect
  • the optical line terminal is configured to execute the method described in the second aspect.
  • a computer program product includes: computer program code, when the computer program code is run on a computer, it causes the computer to execute the methods in the above aspects.
  • a computer-readable medium stores program codes, and when the computer program codes run on a computer, the computer executes the methods in the above aspects.
  • a chip system including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the communication device installed with the chip system executes the above-mentioned Any aspect from the first aspect to the second aspect and a method in a possible implementation thereof.
  • the chip system may include an input chip or interface for sending information or data, and an output chip or interface for receiving information or data.
  • FIG. 1 is a schematic diagram of uplink and downlink transmission in a PON system.
  • Fig. 2 is a schematic diagram of an encoding configuration method provided by an embodiment of the present application.
  • Fig. 3 is a schematic diagram of a specific example of the encoding configuration method provided by the embodiment of the present application.
  • Fig. 4 is a schematic diagram of indicating forward error correction codeword information through a bit sequence provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of forward error correction codeword information indicated by numerical values provided by an embodiment of the present application.
  • Fig. 6 is a schematic diagram of an encoding configuration device provided by an embodiment of the present application.
  • Fig. 7 is a schematic diagram of an encoding configuration device provided by an embodiment of the present application.
  • FTTH fiber to the home
  • OLT central office
  • ONU user
  • a passive optical network wherein, when sending and receiving data, the downlink direction of the PON network is broadcast, and the uplink direction is unicast.
  • FIG. 1 shows a schematic diagram of uplink and downlink transmission in a PON system.
  • the 1-channel signal sent by the OLT is divided into N channels through the splitter (Splitter) and sent to all ONUs at the same time.
  • the ONU selectively receives the downlink data with the same ID number as itself, and discards other data.
  • TDM time division multiplexing
  • TDM requires the OLT to measure the distance between it and each ONU and then carry out strict sending timing for each ONU.
  • Each ONU obtains timing information from the downlink signal sent by the OLT, and sends an uplink packet signal in the time slot specified by the OLT, thereby avoiding ONUs. conflicts between.
  • the PON based on this principle is called Time Division Multiplexing - Passive Optical Network (TDM-PON).
  • the transmission distance from different ONUs to the OLT or the optical splitters passed through are different, so the link loss between different ONUs and the OLT will also be different.
  • FEC technology is used to solve the link loss and transmission cost introduced by optical splitter and optical fiber transmission. This technology can greatly reduce the OSNR tolerance of the receiving end and reduce the bit error rate and transmission power by adding redundant error correction codes to the transmission code sequence. At the same time, this technology can effectively improve the channel of optical fiber signal transmission. The signal will always produce various types of distortion and non-isochronous delay during the transmission process of various media. The final result can be reflected in the bit error rate and jitter of the signal.
  • FEC technology can solve the problem of fiber dispersion, signal attenuation, channel noise, and inter-fiber communication in long-distance, ultra-long-distance, and large-capacity dense wavelength division multiplexing (DWDM) optical fiber communication systems. Interference, greatly reducing the performance between the various systems.
  • DWDM dense wavelength division multiplexing
  • Reed-Solomon (Reed-solomon, RS) coded FEC is used.
  • the encoding method of low density parity check (low density parity check, LDPC) is selected.
  • Different FEC coding methods have different performances and implementation costs, and complex FEC coding methods can often bring more coding benefits. In the same encoding method, introducing more overhead can also bring greater encoding benefits.
  • the FEC coding method is defined between the OLT and the ONU based on the maximum possible link loss, and a unified FEC coding is used.
  • some ONUs have a large link loss to the OLT, and some ONUs have a small link loss to the OLT.
  • FEC coding is usually expensive or complicated. , will cause a certain amount of waste.
  • the present application proposes a coding configuration method and device, in order to realize flexible configuration of forward error correction (FEC) codeword information.
  • FEC forward error correction
  • FIG. 2 shows a schematic diagram of a coding configuration method provided by an embodiment of the present application.
  • the optical network unit 120 receives first information, where the first information is used to indicate a change amount of FEC codeword information relative to the first FEC mother code.
  • the first information is determined by the optical line terminal 110, wherein the optical line terminal 110 can determine the forward error correction codeword information suitable for the optical network unit 120 according to the signal quality and transmission power of the optical network unit 120. And in the form of the first information, it indicates the variable of the FEC codeword information relative to the first FEC mother code, so that the optical network unit 120 can accurately know the FEC codeword information.
  • the optical network unit 120 may send capability report information to the optical line terminal 110, the capability report information is used to indicate the forward error correction mother code supported by the optical network unit 120, and the forward error correction code supported by the optical network unit 120.
  • the mother code for forward error correction includes a first mother code for forward error correction.
  • the optical line terminal 110 determines the first FEC mother code among the FEC mother codes supported by the ONU 120, and can process the first FEC mother code, so as to determine the FEC mother code suitable for the ONU 120.
  • Forward error correction codeword information Furthermore, the codeword information defined by the standard is not required, which helps to realize the flexible configuration of the forward error correction codeword information.
  • the ONU 120 may receive capability query information sent by the OLT 110, where the capability query information is used to query the FEC mother codes supported by the ONU 120.
  • the first information is carried in a first message, and the first message includes at least one of the following: a physical layer operation management and maintenance PLOAM message, an optical network terminal management control interface OMCI message, and an operation management and maintenance OAM message.
  • the optical network unit 120 determines forward error correction codeword information according to the first information.
  • the first information may include second information, and the second information indicates the difference between the payload information of the forward error correction codeword information and the payload information of the first forward error correction mother code through a bit sequence. The amount of change.
  • the bit sequence of the second information includes the first sequence, and the value of the first sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the first sequence are truncated;
  • the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are not truncated deal with.
  • the bit sequence of the second information includes the first sequence, and the value corresponding to the first sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are truncated;
  • the bit sequence of the second information may also include a second sequence, and the value of the second sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the second sequence are not truncated. short handle.
  • one bit of the bit sequence corresponds to one column (half column) of the mother code matrix, and corresponds to 256 (128) bits of code word information of the mother code.
  • the first information may further include third information, and the third information indicates a change amount of the check bit information of the FEC codeword information relative to the check information of the first FEC mother code through a bit sequence.
  • the bit sequence of the third information includes a third sequence, and the value corresponding to the third sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the third sequence are punctured;
  • the bit sequence of the third information may also include a fourth sequence, and the value corresponding to the fourth sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the fourth sequence are not modified. Hole punching.
  • the bit sequence of the third information includes a third sequence, and the value corresponding to the third sequence is 1, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the third sequence are punctured;
  • the bit sequence of the third information may also include a fourth sequence, and the value corresponding to the fourth sequence is 0, which is used to indicate that the 256 or 128 bits of the first forward error correction mother code corresponding to the fourth sequence are not modified. Hole punching.
  • the specific forward error correction codeword information is represented by a bit sequence, and the first forward error correction mother code can be processed in units of one column or a half column of the encoded matrix to obtain the forward error correction codeword information.
  • the error codeword information helps to realize the flexible configuration of the forward error correction codeword information.
  • the first information may include a first value, which is used to indicate that the payload information of the first forward error correction mother code is truncated by M bits in a first order to obtain the forward error correction code
  • the payload information of the word information, M is obtained by multiplying the first value by 256 or 128.
  • the first information may also include a second value, indicating that the check bit information of the first FEC mother code is punctured in a second order to obtain N bits of the check bit information of the FEC codeword information, N is obtained by multiplying the second value by 256 or 128.
  • first order and/or the second order include from back to front or from front to back.
  • the technical solution of the present application uses numerical values to represent the processing of the mother code matrix corresponding to the first forward error correction mother code to obtain specific forward error correction codeword information, which helps to realize the forward error correction codeword information Flexible configuration.
  • the first information may further include fourth information, where the fourth information is used to indicate that the first information takes effect.
  • the technical solution provided by this application helps to realize the flexible configuration of the FEC codeword information by indicating the change amount of the FEC codeword information relative to the first FEC mother code.
  • Fig. 3 shows a schematic diagram of a specific example of the encoding configuration method provided by the embodiment of the present application.
  • the ONU 120 receives capability query information sent by the OLT 110.
  • the capability query information is used to query the FEC mother code supported by the optical network unit 120 .
  • the capability query information may be carried in a first message, and the first message includes at least one of the following: a physical layer operation management and maintenance PLOAM message, an optical network terminal management control interface OMCI message, and an operation management and maintenance OAM message.
  • the capability query information when carried in the PLOAM message, its specific form and content can be shown in Table 1 below. Among them, the bold font part "FEC capability query" is used to indicate that the optical line terminal 110 queries or inquires about the type of forward error correction mother code supported by the optical network unit 120.
  • the optical network unit 120 sends capability report information.
  • the capability report information when carried in the PLOAM message, its specific form may be as shown in Table 2 and Table 3 below. Among them, the bold font part "FEC code Capability" is used to indicate the type of forward error correction mother code supported by the optical network unit 120.
  • the FEC master codes supported by the ONU 120 include LDPC.
  • the ONU 120 supports truncation and puncturing of the FEC mother code.
  • the optical line terminal 110 determines first information, where the first information is used to indicate a change amount of the FEC codeword information relative to the first FEC mother code.
  • the FEC codeword information includes payload information and parity bit information.
  • the first information may indicate a change amount of the FEC codeword information relative to the first FEC mother code in the form of a bit sequence and/or a value.
  • a 12*69 coding matrix is used in 50G PON.
  • the columns of the matrix are usually cut in units of 1 column or half a column.
  • the default codeword LDPC(17280, 14592) uses the first 57 columns + 12 columns of the matrix during encoding. Wherein, according to the difference of the content of the first information, it can be divided into the following four situations.
  • the payload part and the check bit part of the forward error correction codeword information are indicated by a bit sequence.
  • the above-mentioned first information may include the second information and the third information at the same time.
  • the second information indicates the change amount of the payload information of the FEC codeword information relative to the payload information of the first FEC mother code through a bit sequence.
  • the third information indicates the change amount of the check bit information of the FEC codeword information relative to the check information of the first FEC mother code through a bit sequence.
  • the forward error correction codeword information configured for the optical network unit 120 is represented by a bit sequence.
  • the first information when carried in the PLOAM message, its specific form may be as shown in Table 4 below.
  • the bold font "FEC capability set” indicates that the message configures forward error correction codeword information for the optical network unit 120
  • the bold font "FEC code selection” indicates that the message includes a bit sequence.
  • the 12*69 mother code matrix has 69 columns in total, 57 columns of which are payload information, and 12 columns are check bit information.
  • bit sequence A as an example to represent forward error correction codeword information
  • one column of the mother code matrix corresponds to 256 bits of codeword information, and corresponds to one bit of bit sequence A.
  • bit sequence A includes bit sequence A1 and bit sequence A2
  • bit sequence A includes 69 bits
  • bit sequence A1 includes 57 bits
  • bit sequence A2 includes 12 bits.
  • the bit sequence A1 is used to represent the change amount of the payload information of the forward error correction codeword information relative to the payload information of the first forward error correction mother code
  • the bit sequence A2 is used to represent the verification of the forward error correction codeword information
  • the second information is bit sequence A1
  • the third information is bit sequence A2.
  • the bit sequence A1 includes the first sequence (for example, the first column and the second column), and the value of the first sequence is 0, which is used to represent the 256 bits of the first forward error correction mother code corresponding to the first sequence. Truncated.
  • the bit sequence A1 also includes a second sequence (such as the 3rd column to the 57th column), and the value of the second sequence is 0, which is used to represent the 256 bits of the first FEC mother code corresponding to the second sequence Bits are not truncated.
  • the change amount of the payload information of the forward error correction codeword information relative to the payload information of the first mother forward error correction code is indicated by the bit sequence A1.
  • the optical network unit 120 can perform truncation processing on the payload information of the first forward error correction mother code according to the instruction of the bit sequence, so as to obtain the optical network unit 120 Payload information of the configured FEC codeword information.
  • the bit sequence A2 includes a third sequence (for example, the penultimate column to the penultimate column), and the value corresponding to the third sequence is 0, which is used to indicate that the first FEC corresponding to the third sequence
  • the 256 bits of the wrong mother code are punctured.
  • the bit sequence A2 also includes a fourth sequence (for example, the penultimate column to the penultimate 12th column), and the value corresponding to the fourth sequence is 1, which is used to represent the first forward error correction matrix corresponding to the fourth sequence
  • the 256 bits of the code are not punctured. In this way, the change amount of the parity bit information of the FEC codeword information relative to the parity bit information of the first FEC mother code is indicated by the bit sequence A2.
  • the optical network unit 120 After receiving the third information (that is, the bit sequence A2), the optical network unit 120 can perform puncturing processing on the check bit information of the first forward error correction mother code according to the indication of the bit sequence, so as to obtain the optical network unit Check bit information of the FEC codeword information configured at 120 .
  • bit sequence B to represent forward error correction codeword information
  • bit sequence B includes bit sequence B1 and bit sequence B2.
  • the 256 or 128 bits of the first forward error correction mother code corresponding to the sequence can be truncated or punctured by setting the value corresponding to the sequence to 0, or Setting the value corresponding to the sequence to 1 indicates that the 256 or 128 bits of the first FEC mother code corresponding to the sequence are truncated or punctured, which is not limited in this application.
  • the priority order of truncation can be truncated from the last column. For example, to truncate 3 columns, truncate from the 57th column, and then truncate the 57th, 56th, and 55th columns in sequence.
  • punching holes you can punch holes in the priority order of the 59th column, the 60th column, the 61st column, the 62nd column, the 67th column.
  • the specific forward error correction codeword information is represented by a bit sequence, and the first forward error correction mother code can be processed in units of one column or half column of the encoded matrix, Obtaining the forward error correction codeword information helps to realize the flexible configuration of the forward error correction codeword information.
  • the above-mentioned first information may include a first value and a second value at the same time, and the first value is used to indicate that the payload information of the first forward error correction mother code is truncated in the first order by the Mth bit to obtain the previous Payload information to error correction codeword information.
  • the second value is used to indicate that the check bit information of the first FEC mother code is punctured by N bits in a second order to obtain the check bit information of the FEC codeword information.
  • M is obtained by multiplying the first value by 256 or 128, and N is obtained by multiplying the second value by 256 or 128.
  • the first information when the first information is carried in the PLOAM message, its specific form may be as shown in Table 5 below.
  • the bold font "FEC capability set” indicates that the message is for configuring forward error correction codeword information for the optical network unit 120
  • the bold font "Shortened columns number” indicates the first value
  • the bold font "Punctured columns number” indicates the first value binary value.
  • the 12*69 mother code matrix has 69 columns in total, 57 columns of which are payload information, and 12 columns are check bit information.
  • one column of the mother code matrix corresponds to 256 bits of codeword information, and corresponds to one bit of the first value.
  • the first value is 3 and the first order is from back to front, it means that the payload information of the first FEC mother code is truncated from back to front to obtain the FEC code
  • the optical network unit 120 can process the payload information of the first FEC mother code to obtain the payload information of the FEC codeword information.
  • the optical network unit 120 can process the parity bit information of the first FEC mother code to obtain the parity bit information of the FEC codeword information.
  • half columns of the mother code matrix correspond to 128 bits of codeword information, and correspond to one bit of the first value.
  • the first value is 3 and the first order is from back to front, it means that the payload information of the first FEC mother code is truncated from back to front to obtain the FEC code The payload information of word information.
  • the optical network unit 120 can process the payload information of the first FEC mother code to obtain the payload information of the FEC codeword information.
  • the optical network unit 120 can process the check bit information of the first FEC mother code to obtain the check bit information of the FEC codeword information.
  • the first order and/or the second order may include from back to front or from front to back.
  • the first sequence and the second sequence may be the same or different.
  • the first order and/or the second order may also be an order specified according to negotiation or agreement, for example, starting from a middle column, etc., which is not limited in this application.
  • the first order and/or the second order may be continuous, for example, when the first value is 3, three consecutive columns (or half columns) are processed.
  • the first order and/or the second order may also be discontinuous. For example, when the first value is 3, according to the order stipulated in the negotiation or agreement, the processing may be performed in the order of odd columns or even columns, etc., This application does not limit it.
  • the priority order of truncation can be truncated from the last column. For example, to truncate 3 columns, truncate from the 57th column, and then truncate the 57th, 56th, and 55th columns in sequence.
  • punching holes you can punch holes in the priority order of the 59th column, the 60th column, the 61st column, the 62nd column, the 67th column.
  • the half-column when used as a unit, there are 57*2 possibilities for the payload part, and 12*2 possibilities for the check digit.
  • the payload part uses at least 7 bits, and the parity bit can be represented by 5 bits, which helps to reduce signaling overhead and save transmission resources.
  • the codeword in order to ensure the validity of the codeword, generally not all columns are punctured or truncated, but only some columns can be punctured or truncated. For example, only 32 columns can be truncated at most, and 8 columns can be punched. Then, when the semi-column is used as a unit, only 6 bits are needed to represent the payload part, and 4 bits are used to represent the check part, which can further reduce signaling overhead and save transmission resources.
  • the mother code matrix corresponding to the first forward error correction mother code is processed by numerical value, and the specific forward error correction code word information is obtained, which is helpful to realize forward error correction Flexible configuration of codeword information.
  • the payload part of the forward error correction codeword information is indicated by a bit sequence, and the check bit part of the forward error correction codeword information is indicated by a numerical value.
  • the above-mentioned first information may include the second information and the second value at the same time.
  • the second information indicates the change amount of the payload information of the FEC codeword information relative to the payload information of the first FEC mother code through a bit sequence.
  • the second value is used to indicate that the check bit information of the first FEC mother code is punctured by N bits in a second order to obtain the check bit information of the FEC codeword information.
  • N is obtained by multiplying the second value by 256 or 128.
  • the second information includes a bit sequence A1.
  • the check bit part can be indicated with 5 bits in numerical representation.
  • the payload information of the forward error correction codeword information is represented by a bit sequence
  • the check bit information of the forward error correction codeword information is represented by a value, which can be expressed as a column of the encoded matrix or semicolumn as a unit to process the first FEC mother code to obtain FEC codeword information, which helps to realize flexible configuration of FEC codeword information.
  • the payload part of the forward error correction codeword information is indicated by a numerical value, and the check bit part of the forward error correction codeword information is indicated by a bit sequence.
  • the above-mentioned first information may include the third information and the first value at the same time.
  • the first value is used to indicate that the payload information of the first FEC mother code is truncated in a first order to obtain the payload information of the FEC codeword information.
  • M is obtained by multiplying the first value by 256 or 128.
  • the third information indicates the change amount of the check bit information of the FEC codeword information relative to the check information of the first FEC mother code through a bit sequence. For example, when the column is used as a unit, the payload part is represented by 7 bits, the third information includes bit sequence A2, and bit sequence A2 includes 12 bits.
  • the payload information of the forward error correction codeword information is represented by a numerical value
  • the check bit information of the forward error correction codeword information is represented by a bit sequence, which can be expressed as a column of the encoded matrix or semicolumn as a unit to process the first FEC mother code to obtain FEC codeword information, which helps to realize flexible configuration of FEC codeword information.
  • the OLT 110 sends the first information to the ONU 120.
  • the first information is carried in a first message, and the first message includes at least one of the following: a physical layer operation management and maintenance PLOAM message, an optical network terminal management control interface OMCI message, and an operation management and maintenance OAM message.
  • the optical network unit 120 determines forward error correction codeword information according to the first information.
  • the optical network unit 120 according to the content of the first information, according to the bit sequence and/or value, takes one column or half column of the encoding matrix as a unit, and performs the first forward error correction mother code Processing is performed to obtain forward error correction codeword information.
  • the technical solution provided by this application helps to realize the flexible configuration of the FEC codeword information by indicating the change amount of the FEC codeword information relative to the first FEC mother code.
  • sequence numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.
  • the method implemented by the communication device may also be implemented by a component (such as a chip or a circuit) that can be configured inside the communication device.
  • each device includes a corresponding hardware structure and/or software module for performing each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the device for encoding configuration provided by the embodiment of the present application will be described in detail with reference to FIG. 6 and FIG. 7 . It should be understood that the descriptions of the device embodiments correspond to the descriptions of the method embodiments. Therefore, for content that is not described in detail, reference may be made to the method embodiments above. For brevity, some content will not be repeated here.
  • the embodiment of the present application can divide the functional modules of the transmitting end device or the receiving end device according to the above method example, for example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module middle.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation. In the following, description will be made by taking the division of each functional module corresponding to each function as an example.
  • FIG. 6 shows a schematic structural diagram of an example of a device configured for encoding in the present application.
  • Any device involved in any one of methods 200 to 400 above, such as an optical line terminal, an optical network unit, etc., can be implemented by the device with the encoding configuration shown in FIG. 6 .
  • the coded configured device 600 may be a physical device, or a component of the physical device (for example, an integrated circuit, a chip, etc.), or a functional module in the physical device.
  • the device 600 of the encoding configuration includes: one or more processors 610 .
  • the processor 610 may store execution instructions for executing the methods of the embodiments of the present application.
  • the processor 610 may call an interface to implement receiving and sending functions.
  • the interface may be a logical interface or a physical interface, which is not limited.
  • the interface may be a transceiver circuit, or an interface circuit.
  • the transceiver circuits or interface circuits for realizing the functions of receiving and sending can be separated or integrated together.
  • the above-mentioned transceiver circuit or interface circuit can be used for reading and writing code/data, or the above-mentioned transceiver circuit or interface circuit can be used for signal transmission or transfer.
  • the interface can be implemented through a transceiver.
  • the device 600 configured with encoding may further include a transceiver 630 .
  • the transceiver 630 may be called a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., and is used to implement a transceiver function.
  • the device 600 configured for encoding may further include a memory 620 .
  • the embodiment of the present application does not specifically limit the specific deployment location of the memory 620, and the memory may be integrated in the processor, or may be independent of the processor.
  • the device 600 configured with encoding does not include a memory, it is only necessary that the device 600 configured with encoding has a processing function, and the memory may be deployed in another location (eg, a cloud system).
  • the processor 610, the memory 620 and the transceiver 630 communicate with each other through internal connection paths, and transmit control and/or data signals.
  • the encoding-configured device 600 may also include other devices, such as an input device, an output device, a battery, and the like.
  • the memory 620 may store execution instructions for executing the methods of the embodiments of the present application.
  • the processor 610 can execute the instructions stored in the memory 620 in conjunction with other hardware (such as the transceiver 630 ) to complete the steps performed by the method shown below.
  • other hardware such as the transceiver 630
  • the method disclosed in the embodiment of the present application may be applied to the processor 610 or implemented by the processor 610 .
  • the processor 610 may be an integrated circuit chip with signal processing capabilities.
  • each step of the method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software.
  • the above-mentioned processor can be a general-purpose processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) or other available Program logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in random access memory (random access memory, RAM), flash memory, read-only memory (read-only memory, ROM), programmable read-only memory or electrically erasable programmable memory, registers, etc. in the storage medium.
  • the storage medium is located in the memory, and the processor reads the instructions in the memory, and completes the steps of the above method in combination with its hardware.
  • memory 620 can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
  • the non-volatile memory can be read-only memory ROM, programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory RAM, which acts as external cache memory.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM direct memory bus random access memory
  • direct rambus RAM direct rambus RAM
  • FIG. 7 shows a schematic structural diagram of an example of a device configured for encoding in the present application.
  • the specific form of the encoding configuration apparatus 700 may be a general computer device or a chip in a general computer device, which is not limited in this embodiment of the present application.
  • the device configured for encoding includes a processing unit 710 and a transceiver unit 720 .
  • the encoding configured device 700 may be any device involved in the present application, and may realize the functions that the device can realize. It should be understood that the encoding configuration apparatus 700 may be a physical device, or a component of a physical device (for example, an integrated circuit, a chip, etc.), or a functional module in a physical device.
  • the encoding configuration device 700 may be the optical line terminal in the above method embodiment, or may be a chip for realizing the function of the optical line terminal in the above method embodiment.
  • the processing unit 710 is configured to determine the first information, and the first information is used to indicate the change amount of the forward error correction codeword information relative to the first forward error correction mother code; the transceiver unit 720 is used to send the optical network unit Send the first information.
  • the transceiver unit 720 is also used to receive capability report information, and the capability report information is used to indicate the FEC master code supported by the optical network unit, and the FEC master code supported by the optical network unit includes the first forward error correction master code Error correction mother code.
  • the transceiver unit 720 is also configured to send capability query information, and the capability query information is used to query the FEC mother code supported by the optical network unit.
  • the transceiver unit 720 in the coding configuration device 700 can be implemented through a communication interface (such as a transceiver or an input/output interface), and the coding configuration device 700
  • the processing unit 710 in may be implemented by at least one processor, for example, may correspond to the processor 610 shown in FIG. 6 .
  • the apparatus 700 for encoding configuration may further include a storage unit, which may be used to store instructions or data, and the processing unit may call the instructions or data stored in the storage unit to implement corresponding operations.
  • a storage unit which may be used to store instructions or data
  • the processing unit may call the instructions or data stored in the storage unit to implement corresponding operations.
  • the coding configuration device 700 may be the optical network unit device in the above method embodiment, or may be a chip for realizing the function of the optical network unit in the above method embodiment.
  • the transceiver unit 720 is configured to receive first information, and the first information is used to indicate the change amount of the forward error correction codeword information relative to the first forward error correction mother code; the processing unit 710 is configured to A piece of information identifies the forward error correction codeword information.
  • the transceiver unit 720 is also used to send capability report information, and the capability report information is used to indicate the forward error correction master code supported by the optical network unit, and the forward error correction master code supported by the optical network unit includes the first forward error correction master code Error correction mother code.
  • the transceiver unit 720 is also configured to receive capability query information, and the capability query information is used to query the FEC mother code supported by the optical network unit.
  • the transceiver unit 720 in the encoding configuration device 700 can be implemented through a communication interface (such as a transceiver or an input/output interface), for example, it can correspond to FIG. 6
  • the communication interface 630 shown in , the processing unit 710 in the apparatus 700 of the encoding configuration may be implemented by at least one processor, for example, may correspond to the processor 610 shown in FIG. 6 .
  • the apparatus 700 for encoding configuration may further include a storage unit, which may be used to store instructions or data, and the processing unit may call the instructions or data stored in the storage unit to implement corresponding operations.
  • a storage unit which may be used to store instructions or data
  • the processing unit may call the instructions or data stored in the storage unit to implement corresponding operations.
  • the device 700 can also be used to implement the functions of the optical line terminal and the optical network unit in the above method embodiments, wherein the transceiver unit 720 can be used to implement operations related to receiving and sending, and the processing unit 710 can be used to implement For other operations except receiving and sending, refer to the descriptions in the foregoing method embodiments for details, and will not be listed here one by one.
  • the device 700 configured with encoding is presented in the form of a functional module.
  • the "module” here may refer to an application-specific integrated circuit ASIC, a circuit, a processor and memory executing one or more software or firmware programs, an integrated logic circuit, and/or other devices that can provide the above-mentioned functions.
  • the device 700 may take the form shown in FIG. 7 .
  • the processing unit 710 may be implemented by the processor 610 shown in FIG. 6 .
  • the processing unit 710 may be implemented by the processor 610 and the memory 620 .
  • the transceiver unit 720 may be implemented by the transceiver 630 shown in FIG. 6 .
  • the transceiver 630 includes a receiving function and a sending function.
  • the processor is implemented by executing computer programs stored in the memory.
  • the function and/or implementation process of the transceiver unit 720 may also be implemented through pins or circuits.
  • the memory may be a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip in the computer device, as shown in FIG. 6
  • the memory 620 alternatively, may also be a storage unit deployed in other systems or devices, not in the computer device.
  • Computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or tapes, etc.), optical disks (e.g., compact discs (compact discs, CDs), digital versatile discs (digital versatile discs, DVDs), etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), card, stick or key drive, etc.).
  • magnetic storage devices e.g., hard disks, floppy disks, or tapes, etc.
  • optical disks e.g., compact discs (compact discs, CDs), digital versatile discs (digital versatile discs, DVDs), etc.
  • smart cards and flash memory devices for example, erasable programmable read-only memory (EPROM), card, stick or key drive, etc.
  • various storage media described herein can represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing and/or carrying instructions and/or data.
  • the present application also provides a computer program product, the computer program product including: computer program code, when the computer program code is run on the computer, the computer is made to execute the computer program shown in Fig. 2 through Fig. 3 .
  • the method of any one of the embodiments is illustrated.
  • the present application also provides a computer-readable medium, the computer-readable medium stores program code, and when the program code is run on the computer, the computer is made to execute the computer shown in Figure 2 or Figure 3.
  • the method of any one of the embodiments is illustrated.
  • the present application further provides a system, which includes the foregoing apparatus or equipment.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (for example, a solid state disk (solid state disc, SSD)) etc.
  • a magnetic medium for example, a floppy disk, a hard disk, a magnetic tape
  • an optical medium for example, a high-density digital video disc (digital video disc, DVD)
  • a semiconductor medium for example, a solid state disk (solid state disc, SSD)
  • a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and the computing device can be components.
  • One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on a signal having one or more packets of data (e.g., data from two components interacting with another component between a local system, a distributed system, and/or a network, such as the Internet via a signal interacting with other systems). Communicate through local and/or remote processes.
  • packets of data e.g., data from two components interacting with another component between a local system, a distributed system, and/or a network, such as the Internet via a signal interacting with other systems.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Optical Communication System (AREA)

Abstract

本申请提供了一种编码配置的方法和装置。该方法包括：光网络单元接收第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；光网络单元根据第一信息确定所述前向纠错码字信息。根据本申请提供的技术方案，通过指示前向纠错码字信息相对于第一前向纠错母码的改变量，有助于实现前向纠错码字信息的灵活配置。

Description

编码配置的方法和装置
本申请要求于2022年1月7日提交中国国家知识产权局、申请号202210015997.2、申请名称为“编码配置的方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光通信领域，并且更具体地，涉及一种编码配置的方法和装置。
背景技术
在无源光网络(passive optical network，PON)系统中，不同光网络单元(optical network unit，ONU)到光线路终端(optical line termination，OLT)的传输距离或者经过分光器的不同，因此不同ONU与OLT之间的链路损耗也会不同。前向纠错(forward error correction，FEC)被用来解决因分光器及光纤传输引入的链路损耗及传输代价。该技术可以通过在传输码列中加入冗余纠错码，可以大幅度降低接收端的光信噪比(optical signal-to-noise ratio，OSNR)容限，减少误码率和发射功率。
当前，为了保证传输性能，OLT和ONU之间会基于最大可能的链路损耗定义FEC编码方式，并且使用统一的FEC编码。通常情况，在某个的PON系统中有的ONU到OLT的链路损耗大，有的ONU到OLT的链路损耗小。对于链路损耗小的ONU，其不需要纠错能力很强的FEC编码，但是也需要使用与链路损耗大的ONU相同的FEC编码方式，而这样的FEC编码通常开销比较大或者编码比较复杂，会造成一定的浪费。
因此，亟需一种编码配置的方法，能够实现前向纠错FEC码字信息的灵活配置。
发明内容
本申请提供一种编码配置的方法和装置，有助于实现前向纠错码字信息的灵活配置。
第一方面，提供了一种编码配置的方法。包括：光网络单元接收第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；光网络单元根据第一信息确定所述前向纠错码字信息。
本申请提供的技术方案，通过指示前向纠错码字信息相对于第一前向纠错母码的改变量，有助于实现前向纠错码字信息的灵活配置。
结合第一方面，在第一方面的某些实现方式中，在接收第一信息之前，上述方法还包括：光网络单元发送能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括所述第一前向纠错母码。
本申请提供的技术方案，光线路终端在光网络单元支持的前向纠错母码中确定第一前向纠错母码，能够对第一前向纠错母码进行处理，从而确定适合该光网络单元的前向纠错码字信息。进一步地，无需标准定义的码字信息，有助于实现前向纠错码字信息的灵活配置。
结合第一方面，在第一方面的某些实现方式中，在发送能力上报信息之前，上述方法还包括：光网络单元接收能力查询信息，能力查询信息用于查询光网络单元支持的前向纠错母码。
结合第一方面，在第一方面的另一些实现方式中，第一信息包括第二信息，第二信息通过比特序列指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。
结合第一方面，在第一方面的另一些实现方式中，第二信息的比特序列包括第一序列，第一序列的值为0，用于表示对第一序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。或者，第二信息的比特序列包括第一序列，第一序列对应的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为0，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。
其中，比特序列的一个比特，对应母码矩阵的一列(半列)，对应母码码字信息的256(128)个比特。
结合第一方面，在第一方面的另一些实现方式中，第一信息还包括第三信息，第三信息通过比特序列指示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。
结合第一方面，在第一方面的另一些实现方式中，第三信息的比特序列包括第三序列，第三序列对应的值为0，用于表示对第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为1，用于表示对第四序列对应的第一前向纠错母码的256或128个比特不进行打孔处理。或者，第三信息的比特序列包括第三序列，第三序列对应的值为1，用于表示对第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为0，用于表示对第四序列对应的第一前向纠错母码的256或128个比特不进行打孔处理。
本申请的技术方案，通过比特序列来表示具体的前向纠错码字信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
结合第一方面，在第一方面的又一些实现方式中，第一信息包括第一数值，指示对第一前向纠错母码的净荷信息按照第一顺序截短第M个比特，得到前向纠错码字信息的净荷信息，M由第一数值乘以256或128得到。
结合第一方面，在第一方面的又一些实现方式中，所述第一信息包括第二数值，指示对第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到前向纠错码字信息的检验位信息，N由第二数值乘以256或128得到。
本申请的技术方案，通过数值来表示对第一前向纠错母码对应的母码矩阵进行处理，得到具体的前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
其中，第一顺序和/或第二顺序包括从后到前或从前到后。
结合第一方面，在第一方面的某些实现方式中，第一信息还包括第四信息，所述第
四信息用于指示所述第一信息生效。
其中，第一信息承载于第一消息，所述第一消息包括以下至少一种：物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
第二方面，提供了一种编码配置的方法。包括：光线路终端确定第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量，光线路终端向光网络单元发送第一信息，其中，第一信息用于光网络单元确定前向纠错码字信息。
本申请提供的技术方案，通过指示前向纠错码字信息相对于第一前向纠错母码的改变量，有助于实现前向纠错码字信息的灵活配置。
结合第二方面，在第二方面的某些实现方式中，在发送第一信息之前，上述方法还包括：光线路终端接收能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括第一前向纠错母码。
本申请提供的技术方案，光线路终端在光网络单元支持的前向纠错母码中确定第一前向纠错母码，能够对第一前向纠错母码进行处理，从而确定适合该光网络单元的前向纠错码字信息。进一步地，无需标准定义的码字信息，有助于实现前向纠错码字信息的灵活配置。
结合第二方面，在第二方面的某些实现方式中，在接收能力上报信息之前，上述方法还包括：光线路终端发送能力查询信息，能力查询信息用于查询光网络单元支持的前向纠错母码。
结合第二方面，在第二方面的另一些实现方式中，第一信息包括第二信息，第二信息通过比特序列指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。
结合第二方面，在第二方面的另一些实现方式中，第二信息的比特序列包括第一序列，第一序列的值为0，用于表示对第一序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。或者，第二信息的比特序列包括第一序列，第一序列对应的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为0，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。
其中，比特序列的一个比特，对应母码矩阵的一列(半列)，对应母码码字信息的256(128)个比特。
结合第二方面，在第二方面的另一些实现方式中，第一信息还包括第三信息，第三信息通过比特序列指示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。
结合第二方面，在第二方面的另一些实现方式中，第三信息的比特序列包括第三序列，第三序列对应的值为0，用于表示对第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为1，用于表示对第四序列对应的第一前向纠错母码的256或128个比特不进行打孔处。或者，第三信息的比特序列包括第四序列，第四序列对应的值为1，用于表示对第四序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为0，用于表示对第四序列对应的第一前向纠错母码的256或128 个比特不进行打孔处理。
本申请的技术方案，通过比特序列来表示具体的前向纠错码字信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
结合第二方面，在第二方面的又一些实现方式中，第一信息包括第一数值，指示对第一前向纠错母码的净荷信息按照第一顺序截短第M个比特，得到前向纠错码字信息的净荷信息，M由第一数值乘以256或128得到。
结合第二方面，在第二方面的又一些实现方式中，所述第一信息包括第二数值，指示对第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到前向纠错码字信息的检验位信息，N由第二数值乘以256或128得到。
本申请的技术方案，通过数值来表示对第一前向纠错母码对应的母码矩阵进行处理，得到具体的前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
其中，第一顺序和/或第二顺序包括从后到前或从前到后。
结合第二方面，在第二方面的某些实现方式中，第一信息还包括第四信息，所述第四信息用于指示所述第一信息生效。
其中，第一信息承载于第一消息，所述第一消息包括以下至少一种：物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
第三方面，提供了一种编码配置的装置。该装置包括：收发单元，用于接收第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；处理单元，用于根据所述第一信息确定所述前向纠错码字信息。
结合第三方面，在第三方面的某些实现方式中，收发单元，还用于发送能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括第一前向纠错母码。
结合第三方面，在第三方面的某些实现方式中，收发单元，还用于接收能力查询信息，能力查询信息用于查询光网络单元支持的前向纠错母码。
第四方面，提供了一种编码配置的装置。该装置包括：处理单元，用于确定第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；收发单元，用于向光网络单元发送所述第一信息。
结合第四方面，在第四方面的某些实现方式中，收发单元，还用于接收能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括第一前向纠错母码。
结合第四方面，在第四方面的某些实现方式中，收发单元，还用于发送能力查询信息，能力查询信息用于查询光网络单元支持的前向纠错母码。
第五方面，提供了一种通信装置包括：处理器；该处理器用于与存储器耦合，并读取存储器中的指令之后，根据该指令执行如上述任一方面所述的方法。该通信装置可以为上述第一方面中的光网络单元实体，或者包含上述光网络单元实体的装置；或者，该通信装置可以为上述第二方面中的光线路终端实体，或者包含上述光线路终端实体的装置。
结合上述第五方面，在一种可能的实现方式中，该通信装置还包括存储器，该存储器，用于保存必要的程序指令和数据。
结合上述第五方面，在一种可能的实现方式中，该通信装置为芯片或芯片系统。可选的，该通信装置是芯片系统时，可以由芯片构成，也可以包含芯片和其他分立器件。
第六方面，提供了一种通信装置，包括：处理器和接口电路；接口电路，用于接收计算机程序或指令并传输至处理器；处理器用于执行计算机程序或指令，以使该通信装置执行如上述第一方面或第二方面的方法。
结合上述第六方面，在一种可能的实现方式中，该通信装置为芯片或芯片系统。可选的，该用于计费的装置是芯片系统时，可以由芯片构成，也可以包含芯片和其他分立器件。
第七方面，提供了一种通信系统，包括上述第一方面以及第二方面所述的光网络单元，以及光线路终端。
其中，光网络单元用于执行第一方面所述的方法，光线路终端用于执行第二方面所述的方法。
第八方面，提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述各方面中的方法。
需要说明的是，上述计算机程序代码可以全部或者部分存储在第一存储介质上，其中第一存储介质可以与处理器封装在一起的，也可以与处理器单独封装，本申请实施例对此不作具体限定。
第九方面，提供了一种计算机可读介质，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述各方面中的方法。
第十方面，提供了一种芯片系统，包括存储器和处理器，该存储器用于存储计算机程序，该处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片系统的通信设备执行上述第一方面至第二方面中的任意方面及其可能实现方式中的方法。
其中，该芯片系统可以包括用于发送信息或数据的输入芯片或者接口，以及用于接收信息或数据的输出芯片或者接口。
附图说明
图1是一种PON系统上下行传输的示意图。
图2是本申请实施例提供的编码配置方法的示意图。
图3是本申请实施例提供的编码配置方法的具体示例的示意图。
图4是本申请实施例提供的通过比特序列指示前向纠错码字信息的示意图。
图5是本申请实施例提供的通过数值指示前向纠错码字信息的示意图。
图6是本申请实施例提供的编码配置设备的示意图。
图7是本申请实施例提供的编码配置装置的示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
随着电信业务的日益丰富，用户对带宽的需求也越来越大，国内和世界各国运营商已将光纤到户场景(fiber to the home，FTTH)作为接入网的必然选择，FTTH使用PON系统已成为主流选择。在PON网络中，这种接入技术使得接入网的局端(OLT)与用户(ONU)之间只需光纤、光分路器等光无源器件，不需租用机房和配备电源，因此被称为无源光网络。其中， 在发送和接收数据时，PON网络的下行方向是广播的，上行方向是单播的。
图1示出了一种PON系统上下行传输的示意图。
如图1所示，在下行传输时，将OLT下发的1路信号通过分光器(Splitter)分成N路同时送给所有的ONU，ONU选择性接收和自身ID编号相同下行数据，丢弃其他的数据。
上行时，将N路ONU进来的光信号采用时分复用技术(time division multiplexing，TDM)组合成一路光信号组。其原理是将上行传输时间分为若干时隙Ti(i＝1，2，3，……32，……)，在每个时隙内只安排一个ONU以分组的方式向OLT发送分组信息，各ONU按OLT规定的顺序依次发送。TDM要求OLT测定它与各ONU的距离后对各ONU进行严格的发送定时，各ONU从OLT发送的下行信号获取定时信息，并在OLT规定的时隙内发送上行分组信号，从而避免各ONU之间产生冲突。基于这种原理的PON被成为时分复用-无源光网络(TDM-PON)。
在PON系统中，不同ONU到OLT的传输距离或者经过的分光器不同，因此不同ONU与OLT之间的链路损耗也会不同。FEC技术被用来解决因分光器及光纤传输引入的链路损耗及传输代价。该技术可以通过在传输码列中加入冗余纠错码，可以大幅度降低接收端的OSNR容限，减少误码率和发射功率。同时，该技术可以有效的提高光纤信号传输的信道，信号在各个媒体传输过程中总会产生各类型的畸变和非等时时延，对于信号产生误码率和抖动都可以将最终的结果反映在系统误码率上、FEC技术能够解决长距离、超长距离、大容量密集波分复用(dense wavelength division multiplexing，DWDM)光纤通信系统的光纤色散、信号衰减、信道噪声以及多根光纤之间的干扰，大大的降低了各个系统之间的性能。
在10G PON中，使用了里德-所罗门(Reed-solomon，RS)编码的FEC。而在50G PON中选择了低密度奇偶校验(low density parity check，LDPC)的编码方式。不同的FEC编码方式的性能和实现代价是不同的，复杂的FEC编码方式往往能够带来更多的编码收益。同样的编码方式，引入更多的开销也可以带来更大的编码收益。
当前，为了保证传输性能，OLT和ONU之间会基于最大可能的链路损耗定义FEC编码方式，并且使用统一的FEC编码。通常情况，在某个的PON系统中有的ONU到OLT的链路损耗大，有的ONU到OLT的链路损耗小。对于链路损耗小的ONU，其不需要纠错能力很强的FEC编码，但是也需要使用与链路损耗大的ONU相同的FEC编码方式，而这样的FEC编码通常开销比较大或者编码比较复杂，会造成一定的浪费。
基于此，本申请提出了一种编码配置的方法和装置，以期望能够实现前向纠错FEC码字信息的灵活配置。下面以光线路终端110和光网络单元120的交互为例，对本申请的技术方案进行详细介绍。
图2示出了本申请实施例提供的编码配置方法的示意图。
S210，光网络单元120接收第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量。
该第一信息由光线路终端110确定，其中，光线路终端110可以根据光网络单元120的信号质量、发送功率等确定适合该光网络单元120的前向纠错码字信息。并通过第一信息的形式，指示该前向纠错码字信息相对于第一前向纠错母码的该变量，从而使得光网络单元120可以准确获知该前向纠错码字信息。
其中，在接收第一信息之前，光网络单元120可以向光线路终端110发送能力上报信息， 能力上报信息用于指示光网络单元120支持的前向纠错母码，光网络单元120支持的前向纠错母码包括第一前向纠错母码。
这样，光线路终端110在光网络单元120支持的前向纠错母码中确定第一前向纠错母码，能够对第一前向纠错母码进行处理，从而确定适合光网络单元120的前向纠错码字信息。进一步地，无需标准定义的码字信息，有助于实现前向纠错码字信息的灵活配置。
可选的，在发送能力上报信息之前，光网络单元120可以接收光线路终端110发送的能力查询信息，能力查询信息用于查询光网络单元120支持的前向纠错母码。
其中，第一信息承载于第一消息，所述第一消息包括以下至少一种：物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
S220，光网络单元120根据第一信息确定前向纠错码字信息。
作为一种可能的实现方式，第一信息可以包括第二信息，第二信息通过比特序列指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。
其中，第二信息的比特序列包括第一序列，第一序列的值为0，用于表示对第一序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。
或者，第二信息的比特序列包括第一序列，第一序列对应的值为1，用于表示对第二序列对应的第一前向纠错母码的256或128个比特进行截短处理；此时，第二信息的比特序列还可以包括第二序列，第二序列的值为0，用于表示对第二序列对应的第一前向纠错母码的256或128个比特不进行截短处理。
其中，比特序列的一个比特，对应母码矩阵的一列(半列)，对应母码码字信息的256(128)个比特。
可选的，第一信息还可以包括第三信息，第三信息通过比特序列指示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。
其中，第三信息的比特序列包括第三序列，第三序列对应的值为0，用于表示对第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为1，用于表示对第四序列对应的第一前向纠错母码的256或128个比特不进行打孔处理。
或者，第三信息的比特序列包括第三序列，第三序列对应的值为1，用于表示对第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理；此时，第三信息的比特序列还可以包括第四序列，第四序列对应的值为0，用于表示对第四序列对应的第一前向纠错母码的256或128个比特不进行打孔处理。
本申请的技术方案，通过比特序列来表示具体的前向纠错码字信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
作为另一种可能的实现方式，第一信息可以包括第一数值，用于指示对第一前向纠错母码的净荷信息按照第一顺序截短M个比特，得到前向纠错码字信息的净荷信息，M由第一数值乘以256或128得到。
可选的，第一信息还可以包括第二数值，指示对第一前向纠错母码的检验位信息按照第 二顺序打孔N个比特得到前向纠错码字信息的检验位信息，N由第二数值乘以256或128得到。
其中，第一顺序和/或第二顺序包括从后到前或从前到后。
本申请的技术方案，通过数值来表示对第一前向纠错母码对应的母码矩阵进行处理，得到具体的前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
可选的，第一信息还可以包括第四信息，所述第四信息用于指示所述第一信息生效。
本申请提供的技术方案，通过指示前向纠错码字信息相对于第一前向纠错母码的改变量，有助于实现前向纠错码字信息的灵活配置。
图3示出了本申请实施例提供的编码配置方法的具体示例的一例示意图。
S310，光网络单元120接收光线路终端110发送的能力查询信息。
其中，能力查询信息用于查询光网络单元120支持的前向纠错母码。该能力查询信息可以承载于第一消息，所述第一消息包括以下至少一种：物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
作为示例而非限定，当能力查询信息承载于PLOAM消息时，其具体形式和内容可以入下表1所示。其中，加粗字体部分“FEC capability query”用于表示光线路终端110查询或询问光网络单元120支持的前向纠错母码的类型。
表1 能力查询信息的形式和内容
Figure PCTCN2022125641-appb-000001
S320，光网络单元120发送能力上报信息。
作为示例而非限定，当能力上报信息承载于PLOAM消息时，其具体形式可以如下表2和表3所示。其中，加粗字体部分“FEC code Capability”用于表示光网络单元120支持的前向纠错母码的类型。在表2中，光网络单元120支持的前向纠错母码包括LDPC。在表3中，光网络单元120支持对前向纠错FEC母码进行截短和打孔。
表2 能力上报信息的形式和内容
Figure PCTCN2022125641-appb-000002
Figure PCTCN2022125641-appb-000003
表3 能力上报信息的形式和内容
Figure PCTCN2022125641-appb-000004
S330，光线路终端110确定第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量。
前向纠错码字信息包括净荷信息和校验位信息。在本申请实施例中，第一信息可以通过比特序列和/或数值的方式来指示前向纠错码字信息相对于第一前向纠错母码的改变量。在50G PON中使用的是12*69的编码矩阵，在基于该编码矩阵生成新的码字结构时，通常是以1列或者半列为单位，对矩阵的列进行裁剪。如图4所示，默认码字LDPC(17280，14592)在编码时就使用了该矩阵的前57列+12列。其中，根据第一信息内容的不同，可以分为以下四个情形。
情形1：
通过比特序列指示前向纠错码字信息的净荷部分和校验位部分。
具体的，上述第一信息可以同时包括第二信息和第三信息。第二信息通过比特序列指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。第三信息通过比特序列指示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。这样，即通过比特序列来表示为光网络单元120配置的前向纠错码字信息。
作为示例而非限定，当第一信息承载于PLOAM消息时，其具体形式可以如下表4所示。其中，加粗字体“FEC capability set”表示该消息为光网络单元120配置前向纠错码字信息，加粗字体“FEC code selection”表示该消息包括比特序列。
表4 情形1中第一信息的形式和内容
Figure PCTCN2022125641-appb-000005
如图4中所示，12*69的母码矩阵共有69列，其中57列为净荷信息，12列为校验位信息。以通过比特序列A表示前向纠错码字信息为例，母码矩阵的1列对应码字信息的256个比特，对应比特序列A的一个比特。其中，比特序列A包括比特序列A1和比特序列A2，比特序列A包括69个比特，比特序列A1包括57个比特，比特序列A2包括12个比特。比特序列A1用于表示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量，比特序列A2用于表示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。即，第一信息为比特序列A，第二信息为比特序列A1，第三信息为比特序列A2。在比特序列A1中包括第一序列(例如第1列和第2列)，第一序列的值为0，用于表示对第一序列对应的第一前向纠错母码的256个比特进行截短处理。此时，比特序列A1中还包括第二序列(例如第3列至第57列)，第二序列的值为0，用于表示对第二序列对应的第一前向纠错母码的256比特不进行截短处理。这样，即完成了通过比特序列A1指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。光网络单元120在接收到该第二信息(即比特序列A1)后，可以根据比特序列的指示，对第一前向纠错母码的净荷信息进行截短处理，从而得到光网络单元120配置的前向纠错码字信息的净荷信息。在本情形中，在比特序列A2中包括第三序列(例如倒数第1列至倒数第3列)，第三序列对应的值为0，用于表示对第三序列对应的第一前向纠错母码的256个比特进行打孔处理。此时，比特序列A2中还包括第四序列(例如倒数第4列至倒数第12列)，第四序列对应的值为1，用于表示 对第四序列对应的第一前向纠错母码的256个比特不进行打孔处理。这样，即完成了通过比特序列A2指示前向纠错码字信息的校验位信息相对于第一前向纠错母码的校验位信息的改变量。光网络单元120在接收到该第三信息(即比特序列A2)后，可以根据比特序列的指示，对第一前向纠错母码的校验位信息进行打孔处理，从而得到光网络单元120配置的前向纠错码字信息的校验位信息。
对应的，以通过比特序列B表示前向纠错码字信息为例，母码矩阵的半列对应码字信息的128个比特，对应比特序列B的一个比特。其中，比特序列B包括比特序列B1和比特序列B2。与上述比特序列A不同的是，比特序列B包括69*2＝138个比特，比特序列B1包括57*2＝114个比特，比特序列B2包括12*2＝24个比特。其余描述请参考上述关于比特序列A的介绍，在此不再赘述。
应理解，在本申请实施例中，可以通过将序列对应的值置为0表示对该序列对应的第一前向纠错母码的256或128个比特进行截短或打孔处理，也可以通过将序列对应的值置为1表示对该序列对应的第一前向纠错母码的256或128个比特进行截短或打孔处理，本申请对其不做限定。
在该情形中，当以半列为单位时，比特序列最多包括69*2＝138个比特，即使用18个字节(144比特)可以完成指示；当以列为单位时，比特序列最多包括69个比特，即使用9个字节(72比特)可以完成指示，有助于减小信令开销，节省传输资源。
可选地，为了保证码字的有效性，通常不会对所有的列进行打孔和截短，仅能对部分列进行打孔或者截短。例如，最多只能截短32列，打孔8列。则以半列为单位时，比特序列最多包括(32+8)*2＝80个比特，即使用10个字节(80比特)可以完成指示；当以列为单位时，比特序列最多包括32+8＝40个比特，即使用5个字节(40比特)可以完成指示，可以进一步地减小信令开销，节省传输资源。
可选的，截短时的优先级顺序可以是从最末尾的列开始截短。例如，截短3列，则从第57列开始截短，依次截短第57列、第56列以及第55列。打孔时，可以按照第59列、第60列、第61列、第62列、第67列……的优先级顺序进行打孔。
根据情形1中所介绍的技术方案，通过比特序列来表示具体的前向纠错码字信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
情形2：
通过数值指示前向纠错码字信息的净荷部分和校验位部分。
具体的，上述第一信息可以同时包括第一数值和第二数值，第一数值用于指示对第一前向纠错母码的净荷信息按照第一顺序截短第M个比特，得到前向纠错码字信息的净荷信息。第二数值用于指示对第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到前向纠错码字信息的检验位信息。其中，M由第一数值乘以256或128得到，N由第二数值乘以256或128得到。
作为示例而非限定，当第一信息承载于PLOAM消息时，其具体形式可以如下表5所示。其中，加粗字体“FEC capability set”表示该消息为光网络单元120配置前向纠错码字信息，加粗字体“Shortened columns number”表示第一数值，加粗字体“Punctured columns number”表示第二数值。
表5 情形2中第一信息的形式和内容
Figure PCTCN2022125641-appb-000006
如图5中所示，12*69的母码矩阵共有69列，其中57列为净荷信息，12列为校验位信息。
作为一种可能的实现方式，母码矩阵的1列对应码字信息的256个比特，对应第一数值的一个比特。当第一数值为3，第一顺序为从后到前时，则代表对第一前向纠错母码的净荷信息按照从后到前截短第M个比特，得到前向纠错码字信息的净荷信息。其中，M由第一数值乘以256得到，即M＝3*256＝768。这样，光网络单元120在接收到该第一数值后，可以对第一前向纠错母码的净荷信息进行处理，得到前向纠错码字信息的净荷信息。
当第二数值为2，第二顺序为后到前时，则代表对第一前向纠错母码的检验位信息按照从后到前打孔N个比特得到前向纠错码字信息的检验位信息。其中，N由第二数值乘以256得到，即N＝2*256＝512。这样，光网络单元120在接收到该第二数值后，可以对第一前向纠错母码的校验位信息进行处理，得到前向纠错码字信息的校验位信息。
作为另一种可能的实现方式，母码矩阵的半列对应码字信息的128个比特，对应第一数值的一个比特。当第一数值为3，第一顺序为从后到前时，则代表对第一前向纠错母码的净荷信息按照从后到前截短第M个比特，得到前向纠错码字信息的净荷信息。其中，M由第一数值乘以128得到，即M＝3*128＝384。这样，光网络单元120在接收到该第一数值后，可以对第一前向纠错母码的净荷信息进行处理，得到前向纠错码字信息的净荷信息。当第二数值为2，第二顺序为后到前时，则代表对第一前向纠错母码的检验位信息按照从后到前打孔N个比特得到前向纠错码字信息的检验位信息。其中，N由第二数值乘以128得到，即N＝2*128＝256。这样，光网络单元120在接收到该第二数值后，可以对第一前向纠错母码的 校验位信息进行处理，得到前向纠错码字信息的校验位信息。
应理解，在本申请实施例中，第一顺序和/或第二顺序可以包括从后到前或从前到后。其中，第一顺序和第二顺序可以相同，也可以不同。可选的，第一顺序和/或第二顺序还可以是根据协商或者协议规定的顺序，例如从中间某个列开始等，本申请对其不做限定。其中，第一顺序和/或第二顺序可以是连续的，例如，第一数值为3时，对连续3个列(或半列)进行处理。可选的，第一顺序和/或第二顺序还可以是不连续的，例如，第一数值为3时，根据协商或者协议规定的顺序，可以按照奇数列或偶数列的顺序进行处理等，本申请对其不做限定。
可选的，截短时的优先级顺序可以是从最末尾的列开始截短。例如，截短3列，则从第57列开始截短，依次截短第57列、第56列以及第55列。打孔时，可以按照第59列、第60列、第61列、第62列、第67列……的优先级顺序进行打孔。
在该情形中，当以半列为单位，那净荷部分一共57*2种可能，校验位一共有12*2可能。净荷部分最少用7比特，校验位用5比特即可表示，有助于减小信令开销，节省传输资源。
可选地，为了保证码字的有效性，通常不会对所有的列进行打孔和截短，仅能对部分列进行打孔或者截短。例如，最多只能截短32列，打孔8列。则以半列为单位时，只需要用6比特表示净荷部分，4比特表示校验部分，可以进一步地减小信令开销，节省传输资源。
根据情形2中所介绍的技术方案，通过数值来表示对第一前向纠错母码对应的母码矩阵进行处理，得到具体的前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
情形3：
通过比特序列指示前向纠错码字信息的净荷部分，通过数值指示前向纠错码字信息的校验位部分。
具体的，上述第一信息可以同时包括第二信息和第二数值。第二信息通过比特序列指示前向纠错码字信息的净荷信息相对于第一前向纠错母码的净荷信息的改变量。第二数值用于指示对第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到前向纠错码字信息的检验位信息。其中，N由第二数值乘以256或128得到。例如，第二信息包括比特序列A1，当以半列为单位时，比特序列A1包括57*2＝114个比特，此时检验位部分使用数值表示的方式用5比特即可完成指示。
应理解，第二信息和第二数值的具体表示方式及有益效果可参照上述情形1和情形2中的描述，在此不再赘述。
根据情形3中所介绍的技术方案，通过比特序列来表示前向纠错码字信息的净荷信息，通过数值来表示前向纠错码字信息的检验位信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
情形4：
通过数值指示前向纠错码字信息的净荷部分，通过比特序列指示前向纠错码字信息的校验位部分。
具体的，上述第一信息可以同时包括第三信息和第一数值。第一数值用于指示对第一前向纠错母码的净荷信息按照第一顺序截短第M个比特，得到前向纠错码字信息的净荷信息。其中，M由第一数值乘以256或128得到。第三信息通过比特序列指示前向纠错码字信息的检验位信息相对于第一前向纠错母码的检验信息的改变量。例如，当以列为单位时，净荷部 分用7比特表示，第三信息包括比特序列A2，比特序列A2包括12个比特。
应理解，第三信息和第一数值的具体表示方式及有益效果可参照上述情形1和情形2中的描述，在此不再赘述。
根据情形4中所介绍的技术方案，通过数值来表示前向纠错码字信息的净荷信息，通过比特序列来表示前向纠错码字信息的检验位信息，可以以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息，有助于实现前向纠错码字信息的灵活配置。
S340，光线路终端110向光网络单元120发送第一信息。
其中，第一信息承载于第一消息，所述第一消息包括以下至少一种：物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
S350，光网络单元120根据第一信息确定前向纠错码字信息。
具体的，对应于S330中的说明，光网络单元120根据第一信息的内容，根据比特序列和/或数值，以编码的矩阵的一列或半列为单位，对第一前向纠错母码进行处理，得到前向纠错码字信息。
本申请提供的技术方案，通过指示前向纠错码字信息相对于第一前向纠错母码的改变量，有助于实现前向纠错码字信息的灵活配置。
应理解，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
可以理解的是，本申请上述实施例中，由通信设备实现的方法，也可以由可配置于通信设备内部的部件(例如芯片或者电路)实现。
以上，结合图2、图3、图4以及图5详细说明了本申请实施例提供的编码配置的方法。上述编码配置的方法主要从各个网元之间交互的角度进行了介绍。可以理解的是，各个装置，为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
以下，结合图6和图7详细说明本申请实施例提供的编码配置的装置。应理解，装置实施例的描述与方法实施例的描述相互对应，因此，未详细描述的内容可以参见上文方法实施例，为了简洁，部分内容不再赘述。
本申请实施例可以根据上述方法示例对发射端设备或者接收端设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。下面以采用对应各个功能划分各个功能模块为例进行说明。
图6示出了本申请编码配置的设备的一例示意性结构图。上述方法200至方法400中任一方法所涉及的任一设备，如光线路终端、光网络单元等都可以由图6所示的编码配置的设备来实现。
应理解，编码配置的设备600可以是实体设备，也可以是实体设备的部件(例如，集成电路，芯片等等)，还可以是实体设备中的功能模块。
如图6所示，该编码配置的设备600包括：一个或多个处理器610。处理器610可以存储用于执行本申请实施例的方法的执行指令。可选地，处理器610中可以调用接口实现接收和发送功能。所述接口可以是逻辑接口或物理接口，对此不作限定。例如，接口可以是收发电路，或是接口电路。用于实现接收和发送功能的收发电路、或接口电路可以是分开的，也可以集成在一起。上述收发电路或接口电路可以用于代码/数据的读写，或者，上述收发电路或接口电路可以用于信号的传输或传递。
可选地，接口可以通过收发器实现。可选地，该编码配置的设备600还可以包括收发器630。所述收发器630可以称为收发单元、收发机、收发电路或者收发器等，用于实现收发功能。
可选地，该编码配置的设备600还可以包括存储器620。本申请实施例对存储器620的具体部署位置不作具体限定，该存储器可以集成于处理器中，也可以是独立于处理器之外。对于该编码配置的装置600不包括存储器的情形，该编码配置的设备600具备处理功能即可，存储器可以部署在其他位置(如，云系统)。
处理器610、存储器620和收发器630之间通过内部连接通路互相通信，传递控制和/或数据信号。
可以理解的是，尽管并未示出，编码配置的设备600还可以包括其他装置，例如输入装置、输出装置、电池等。
可选的，在一些实施例中，存储器620可以存储用于执行本申请实施例的方法的执行指令。处理器610可以执行存储器620中存储的指令结合其他硬件(例如收发器630)完成下文所示方法执行的步骤，具体工作过程和有益效果可以参见上文方法实施例中的描述。
本申请实施例揭示的方法可以应用于处理器610中，或者由处理器610实现。处理器610可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的指令，结合其硬件完成上述方法的步骤。
可以理解，存储器620可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器ROM、可编程只读存储器 (programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器RAM，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
图7示出了本申请编码配置的装置的一例示意性结构图。
可选地，所述编码配置的装置700的具体形态可以是通用计算机设备或通用计算机设备中的芯片，本申请实施例对此不作限定。如图7所示，该编码配置的装置包括处理单元710和收发单元720。
具体而言，编码配置的装置700可以是本申请涉及的任一装置，并且可以实现该装置所能实现的功能。应理解，编码配置的装置700可以是实体设备，也可以是实体设备的部件(例如，集成电路，芯片等等)，还可以是实体设备中的功能模块。
在一种可能的设计中，该编码配置的装置700可以是上文方法实施例中的光线路终端，也可以是用于实现上文方法实施例中光线路终端的功能的芯片。
例如，处理单元710，用于确定第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；收发单元720，用于向光网络单元发送所述第一信息。
可选的，收发单元720，还用于接收能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括第一前向纠错母码。
可选的，收发单元720，还用于发送能力查询信息，能力查询信息用于查询光网络单元支持的前向纠错母码。
还应理解，该编码配置的装置700为光线路终端设备时，该编码配置的装置700中的收发单元720可通过通信接口(如收发器或输入/输出接口)实现，该编码配置的装置700中的处理单元710可通过至少一个处理器实现，例如可对应于图6中示出的处理器610。
可选地，编码配置的装置700还可以包括存储单元，该存储单元可以用于存储指令或者数据，处理单元可以调用该存储单元中存储的指令或者数据，以实现相应的操作。
应理解，各单元执行上述相应步骤的具体过程在上述方法实施例中已经详细说明，为了简洁，在此不再赘述。
在另一种可能的设计中，该编码配置的装置700可以是上文方法实施例中的光网络单元装置，也可以是用于实现上文方法实施例中光网络单元功能的芯片。
例如，收发单元720，用于接收第一信息，第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；处理单元710，用于根据所述第一信息确定所述前向纠错码字信息。
可选的，收发单元720，还用于发送能力上报信息，能力上报信息用于指示光网络单元支持的前向纠错母码，光网络单元支持的前向纠错母码包括第一前向纠错母码。
可选的，收发单元720，还用于接收能力查询信息，能力查询信息用于查询光网络单元 支持的前向纠错母码。
还应理解，该编码配置的装置700为光网络单元装置时，该编码配置的装置700中的收发单元720可通过通信接口(如收发器或输入/输出接口)实现，例如可对应于图6中示出的通信接口630，该编码配置的装置700中的处理单元710可通过至少一个处理器实现，例如可对应于图6中示出的处理器610。
可选地，编码配置的装置700还可以包括存储单元，该存储单元可以用于存储指令或者数据，处理单元可以调用该存储单元中存储的指令或者数据，以实现相应的操作。
应理解，各单元执行上述相应步骤的具体过程在上述方法实施例中已经详细说明，为了简洁，在此不再赘述。
还应理解，装置700还可以用于实现上述方法实施例中的光线路终端、光网络单元的功能，其中收发单元720可以用于实现与接收和发送相关的操作，处理单元710可以用于实现除接收和发送以外的其他操作，具体可以参见上述方法实施例中的描述，这里不再一一列出。
另外，在本申请中，编码配置的装置700是以功能模块的形式来呈现。这里的“模块”可以指特定应用集成电路ASIC、电路、执行一个或多个软件或固件程序的处理器和存储器、集成逻辑电路，和/或其他可以提供上述功能的器件。在一个简单的实施例中，本领域的技术人员可以想到装置700可以采用图7所示的形式。处理单元710可以通过图6所示的处理器610来实现。可选地，如果图6所示的计算机设备包括存储器620，处理单元710可以通过处理器610和存储器620来实现。收发单元720可以通过图6所示的收发器630来实现。所述收发器630包括接收功能和发送功能。具体的，处理器通过执行存储器中存储的计算机程序来实现。可选地，当所述装置700是芯片时，那么收发单元720的功能和/或实现过程还可以通过管脚或电路等来实现。可选地，所述存储器可以为所述芯片内的存储单元，比如寄存器、缓存等，所述存储单元还可以是所述计算机设备内的位于所述芯片外部的存储单元，如图6所的存储器620，或者，也可以是部署在其他系统或设备中的存储单元，不在所述计算机设备内。
本申请的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本申请中使用的术语“制品”涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括，但不限于:磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，压缩盘(compact disc，CD)、数字通用盘(digital versatile disc，DVD)等)，智能卡和闪存器件(例如，可擦写可编程只读存储器(erasable programmable read-only memory，EPROM)、卡、棒或钥匙驱动器等)。另外，本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语“机器可读介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行图2过图3所示实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行图2或图3所示实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种系统，其包括前述的装置或设备。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，高密度数字视频光盘(digital video disc，DVD))、或者半导体介质(例如，固态硬盘(solid state disc，SSD))等。
在本说明书中使用的术语“部件”、“模块”、“系统”等用于表示计算机相关的实体、硬件、固件、硬件和软件的组合、软件、或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进程和/或执行线程中，部件可位于一个计算机上和/或分布在两个或更多个计算机之间。此外，这些部件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如根据具有一个或多个数据分组(例如来自与本地系统、分布式系统和/或网络间的另一部件交互的二个部件的数据，例如通过信号与其它系统交互的互联网)的信号通过本地和/或远程进程来通信。
还应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
还应理解，本申请实施例中引入编号“第一”、“第二”等只是为了区分不同的对象，比如，区分不同的“信息”，或，“设备”，或，“单元”，对具体对象以及不同对象间的对应关系的理解应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (35)

  1. 一种编码配置的方法，其特征在于，包括：
    光网络单元接收第一信息，所述第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；
    所述光网络单元根据所述第一信息确定所述前向纠错码字信息。
  2. 根据权利要求1所述的方法，其特征在于，所述第一信息包括第二信息，所述第二信息通过比特序列指示所述前向纠错码字信息的净荷信息相对于所述第一前向纠错母码的净荷信息的改变量。
  3. 根据权利要求2所述的方法，其特征在于，所述第二信息的比特序列包括第一序列，所述第一序列的值为0，用于表示对所述第一序列对应的第一前向纠错母码的256或128个比特进行截短处理。
  4. 根据权利要求2所述的方法，其特征在于，所述第二信息的比特序列包括第一序列，所述第一序列对应的值为1，用于表示对所述第一序列对应的第一前向纠错母码的256或128个比特进行截短处理。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述第一信息还包括第三信息，所述第三信息通过比特序列指示所述前向纠错码字信息的检验位信息相对于所述第一前向纠错母码的检验信息的改变量。
  6. 根据权利要求5所述的方法，其特征在于，所述第三信息的比特序列包括第三序列，所述第三序列对应的值为0，用于表示对所述第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理。
  7. 根据权利要求5所述的方法，其特征在于，所述第三信息的比特序列包括第三序列，所述第三序列对应的值为1，用于表示对所述第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理。
  8. 根据权利要求1以及5至7中任一项所述的方法，其特征在于，所述第一信息包括第一数值，指示对所述第一前向纠错母码的净荷信息按照第一顺序截短M个比特，得到所述前向纠错码字信息的净荷信息，所述M由第一数值乘以256或128得到。
  9. 根据权利要求1至4以及8中任一项所述的方法，其特征在于，所述第一信息包括第二数值，指示对所述第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到所述前向纠错码字信息的检验位信息，所述N由第二数值乘以256或128得到。
  10. 根据权利要求8或9所述的方法，其特征在于，所述第一顺序和/或所述第二顺序包括从后到前或从前到后。
  11. 根据权利要求1至10中任一项所述的方法，其特征在于，所述第一信息还包括第四信息，所述第四信息用于指示所述第一信息生效。
  12. 根据权利要求1至11中任一项所述的方法，其特征在于，所述第一信息承载于第一消息，所述第一消息包括以下至少一种：
    物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
  13. 根据权利要求1至12中任一项所述的方法，其特征在于，所述方法还包括：
    所述光网络单元发送能力上报信息，所述能力上报信息用于指示所述光网络单元支持的前向纠错母码，所述光网络单元支持的前向纠错母码包括所述第一前向纠错母码。
  14. 根据权利要求1至13中任一项所述的方法，其特征在于，所述方法还包括：
    所述光网络单元接收能力查询信息，所述能力查询信息用于查询所述光网络单元支持的前向纠错母码。
  15. 一种编码配置的方法，其特征在于，包括：
    光线路终端确定第一信息，所述第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；
    所述光线路终端向光网络单元发送所述第一信息。
  16. 根据权利要求15所述的方法，其特征在于，所述第一信息包括第二信息，所述第二信息通过比特序列指示所述前向纠错码字信息的净荷信息相对于所述第一前向纠错母码的净荷信息的改变量。
  17. 根据权利要求16所述的方法，其特征在于，所述第二信息的比特序列包括第一序列，所述第一序列的值为0，用于表示对所述第一序列对应的第一前向纠错母码的256或128个比特进行截短处理。
  18. 根据权利要求16所述的方法，其特征在于，所述第二信息的比特序列包括第一序列，所述第一序列对应的值为1，用于表示对所述第一序列对应的第一前向纠错母码的256或128个比特进行截短处理。
  19. 根据权利要求15至18中任一项所述的方法，其特征在于，所述第一信息还包括第三信息，所述第三信息通过比特序列指示所述前向纠错码字信息的检验位信息相对于所述第一前向纠错母码的检验信息的改变量。
  20. 根据权利要求19所述的方法，其特征在于，所述第三信息的比特序列包括第三序列，所述第三序列对应的值为0，用于表示对所述第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理。
  21. 根据权利要求19所述的方法，其特征在于，所述第三信息的比特序列包括第三序列，所述第三序列对应的值为1，用于表示对所述第三序列对应的第一前向纠错母码的256或128个比特进行打孔处理。
  22. 根据权利要求15以及19至21中任一项所述的方法，其特征在于，所述第一信息包括第一数值，指示对所述第一前向纠错母码的净荷信息按照第一顺序截短M个比特，得到所述前向纠错码字信息的净荷信息，所述M由第一数值乘以256或128得到。
  23. 根据权利要求15至18以及22中任一项所述的方法，其特征在于，所述第一信息包括第二数值，指示对所述第一前向纠错母码的检验位信息按照第二顺序打孔N个比特得到所述前向纠错码字信息的检验位信息，所述N由第二数值乘以256或128得到。
  24. 根据权利要求22或23所述的方法，其特征在于，所述第一顺序和/或所述第二顺序包括从后到前或从前到后。
  25. 根据权利要求15至24中任一项所述的方法，其特征在于，所述第一信息还包括第四信息，所述第四信息用于指示所述第一信息生效。
  26. 根据权利要求15至25中任一项所述的方法，其特征在于，所述第一信息承载于第一消息，所述第一消息包括以下至少一种：
    物理层运行管理维护PLOAM消息、光网络终端管理控制接口OMCI消息、运行管理和维护OAM消息。
  27. 根据权利要求15至26中任一项所述的方法，其特征在于，所述方法还包括：
    所述光线路终端接收能力上报信息，所述能力上报信息用于指示光网络单元支持的前向纠错母码，所述光网络单元支持的前向纠错母码包括所述第一前向纠错母码。
  28. 根据权利要求15至27中任一项所述的方法，其特征在于，所述方法还包括：
    所述光线路终端发送能力查询信息，所述能力查询信息用于查询所述光网络单元支持的前向纠错母码。
  29. 一种编码配置的装置，其特征在于，包括：
    收发单元，用于接收第一信息，所述第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；
    处理单元，用于根据所述第一信息确定所述前向纠错码字信息。
  30. 一种编码配置的方法，其特征在于，包括：
    处理单元，用于确定第一信息，所述第一信息用于指示前向纠错码字信息相对于第一前向纠错母码的改变量；
    收发单元，用于向光网络单元发送所述第一信息。
  31. 一种通信装置，其特征在于，包括：处理器，所述处理器用于与存储器耦合，并读取所述存储器中的指令之后，执行如权利要求1至14中任一项所述的方法；或者，
    执行如权利要求15至28中任一项所述的方法。
  32. 一种芯片系统，其特征在于，包括：处理器，用于从存储器中调用并运行计算机程序，使得安装有所述芯片系统的通信设备执行如权利要求1至14中任一项所述的方法；或者，
    使得安装有所述芯片系统的通信设备执行如权利要求15至28中任一项所述的方法。
  33. 一种通信系统，其特征在于，包括光线路终端和光网络单元，
    所述光网络单元用于执行如权利要求1至14中任一项所述的方法；
    所述光线路终端用于执行如权利要求15至28中任一项所述的方法。
  34. 一种计算机可读介质，其特征在于，所述计算机可读介质存储有程序代码，当所述程序代码在计算机上运行时，使得计算机执行如权利要求1至14中任一项所述的方法；或者，
    使得计算机执行如权利要求15至28中任一项所述的方法。
  35. 一种计算机程序产品，其特征在于，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如权利要求1至14中任一项所述的方法；或者，
    使得计算机执行如权利要求15至28中任一项所述的方法。
PCT/CN2022/125641 2022-01-07 2022-10-17 编码配置的方法和装置 WO2023130796A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210015997.2 2022-01-07
CN202210015997.2A CN116455511A (zh) 2022-01-07 2022-01-07 编码配置的方法和装置

Publications (1)

Publication Number Publication Date
WO2023130796A1 true WO2023130796A1 (zh) 2023-07-13

Family

ID=87073018

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/125641 WO2023130796A1 (zh) 2022-01-07 2022-10-17 编码配置的方法和装置

Country Status (2)

Country Link
CN (1) CN116455511A (zh)
WO (1) WO2023130796A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013093993A1 (ja) * 2011-12-19 2013-06-27 三菱電機株式会社 ネットワークシステム
CN112219363A (zh) * 2018-03-02 2021-01-12 中兴通讯股份有限公司 可重新配置的自适应前向纠错
CN112368964A (zh) * 2018-10-15 2021-02-12 华为技术有限公司 点对多点通信网络中的通信方法和装置
CN114374472A (zh) * 2020-10-15 2022-04-19 诺基亚通信公司 前向纠错控制
CN114928429A (zh) * 2021-02-03 2022-08-19 诺基亚通信公司 用于onu激活的方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013093993A1 (ja) * 2011-12-19 2013-06-27 三菱電機株式会社 ネットワークシステム
CN112219363A (zh) * 2018-03-02 2021-01-12 中兴通讯股份有限公司 可重新配置的自适应前向纠错
CN112368964A (zh) * 2018-10-15 2021-02-12 华为技术有限公司 点对多点通信网络中的通信方法和装置
CN114374472A (zh) * 2020-10-15 2022-04-19 诺基亚通信公司 前向纠错控制
CN114928429A (zh) * 2021-02-03 2022-08-19 诺基亚通信公司 用于onu激活的方法及装置

Also Published As

Publication number Publication date
CN116455511A (zh) 2023-07-18

Similar Documents

Publication Publication Date Title
US10476526B2 (en) Coding and decoding method and device, and system
US7917833B2 (en) Communication apparatus, transmitter, receiver, and error correction optical communication system
CN102891731B (zh) 64b66b编码系统的前向纠错
JP7424724B2 (ja) データ伝送方法、データ伝送装置、通信システム、ネットワークデバイス、データ伝送システム、コンピュータ可読記憶媒体、およびコンピュータプログラムコード
WO2020057187A1 (en) Passive optical network (pon) channel bonding protocol
WO2019105471A1 (zh) 数据编译码方法和装置、olt、onu和pon系统
CN107925422A (zh) 无源光网络（pon）中的自适应前向纠错（fec）
US11812206B2 (en) Method and apparatus for ONU activation
JP2023107856A (ja) 受動光ネットワーク（ｐｏｎ）フレーム設計
JP2005184811A (ja) ギガビットイーサネット（登録商標）受動光加入者網及び方法
WO2023130796A1 (zh) 编码配置的方法和装置
WO2020147023A1 (zh) 一种突发信号转连续信号的方法、设备
CN113132057B (zh) 光线路终端和光网络单元及其方法
WO2023246416A1 (zh) 一种数据传输方法及装置
CN110830152B (zh) 接收码块流的方法、发送码块流的方法和通信装置
WO2019218965A1 (zh) 数据处理方法和装置、通信系统
US20230353279A1 (en) Methods, apparatuses, and optical network devices for uplink fec encoding and decoding
WO2022267543A1 (zh) 一种数据帧的分片方法、数据帧的解析方法及相关设备
WO2022033559A1 (zh) 数据发送、接收方法、装置、发送设备、接收设备及介质
RU2809182C1 (ru) Способ передачи служебных данных, соответствующее устройство и микросхема цифровой обработки
WO2024002146A1 (zh) 一种配置时隙的方法、装置和系统
WO2023040466A1 (zh) 一种编码方法、译码方法以及相关装置
KR102669462B1 (ko) 수동 광 네트워크(ｐｏｎ) 프레임 설계
WO2024022458A1 (zh) 一种onu数据的采集方法、装置及系统
JP5977202B2 (ja) 光通信システム及び光通信方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22918248

Country of ref document: EP

Kind code of ref document: A1