WO2019105471A1 - 数据编译码方法和装置、olt、onu和pon系统 - Google Patents

数据编译码方法和装置、olt、onu和pon系统 Download PDF

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WO2019105471A1
WO2019105471A1 PCT/CN2018/118665 CN2018118665W WO2019105471A1 WO 2019105471 A1 WO2019105471 A1 WO 2019105471A1 CN 2018118665 W CN2018118665 W CN 2018118665W WO 2019105471 A1 WO2019105471 A1 WO 2019105471A1
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payload
data
length
fec
value
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PCT/CN2018/118665
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English (en)
French (fr)
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景磊
高波
聂世玮
刘德坤
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华为技术有限公司
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Priority to KR1020207018378A priority Critical patent/KR102373841B1/ko
Priority to JP2020529745A priority patent/JP7152488B2/ja
Publication of WO2019105471A1 publication Critical patent/WO2019105471A1/zh
Priority to US16/889,053 priority patent/US11245490B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H04L1/0008—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0075—Transmission of coding parameters to receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0084—Formats for payload data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes

Definitions

  • the present invention relates to the field of optical communications, and more particularly to a data encoding and decoding method, a data encoding and decoding apparatus, an optical line terminal, an optical network unit, and a PON system in a PON system.
  • Passive Optical Network (PON) technology is a point-to-multipoint fiber access technology.
  • the PON system may include an Optical Line Terminal (OLT), an Optical Distribution Network (ODN), and at least one Optical Network Unit (ONU).
  • OLT is connected to the ODN, and the ODN is connected to multiple ONUs.
  • Ethernet Passive Optical Network (EPON) technology is a better access technology. Its main features are simple maintenance, low cost, high transmission bandwidth and high performance price ratio.
  • EPON is a technology that uses passive optical transmission, components with amplification and relay functions are not used. Therefore, the transmission distance and number of branches of an EPON network depend on the power budget and various transmission losses. As the transmission distance or the number of branch ratios increases, the signal-to-noise ratio (SNR) of the transmitted data gradually decreases, resulting in more bit errors.
  • SNR signal-to-noise ratio
  • FEC technology is introduced in the EPON system to improve the anti-interference ability of the system to increase the power budget of the system.
  • FEC Forward Error Correction
  • the basic working principle of the FEC in the EPON system is: after the information data transmitted by the transmitting end, the FEC check code words are added, and the check code words and the verified information data are related to each other by certain certain rules (constraint The receiving end checks the relationship between the information data and the check code word according to the established rule. Once an error occurs in the transmission, the relationship is destroyed, and the wrong code is automatically found and corrected.
  • FEC technology seeks to correct as many errors as possible with as few check bytes as possible, finding an optimal balance between overhead (increased check bytes) and the resulting code gain.
  • the FEC pattern and line coding used in the existing 10GEPON and 1GEPON are disadvantageous in that the synchronization process is complicated and the synchronization speed is slow.
  • the present application provides a data encoding and decoding method, a data encoding and decoding apparatus, a precoding indication method and apparatus, an optical line terminal, an optical network unit, and a PON system in a PON system, which are intended to simplify synchronization. Process for fast synchronization.
  • the first aspect provides a data encoding method in a PON system.
  • the execution entity may be a network device in the PON system.
  • the OLT may send data to the ONU, and the OLT may encode the data to the OLT.
  • the encoding method is performed at the physical coding sublayer, the method includes: collecting N data block combinations in the physical coding sublayer to generate valid data, where N is an integer, and N is less than or equal to a forward error correction coding FEC code.
  • the quotient of the type corresponding payload value divided by the length of the collected data block (ie, N is less than or equal to the ratio of the payload value of the FEC pattern to the length of each data block), and the FEC pattern corresponds to the FEC code.
  • the length of the check portion is equal to the difference between the FEC codeword value and the payload value;
  • the codeword structure is generated in the physical coding sublayer, and the codeword structure includes valid data, a check portion, and a sync header, valid data, Check section and sync header They are independent of each other and distributed in the codeword structure, so that fast synchronization can be realized, and synchronization is simple, and the synchronization header can be quickly located.
  • the sync header is located at the head of the codeword structure or at the end of the codeword structure, enabling further fast synchronization.
  • the sync header can also be located between the valid data and the check portion.
  • the collected data block may be a 128B/129B or 256B/257B data block
  • the data block input to the physical coding sublayer may be a 64B/66B or 64B/65B data block.
  • the physical coding sublayer needs to be input.
  • the data block of 64B/66B or 64B/65B is transcoded into 128B/129B or 256B/257B data blocks; by transcoding, the coding overhead is reduced, and the bandwidth efficiency can be effectively improved.
  • the collected data block may also be a 64B/66B or 64B/65B data block.
  • the FEC codeword value is equal to the payload value plus the check length value, indicating that the valid bit of the payload value is subjected to FEC encoding to generate a check length value check bit, and the sum of the valid bit and the check bit length is equal to the FEC codeword value. .
  • the payload When the length of the valid data is equal to the payload value, the payload consists only of valid data. Since the payload portion is all valid data, the coding efficiency is high and the bandwidth efficiency is high.
  • the length of the valid data may also be less than the payload value of the FEC pattern used, and the codeword structure also includes a padding portion, in which case the valid data and the padding portion constitute a payload.
  • the payload length is equal to the payload value of the FEC pattern used. That is, the length of the padding portion can be equal to the difference between the payload value and the effective data length.
  • the length of the padding portion can also be equal to the remainder of the payload value divided by the length of the collected data block.
  • a padding portion and an indication field may be included at the same time, and a partial or all bits of the padding portion are used as a sync header.
  • a padding portion and an indication field may be included at the same time, and a partial or all bits of the padding portion are used as a sync header.
  • a portion of the bits in the padding portion are used as a sync header, and another portion of the bits are used to indicate the length of the codeword structure, or the length of the valid data, or the sum of the length of the valid data and the check portion, or the length of the payload, or
  • the sum of the payload and the length of the check portion may be additionally included in the above-mentioned sync head, or may not additionally include the sync head.
  • the second aspect provides a data decoding method in a PON system.
  • the execution entity may be a network device in the PON system.
  • the OLT may send data to the ONU, and the ONU may decode the data, or the ONU may send data to the OLT.
  • the decoding method is performed by a physical coding sublayer, the method comprising: receiving a codeword structure at a physical coding sublayer, the codeword structure including valid data, a check portion, and a synchronization header, and valid data,
  • the verification part and the synchronization head are independently distributed among the codeword structures, and the valid data is composed of N data blocks, N is an integer, and N is less than or equal to a payload value corresponding to a forward error correction coding FEC pattern and a ratio of the length of each of the data blocks, the FEC pattern corresponding to the FEC codeword value and the payload value, the length of the check portion being equal to the difference between the FEC codeword value and the payload value
  • the physical coding sublayer synchronizes the received codeword structure according to the synchronization header, extracts the payload and the check portion, the payload includes valid data, and the length of the payload is equal to the payload value, and according to the FEC pattern pair
  • the payload performs forward error correction
  • the physical coding sublayer generates a codeword structure, the codeword structure includes a payload, a check data, and a synchronization header; and the physical coding sublayer transmits a codeword structure.
  • the target network device can be enabled to determine whether the codeword structure is precoded based on the indication information.
  • the source network device may be an OLT, and the target network device is an ONU.
  • the data frame carries a discovery authorization message, and the discovery authorization message includes indication information indicating whether the ONU needs to be precoded or deprecoded.
  • the OLT may indicate whether the message sent by the downlink to the ONU is pre-coded, that is, whether the ONU needs to perform pre-coding on the downlink received data, and may also indicate whether the uplink data sent by the ONU to the OLT needs to be pre-coded.
  • the target network device can be further determined according to the information whether the result of the previous blind detection is correct, and double insurance is implemented.
  • the source network device and the target network device can perform precoding and deprecoding according to the indication, without error, and improve efficiency.
  • a sixth aspect provides a precoding indication method in a PON system, which may be performed by a MAC sublayer or a processor of an OLT, or may be performed by a MAC sublayer or an ONU of an ONU, where the method includes: receiving by a target network device a data frame sent by the source network device, the data frame includes indication information indicating whether the data frame is precoded, or whether the source network device has precoding capability, or whether the target network device needs to be precoded or deprecoded; the target network The device determines, according to the indication information, whether to de-code the data frame, or determines whether a data frame transmitted with the source network device needs to be pre-coded and de-coded.
  • a seventh aspect provides a data encoding apparatus in a PON system, the apparatus comprising: a collecting module, configured to collect N data block combinations to generate valid data, where N is an integer, and N is less than or equal to a forward error correction coding FEC.
  • a data decoding apparatus in a PON system comprising: a receiving module, configured to receive a codeword structure, where the codeword structure includes valid data, a check part, and a synchronization header, and valid data and verification
  • the part and the synchronization header are independently distributed among the codeword structures, and the forward error correction decoding FEC pattern is correspondingly provided with the FEC codeword value and the payload value, and the valid data is composed of N data blocks.
  • N is an integer, N is less than or equal to a ratio of a payload value corresponding to an FEC pattern to a length of each of the data blocks, and the FEC pattern is correspondingly provided with an FEC codeword value and a payload value, where The length of the check portion is equal to the difference between the FEC codeword value and the payload value; the synchronization module is configured to synchronize the received codeword structure according to the synchronization header; and the extraction module is configured to extract the payload and the checksum In part, the payload includes valid data, and the length of the payload is equal to the payload value; and the forward error correction decoding module is configured to perform forward error correction decoding on the payload according to the FEC pattern. Since the effective data, the check portion and the sync header are distributed independently of each other in the code word structure, fast synchronization can be realized, and bandwidth efficiency and error correction capability can be improved.
  • a ninth aspect provides a precoding indication device in a PON system, the device comprising: an adding module, configured to add, in a synchronization header, indication information indicating whether a codeword structure is precoded; and a generating module, configured to generate a codeword
  • the structure, the codeword structure includes a payload, a check data, and a synchronization header; and a sending module is configured to send the codeword structure.
  • the network device receiving the codeword structure can be made to determine whether the codeword structure is precoded based on the indication information.
  • a twelfth aspect provides a precoding indication device in a PON system, the device comprising: a receiving module, configured to receive a data frame sent by a source network device, where the data frame includes: indicating whether the data frame is precoded, or Whether the source network device has precoding capability or whether the device needs precoding or deprecoding indication information; the determining module is configured to determine, according to the indication information, whether to decode the data frame, or determine whether the source network device needs to be The transmitted data frames are precoded and deprecoded.
  • a network device in a thirteenth aspect, can be an OLT or an ONU.
  • the network device can include a chip, which can be a MAC chip.
  • the chip collects N data block combinations in the physical coding sublayer to generate valid data; the N is an integer, and N is less than or equal to a payload value corresponding to a forward error correction coding FEC pattern and each of the data blocks.
  • the FEC pattern is correspondingly provided with an FEC codeword value and a payload value; a payload is generated at the physical coding sublayer, the payload includes valid data, and the length of the payload is equal to the payload value; Generating, by the physical coding sublayer, the FEC encoding of the payload according to the FEC pattern to generate a check portion, the length of the check portion being equal to the difference between the FEC codeword value and the payload value; generating a codeword structure in the physical coding sublayer
  • the codeword structure includes valid data, a check portion, and a sync header. The valid data, the check portion, and the sync header are independently distributed among the codeword structures, thereby enabling fast synchronization and improving bandwidth efficiency and error correction capability.
  • a network device in a fourteenth aspect, can be an OLT or an ONU.
  • the network device can include a chip, which can be a MAC chip.
  • the chip receives a codeword structure at a physical coding sublayer, the codeword structure includes valid data, a check portion, and a sync header, and the valid data, the check portion, and the sync header are independently distributed among the codeword structures.
  • the valid data is composed of N data blocks, N is an integer, and N is less than or equal to a ratio of a payload value corresponding to a forward error correction code FEC pattern to a length of each of the data blocks, where the FEC pattern corresponds to Configuring a FEC codeword value and a payload value, the length of the check portion being equal to a difference between the FEC codeword value and the payload value; synchronizing the received codeword structure according to a synchronization header at a physical coding sublayer And extracting a payload and a check portion, the payload including the valid data, and the length of the payload is equal to the payload value, and performing forward error correction decoding on the payload according to the FEC pattern.
  • the network device may comprise a chip, which may be a MAC chip, the MAC chip comprising the physical coding sublayer described above.
  • a network device may be an OLT or an ONU.
  • the network device includes a physical coding sublayer, and the physical coding sublayer adds indication information indicating whether the codeword structure is precoded in the synchronization header; the preset position bit in the synchronization header may be used as the indication information, and which location, source
  • the network device and the target network device can be agreed upon. For example, if the bit at the end of the sync header is "0", it means that the precoding is performed; when the bit at the end of the sync header is "1", it means that the precoding is not performed.
  • the physical coding sublayer generates a codeword structure, the codeword structure includes a payload, a check data, and a synchronization header; and the physical coding sublayer transmits a codeword structure.
  • the target network device can be enabled to determine whether the codeword structure is precoded based on the indication information.
  • the network device may comprise a chip, which may be a MAC chip, the MAC chip comprising the physical coding sublayer described above.
  • a network device in a sixteenth aspect, can be an OLT or an ONU.
  • the network device includes a physical coding sublayer, the physical coding sublayer receives a codeword structure, the codeword structure includes a payload, a check data, and a synchronization header, and the synchronization header includes indication information indicating whether the codeword structure is precoded;
  • the coding sublayer determines whether the codeword structure is precoded based on the indication information in the synchronization header.
  • the network device may comprise a chip, which may be a MAC chip, the MAC chip comprising the physical coding sublayer described above.
  • a network device in a seventeenth aspect, can be an OLT or an ONU.
  • the network device includes a MAC sublayer, a processor and a transceiver, and the MAC sublayer or processor generates a data frame, the data frame includes a function to indicate whether the network device has precoding capability, or whether the target network device needs to be precoded or solved.
  • the precoding, or the target network device turns on or off the indication information of the precoding enable bit; the transceiver transmits the data frame to the target network device. Thereby, the target network device can determine whether precoding and deprecoding are required according to the indication information.
  • a network device in an eighteenth aspect, is provided, and the network device may be an OLT or an ONU.
  • the network device includes a MAC sublayer, a processor, and a transceiver, and the transceiver receives a data frame sent by the source network device, where the data frame includes an indication of whether the data frame is precoded, or whether the source network device has precoding capability, Or whether the network device needs precoding or deprecoding indication information; the MAC sublayer or the processor determines, according to the indication information, whether to decode the data frame, or determines whether a data frame to be transmitted to the source network device is needed. Precoding and deprecoding are performed.
  • protection themes between different embodiments are different, but the specific implementation details may be referred to each other. Some protection topics do not specifically describe the implementation details, and other various topics may be referred to.
  • an optical line terminal comprising the apparatus according to any one of the above seventh to twelfth aspects, or the optical line terminal comprising any one of the thirteenth to eighteenth aspects described above The network device described in the item.
  • an optical network unit comprising the apparatus according to any one of the above seventh to twelfth aspects, or the optical network unit comprising any one of the thirteenth to eighteenth aspects described above The network device described in the item.
  • a codeword structure in still another aspect of the present application, includes a payload, a checksum, and a sync header.
  • the checksum is generated for the payload FEC, and the payload includes valid data, and the valid data is N.
  • Each of the FEC patterns is provided with an FEC codeword value and a payload value, N is an integer, and N is less than or equal to the quotient of the payload value divided by the length of the data block, the payload
  • the length of the check portion is equal to the difference between the FEC codeword value and the payload value; the valid data, the check portion, and the sync header are independent of each other. Distributed within the codeword structure.
  • MAC chip comprising the apparatus of any of the above seventh to twelfth aspects.
  • a PON system comprising the optical line terminal of the nineteenth aspect and the optical network unit of the twentieth aspect.
  • a still further aspect of the present application provides a computer readable storage medium storing computer software instructions for use in the apparatus of any of the above seventh to twelfth aspects, or storing Computer software instructions for use with the network device of any of the above-described thirteenth to eighteenth aspects, when executed on a computer, cause the computer to perform the methods described in the above aspects.
  • FIG. 1 is a schematic structural diagram of a PON system according to an embodiment of the invention.
  • FIG. 2 is an exemplary flowchart of a data encoding and decoding method according to an embodiment of the invention
  • FIG. 3(d) is still another schematic diagram of data block transcoding according to an embodiment of the invention.
  • 4(1) is a schematic diagram showing the combination of FEC coding and line coding according to an embodiment of the present invention.
  • 4(2) is another schematic diagram of combining FEC coding and line coding according to an embodiment of the present invention.
  • 4(5) is another schematic diagram of combining FEC encoding and line coding according to an embodiment of the invention.
  • 4(6) is another schematic diagram of combining FEC encoding and line coding according to an embodiment of the invention.
  • FIG. 4 (7) is another schematic diagram of combining FEC encoding and line coding according to an embodiment of the invention.
  • FIG. 6 is an exemplary flowchart of a method for indicating a precoding according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of hardware of a network device according to an embodiment of the invention.
  • FIG. 8 is a schematic diagram of an exemplary functional module of a data encoding apparatus according to an embodiment of the invention.
  • the direction from the OLT 110 to the ONU 130 is defined as the downstream direction, and the direction from the ONU 130 to the OLT 110 is defined as the upstream direction.
  • the OLT 110 broadcasts the downlink data to the multiple ONUs 130 managed by the OLT 110 by using a Time Division Multiplexing (TDM) method.
  • TDM Time Division Multiplexing
  • Each ONU 130 only receives data carrying its own identity;
  • the ONUs 130 communicate with the OLT 110 in a Time Division Multiple Access (TDMA) manner, and each ONU 130 transmits uplink data according to the time domain resources allocated by the OLT 110.
  • TDMA Time Division Multiple Access
  • the downlink optical signal sent by the OLT 110 is a continuous optical signal
  • the upstream optical signal sent by the ONU 130 is a burst optical signal.
  • the ONU 130 can be distributed in a user-side location (such as a customer premises).
  • the ONU 130 can be a network device for communicating with the OLT 110 and the user, in particular, the ONU 130 can act as a medium between the OLT 110 and the user, for example, the ONU 130 can receive data from the OLT 110. Forwarded to the user and forwarded data received from the user to the OLT 110.
  • the OLT 110 performs coding to generate a codeword structure, and sends the codeword structure to the ONU 130, and the ONU 130 decodes the codeword structure; or the ONU 130 encodes the codeword structure.
  • the codeword structure is transmitted to the OLT 110, and the codeword structure is decoded by the OLT 110.
  • the device as the sender in the OLT 110 and the ONU 130 is hereinafter referred to as a source network device, and the device as a receiver is referred to as a target network device.
  • the method includes steps S200 to S209, and each step is performed.
  • the specific implementation is as follows:
  • the physical coding sublayer of the source network device receives the input data block of 64B/66B or 64B/65B.
  • the input data block refers to the data content that needs to be transmitted.
  • the physical coding sublayer is also referred to as a PCS (Physical Coding Sublayer) sublayer.
  • the data block of 64B/66B means that the total length of the data block is 66 bits, which contains 64 bits of data, and there are 2 bits of indication information for indicating whether the 64-bit data in the data block is data information or control information.
  • the 2-bit indication information may be located at the head or the tail of the data block.
  • the data block of 64B/65B means that the total length of the data block is 65 bits, which contains 64 bits of data, and there is 1 bit of indication information for indicating whether 64-bit data in the data block is data information or Control information.
  • the 1-bit indication information may be located at the head or the tail of the data block.
  • step S201 The physical coding sublayer of the source network device transcodes the input data block of 64B/66B or 64B/65B into a data block of 128B/129B or 256B/257B; step S201 is optional. If the data block collected in step S202 is a data block of 64B/66B or 64B/65B, step S201 may be omitted. If the data block collected in step S202 is a data block of 128B/129B, 256B/257B, step S201 can be performed.
  • 64B/66B data block transcoded into 128B/129B data blocks As shown in Figures 3(a) to (d), every 2 64B/66B data blocks are transcoded into one 128B/129B data block.
  • the data blocks of 64B/66B are divided into two types, one is a data block carrying data information, and the other is a data block carrying control information.
  • the 2-bit indication information in the data block is “01”, indicating that 64 bits of the data block are data information; and the 2-bit indication information in the data block is “10”. Indicates that 64 bits of the data block are control information.
  • FIG. 3(a) shows that two data blocks of 64B/66B carrying data information are transcoded into one 128B/129B data block.
  • the two-bit indication information of the two 64B/66B data blocks can be separately removed, and the 1-bit indication information is added to the 128-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64) and DB2 (64) respectively represent 64-bit data information in two data blocks.
  • FIG. 3(b) shows that two blocks of 64B/66B carrying control information are transcoded into one 128B/129B data block.
  • the 64B/66B data block carrying the control information includes 4 bits of S1(4), and 4 bits of S1(4) in one of the data blocks can be deleted, and 2 bits of 2 64B/66B data blocks are reserved. Indicate the information and add another 1 bit.
  • the arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs to achieve interworking. Taking FIG. 3(b) as an example, an additional 1 bit is placed in the header of the data block, and then 2 bits of information information of 2 64B/66B data blocks are respectively, and then 4 bits of S1(4) are removed.
  • the control information in the data block of 64B/66B is then the control information in the 64B/66B data block of S1(4) which does not remove 4 bits. It can be understood that other ways can also be arranged.
  • FIG. 3(c) shows that one 64B/66B data block carrying control information and one 64B/66B data block carrying data information are transcoded into one 128B/129B data block.
  • the 64B/66B data block carrying the control information includes 4 bits of S1(4), and the 4-bit S1(4) in the data block can be deleted, and the 2-bit indication of the two 64B/66B data blocks is reserved. Information, and add another 1 bit.
  • the arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs to achieve interworking. Taking FIG.
  • an additional 1 bit is placed in the header of the data block, followed by 2-bit indication information carrying the control information and the 64B/66B data block carrying the data information, and then removing the 4 bits.
  • the control information in the 64B/66B data block of S1(4) is then the data information in the 64B/66B data block carrying the data information. It can be understood that other ways can also be arranged.
  • FIG. 3(d) shows that one 64B/66B data block carrying data information and one 64B/66B data block carrying control information are transcoded into one 128B/129B data block.
  • the additional 1 bit is placed in the data block header, and then is the 2-bit indication information carrying the data information and the 64B/66B data block carrying the control information, and then carrying the data information.
  • the data information in the 64B/66B data block is then removed for control information in the 64-bit/BB block of the 4-bit S1(4). It can be understood that other ways can also be arranged.
  • Figure 3(e) shows that two blocks of 64B/65B carrying data information are transcoded into one 128B/129B data block.
  • the 1-bit indication information of the two 64B/65B data blocks can be separately removed, and the 1-bit indication information is added to the 128-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64) and DB2 (64) respectively represent 64-bit data information in two data blocks.
  • FIG. 3(f) is a transcoding of four 64B/65B data blocks carrying data information into one 256B/257B data block.
  • the 1-bit indication information of the four 64B/65B data blocks can be separately removed, and the 1-bit indication information is added to convert the 256-bit data type carried by the transcoded data block (including two types of data information and control information). ).
  • DB1 (64), DB2 (64), DB3 (64), and DB4 (64) respectively represent 64-bit data information among four data blocks.
  • every 4 64B/66B data blocks are transcoded into one 256B/257B data block.
  • the specific transcoding principle is similar to the above, and can be effectively retained.
  • the data information and the control information are removed from the indication information or S1(4), and one or more bits may be additionally added.
  • the transcoded data block does not lose valid data, and the total number of bits is 256B.
  • the data block may also be scrambled, and the data block collected in step S202 is a scrambled data block.
  • the physical coding sublayer of the source network device collects N data block combinations to generate valid data.
  • the N data blocks collected by the source network device may be 256B/257B data blocks (that is, the line code is 256B/257B), or may be 128B/129B data blocks (that is, the line code is 128B/129B), or may be 64B.
  • the /66B data block ie line code is 64B/66B
  • can also be a 64B/65B data block ie line code is 64B/65B.
  • each data block has the same length. That is, all N data blocks are 256B/257B data blocks, or all are 128B/129B data blocks, or all are 64B/66B data blocks, or all are 64B/65B data blocks.
  • the physical coding sublayer generates a payload, where the payload includes valid data.
  • the physical coding sublayer of the source network device performs an FEC generation check part on the payload, and each FEC pattern is correspondingly provided with an FEC codeword value and a payload value, where N is an integer, and N is less than or equal to a payload value.
  • N is an integer, and N is less than or equal to a payload value.
  • the physical coding sublayer of the source network device generates a codeword structure, where the codeword structure includes valid data, a checksum, and a synchronization header.
  • the FEC pattern may include a Low Density Parity Check Code (LDPC) and a Reed-Solomon code (RS), and may be, for example, LDPC (18493, 15677), RS (2047). , 1739), RS (1023, 847), RS (1023, 845), RS (1023, 843), RS (1023, 841), RS (1015, 839), RS (1017, 839) or RS (1019, 839) and so on, are not limited to the ones listed above.
  • LDPC Low Density Parity Check Code
  • RS Reed-Solomon code
  • Each of the FEC patterns corresponds to an FEC codeword value and a payload value, such as LDPC (18493, 15677), and the granularity is 1 bit, indicating that the FEC codeword value is 18493x1 bits, and the payload value is 15677x1 bits; RS (1023, 847), with a granularity of 10 bits, indicates that the FEC codeword value is 1023 x 10 bits and the payload value is 847 x 10 bits.
  • Other FEC patterns are similar and will not be described here.
  • RS (1023, 845), RS (1023, 843), RS (1023, 841), RS (1015, 839), RS (1017, 839), and RS (1019, 839) have a granularity of 10 bits.
  • the FEC pattern can also adopt other expressions, for example, the FEC codeword value and the payload value can be indirectly indicated.
  • the FEC codeword value is equal to the payload value plus the check length value, indicating that the valid bit of the payload value is subjected to FEC encoding to generate a check length value check bit, and the sum of the valid bit and the check bit length is equal to the FEC codeword value.
  • LDPC (18493, 15677) indicates that after performing FEC on 15677 bits of data, 2816 bits of parity data are generated, and the total length of data after FEC becomes 18493 bits.
  • RS (1023, 847) after performing FEC on 8470 bits of data, 1760 bits of parity data is generated, and the total length of data after FEC becomes 10,230 bits.
  • the length of the valid data is less than or equal to the payload value of the FEC pattern used.
  • the effective data length can be adjusted by adjusting the value of N.
  • N is an integer and the value of N can be equal to the quotient of the payload value divided by the length of the collected data block.
  • the value of N may also be less than the quotient of the payload value divided by the length of the collected data block.
  • N can be equal to 1, in which case the payload includes one block of data.
  • N can also be greater than or equal to 2.
  • the length of the valid data is equal to the payload value of the FEC pattern employed.
  • the payload is all composed of valid data. That is, the payload value divided by the length of the collected data block is equal to an integer, which is an integer N.
  • the valid data can also be referred to as a payload.
  • the length of the valid data is less than the payload value of the FEC pattern employed.
  • the codeword structure further includes a padding portion, in which case the valid data and the padding portion constitute a payload, and the sum of the lengths of the valid data and the padding portion is equal to the payload value.
  • the payload length is equal to the payload value of the FEC pattern used. That is, the length of the padding portion can be equal to the difference between the payload value and the effective data length.
  • the length of the padding portion can also be equal to the remainder of the payload value divided by the length of the collected data block. For example, in the case of LDPC (18493, 15677), the collected data block is a 128B/129B data block.
  • Step S203 is specifically: the physical coding sublayer of the source network device performs an FEC generation check portion on the payload.
  • the source network device can perform the FEC generation check portion as a whole on the 15677-bit field composed of the valid data and the padding portion. In this manner, by adding padding fields, various FEC patterns and various line codes can be effectively compatible and adapted.
  • the check portion and the valid data do not contain a sync header, that is, the sync header is not distributed inside the check portion and the valid data.
  • the valid data, the check portion, and the sync header are distributed independently of each other within the code word structure.
  • the sync header can be located at the head of the codeword structure or at the end of the codeword structure to enable further fast synchronization.
  • a sync header may also be located between the valid data and the check portion.
  • the FEC pattern is LDPC (18493, 15677), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the code word structure may not require a padding portion.
  • the N value is 61, and the valid data is generated by 61 256B/257B data blocks.
  • the effective data length is 15677, that is, the payload length is 15677 bits, which can meet the FEC requirement.
  • the length of the check portion is 2816 bits.
  • each placeholder block size is 66 bits
  • the placeholder block The sum of the number and the number of input data blocks is at least 281.
  • the length of the sync header is 53 bits.
  • the length of the sync header is 119 bits. And so on.
  • the FEC pattern is LDPC (18493, 15677), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the code word structure requires a filling portion, and the length of the filling portion is 68.
  • the N value is 121
  • the valid data is generated by 121 128B/129B data blocks.
  • the effective data length is 15609, and the sum of the effective data length and the padding length is 15677, that is, the payload is 15677 bits, which can meet the FEC requirement.
  • the length of the check portion is 2816 bits.
  • each placeholder block size is 66 bits
  • the length of the sync header is 53 bits.
  • the length of the sync header is 119 bits. And so on.
  • the FEC pattern is LDPC (18493, 15677), and the collected data block is a 64B/66B data block.
  • the calculation process is the same as the above example and will not be described here.
  • the valid data is generated by 237 64B/66B data blocks
  • the effective data length is 15642 bits
  • the padding part length is 35 bits
  • the check part length is 2816 bits.
  • the length of the header is 53 bits.
  • the FEC pattern is RS (1023, 847), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the FEC codeword value is 10230 and the payload is 8470.
  • the code word structure requires a filling portion, and the length of the filling portion is 85.
  • the N value is 65, and the valid data is generated by 65 128B/129B data blocks.
  • the effective data length is 8385, and the sum of the effective data length and the padding length is 8470, that is, the payload length is 8470, which can meet the FEC requirement.
  • the length of the check portion is 1760 bits.
  • a partially filled portion as a sync header, for example, to use 50 bits in the padding portion for synchronization. Therefore, no additional bits are needed for the synchronization header, and the padding portion is directly used as the synchronization header, which can effectively reduce the number of bits of invalid data, improve bandwidth efficiency and coding efficiency.
  • the FEC pattern is RS (1023, 847), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the FEC codeword value is 10230 and the payload is 8470.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4(5), the effective data is 8224 bits, and the padding portion is 246 bits.
  • the FEC pattern is RS (1023, 847), and the collected data block is a 64B/66B data block.
  • the FEC codeword value is 10230 and the payload is 8470.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (6), the effective data is 8448 bits, and the padding portion is 22 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the FEC codeword value is 22517 and the payload is 19129.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (7).
  • the valid data is 19018 bits
  • the padding part is 111 bits
  • the synchronization header is 55 bits
  • the check part is 3388 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/66B data block, the 64B/66B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the FEC codeword value is 22517 and the payload is 19129.
  • the valid data is 19092 bits
  • the padding part is 37 bits
  • the synchronization header is 55 bits
  • the check part is 3388 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/66B data block, and the collected data block is 64B/66B data block.
  • the FEC codeword value is 22517 and the payload is 19129.
  • the valid data is 19074 bits
  • the padding part is 55 bits
  • the synchronization header is 55 bits
  • the check part is 3388 bits.
  • the FEC pattern is LDPC (18493, 15677), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the FEC codeword value is 18493 and the payload is 15677.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (10), the effective data is 15677 bits, there is no padding part, the synchronization header is 32 bits, and the verification part is 2816 bits.
  • the FEC pattern is LDPC (18493, 15677), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the FEC codeword value is 18493 and the payload is 15677.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (11).
  • the valid data is 15609 bits
  • the padding part is 68 bits
  • the synchronization header is 32 bits
  • the check part is 2816 bits.
  • the FEC pattern is LDPC (18493, 15677), the input data block is 64B/65B data block, and the collected data block is 64B/65B data block.
  • the FEC codeword value is 18493 and the payload is 15677.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (12).
  • the valid data is 15665 bits
  • the padding part is 12 bits
  • the synchronization header is 32 bits
  • the check part is 2816 bits.
  • the FEC pattern is RS (1023, 847), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the FEC codeword value is 10230 and the payload is 8470.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (13).
  • the valid data is 8224 bits
  • the padding portion is 246 bits
  • the synchronization header is 40 bits
  • the check portion is 1760 bits.
  • the FEC pattern is RS (1023, 847), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the FEC codeword value is 10230 and the payload is 8470.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (14), the effective data is 8385 bits, the padding part is 85 bits, the synchronization header is 40 bits, and the verification part is 1760 bits.
  • the FEC pattern is RS (1023, 847), the input data block is 64B/65B data block, and the collected data block is 64B/65B data block.
  • the FEC codeword value is 10230 and the payload is 8470.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (15), the effective data is 8450 bits, the padding part is 20 bits, the synchronization header is 40 bits, and the verification part is 1760 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 256B/257B data block, and the collected data block is 256B/257B data block. .
  • the FEC codeword value is 22517 and the payload is 19129.
  • the specific calculation process is the same as above, and will not be described here.
  • the specific principle can refer to FIG. 4 (16).
  • the valid data is 19018 bits
  • the padding portion is 111 bits
  • the synchronization header is 38 bits
  • the check portion is 3388 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/65B data block, the 64B/65B data block is transcoded into 128B/129B data block, and the collected data block is 128B/129B data block. .
  • the FEC codeword value is 22517 and the payload is 19129.
  • the valid data is 19092 bits
  • the padding part is 37 bits
  • the synchronization header is 38 bits
  • the check part is 3388 bits.
  • the FEC pattern is RS (2047, 1739), the input data block is 64B/65B data block, and the collected data block is 64B/65B data block.
  • the FEC codeword value is 22517 and the payload is 19129.
  • the valid data is 19110 bits
  • the padding part is 19 bits
  • the synchronization header is 38 bits
  • the check part is 3388 bits.
  • the padding portion when there are redundant bits used as the synchronization header (for example, when the FEC codeword value is divided by the length of the input information block, the remainder is not 0), the padding portion may be simultaneously used as the synchronization header, and all may be used.
  • the padding portion is used as a sync header, and the partially padded portion can also be used as a sync header.
  • the padding portion when the length of the sync header is short enough to meet the synchronization requirement, the padding portion can be used as the sync header at the same time, and all the padding portions can be used as the sync header, or the partial pad portion can be used as the sync header.
  • the padding portion is further configured to indicate a length of the codeword structure, or a length of valid data, or a sum of valid data and a length of the check portion, or a length of the payload, or a payload and a check portion. The sum of the lengths. Part or all of the bits of the padding portion can be used for indication.
  • the codeword structure further includes an indication portion for indicating the length of the codeword structure, or the length of the valid data, or the sum of the length of the valid data and the check portion, or the length of the payload, Or the sum of the payload and the length of the check portion.
  • the physical coding sublayer of the target network device receives the codeword structure.
  • the target network device may pre-store the synchronization sequence, traverse the pre-stored synchronization sequence in the received codeword structure until the synchronization header in the codeword structure matches the pre-stored synchronization sequence, and the synchronization is completed.
  • the physical coding sublayer of the target network device extracts a payload and a checksum component.
  • the physical coding sublayer of the target network device performs forward error correction decoding on the payload by using the extracted check portion.
  • the generated codeword structure includes valid data, a verification part, and a synchronization header, and the valid data, the verification part, and the synchronization header are independently distributed among the codeword structures, thereby being capable of being Fast synchronization, improved bandwidth efficiency and error correction.
  • the invention also provides a precoding indication method.
  • the source network device sends a codeword structure to the target network device, and may perform precoding on the codeword structure or may not perform precoding.
  • the indication information may indicate whether the codeword structure is precoded, and the target network device may The indication information determines whether the codeword structure has been precoded to further determine whether the codeword structure needs to be precoded.
  • the synchronization header in this embodiment, reference may be made to the foregoing embodiment of the data encoding and decoding method, and details are not described herein again.
  • the precoding indication method includes:
  • the physical coding sublayer of the source network device adds indication information indicating whether the codeword structure is precoded in the synchronization header.
  • a bit of a preset position in the synchronization header may be used as the indication information, and which location, the source network device and the target network device may agree. For example, if the bit at the end of the sync header is "0", it means that the precoding is performed; when the bit at the end of the sync header is "1", it means that the precoding is not performed.
  • the precoding can be performed by using an exclusive OR method.
  • a predetermined initial bit may be XORed with the first bit of the original codeword structure, and the resulting one bit is used as the first bit of the output codeword structure; then the original codeword is used.
  • the second bit of the structure is XORed with the first bit of the output codeword structure, and the resulting one bit is used as the second bit of the output codeword structure; then the third bit of the original codeword structure is output.
  • the second bit of the codeword structure is XORed, the resulting one bit is used as the third bit of the output codeword structure, and so on, until the last bit of the original codeword structure is associated with the output codeword structure.
  • the second to last bit is XORed and the resulting one bit is used as the last bit of the output codeword structure.
  • the preset initial bit can be “0” or "1".
  • a piece of the original sequence in the original codeword structure is assumed to be "0110101110".
  • the output sequence is "0100110100”; when the preset initial bit is "1", the output sequence is "1011001011".
  • a preset initial bit may also be XORed with each bit of the original codeword structure, that is, the initial bit is XORed with the first bit of the original codeword structure to obtain an output codeword.
  • the first bit of the structure, the initial bit is XORed with the second bit of the original codeword structure to obtain the second bit of the output codeword structure, and so on.
  • the physical coding sublayer of the source network device generates a codeword structure, and the codeword structure includes a payload, a checksum data, and a synchronization header.
  • the codeword structure is different from the above embodiment in that indication information indicating whether the code word structure is precoded is added to the synchronization header.
  • the physical coding sublayer of the source network device sends the codeword structure.
  • the physical coding sublayer can transmit the codeword structure to the Physical Medium Attachment (PMA) sublayer of the source network device for subsequent processing.
  • PMA Physical Medium Attachment
  • the physical coding sublayer of the target network device receives the codeword structure; the physical coding sublayer of the target network device may receive the transmitted codeword structure of the PMA sublayer of the target network device.
  • the physical coding sublayer of the target network device synchronizes the received codeword structure according to the synchronization header.
  • the source network device and the target network device may pre-appoint whether to pre-code or pre-code the pre-coded initial bits. Therefore, after receiving the codeword structure, the target network device may decide whether to de-pre-code according to a predetermined agreement, and decompose the initial bits used for pre-coding. Specifically, when the source network device and the target network device have previously agreed not to perform precoding, the target network device may directly synchronize the codeword structure according to the pre-stored synchronization sequence. When the source network device and the target network device pre-arrange pre-coding, the target network device may first perform pre-coding on the codeword structure, and then synchronize the codeword structure according to the pre-stored synchronization sequence; or may synchronize first. Then solve the precoding.
  • the source network device may also not pre-arrange whether to pre-code with the target network device. Whether the received codeword structure is precoded can be determined by the target network device by blind detection.
  • the target network device may pre-store the first synchronization sequence and the second synchronization sequence, where the first synchronization sequence may be an original synchronization sequence before precoding of the codeword structure, and the second synchronization sequence may be output synchronization after precoding of the codeword structure.
  • Sequence it can be understood that there may be two types of second synchronization sequences, one is a synchronization sequence for precoding output with original bit "0", and the other is a synchronization sequence for precoding output with original bit "1".
  • the target network device directly extracts the valid data and the check portion from the codeword structure.
  • the target network device deprecodes the codeword structure; the target network device extracts valid data and the calibration from the precoded codeword structure. Test section.
  • the physical coding sublayer of the target network device determines whether the codeword structure is precoded according to the indication information in the synchronization header.
  • the target network device can further determine whether the result of the previous blind detection is correct according to the information, and implement double insurance.
  • the invention also provides a precoding indication method.
  • the source network device sends a data frame to the target network device, and may or may not perform precoding on the data frame.
  • the indication information may be used to indicate whether the data frame is precoded, and the target network device may determine according to the indication information. Whether the data frame is precoded to further determine whether the data frame needs to be pre-coded.
  • the method may be performed by the MAC control sublayer or by a processor, as shown in FIG. 6, the method includes:
  • the source network device generates a data frame, where the data frame includes: indicating whether the source network device has precoding capability, or whether the target network device needs to be precoded or deprecoded, or the target network device turns the precoding on or off. Indicator information of the energy level;
  • the source network device sends a data frame to the target network device.
  • the target network device receives a data frame sent by the source network device.
  • the target network device determines, according to the indication information, whether to de-code the data frame, or determines whether a data frame transmitted by the source network device needs to be pre-coded and de-coded.
  • the target network device also needs to synchronize the data frame.
  • the specific synchronization method refer to the foregoing embodiment, and details are not described herein again.
  • the source network device is an ONU
  • the target network device is an OLT
  • the data frame carries a registration request message (REISTER_REQ)
  • the registration request message includes indication information for indicating whether the ONU has precoding capability. That is, the ONU reports to the OLT whether it has precoding capability. Based on the indication information, the OLT can determine whether it is necessary to precode the data sent to the ONU. By adding indication information indicating whether the source network device has precoding capability in the data frame, it is possible to inform the target network device whether the data frame sent by the source network device needs to be de-coded, and whether the target network device needs to be The data frame sent to the source network device is precoded.
  • the source network device is an OLT
  • the target network device is an ONU
  • the data frame carries a discovery message (Discovery Gate)
  • the discovery authorization message includes indication information indicating whether the ONU needs to be precoded or deprecoded.
  • the OLT may indicate whether the message sent by the downlink to the ONU is pre-coded, that is, whether the ONU needs to perform pre-coding on the downlink received data, and may also indicate whether the uplink data sent by the ONU to the OLT needs to be pre-coded.
  • the data frame may include an uplink indication part and a downlink indication part, where the uplink indication part is used to indicate whether the uplink transmission is pre-coded, and the downlink indication part is used to indicate whether the downlink transmission is pre-coded.
  • the uplink indication portion and the downlink indication portion may be located at a preset location, and are predetermined between the OLT and the ONU.
  • the uplink identifier and the downlink identifier may also be added to indicate whether an indication portion is an uplink indication portion or a downlink indication portion.
  • the target network device can further determine, according to the information, whether the result of the previous blind detection is correct, and implement double insurance.
  • the source network device and the target network device can perform precoding and deprecoding according to the indication, without error, and improve efficiency.
  • the source network device is an OLT
  • the target network device is an ONU
  • the data frame carries a registration message.
  • the registration message includes indication information for instructing the ONU to enable or disable the precoding enable bit.
  • the ONU turns the precoding enable bit on or off. For example, when the precoding enable bit is turned on, the ONU performs precoding or deprecoding. When the precoding enable bit is turned off, the ONU does not perform precoding and deprecoding. Alternatively, when the precoding enable bit is also turned on, the ONU does not perform precoding and deprecoding. When the precoding enable bit is turned off, the ONU performs precoding or deprecoding.
  • the precoding enable bit may be a bit of a preset position, for example, may be 1 bit or 2 bits, or other number of bits. Taking 1 bit as an example, when the bit is "0", it means that the precoding enable bit is turned off; when the bit is "1", it means that the precoding enable bit is turned on.
  • the ONU may forward the enable response indication information to the OLT, and may carry the enable response indication information in the registration response message (Register_ACK) to inform the OLT whether the ONU opens the precoding enable bit.
  • the present invention also provides a network device, which may be an OLT 110 or an ONU 130.
  • the network device includes a processor 510, a memory 520, a medium access control (MAC) chip 530, a transceiver 540, and a wavelength division multiplexer 550.
  • MAC medium access control
  • the processor 510 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit ASIC, or at least one integrated circuit for executing related programs to implement the technology provided by the embodiments of the present invention. Program.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the memory 520 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • Memory 520 can store operating systems and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 520 and executed by the processor 510.
  • the processor 510 may include a memory 520 internally. In another embodiment, processor 510 and memory 520 are two separate structures.
  • processor 510 and MAC chip 530 may be two separate structures.
  • a MAC chip 530 can be included in the processor 510.
  • the MAC chip 530 may include a physical coding sublayer and a MAC control sublayer.
  • Transceiver 540 can include a light emitter and/or a light receiver.
  • the light emitter can be used to transmit an optical signal and the optical receiver can be used to receive an optical signal.
  • the light emitter can be realized by a light emitting device such as a gas laser, a solid laser, a liquid laser, a semiconductor laser, a direct modulation laser, or the like.
  • the light receiver can be implemented by a photodetector such as a photodetector or a photodiode such as an avalanche diode.
  • the transceiver 540 can also include a digital to analog converter and an analog to digital converter.
  • the wavelength division multiplexer 550 is coupled to the transceiver 540, which acts as a multiplexer when the network device transmits an optical signal.
  • the wavelength division multiplexer acts as a demultiplexer.
  • a wavelength division multiplexer can also be referred to as an optical coupler.
  • the physical coding sublayer of the source network device is used to perform steps S200, S201, S202, S203, S204, and S205.
  • the physical coding sublayer of the source network device is used to perform steps S301, S302 and S303.
  • the MAC control sublayer or processor of the source network device is configured to perform step S401, and the transceiver is configured to perform step S402.
  • the physical coding sublayer of the target network device is used to perform steps S206, S207, S208 and S209, and the physical coding sublayer of the target network device is also used for Steps S304, S305 and S306 are performed.
  • the MAC control sublayer or processor 510 of the target network device is configured to perform step S404, and the transceiver 540 is configured to perform step S403.
  • the processor 510 the transceiver 540, the MAC control sub-layer, and the physical coding sub-layer may refer to the related descriptions of the foregoing embodiments and the accompanying drawings, and details are not described herein again.
  • the present invention also provides a data encoding apparatus in a PON system, which can be integrated in the source network device of the above embodiment, for example, can be integrated in the MAC chip of the source network device.
  • the apparatus includes a collection module 610, a forward error correction coding module 620, and a generation module 630.
  • the collecting module 610 is configured to perform steps S200, S202, the forward error correction encoding module 620 is configured to perform step S204, and the generating module 630 is configured to perform steps S203 and S205.
  • the device further includes a transcoding module 640, and the transcoding module is configured to perform step S201.
  • the present invention also provides a data decoding apparatus in a PON system, which can be integrated in the target network device of the above embodiment, for example, can be integrated in the MAC chip of the target network device.
  • the apparatus includes: a receiving module 710, a synchronization module 720, an extraction module 730, and a forward error correction decoding module 740.
  • the receiving module 710 is configured to perform step S205
  • the synchronization module 720 is configured to perform step S206
  • the extracting module 730 is configured to perform step S207
  • the forward error correction decoding module 740 is configured to perform step S208.
  • the present invention also provides a precoding indication device in a PON system, which may be integrated in the source network device of the above embodiment, for example, may be integrated in a MAC chip of the source network device.
  • the device comprises: an adding module, a generating module and a sending module.
  • the adding module is configured to perform step S301
  • the generating module is configured to perform step S302
  • the sending module is configured to perform step S303.
  • the present invention also provides a precoding indication device in a PON system, which can be integrated in the target network device of the above embodiment, for example, can be integrated in the MAC chip of the target network device.
  • the device comprises: a receiving module, a synchronization module and a determining module.
  • the receiving module is configured to perform step S304
  • the synchronization module is configured to perform step S305
  • the determining module is configured to perform step S306.
  • the present invention also provides a precoding indication device in a PON system, which may be integrated in the source network device of the above embodiment, for example, may be integrated in the MAC chip of the source network device or in the processor.
  • the device comprises: a generating module and a sending module.
  • the generating module is configured to perform step S401, and the sending module is configured to perform step S402.
  • the present invention also provides a precoding indication device in a PON system, which may be integrated in the target network device of the above embodiment, for example, may be integrated in a MAC chip or a processor of the target network device.
  • the device comprises: a receiving module and a determining module.
  • the receiving module is configured to perform step S403, and the determining module is configured to perform step S404.
  • the present invention further provides an optical line terminal comprising the data encoding apparatus according to any of the above embodiments, or the optical line terminal comprising the data decoding apparatus according to any of the above embodiments, or the optical line
  • the terminal includes the precoding indicating device described in any of the above embodiments.
  • the present invention further provides an optical network unit, which includes the data encoding apparatus according to any of the above embodiments, or the optical network unit includes the data decoding apparatus according to any of the above embodiments, or the optical network.
  • the unit includes the precoding indicating device described in any of the above embodiments.
  • the present invention also provides a PON system comprising the optical line terminal described above and the optical network unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

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Abstract

本发明公开了一种PON系统中的数据编译码方法和装置。该方法包括：在物理编码子层收集N个数据块组合生成有效数据，生成净荷，该净荷包括有效数据，对净荷进行FEC生成校验部分，进一步生成码字结构，码字结构包括相互独立分布的有效数据、校验部分和同步头，同步头可以位于码字结构头部或尾部，FEC码型可以为LDPC(18493,15677)，线路编码可以为256B/257B，能够实现快速同步，提高带宽效率和纠错能力。码字结构还包括填充部分，有效数据和填充部分构成净荷。使得各种FEC码型和各种线路编码均能够有效的兼容和适配。填充部分可以作为同步头，还可以用于指示码字结构的长度或净荷长度等。

Description

数据编译码方法和装置、OLT、ONU和PON系统 技术领域
本发明涉及光通信领域，并且更具体地，涉及一种PON系统中的数据编码和译码方法、数据编码和译码装置、光线路终端、光网络单元和PON系统。
背景技术
无源光网络(Passive Optical Network，PON)技术是一种点到多点的光纤接入技术。PON系统可以包括光线路终端(Optical Line Terminal,OLT)、光分配网络(Optical Distribution Network，ODN)和至少一个光网络单元(Optical Network Unit，ONU)。OLT与ODN连接，ODN与多个ONU连接。
其中以太网无源光网络(Ethernet Passive Optical Network，EPON)技术是一种较好的接入技术。其主要特点在于维护简单，成本较低，较高的传输带宽和高性能价格比。
由于EPON是一种采用无源光传输的技术，不使用具有放大和中继功能的元器件。因此EPON网络的传输距离和分支数目依赖于功率预算和各种传输损耗。随着传输距离或分支比数目的增加，传输数据的信噪比(Signal Noise ratio，SNR)逐渐减小，从而导致更多的比特错误。为了解决这一问题，在EPON系统中引入了FEC技术来提高系统的抗干扰能力，以增大系统的功率预算。
前向纠错编码(Forward Error Correction，FEC)是指信号在被传输之前预先对其按一定的方式进行处理，在接收端则按相应的算法进行解码以达到找出错码并纠错的目的。EPON系统中的FEC的基本工作原理是：在发送端被传输的信息数据后附加上FEC校验码字，这些校验码字与被校验的信息数据以某种确定的规则互相关联(约束)，接收端按既定的规则检验信息数据与校验码字的关系，一旦传输中发生错误，就会破坏这种关系，从而自动发现并纠正错误的码。FEC技术力求用尽可能少的校验字节纠正尽可能多的错误，在开销(增加了校验字节)和获得的编码增益之间找到一个最佳的平衡点。
现有10GEPON和1GEPON采用的FEC码型与线路编码的缺陷在于同步过程复杂，同步速度慢。
发明内容
有鉴于此，本申请提供了一种PON系统中的数据编码和译码方法、数据编码和译码装置、预编码指示方法和装置、光线路终端、光网络单元和PON系统，旨在简化同步过程，实现快速同步。
第一方面，提供了一种PON系统中的数据编码方法，执行主体可以为PON系统中的网络设备，例如，可以为OLT向ONU发送数据，由OLT编码，也可以为ONU向OLT发送数据，由ONU编码，该编码方法在物理编码子层执行，该方法包括：在物理编码子层收集N个数据块组合生成有效数据，N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值除以收集的数据块的长度的商(即N小于或等于所述FEC码型的净荷值与每个数据块的长度的比值)，FEC码型对应设有FEC码字值和净荷值；在物理编码子层生成净荷，净荷包括有效数据，净荷的长度等于该FEC码型的净荷值，根据该FEC码型对净荷进行FEC编码生成校验部分，校验部分的长度等于所述FEC码字值与所述净荷值之差；在物 理编码子层生成码字结构，码字结构包括有效数据、校验部分和同步头，有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，同步时实现简单，可以快速定位同步头。
同步头位于码字结构的头部，或者位于码字结构的尾部，从而能够进一步实现快速同步。同步头还可以位于有效数据与校验部分之间。
收集的数据块可以为128B/129B或256B/257B的数据块，输入至物理编码子层的数据块可以为64B/66B或者64B/65B的数据块，此时，物理编码子层需要将输入的64B/66B或者64B/65B的数据块转码为128B/129B或256B/257B的数据块；通过转码，减小了编码开销，能够有效地提高带宽效率。
或者，收集的所述数据块也可以为64B/66B或者64B/65B的数据块。
前向纠错编码方式为LDPC(18493,15677)、RS(2047,1739)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)或者RS(1019,839)。能够提高纠错能力。
其中FEC码字值等于净荷值加上检验长度值，表示净荷值个有效比特经过FEC编码后生成校验长度值个校验比特，有效比特与校验比特长度之和等于FEC码字值。
在有效数据的长度等于净荷值时，净荷仅由有效数据组成。由于净荷部分全部为有效数据，编码效率高，带宽效率高。
有效数据的长度也可以小于所采用的FEC码型的净荷值，码字结构还包括填充部分，此时，有效数据和填充部分构成净荷。净荷的长度等于所采用的FEC码型的净荷值。即填充部分的长度可以等于净荷值与有效数据长度之差。填充部分的长度也可以等于净荷值除以收集的数据块的长度的余数。通过增加填充字段，可以使得各种FEC码型和各种线路编码均能够有效的兼容和适配。
为了保证输入速率和输出速率保持不变，可以采用以下方式计算同步头的长度：同步头的长度设为S，输入的数据块的长度设为X，FEC码字值除以X的余数设为Y，则S＝tX-Y，且t为整数；其中，在Y≠0时，t≥1；在Y＝0时，t≥0。
在Y＝0，且t＝0时，S＝0。此时，可以将填充部分作为同步头。可以将填充部分全部作为同步头，也可以将填充部分中的部分比特作为同步头。从而不需要额外的比特用作同步头，直接将填充部分用作同步头，可以有效地降低无效数据的比特数，提高带宽效率和编码效率。
填充部分还可以用于指示码字结构的长度，或者有效数据的长度，或者有效数据与校验部分的长度之和，或者净荷的长度，或者净荷与校验部分的长度之和。该填充部分可以指示该填充部分所在码字结构，也可以指示相邻的下一个码字结构或者其他码字结构。或者，码字结构还可以包括指示部分，指示部分用于指示码字结构的长度，或者有效数据的长度，或者有效数据与校验部分的长度之和，或者净荷的长度，或者净荷与校验部分的长度之和。该指示部分可以指示该指示部分所在码字结构，也可以指示相邻的下一个码字结构或者其他码字结构。可以将上述同步头的部分比特用来指示。通过填充部分或指示部分，可以使得目标网络设备获知码字结构的长度，从而实现正确解析。
可以理解的是，上述各个实施细节可以相互结合。例如，可以同时包括填充部分和指 示字段，填充部分的部分比特或全部比特用作同步头。或者，还可以同时包括填充部分和同步头，填充部分的部分比特或全部比特用作同步头，此时相当于有两个同步头。或者，填充部分中的部分比特用作同步头，另外部分比特用于指示码字结构的长度，或者有效数据的长度，或者有效数据与校验部分的长度之和，或者净荷的长度，或者净荷与校验部分的长度之和，此时，可以另外包括上述同步头，也可以不另外包括上述同步头。
第二方面，提供一种PON系统中的数据译码方法，执行主体可以为PON系统中的网络设备，例如，可以为OLT向ONU发送数据，由ONU译码，也可以为ONU向OLT发送数据，由OLT译码，该译码方法由物理编码子层执行，该方法包括：在物理编码子层接收码字结构，码字结构包括有效数据、校验部分和同步头，且有效数据、校验部分和同步头之间相互独立的分布于码字结构内，有效数据由N个数据块组成，N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值，所述FEC码型对应设有FEC码字值和净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；在物理编码子层根据同步头对接收的码字结构进行同步，提取出净荷和校验部分，净荷包括有效数据，且净荷的长度等于净荷值，并根据该FEC码型对净荷进行前向纠错译码。由于有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。
第三方面，提供一种PON系统中的预编码指示方法，该方法可以由OLT的物理编码子层执行，也可以由ONU的物理编码子层执行，该方法包括：物理编码子层在同步头中添加指示码字结构是否经过预编码的指示信息；可以将同步头中预设位置的比特作为该指示信息，具体哪个位置，源网络设备和目标网络设备之间可以约定好。例如，同步头末尾比特为“0”则表示经过预编码；同步头末尾比特为“1”则表示未经过预编码。物理编码子层生成码字结构，码字结构包括净荷、校验数据和同步头；物理编码子层发送码字结构。可以使得目标网络设备能够根据该指示信息确定该码字结构是否经过预编码。
第四方面，提供一种PON系统中的预编码指示方法，该方法可以由OLT的物理编码子层执行，也可以由ONU的物理编码子层执行，该方法包括：物理编码子层接收码字结构，码字结构包括净荷、校验数据和同步头，同步头包括用于指示码字结构是否经过预编码的指示信息；物理编码子层根据同步头中的指示信息确定码字结构是否经过预编码。
可以由目标网络设备通过盲检的方式确定接收到的码字结构是否经过预编码。目标网络设备可以预存第一同步序列和第二同步序列，第一同步序列可以为码字结构预编码之前的原始同步序列，第二同步序列可以为码字结构预编码之后的输出同步序列。若同步头与第一同步序列匹配，则判定码字结构未经过预编码；目标网络设备直接从码字结构中提取有效数据和校验部分。如果同步头与第二同步序列匹配，则判定码字结构经过了预编码，目标网络设备对码字结构进行解预编码；目标网络设备从解预编码后的码字结构中提取有效数据和校验部分。通过在同步头中添加指示码字结构是否经过预编码的指示信息，可以使得目标网络设备能够根据该信息进一步确定之前盲检的结果是否正确，实现双重保险。
第五方面，提供一种PON系统中的预编码指示方法，该方法可以由OLT的MAC子层或处理器执行，也可以由ONU的MAC子层或ONU执行，该方法包括：源网络设备生成数据帧，数据帧包括用于指示该源网络设备是否具有预编码能力、或者目标网络设备是 否需要预编码或解预编码、或者目标网络设备打开或关闭预编码使能位的指示信息；源网络设备向目标网络设备发送数据帧。从而目标网络设备可以根据指示信息，确定是否需要预编码和解预编码。
源网络设备可以为ONU，目标网络设备为OLT，数据帧承载注册请求消息，注册请求消息中包括用于指示ONU是否具有预编码能力的指示信息。通过在数据帧中添加指示该源网络设备是否具有预编码能力的指示信息，从而可以告知目标网络设备是否需要对该源网络设备发送的数据帧进行解预编码，以及告知目标网络设备是否需要对发送给该源网络设备的数据帧进行预编码。
源网络设备可以为OLT，目标网络设备为ONU，数据帧承载发现授权消息，发现授权消息中包括用于指示ONU是否需要预编码或解预编码的指示信息。具体的，OLT可以指示下行发送给ONU的消息是否预编码，也即指示了ONU是否需要对下行接收的数据进行解预编码；也可以指示ONU上行发送给OLT的上行数据是否需要预编码。通过在数据帧中添加指示该数据帧是否预编码的指示信息，可以使得目标网络设备能够根据该信息进一步确定之前盲检的结果是否正确，实现双重保险。另外，通过指示上行或下行是否需要预编码，使得源网络设备和目标网络设备可以根据指示进行预编码和解预编码，不会出错，提高效率。
源网络设备可以为OLT，目标网络设备为ONU，数据帧承载注册消息，注册消息中包括用于指示ONU打开或关闭预编码使能位的指示信息。ONU接收到该指示信息后，打开或关闭预编码使能位。
第六方面，提供一种PON系统中的预编码指示方法，该方法可以由OLT的MAC子层或处理器执行，也可以由ONU的MAC子层或ONU执行，该方法包括：目标网络设备接收源网络设备发送的数据帧，数据帧包括用于指示该数据帧是否预编码、或者该源网络设备是否具有预编码能力、或者目标网络设备是否需要预编码或解预编码的指示信息；目标网络设备根据指示信息确定是否对所述数据帧解预编码，或者确定是否需要对与所述源网络设备传输的数据帧进行预编码和解预编码。
第七方面，提供一种PON系统中的数据编码装置，该装置包括：收集模块，用于收集N个数据块组合生成有效数据，N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值；所述FEC码型对应设有FEC码字值和净荷值；生成模块，用于生成净荷，净荷包括有效数据，且净荷的长度等于净荷值；前向纠错编码模块，用于根据所述FEC码型对净荷进行FEC编码生成校验部分，所述净荷的长度等于所述净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；生成模块还用于生成码字结构，码字结构包括有效数据、校验部分和同步头，有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。
第八方面，提供一种PON系统中的数据译码装置，该装置包括：接收模块，用于接收码字结构，码字结构包括有效数据、校验部分和同步头，且有效数据、校验部分和同步头之间相互独立的分布于码字结构内，所采用的前向纠错译码FEC码型对应设有FEC码字值和净荷值，所述有效数据由N个数据块组成，N为整数，N小于或等于一种FEC码型对应的净荷值与每个所述数据块的长度的比值，所述FEC码型对应设有FEC码字值和净荷值， 所述校验部分的长度等于所述FEC码字值与所述净荷值之差；同步模块，用于根据同步头对接收的码字结构进行同步；提取模块，用于提取出净荷和校验部分，净荷包括有效数据，且净荷的长度等于净荷值；前向纠错译码模块，用于根据所述FEC码型对净荷进行前向纠错译码。由于有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。
第九方面，提供一种PON系统中的预编码指示装置，该装置包括：添加模块，用于在同步头中添加指示码字结构是否经过预编码的指示信息；生成模块，用于生成码字结构，码字结构包括净荷、校验数据和同步头；发送模块，用于发送码字结构。可以使得接收该码字结构的网络设备能够根据该指示信息确定该码字结构是否经过预编码。
第十方面，提供一种PON系统中的预编码指示装置，该装置包括：接收模块，用于接收码字结构，码字结构包括净荷、校验数据和同步头，同步头包括用于指示码字结构是否经过预编码的指示信息；确定模块，用于根据同步头中的指示信息确定码字结构是否经过预编码。通过在同步头中添加指示码字结构是否经过预编码的指示信息，可以使得目标网络设备能够根据该信息进一步确定之前盲检的结果是否正确，实现双重保险。
第十一方面，提供一种PON系统中的预编码指示装置，该装置包括：生成模块，用于生成数据帧，数据帧包括用于指示该数据帧是否预编码、或者该装置是否具有预编码能力、或者目标网络设备是否需要预编码或解预编码的指示信息；发送模块，用于向目标网络设备发送数据帧。从而目标网络设备可以根据指示信息，确定是否需要预编码和解预编码。
第十二方面，提供一种PON系统中的预编码指示装置，该装置包括：接收模块，用于接收源网络设备发送的数据帧，数据帧包括用于指示该数据帧是否预编码、或者该源网络设备是否具有预编码能力、或者该装置是否需要预编码或解预编码的指示信息；确定模块，用于根据指示信息确定是否对数据帧解预编码，或者确定是否需要对与源网络设备传输的数据帧进行预编码和解预编码。
第十三方面，提供一种网络设备，该网络设备可以为OLT，也可以为ONU。该网络设备可以包括芯片，该芯片可以为MAC芯片。该芯片在物理编码子层收集N个数据块组合生成有效数据；所述N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值；所述FEC码型对应设有FEC码字值和净荷值；在物理编码子层生成净荷，净荷包括有效数据，且所述净荷的长度等于所述净荷值；在物理编码子层根据FEC码型对净荷进行FEC编码生成校验部分，校验部分的长度等于所述FEC码字值与所述净荷值之差；在物理编码子层生成码字结构，码字结构包括有效数据、校验部分和同步头，有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。
第十四方面，提供一种网络设备，该网络设备可以为OLT，也可以为ONU。该网络设备可以包括芯片，该芯片可以为MAC芯片。该芯片在物理编码子层接收码字结构，码字结构包括有效数据、校验部分和同步头，且有效数据、校验部分和同步头之间相互独立的分布于码字结构内，所述有效数据由N个数据块组成，N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值，所述FEC码型对应设 有FEC码字值和净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；在物理编码子层根据同步头对接收的码字结构进行同步，提取出净荷和校验部分，净荷包括所述有效数据，且所述净荷的长度等于所述净荷值，并根据该FEC码型对净荷进行前向纠错译码。由于有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。该网络设备可以包括芯片，该芯片可以为MAC芯片，该MAC芯片包括上述物理编码子层。
第十五方面，提供一种网络设备，该网络设备可以为OLT，也可以为ONU。该网络设备包括物理编码子层，物理编码子层在同步头中添加指示码字结构是否经过预编码的指示信息；可以将同步头中预设位置的比特作为该指示信息，具体哪个位置，源网络设备和目标网络设备之间可以约定好。例如，同步头末尾比特为“0”则表示经过预编码；同步头末尾比特为“1”则表示未经过预编码。物理编码子层生成码字结构，码字结构包括净荷、校验数据和同步头；物理编码子层发送码字结构。可以使得目标网络设备能够根据该指示信息确定该码字结构是否经过预编码。该网络设备可以包括芯片，该芯片可以为MAC芯片，该MAC芯片包括上述物理编码子层。
第十六方面，提供一种网络备，该网络设备可以为OLT，也可以为ONU。该网络设备包括物理编码子层，物理编码子层接收码字结构，码字结构包括净荷、校验数据和同步头，同步头包括用于指示码字结构是否经过预编码的指示信息；物理编码子层根据同步头中的指示信息确定码字结构是否经过预编码。该网络设备可以包括芯片，该芯片可以为MAC芯片，该MAC芯片包括上述物理编码子层。
第十七方面，提供一种网络设备，该网络设备可以为OLT，也可以为ONU。该网络设备包括MAC子层、处理器和收发器，该MAC子层或处理器生成数据帧，数据帧包括用于指示该网络设备是否具有预编码能力、或者目标网络设备是否需要预编码或解预编码、或者目标网络设备打开或关闭预编码使能位的指示信息；收发器向目标网络设备发送数据帧。从而目标网络设备可以根据指示信息，确定是否需要预编码和解预编码。
第十八方面，提供一种网络设备，该网络设备可以为OLT，也可以为ONU。该网络设备包括MAC子层、处理器和收发器，该收发器接收源网络设备发送的数据帧，数据帧包括用于指示该数据帧是否预编码、或者该源网络设备是否具有预编码能力、或者该网络设备是否需要预编码或解预编码的指示信息；该MAC子层或处理器根据所述指示信息确定是否对数据帧解预编码，或者确定是否需要对与源网络设备传输的数据帧进行预编码和解预编码。
可以理解的是，不同实施例之间的保护主题不同，但是具体实施细节可以相互参考，某些保护主题没有具体阐述实施细节，可以参考其他各个主题。
第十九方面，提供一种光线路终端，该光线路终端包括上述第七至第十二方面任一项所述的装置，或者该光线路终端包括上述第十三至第十八方面任一项所述的网络设备。
第二十方面，提供一种光网络单元，该光网络单元包括上述第七至第十二方面任一项所述的装置，或者该光网络单元包括上述第十三至第十八方面任一项所述的网络设备。
本申请的又一方面，提供一种码字结构，该码字结构包括净荷、校验部分和同步头，校验部分为对净荷FEC生成的，净荷包括有效数据，有效数据由N个数据块组成，每一 FEC码型对应设有FEC码字值和净荷值，N为整数，N小于或等于所述净荷值除以所述数据块的长度的商，所述净荷的长度等于所述净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；有效数据、所述校验部分和所述同步头之间相互独立的分布于所述码字结构内。
同步头的具体细节、数据块的具体细节、FEC码型的具体细节、码字结构的具体细节等均可以参照其他各个方面，在此不再赘述。
本申请的又一方面，提供一种MAC芯片，该MAC芯片包括上述第七至第十二方面任一项所述的装置。
本申请的又一方面，提供一种PON系统，该系统包括上述第十九方面所述的光线路终端和第二十方面所述的光网络单元。
本申请的又一方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有上述第七至第十二方面任一项所述的装置所用的计算机软件指令，或者存储有上述第十三至第十八方面任一项所述的网络设备所用的计算机软件指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
附图说明
图1为依照本发明一实施例的PON系统的架构示意图；
图2为依照本发明一实施例的数据编译码方法的示范性流程图；
图3(a)为依照本发明一实施例的数据块转码的一示意图；
图3(b)为依照本发明一实施例的数据块转码的另一示意图；
图3(c)为依照本发明一实施例的数据块转码的又一示意图；
图3(d)为依照本发明一实施例的数据块转码的再一示意图；
图3(e)为依照本发明一实施例的数据块转码的再一示意图；
图3(f)为依照本发明一实施例的数据块转码的再一示意图；
图4(1)为依照本发明一实施例的FEC编码与线路编码结合的一示意图；
图4(2)为依照本发明一实施例的FEC编码与线路编码结合的另一示意图；
图4(3)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(4)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(5)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(6)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(7)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(8)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(9)为依照本发明一实施例的FEC编码与线路编码结合的另一示意图；
图4(10)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(11)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(12)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(13)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(14)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(15)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(16)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(17)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图4(18)为依照本发明一实施例的FEC编码与线路编码结合的又一示意图；
图5为依照本发明一实施例的预编码指示方法的示范性流程图；
图6为依照本发明另一实施例的预编码指示方法的示范性流程图；
图7为依照本发明一实施例的网络设备的硬件结构示意图；
图8为依照本发明一实施例的数据编码装置一示范性功能模块示意图；
图9为依照本发明一实施例的数据译码装置另一示范性功能模块示意图。
具体实施方式
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例的技术方案，可以应用于各种以太网无源光网络(Ethernet Passive Optical Network，EPON)和吉比特无源光网络(Gigabit Passive Optical Network，GPON)中，如10G EPON、单波25G EPON、2ⅹ25G EPON、单波50G EPON、2ⅹ50G EPON以及100G EPON等，以及各种GPON中。
图1为适用本发明各个实施例的PON系统的架构示意图，如图1所示，PON系统100包括至少一个OLT110、至少一个ODN120和多个ONU130。其中，OLT110为PON系统100提供网络侧接口，ONU130为PON系统100提供用户侧接口，与ODN 120相连。如果ONU 130直接提供用户端口功能，则称为光网络终端(Optical Network Terminal，ONT)。为了便于描述，下文所提到的ONU130统指可以直接提供用户端口功能的ONT和提供用户侧接口的ONU。ODN 120是由光纤和无源分光器件组成的网络，用于连接OLT 110设备和ONU 130设备，用于分发或复用OLT 110和ONU 130之间的数据信号。
在该PON系统100中，从OLT 110到ONU 130的方向定义为下行方向，而从ONU 130到OLT 110的方向定义为上行方向。在下行方向，OLT 110采用时分复用(Time Division Multiplexing，TDM)方式将下行数据广播给该OLT 110管理的多个ONU 130，各个ONU 130只接收携带自身标识的数据；而在上行方向，多个ONU 130采用时分多址(Time Division Multiple Access，TDMA)的方式与OLT 110进行通信，每个ONU 130按照OLT 110为其分配的时域资源发送上行数据。采用上述机制，OLT 110发送的下行光信号为连续光信号，而ONU 130发送的上行光信号为突发光信号。
该OLT 110通常位于中心局(Central Office，CO)，可以统一管理至少一个ONU 130，并在ONU 130与上层网络之间传输数据。具体来说，该OLT 110可以充当ONU 130与所述上层网络(比如因特网、公共交换电话网络(Public Switched Telephone Network，PSTN)之间的媒介，将从上层网络接收到的数据转发到ONU 130，以及将从ONU 130接收到的数据转发到该上层网络。该OLT 110的具体结构配置可能会因该PON系统100的具体类型而 异，比如，在一种实施例中，该OLT 110可以包括发射机和接收机，该发射机用于向ONU130发送下行连续光信号，该接收机用于接收来自ONU 130的上行突发光信号，其中该下行光信号和上行光信号可以通过该ODN 120进行传输，但本发明实施例不限于此。
该ONU 130可以分布式地设置在用户侧位置(比如用户驻地)。该ONU 130可以为用于与OLT 110和用户进行通信的网络设备，具体而言，该ONU 130可以充当OLT 110与用户之间的媒介，例如，ONU 130可以将从该OLT 110接收到的数据转发到用户，以及将从该用户接收到的数据转发到OLT 110。
该ODN 120可以是一个数据分发网络，可以包括光纤、光耦合器、分光器或其他设备。在一个实施例中，该光纤、光耦合器、分光器或其他设备可以是无源光器件，具体来说，该光纤、光耦合器、分光器或其他设备可以是在OLT 110和ONU 130之间分发数据信号时不需要电源支持的器件。具体地说，以光分路器(Splitter)为例，该光分路器可以通过主干光纤连接到OLT 110，并分别通过多个分支光纤连接到多个ONU 130，从而实现OLT 110和ONU 130之间的点到多点连接。另外，在其他实施例中，该ODN 120还可以包括一个或多个处理设备，例如，光放大器或者中继设备(Relay device)。另外，ODN 120具体可以从OLT 110延伸到多个ONU 130，但也可以配置成其他任何点到多点的结构，本发明实施例不限于此。
下文所描述的本发明实施例的技术方案，可以是OLT110进行编码生成码字结构，并将码字结构发送至ONU130，由ONU130对码字结构进行译码；也可以是ONU130编码码字结构，并将码字结构发送至OLT110，由OLT110对码字结构进行译码。为了便于描述，以下将OLT110和ONU130中作为发送方的设备称为源网络设备，作为接收方的设备称为目标网络设备。
为此，以下提出一种数据编译码方法，下面将结合附图，对本发明实施例所提供的数据编译码方法进行详细的描述，如图2所示，该方法包括步骤S200至S209，各个步骤的具体实施方式如下：
S200，源网络设备的物理编码子层接收输入的64B/66B或者64B/65B的数据块。
在本实施例中，输入的数据块指需要传输的数据内容。物理编码子层也称为PCS(Physical Coding Sublayer)子层。
64B/66B的数据块是指该数据块总长度为66比特，其中含有64比特的数据，还有2比特的指示信息，用于指示该数据块内64比特的数据为数据信息还是控制信息。该2比特的指示信息可以位于数据块的头部或尾部。
同理，64B/65B的数据块是指该数据块总长度为65比特，其中含有64比特的数据，还有1比特的指示信息，用于指示该数据块内64比特的数据为数据信息还是控制信息。该1比特的指示信息可以位于数据块的头部或尾部。
同理，以下实施例中所描述的128B/129B、256B/257B的数据块与上述类似，在此不再赘述。
S201，所述源网络设备的物理编码子层将输入的64B/66B或者64B/65B的数据块转码为128B/129B或256B/257B的数据块；步骤S201为可选项。若步骤S202中收集的数据块为64B/66B或者64B/65B的数据块，则步骤S201可以省去。若步骤S202中收集的数据块 为128B/129B、256B/257B的数据块，则步骤S201可以执行。
64B/66B的数据块转码为128B/129B的数据块如图3(a)至(d)所示，每2个64B/66B的数据块转码为一个128B/129B的数据块。
64B/66B的数据块分为两种类型，一种为携带数据信息的数据块，另一种为携带控制信息的数据块。以图3(a)至(d)为例，数据块中的2比特指示信息为“01”，表示该数据块的64比特为数据信息；数据块中的2比特指示信息为“10”，表示该数据块的64比特为控制信息。
图3(a)为2个携带数据信息的64B/66B的数据块转码为1个128B/129B的数据块。可以分别将2个64B/66B的数据块的2比特指示信息去除，并添加1比特的指示信息来转码后的数据块所携带的128比特的数据类型(包括数据信息和控制信息两种类型)。如图3(a)所示，DB1(64)和DB2(64)分别表示两个数据块中的64比特的数据信息。
图3(b)为2个携带控制信息的64B/66B的数据块转码为1个128B/129B的数据块。携带控制信息的64B/66B的数据块中包括4比特的S1(4)，可以将其中一个数据块中的4比特的S1(4)删除，并保留2个64B/66B的数据块的2比特指示信息，并另外添加1比特。转码后的129比特的数据块中各个信息的排布规则可以根据实际需要进行设置，实现互通。以图3(b)为例，将另外添加的1比特置于数据块头部，之后分别为2个64B/66B的数据块的2比特指示信息，然后为去除4比特的S1(4)的64B/66B的数据块中的控制信息，然后为未去除4比特的S1(4)的64B/66B的数据块中的控制信息。可以理解的是，也可以采用其他方式排布。
图3(c)为1个携带控制信息的64B/66B的数据块和1个携带数据信息的64B/66B的数据块转码为1个128B/129B的数据块。携带控制信息的64B/66B的数据块中包括4比特的S1(4)，可以将该数据块中的4比特的S1(4)删除，并保留2个64B/66B的数据块的2比特指示信息，并另外添加1比特。转码后的129比特的数据块中各个信息的排布规则可以根据实际需要进行设置，实现互通。以图3(c)为例，将另外添加的1比特置于数据块头部，之后分别为携带控制信息和携带数据信息的64B/66B的数据块的2比特指示信息，然后为去除4比特的S1(4)的64B/66B的数据块中的控制信息，然后为携带数据信息的64B/66B的数据块中的数据信息。可以理解的是，也可以采用其他方式排布。
图3(d)为1个携带数据信息的64B/66B的数据块和1个携带控制信息的64B/66B的数据块转码为1个128B/129B的数据块。与图3(c)不同的是，另外添加的1比特置于数据块头部，之后分别为携带数据信息和携带控制信息的64B/66B的数据块的2比特指示信息，然后为携带数据信息的64B/66B的数据块中的数据信息，然后为去除4比特的S1(4)的64B/66B的数据块中的控制信息。可以理解的是，也可以采用其他方式排布。
图3(e)为2个携带数据信息的64B/65B的数据块转码为1个128B/129B的数据块。可以分别将2个64B/65B的数据块的1比特指示信息去除，并添加1比特的指示信息来转码后的数据块所携带的128比特的数据类型(包括数据信息和控制信息两种类型)。如图3(e)所示，DB1(64)和DB2(64)分别表示两个数据块中的64比特的数据信息。
图3(f)为4个携带数据信息的64B/65B的数据块转码为1个256B/257B的数据块。可以分别将4个64B/65B的数据块的1比特指示信息去除，并添加1比特的指示信息来转码 后的数据块所携带的256比特的数据类型(包括数据信息和控制信息两种类型)。如图3(f)所示，DB1(64)、DB2(64)、DB3(64)、DB4(64)分别表示四个数据块中的64比特的数据信息。
64B/66B的数据块转码为256B/257B的数据块时，每4个64B/66B的数据块转码为1个256B/257B的数据块，具体转码原理与上述类似，可以保留有效的数据信息和控制信息，去除指示信息或者S1(4)，也可以另外添加1比特或者更多的比特，总之转码后的数据块不丢失有效数据，且总比特数为256B即可。
64B/65B的数据块转码为128B/129B或256B/257B的数据块的具体实现方案，可以参照上述64B/66B的数据块的转码方案，在此不再赘述。
通过转码，可以有效地提高带宽效率。
在一实施例中，转码之后，还可以对数据块进行加扰，步骤S202中收集的数据块为加扰后的数据块。
S202，源网络设备的物理编码子层收集N个数据块组合生成有效数据；
源网络设备收集的N个数据块可以为256B/257B的数据块(即线路编码为256B/257B)，也可以为128B/129B的数据块(即线路编码为128B/129B)，也可以为64B/66B的数据块(即线路编码为64B/66B)，也可以为64B/65B的数据块(即线路编码为64B/65B)。收集的N个数据块中，各个数据块的长度相同。即，N个数据块全部为256B/257B的数据块，或者全部为128B/129B的数据块，或者全部为64B/66B的数据块，或者全部为64B/65B的数据块。
S203，物理编码子层生成净荷，净荷包括有效数据；
S204，源网络设备的物理编码子层对所述净荷进行FEC生成校验部分，每一FEC码型对应设有FEC码字值和净荷值，N为整数，N小于或等于净荷值除以收集的数据块的长度的商(即N小于或等于所述净荷值与每个所述数据块的长度的比值)，净荷的长度等于净荷值，校验部分的长度等于所述FEC码字值与所述净荷值之差；
S205，源网络设备的物理编码子层生成码字结构，码字结构包括有效数据、校验部分和同步头。
FEC码型可以包括低密度奇偶校验编码(Low Density Parity Check Code，LDPC)和里得—索罗门编码(Reed-Solomon code，RS)，例如可以为LDPC(18493,15677)、RS(2047,1739)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)或者RS(1019,839)等等，并不限于以上列举的几种。
每一所述FEC码型对应设有FEC码字值和净荷值，如LDPC(18493,15677)，粒度为1比特，表示FEC码字值为18493ⅹ1比特，净荷值为15677ⅹ1比特；又如RS(1023,847)，粒度为10比特，表示FEC码字值为1023ⅹ10比特，净荷值为847ⅹ10比特。其他FEC码型类似，在此不再赘述。RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)和RS(1019,839)的粒度均为10比特。RS(2047,1739)的粒度为11比特，表示FEC码字值为2047ⅹ11＝22517比特，净荷值为1739ⅹ11＝19129比特。
可以理解的是，FEC码型也可以采用其他表达方式，例如可以间接指示出FEC码字值和净荷值。
其中FEC码字值等于净荷值加上检验长度值，表示净荷值个有效比特经过FEC编码后生成校验长度值个校验比特，有效比特与校验比特长度之和等于FEC码字值。例如，LDPC(18493,15677)，表示对15677比特的数据进行FEC后，生成2816比特的校验数据，FEC后的数据总长变为18493比特。又如RS(1023,847)，表示对8470比特的数据进行FEC后，生成1760比特的校验数据，FEC后的数据总长变为10230比特。
有效数据的长度小于或等于所采用的FEC码型的净荷值。可以通过调整N值，来调整有效数据长度。N为整数，N值可以等于净荷值除以收集的所述数据块的长度的商。N值也可以小于净荷值除以收集的所述数据块的长度的商。N可以等于1，此时，净荷包括一个数据块。N也可以大于或等于2。
在一实施方式中，有效数据的长度等于所采用的FEC码型的净荷值。此时，净荷全部由有效数据组成。即，净荷值除以收集的数据块的长度等于整数，即为整数N。此时，有效数据也可以称作净荷。以LDPC(18493,15677)为例，假设收集的数据块为256B/257B的数据块，由于15677/257＝61，即上述N取值为61，61个256B/257B的数据块生成的有效数据长度为15677。该方式中，净荷部分全部为有效数据，编码效率高，带宽效率高。
在另一实施方式中，有效数据的长度小于所采用的FEC码型的净荷值。码字结构还包括填充部分，此时，有效数据和填充部分构成净荷，有效数据与所述填充部分的长度之和等于所述净荷值。净荷的长度等于所采用的FEC码型的净荷值。即填充部分的长度可以等于净荷值与有效数据长度之差。填充部分的长度也可以等于净荷值除以收集的数据块的长度的余数。例如，以LDPC(18493,15677)为例，收集的数据块为128B/129B的数据块，由于15677除以129的商为121，余数为68，即上述N取值为121,121个128B/129B的数据块生成的有效数据长度为15609，还需要填充68个比特作为所述填充部分，使得有效数据与填充部分的长度之和等于净荷值15677。则步骤S203具体为：源网络设备的物理编码子层对净荷进行FEC生成校验部分。源网络设备可以对由有效数据和填充部分组成的15677比特的字段作为一整体进行FEC生成校验部分。该方式中，通过增加填充字段，可以使得各种FEC码型和各种线路编码均能够有效的兼容和适配。
在本实施例中，校验部分和有效数据内不含同步头，也即同步头不会分布于校验部分和有效数据内部。在本实施例中，有效数据、校验部分和同步头之间相互独立的分布于码字结构内。
同步头可以位于码字结构的头部，或者位于所述码字结构的尾部，能够进一步实现快速同步。
同步头也可以位于所述有效数据与所述校验部分之间。
为了保证输入速率和输出速率保持不变，可以采用以下方式计算同步头的长度：同步头的长度设为S，输入的数据块的长度设为X，FEC码字值除以X的余数设为Y，则S＝tX-Y，且t为整数；其中，在Y≠0时，t≥1；在Y＝0时，t≥0。
例子1：
FEC码型为LDPC(18493,15677)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。
如图4(1)所示，15677/257＝61，因此码字结构可以不需要填充部分。N值为61，有效 数据由61个256B/257B的数据块生成，有效数据长度为15677，即净荷长度为15677比特，可以满足FEC需求。校验部分的长度为2816比特。
61个256B/257B的数据块可以由61*4＝244个64B/66B的数据块转码生成。
由于18493/66＝280.197，因此为了保证输入速率和输出速率保持不变，还需要另外生成一定数量的66比特的占位块(即每个占位块大小为66比特)，使得占位块的数量与输入的数据块的数量之和至少为281个。如图4(1)，本实施例以281个为例(相当于上述t＝1)。因此需要281-244＝37个占位块。此时能够使得编码效率最大化，提高带宽效率。
281*66＝18546,18546-18493＝53。因此，同步头的长度为53比特。
同理，当占位块的数量为38个时，相当于上述t＝2，同步头的长度为119比特。以此类推。
例子2：
FEC码型为LDPC(18493,15677)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。
如图4(2)所示，15677除以129的商为121，余数为68，因此码字结构需要填充部分，填充部分的长度为68。N值为121，有效数据由121个128B/129B的数据块生成，有效数据长度为15609，有效数据长度与填充部分长度之和为15677，即净荷为15677比特，可以满足FEC需求。校验部分的长度为2816比特。
121个128B/129B的数据块可以由121*2＝242个64B/66B的数据块转码生成。
由于18493/66＝280.197，因此为了保证输入速率和输出速率保持不变，还需要另外生成一定数量的66比特的占位块(即每个占位块大小为66比特)，使得占位块的数量与输入的数据块的数量之和至少为281个。如图4(2)，本实施例以281个为例(相当于上述t＝1)。因此需要281-242＝39个占位块。
281*66＝18546,18546-18493＝53。因此，同步头的长度为53比特。
同理，当占位块的数量为40个时，相当于上述t＝2，同步头的长度为119比特。以此类推。
例子3：
FEC码型为LDPC(18493,15677)，收集的数据块为64B/66B的数据块。计算过程同上述例子，在此不再赘述。如图4(3)所示，有效数据由237个64B/66B的数据块生成，有效数据长度为15642比特，填充部分长度为35比特，校验部分长度为2816比特，t＝1时，同步头的长度为53比特。
例子4：
FEC码型为RS(1023,847)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。FEC码字值为10230，净荷值为8470。
如图4(4)所示，8470除以129的商为65，余数为85，因此码字结构需要填充部分，填充部分的长度为85。N值为65，有效数据由65个128B/129B的数据块生成，有效数据长度为8385，有效数据长度与填充部分长度之和为8470，即净荷长度为8470，可以满足FEC需求。校验部分的长度为1760比特。
65个128B/129B的数据块可以由65*2＝130个64B/66B的数据块转码生成。
由于10230/66＝155，余数为0，相当于上述Y＝0的情形，为了保证输入速率和输出速率保持不变，还需要另外生成一定数量的66比特的占位块(即每个占位块大小为66比特)，使得占位块的数量与输入的数据块的数量之和至少为155个。以155个为例(相当于上述t＝0)。因此需要155-130＝25个占位块。此时没有多余的比特用作同步头，但可以直接将填充部分作为同步头。可以将全部的填充部分作为同步头，例如，将85比特全部用作同步。也可以将部分填充部分作为同步头，例如，将填充部分中的50比特用作同步。从而不需要额外的比特用作同步头，直接将填充部分用作同步头，可以有效地降低无效数据的比特数，提高带宽效率和编码效率。
可以理解的是，占位块的数量也可以为26个，相当于t＝1，此时同步头的长度为66比特。以此类推。
例子5：
FEC码型为RS(1023,847)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。FEC码字值为10230，净荷值为8470。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(5)，有效数据为8224比特，填充部分为246比特。
例子6：
FEC码型为RS(1023,847)，收集的数据块为64B/66B的数据块。FEC码字值为10230，净荷值为8470。具体计算过程同上，在此不再赘述，具体原理可以参照图4(6)，有效数据为8448比特，填充部分为22比特。
例子7：
FEC码型为RS(2047,1739)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(7)，有效数据为19018比特，填充部分为111比特，同步头为55比特，校验部分为3388比特。
例子8：
FEC码型为RS(2047,1739)，输入的数据块为64B/66B的数据块，64B/66B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(8)，有效数据为19092比特，填充部分为37比特，同步头为55比特，校验部分为3388比特。
例子9：
FEC码型为RS(2047,1739)，输入的数据块为64B/66B的数据块，收集的数据块为64B/66B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(9)，有效数据为19074比特，填充部分为55比特，同步头为55比特，校验部分为3388比特。
例子10：
FEC码型为LDPC(18493,15677)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。FEC码字值为18493，净荷值为15677。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(10)，有效数据为15677比特，没有填充部分，同步头为32比特，校验部分为2816比特。
例子11：
FEC码型为LDPC(18493,15677)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。FEC码字值为18493，净荷值为15677。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(11)，有效数据为15609比特，填充部分为68比特，同步头为32比特，校验部分为2816比特。
例子12：
FEC码型为LDPC(18493,15677)，输入的数据块为64B/65B的数据块，收集的数据块为64B/65B的数据块。FEC码字值为18493，净荷值为15677。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(12)，有效数据为15665比特，填充部分为12比特，同步头为32比特，校验部分为2816比特。
例子13：
FEC码型为RS(1023,847)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。FEC码字值为10230，净荷值为8470。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(13)，有效数据为8224比特，填充部分为246比特，同步头为40比特，校验部分为1760比特。
例子14：
FEC码型为RS(1023,847)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。FEC码字值为10230，净荷值为8470。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(14)，有效数据为8385比特，填充部分为85比特，同步头为40比特，校验部分为1760比特。
例子15：
FEC码型为RS(1023,847)，输入的数据块为64B/65B的数据块，收集的数据块为64B/65B的数据块。FEC码字值为10230，净荷值为8470。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(15)，有效数据为8450比特，填充部分为20比特，同步头为40比特，校验部分为1760比特。
例子16：
FEC码型为RS(2047,1739)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为256B/257B的数据块，收集的数据块为256B/257B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(16)，有效数据为19018比特，填充部分为111比特，同步头为38比特，校验部分为3388比特。
例子17：
FEC码型为RS(2047,1739)，输入的数据块为64B/65B的数据块，64B/65B的数据块转码为128B/129B的数据块，收集的数据块为128B/129B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(17)，有效数据为19092比特，填充部分为37比特，同步头为38比特，校验部分为3388比特。
例子18：
FEC码型为RS(2047,1739)，输入的数据块为64B/65B的数据块，收集的数据块为64B/65B的数据块。FEC码字值为22517，净荷值为19129。
具体计算过程同上，在此不再赘述，具体原理可以参照图4(18)，有效数据为19110比特，填充部分为19比特，同步头为38比特，校验部分为3388比特。
对于其他FEC码型，如RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)以及RS(1019,839)等，原理同上，在此不再赘述。
可以理解的是，还可以采用其他FEC码型，如RS方式的FEC码字值不限于上述10230、20470、10150、10170、10190等，也可以为10210或其他数值。RS方式的净荷值不限于上述8390、8310、8330、8350、17390等，也可以为8370、17310或其他数值等。且上述各个FEC码字值与各个净荷值之间可以自由组合构成一种RS方式，只要能够满足上述计算原理即可。
在一实施例中，有多余的比特用作同步头时(例如FEC码字值除以输入的信息块的长度的余数不为0时)，也可以同时将填充部分作为同步头，可以将全部的填充部分用作同步头，也可以将部分填充部分作为同步头。在一个例子中，同步头的长度较短不足以满足同步需求时，可以同时将填充部分作为同步头，可以将全部的填充部分用作同步头，也可以将部分填充部分作为同步头。
在一实施例中，填充部分还用于指示码字结构的长度，或者有效数据的长度，或者有效数据与校验部分的长度之和，或者净荷的长度，或者净荷与校验部分的长度之和。可以将填充部分的部分比特或全部比特用来指示。
在另一实施例中，码字结构还包括指示部分，指示部分用于指示码字结构的长度，或者有效数据的长度，或者有效数据与校验部分的长度之和，或者净荷的长度，或者净荷与校验部分的长度之和。可以将上述同步头的部分比特用来指示。
例如，在上行方向可能会出现突发尾截断，导致有效数据长度小于FEC编码的净荷值，或者有效数据与填充部分长度之和小于FEC编码的净荷值，如采用LDPC(18493,15677)时，上行发送的最后一个码字结构的有效数据长度可能小于15677，或者上行发送的最后一个码字结构的有效数据与填充部分长度之和可能小于15677。因此，通过填充部分或指示部分，可以使得目标网络设备获知码字结构的长度，从而实现正确解析。
S206，目标网络设备的物理编码子层接收码字结构。
S207，目标网络设备的物理编码子层根据同步头对接收到的码字结构进行同步。
例如，目标网络设备可以预存同步序列，在接收的码字结构中遍历预存的同步序列，直至码字结构中的同步头与预存的同步序列匹配，则同步完成。
S208，目标网络设备的物理编码子层提取出净荷和校验部分；
S209，目标网络设备的物理编码子层使用提取的校验部分对净荷进行前向纠错译码。
可以理解的是，这里的前向纠错译码与上述前向纠错编码相对应，可以采用同一种表达方式，如前向纠错译码方式为LDPC(18493,15677)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(2047,1739)、RS(1015,839)、RS(1017,839)或者RS(1019,839)。以LDPC(18493,15677)为例，目标网络设备使用2816比特的校验数据字段对15677比特的有效数据进行前向纠错译码。
可以理解的是，在码字结构包括填充部分时，S210具体为：目标网络设备使用校验部分对有效数据和填充部分进行前向纠错译码。
具体细节可以参照上述前向纠错编码的表述，在此不再赘述。
本发明实施例提供的数据编译码方法，生成的码字结构中包括有效数据、检验部分和同步头，有效数据、校验部分和同步头之间相互独立的分布于码字结构内，从而能够实现快速同步，提高带宽效率和纠错能力。
本发明还提供一种预编码指示方法。本发明实施例中涉及的源网络设备和目标网络设备的具体细节可以参照上述实施例，在此不再赘述。源网络设备向目标网络设备发送码字结构，可以对码字结构进行预编码，也可以不进行预编码，可以通过指示信息来指示是否对码字结构进行了预编码，目标网络设备可以根据该指示信息确定码字结构是否经过了预编码，进而进一步确定是否需要对码字结构进行解预编码。本实施例中的同步头的具体细节可以参照上述数据编译码方法的实施例，在此不再赘述。
如图5所示，该预编码指示方法包括：
S301，源网络设备的物理编码子层在同步头中添加指示码字结构是否经过预编码的指示信息；
例如，可以将同步头中预设位置的比特作为该指示信息，具体哪个位置，源网络设备和目标网络设备之间可以约定好。例如，同步头末尾比特为“0”则表示经过预编码；同步头末尾比特为“1”则表示未经过预编码。
具体的，可以采用异或的方式进行预编码。
在一实施例中，可以采用一个预设的初始比特与原始码字结构的第一位比特进行异或，所得到的一位比特作为输出码字结构的第一位比特；然后将原始码字结构的第二位比特与输出码字结构的第一位比特进行异或，所得到的一位比特作为输出码字结构的第二位比特；然后将原始码字结构的第三位比特与输出码字结构的第二位比特进行异或，所得到的一位比特作为输出码字结构的第三位比特，以此类推，直至将原始码字结构的最后一位比特与输出码字结构的倒数第二位比特进行异或，所得到的一位比特作为输出码字结构的最后一位比特。
预设的初始比特可以为“0”，也可以为“1”。
例如，原始码字结构中的一段原始序列假设为“0110101110”。预设的初始比特为“0”时，输出序列为“0100110100”；预设的初始比特为“1”时，输出序列为“1011001011”。
在另一实施例中，也可以采用一个预设的初始比特分别与原始码字结构的每一位比特进行异或，即，初始比特与原始码字结构第一位比特异或得到输出码字结构的第一位比特，初始比特与原始码字结构第二位比特进行异或得到输出码字结构的第二位比特，以此类推。
S302，源网络设备的物理编码子层生成码字结构，码字结构包括净荷、校验数据和同步头；该码字结构的具体细节可以参照上述各个实施例，在此不再赘述。码字结构与上述实施例不同的是，同步头中添加了指示该码字结构是否经过预编码的指示信息。
S303，源网络设备的物理编码子层发送所述码字结构。
物理编码子层可以发送码字结构至源网络设备的物理介质连接(Physical Medium Attachment,PMA)子层，进行后一步的处理。
S304，目标网络设备的物理编码子层接收码字结构；目标网络设备的物理编码子层可以接收目标网络设备的PMA子层的发送的码字结构。
S305，目标网络设备的物理编码子层根据所述同步头对接收的所述码字结构进行同步；
在一实施例中，源网络设备和目标网络设备可以预先约好是否预编码，还可以预先约好预编码的初始比特。从而目标网络设备接收到码字结构后，可以根据预先约定决定是否解预编码，以及解预编码所采用的初始比特。具体的，在源网络设备和目标网络设备预先约定好不进行预编码时，目标网络设备可以直接根据预存的同步序列对码字结构进行同步。在源网络设备和目标网络设备预先约定好进行预编码时，则目标网络设备可以先对码字结构进行解预编码，然后再根据预存的同步序列对码字结构进行同步；也可以先同步，再解预编码。
在另一实施例中，源网络设备也可以不和目标网络设备预先约定是否预编码。可以由目标网络设备通过盲检的方式确定接收到的码字结构是否经过预编码。
具体的，目标网络设备可以预存第一同步序列和第二同步序列，第一同步序列可以为码字结构预编码之前的原始同步序列，第二同步序列可以为码字结构预编码之后的输出同步序列，可以理解的是，第二同步序列可以有两种，一种为采用原始比特“0”进行预编码输出的同步序列，另一种为采用原始比特“1”预编码输出的同步序列。
若同步头与第一同步序列匹配，则判定码字结构未经过预编码；目标网络设备直接从码字结构中提取有效数据和校验部分。
如果同步头与第二同步序列匹配，则判定码字结构经过了预编码，目标网络设备对码字结构进行解预编码；目标网络设备从解预编码后的码字结构中提取有效数据和校验部分。
S306，目标网络设备的物理编码子层根据同步头中的指示信息确定码字结构是否经过预编码。
本实施例中，通过在同步头中添加指示码字结构是否经过预编码的指示信息，可以使得目标网络设备能够根据该信息进一步确定之前盲检的结果是否正确，实现双重保险。
本发明还提供一种预编码指示方法。本发明实施例中涉及的源网络设备和目标网络设备的具体细节可以参照上述实施例，在此不再赘述。源网络设备向目标网络设备发送数据帧，可以对数据帧进行预编码，也可以不进行预编码，可以通过指示信息来指示是否对数据帧进行了预编码，目标网络设备可以根据该指示信息确定数据帧是否经过了预编码，进 而进一步确定是否需要对数据帧进行解预编码。该方法可以由MAC控制子层执行，也可以由处理器执行，如图6所示，该方法包括：
S401，源网络设备生成数据帧，数据帧包括用于指示该源网络设备是否具有预编码能力、或者目标网络设备是否需要预编码或解预编码、或者所述目标网络设备打开或关闭预编码使能位的指示信息；
S402，源网络设备向目标网络设备发送数据帧。
S403，目标网络设备接收源网络设备发送的数据帧；
S404，目标网络设备根据指示信息确定是否对数据帧解预编码，或者确定是否需要对与源网络设备传输的数据帧进行预编码和解预编码。
可以理解的是，该目标网络设备同样需要对数据帧进行同步，具体同步方法的细节可以参照上述实施例，在此不再赘述。
在一实施例中，源网络设备为ONU，所述目标网络设备为OLT，数据帧承载注册请求消息(REISTER_REQ)，注册请求消息中包括用于指示ONU是否具有预编码能力的指示信息。即ONU向OLT上报其是否具有预编码能力。OLT根据该指示信息，可以决定是否需要对发送给该ONU的数据进行预编码。通过在数据帧中添加指示该源网络设备是否具有预编码能力的指示信息，从而可以告知目标网络设备是否需要对该源网络设备发送的数据帧进行解预编码，以及告知目标网络设备是否需要对发送给该源网络设备的数据帧进行预编码。
在另一实施例中，源网络设备为OLT，目标网络设备为ONU，数据帧承载发现授权消息(Discovery Gate)，发现授权消息中包括用于指示ONU是否需要预编码或解预编码的指示信息。具体的，OLT可以指示下行发送给ONU的消息是否预编码，也即指示了ONU是否需要对下行接收的数据进行解预编码；也可以指示ONU上行发送给OLT的上行数据是否需要预编码。该数据帧中可以包括上行指示部分和下行指示部分，上行指示部分用于指示上行发送是否预编码，下行指示部分用于指示下行发送是否预编码。上行指示部分和下行指示部分可以位于预设位置，OLT和ONU之间预先预定。也可以增加上行标识和下行标识，以用来指示某个指示部分是上行指示部分还是下行指示部分。本实施例中，通过在数据帧中添加指示该数据帧是否预编码的指示信息，可以使得目标网络设备能够根据该信息进一步确定之前盲检的结果是否正确，实现双重保险。另外，通过指示上行或下行是否需要预编码，使得源网络设备和目标网络设备可以根据指示进行预编码和解预编码，不会出错，提高效率。
在另一实施例中，源网络设备为OLT，目标网络设备为ONU，数据帧承载注册消息(Register)，注册消息中包括用于指示ONU打开或关闭预编码使能位的指示信息。ONU接收到该指示信息后，打开或关闭预编码使能位。例如，打开预编码使能位时，则该ONU进行预编码，或者解预编码。关闭预编码使能位时，则该ONU不进行预编码和解预编码。或者，也可以打开预编码使能位时，则该ONU不进行预编码和解预编码。关闭预编码使能位时，则该ONU进行预编码，或者解预编码。所述预编码使能位可以为预设位置的比特，例如，可以为1比特或2比特，或者其他数量的比特。以1比特为例，可以在该比特为“0”时，表示关闭预编码使能位；在该比特为“1”时，表示打开预编码使能位。ONU可以向OLT反 馈使能响应指示信息，可以在注册响应消息(Register_ACK)中携带该使能响应指示信息，以告知OLT该ONU是否打开预编码使能位。
本发明还提供一种网络设备，该网络设备可以为OLT110，也可以为ONU130。
如图7所示，该网络设备包括处理器510、存储器520、媒体访问控制(medium access control，MAC)芯片530、收发器540和波分复用器550。
处理器510可以采用通用的中央处理器(Central Processing Unit，CPU)，微处理器，应用专用集成电路ASIC，或者至少一个集成电路，用于执行相关程序，以实现本发明实施例所提供的技术方案。
存储器520可以是只读存储器(Read Only Memory，ROM)，静态存储设备，动态存储设备或者随机存取存储器(Random Access Memory，RAM)。存储器520可以存储操作系统和其他应用程序。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在存储器520中，并由处理器510来执行。
在一实施例中，处理器510内部可以包括存储器520。在另一实施例中，处理器510和存储器520是两个独立的结构。
在一实施例中，处理器510和MAC芯片530可以是两个独立的结构。在另一实施例中，处理器510中可以包括MAC芯片530。MAC芯片530可以包括物理编码子层和MAC控制子层。
收发器540可以包括光发射器和/或光接收器。光发射器可以用于发送光信号，光接收器可以用于接收光信号。光发射器可以通过发光器件，例如气体激光器、固体激光器、液体激光器、半导体激光器、直调激光器等实现。光接收器可以通过光检测器，例如光电检波器或者光电二极管(如雪崩二极管)等实现。收发器540还可以包括数模转换器和模数转换器。
波分复用器550与收发器540相连，当网络设备发送光信号时，波分复用器充当复用器。当网络设备接收光信号时，波分复用器充当解复用器。波分复用器也可以称为光耦合器。
在该网络设备作为上述源网络设备时，从上述实施例可以看出，源网络设备的物理编码子层用于执行步骤S200，S201，S202，S203、S204和S205。源网络设备的物理编码子层用于执行步骤S301，S302和S303。源网络设备的MAC控制子层或处理器用于执行步骤S401，收发器用于执行步骤S402。
在该网络设备作为上述目标网络设备时，从上述实施例可以看出，目标网络设备的物理编码子层用于执行步骤S206，S207，S208和S209，目标网络设备的物理编码子层还用于执行步骤S304，S305和S306。目标网络设备的MAC控制子层或处理器510用于执行步骤S404，收发器540用于执行步骤S403。
处理器510、收发器540、MAC控制子层和物理编码子层执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的数据编码装置，该装置可以集成在上述实施例源网络 设备中，例如，可以集成在源网络设备的MAC芯片中。如图8所示，该装置包括：收集模块610，前向纠错编码模块620和生成模块630。
从上述实施例可以看出，收集模块610用于执行步骤S200，S202，前向纠错编码模块620用于执行步骤S204，生成模块630用于执行步骤S203和S205。
该装置还包括转码模块640，转码模块用于执行步骤S201，
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的数据译码装置，该装置可以集成在上述实施例目标网络设备中，例如，可以集成在目标网络设备的MAC芯片中。如图9所示，该装置包括：接收模块710，同步模块720，提取模块730，前向纠错译码模块740。
从上述实施例可以看出，接收模块710用于执行步骤S205，同步模块720用于执行步骤S206，提取模块730用于执行步骤S207，前向纠错译码模块740用于执行步骤S208。
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的预编码指示装置，该装置可以集成在上述实施例源网络设备中，例如，可以集成在源网络设备的MAC芯片中。该装置包括：添加模块，生成模块和发送模块。
从上述实施例可以看出，添加模块用于执行步骤S301，生成模块用于执行步骤S302，发送模块用于执行步骤S303。
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的预编码指示装置，该装置可以集成在上述实施例目标网络设备中，例如，可以集成在目标网络设备的MAC芯片中。该装置包括：接收模块，同步模块和确定模块。
从上述实施例可以看出，接收模块用于执行步骤S304，同步模块用于执行步骤S305，确定模块用于执行步骤S306。
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的预编码指示装置，该装置可以集成在上述实施例源网络设备中，例如，可以集成在源网络设备的MAC芯片中或者处理器中。该装置包括：生成模块和发送模块。
从上述实施例可以看出，生成模块用于执行步骤S401，发送模块用于执行步骤S402。
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种PON系统中的预编码指示装置，该装置可以集成在上述实施例目标网络设备中，例如，可以集成在目标网络设备的MAC芯片或处理器中。该装置包括：接收模块和确定模块。
从上述实施例可以看出，接收模块用于执行步骤S403，确定模块用于执行步骤S404。
该装置各个模块执行上述步骤时的更多细节可以参照上述方法各个实施例及附图的相关描述，此处不再赘述。
本发明实施例同样具有上述各个方法实施例中所描述的各种有益效果，在此不再赘述。
本发明还提供一种光线路终端，该光线路终端包括上述任一实施例所述的数据编码装置，或者该光线路终端包括上述任一实施例所述的数据译码装置，或者该光线路终端包括上述任一实施例所述的预编码指示装置。
本发明还提供一种光网络单元，该光网络单元包括上述任一实施例所述的数据编码装置，或者该光网络单元包括上述任一实施例所述的数据译码装置，或者该光网络单元包括上述任一实施例所述的预编码指示装置。
本发明还提供一种PON系统，该系统包括上述所述的光线路终端和所述的光网络单元。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
综上所述，以上仅为本发明的实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (21)

  1. 一种PON系统中的数据编码方法，其特征在于，所述方法包括：
    在物理编码子层收集N个数据块组合生成有效数据；所述N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值；所述FEC码型对应设有FEC码字值和净荷值；
    在所述物理编码子层生成净荷，所述净荷包括所述有效数据，且所述净荷的长度等于所述净荷值；
    在所述物理编码子层根据所述FEC码型对所述净荷进行FEC编码生成校验部分，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；
    在所述物理编码子层生成码字结构，所述码字结构包括所述有效数据、所述校验部分和同步头，所述有效数据、所述校验部分和所述同步头之间相互独立的分布于所述码字结构内。
  2. 如权利要求1所述的方法，其特征在于，所述同步头位于所述码字结构的头部，或者位于所述码字结构的尾部，或者位于所述有效数据与所述校验部分之间。
  3. 如权利要求1或2所述的方法，其特征在于，收集的所述数据块为128B/129B或256B/257B的数据块，所述方法还包括：所述物理编码子层将输入的64B/66B或者64B/65B的数据块转码为128B/129B或256B/257B的数据块；
    或者，收集的所述数据块为64B/66B或者64B/65B的数据块。
  4. 如权利要求1至3任一项所述的方法，其特征在于，所述前向纠错编码方式为LDPC(18493,15677)、RS(2047,1739)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)或者RS(1019,839)。
  5. 如权利要求1至4任一项所述的方法，其特征在于，在所述有效数据的长度等于所述净荷值时，所述净荷由所述有效数据组成。
  6. 如权利要求1至4任一项所述的方法，其特征在于，在所述有效数据的长度小于所述净荷值时，所述码字结构还包括填充部分，所述有效数据和所述填充部分构成所述净荷，且所述有效数据与所述填充部分的长度之和等于所述净荷值。
  7. 如权利要求6所述的方法，其特征在于，所述填充部分还用于指示所述码字结构的长度，或者所述有效数据的长度，或者所述有效数据与所述校验部分的长度之和，或者所述净荷的长度，或者所述净荷与所述校验部分的长度之和。
  8. 如权利要求1至7任一项所述的方法，其特征在于，所述同步头的长度设为S，输入的数据块的长度设为X，所述FEC码字值除以所述X的余数设为Y，则S＝tX-Y，且t为整数；其中，在Y≠0时，t≥1；在Y＝0时，t≥0。
  9. 一种PON系统中的数据译码方法，其特征在于，所述方法包括：
    在物理编码子层接收码字结构，所述码字结构包括有效数据、校验部分和同步头，且所述有效数据、所述校验部分和所述同步头之间相互独立的分布于所述码字结构内，所述有效数据由N个数据块组成，N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值，所述FEC码型对应设有FEC码字值和净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；
    在所述物理编码子层根据所述同步头对接收的所述码字结构进行同步；
    在所述物理编码子层提取出净荷和所述校验部分，所述净荷包括所述有效数据，且所述净荷的长度等于所述净荷值；
    在所述物理编码子层根据所述FEC码型对所述净荷进行前向纠错译码。
  10. 如权利要求9所述的方法，其特征在于，组成所述有效数据的所述数据块为64B/66B、64B/65B、28B/129B或256B/257B的数据块。
  11. 如权利要求9或10所述的方法，其特征在于，所采用的前向纠错译码方式为LDPC(18493,15677)、RS(2047,1739)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)或者RS(1019,839)。
  12. 如权利要求9至10任一项所述的方法，其特征在于，在所述有效数据的长度等于所述净荷值时，所述净荷由所述有效数据组成。
  13. 如权利要求9至10任一项所述的方法，其特征在于，在所述有效数据的长度小于所述净荷值时，所述码字结构还包括填充部分，所述有效数据和所述填充部分构成所述净荷。
  14. 如权利要求9至13任一项所述的方法，其特征在于，所述同步头的长度设为S，组成所述有效数据的数据块的长度设为X，所述FEC码字值除以所述X的余数设为Y，则S＝tX-Y，且t为整数；其中，在Y≠0时，t≥1；在Y＝0时，t≥0。
  15. 一种PON系统中的数据编码装置，其特征在于，所述装置包括：
    收集模块，用于收集N个数据块组合生成有效数据，所述N为整数，N小于或等于一种前向纠错编码FEC码型对应的净荷值与每个所述数据块的长度的比值；所述FEC码型对应设有FEC码字值和净荷值；
    生成模块，用于生成净荷，所述净荷包括所述有效数据，且所述净荷的长度等于所述净荷值；
    前向纠错编码模块，用于根据所述FEC码型对所述净荷进行FEC编码生成校验部分，所述净荷的长度等于所述净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；
    所述生成模块还用于生成码字结构，所述码字结构包括所述有效数据、所述校验部分和同步头，所述有效数据、所述校验部分和所述同步头之间相互独立的分布于所述码字结构内。
  16. 如权利要求15所述的装置，其特征在于，收集的所述数据块为128B/129B或256B/257B的数据块，所述方法还包括：所述物理编码子层将输入的64B/66B或者64B/65B的数据块转码为128B/129B或256B/257B的数据块；
    或者，收集的所述数据块为64B/66B或者64B/65B的数据块。
  17. 如权利要求15或16所述的装置，其特征在于，所述前向纠错编码方式为LDPC(18493,15677)、RS(2047,1739)、RS(1023,847)、RS(1023,845)、RS(1023,843)、RS(1023,841)、RS(1015,839)、RS(1017,839)或者RS(1019,839)。
  18. 一种PON系统中的数据译码装置，其特征在于，所述装置包括：
    接收模块，用于接收码字结构，所述码字结构包括有效数据、校验部分和同步头，且 所述有效数据、所述校验部分和所述同步头之间相互独立的分布于所述码字结构内，所采用的前向纠错译码FEC码型对应设有FEC码字值和净荷值，所述有效数据由N个数据块组成，N为整数，N小于或等于一种FEC码型对应的净荷值与每个所述数据块的长度的比值，所述FEC码型对应设有FEC码字值和净荷值，所述校验部分的长度等于所述FEC码字值与所述净荷值之差；
    同步模块，用于根据所述同步头对接收的所述码字结构进行同步；
    提取模块，用于提取出净荷和所述校验部分，所述净荷包括所述有效数据，且所述净荷的长度等于所述净荷值；
    前向纠错译码模块，用于根据所述FEC码型对所述净荷进行前向纠错译码。
  19. 一种光线路终端，其特征在于，所述光线路终端包括如权利要求15至18任一项所述的装置。
  20. 一种光网络单元，其特征在于，所述光网络单元包括如权利要求15至18任一项所述的装置。
  21. 一种PON系统，其特征在于，所述PON系统包括如权利要求19所述的光线路终端和如权利要求20所述的光网络单元。
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