WO2023130584A1 - 电容测试结构及其形成方法 - Google Patents

电容测试结构及其形成方法 Download PDF

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WO2023130584A1
WO2023130584A1 PCT/CN2022/081992 CN2022081992W WO2023130584A1 WO 2023130584 A1 WO2023130584 A1 WO 2023130584A1 CN 2022081992 W CN2022081992 W CN 2022081992W WO 2023130584 A1 WO2023130584 A1 WO 2023130584A1
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capacitance
doped
well region
region
type
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PCT/CN2022/081992
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English (en)
French (fr)
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张书浩
李宁
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present application relates to the field of semiconductor testing, in particular to a capacitance testing structure and a forming method thereof.
  • some embodiments of the present application provide a capacitance testing structure, including:
  • the well region located in the semiconductor substrate, the well region is doped with a first type of impurity ions
  • the isolated doped region is doped with impurity ions of a second type, the second type being opposite to the first type;
  • the capacitive test device located in the well region.
  • the semiconductor substrate is a semiconductor substrate doped with the first type of impurity ions, and the concentration of the first type of impurity ions doped in the semiconductor substrate is lower than that of the doped in the well region.
  • the first type of impurity ion concentration is lower than that of the doped in the well region.
  • the isolated doped region includes a deeply doped region located at the bottom of the well region and a ring-shaped doped region located around the well region, the bottom of the ring-shaped doped region is connected to the surrounding edges of the deeply doped region;
  • the well region is located above the deeply doped region, and the width of the well region is smaller than the width of the deeply doped region.
  • the first type of impurity ions are P-type impurity ions
  • the second type of impurity ions are N-type impurity ions.
  • the capacitance testing device is a MOS device or a diode.
  • the MOS device is a planar MOS transistor, and the planar MOS transistor includes: a gate dielectric layer located on the surface of the well region; a gate located on the surface of the gate dielectric layer; source and drain in the well region on the side.
  • the MOS device is a buried gate MOS transistor
  • the buried gate MOS transistor includes: a trench located in the well region; a gate dielectric layer located on the sidewall and bottom surface of the trench; A gate located on the surface of the gate dielectric layer and filling the trench; a source and a drain located in the well region on both sides of the trench.
  • the source, the drain, and the semiconductor substrate are grounded, and a varying voltage is applied to the gate to obtain a capacitance curve.
  • the capacitance curve Calculate the capacitance value of the gate dielectric layer and the thickness of the effective gate dielectric layer.
  • the diode includes: a second doped region located in the well region, the second doped region is doped with impurity ions of the second type, the well region and the second doped region
  • the impurity regions are respectively used as two electrodes of the diode; when the diode is tested for capacitance, the well region and the second doped region are respectively applied with a voltage to obtain a capacitance curve, and the junction capacitance of the diode is calculated according to the capacitance curve.
  • the well region being doped with a first type of impurity ions
  • the isolated doped region doped with impurity ions of a second type, the second type being opposite to the first type;
  • a capacitive testing device is formed in the well region.
  • the semiconductor substrate is a semiconductor substrate doped with the first type of impurity ions, and the concentration of the first type of impurity ions doped in the semiconductor substrate is lower than that of the doped in the well region.
  • the first type of impurity ion concentration is lower than that of the doped in the well region.
  • the isolated doped region includes a deeply doped region formed at the bottom of the well region and a ring-shaped doped region formed around the well region, the bottom of the ring-shaped doped region is connected to the surrounding edges of the deeply doped region .
  • the deeply doped region is formed by a first ion implantation
  • the well region is formed by a second ion implantation
  • the annular doped region is formed by a third ion implantation.
  • the first type of impurity ions are P-type impurity ions
  • the second type of impurity ions are N-type impurity ions.
  • the energy range of the first ion implantation is 500KeV-1200KeV, and the dose range is 1E13-5E13/cm 2
  • the energy range of the third ion implantation is 50KeV-200KeV
  • the dose range is 1E13-5E13 /cm 2 .
  • the energy of the second ion implantation is less than 500KeV, and the dose range is 1E12-3E13/cm 2 .
  • the capacitance testing device is a MOS device, a square capacitance or a striped oxide layer testing structure, or a diode.
  • the MOS device is a planar MOS transistor
  • the forming process of the capacitance test structure of the planar MOS transistor includes: forming a gate dielectric layer on the surface of the well region; forming a gate on the surface of the gate dielectric layer ; A source and a drain are respectively formed in the well regions on both sides of the gate.
  • the MOS device is a buried gate MOS transistor
  • the formation process of the capacitance test structure of the buried gate MOS transistor includes: forming a trench in the well region; A gate dielectric layer is formed on the bottom surface; a gate that fills the trench is formed on the surface of the gate dielectric layer; a source and a drain are respectively formed in the well regions on both sides of the trench.
  • the source, the drain, and the semiconductor substrate are grounded, and a varying voltage is applied to the gate to obtain a capacitance curve.
  • the capacitance curve Calculate the capacitance value of the gate dielectric layer and the thickness of the effective gate dielectric layer.
  • the forming process of the diode includes: forming a second doped region in the well region, and the second doped region is doped with a second type
  • the impurity ions of the well region and the second doped region are respectively used as two electrodes of the diode; when the diode is tested for capacitance, voltages are applied to the well region and the second doped region respectively to obtain a capacitance curve, The junction capacitance of the diode is calculated from the capacitance curve.
  • the method for forming a capacitance test structure includes, after providing a semiconductor substrate, forming a well region in the semiconductor substrate, and the well region is doped with a first type of impurity ions; in the semiconductor substrate An isolated doped region surrounding the well region is formed in the substrate, the isolated doped region is doped with impurity ions of a second type, the second type is opposite to the first type; a capacitor is formed in the well region Test device.
  • the isolation doped region surrounds the well region, and since the type of impurity ions doped in the isolation doped region is opposite to the type of impurity ions doped in the well region and the semiconductor substrate, so that the well There will be no direct contact or isolation between the region and the semiconductor substrate outside the isolation doped region.
  • the capacitance test structure After the capacitance test structure is formed in the well region, when the capacitance test structure is tested for capacitance, it can prevent the well region from directly contacting the semiconductor substrate. The influence of the parasitic capacitance of the external circuit on the capacitance test result during contact, thereby improving the accuracy of the capacitance test result.
  • FIGS. 1-8 are structural schematic diagrams of the formation process of the capacitance test structure in some embodiments of the present application.
  • FIG. 9-FIG. 10 are schematic diagrams of the circuit structure when the capacitance test structure is tested for capacitance in some embodiments of the present application.
  • FIG. 11 is a structural schematic diagram of capacitance curves obtained in some embodiments of the present application.
  • FIG. 12 is a comparison diagram of some parameters obtained with/without isolation doped regions in some embodiments of the present application.
  • the application provides a capacitance testing structure and a method for forming the same.
  • an isolation doped region By forming an isolation doped region, the well region of the capacitance testing device is isolated from the semiconductor substrate, thereby avoiding damage to the capacitance testing device when testing the capacitance.
  • the well region is directly connected to the semiconductor substrate, thereby avoiding the influence of the parasitic capacitance of the external circuit on the accuracy of the capacitance test result.
  • a semiconductor substrate 101 is provided.
  • the semiconductor substrate 101 is subsequently used to form a capacitance testing device.
  • the material of the semiconductor substrate 101 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), insulator germanium on (GOI); or other materials, such as III-V group compounds such as gallium arsenide.
  • a small amount of impurity ions of the first type, such as P-type impurity ions, can be doped in the semiconductor substrate 101.
  • the semiconductor substrate 101 is a silicon substrate doped with P-type impurity ions.
  • the P-type impurity ions are one or more of boron ions, gallium ions or indium ions.
  • a deeply doped region 102 is formed in the semiconductor substrate 101 .
  • the deeply doped region 102 is used as a part of the isolated doped region.
  • the deeply doped region 102 forms an isolation doped region together with the subsequently formed annular doped region.
  • the doping type of the deeply doped region 102 is opposite to that of the semiconductor substrate 101 , and the deeply doped region is doped with second type impurity ions.
  • the second type of impurity ions are N-type impurity ions
  • the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions.
  • the deeply doped region 102 is formed by a first ion implantation process, the energy of the first ion implantation is greater than the energy of the second ion implantation when forming the well region and the energy of the third ion implantation when forming the annular doped region , so that the formed deeply doped region can be located under the subsequently formed well region, so that the deeply doped region completely isolates the well region from the semiconductor substrate from the bottom.
  • the energy range of the first ion implantation is 500KeV-1200KeV, and the dose range is 1E13-5E13/cm 2 .
  • a first mask layer (not shown in the figure) is formed on the surface of the semiconductor substrate 101, and the material of the first mask layer may be photoresist , the first mask layer has a first opening exposing the surface of the area to be implanted, and the first mask layer is used as a mask for the first ion implantation to define the implantation position of the deeply doped region 102; After performing the first ion implantation, the first mask layer is removed.
  • a well region 103 is formed in the semiconductor substrate 101 .
  • the doping type of the well region 103 is the same as the doping type of the semiconductor substrate, and opposite to the doping type of the deeply doped region 102, and the well region 103 is doped with a first type of impurity ions .
  • the first type of impurity ions in this embodiment are P-type impurity ions.
  • the P-type impurity ions are one or more of boron ions, gallium ions or indium ions.
  • the formed well region 103 is located above the deeply doped region 102 , and the width of the well region 103 is smaller than the width of the deeply doped region 102 .
  • the size of the deeply doped region 102 wider than the well region 103 is 1um-10um, which can be 1um, 5um, or 10um. Ensure that the formed well region can be surrounded by the deeply doped region and the subsequently formed annular doped region to achieve electrical isolation, avoid charge leakage, and affect the accuracy of capacitance testing.
  • the well region 103 is formed by a second ion implantation process.
  • a second mask layer (not shown in the figure) is formed on the surface of the semiconductor substrate 101.
  • the second mask layer The material of the film layer can be photoresist, and the second mask layer has a second opening exposing the surface of the region to be implanted, and the second mask layer is used as a mask for the second ion implantation, defining the well
  • the width of the second mask layer is 1um-10um smaller than the width of the first mask layer forming the deeply doped region.
  • the energy of the second ion implantation is less than 500KeV, and the dose range is 1E12-3E13/cm 2 .
  • the well region that is beneficial to be formed is above the deeply doped region, and can be surrounded by the deeply doped region and the subsequently formed ring-shaped doped region to achieve electrical isolation, avoid charge leakage, and affect the accuracy of capacitance testing.
  • the well region 103 may be formed before the deeply doped region 102 .
  • FIG. 4 is a schematic cross-sectional structure diagram of FIG. 5 along the cutting line AB, and a ring-shaped doped region 104 is formed in the semiconductor substrate 101 around the well region 103, and the ring-shaped doped region The bottom of 104 is connected to the surrounding edges of the deeply doped region 102 to form an isolated doped region 105 .
  • the doping type of the annular doped region 104 is the same as the doping type of the deeply doped region 102, which is opposite to the doping type of the semiconductor substrate 101 and the well region 103, and the annular doped region 104 is doped with Doped with the second type of impurity ions.
  • the second type of impurity ions are N-type impurity ions
  • the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions.
  • the annular doped region 104 and the deeply doped region 102 together form an isolation doped region 105, the isolation doped region 105 surrounds the well region 103, and because the impurity ions doped in the isolation doped region 105 and The type of impurity ions doped in the well region 103 and the semiconductor substrate 101 is opposite, so that the well region 103 and the semiconductor substrate 101 outside the isolation doped region 105 will not be directly contacted or isolated, and subsequently formed in the well region 103
  • the capacitance test structure when the capacitance test is performed on the capacitance test structure, it can prevent the influence of the parasitic capacitance of the external circuit on the capacitance test result when the well region 103 is in direct contact with the semiconductor substrate 101, thereby improving the accuracy of the capacitance test result.
  • the annular doped region 104 is formed by a third ion implantation process.
  • a third mask layer (not shown) is formed on the surface of the semiconductor substrate 101.
  • the first The material of the three mask layers can be photoresist, the third mask layer has a ring-shaped third opening exposing the surface of the area to be implanted, and the third mask layer is used as a mask for the third ion implantation , defining the implantation position of the annular doped region 104; after the third ion implantation, the third mask layer is removed.
  • the energy range of the third ion implantation is 50KeV-200KeV, and the dose range is 1E13-5E13/cm 2 .
  • the annular doped region 104 may be formed before the well region 103 .
  • a capacitive testing device is formed in the well region 103 .
  • the capacitance testing device is a MOS device or a diode.
  • the MOS device includes planar MOS transistors and buried gate MOS transistors.
  • the MOS device is a planar MOS transistor.
  • a gate 107 is formed on the surface of the dielectric layer 106; a source 108 and a drain 109 are respectively formed in the well region 103 on both sides of the gate 107.
  • the material of the gate dielectric layer 106 can be silicon oxide, and the material of the gate 107 can be doped polysilicon.
  • the material of the gate dielectric layer 106 can be high K dielectric material, such as HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 or BaSrTiO
  • the material of the gate 107 is metal, such as W, One or more of Al, Cu, Ti, Ag, Au, Pt, Ni.
  • the source electrode 108 and the drain electrode 109 are formed by an ion implantation process, and the type of impurity ions doped in the source electrode 108 and the drain electrode 109 is opposite to the type of impurity ions doped in the well region 103.
  • the The source 108 and the drain 109 are doped with N-type impurity ions.
  • the MOS device is a buried gate MOS transistor.
  • the formation process of the capacitance test structure of the buried gate MOS transistor includes: forming a trench in the well region 103; A gate dielectric layer 110 is formed on the sidewall and bottom surface of the trench; a gate 111 filling the trench is formed on the surface of the gate dielectric layer 110; a source 113 and a drain are respectively formed in the well regions on both sides of the trench 112.
  • the number of the grooves is one. In other embodiments, the number of the trenches may be two to form a double-trench buried gate MOS transistor.
  • the material of the gate dielectric layer 110 may be silicon oxide, and the material of the gate 111 is doped polysilicon.
  • the material of the gate dielectric layer 110 may be high K dielectric material, such as HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 , Al 2 O 3 , SrTiO 3 or BaSrTiO
  • the material of the gate 111 is metal, such as W, One or more of Al, Cu, Ti, Ag, Au, Pt, Ni.
  • the source 113 and the drain 112 are formed by an ion implantation process, and the type of impurity ions doped in the source 111 and the drain 112 is opposite to the type of impurity ions doped in the well region 103.
  • the The source 113 and the drain 112 are doped with N-type impurity ions.
  • Fig. 9 or Fig. 10 described source (108 or 113), drain (109 or 112) and semiconductor substrate 101 are grounded (Vs) , applying a variable voltage V G on the gate (107 or 111) to obtain a capacitance curve, and calculate the capacitance value of the gate dielectric layer and the thickness of the effective gate dielectric layer according to the capacitance curve.
  • the solid line represents the capacitance of the gate dielectric layer obtained when there is an isolation doped region in this application, and the dotted line represents the capacitance obtained when there is no isolation doped region.
  • the capacitance of the gate dielectric layer it can be seen that the capacitance value of the gate dielectric layer obtained when there is an isolation doped region is smaller, so the accuracy is improved).
  • the accuracy of the capacitance value Cox of the obtained gate dielectric layer is improved, the accuracy of the thickness D of the effective gate dielectric layer is also improved (refer to the right figure in FIG.
  • the comparison diagram of the effective gate dielectric layer thickness obtained at the time the solid line represents the effective gate dielectric layer thickness obtained when there is an isolation doped region in this application, and the dotted line represents the effective gate dielectric layer thickness obtained when there is no isolation doped region, you can see The thickness of the effective gate dielectric layer obtained when there is an isolation doped region is greater, so the accuracy is improved).
  • the forming process of the diode includes: forming a second doped region 114 in the well region 103, the second doped region 114 is doped with the second type of impurity ions, and the well region 103 and the second doped region 114 serve as two electrodes of the diode respectively.
  • a heavily doped region 115 can also be formed in the well region 103 on both sides of the second doped region 114, and the type of impurity ions doped in the heavily doped region 115 is the same as that of the well.
  • the impurity ions doped in the region 103 have the same doping type, the concentration of the impurity ions doped in the heavily doped region 115 is greater than the concentration of the impurity ions doped in the well region 103, and the heavily doped region A shallow trench isolation structure 116 may also be formed between 115 and the second doped region.
  • Some embodiments of the present application also provide a capacitance testing structure, combined with reference to FIG. 4-FIG. 5 and FIG. 6, including:
  • the well region 103 located in the semiconductor substrate 101, the well region 103 is doped with a first type of impurity ions;
  • Capacitance testing devices located in the well region 103 .
  • the semiconductor substrate 101 is a semiconductor substrate doped with a first type of impurity ions, and the concentration of the first type of impurity ions doped in the semiconductor substrate 101 is lower than that of the well region 103 The concentration of the first type of impurity ions doped in the medium.
  • the isolated doped region 105 includes a deeply doped region 102 located at the bottom of the well region 103 and a ring-shaped doped region 104 located around the well region 103, and the bottom of the ring-shaped doped region 104 and the deeply doped Area 102 is bordered around.
  • the first type of impurity ions are P-type impurity ions
  • the second type of impurity ions are N-type impurity ions.
  • the capacitance testing device is a MOS device, a square capacitance or a striped oxide layer testing structure, or a diode.
  • the MOS device is a planar MOS transistor.
  • the planar MOS transistor includes: a gate dielectric layer 106 located on the surface of the well region 103; a gate 107 located on the surface of the gate dielectric layer 106 ; The source 108 and the drain 109 in the well region 103 located on both sides of the gate 107 .
  • the MOS device is a buried gate MOS transistor.
  • the buried gate MOS transistor includes: a trench located in the well region 103; The gate dielectric layer 110 on the surface; the gate 111 located on the surface of the gate dielectric layer 110 and filling the trench; the source 113 and the drain 112 in the well region 103 located on both sides of the trench.
  • the source (108 or 113), the drain (109 or 112) and the semiconductor substrate 101 are grounded (Vs), and a variable voltage is applied to the gate (107 or 111).
  • the voltage V G is used to obtain a capacitance curve, and the capacitance value of the gate dielectric layer and the thickness of the effective gate dielectric layer are calculated according to the capacitance curve.
  • the capacitance testing device is a diode.
  • the diode includes: a second doped region 114 located in the well region 103, and the second doped region 114 is doped with For impurity ions of the second type, the well region 103 and the second doped region 114 serve as two electrodes of the diode respectively.
  • the diode further includes a heavily doped region 115 located in the well region 103 on both sides of the second doped region 114, the heavily doped region serves as an extraction electrode at one end of the diode, the The type of impurity ions doped in the heavily doped region 115 is the same as the doping type of the impurity ions doped in the well region 103, and the concentration of the impurity ions doped in the heavily doped region 115 is greater than that of the well region 115.
  • the concentration of impurity ions doped in the region 103 in order to ensure the ohmic contact of the contact segment and reduce the contact resistance, also includes a shallow trench isolation structure 116 between the heavily doped region 115 and the second doped region .
  • voltages are applied to the well region 103 (the voltage of the well region 103 is applied through the heavily doped region 115) and the second doped region 114 respectively.
  • V1 is applied to the well region 103
  • V2 is applied to the second doped region
  • V2 is greater than V1 (or V2 is smaller than V1), so that there is a voltage difference between the well region 103 and the second doped region 114, and a capacitance curve is obtained
  • the junction capacitance of the diode is calculated from the capacitance curve.

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Abstract

一种电容测试结构及其形成方法，提供半导体衬底（101），在半导体衬底（101）中形成阱区（103），阱区（103）掺杂有第一类型的杂质离子；在半导体衬底（101）中形成包围阱区（103）的隔离掺杂区（105），隔离掺杂区（105）掺杂有第二类型的杂质离子，第二类型与第一类型相反；在阱区（103）中形成电容测试器件。由于隔离掺杂区（105）将阱区（103）包围，且由于隔离掺杂区（105）中掺杂的杂质离子与阱区（103）和半导体衬底（101）掺杂的杂质离子类型相反，从而使得阱区（103）与隔离掺杂区（105）外侧的半导体衬底（101）之间不会直接接触或者被隔离，在对电容测试结构进行电容的测试时，能防止阱区（103）与半导体衬底（101）直接接触时外部电路的寄生电容对电容测试结果的影响，从而提高电容测试结果的准确性。

Description

电容测试结构及其形成方法
相关申请引用说明
本申请要求于2022年01月10日递交的中国专利申请号202210021448.6，申请名为“电容测试结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体测试领域，尤其涉及一种电容测试结构及其形成方法。
背景技术
现有的用于集成电路制作的晶圆一般为掺杂有P型杂质的衬底，然后在该P型衬底上制作电容测试用的各种待测器件，以MOS晶体管(Metal-oxide-semiconductor)为例，由于NMOS晶体管的阱区也是P型，即与P型衬底的掺杂类型相同，在进行栅介质层电容的测试时，NMOS晶体管的P型阱区会与P型衬底直接相连，而P型衬底会与测试机台以及外部其他电路相连，当我们利用探针对该NMOS晶体管进行电容测试时不可避免的会把外电路的寄生电容带入，从而直接影响到栅介质层电容的测试结果的准确性。
发明内容
鉴于此，本申请一些实施例提供了一种电容测试结构，包括：
半导体衬底；
位于所述半导体衬底中的阱区，所述阱区掺杂有第一类型的杂质离子；
位于所述半导体衬底中包围所述阱区的隔离掺杂区，所述隔离掺杂区掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；
位于所述阱区的电容测试器件。
在一些实施例中，所述半导体衬底为掺杂有第一类型的杂质离子的半导体衬底，所述半导体衬底中掺杂的第一类型杂质离子的浓度小于所述阱区中掺杂的第一类型的杂质离子浓度。
在一些实施例中，所述隔离掺杂区包括位于阱区底部的深掺杂区以及位于阱区周围的环形掺杂区，所述环形掺杂区底部与深掺杂区四周边缘连接；所述阱区位于所述深掺杂区的上方，且所述阱区的宽度小于所述深掺杂区的宽度。
在一些实施例中，所述第一类型的杂质离子为P型的杂质离子，所述第二类型的杂质离子为N型的杂质离子。
在一些实施例中，所述电容测试器件为MOS器件或者二极管。
在一些实施例中，所述MOS器件为平面MOS晶体管，所述平面MOS晶体管包括：位于所述阱区表面的栅介质层；位于所述栅介质层表面的栅极；位于所述栅极两侧的阱区中的源极和漏极。
在一些实施例中，所述MOS器件为掩埋栅MOS晶体管，所述掩埋栅MOS晶体管包括：位于所述阱区中的沟槽；位于所述沟槽的侧壁和底部表面的栅介质层；位于所述栅介质层表面且填充沟槽的栅极；位于所述沟槽两侧的阱区中的源极和漏极。
在一些实施例中，对所述MOS器件进行电容测试时，将所述源极、漏极和半导体衬底接地，在所述栅极上施加变化的电压，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效栅介质层的厚度。
在一些实施例中，所述二极管包括：位于所述阱区中的第二掺杂区，所述第二掺杂区的掺杂有第二类型的杂质离子，所述阱区和第二掺杂区分别作为二极管的两个电极；对所述二极管进行电容测试时，将所述阱区和第二掺杂区分别施加电压，获得电容曲线，根据所述电容曲线计算出二极管的结电容。
本申请另一些实施例还提供了一种电容测试结构的形成方法，包括：
提供半导体衬底；
在所述半导体衬底中形成阱区，所述阱区掺杂有第一类型的杂质离子；
在所述半导体衬底中形成包围所述阱区的隔离掺杂区，所述隔离掺杂区掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；
在所述阱区中形成电容测试器件。
在一些实施例中，所述半导体衬底为掺杂有第一类型的杂质离子的半导体衬底，所述半导体衬底中掺杂的第一类型杂质离子的浓度小于所述阱区中掺杂的第一类型的杂质离子浓度。
在一些实施例中，所述隔离掺杂区包括形成于阱区底部的深掺杂区以及形成于阱区周围的环形掺杂区，所述环形掺杂区底部与深掺杂区四周边缘连接。
在一些实施例中，通过第一离子注入形成所述深掺杂区，通过第二离子注 入形成所述阱区，通过第三离子注入形成所述环形掺杂区。
在一些实施例中，所述第一类型的杂质离子为P型的杂质离子，所述第二类型的杂质离子为N型的杂质离子。
在一些实施例中，所述第一离子注入的能量范围为500KeV-1200KeV，剂量范围为1E13-5E13/cm 2，所述第三离子注入的能量范围为50KeV-200KeV，剂量范围为1E13-5E13/cm 2。
在一些实施例中，所述第二离子注入的能量小于500KeV，剂量范围为1E12-3E13/cm 2。
在一些实施例中，所述电容测试器件为MOS器件、方块电容或者条带状氧化层测试结构或者二极管。
在一些实施例中，所述MOS器件为平面MOS晶体管，所述平面MOS晶体管的电容测试结构的形成过程包括：在所述阱区表面形成栅介质层；在所述栅介质层表面形成栅极；在栅极两侧的阱区中分别形成源极和漏极。
在一些实施例中，所述MOS器件为掩埋栅MOS晶体管，所述掩埋栅MOS晶体管的电容测试结构的形成过程包括：在所述阱区中形成沟槽；在所述沟槽的侧壁和底部表面形成栅介质层；在所述栅介质层表面形成填充沟槽的栅极；在所述沟槽两侧的阱区中分别形成源极和漏极。
在一些实施例中，对所述MOS器件进行电容测试时，将所述源极、漏极和半导体衬底接地，在所述栅极上施加变化的电压，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效栅介质层的厚度。
在一些实施例中，所述电容测试结构为二极管时，所述二极管的形成过程包括：在所述阱区中形成第二掺杂区，所述第二掺杂区的掺杂有第二类型的杂质离子，所述阱区和第二掺杂区分别作为二极管的两个电极；对所述二极管进行电容测试时，将所述阱区和第二掺杂区分别施加电压，获得电容曲线，根据所述电容曲线计算出二极管的结电容。
本申请前述一些实施例中，电容测试结构的形成方法，提供半导体衬底后，在所述半导体衬底中形成阱区，所述阱区掺杂有第一类型的杂质离子；在所述半导体衬底中形成包围所述阱区的隔离掺杂区，所述隔离掺杂区掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；在所述阱区中形成电容测试器 件。通过形成隔离掺杂区，所述隔离掺杂区将所述阱区包围，且由于隔离掺杂区中掺杂的杂质离子与阱区和半导体衬底掺杂的杂质离子类型相反，从而使得阱区与隔离掺杂区外侧的半导体衬底之间不会直接接触或者被隔离，在阱区中形成电容测试结构后，对电容测试结构进行电容的测试时，能防止阱区与半导体衬底直接接触时外部电路的寄生电容对电容测试结果的影响，从而提高电容测试结果的准确性。
附图说明
图1-图8为本申请一些实施例中电容测试结构的形成过程的结构示意图；
图9-图10为本申请一些实施例中对电容测试结构进行电容测试时的电路结构示意图；
图11为本申请一些实施例中获得的电容曲线的结构示意图；
图12为本申请一些实施例中在有/无隔离掺杂区时获得的部分参数的对比图。
具体实施方式
如背景技术所言，现有的电容测试结果的准确性仍有待提升。
为此，本申请提供了一种电容测试结构及其形成方法，通过形成隔离掺杂区将电容测试器件的阱区与半导体衬底进行隔离，从而在进行电容的测试时，避免电容测试器件的阱区与半导体衬底直接连接，从而避免外部电路的寄生电容对电容测试结果的准确性的影响。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图1，提供半导体衬底101。
所述半导体衬底101中后续用于形成电容测试器件。
在一些实施例中，所述半导体衬底101的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)； 或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。所述半导体衬底101中可以掺杂少量的第一类型的杂质离子，比如P型杂质离子，所述半导体衬底101中掺杂的P型杂质离子的浓度小于后续阱区中掺杂的第一类型的杂质离子的浓度。本实施中，所述半导体衬底101为掺杂P型杂质离子的硅衬底。
在一些实施例中，所述P型杂质离子为硼离子、镓离子或铟离子一种或几种。
参考图2，在所述半导体衬底101中形成深掺杂区102。
所述深掺杂区102作为隔离掺杂区的一部分。所述深掺杂区102与后续形成的环形掺杂区一起构成隔离掺杂区。
所述深掺杂区102的掺杂类型与半导体衬底101的掺杂类型相反，所述深掺杂区中掺杂有第二类型的杂质离子。本实施例中，所述第二类型的杂质离子为N型杂质离子，所述N型杂质离子为磷离子、砷离子或锑离子一种或几种。
所述深掺杂区102通过第一离子注入工艺形成，所述第一离子注入的能量大于后续形成阱区时的第二离子注入的能量以及形成环形掺杂区时的第三离子注入的能量，以使得形成的深掺杂区能位于后续形成的阱区下方，使得深掺杂区从底部将阱区与半导体衬底完全隔离。在一些实施例中，所述第一离子注入的能量范围为500KeV-1200KeV，剂量范围为1E13-5E13/cm 2。
在一些实施例中，在进行第一离子注入之前，在所述半导体衬底101表面形成第一掩膜层(图中未示出)，所述第一掩膜层的材料可以为光刻胶，所述第一掩膜层中具有暴露出待注入区域表面的第一开口，所述第一掩膜层作为第一离子注入时的掩膜，限定了深掺杂区102的注入位置；在进行第一离子注入后，去除所述第一掩膜层。
参考图3，在所述半导体衬底101中形成阱区103。
所述阱区103的掺杂类型与所述半导体衬底的掺杂类型相同，且与所述深掺杂区102的掺杂类型相反，所述阱区103掺杂有第一类型的杂质离子。本实施例中所述第一类型的杂质离子为P型杂质离子。所述P型杂质离子为硼离子、镓离子或铟离子一种或几种。
所述形成的阱区103位于所述深掺杂区102的上方，且所述阱区103的宽度小于所述深掺杂区102的宽度。在一些实施例中，所述深掺杂区102宽于所 述阱区103的大小为1um-10um，可以是1um,5um,10um。确保形成的阱区可以被深掺杂区和后续形成的环形掺杂区包围，实现电性隔离，避免电荷泄露，影响电容测试的准确性。
所述阱区103通过第二离子注入工艺形成，在进行第二离子注入工艺之前，在所述半导体衬底101表面上形成第二掩膜层(图中未示出)，所述第二掩膜层的材料可以为光刻胶，所述第二掩膜层中具有暴露出待注入区域表面的第二开口，所述第二掩膜层作为第二离子注入时的掩膜，限定了阱区103的注入位置；在进行第二离子注入后，去除所述第二掩膜层。所述第二掩膜层的宽度比形成所述深掺杂区的第一掩膜层的宽度小1um-10um。
在一些实施例中，所述第二离子注入的能量小于500KeV，剂量范围为1E12-3E13/cm 2。有利于形成的所述阱区在深掺杂区的上方，可以被深掺杂区和后续形成的环形掺杂区包围，实现电性隔离，避免电荷泄露，影响电容测试的准确性。
需要说明的是，在其他一些实施例中，所述阱区103可以先于所述深掺杂区102形成。
参考图4和图5，所述图4为图5沿切割线AB方向的剖面结构示意图，在所述阱区103周围的半导体衬底101中形成环形掺杂区104，所述环形掺杂区104底部与深掺杂区102四周边缘连接，形成隔离掺杂区105。
所述环形掺杂区104的掺杂类型与所述深掺杂区102的掺杂类型相同，与所述半导体衬底101和阱区103的掺杂类型相反，所述环形掺杂区104掺杂有第二类型的杂质离子。本实施例中，所述第二类型的杂质离子为N型杂质离子，所述N型杂质离子为磷离子、砷离子或锑离子一种或几种。
所述环形掺杂区104与深掺杂区102一起构成隔离掺杂区105，所述隔离掺杂区105将所述阱区103包围，且由于隔离掺杂区105中掺杂的杂质离子与阱区103和半导体衬底101掺杂的杂质离子类型相反，从而使得阱区103与隔离掺杂区105外侧的半导体衬底101之间不会直接接触或者被隔离，后续在阱区103中形成电容测试结构后，对电容测试结构进行电容的测试时，能防止阱区103与半导体衬底101直接接触时外部电路的寄生电容对电容测试结果的影响，从而提高电容测试结果的准确性。
所述环形掺杂区104通过第三离子注入工艺形成，在进行第三离子注入工艺之前，在所述半导体衬底101表面上形成第三掩膜层(图中未示出)，所述第三掩膜层的材料可以为光刻胶，所述第三掩膜层中具有暴露出待注入区域表面的环形的第三开口，所述第三掩膜层作为第三离子注入时的掩膜，限定了环形掺杂区104的注入位置；在进行第三离子注入后，去除所述第三掩膜层。
在一些实施例中，所述第三离子注入的能量范围为50KeV-200KeV，剂量范围为1E13-5E13/cm 2。
需要说明的是，在其他一些实施例中，所述环形掺杂区104可以先于所述阱区103形成。
参考图6，在所述阱区103中形成电容测试器件。
在一些实施例中，所述电容测试器件为MOS器件或者二极管。所述MOS器件包括平面MOS晶体管和掩埋栅MOS晶体管。
本公开实施例中，所述MOS器件为平面MOS晶体管，参考图6，所述平面MOS晶体管的电容测试结构的形成过程包括：在所述阱区103表面形成栅介质层106；在所述栅介质层106表面形成栅极107；在栅极107两侧的阱区103中分别形成源极108和漏极109。
在一些实施例中，所述栅介质层106的材料可以为氧化硅，所述栅极107的材料为掺杂的多晶硅，在另一些实施例中，所述栅介质层106的材料可以为高K介质材料，比如HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2、Al 2O 3、SrTiO 3或BaSrTiO，所述栅极107的材料为金属，比如为W、Al、Cu、Ti、Ag、Au、Pt、Ni其中一种或几种。
所述栅极107和栅介质层106的侧壁表面还可以形成侧墙。所述源极108和漏极109通过离子注入工艺形成，所述源极108和漏极109掺杂的杂质离子类型与阱区103的掺杂的杂质离子类型相反，本实施例中，所述源极108和漏极109中掺杂有N型杂质离子。
在另一些实施例中，所述MOS器件为掩埋栅MOS晶体管，参考图7，所述掩埋栅MOS晶体管的电容测试结构的形成过程包括：在所述阱区103中形成沟槽；在所述沟槽的侧壁和底部表面形成栅介质层110；在所述栅介质层110表面形成填充沟槽的栅极111；在所述沟槽两侧的阱区中分别形成源极113和 漏极112。本实施例中，所述沟槽的数量为一个。在其他实施例中，所述沟槽的数量可以为两个，以形成双沟槽掩埋栅MOS晶体管。
在一些实施例中，所述栅介质层110的材料可以为氧化硅，所述栅极111的材料为掺杂的多晶硅，在另一些实施例中，所述栅介质层110的材料可以为高K介质材料，比如HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2、Al 2O 3、SrTiO 3或BaSrTiO，所述栅极111的材料为金属，比如为W、Al、Cu、Ti、Ag、Au、Pt、Ni其中一种或几种。
所述源极113和漏极112通过离子注入工艺形成，所述源极111和漏极112掺杂的杂质离子类型与阱区103的掺杂的杂质离子类型相反，本实施例中，所述源极113和漏极112中掺杂有N型杂质离子。
对前述所述MOS器件的电容测试结构进行电容测试时，请参考图9或图10，将所述源极(108或113)、漏极(109或112)和半导体衬底101接地(Vs)，在所述栅极(107或111)上施加变化的电压V G，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效栅介质层的厚度。
在一具体的实施例中，所述获得的电容曲线如图11所示，根据该电容曲线可以计算获得栅介质层的电容值Cox。然后根据公式Cox＝K*A/D(其中K为栅介质层的介电常数，A为栅介质层的面积)，计算出有效栅介质层的厚度D。本申请中在对前述MOS器件进行电容的测试时，由于MOS器件中隔离掺杂区105，使得阱区103与隔离掺杂区105外侧的半导体衬底101之间不会直接接触或者被隔离，能防止阱区103与半导体衬底101直接接触时外部电路的寄生电容对电容测试结果的影响，从而提高了获得的栅介质层的电容值Cox结果的准确性(参考图12中左图为在有隔离掺杂区和无隔离掺杂区时获得的栅介质层电容的对比图，实线表示本申请中有隔离掺杂区时获得的栅介质层电容，虚线表示无隔离掺杂区时获得的栅介质层电容，可以看出有隔离掺杂区时获得的栅介质层电容值更小，因而准确性提高)。同时，由于获得的栅介质层的电容值Cox准确性提高，进而使得有效栅介质层的厚度D的准确性也提高(参考图12中右图为在有隔离掺杂区和无隔离掺杂区时获得的有效栅介质层厚度的对比图，实线表示本申请中有隔离掺杂区时获得的有效栅介质层厚度，虚线表示无隔离掺杂区时获得的有效栅介质层厚度，可以看出有隔离掺杂区时 获得的有效栅介质层厚度更大，因而准确性提高)。
在另一些实施例中，所述电容测试结构为二极管时，参考图8，所述二极管的形成过程包括：在所述阱区103中形成第二掺杂区114，所述第二掺杂区114掺杂有第二类型的杂质离子，所述阱区103和第二掺杂区114分别作为二极管的两个电极。在一些实施例中，在所述第二掺杂区114两侧的阱区103内还可以形成重掺杂区115，所述重掺杂区115中掺杂的杂质离子的类型与所述阱区103中掺杂的杂质离子的掺杂类型相同，所述重掺杂区115中掺杂的杂质离子的浓度大于所述阱区103中掺杂的杂质离子的浓度，所述重掺杂区115和所述第二掺杂区之间还可以形成浅沟槽隔离结构116。
对所述二极管进行电容测试时，将所述阱区103(阱区103的电压通过重掺杂区115施加)和第二掺杂区114分别施加电压，使得所述阱区103和第二掺杂区114之间存在电压差，获得电容曲线，根据所述电容曲线计算出二极管的结电容。
本申请一些实施例中还提供了一种电容测试结构，结合参考图4-图5与图6，包括：
半导体衬底101；
位于所述半导体衬底101中的阱区103，所述阱区103掺杂有第一类型的杂质离子；
位于所述半导体衬底101中包围所述阱区103的隔离掺杂区105，所述隔离掺杂区103掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；
位于所述阱区103的电容测试器件。
在一些实施例中，所述半导体衬底101为掺杂有第一类型的杂质离子的半导体衬底，所述半导体衬底101中掺杂的第一类型杂质离子的浓度小于所述阱区103中掺杂的第一类型的杂质离子浓度。
在一些实施例中，所述隔离掺杂区105包括位于阱区103底部的深掺杂区102以及位于阱区103周围的环形掺杂区104，所述环形掺杂区104底部与深掺杂区102四周边缘连接。
在一些实施例中，所述第一类型的杂质离子为P型的杂质离子，所述第二类型的杂质离子为N型的杂质离子。
在一些实施例中，所述电容测试器件为MOS器件、方块电容或者条带状氧化层测试结构或者二极管。
本实施例中，所述MOS器件为平面MOS晶体管，参考图6，所述平面MOS晶体管包括：位于所述阱区103表面的栅介质层106；位于所述栅介质层106表面的栅极107；位于所述栅极107两侧的阱区103中的源极108和漏极109。
在另一实施例中，所述MOS器件为掩埋栅MOS晶体管，参考图7，所述掩埋栅MOS晶体管包括：位于所述阱区103中的沟槽；位于所述沟槽的侧壁和底部表面的栅介质层110；位于所述栅介质层110表面且填充沟槽的栅极111；位于所述沟槽两侧的阱区103中的源极113和漏极112。
在一些实施例中，对所述MOS器件的电容测试结构进行电容测试时，
请参考图9或图10，将所述源极(108或113)、漏极(109或112)和半导体衬底101接地(Vs)，在所述栅极(107或111)上施加变化的电压V G，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效栅介质层的厚度。
在另一些实施例中，所述电容测试器件为二极管，参考图8，所述二极管包括：位于所述阱区103中的第二掺杂区114，所述第二掺杂区114掺杂有第二类型的杂质离子，所述阱区103和第二掺杂区114分别作为二极管的两个电极。在一些实施例中，所述二极管还包括位于所述第二掺杂区114两侧的阱区103内的重掺杂区115，所述重掺杂区作为二极管的一端的引出电极，所述重掺杂区115中掺杂的杂质离子的类型与所述阱区103中掺杂的杂质离子的掺杂类型相同，所述重掺杂区115中掺杂的杂质离子的浓度大于所述阱区103中掺杂的杂质离子的浓度，为了保证接触段的欧姆接触，降低接触电阻，还包括位于所述重掺杂区115和所述第二掺杂区之间的浅沟槽隔离结构116。
对所述二极管进行电容测试时，将所述阱区103(阱区103的电压通过重掺杂区115施加)和第二掺杂区114分别施加电压，具体的，继续参考图8，可以在阱区103施加电压V1，在第二掺杂区施加电压V2，V2大于V1(或者V2小于V1)，使得所述阱区103和第二掺杂区114之间存在电压差，获得电 容曲线，根据所述电容曲线计算出二极管的结电容。
需要说明的是，本实施例(电容测试结构)中与前述实施例(电容测试结构的形成方法)中相同或相似结构的其他限定或描述，在本实施例中不再赘述，具体请参考前述实施例中相应部分的限定或描述。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。

Claims (21)

  1. 一种电容测试结构，包括：
    半导体衬底；
    位于所述半导体衬底中的阱区，所述阱区掺杂有第一类型的杂质离子；
    位于所述半导体衬底中包围所述阱区的隔离掺杂区，所述隔离掺杂区掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；
    位于所述阱区的电容测试器件。
  2. 如权利要求1所述的电容测试结构，其中，所述半导体衬底为掺杂有第一类型的杂质离子的半导体衬底，所述半导体衬底中掺杂的第一类型杂质离子的浓度小于所述阱区中掺杂的第一类型的杂质离子浓度。
  3. 如权利要求2所述的电容测试结构，其中，所述隔离掺杂区包括位于阱区底部的深掺杂区以及位于阱区周围的环形掺杂区，所述环形掺杂区底部与深掺杂区四周边缘连接；所述阱区位于所述深掺杂区的上方，且所述阱区的宽度小于所述深掺杂区的宽度。
  4. 如权利要求3所述的电容测试结构，其中，所述第一类型的杂质离子为P型的杂质离子，所述第二类型的杂质离子为N型的杂质离子。
  5. 如权利要求1所述的电容测试结构，其中，所述电容测试器件为MOS器件或者二极管。
  6. 如权利要求5所述的电容测试结构，其中，所述MOS器件为平面MOS晶体管，所述平面MOS晶体管包括：位于所述阱区表面的栅介质层；位于所述栅介质层表面的栅极；位于所述栅极两侧的阱区中的源极和漏极。
  7. 如权利要求5所述的电容测试结构，其中，所述MOS器件为掩埋栅MOS晶体管，所述掩埋栅MOS晶体管包括：位于所述阱区中的沟槽；位于所述沟槽的侧壁和底部表面的栅介质层；位于所述栅介质层表面且填充沟槽的栅极；位于所述沟槽两侧的阱区中的源极和漏极。
  8. 如权利要求6或7所述的电容测试结构，其中，对所述MOS器件进行电容测试时，将所述源极、漏极和半导体衬底接地，在所述栅极上施加变化的电压，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效 栅介质层的厚度。
  9. 如权利要求5所述的电容测试结构，其中，所述二极管包括：位于所述阱区中的第二掺杂区，所述第二掺杂区的掺杂有第二类型的杂质离子，所述阱区和第二掺杂区分别作为二极管的两个电极；对所述二极管进行电容测试时，将所述阱区和第二掺杂区分别施加电压，获得电容曲线，根据所述电容曲线计算出二极管的结电容。
  10. 一种电容测试结构的形成方法，包括：
    提供半导体衬底；
    在所述半导体衬底中形成阱区，所述阱区掺杂有第一类型的杂质离子；
    在所述半导体衬底中形成包围所述阱区的隔离掺杂区，所述隔离掺杂区掺杂有第二类型的杂质离子，所述第二类型与第一类型相反；
    在所述阱区中形成电容测试器件。
  11. 如权利要求10所述的电容测试结构的形成方法，其中，所述半导体衬底为掺杂有第一类型的杂质离子的半导体衬底，所述半导体衬底中掺杂的第一类型杂质离子的浓度小于所述阱区中掺杂的第一类型的杂质离子浓度。
  12. 如权利要求11所述的电容测试结构的形成方法，其中，所述隔离掺杂区包括形成于阱区底部的深掺杂区以及形成于阱区周围的环形掺杂区，所述环形掺杂区底部与深掺杂区四周边缘连接。
  13. 如权利要求12所述的电容测试结构的形成方法，其中，通过第一离子注入形成所述深掺杂区，通过第二离子注入形成所述阱区，通过第三离子注入形成所述环形掺杂区。
  14. 如权利要求13所述的电容测试结构的形成方法，其中，所述第一类型的杂质离子为P型的杂质离子，所述第二类型的杂质离子为N型的杂质离子。
  15. 如权利要求14所述的电容测试结构的形成方法，其中，所述第一离子注入的能量范围为500KeV-1200KeV，剂量范围为1E13-5E13/cm 2，所述第三离子注入的能量范围为50KeV-200KeV，剂量范围为1E13-5E13/cm 2。
  16. 如权利要求15所述的电容测试结构的形成方法，其中，所述第二离子注入 的能量小于500KeV，剂量范围为1E12-3E13/cm 2。
  17. 如权利要求10所述的电容测试结构的形成方法，其中，所述电容测试器件为MOS器件或者二极管。
  18. 如权利要求17所述的电容测试结构的形成方法，其中，所述MOS器件为平面MOS晶体管，所述平面MOS晶体管的电容测试结构的形成过程包括：在所述阱区表面形成栅介质层；在所述栅介质层表面形成栅极；在栅极两侧的阱区中分别形成源极和漏极。
  19. 如权利要求17所述的电容测试结构的形成方法，其中，所述MOS器件为掩埋栅MOS晶体管，所述掩埋栅MOS晶体管的电容测试结构的形成过程包括：在所述阱区中形成沟槽；在所述沟槽的侧壁和底部表面形成栅介质层；在所述栅介质层表面形成填充沟槽的栅极；在所述沟槽两侧的阱区中分别形成源极和漏极。
  20. 如权利要求18或19所述的电容测试结构的形成方法，其中，对所述MOS器件进行电容测试时，将所述源极、漏极和半导体衬底接地，在所述栅极上施加变化的电压，获得电容曲线，根据所述电容曲线计算出栅介质层电容值以及有效栅介质层的厚度。
  21. 如权利要求17所述的电容测试结构的形成方法，其中，所述电容测试结构为二极管时，所述二极管的形成过程包括：在所述阱区中形成第二掺杂区，所述第二掺杂区的掺杂有第二类型的杂质离子，所述阱区和第二掺杂区分别作为二极管的两个电极；对所述二极管进行电容测试时，将所述阱区和第二掺杂区分别施加电压，获得电容曲线，根据所述电容曲线计算出二极管的结电容。
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