WO2023130567A1 - 存储器功耗确定方法及装置、存储介质及电子设备 - Google Patents

存储器功耗确定方法及装置、存储介质及电子设备 Download PDF

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Publication number
WO2023130567A1
WO2023130567A1 PCT/CN2022/080238 CN2022080238W WO2023130567A1 WO 2023130567 A1 WO2023130567 A1 WO 2023130567A1 CN 2022080238 W CN2022080238 W CN 2022080238W WO 2023130567 A1 WO2023130567 A1 WO 2023130567A1
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Prior art keywords
memory
target
change curve
power consumption
current change
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PCT/CN2022/080238
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English (en)
French (fr)
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吴钰焱
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长鑫存储技术有限公司
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Priority to US17/840,932 priority Critical patent/US11861187B2/en
Publication of WO2023130567A1 publication Critical patent/WO2023130567A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a method for determining memory power consumption, a device for determining memory power consumption, a computer-readable storage medium, and electronic equipment.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers. Due to its simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and electronics industry. application.
  • a method for determining power consumption of a memory comprising: receiving a memory control command, and controlling the analog memory to enter different working stages according to the memory control command; The original current change curve in the working stage; according to the sequence of the memory control command, determine the target time period corresponding to the target working stage; according to the target time period, intercept the target working stage from the original current change curve Corresponding stage current change curves to obtain target current change curves; according to the target working stage, select target performance parameters from the memory performance parameter table; according to the target performance parameters and the target current change curve, determine the memory power consumption.
  • the device includes: a memory simulation module, configured to receive a memory control command, and according to the memory control command Control the analog memory to enter different working stages; the original current acquisition module is used to obtain the original current change curve of the analog memory in different working stages; the target time period determination module is used to determine the time period according to the memory control command Timing, determine the target time period corresponding to the target working stage; the target current determination module is used to intercept the stage current change curve corresponding to the target working stage from the original current change curve according to the target time period, so as to obtain the target The current change curve; the target parameter determination module is used to select the target performance parameter from the memory performance parameter table according to the target working stage; the power consumption determination module is used to select the target performance parameter according to the target performance parameter and the target current change curve, Determine the memory power consumption.
  • a memory simulation module configured to receive a memory control command, and according to the memory control command Control the analog memory to enter different working stages
  • the original current acquisition module is used to obtain the original current change curve of the analog memory in different working stages
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method for determining memory power consumption is implemented.
  • an electronic device including: a processor; and a memory for storing executable instructions of the processor; wherein, the processor is configured to execute by executing the executable instructions The above-mentioned method for determining memory power consumption.
  • the original current change curve of the analog memory in different working stages can be obtained conveniently as the original current change curve of the memory for use in Subsequent power consumption determination; on the other hand, after the target working stage is determined, according to the corresponding target time period, the stage current change curve corresponding to the target working stage can be intercepted, and the target current change curve can be obtained based on the stage current change curve, Finally, combined with the target current change curve and target performance parameters, the power consumption of the memory can be determined.
  • the determined power consumption of the memory can be used as the actual power consumption of the memory for performance analysis of the memory, and can also provide a basis for system failure analysis.
  • FIG. 1 schematically shows a schematic structural diagram of a storage unit according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a schematic structural diagram of a memory peripheral circuit according to an exemplary embodiment of the present disclosure
  • Fig. 3 schematically shows a schematic diagram of a storage block in a memory according to an exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a flowchart of a method for determining memory power consumption according to an exemplary embodiment of the present disclosure
  • Fig. 5 schematically shows a schematic diagram of data processing of a phase current change curve according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically shows a block diagram of an apparatus for determining memory power consumption according to an exemplary embodiment of the present disclosure
  • Fig. 7 schematically shows a block diagram of an electronic device according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • Semiconductor memory is used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications.
  • a semiconductor memory includes a plurality of memory cells in a memory array, each memory cell storing at least one bit of information.
  • DRAM is an example of such a semiconductor memory. This scheme is preferably used in DRAM. Therefore, the ensuing description of embodiments is made with reference to a DRAM as a non-limiting example.
  • an array of memory cells is typically arranged in rows and columns such that a particular memory cell can be addressed by designating its row and column of the array.
  • the word lines connect the rows to a set of bit line sense amplifiers (Sense Amplifiers, SAs) that detect data in the cells. Then in a read operation, a subset of the data in the sense amplifiers is selected or "column selected" for output.
  • SAs bit line sense amplifiers
  • each memory cell 100 in DRAM generally comprises capacitor 110, transistor 120, word line (Word Line, WL) 130 and bit line (Bit Line, BL) 140, and the gate of transistor 120 is connected with word line 130 1.
  • the drain of the transistor 120 is connected to the bit line 140, and the source of the transistor 120 is connected to the capacitor 110.
  • the voltage signal on the word line 130 can control the opening or closing of the transistor 120, and then read and store in the capacitor 110 through the bit line 140. data information, or write the data information into the capacitor 110 through the bit line 140 for storage.
  • the storage block is composed of the above-mentioned multiple storage units.
  • the storage block generally occupies 50-65% of the area of the entire DRAM device, and the rest of the area of the DRAM device is mainly composed of peripheral circuits.
  • FIG. 2 a schematic structural diagram of a peripheral circuit is shown.
  • the peripheral circuit of the DRAM device includes a Command Decoder command decoder 210, an address latch (Address Latch) 220, a refresh address counter (Refresh Address Counter, RAC) 230, an address multiplexer (Address Mux, AM) 240 and pre-decoder (Pre-Decoder, Pre-D) 250.
  • the Command Decoder 210 is used to decode the commands CMD such as RESET_n, CKE, CK_t/CK_c, PAR, TEN, CS_n, ACT_n issued by the system, and the Address Latch 220 is used to decode the address code A ⁇ 16:0>, etc. perform temporary storage, etc.
  • the peripheral circuit of the DRAM device also includes: activation window signal generation module 260, refresh window signal generation module 270 and control signal generation module 280; activation window signal generation module 260 is used to generate memory block activation window signal BANK ACT Window Signal, refresh The window signal generation module 270 is used to generate a refresh window signal Refresh Window Signal.
  • the memory block 300 includes: a bit line BL, a complementary bit line BL_B, a plurality of word lines WL and a plurality of memory cells 100, and the plurality of memory cells 100 share the aforementioned bit line BL or complementary bit line BL_B.
  • the bit line BL and the complementary bit line BL_B are also used to access the write input drivers INPUT Write Driver and INPUT_B Write Driver, and output the output signals OUTPUT and OUTPUT_B.
  • the memory block 300 further includes: a sensing module 310 and a bit line balancing module 320, wherein the bit line balancing module 320 is used to pinch the bit line BL and the complementary bit line under the action of the bit line balancing control signal BLEQ Line BL_B, so as to close the read and write operations on the memory cell 100 .
  • the sensing module 310 mainly includes a sense amplifier, and the sense amplifier (Sense Amplifier, SA) can address a plurality of memory cells 100 through the bit line BL or BL_B.
  • SA sense Amplifier
  • a conventional sense amplifier is more specifically a differential amplifier that operates using a bit line BL and a complementary bit line BL_B (as a reference line) used as a reference line to detect and amplify the voltage difference.
  • a complete read operation stage includes four different sub-stages of precharge Precharge, read Access, sense amplification Sense and re-store Restore.
  • the write operation phase it includes five different sub-phases: Precharge, Access, Sense, Restore, and Write Recovery.
  • the specific working stages of the memory are not described in detail in the exemplary embodiments of the present disclosure, and the existing memory may be referred to.
  • the method for determining memory power consumption may include the following steps:
  • Step S410 receiving a memory control command, and controlling the analog memory to enter different working stages according to the memory control command;
  • Step S420 obtaining the original current variation curve of the analog memory in different working stages
  • Step S430 according to the timing sequence of the memory control command, determine the target time period corresponding to the target working stage
  • Step S440 according to the target time period, intercept the stage current change curve corresponding to the target working stage from the original current change curve to obtain the target current change curve;
  • Step S450 according to the target working stage, select the target performance parameter from the memory performance parameter table
  • Step S460 determining memory power consumption according to the target performance parameter and the target current change curve.
  • the original current change curves of the analog memory in different working stages can be obtained conveniently as the The original current change curve is used for subsequent determination of power consumption; on the other hand, after the target working stage is determined, according to the corresponding target time period, the stage current change curve corresponding to the target working stage can be intercepted, based on the stage current change curve The target current change curve can be obtained, and finally combined with the target current change curve and target performance parameters, the power consumption of the memory can be determined, and the determined power consumption of the memory can be used as the actual power consumption of the memory for performance analysis of the memory.
  • System failure analysis provides the basis.
  • step S410 a memory control command is received, and the analog memory is controlled to enter different working stages according to the memory control command.
  • the simulated memory is a memory model simulated according to the components of the memory and the corresponding connection relationship.
  • the memory structure can be established on the simulation software based on the actually used memory, and at the same time, it can also be based on the memory control command , to perform various operations of the memory during actual operation. That is to say, the above-mentioned simulated memory can simulate a real memory to enter different working stages, so as to obtain various required data, for example, current data, voltage data, and the like.
  • the memory has multiple control commands, such as read operation commands, write operation commands, refresh operation commands, etc. According to different control commands, the memory will enter different working stages to complete corresponding operations.
  • step S420 the original current change curves of the analog memory in different working stages are obtained.
  • the simulated memory is controlled to enter different working phases, for example, a read operation phase, a write operation phase, and a refresh operation phase.
  • different working phases for example, a read operation phase, a write operation phase, and a refresh operation phase.
  • the above-mentioned different working stages are executed at intervals, therefore, it is necessary to mark the time of entering different working stages of the analog memory.
  • the marking process it is also necessary to consider the time lag between the issuance of the memory control command and the actual start of execution. The time when the actual execution starts is used as the marking point to mark the collected data, for example, to obtain the original current change curve.
  • the above-mentioned original current change curve includes the current change data with time corresponding to multiple different working stages of the read operation stage, the write operation stage and the refresh operation stage, based on these data, subsequent memory power consumption can be determined.
  • step S430 the target time period corresponding to the target working phase is determined according to the sequence of the memory control command.
  • the memory control commands are usually issued according to the timing of the memory control commands. According to the specific issuing time of the control commands and the delay from issuing to executing the control commands, the starting point corresponding to the target working stage that needs to be acquired can be determined.
  • the target time period of the target work phase can be determined according to the execution time of the target work phase.
  • the target working phase may be at least one of different working phases, that is, the target working phase may only be a read operation phase, a write operation phase, and a refresh operation phase; it may also be a read and write operation phase, or include A complete operation stage of reading and writing refresh; or, the target working stage can also be at least one of the four different sub-stages of Precharge, Access, Sense and Restore in the read operation stage.
  • the exemplary implementation of the present disclosure is specific to the target There are no special restrictions on the working stage, which can be flexibly determined according to actual needs.
  • step S440 according to the target time period, the stage current change curve corresponding to the target working stage is intercepted from the original current change curve to obtain the target current change curve.
  • the stage current change curve corresponding to the target time period can be extracted from the original current change curve.
  • the phase current change curve corresponding to the target read operation phase the phase current change curve corresponding to the target write operation phase, and the like.
  • the current change curve of the phase needs to be processed to obtain the target current change curve.
  • the specific method of processing the current change curve in the stage can be determined according to the required memory power consumption. If the required memory power consumption is the total power consumption, the total power consumption can be determined directly according to the current change curve and combined with memory performance parameters.
  • the intercepted phase current change curve can be discretized according to the preset step size to obtain discrete data; then, determine the phase peak value and Stage valley value; And carry out linear interpolation to above-mentioned stage peak value and stage valley value, obtain interpolation line; Then, can be based on interpolation line, determine preset error range, for example, two preset error range boundaries among Fig. 5 Line, a part of the phase current change curve falls within the preset error range, and another part falls outside the preset error range.
  • the above preset error range may be determined according to actual conditions, for example, the preset error range is any value between 5% and 15%. If the preset error range is 5%, as shown in Figure 5, the boundary line of the preset error range can be determined at a position of ⁇ 5% from the interpolation line on both sides of the interpolation line, as the preset error range .
  • the above-mentioned process of determining the phase peak value and the phase valley value can also be performed before discretizing the phase current change curve, that is, directly determine the highest point from the phase current change curve as the phase peak value, and determine the phase peak value from the phase current change curve. The lowest point in the curve is determined as the stage valley. In order to improve the accuracy of determining the peak and valley of the stage, avoid the peak and valley of the stage from being lost in the discretization process.
  • the discrete data falling outside the preset error range can be obtained and recorded as overrun data, and the overrun data, phase peak value and phase valley value can be fitted to obtain the target current change curve .
  • the obtained target current change curve is mainly composed of data beyond the preset error range. Therefore, based on the target current change curve, it can be used to calculate the average over-limit power consumption of the memory, and the average over-limit power consumption of the memory can be used It is used for performance analysis and failure analysis of memory.
  • the over-limit data and the stage peak value can be directly used for fitting to obtain the target current change curve.
  • the exemplary embodiments of the present disclosure make no special limitation on the manner of determining the target current change curve.
  • the above-mentioned preset step size may be determined according to actual conditions, for example, the preset step size may be any value between 8ps-12ps, for example, 10ps. It can be understood that the smaller the step size, the higher the accuracy and the longer the simulation time. That is to say, the preset step size can be adjusted according to the required accuracy and time cost. The specific value of is not specifically limited.
  • preliminary data discretization may be performed with a larger preset step size, for example, the intercepted stage current change curve is discretized with a first preset step size to obtain first discrete data.
  • the intercepted stage current change curve is discretized with a first preset step size to obtain first discrete data.
  • it is beneficial to dynamically balance the simulation duration and simulation accuracy according to the actual waveform of the phase current change curve and it is beneficial to realize the shortening of the simulation duration and the improvement of the simulation accuracy at the same time.
  • the first preset step size is greater than the second preset step size, wherein the values of the first preset step size and the second preset step size can be determined according to actual conditions, for example, the first preset step size
  • the step size may be greater than 12ps
  • the second preset step size may be less than or equal to 12ps, and so on.
  • the exemplary embodiments of the present disclosure do not specifically limit specific values of the first preset step size and the second preset step size.
  • step S450 and step S460 according to the target working phase, the target performance parameter is selected from the memory performance parameter table; according to the target performance parameter and the target current change curve, the power consumption of the memory is determined.
  • the target current change curve is determined, it is also necessary to select the target performance parameter from the memory performance parameter table according to the target working stage. If the target working phase is the read operation phase, it is necessary to obtain the components in the memory involved in the read operation phase, and the target performance parameters can be determined from the performance parameters of these components.
  • the target performance parameters corresponding to different working stages are usually determined in advance and stored in the memory performance parameter table for later call.
  • the target performance parameter may include a resistance value, a capacitance value, an inductance value, etc. corresponding to a target working stage.
  • the memory power consumption can be determined according to the target performance parameter and in combination with the target current change curve. Specifically, in the process of determining the power consumption of the memory, the determined power consumption of the memory is different according to different target current change curves.
  • the target current change curve is the initially intercepted stage current change curve
  • the total power consumption of the memory in the target working stage can be calculated. If the target current change curve is composed of the above-mentioned overrun data, stage peak value and stage valley value, then The determined memory power consumption is memory overrun power consumption and average overrun power consumption.
  • the average over-limit current in the target working stage can be determined according to the target current change curve determined in the above step S440, wherein, in the process of determining the average over-limit current, the target The area covered by the current change curve is obtained by dividing the covered time length.
  • the average over-limit power consumption of the memory can be determined according to the average over-limit current, the resistance value, the capacitance value and the inductance value corresponding to the target working stage. The specific determination process will not be repeated here.
  • the memory may be adjusted accordingly according to the average over-limit power consumption of the memory. For example, when the average over-limit power consumption of the memory is greater than or equal to the preset power consumption, power consumption analysis is performed on the memory to adjust target performance parameters. For example, reducing the resistance value, capacitance value or inductance value, etc., the specific reduction of the resistance value may be to select components with a smaller resistance value, etc., or to reduce the operating frequency of the memory to ensure that the memory operates within a safe range.
  • the operating parameters of the target working stage in the memory can be adjusted, for example, the operating frequency of the memory can be increased, so as to improve the operating performance of the memory while ensuring that the memory operates normally.
  • the above-mentioned preset power consumption may be the limit power consumption of the memory in the target working stage stipulated in the memory-related standards, or it may be artificially set according to the actual situation, or determined by the peak value of the stage and the valley value of the stage. Exemplary embodiments do not specifically limit this.
  • the data corresponding to the target current change curve can also be processed into a data format that can be recognized by the analysis model, and the processed Input the data corresponding to the target current change curve into the analysis model to analyze the power consumption of the system to find out the possible power consumption problems of the memory, for example, whether the power consumption is caused by the memory itself or by noise.
  • the exemplary implementation of the present disclosure does not describe this data analysis method in detail.
  • the memory power consumption determination method can select the target current change curve corresponding to the target work stage according to different work stages, and then determine the possible power consumption of the memory according to the target current change curve. Average overrun power consumption. Based on the average over-limit power consumption, the target performance parameters or operating parameters of the memory can be adjusted, so that the memory can be adjusted to the best working state, and the utilization rate of the memory can be improved on the premise of meeting actual needs.
  • the memory power consumption determination device 600 may include: a memory simulation module 610, an original current acquisition module 620, a target time period determination module 630, a target current determination module 640, a target parameter determination module 650, a power consumption determination module 660 and memory adjustment module 670, wherein:
  • the memory simulation module 610 can be used to receive a memory control command, and control the simulated memory to enter different working stages according to the memory control command;
  • the original current acquisition module 620 can be used to acquire the original current change curve of the analog memory in different working stages;
  • the target time period determination module 630 can be used to determine the target time period corresponding to the target working stage according to the timing of the memory control command;
  • the target current determination module 640 can be used to intercept the stage current change curve corresponding to the target working stage from the original current change curve according to the target time period, so as to obtain the target current change curve;
  • the target parameter determination module 650 can be used to select target performance parameters from the memory performance parameter table according to the target working stage;
  • the power consumption determining module 660 may be configured to determine memory power consumption according to the target performance parameter and the target current change curve.
  • the target current determination module 640 can be used to discretize the phase current change curve according to a preset step size to obtain discrete data; determine the phase peak value and phase valley from the discrete data value; perform linear interpolation on the stage peak value and stage valley value to obtain an interpolation line; use the interpolation line as a benchmark to obtain discrete data outside the preset error range, which is recorded as overrun data; for overrun data, stage peak value and stage valley value Fitting is performed to obtain the target current change curve.
  • the target current determination module 640 can also be used to discretize the intercepted stage current change curve according to the first preset step size to obtain the first discrete data; obtain the preset error The first discrete data outside the range is recorded as the first overrun data; the phase current change curve corresponding to the period of the first overrun data is discretized with the second preset step size to obtain the second discrete data; the preset error is obtained The second discrete data outside the range is recorded as the second overrun data; the second overrun data, the phase peak value and the phase valley value are fitted to obtain the target current change curve.
  • the first preset step size is greater than the second preset step size.
  • the power consumption determination module 660 can be used to determine the average over-limit current in the target working stage according to the target current change curve; the target performance parameters include the resistance value corresponding to the target working stage, Capacitance value and inductance value; According to the average over-limit current, resistance value, capacitance value and inductance value, the average over-limit power consumption of the memory is determined.
  • the device for determining memory power consumption further includes:
  • the memory adjustment module 670 can be configured to analyze the power consumption of the memory when the average over-limit power consumption of the memory is greater than or equal to the preset power consumption, so as to adjust the target performance parameters.
  • the memory adjustment module 670 may also be configured to adjust the operating parameters of the target working stage in the memory when the average over-limit power consumption of the memory is less than the preset power consumption.
  • different working stages include: a read operation stage, a write operation stage and a refresh operation stage.
  • the target work stage is at least one of different work stages.
  • the preset error range is any value between 5% and 15%.
  • the simulated memory is a memory model simulated according to the constituent elements of the memory and corresponding connection relationships.
  • modules or units of the device for determining memory power consumption are mentioned in the above detailed description, such division is not mandatory.
  • the features and functions of two or more modules or units described above may be embodied in one module or unit.
  • the features and functions of one module or unit described above can be further divided to be embodied by a plurality of modules or units.
  • an electronic device capable of implementing the above method is also provided.
  • FIG. 7 An electronic device 700 according to this embodiment of the present invention is described below with reference to FIG. 7 .
  • the electronic device 700 shown in FIG. 7 is only an example, and should not limit the functions and application scope of the embodiments of the present invention.
  • electronic device 700 takes the form of a general-purpose computing device.
  • the components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including the storage unit 720 and the processing unit 710), and a display unit 740.
  • the storage unit 720 stores program codes, and the program codes can be executed by the processing unit 710, so that the processing unit 710 executes various examples according to the present invention described in the above-mentioned "Exemplary Methods" section of this specification. Steps of implementation.
  • the processing unit 710 may execute step S410 as shown in FIG.
  • step S420 receive a memory control command, and control the analog memory to enter different working stages according to the memory control command; step S420, obtain the simulation memory in different working stages The original current change curve; step S430, according to the timing sequence of the memory control command, determine the target time period corresponding to the target working stage; step S440, according to the target time period, intercept the stage current change curve corresponding to the target working stage from the original current change curve, Obtain the target current change curve; step S450, select the target performance parameter from the memory performance parameter table according to the target working stage; step S460, determine the power consumption of the memory according to the target performance parameter and the target current change curve.
  • the storage unit 720 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 7201 and/or a cache storage unit 7202 , and may further include a read-only storage unit (ROM) 7203 .
  • RAM random access storage unit
  • ROM read-only storage unit
  • the storage unit 720 may also include a program/utility 7204 having a set (at least one) of program modules 7205, such program modules 7205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, Implementations of networked environments may be included in each or some combination of these examples.
  • Bus 730 may represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local area using any of a variety of bus structures. bus.
  • the electronic device 700 can also communicate with one or more external devices 770 (such as keyboards, pointing devices, Bluetooth devices, etc.), and can also communicate with one or more devices that enable the user to interact with the electronic device 700, and/or communicate with Any device (eg, router, modem, etc.) that enables the electronic device 700 to communicate with one or more other computing devices. Such communication may occur through input/output (I/O) interface 750 .
  • the electronic device 700 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN) and/or a public network such as the Internet) through the network adapter 760 . As shown, the network adapter 760 communicates with other modules of the electronic device 700 through the bus 730 .
  • other hardware and/or software modules may be used in conjunction with electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives And data backup storage system, etc.
  • the example implementations described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of software products, and the software products can be stored in a non-volatile storage medium (which can be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to make a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) execute the method according to the embodiments of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, or a network device, etc.
  • a computer-readable storage medium on which a program product capable of implementing the above-mentioned method in this specification is stored.
  • various aspects of the present invention can also be implemented in the form of a program product, which includes program code, and when the program product is run on a terminal device, the program code is used to make the The terminal device executes the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section above in this specification.
  • a program product for implementing the above method according to the embodiment of the present invention, it may adopt a portable compact disc read-only memory (CD-ROM) and include program codes, and may run on a terminal device such as a personal computer.
  • CD-ROM compact disc read-only memory
  • the program product of the present invention is not limited thereto.
  • a readable storage medium may be any tangible medium containing or storing a program, and the program may be used by or in combination with an instruction execution system, apparatus or device.
  • the program product may reside on any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer readable signal medium may include a data signal carrying readable program code in baseband or as part of a carrier wave. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for carrying out the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural programming languages. Programming language - such as "C" or a similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server to execute.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (for example, using an Internet service provider). business to connect via the Internet).
  • LAN local area network
  • WAN wide area network
  • Internet service provider for example, using an Internet service provider

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Abstract

一种存储器功耗确定方法、存储器功耗确定装置、计算机可读存储介质及电子设备，涉及集成电路技术领域。该存储器功耗确定方法包括：接收存储器控制命令，根据存储器控制命令控制模拟存储器进入不同的工作阶段(S410)；获取模拟存储器在不同的工作阶段中的原始电流变化曲线(S420)；根据存储器控制命令的时序，确定目标工作阶段对应的目标时间段(S430)；根据目标时间段，从原始电流变化曲线中截取目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线(S440)；根据目标工作阶段，从存储器性能参数表中选取目标性能参数(S450)；根据目标性能参数和目标电流变化曲线，确定存储器功耗(S460)，所确定的存储器功耗可以作为存储器的实际功耗，用于存储器的性能分析，同时还可以为系统失效分析提供依据。

Description

存储器功耗确定方法及装置、存储介质及电子设备
相关申请的交叉引用
本公开要求于2022年01月06日提交的申请号为202210009824.X名称为“存储器功耗确定方法及装置、存储介质及电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种存储器功耗确定方法、存储器功耗确定装置、计算机可读存储介质及电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由于具有结构简单，密度高，功耗低，价格低廉等优点，在计算机领域和电子行业中受到了广泛的应用。
存储器功耗对于系统性能起着重要的作用，过高的存储器功耗可能会导致系统失效，因此，确定出存储器功耗，以进行系统失效分析，是确保系统正常运行的必要手段。
发明内容
根据本公开的一方面，提供一种存储器功耗确定方法，所述方法包括：接收存储器控制命令，根据所述存储器控制命令控制模拟存储器进入不同的工作阶段；获取所述模拟存储器在不同的所述工作阶段中的原始电流变化曲线；根据所述存储器控制命令的时序，确定目标工作阶段对应的目标时间段；根据所述目标时间段，从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；根据所述目标工作阶段，从存储器性能参数表中选取目标性能参数；根据所述目标性能参数和所述目标电流变化曲线，确定所述存储器功耗。
根据本公开的一方面，提供一种存储器功耗确定装置，在本公开的一种示例性实施方式中，所述装置包括：存储器模拟模块，用于接收存储器控制命令，根据所述存储器控制命令控制模拟存储器进入不同的工作阶段；原始电流获取模块，用于获取所述模拟存储器在不同的所述工作阶段中的原始电流变化曲线；目标时间段确定模块，用于根据所述存储器控制命令的时序，确定目标工作阶段对应的目标时间段；目标电流确定模块，用于根据所述目标时间段，从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；目标参数确定模块，用于根据所述目标工作阶段，从存储器性能参数表中选取目标性能参数；功耗确定模块，用于根据所述目标性能参数和所述目标电流变化曲线，确定所述存储器功耗。
根据本公开的一方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述的存储器功耗确定方法。
根据本公开的一方面，提供一种电子设备，包括：处理器；以及存储器，用于存储所述处理器的可执行指令；其中，所述处理器配置为经由执行所述可执行指令来执行上述的存储器功耗确定方法。
本公开提供的技术方案可以包括以下有益效果：
本公开示例性实施方式中，一方面，通过控制模拟存储器进入不同的工作阶段，可以方便地获取模拟存储器在不同的工作阶段中的原始电流变化曲线，以作为存储器的原始电流变化曲线，用于后续的功耗确定；另一方面，在确定出目标工作阶段后，根据对应的目标时间段，可以截取到目标工作阶段对应的阶段电流变化曲线，基于阶段电流变化曲线可以得到目标电流变化曲线，最后结合目标电流变化曲线和目标性能参数，可以确定出存储器功耗，所确定的存储器功耗可以作为存储器的实际功耗，用于存储器的性能分析，同时还可以为系统失效分析提供依据。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出了根据本公开的示例性实施例的一种存储单元的结构示意图；
图2示意性示出了根据本公开的示例性实施例的一种存储器外围电路的结构示意图；
图3示意性示出了根据本公开的示例性实施例的一种存储器中存储块的示意图；
图4示意性示出了根据本公开的示例性实施例的一种存储器功耗确定方法的流程图；
图5示意性示出了根据本公开的示例性实施例的一种阶段电流变化曲线数据处理示意图；
图6示意性示出了根据本公开的示例性实施例的一种存储器功耗确定装置的方框图；
图7示意性示出了根据本公开的示例性实施例的一种电子设备的模块示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相 同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
半导体存储器用于计算机、服务器、诸如移动电话等手持设备、打印机和许多其他电子设备和应用。半导体存储器在存储器阵列中包括多个存储单元，每个存储单元存储信息的至少一位。DRAM为这种半导体存储器的实例。本方案优选地用于DRAM中。因此，接下来的实施例描述是参考作为非限制性示例的DRAM进行的。
在DRAM集成电路设备中，存储单元阵列典型地以行和列布置，使得特定的存储单元可以通过指定其阵列的行和列来寻址。字线将行连接到一组探测单元中数据的位线感应放大器(Sense Amplifier，SA)。然后在读取操作中，选择或者“列选择”感应放大器中的数据子集用于输出。
参照图1，DRAM中的每个存储单元100通常包括电容器110、晶体管120、字线(Word Line，WL)130和位线(Bit Line，BL)140，晶体管120的栅极与字线130相连、晶体管120的漏极与位线140相连、晶体管120的源极与电容器110相连，字线130上的电压信号能够控制晶体管120的打开或关闭，进而通过位线140读取存储在电容器110中的数据信息，或者通过位线140将数据信息写入到电容器110中进行存储。
存储块就是由上述的多个存储单元所组成，存储块一般会占用整个DRAM器件面积的50-65％，DRAM器件的其余面积则主要由外围电路所组成。参照图2，示出了一种外围电路的结构示意图。如图2，DRAM器件的外围电路包括Command Decoder命令解码器210、地址锁存器(Address Latch)220、刷新地址计数器(Refresh Address Counter，RAC)230、地址多路选择器(Address Mux，AM)240和前置解码器(Pre-Decoder，Pre-D)250。其中，Command Decoder命令解码器210用于对系统下发的RESET_n、CKE、CK_t/CK_c、PAR、TEN、CS_n、ACT_n等命令CMD进行命令解码，Address Latch地址锁存器220则用于对地址代码A<16:0>等进行暂存等。
另外，DRAM器件的外围电路还包括：激活窗口信号产生模块260、刷新窗口信号产生模块270和控制信号产生模块280；激活窗口信号产生模块260用于产生存储块激活窗口信号BANK ACT Window Signal，刷新窗口信号产生模块270用于产生刷新窗口信号Refresh Window Signal。
参照图3，示出了一种存储块的结构示意图。该存储块300包括：位线BL、互补位线BL_B、若干字线WL及若干存储单元100，该若干存储单元100共用上述的位线BL或互补位线BL_B。另外，位线BL、互补位线BL_B还用于接入写输入驱动INPUT Write Driver、INPUT_B Write Driver，并输出输出信号OUTPUT、OUTPUT_B。
本公开示例性实施方式中，存储块300还包括：感应模块310和位线平衡模块320，其中，位线平衡模块320用于在位线平衡控制信号BLEQ作用下，捏合位线BL和互补位线BL_B，以达到关闭对存储单元100的读写操作。
参照图3，感应模块310主要包括感应放大器，感应放大器(Sense Amplifier，SA)可以通过位线BL或BL_B对多个存储单元100进行寻址。常规的感应放大器更具体而言是一种差分放大器，差分放大器利用位线BL和用作参考线的互补位线BL_B(作为参考线)来工作，以检测和放大一对位线BL和BL_B上的电压差。
对于一个存储器而言，通常具有多个不同的工作阶段，例如，读操作阶段、写操作阶段和刷新操作阶段等。一个完整的读操作阶段又包括了预充电Precharge、读取Access、感应放大Sense和重新存储Restore四个不同的子阶段。对于写操作阶段则包括Precharge、Access、Sense、Restore以及Write Recovery五个不同的子阶段。本公开示例性实施方式对于存储器的具体工作阶段不做详细描述，参照现有的存储器即可。
本公开示例性实施方式提供的存储器功耗确定方法，参照图4，可以包括以下步骤：
步骤S410、接收存储器控制命令，根据存储器控制命令控制模拟存储器进入不同的工作阶段；
步骤S420、获取模拟存储器在不同的工作阶段中的原始电流变化曲线；
步骤S430、根据存储器控制命令的时序，确定目标工作阶段对应的目标时间段；
步骤S440、根据目标时间段，从原始电流变化曲线中截取目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；
步骤S450、根据目标工作阶段，从存储器性能参数表中选取目标性能参数；
步骤S460、根据目标性能参数和目标电流变化曲线，确定存储器功耗。
本公开示例性实施方式提供的存储器功耗确定方法中，一方面，通过控制模拟存储器进入不同的工作阶段，可以方便地获取模拟存储器在不同的工作阶段中的原始电流变化曲线，以作为存储器的原始电流变化曲线，用于后续的功耗确定；另一方面，在确定出目标工作阶段后，根据对应的目标时间段，可以截取到目标工作阶段对应的阶段电流变化曲线，基于阶段电流变化曲线可以得到目标电流变化曲线，最后结合目标电流变化曲线和目标性能参数，可以确定出存储器功耗，所确定的存储器功耗可以作为存储器的实际功耗，用于存储器的性能分析，同时还可以为系统失效分析提供依据。
在步骤S410中，接收存储器控制命令，根据存储器控制命令控制模拟存储器进入不同的工作阶段。
本公开示例性实施方式中，模拟存储器是根据存储器的组成元件及相应的连接关系模 拟的存储器模型，例如，可以基于实际所使用的存储器在模拟软件上建立存储器结构，同时还可以根据存储器控制命令，执行存储器在实际运行过程中的各种操作。也就是说，上述的模拟存储器可以模拟真实的存储器进入不同的工作阶段，以便于获取所需要的各种数据，例如，电流数据、电压数据等。
在实际应用中，存储器具有多个控制命令，例如，读操作命令、写操作命令、刷新操作命令等，根据不同的控制命令，存储器会进入不同的工作阶段，从而完成相应的操作。
本公开示例性实施方式中，通过模拟存储器来模拟真实的存储器进入不同的工作阶段，可以解决真实的存储器在工作过程中，其电流数据或电压数据等较难记录获取的问题。
在步骤S420中，获取模拟存储器在不同的工作阶段中的原始电流变化曲线。
根据存储器控制命令控制模拟存储器进入不同的工作阶段，例如，读操作阶段、写操作阶段和刷新操作阶段等。通常，上述不同的工作阶段会间隔执行，因此，需要对模拟存储器进入的不同工作阶段的时间进行标记。同时在标记过程中，还需要考虑存储器控制命令发出和真正开始执行在时间上的滞后性，以真正执行开始的时间作为标记点，对采集的数据进行标记，例如，从而获得原始电流变化曲线。
上述原始电流变化曲线包含有读操作阶段、写操作阶段和刷新操作阶段多个不同的工作阶段所对应的电流随时间的变化数据，基于这些数据可以进行后续的存储器功耗确定。
在步骤S430中，根据存储器控制命令的时序，确定目标工作阶段对应的目标时间段。
在实际应用中，存储器控制命令通常是根据存储器控制命令的时序发出的，根据控制命令的具体发出时间，以及控制命令从发出到执行的延迟，可以确定出所需要获取的目标工作阶段所对应的起始时间点，再根据目标工作阶段的执行时长，即可确定出目标工作阶段的目标时间段。
本公开示例性实施方式中，目标工作阶段可以是不同的工作阶段中的至少一个，即目标工作阶段可以只是读操作阶段、写操作阶段、刷新操作阶段；还可以是读写操作阶段，或者包括读写刷新的一个完整操作阶段；又或者，目标工作阶段还可以是读操作阶段中的Precharge、Access、Sense和Restore四个不同子阶段中的至少一个，本公开示例性实施方式对于具体的目标工作阶段不作特殊限定，可根据实际需要灵活确定。
在步骤S440中，根据目标时间段，从原始电流变化曲线中截取目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线。
在根据步骤S430确定出目标时间段之后，就可以从原始电流变化曲线中截取出目标时间段对应的阶段电流变化曲线，也即目标工作阶段对应的阶段电流变化曲线。例如，目标读操作阶段对应的阶段电流变化曲线、目标写操作阶段对应的阶段电流变化曲线等。
本公开示例性实施方式中，在截取到目标工作阶段对应的阶段电流变化曲线之后，还需要对该阶段电流变化曲线进行处理，以获得目标电流变化曲线。
具体的处理阶段电流变化曲线的方式可以根据所需要的存储器功耗来确定，如果所需要确定的存储器功耗为总功耗，可以直接根据电流变化曲线，结合存储器性能参数确定总 功耗。
本公开示例性实施方式中，以所需要确定的存储器功耗为存储器平均超限功耗为例，对截取的阶段电流变化曲线的处理过程进行详细说明：
参照图5，在截取到目标工作阶段对应的阶段电流变化曲线之后，可以按照预设步长，对截取的阶段电流变化曲线离散化，获得离散数据；接着，从离散数据中确定出阶段峰值和阶段谷值；并对上述的阶段峰值和阶段谷值进行线性插值，获得插值线；接着，可以以插值线为基准，确定预设误差范围，例如，图5中的两条预设误差范围边界线，阶段电流变化曲线的一部分落入到预设误差范围内，另一部分落入到预设误差范围外。
在实际应用中，上述的预设误差范围可以根据实际情况来确定，例如，预设误差范围为5％-15％之间的任一值。假如预设误差范围为5％，如图5所示，可以以插值线为基准，在插值线的两侧距离插值线±5％的位置确定出预设误差范围边界线，作为预设误差范围。
需要说明的是，上述确定阶段峰值和阶段谷值的过程，也可以在对阶段电流变化曲线进行离散化之前进行，即直接从阶段电流变化曲线中确定出最高点作为阶段峰值，从阶段电流变化曲线中确定出最低点作为阶段谷值。以提高阶段峰值和阶段谷值确定的准确性，避免阶段峰值和阶段谷值在离散化过程中丢失。
本公开示例性实施方式中，可以获取落入到预设误差范围外的离散数据，记为超限数据，对该超限数据、阶段峰值以及阶段谷值进行拟合，以获得目标电流变化曲线。其中，所获得的目标电流变化曲线主要是由超出预设误差范围外的数据组成，因此，基于该目标电流变化曲线可以用于计算存储器平均超限功耗，该存储器平均超限功耗可以用于对存储器进行性能分析、失效分析等。
需要说明的是，在平均超限功耗确定过程中，还可以不选择阶段谷值，而直接使用超限数据和阶段峰值进行拟合，来获得目标电流变化曲线。本公开示例性实施方式对于目标电流变化曲线的确定方式不作特殊限定。
在实际应用中，上述的预设步长可以根据实际情况确定，例如，预设步长可以为8ps-12ps之间的任一值，例如10ps。可以理解的是，步长越小，精度越高，模拟时长越长，也就是说，可以根据所需精度和时间成本对预设步长进行调节，本公开示例性实施方式对于预设步长的具体取值不作特殊限定。
在一些实施例中，还可以先以较大的预设步长进行初步的数据离散，例如，以第一预设步长，对截取的阶段电流变化曲线离散化，获得第一离散数据。获取预设误差范围外的第一离散数据，记为第一超限数据；再对第一超限数据所在时段对应的阶段电流变化曲线以较小的第二预设步长进行进一步的数据离散，以获得第二离散数据，获取预设误差范围外的第二离散数据，记为第二超限数据；后续再对第二超限数据、阶段峰值以及阶段谷值进行拟合，以获得目标电流变化曲线。如此，有利于根据阶段电流变化曲线的实际波形动态平衡模拟时长和模拟精度，有利于同时实现模拟时长的缩短和模拟精度的提高。
在实际应用中，第一预设步长大于第二预设步长，其中，第一预设步长和第二预设步 长的取值可以根据实际情况来确定，例如，第一预设步长可以大于12ps，第二预设步长可以小于或等于12ps等。本公开示例性实施方式对于第一预设步长和第二预设步长的具体取值不作特殊限定。
在步骤S450和步骤S460中，根据目标工作阶段，从存储器性能参数表中选取目标性能参数；根据目标性能参数和目标电流变化曲线，确定存储器功耗。
本公开示例性实施方式中，在确定出目标电流变化曲线后，还需要根据目标工作阶段，从存储器性能参数表中选取目标性能参数。假如目标工作阶段为读操作阶段，则需要获取读操作阶段所牵扯到的存储器中的组成元件，由这些组成元件的性能参数即可确定出目标性能参数。
在实际应用中，根据所模拟的实际存储器的情况，通常会将不同的工作阶段对应的目标性能参数提前确定好，存储在存储器性能参数表中，便于后期的调用。其中，目标性能参数可以包括目标工作阶段对应的电阻值、电容值和电感值等。
在选取出目标性能参数后，即可根据该目标性能参数，结合目标电流变化曲线，来确定存储器功耗。具体在确定存储器功耗过程中，根据目标电流变化曲线的不同，所确定的存储器功耗不同。
如果目标电流变化曲线就是初始所截取的阶段电流变化曲线，则可以计算存储器在目标工作阶段的总功耗，如果目标电流变化曲线是上述的超限数据、阶段峰值以及阶段谷值所组成，则所确定的存储器功耗就是存储器超限功耗和平均超限功耗。
以存储器平均超限功耗的确定为例，可以根据上述步骤S440所确定的目标电流变化曲线，确定出目标工作阶段的平均超限电流，其中，在平均超限电流确定过程中，可以通过目标电流变化曲线所覆盖的面积除以所覆盖的时间长度获得。最后，即可根据平均超限电流、目标工作阶段对应的电阻值、电容值和电感值，来确定存储器平均超限功耗。具体的确定过程此处不再赘述。
本公开示例性实施方式中，在确定出存储器平均超限功耗之后，可以根据存储器平均超限功耗的大小对存储器进行相应调整。例如，在存储器平均超限功耗大于或等于预设功耗的时候，对存储器进行功耗分析，以调整目标性能参数。例如，降低电阻值、电容值或电感值等，具体的降低电阻值可以是选择电阻值更小的组成元件等，也可以是降低存储器运行的频率，以保证存储器运行在安全范围内。在存储器平均超限功耗小于预设功耗时，可以调整存储器中目标工作阶段的运行参数，例如，提高存储器运行的频率等，在保证存储器运行正常的情况下，提高存储器的运行性能。
在实际应用中，上述预设功耗可以是存储器相关标准所规定的存储器在目标工作阶段的极限功耗，也可以根据实际情况人为设定，或者由阶段峰值和阶段谷值来确定，本公开示例性实施方式对此不作特殊限定。
需要说明的是，在确定出目标电流变化曲线，除过上述直接确定存储器功耗的方法之外，还可以将目标电流变化曲线对应的数据处理成分析模型可识别的数据格式，并将处理 后的目标电流变化曲线对应的数据输入到分析模型中，进行系统功耗分析，以找出存储器可能存在的功耗问题，例如，功耗是由存储器自身造成，还是由于噪声所引起等。本公开示例性实施方式对于此种数据分析方式不作赘述。
综上所述，本公开示例性实施方式提供的存储器功耗确定方法，可以根据不同的工作阶段，选择目标工作阶段对应的目标电流变化曲线，再根据该目标电流变化曲线确定出存储器可能存在的平均超限功耗。基于该平均超限功耗可以对存储器的目标性能参数或者运行参数进行调整，从而将存储器调整到最好的工作状态，在满足实际需要的前提下，提高存储器的利用率。
需要说明的是，尽管在附图中以特定顺序描述了本发明中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
此外，在本示例实施例中，还提供了一种存储器功耗确定装置。参照图6，该存储器功耗确定装置600可以包括：存储器模拟模块610、原始电流获取模块620、目标时间段确定模块630、目标电流确定模块640、目标参数确定模块650、功耗确定模块660和存储器调整模块670，其中：
存储器模拟模块610，可以用于接收存储器控制命令，根据存储器控制命令控制模拟存储器进入不同的工作阶段；
原始电流获取模块620，可以用于获取模拟存储器在不同的工作阶段中的原始电流变化曲线；
目标时间段确定模块630，可以用于根据存储器控制命令的时序，确定目标工作阶段对应的目标时间段；
目标电流确定模块640，可以用于根据目标时间段，从原始电流变化曲线中截取目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；
目标参数确定模块650，可以用于根据目标工作阶段，从存储器性能参数表中选取目标性能参数；
功耗确定模块660，可以用于根据目标性能参数和目标电流变化曲线，确定存储器功耗。
在本公开的一种示例性实施方式中，目标电流确定模块640，可以用于按照预设步长，对阶段电流变化曲线离散化，获得离散数据；从离散数据中确定出阶段峰值和阶段谷值；对阶段峰值和阶段谷值进行线性插值，获得插值线；以插值线为基准，获取预设误差范围外的离散数据，记为超限数据；对超限数据、阶段峰值以及阶段谷值进行拟合，获得目标电流变化曲线。
在本公开的一种示例性实施方式中，目标电流确定模块640，还可以用于按照第一预设步长，对截取的阶段电流变化曲线离散化，获得第一离散数据；获取预设误差范围外的 第一离散数据，记为第一超限数据；对第一超限数据所在时段对应的阶段电流变化曲线以第二预设步长离散化，获得第二离散数据；获取预设误差范围外的第二离散数据，记为第二超限数据；对第二超限数据、阶段峰值和阶段谷值进行拟合，获得目标电流变化曲线。
在本公开的一种示例性实施方式中，第一预设步长大于第二预设步长。
在本公开的一种示例性实施方式中，功耗确定模块660，可以用于根据目标电流变化曲线，确定出目标工作阶段的平均超限电流；目标性能参数包括目标工作阶段对应的电阻值、电容值和电感值；根据平均超限电流、电阻值、电容值和电感值，确定出存储器平均超限功耗。
在本公开的一种示例性实施方式中，存储器功耗确定装置还包括：
存储器调整模块670，可以用于在存储器平均超限功耗大于或等于预设功耗的时候，对存储器进行功耗分析，以调整目标性能参数。
在本公开的一种示例性实施方式中，存储器调整模块670，还可以用于在存储器平均超限功耗小于预设功耗时，调整存储器中目标工作阶段的运行参数。
在本公开的一种示例性实施方式中，不同的工作阶段包括：读操作阶段、写操作阶段和刷新操作阶段。
在本公开的一种示例性实施方式中，目标工作阶段是不同的工作阶段中的至少一个。
在本公开的一种示例性实施方式中，预设误差范围为5％-15％之间的任一值。
在本公开的一种示例性实施方式中，模拟存储器是根据存储器的组成元件及相应的连接关系模拟的存储器模型。
上述中各存储器功耗确定装置的虚拟模块的具体细节已经在对应的存储器功耗确定方法中进行了详细的描述，因此，此处不再赘述。
应当注意，尽管在上文详细描述中提及了存储器功耗确定装置的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本发明的各个方面可以实现为系统、方法或程序产品。因此，本发明的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图7来描述根据本发明的这种实施方式的电子设备700。图7显示的电子设备700仅仅是一个示例，不应对本发明实施例的功能和使用范围带来任何限制。
如图7所示，电子设备700以通用计算设备的形式表现。电子设备700的组件可以包括但不限于：上述至少一个处理单元710、上述至少一个存储单元720、连接不同系统组件(包括存储单元720和处理单元710)的总线730、显示单元740。
其中，所述存储单元720存储有程序代码，所述程序代码可以被所述处理单元710执行，使得所述处理单元710执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。例如，所述处理单元710可以执行如图4中所示的步骤S410、接收存储器控制命令，根据存储器控制命令控制模拟存储器进入不同的工作阶段；步骤S420、获取模拟存储器在不同的工作阶段中的原始电流变化曲线；步骤S430、根据存储器控制命令的时序，确定目标工作阶段对应的目标时间段；步骤S440、根据目标时间段，从原始电流变化曲线中截取目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；步骤S450、根据目标工作阶段，从存储器性能参数表中选取目标性能参数；步骤S460、根据目标性能参数和目标电流变化曲线，确定存储器功耗。
存储单元720可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)7201和/或高速缓存存储单元7202，还可以进一步包括只读存储单元(ROM)7203。
存储单元720还可以包括具有一组(至少一个)程序模块7205的程序/实用工具7204，这样的程序模块7205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线730可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备700也可以与一个或多个外部设备770(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备700交互的设备通信，和/或与使得该电子设备700能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口750进行。并且，电子设备700还可以通过网络适配器760与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器760通过总线730与电子设备700的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备700使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本发明的各个方面还可以实 现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本发明各种示例性实施方式的步骤。
根据本发明的实施方式的用于实现上述方法的程序产品，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本发明的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本发明操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指 出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (20)

  1. 一种存储器功耗确定方法，包括：
    接收存储器控制命令，根据所述存储器控制命令控制模拟存储器进入不同的工作阶段；
    获取所述模拟存储器在不同的所述工作阶段中的原始电流变化曲线；
    根据所述存储器控制命令的时序，确定目标工作阶段对应的目标时间段；
    根据所述目标时间段，从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；
    根据所述目标工作阶段，从存储器性能参数表中选取目标性能参数；
    根据所述目标性能参数和所述目标电流变化曲线，确定所述存储器功耗。
  2. 根据权利要求1所述的方法，其中，所述从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线，包括：
    按照预设步长，对截取的所述阶段电流变化曲线离散化，获得离散数据；
    从所述离散数据中确定出阶段峰值和阶段谷值；
    对所述阶段峰值和所述阶段谷值进行线性插值，获得插值线；
    以所述插值线为基准，获取预设误差范围外的所述离散数据，记为超限数据；
    对所述超限数据、所述阶段峰值以及所述阶段谷值进行拟合，获得所述目标电流变化曲线。
  3. 根据权利要求1所述的方法，其中，所述从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线，包括：
    按照第一预设步长，对截取的所述阶段电流变化曲线离散化，获得第一离散数据；
    获取预设误差范围外的所述第一离散数据，记为第一超限数据；
    对所述第一超限数据所在时段对应的所述阶段电流变化曲线以第二预设步长离散化，获得第二离散数据；
    获取所述预设误差范围外的所述第二离散数据，记为第二超限数据；
    对所述第二超限数据、所述阶段峰值和所述阶段谷值进行拟合，获得所述目标电流变化曲线。
  4. 根据权利要求3所述的方法，其中，所述第一预设步长大于所述第二预设步长。
  5. 根据权利要求2-4中任一项所述的方法，其中，所述根据所述目标性能参数和所述目标电流变化曲线，确定所述存储器功耗包括：
    根据所述目标电流变化曲线，确定出所述目标工作阶段的平均超限电流；
    所述目标性能参数包括所述目标工作阶段对应的电阻值、电容值和电感值；
    根据所述平均超限电流、所述电阻值、所述电容值和所述电感值，确定出存储器平均超限功耗。
  6. 根据权利要求5所述的方法，其中，所述方法还包括：
    在所述存储器平均超限功耗大于或等于预设功耗的时候，对所述存储器进行功耗分析，以调整所述目标性能参数。
  7. 根据权利要求5所述的方法，其中，所述方法还包括：
    在所述存储器平均超限功耗小于所述预设功耗时，调整所述存储器中所述目标工作阶段的运行参数。
  8. 根据权利要求1所述的方法，其中，不同的所述工作阶段包括：读操作阶段、写操作阶段和刷新操作阶段。
  9. 根据权利要求8所述的方法，其中，所述目标工作阶段是不同的所述工作阶段中的至少一个。
  10. 根据权利要求2-4中任一项所述的方法，其中，所述预设误差范围为5％-15％之间的任一值。
  11. 根据权利要求1所述的方法，其中，所述模拟存储器是根据所述存储器的组成元件及相应的连接关系模拟的存储器模型。
  12. 一种存储器功耗确定装置，包括：
    存储器模拟模块，用于接收存储器控制命令，根据所述存储器控制命令控制模拟存储器进入不同的工作阶段；
    原始电流获取模块，用于获取所述模拟存储器在不同的所述工作阶段中的原始电流变化曲线；
    目标时间段确定模块，用于根据所述存储器控制命令的时序，确定目标工作阶段对应的目标时间段；
    目标电流确定模块，用于根据所述目标时间段，从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线；
    目标参数确定模块，用于根据所述目标工作阶段，从存储器性能参数表中选取目标性能参数；
    功耗确定模块，用于根据所述目标性能参数和所述目标电流变化曲线，确定所述存储器功耗。
  13. 根据权利要求12所述的装置，其中，所述目标电流确定模块，用于按照 预设步长，对所述阶段电流变化曲线离散化，获得离散数据；对阶段峰值和阶段谷值进行线性插值，获得插值线；以所述插值线为基准，获取预设误差范围外的所述离散数据，记为超限数据；对所述超限数据、所述阶段峰值以及所述阶段谷值进行拟合，获得所述目标电流变化曲线。
  14. 根据权利要求12所述的装置，其中，所述从所述原始电流变化曲线中截取所述目标工作阶段对应的阶段电流变化曲线，以获得目标电流变化曲线，包括：
    按照第一预设步长，对截取的所述阶段电流变化曲线离散化，获得第一离散数据；
    获取预设误差范围外的所述第一离散数据，记为第一超限数据；
    对所述第一超限数据所在时段对应的所述阶段电流变化曲线以第二预设步长离散化，获得第二离散数据；
    获取所述预设误差范围外的所述第二离散数据，记为第二超限数据；
    对所述第二超限数据、所述阶段峰值和所述阶段谷值进行拟合，获得所述目标电流变化曲线。
  15. 根据权利要求14所述的装置，其中，所述第一预设步长大于所述第二预设步长。
  16. 根据权利要求13-15中任一项所述的装置，其中，所述功耗确定模块，用于根据所述目标电流变化曲线，确定出所述目标工作阶段的平均超限电流；所述目标性能参数包括所述目标工作阶段对应的电阻值、电容值和电感值；根据所述平均超限电流、所述电阻值、所述电容值和所述电感值，确定出存储器平均超限功耗。
  17. 根据权利要求16所述的装置，其中，所述装置还包括：
    存储器调整模块，用于在所述存储器平均超限功耗大于或等于预设功耗的时候，对所述存储器进行功耗分析，以调整所述目标性能参数。
  18. 根据权利要求16所述的装置，其中，所述存储器调整模块，还用于在所述存储器平均超限功耗小于所述预设功耗时，调整所述存储器中所述目标工作阶段的运行参数。
  19. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-11中任意一项所述的存储器功耗确定方法。
  20. 一种电子设备，包括：
    处理器；以及
    存储器，用于存储所述处理器的可执行指令；
    其中，所述处理器配置为经由执行所述可执行指令来执行权利要求1-11中任意一项所述的存储器功耗确定方法。
PCT/CN2022/080238 2022-01-06 2022-03-10 存储器功耗确定方法及装置、存储介质及电子设备 WO2023130567A1 (zh)

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CN101329907A (zh) * 2008-07-24 2008-12-24 中国科学院上海微系统与信息技术研究所 一种降低相变存储器编程功耗的系统及方法
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