WO2023127385A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2023127385A1
WO2023127385A1 PCT/JP2022/044249 JP2022044249W WO2023127385A1 WO 2023127385 A1 WO2023127385 A1 WO 2023127385A1 JP 2022044249 W JP2022044249 W JP 2022044249W WO 2023127385 A1 WO2023127385 A1 WO 2023127385A1
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WIPO (PCT)
Prior art keywords
wiring
power supply
semiconductor chip
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/044249
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English (en)
French (fr)
Japanese (ja)
Inventor
淳司 岩堀
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Socionext Inc
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Socionext Inc
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Application filed by Socionext Inc filed Critical Socionext Inc
Priority to CN202280080227.4A priority Critical patent/CN118355485A/zh
Priority to JP2023570747A priority patent/JPWO2023127385A1/ja
Publication of WO2023127385A1 publication Critical patent/WO2023127385A1/ja
Priority to US18/752,353 priority patent/US20240347460A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/981—Power supply lines

Definitions

  • the present disclosure relates to a semiconductor integrated circuit device in which semiconductor chips are stacked.
  • a standard cell method is known as a method of forming a semiconductor integrated circuit on a semiconductor substrate.
  • basic units for example, inverters, latches, flip-flops, full adders, etc.
  • multiple standard cells are arranged on a semiconductor substrate. Then, by connecting these standard cells with wiring, an LSI chip is designed.
  • BI Buried Interconnect
  • Patent Document 1 discloses a technique of using a wiring provided in a buried wiring layer as a power wiring (Buried Power Rail (BPR)) and also as a signal wiring.
  • Patent Literature 2 discloses a technique of connecting embedded power wiring to the rear surface of a chip via a TSV (Through Silicon Via).
  • Patent Documents 1 and 2 do not disclose how the signal wiring formed on the main chip is connected to the back surface of the chip.
  • the present disclosure provides, in a semiconductor integrated circuit device in which semiconductor chips are stacked, a configuration for connecting signal wirings formed on a main chip to the back surface of the chip, which has easy manufacturability and reliability.
  • a semiconductor integrated circuit device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the rear surface of the first semiconductor chip and the second semiconductor chip
  • the first semiconductor chip is provided in a plurality of standard cells and an embedded wiring layer, extends in a first direction, and applies a first power supply voltage to the plurality of standard cells.
  • a first power supply wiring which is provided in the embedded wiring layer, extends in the first direction, and is arranged adjacent to the first power supply wiring in a second direction perpendicular to the first direction.
  • a second power supply wiring for supplying a second power supply voltage to the plurality of standard cells; , a third power supply wiring arranged adjacent to the opposite side of the first power supply wiring and supplying the first power supply voltage to the plurality of standard cells; a first contact provided between the back surface of the first semiconductor chip; a second contact provided between the second power supply wiring and the back surface of the first semiconductor chip; and a first contact connected to one of the plurality of standard cells.
  • 1 signal wiring and a back surface of the first semiconductor chip, wherein the third contact overlaps the second power supply wiring in the second direction in plan view. and at a position different from the first and second contacts in the first direction.
  • the first semiconductor chip and the second semiconductor chip are stacked, and the back surface of the first semiconductor chip faces the main surface of the second semiconductor chip.
  • the first semiconductor chip is formed in the embedded wiring layer, extends in the first direction, and includes first, second and third power supply wirings adjacent to each other in the second direction. It also has first and second contacts provided between the first and second power supply wirings and the back surface of the chip, and a third contact provided between the signal wirings and the back surface of the chip.
  • the third contact overlaps the second power supply wiring in the second direction, and is located at a different position from the first and second contacts in the first direction.
  • a sufficient distance can be secured between the third contact and the first and second contacts. Therefore, even if the size of the third contact in a plan view is increased, manufacturing can be facilitated and reliability can be improved. can be ensured.
  • a semiconductor integrated circuit device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the rear surface of the first semiconductor chip and the second semiconductor chip
  • the first semiconductor chip is provided in a plurality of standard cells and an embedded wiring layer, extends in a first direction, and applies a first power supply voltage to the plurality of standard cells.
  • a first power supply wiring which is provided in the embedded wiring layer, extends in the first direction, and is arranged adjacent to the first power supply wiring in a second direction perpendicular to the first direction.
  • a second power supply wiring for supplying a second power supply voltage to the plurality of standard cells; , a third power supply wiring arranged adjacent to the opposite side of the first power supply wiring and supplying the first power supply voltage to the plurality of standard cells; a first contact provided between the rear surface of the first semiconductor chip; a second contact provided between the second power supply wiring and the rear surface of the first semiconductor chip; and a signal connected to one of the plurality of standard cells.
  • a third contact provided between the wiring and the back surface of the first semiconductor chip, wherein the third contact overlaps the second contact in the second direction in plan view; Moreover, it is located at a position different from that of the first and second contacts in the first direction.
  • the first semiconductor chip and the second semiconductor chip are stacked, and the back surface of the first semiconductor chip faces the main surface of the second semiconductor chip.
  • the first semiconductor chip is formed in an embedded wiring layer, extends in a first direction, and includes first, second, and third power supply wirings adjacent to each other in a second direction. It also has first and second contacts provided between the first and second power supply wirings and the back surface of the chip, and a third contact provided between the signal wirings and the back surface of the chip.
  • the third contact overlaps the second contact in the second direction and is located at a position different from the first and second contacts in the first direction in plan view.
  • a semiconductor integrated circuit device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein the back surface of the first semiconductor chip and the second semiconductor chip
  • the first semiconductor chip is provided in a plurality of standard cells and an embedded wiring layer, extends in a first direction, and applies a first power supply voltage to the plurality of standard cells.
  • a first power supply wiring for supplying power, a first contact provided between the first power supply wiring and the rear surface of the first semiconductor chip, a first signal wiring connected to one of the plurality of standard cells, a second contact provided between the back surface of the first semiconductor chip, the first power wiring having first and second portions separated from each other in the first direction, and the second contact is positioned between the first portion and the second portion in the first direction in a plan view, and the first power supply wiring in a second direction perpendicular to the first direction has an overlap with
  • the first semiconductor chip and the second semiconductor chip are stacked, and the back surface of the first semiconductor chip faces the main surface of the second semiconductor chip.
  • the first semiconductor chip includes a first power supply wiring formed in an embedded wiring layer and extending in a first direction. It also has a first contact provided between the first power supply wiring and the back surface of the chip, and a second contact provided between the signal wiring and the back surface of the chip.
  • the first power supply wiring has first and second portions separated from each other in the first direction, and the second contact is positioned between the first portion and the second portion in the first direction in plan view. and overlaps with the first power supply wiring in a second direction perpendicular to the first direction.
  • Block layout example in the semiconductor integrated circuit device of FIG. are layout examples of power supply cells.
  • Layout example with TSV for power supply in normal cell Inverter circuit configuration Layout example of cell with signal TSV Sectional view of the structure of FIG.
  • Layout example of cell with signal TSV Sectional view in the structure of FIG. Layout example of cell with signal TSV
  • Layout example of cell with signal TSV Layout example of cell with signal TSV
  • the horizontal direction of the drawing is the X direction (corresponding to the first direction), and the vertical direction of the drawing is the Y direction (corresponding to the second direction).
  • the direction perpendicular to the substrate surface is defined as the Z direction (corresponding to the depth direction).
  • VDD indicates a power supply voltage, a high voltage power supply itself or a high voltage power supply line
  • VVS indicates a power supply voltage, a low voltage power supply itself or a low voltage power supply line.
  • the standard cell is abbreviated as “cell” as appropriate.
  • FIG. 1 is a diagram showing the overall configuration of a semiconductor integrated circuit device according to an embodiment.
  • a semiconductor integrated circuit device 100 is configured by stacking a first semiconductor chip 101 (chip A, main chip) and a second semiconductor chip 102 (chip B, rear chip). ing.
  • a circuit including a plurality of transistors is formed in the first semiconductor chip 101 .
  • the second semiconductor chip 102 is not formed with elements such as transistors, but is provided with power supply wirings formed in a plurality of wiring layers.
  • the back surface of the first semiconductor chip 101 faces the main surface of the second semiconductor chip 102 .
  • FIG. 2 is a plan view showing an example of a block layout in the semiconductor integrated circuit device of FIG. 1
  • FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along line Y1-Y1' of FIG.
  • a plurality of standard cells SC are arranged side by side in the X direction and the Y direction in the first semiconductor chip 101 .
  • FIG. 2 only power supply wiring and contacts (TSV) formed in the embedded wiring layer (BI) are shown for the first semiconductor chip 101, and for the second semiconductor chip 102, the first metal wiring layer (BM1 ), the wiring formed in the second metal wiring layer (BM2), and the contacts therebetween.
  • TSV power supply wiring and contacts
  • the embedded power wiring 11 that supplies VDD to the standard cells SC and the embedded power wiring 12 that supplies VSS to the standard cells SC extend in the X direction.
  • the embedded power supply wiring 11 and the embedded power supply wiring 12 are alternately arranged in the Y direction, and each standard cell SC is arranged between the embedded power supply wiring 11 and the embedded power supply wiring 12.
  • VDD is supplied from wiring 11 and VSS is supplied from embedded power supply wiring 12 .
  • the power wiring 21 for supplying VDD and the power wiring 22 for supplying VSS extend in the Y direction.
  • the power supply wirings 21 and 22 form a pair and are arranged at a predetermined interval in the X direction.
  • a power supply wiring 25 that supplies VDD and a power supply wiring 26 that supplies VSS extend in the X direction.
  • the power wiring 21 and the power wiring 25 are connected via contacts.
  • the power wiring 22 and the power wiring 26 are connected via contacts.
  • power supply cells 31 are arranged at positions overlapping the power supply wirings 21 and 22 of the second semiconductor chip 102 in plan view.
  • the power supply cells 31 are arranged in the Y direction and have a TSV 41 for VDD and a TSV 42 for VSS.
  • the embedded power wiring 11 of the first semiconductor chip 101 and the power wiring 21 of the second semiconductor chip 102 are connected via the TSV 41 .
  • the embedded power wiring 12 of the first semiconductor chip 101 and the power wiring 22 of the second semiconductor chip 102 are connected via the TSV 42 .
  • the details of the configuration of the power supply cell 31 will be described later.
  • the TSV (VDD TSV 41 in FIG. 3) formed in the first semiconductor chip 101 is embedded power supply wiring (VDD embedded in FIG.
  • the size (depth) in the Z direction is large because the via reaches from the embedded power supply wiring 11) to the rear surface.
  • the VSS TSV 42 also increases in size in the Z direction. Therefore, it is necessary to increase the size of the TSV in plan view in order to sufficiently suppress the resistance value and to make the TSV highly reliable and manufacturable. That is, by increasing the planar size of the TSV, the power supply voltage drop can be suppressed.
  • the TSVs 41 overlap the power supply wirings 21 in plan view and are arranged in a line in the Y direction.
  • the TSVs 42 overlap the power supply wiring 22 in a plan view, and are arranged in a row in the Y direction. That is, the VDD TSV 41 and the VSS TSV 42 are arranged at different positions in the X direction. Thereby, the power wirings 21 and 22 of the second semiconductor chip 102 can be arranged in a straight line.
  • a sufficiently wide space can be secured between the TSV 41 for VDD and the TSV 42 for VSS, it is possible to easily manufacture a TSV having a large planar size and ensure reliability.
  • the plurality of standard cells SC include standard cells SCA and SCB having signal TSVs.
  • Cells SCA and SCB are double height cells.
  • the cell SCA has a signal TSV 51 .
  • the cell SCB has a signal TSV 52 .
  • the TSV 51 of the cell SCA is connected to the TSV 52 of the cell SCB via wiring and contacts of the second semiconductor chip 102 .
  • a signal output from cell SCA via TSV 51 is input to cell SCB via TSV 52 via wiring and contacts of second semiconductor chip 102 .
  • the signal TSVs 51 and 52 are arranged at different positions from the power supply TSVs 41 and 42 in the X direction. This is to ensure a sufficient distance between TSVs to facilitate manufacturing and ensure reliability.
  • the TSVs 51 and 52 for signals are arranged at positions overlapping the embedded power supply wiring 11 that supplies VDD in the Y direction. Further, the signal TSVs 51 and 52 are positioned so as to overlap the power supply TSV 41 in the Y direction. As a result, the embedded power supply wiring 11 for supplying VDD is discontinuous at the arrangement positions of the signal TSVs 51 and 52 .
  • the signal TSV may be arranged at a position overlapping with the embedded power supply wiring 12 supplying VSS or at a position overlapping with the power supply TSV 42 in the Y direction. In this case, the embedded power supply wiring 12 for supplying VSS may be discontinuous at the positions where the signal TSVs are arranged.
  • FIG. 4 is a plan view showing a layout example of power supply cells.
  • FIG. 4(a) is a layout of the power supply cell 31 shown in FIG.
  • the power supply cell 31 includes an embedded power supply wiring 11 that supplies VDD, an embedded power supply wiring 12 that supplies VSS, and TSVs 41 and 42 .
  • TSV 41 is connected to embedded power supply wiring 11
  • TSV 42 is connected to embedded power supply wiring 12 .
  • the power supply cell 31 has a dummy gate 61 . Note that the power supply cell 31 may include a dummy transistor.
  • FIG. 4(b) is a power supply cell for VDD
  • FIG. 4(c) is a power supply cell for VSS
  • the power supply cell shown in FIG. 4B has only the TSV 41 for VDD, that is, connected to the embedded power supply wiring 11
  • the power supply cell shown in FIG. 4C has only TSV 42 for VSS, that is, connected to embedded power supply wiring 12 . If the power cell shown in FIG. 4B and the power cell shown in FIG. 4C are arranged adjacent to each other in the X direction, the same layout as that of the power cell shown in FIG. 4A is obtained. However, the power supply cells shown in FIG. 4B and the power supply cells shown in FIG. 4C do not need to be arranged adjacent to each other, and may be arranged apart from each other. Also, the power supply cells shown in FIG. 4A and the power supply cells shown in FIGS. 4B and 4C may be mixed in the block layout.
  • the TSV may be appropriately provided for the embedded power supply wiring in the arranged normal standard cells. Since this eliminates the need to provide a dedicated power supply cell, the area of the semiconductor integrated circuit device can be reduced.
  • the TSVs may be arranged such that the TSVs for VDD are arranged in the Y direction and the TSVs for VSS are arranged in the Y direction. It should be noted that power supply cells and normal cells provided with power supply TSVs may coexist.
  • FIG. 5 is an example of a layout in which TSVs are provided for embedded power supply wiring in a normal standard cell.
  • the cells in FIG. 5 constitute the inverter shown in FIG.
  • a TSV 43 is provided for the embedded power supply wiring 11 that provides VDD.
  • the position of the TSV 43 is not limited to that shown in FIG. 5.
  • the TSV 43 for VDD is arranged, but the TSV may be arranged for the embedded power supply wiring 12 that provides VSS.
  • both the VDD TSV and the VSS TSV may be arranged in one cell, or either one of them may be arranged.
  • FIG. 7 is a layout example of a cell having signal TSVs.
  • FIG. 7 is a layout of standard cells SCA in the block layout of FIG.
  • the layout of the standard cells SCB is also the same as in FIG. 8 is a cross-sectional view showing the cross-sectional structure along the line Y2-Y2' in FIG.
  • the cell SCA shown in FIG. 7 has a TSV 51 for signals.
  • a power supply line 11 extending in the X direction and supplying VDD is arranged in the center of the cell SCA in the Y direction.
  • the power wiring 11 is discontinuous around the position where the TSV 51 is arranged. That is, the power supply wiring 11 has a first portion 11a and a second portion 11b that are separated from each other, and the TSV 51 is arranged between the first portion 11a and the second portion 11b. This avoids short-circuiting between the TSV 51 and the power supply wiring 11 formed in the embedded wiring layer.
  • Power supply wirings 12 extending in the X direction and supplying VSS are arranged at both ends of the cell SCA in the Y direction.
  • An M1 wiring 151 extending in the X direction is formed in the upper metal wiring layer (M1) where the power supply wiring 11 is discontinuous.
  • the M1 wiring 151 electrically connects the first portion 11a and the second portion 11b of the power wiring 11 .
  • the M1 wiring 151 may not be provided if, for example, a problem such as a power supply voltage drop does not occur.
  • the cell SCA shown in FIG. 7 includes an M1 wiring 111 serving as a signal terminal A, and an embedded wiring 131 and a local wiring 121 formed on the TSV 51 .
  • TSV 51 is connected to M1 wiring 111 via embedded wiring 131 and local wiring 121 .
  • dummy transistors are arranged around the TSV 51 in order to improve the manufacturing accuracy and reliability by making the pattern uniform.
  • the dummy transistor does not have to be arranged.
  • the power wiring 11 that supplies VDD is arranged in the center in the Y direction, but the power wiring 12 that supplies VSS may be arranged in the center in the Y direction.
  • power supply lines 11 for supplying VDD are arranged at both ends of the cell SCA in the Y direction. The same applies to the subsequent layout examples.
  • FIG. 9 is another layout example of a cell having signal TSVs.
  • 10 is a cross-sectional view showing the cross-sectional structure along the line Y3-Y3' in FIG.
  • components common to those in FIGS. 7 and 8 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • the cell shown in FIG. 9 includes a TSV 51A having a larger planar size than the TSV 51 shown in FIG. No embedded wiring is formed on the TSV 51A, and the TSV 51A is directly connected to the local wirings 122, 123 and 124 formed thereon. That is, the TSV 51A is larger than the TSV 51 in size in the Z direction (depth direction).
  • the TSV 51A is connected to the M1 wiring 112 serving as the signal terminal A through local wirings 122, 123, and .
  • the local wiring has a greater distance from the back surface of the first semiconductor chip 101 than the embedded wiring. Therefore, by directly connecting the TSV to the local wiring without forming the buried wiring, there is a possibility that manufacturability is impaired and performance (speed) and reliability are lowered.
  • the TSV 51A is formed so that the planar size is larger than that of the TSV 51 . As a result, it is possible to suppress deterioration in manufacturability, performance, and reliability.
  • FIGS. 11 and 12 are other layout examples of cells having signal TSVs.
  • components common to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof may be omitted here.
  • the cell shown in FIG. 11 has an inverter INV1, which is an example of a logic circuit.
  • the circuit of the inverter INV1 is as shown in FIG.
  • the M1 wiring 113 is connected to the output of the inverter INV1.
  • TSV 51 is connected to M1 wiring 113 via embedded wiring 131 and local wiring 121 . With this configuration, the output signal of the inverter INV1 can be output to the second semiconductor chip 102 via the TSV51.
  • the cell shown in FIG. 12 has an inverter INV2, which is an example of a logic circuit.
  • the M1 wiring 114 is connected to the input of the inverter INV2.
  • TSV 51 is connected to M1 wiring 114 via embedded wiring 131 and local wiring 121 . With this configuration, the input signal of the inverter INV2 can be input from the second semiconductor chip 102 via the TSV51.
  • logic circuits provided in the cells are not limited to inverters. Also, the layout examples shown in FIGS. 11 and 12 may be combined with the layout example shown in FIG.
  • the first semiconductor chip 101 and the second semiconductor chip 102 are stacked, and the back surface of the first semiconductor chip 101 and the main surface of the second semiconductor chip 102 face each other.
  • the first semiconductor chip 101 is formed in an embedded wiring layer, extends in the X direction, and includes power supply wirings 11 and 12 adjacent in the Y direction. and contacts 51 and 52 provided between the signal wiring and the back surface of the chip.
  • the contacts 51 and 52 overlap the power supply wiring 11 in the Y direction and are located at different positions from the contacts 41 and 42 in the X direction.
  • the contacts 51 and 52 overlap the power supply wiring 11 in the Y direction and are located at different positions from the contacts 41 and 42 in the X direction in plan view.
  • the power supply wiring 11 has first and second portions 11a and 11b separated from each other in the X direction, and the contacts 51 and 52 are separated from each other by the first portion 11a and the second portion 11b in the X direction in plan view. It is positioned in between and overlaps with the power supply wiring 11 in the Y direction. As a result, short-circuiting between the contacts 51 and 52 and the power wiring 11 can be avoided even if the planar size of the contacts 51 and 52 is increased, so that manufacturing can be facilitated and reliability can be ensured.

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Wire Bonding (AREA)
PCT/JP2022/044249 2021-12-27 2022-11-30 半導体集積回路装置 Ceased WO2023127385A1 (ja)

Priority Applications (3)

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CN202280080227.4A CN118355485A (zh) 2021-12-27 2022-11-30 半导体集成电路装置
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032839A (ja) * 2003-07-08 2005-02-03 Toshiba Microelectronics Corp 半導体集積回路及びマスターチップ
JP2018182213A (ja) * 2017-04-19 2018-11-15 富士通株式会社 半導体装置及び半導体装置の製造方法
WO2020066797A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体集積回路装置および半導体パッケージ構造
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置
WO2021070367A1 (ja) * 2019-10-11 2021-04-15 株式会社ソシオネクスト 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032839A (ja) * 2003-07-08 2005-02-03 Toshiba Microelectronics Corp 半導体集積回路及びマスターチップ
JP2018182213A (ja) * 2017-04-19 2018-11-15 富士通株式会社 半導体装置及び半導体装置の製造方法
WO2020066797A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体集積回路装置および半導体パッケージ構造
WO2020065916A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体装置
WO2021070367A1 (ja) * 2019-10-11 2021-04-15 株式会社ソシオネクスト 半導体装置

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