WO2023127091A1 - Dispositif à semi-conducteur et antenne - Google Patents

Dispositif à semi-conducteur et antenne Download PDF

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Publication number
WO2023127091A1
WO2023127091A1 PCT/JP2021/048775 JP2021048775W WO2023127091A1 WO 2023127091 A1 WO2023127091 A1 WO 2023127091A1 JP 2021048775 W JP2021048775 W JP 2021048775W WO 2023127091 A1 WO2023127091 A1 WO 2023127091A1
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WIPO (PCT)
Prior art keywords
resin substrate
multilayer resin
semiconductor device
conductive film
ground pattern
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PCT/JP2021/048775
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English (en)
Japanese (ja)
Inventor
俊一 阿部
勝巳 宮脇
哲成 齋藤
健寿 前田
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2022537860A priority Critical patent/JPWO2023127091A1/ja
Priority to PCT/JP2021/048775 priority patent/WO2023127091A1/fr
Publication of WO2023127091A1 publication Critical patent/WO2023127091A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon

Definitions

  • the present invention relates to a semiconductor device and an antenna.
  • Patent Document 1 discloses a semiconductor device equipped with a conductive film having a shielding function.
  • This semiconductor device includes an IC, an electronic component, a heat spreader in contact with the IC, and the like, and a molding resin that covers and physically protects these is provided in the center of the upper surface of the multilayer resin substrate.
  • the semiconductor device includes ground patterns on the upper and lower surfaces of the outer peripheral portion of the multilayer resin substrate, and a plurality of ground via holes for electrically conducting these ground patterns. Electromagnetic waves radiated from the IC are confined inside the semiconductor device by electrically connecting the conductive film to a ground pattern provided on the upper surface of the multilayer resin substrate.
  • the ground pattern provided on the top surface of the multilayer resin substrate is electrically connected to the conductive film, it must be exposed from the mold resin.
  • the ground pattern is placed on the outer periphery of the mold resin that protects the IC, etc., using a space corresponding to the ground pattern. I had to. Even if the ground pattern and ground via holes provided on the lower surface of the multilayer resin substrate were provided within the range of the mold resin, the size of the semiconductor device could not be reduced to the size of the mold resin.
  • the area of the multilayer resin substrate required for one device has increased, and the number of semiconductor devices that can be placed on one panel has decreased, resulting in lower productivity and higher costs.
  • An object of the present invention is to provide a semiconductor device and an antenna capable of
  • An aspect of the present disclosure includes a first multilayer resin substrate, a ground pattern disposed between layers of the first multilayer resin substrate, an element mounted on the upper surface of the first multilayer resin substrate, and a first multilayer A resin substrate and a conductive film placed so as to surround the element are provided, and the ground pattern has an exposed portion exposed on an end face on the side surface side of the first multilayer resin substrate, and the conductive film and the conductive film are formed at the exposed portion.
  • An electrical connection is preferred.
  • the aspect of the present disclosure there is no need to install a ground pattern on the upper surface of the multilayer resin substrate, so the number of semiconductor devices that can be arranged on one panel can be increased. Accordingly, it is possible to provide a semiconductor device and an antenna capable of improving productivity and reducing costs.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present disclosure
  • FIG. 1 is a cross-sectional view of an antenna provided with a semiconductor device according to Embodiment 1 of the present disclosure
  • FIG. 1 is a block diagram showing functions of a semiconductor device according to a first embodiment of the present disclosure
  • FIG. 2 is a flow chart showing the overall manufacturing flow of a conventional example; It is a figure which shows the process from a solder printing process to a die-bonding curing process of the manufacturing flow of a conventional example. It is a figure which shows the semiconductor device clamped by the mold sealing process of the manufacturing flow of a conventional example.
  • FIG. 4 is a flow chart showing the overall manufacturing flow according to Embodiment 1 of the present disclosure;
  • FIG. 4 is a diagram showing processes from a solder printing process to a die bonding/curing process in the manufacturing flow according to the first embodiment of the present disclosure;
  • FIG. 4 is a diagram showing processes from a solder printing process to a die bonding/curing process in the manufacturing flow according to the first embodiment of the present disclosure;
  • FIG. 4 is a diagram showing the semiconductor device mold-clamped in the mold sealing step of the manufacturing flow according to the first embodiment of the present disclosure; It is a figure which shows the semiconductor device of the mold sealing process of the manufacturing flow which concerns on Embodiment 1 of this indication. It is a figure which shows the semiconductor device of the grinding process of the manufacturing flow which concerns on Embodiment 1 of this indication.
  • FIG. 4 is a diagram showing the individualization process of the manufacturing flow according to Embodiment 1 of the present disclosure;
  • FIG. 4 is a diagram showing a shielding step in the manufacturing flow according to Embodiment 1 of the present disclosure; It is a figure which shows the distance between the semiconductor devices of a prior art example.
  • FIG. 10 is a diagram showing the position of the ground pattern exposed portion on the side surface of the semiconductor device according to the second embodiment of the present disclosure;
  • FIG. 10 is a diagram showing the position of the ground pattern exposed portion on the side surface of the semiconductor device according to the third embodiment of the present disclosure;
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present disclosure.
  • a semiconductor device 100 includes a multilayer resin substrate 1 .
  • a multilayer resin substrate 1 is a first multilayer resin substrate for a device.
  • a plurality of ground via holes 11, signal via holes 12 and 13, and a ground pattern 14 are formed near the periphery of the multilayer resin substrate 1.
  • FIG. The multilayer resin substrate 1 has four resin layers, three inner layers, and outer layers on the upper and lower surfaces of the multilayer resin substrate 1 .
  • the inner layer is an internal conductor pattern layer of the multilayer resin substrate 1
  • the outer layer is a surface conductor pattern layer of the multilayer resin substrate 1 .
  • the ground pattern 14 is formed in the inner layer of the multilayer resin substrate 1 .
  • one end surface of the multilayer resin substrate 1 in the Y-axis direction specifically the lower surface in FIG.
  • a second plate surface 1b is used.
  • a peripheral end surface of the multilayer resin substrate 1, that is, a side surface in FIG. 1 is referred to as a third plate surface 1c.
  • the horizontal direction in FIG. 1 is the X-axis direction, the vertical direction in FIG. .
  • a ground external terminal 19 electrically connected to one end of the ground via hole 11 in the Y-axis direction, and a signal input terminal electrically connected to one end of the signal via hole 12 in the Y-axis direction.
  • An output terminal 20 and a signal input/output terminal 21 electrically connected to one end of the signal via hole 13 in the Y-axis direction are provided.
  • the ground external terminal 19 is a ground terminal when the semiconductor device 100 is secondarily mounted.
  • a signal line 15 is provided on the second plate surface 1b.
  • Examples of types of the signal line 15 include an input RF line, a gate bias supply line, an output RF line, and a drain bias supply line.
  • Signal line 15 is connected to chip component 8 .
  • a chip component 8 is a bypass capacitor that is surface-mounted on the multilayer resin substrate 1 and suppresses RF superimposed waves.
  • a pad 16 electrically connected to the other end of the signal via hole 12 in the Y-axis direction is provided on the second plate surface 1b.
  • the pad 16 is connected to the input/output terminal 41 through the fine bonding material 30-1.
  • the input/output terminal 41 is connected to one end surface 4a of the IC4.
  • the IC4 is a highly exothermic RF device and a driver amplifier (DA).
  • DA driver amplifier
  • IC4 is a semiconductor element whose main material is GaN (gallium nitride) epitaxially grown on a SiC (Silicon Carbide) substrate.
  • Integrated Circuit: MMIC Integrated Circuit
  • An input/output terminal 42 is further provided on one end surface 4a of the IC 4, and is connected to the pad 18-1 provided on the second plate surface 1b via a fine bonding material 30-2.
  • Conductive copper pillars or solder balls can be exemplified as the fine bonding materials 30-1 and 30-2.
  • a heat spreader 5 is provided on the other end surface 4b side of the IC 4 in the Y-axis direction. Examples of materials for the heat spreader 5 include metals such as copper, copper alloys, and aluminum, which have high thermal conductivity and are easy to process, or carbon composite materials.
  • the IC 4 is thermally and electrically connected to one end surface 5a of the heat spreader 5 in the Y-axis direction.
  • a pad 17 electrically connected to the other end of the signal via hole 13 in the Y-axis direction is provided on the second plate surface 1b side.
  • the pad 17 is connected to the input/output terminal 62 via the fine bonding material 30-4.
  • the input/output terminal 62 is connected to the IC 6 on the one end surface 6a side of the IC 6 in the Y-axis direction.
  • the IC 6 is a highly exothermic RF device and a high power amplifier (HPA).
  • HPA high power amplifier
  • IC 6 is a semiconductor element whose main material is GaN epitaxially grown on a SiC substrate, and is a monolithic microwave integrated circuit which is a circuit for amplifying high-frequency signals in the microwave band.
  • An input/output terminal 61 is further provided on the one end surface 6a side of the IC 6, and is connected to the pad 18-2 provided on the second plate surface 1b via the fine bonding material 30-3.
  • Conductive copper pillars or solder balls can be exemplified as the fine bonding materials 30-3 and 30-4.
  • a heat spreader 7 is provided on the other end face 6b side of the IC 6 in the Y-axis direction. Examples of the material of the heat spreader 7 include metals such as copper, copper alloys, and aluminum, which have high thermal conductivity and are easy to process, or carbon composite materials.
  • the IC 6 is thermally and electrically connected to one end surface 7a of the heat spreader 7 in the Y-axis direction.
  • the IC 6 is mounted face down on the multilayer resin substrate 1 .
  • a metal film that serves as a ground for the IC 6 is formed on the entire back surface, and the metal film includes via holes (ViaHole) penetrating the IC 6, terminals provided on the front side, fine bonding material, the outer layer pattern described above, and the like. is electrically connected to the ground external terminal 19 via the .
  • ViaHole via holes
  • the ground pattern 14 is exposed on the third plate surface 1c side.
  • a plurality of ground via holes 11 surround the signal line 15, the pads 16, 17 and 18, the signal pads such as the signal input/output terminals 20 and 21, and the signal via holes 12 and 13 near the periphery of the multilayer resin substrate 1. is formed as Also, the plurality of ground via holes 11 are electrically connected to the ground pattern 14 inside the multilayer resin substrate 1 .
  • the ground pattern 14 is electrically connected to the outer layer pattern on the second plate surface 1b side.
  • a molding resin 50 is molded on the multilayer resin substrate 1 to which the ICs 4 and 6 are bonded. Mold resin 50 is molded so as to include ICs 4 and 6, heat spreaders 5 and 7, chip component 8, signal line 15, and pads 16, 17 and 18 inside.
  • the outer peripheral surface of the IC 4 is covered with the mold resin 50 except for the other end surface 4b of the IC 4 in the Y-axis direction.
  • the outer peripheral surface of the IC 6 is covered with a mold resin 50 except for the other end surface 6b of the IC 6 in the Y-axis direction.
  • the outer peripheral surface of the heat spreader 5 is covered with a mold resin 50 except for one end surface 5a of the heat spreader 5 in the Y-axis direction and the other end surface 5b of the heat spreader 5 in the Y-axis direction.
  • the outer peripheral surface of the heat spreader 7 is covered with a mold resin 50 except for one end surface 7a of the heat spreader 7 in the Y-axis direction and the other end surface 7b of the heat spreader 7 in the Y-axis direction.
  • a conductive film 2 is formed on the surfaces of the mold resin 50 and the heat spreaders 5 and 7 .
  • the conductive film 2 is a film having conductivity such as electroless plating or a conductive adhesive.
  • Examples of the material of the plated film include Ni or Ag.
  • Examples of the conductive adhesive include an epoxy material containing silver particles. I can give an example.
  • electroless plating is used as the conductive film 2
  • a conductive adhesive or a thin film conductive metal sheet is brought into contact with the upper surface of the border region where the upper end surface of the mold resin 50 and the upper end surfaces of the heat spreaders 5 and 7 are adjacent to each other. , the electrical connection and the electromagnetic shielding function of the boundary region between the upper end surface of the mold resin 50 and the upper end surfaces of the heat spreaders 5 and 7 may be enhanced.
  • the inner side surface 2 a of the conductive film 2 is thermally and electrically connected to the other end surface 5 b of the heat spreader 5 and is thermally and electrically connected to the other end surface 7 b of the heat spreader 7 .
  • Conductive film 2 is electrically connected to ground pattern 14 exposed from multilayer resin substrate 1 on third plate surface 1 c of multilayer resin substrate 1 .
  • a method of molding a resin material around the ICs 4 and 6 and the heat spreaders 5 and 7 may be used so that the end surface of the conductive film 2 on the inner side surface 2a side does not have a step.
  • the end surface of the mold resin 50 on the inner side surface 2a side of the conductive film 2 and the upper end surface of the heat spreaders 5 and 7 are made substantially flush with each other. or the end surface of the mold resin 50 on the side of the inner surface 2a of the conductive film 2 and the upper end surface of the heat spreaders 5 and 7 are ground so that the other end surfaces 5b and 7b of the heat spreaders 5 and 7 are flat. may be exposed.
  • An example of signal transmission in the semiconductor device 100 configured in this way is as follows. First, an RF signal is input to the signal input/output terminal 20 .
  • An RF signal which is a transmission signal input to the signal input/output terminal 20, is input to the IC 4 via the signal via hole 12, the pad 16, the fine bonding material 30-1 and the input/output terminal 41.
  • FIG. The RF signal input to IC4 is amplified by IC4 and then transmitted through input/output terminal 42, fine bonding material 30-2, and pads 18-1 and 18-2.
  • the RF signal input to the IC 6 via the input/output terminal 61 is amplified by the IC 6 and then transmitted via the input/output terminal 62, the fine bonding material 30-4, the pad 17 and the signal via hole 13 to the signal input/output terminal 21. is transmitted to
  • the pad 16, the signal via hole 12 and the signal input/output terminal 20 constitute a signal terminal portion 84 having a coaxial structure.
  • the pad 17, the signal via hole 13 and the signal input/output terminal 21 form a signal terminal portion 85 having a coaxial structure.
  • FIG. 2 is a cross-sectional view of an antenna provided with the semiconductor device according to Embodiment 1 of the present disclosure.
  • Antenna 500 comprises microwave module 200 .
  • the microwave module 200 includes a module multilayer resin substrate 110 that is a second multilayer resin substrate.
  • a plurality of semiconductor devices 100, a control IC 120, and a chip component 130 are provided on one end surface 110a of the multilayer resin substrate 110 in the Y-axis direction.
  • a resistor or a capacitor can be exemplified as the chip component 130 .
  • a plurality of antenna elements 210 are provided on the other end surface 110b of the multilayer resin substrate 110 in the Y-axis direction.
  • the conductive films 2 of the plurality of semiconductor devices 100 included in the microwave module 200 are in contact with the heat dissipation sheet 150 having elasticity.
  • the heat dissipation sheet 150 is a sheet having high elasticity and high thermal conductivity. Examples of the material of the heat dissipation sheet 150 include silicon rubber embedded with a high thermal conductivity material such as carbon and silver. One end surface of the heat dissipation sheet 150 in the Y-axis direction is in contact with the heat dissipation plate 140 .
  • One end surface of the heat sink 140 in the Y-axis direction is in contact with the control board 160 .
  • the control board 160 generates power and control signals to be supplied to the microwave module 200 .
  • Power and control signals are input to semiconductor device 100 on multilayer resin substrate 110 via power/control connector 170 .
  • the multilayer resin substrate 110 and the control substrate 160 are connected to each other via the heat radiation sheet 150 and the heat radiation plate 140 by the power/control connector 170 as the first connector and the RF connector 180 as the second connector.
  • the multilayer resin substrate 110 is fixed to the radiator plate 140 with screws or the like while pressure is applied in the Y-axis direction, the conductive film 2 of the semiconductor device 100 is pressed against the elastic radiator sheet 150 . . Thereby, the conductive film 2 of the semiconductor device 100, the heat dissipation sheet 150, and the heat dissipation plate 140 are thermally connected.
  • a signal terminal portion 115 having a coaxial structure, a signal input/output terminal 121, and RF transmission lines 116 and 117 as inner layer signal lines are provided on the multilayer resin substrate 110 .
  • the RF connector 180 and the semiconductor device 100 are connected to each other via the RF transmission line 116 and the signal terminal portion 115 .
  • Antenna element 210 and semiconductor device 100 are connected to each other via RF transmission line 117 and signal input/output terminal 121 .
  • An RF transmission signal and an RF reception signal which are RF signals of the microwave module 200 , are transmitted from the antenna element 210 to the transmitter/receiver 600 and the divider/combiner circuit 700 via the RF connector 180 . Note that the connection order of the transmitter/receiver 600 and the divider/combiner circuit 700 may be reversed.
  • An RF transmission signal output from the transceiver 600 is transmitted to the signal input/output terminal 20 shown in FIG.
  • An RF transmission signal output from signal input/output terminal 21 shown in FIG. 1 is transmitted to antenna element 210 via RF transmission line 117 and output from antenna element 210 .
  • An RF reception signal received by antenna element 210 is transmitted to signal input/output terminal 21 shown in FIG. and transmitted to the transceiver 600 .
  • FIG. 3 is a block diagram showing functions of the semiconductor device according to the first embodiment of the present disclosure.
  • a microwave module 200 includes a plurality of semiconductor devices 100 .
  • the semiconductor device 100 includes a low noise amplifier (LNA), a circulator (CIR), and a phase shifter (PS) in addition to the DA and HPA described above.
  • LNA low noise amplifier
  • CIR circulator
  • PS phase shifter
  • the RF transmission signal output from transceiver 600 is transmitted to antenna element 210 via PS, DA, HPA and CIR.
  • An RF receive signal received at antenna element 210 is transmitted to transceiver 600 via CIR, LNA and PS.
  • a switch (SW) may be used instead of the CIR as the transmission/reception switching circuit on the antenna side.
  • FIG. 4 is a flow chart showing the overall manufacturing flow of the conventional example.
  • a solder printing step 804 is performed by printing a solder paste 802 on a multilayer resin substrate 800 .
  • a mounting step 810 is performed to mount the mounted component 806 and the semiconductor element 808 on the multilayer resin substrate 800 .
  • the solder is melted to fix the mounting component 806 and the semiconductor element 808 on the multilayer resin substrate 800, and a reflow cleaning step 812 is performed to remove the residue of the solder paste.
  • a heat spreader 814 is mounted on the semiconductor element 808 which has already been mounted on the multilayer resin substrate 800, and a die bonding/curing process 818 is performed in which the heat spreader 814 is fixed using an adhesive 816.
  • FIG. A wire bonding step 822 is then performed using a gold wire 820 .
  • a mold sealing step 826 is performed to seal the multilayer resin substrate 800 using a mold resin 824 .
  • a grinding step 828 is performed to grind the mold surface and expose the mounted heat spreader 814 .
  • a shielding step 832 is performed to form a conductive film 830 on the front surface of the multilayer resin substrate 800 and impart an electromagnetic shielding effect.
  • the multi-layered resin substrate 800 is cut, and a singulation step 834 is performed to individually divide a plurality of semiconductor devices arranged on the panel.
  • FIG. 5 is a diagram showing processes from a solder printing process to a die bonding/curing process in a conventional manufacturing flow.
  • Horizontally arranged views are a plan view of a plurality of semiconductor devices arranged on the panel from the left, a plan view enlarging one of the semiconductor devices, and a cross-sectional view enlarging one of the semiconductor devices.
  • These three figures show one step. These show three processes, solder printing process 804, mounting process 810, and die bond curing process 818, in order from the top.
  • solder paste is printed on a predetermined location on the multilayer resin substrate 800.
  • a copper pillar or land placed on the multilayer resin substrate 800 can be exemplified.
  • the ground pattern 302 is arranged at a position exposed from the mold resin around the range where each semiconductor device is molded.
  • the ground pattern 302 is electrically connected to a ground via hole 304 penetrating to the back surface of the semiconductor device.
  • a space for providing a molding resin flowing portion that is, a path for molding resin to flow, is secured between the semiconductor devices.
  • a mounting step 810 mounted components 806 and semiconductor elements 808a and 808b are mounted on the multilayer resin substrate 800 on the printed solder paste.
  • the multilayer resin substrate 800 is placed in a reflow furnace and heated to a temperature at which solder melts, and the mounted components 806 and semiconductor elements 808a and 808b are reflow soldered. After that, flux residues and the like in the solder paste remaining on the multilayer resin substrate 800 are washed off.
  • a conductive adhesive or the like is applied on the mounted semiconductor elements 808a and 808b, and a heat spreader 814a is placed on the semiconductor element 808a, and a heat spreader 814b is placed on the semiconductor element 808b.
  • curing is performed to harden the conductive adhesive, and the semiconductor element 808a and the heat spreader 814a and the semiconductor element 808b and the heat spreader 814b are respectively bonded and fixed.
  • FIG. 6 is a diagram showing the mold sealing process of the manufacturing flow of the conventional example, and shows a cross section of a mold and a semiconductor device clamped by the mold, viewed from the side.
  • the mold sealing step 826 after placing the multilayer resin substrate 800 on the molding die 306a, the entire panel is clamped by the molding dies 306a and 306b.
  • the mold 306b has a space 308 having a recess for each semiconductor device when the mold is clamped.
  • This space 308 is a space into which mold resin is injected and molded, and has a shape divided by the convex portion 307 for each semiconductor device.
  • the width of the convex portion 307 is W1.
  • a molding resin 824 is injected from one direction into the clamped molding dies 306a and 306b to form a shape in which the surface of the multilayer resin substrate 800 is sealed with the molding resin. After a certain period of time has passed and the mold resin has hardened, the molded multilayer resin substrate 800 is removed from the mold. At this stage, the heat spreader is covered with mold resin.
  • FIG. 7 is a diagram showing the state of the semiconductor device after the mold sealing step in the manufacturing flow of the conventional example.
  • 3A and 3B are a plan view and a side view of a plurality of semiconductor devices arranged on a panel in order from the top, a plan view and a cross-sectional view enlarging one semiconductor device;
  • FIG. A dashed line connecting each drawing corresponds to the width of one semiconductor device. It can be seen that in the conventional molding process 826, a portion of the ground pattern 302 is exposed even after the mounting component 806 and the heat spreaders 814a and 814b are no longer exposed after sealing with the molding resin 824.
  • FIG. 1 is a diagram showing the state of the semiconductor device after the mold sealing step in the manufacturing flow of the conventional example.
  • FIG. 8 is a diagram showing the processes from the grinding process to the shielding process in the manufacturing flow of the conventional example.
  • Horizontally arranged views are a plan view of a plurality of semiconductor devices arranged on the panel from the left, a plan view enlarging one of the semiconductor devices, and a cross-sectional view enlarging one of the semiconductor devices. These three figures show one step. Furthermore, two processes, a grinding process 828 and a shielding process 832, are shown in order from the top.
  • a grinding step 828 the surface of the mold resin 824 is ground to expose the sealed heat spreaders 814a and 814b.
  • the upper surface of the semiconductor device molded on the multilayer resin substrate 800 is covered with a conductive film 830 .
  • the exposed ground pattern 302 and heat spreaders 814 a and 814 b are electrically connected to the conductive film 830 .
  • FIG. 9 is a diagram showing the individualization process of the conventional manufacturing flow.
  • a plan view and a cross-sectional view of a plurality of semiconductor devices arranged on a panel in order from the top are shown.
  • the individualizing step 834 the multi-layered resin substrate 800 is cut using a disk-shaped grindstone 310 or the like, which is generally called a dicing blade, rotating at high speed, and the semiconductor devices are separated into individual pieces. It can be seen that there is an extra space between the semiconductor devices that does not contribute to the product because the cutting is performed at the positions indicated by the dashed arrows.
  • FIG. 10 is a diagram showing a conventional semiconductor device. A side view, a cross-sectional view, and a bottom view of the semiconductor device are shown in this order from the top.
  • the conductive film 830 covers the mold resin 824 , the heat spreaders 814 a and 814 b , and the mounted component 806 and is connected to the ground pattern 302 and the ground via hole 304 . At this time, the conductive film 830 does not cover the side surface of the semiconductor device due to the order of the manufacturing flow. As shown in the bottom view, the external terminal 312 for grounding and the external terminal 314 for signal are exposed on the rear surface.
  • the ground pattern 302 provided on the multilayer resin substrate 800 and the conductive film 830 on the mold resin 824 are electrically connected, and the ground pattern 302 is exposed from the mold resin 824. Therefore, it is necessary to secure a space between the semiconductor devices on the multilayer resin substrate 800 . Therefore, the number of semiconductor devices that can be arranged on the panel is reduced. Therefore, there is a problem that the productivity per panel is lowered and the cost is increased.
  • FIG. 11 is a flow chart showing the overall manufacturing flow according to Embodiment 1 of the present disclosure.
  • a solder printing step 904 is performed by printing a solder paste 902 on a multilayer resin substrate 900 .
  • a mounting step 910 is performed to mount the mounted component 906 and the semiconductor element 908 on the multilayer resin substrate 900 .
  • the solder is melted to fix the mounting component 906 and the semiconductor element 908 on the multilayer resin substrate 900, and a reflow cleaning step 912 is performed to remove the residue of the solder paste.
  • a die bond curing process 918 is performed in which a heat spreader 914 is mounted on the semiconductor element 908 already mounted on the multilayer resin substrate 900 and fixed with an adhesive 916 .
  • a wire bonding step 922 is then performed using a gold wire 920 .
  • a mold sealing step 926 is performed to seal the multilayer resin substrate 900 using a mold resin 924 .
  • a grinding step 928 is performed to grind the mold surface and expose the mounted heat spreader 914 .
  • the multi-layered resin substrate 900 is cut, and a singulation step 930 is performed to individually separate the plurality of semiconductor devices arranged on the multi-layered resin substrate 900 .
  • a conductive film 932 is formed on the front surface of the multilayer resin substrate 900, and after performing a shielding step 934 for providing an electromagnetic shielding effect, test 936 is performed.
  • FIG. 12 is a diagram showing processes from a solder printing process to a die bonding/curing process in the manufacturing flow according to the first embodiment of the present disclosure.
  • Horizontally arranged views are a plan view of a plurality of semiconductor devices arranged on the panel from the left, a plan view enlarging one of the semiconductor devices, and a cross-sectional view enlarging one of the semiconductor devices.
  • These three figures show one step. These show three processes, solder printing process 904, mounting process 910, and die bond curing process 918, in order from the top.
  • solder printing is performed on the multilayer resin substrate 900.
  • the ground pattern 316 is provided between the layers of the multilayer resin substrate 900 .
  • the ground pattern 316 is electrically connected to a ground via hole 318 penetrating to the back surface of the semiconductor device. Due to this configuration, the ground pattern 316 is not exposed when viewed from the top, unlike the conventional case.
  • a mounting step 910 mounted components 906 and semiconductor elements 908a and 908b are mounted on the multilayer resin substrate 900 on the printed solder paste.
  • the multilayer resin substrate 900 is placed in a reflow furnace and heated to a temperature at which solder melts, and the mounted component 906 and the semiconductor elements 908a and 908b are reflow soldered. After that, flux residues and the like in the solder paste remaining on the multilayer resin substrate 900 are washed off.
  • a conductive adhesive or the like is applied on the mounted semiconductor elements 908a and 908b, and a heat spreader 914a is placed on the semiconductor element 908a, and a heat spreader 914b is placed on the semiconductor element 908b.
  • curing is performed to harden the conductive adhesive, and the semiconductor element 908a and the heat spreader 914a and the semiconductor element 908b and the heat spreader 914b are respectively bonded and fixed.
  • FIG. 13 is a diagram showing the mold sealing step of the manufacturing flow according to the first embodiment of the present disclosure, and shows a cross section of the mold and the semiconductor device clamped by the mold, viewed from the side. .
  • the mold sealing step 926 after placing the multilayer resin substrate 900 on the molding die 320a, the entire panel is clamped by the molding dies 320a and 320b.
  • the molding die 320b has a concave space 322 that covers the entire upper surface of the multilayer organic substrate placed thereon when clamped, except for the outermost peripheral portion.
  • a concave space 322 is a space into which molding resin is injected and molded, and has a shape that is not divided for each semiconductor device.
  • a molding resin 924 is injected from one direction into the clamped molding dies 320a and 320b to form a shape in which the surface of the multilayer resin substrate 900 is sealed with the molding resin. After a certain period of time has passed and the mold resin has hardened, the molded multilayer resin substrate 900 is removed from the mold. At this stage, the heat spreader is covered with mold resin.
  • FIG. 14 is a diagram showing the semiconductor device in the mold sealing step of the manufacturing flow according to Embodiment 1 of the present disclosure.
  • 3A and 3B are a plan view and a side view of a plurality of semiconductor devices arranged on a panel in order from the top, an enlarged plan view and a cross-sectional view of one of the semiconductor devices;
  • FIG. A dashed line connecting each drawing corresponds to the width of one semiconductor device. It can be seen that in the mold sealing step 926 of the first embodiment, the ground pattern 316 is not exposed even after the mounting component 906 and the heat spreaders 914a and 914b are not exposed after sealing with the mold resin 924.
  • FIG. 1 is a diagram showing the semiconductor device in the mold sealing step of the manufacturing flow according to Embodiment 1 of the present disclosure.
  • 3A and 3B are a plan view and a side view of a plurality of semiconductor devices arranged on a panel in order from the top, an enlarged plan view and a cross-sectional view of one of
  • FIG. 15 is a diagram showing the semiconductor device in the grinding process of the manufacturing flow according to Embodiment 1 of the present disclosure.
  • 1A and 1B are a plan view of a plurality of semiconductor devices arranged on a panel in order from the top, a plan view enlarging one of the semiconductor devices, and a cross-sectional view; FIG. A dashed line connecting each drawing corresponds to the width of one semiconductor device.
  • the surface of the mold resin 924 is ground to expose the surfaces of the sealed heat spreaders 914a and 914b.
  • FIG. 16 is a diagram showing the individualization process of the manufacturing flow according to Embodiment 1 of the present disclosure.
  • a plan view and a cross-sectional view of a plurality of semiconductor devices arranged on a panel in order from the top are shown.
  • the individualization step 930 the multilayer resin substrate 900 is cut by using a blade-shaped grindstone 310 or the like that rotates at high speed, and the semiconductor devices are separated into individual pieces.
  • the ground pattern 316 in the inner layer of the multilayer resin substrate 900 is exposed at the cut surface in each of the individualized semiconductor devices. It can be seen that there is no wasted space between the semiconductor devices, unlike the conventional example, because it is sufficient to cut at the positions indicated by the dashed arrows.
  • FIG. 17 is a diagram showing the shielding process of the manufacturing flow according to Embodiment 1 of the present disclosure.
  • a cross-sectional view and a bottom view of the semiconductor device are shown in this order from the top.
  • a shielding step 934 the upper surface and side surfaces of each of the separated semiconductor devices are covered with a conductive film 932 .
  • the conductive film 932, the heat spreaders 914a and 914b exposed from the upper surface of the mold resin, and the ground pattern 316 exposed from the side surface of the multilayer resin substrate 900 are electrically connected.
  • the external terminals 324 are exposed on the rear surface.
  • FIG. 18 is a diagram showing the distance between semiconductor devices in the conventional example.
  • the distance W1 between the semiconductor devices is defined by the width of the ground pattern exposed from the outer periphery of the semiconductor device sealed with the molding resin 824, which is the ground pattern exposed width W2, and the width of the portion where the molding resin is injected into the adjacent semiconductor device.
  • W1 is the width of the convex portion 307, and it cannot be narrowed below a certain level due to limitations in mechanical machining accuracy and structural strength. It is generally difficult to eliminate.
  • Embodiment 1 the electrical connection point between the conductive film 932 and the ground pattern 316 is changed from the surface of the substrate to the end surface of the multilayer resin substrate after singulation. Therefore, it is not necessary to provide a ground pattern and ground via holes on the substrate surface and expose the ground pattern when molding is performed. Therefore, the degree of freedom in design is improved as compared with the conventional example, and it becomes possible to reduce the size and increase the density of the semiconductor device.
  • the size of the semiconductor device 100 is about 10 mm square.
  • the resonance frequency will drop to the X band, ie, close to the 10 GHz band.
  • the mold dimensions are 10 mm ⁇ 10 mm ⁇ 1 mm, the entire periphery of the mold resin is covered with a conductor, and the dielectric constant of the mold material is 3.5, the lowest resonance frequency is 11.33 GHz. be.
  • the resonance frequency can be set sufficiently higher than the operating frequency, and RF signal coupling inside the semiconductor device 100 can be achieved. Oscillation caused by
  • the external terminal 312 for grounding and the ground via hole 304 are provided on the back surface provided on the lower surface of the multilayer resin substrate within the range of the mold resin 824, they are provided on the upper surface of the multilayer resin substrate.
  • the external size of the semiconductor device cannot be reduced to the external size of the mold resin 824 .
  • the electrical connection point between the conductive film 932 and the ground pattern 316 is changed from the surface of the substrate to the end surface of the multilayer resin substrate after singulation. It can be reduced to the external size.
  • the electrical resonance frequency can be increased. Since the resonance frequency is higher in the first place, it becomes less necessary to consider the arrangement for raising the resonance frequency in the arrangement of the heat spreader in the mold resin. Therefore, the heat spreader and the semiconductor, which is the heat source in the module, can be arranged more freely.
  • Embodiment 1 by bonding the back surfaces of the ICs 4 and 6 to the heat sink with a conductive adhesive, the ICs 4 and 6 can be grounded not only from the front surface side but also from the back surface side via the conductive film 2. . As a result, the ground potential of the ICs 4 and 6 can be strengthened, which is advantageous in improving high frequency characteristics and preventing unnecessary oscillation.
  • FIG. 20 is a diagram showing the position of the ground pattern exposed portion on the side surface of the semiconductor device according to Embodiment 1 of the present disclosure. Although the ground pattern is actually covered with the conductive film 932 , this figure shows the position of the exposed portion of the ground pattern 316 when the semiconductor device is viewed from the side through the conductive film 932 .
  • the exposed portions of the ground pattern 316 are randomly arranged, and may or may not overlap each other in adjacent upper and lower layers.
  • the ground pattern is made of copper, which has good electrical conductivity.
  • the grindstone 310 is easily clogged due to adhesion of copper forming the ground pattern.
  • problems such as degradation of the quality of the multilayer resin substrate 900 due to deterioration of the grindstone 310 and decrease in productivity due to an increase in the replacement frequency of the grindstone 310 occurred.
  • the second embodiment solves the above problems.
  • FIG. 21 is a diagram showing the position of the ground pattern exposed portion on the side surface of the semiconductor device according to the second embodiment of the present disclosure.
  • the ground pattern is actually covered with the conductive film 932, this figure shows the position of the exposed portion of the ground pattern 316a when the semiconductor device is viewed from the side through the conductive film 932.
  • FIG. The semiconductor device of the second embodiment is manufactured by a manufacturing flow similar to that of the first embodiment.
  • the ground pattern 316a is the same as the first embodiment in that it is provided in the inner layer of the multilayer resin substrate, is exposed from the side surface of the substrate in the individualizing process, and is electrically connected to the conductive film in the shielding process.
  • the ground pattern 316a in the second embodiment is designed so that the portions exposed at the end faces do not overlap each other in the thickness direction of the multilayer resin substrate.
  • this is the vertical direction of the paper surface.
  • the grindstone 310 cuts the multilayer resin substrate while rotating and moving along the surface of the multilayer resin substrate in a direction orthogonal to the thickness direction, that is, in the horizontal direction of the paper surface in FIG.
  • This design has the effect of reducing the amount of copper cut by the grindstone 310 and the effect of preventing clogging of the grindstone 310 due to intermittent cutting during the singulation process. As a result, an improvement in the quality of the cut surface of the multilayer resin substrate and an improvement in productivity due to a reduction in the frequency of replacement of the grindstone can be expected.
  • FIG. 22 is a diagram showing the position of the ground pattern exposed portion on the side surface of the semiconductor device according to the third embodiment of the present disclosure.
  • the semiconductor device of the third embodiment is manufactured by the same manufacturing flow as that of the first embodiment.
  • the ground pattern 316b is provided in the inner layer of the multilayer resin substrate, is exposed from the side surface of the substrate in the individualizing process, and is electrically connected to the conductive film in the shielding process, as in the first embodiment.
  • the ground pattern 316b in Embodiment 3 is designed so that the portions exposed on the end face are arranged so that adjacent upper and lower layers do not overlap each other. As a result, the cutting in the singulation process becomes intermittent, so that the effect of preventing clogging of the blade can be obtained. As a result, an improvement in the quality of the cut surface of the multilayer resin substrate and an improvement in productivity due to a reduction in the frequency of replacement of the grindstone can be expected.
  • Multilayer resin substrate 2 Conductive film 5 Heat spreader 7 Heat spreader 11 Ground via hole 14 Ground pattern 19 Ground external terminal 36 Ground pattern 100
  • Multilayer resin substrate 140 Radiator plate 150 Heat radiation sheet 160 control board, 302 ground pattern, 304 ground via hole, 316 ground pattern, 316a ground pattern, 316b ground pattern, 318 ground via hole, 500 antenna, 600 transceiver, 800 multilayer resin substrate, 814 heat spreader, 814a heat spreader, 814b heat spreader, 830 Conductive film 900 Multilayer resin substrate 914 Heat spreader 914a Heat spreader 914b Heat spreader 932 Conductive film

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Un dispositif à semi-conducteur de la présente invention comprend : un premier substrat de résine multicouche ; un motif de masse disposé entre des couches du premier substrat de résine multicouche ; un élément monté sur une surface supérieure du premier substrat de résine multicouche ; et un film conducteur monté de façon à entourer le premier substrat de résine multicouche et l'élément. Le motif de masse comprend une partie exposée exposée sur une surface d'extrémité sur le côté du premier substrat de résine multicouche, et est électriquement connecté au film conducteur au niveau de la partie exposée.
PCT/JP2021/048775 2021-12-28 2021-12-28 Dispositif à semi-conducteur et antenne WO2023127091A1 (fr)

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PCT/JP2021/048775 WO2023127091A1 (fr) 2021-12-28 2021-12-28 Dispositif à semi-conducteur et antenne

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011040030A1 (fr) * 2009-10-01 2011-04-07 パナソニック株式会社 Module et procédé de production associé
JP2011124366A (ja) * 2009-12-10 2011-06-23 Renesas Electronics Corp 半導体装置およびその製造方法
WO2016204208A1 (fr) * 2015-06-19 2016-12-22 株式会社村田製作所 Module et son procédé de fabrication
WO2017170535A1 (fr) * 2016-03-31 2017-10-05 株式会社村田製作所 Module de circuit
JP2019145536A (ja) * 2018-02-15 2019-08-29 三菱電機株式会社 高周波デバイスおよび空中線
JP6821008B2 (ja) * 2017-03-13 2021-01-27 三菱電機株式会社 マイクロ波デバイス及び空中線

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011040030A1 (fr) * 2009-10-01 2011-04-07 パナソニック株式会社 Module et procédé de production associé
JP2011124366A (ja) * 2009-12-10 2011-06-23 Renesas Electronics Corp 半導体装置およびその製造方法
WO2016204208A1 (fr) * 2015-06-19 2016-12-22 株式会社村田製作所 Module et son procédé de fabrication
WO2017170535A1 (fr) * 2016-03-31 2017-10-05 株式会社村田製作所 Module de circuit
JP6821008B2 (ja) * 2017-03-13 2021-01-27 三菱電機株式会社 マイクロ波デバイス及び空中線
JP2019145536A (ja) * 2018-02-15 2019-08-29 三菱電機株式会社 高周波デバイスおよび空中線

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