WO2023124276A1 - 缓冲电路和延时电路 - Google Patents

缓冲电路和延时电路 Download PDF

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Publication number
WO2023124276A1
WO2023124276A1 PCT/CN2022/119894 CN2022119894W WO2023124276A1 WO 2023124276 A1 WO2023124276 A1 WO 2023124276A1 CN 2022119894 W CN2022119894 W CN 2022119894W WO 2023124276 A1 WO2023124276 A1 WO 2023124276A1
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triode
electrically connected
output terminal
terminal
diode structure
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PCT/CN2022/119894
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English (en)
French (fr)
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许强
王悦
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普源精电科技股份有限公司
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Publication of WO2023124276A1 publication Critical patent/WO2023124276A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only

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  • the embodiments of the present application relate to the field of circuit technology, and in particular, to a buffer circuit and a delay circuit.
  • the buffer circuit can buffer the input signal and then output it, which has the advantages of increasing the driving capability of the circuit and optimizing the waveform, and is widely used in various circuits.
  • the present application provides a buffer circuit and a delay circuit to increase the working frequency of the buffer circuit.
  • an embodiment of the present application provides a buffer circuit, and the buffer circuit includes an input terminal, an output terminal, a power supply terminal, a drive unit, a load unit, and a negative capacitance unit.
  • the input terminal is configured to be connected to an input differential signal
  • the output terminal is configured to be connected to a functional circuit
  • the power supply terminal is configured to be connected to a power supply.
  • the drive unit is configured to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal.
  • the load unit is coupled between the output terminal and the power supply terminal.
  • the negative capacitance unit coupled between the power supply terminal and the output terminal, is configured to reduce the capacitance of the functional circuit.
  • the output terminals include a first output terminal and a second output terminal.
  • the load unit includes a first load and a second load.
  • the negative capacitance unit includes a first transistor, a second transistor, a first diode structure and a second diode structure.
  • the first load, the first triode and the first diode structure are connected in series between the power supply terminal and the first output terminal.
  • the second load, the second triode and the second diode structure are connected in series between the power supply terminal and the second output terminal.
  • the base of the first triode is electrically connected to the collector of the second triode
  • the base of the second triode is electrically connected to the collector of the first triode
  • the first end of the first load is electrically connected to the power supply terminal, and the second end of the first load is electrically connected to the collector of the first triode;
  • An emitter of a triode is electrically connected to the first pole of the first diode structure, and a second pole of the first diode structure is electrically connected to the first output terminal.
  • the first end of the second load is electrically connected to the power supply terminal, and the second end of the second load is electrically connected to the collector of the second triode.
  • the emitter of the second triode is electrically connected to the first pole of the second diode structure, and the second pole of the second diode structure is electrically connected to the second output terminal.
  • the first pole of the first diode structure is electrically connected to the power supply terminal, and the second pole of the first diode structure is connected to the collector of the first triode Electrical connection; the emitter of the first triode is electrically connected to the first end of the first load, and the second end of the first load is electrically connected to the first output terminal.
  • the first pole of the second diode structure is electrically connected to the power supply terminal, and the second pole of the second diode structure is electrically connected to the collector of the second triode; the first The emitter of the triode is electrically connected to the first end of the second load, and the second end of the second load is electrically connected to the second output terminal.
  • the first diode structure includes a third triode, the base of the third triode is electrically connected to the collector of the third triode as the first The first pole of the diode structure, the emitter of the third triode serves as the second pole of the first diode structure.
  • the second diode structure includes a fourth triode, and the base of the fourth triode is electrically connected to the collector of the fourth triode as the first transistor of the second diode structure.
  • One pole, the emitter of the fourth triode serves as the second pole of the second diode structure.
  • the driving unit includes a fifth triode and a sixth triode.
  • the input terminals include a first input terminal and a second input terminal.
  • the collector of the fifth triode is electrically connected to the first output terminal
  • the emitter of the fifth triode is electrically connected to the emitter of the sixth triode
  • the fifth triode The base of the tube is electrically connected to the first input terminal.
  • the collector of the sixth triode is electrically connected to the second output terminal, and the base of the sixth triode is electrically connected to the second input terminal.
  • the buffer circuit further includes a first current source, the first end of the first current source is electrically connected to the emitter of the fifth triode and the emitter of the sixth triode connection, the second pole of the first current source is grounded.
  • the buffer circuit further includes a first emitter follower and a second emitter follower.
  • the first output terminal is electrically connected to the input end of the first emitter follower, and the output end of the first emitter follower serves as the first follower output end of the buffer circuit.
  • the second output terminal is electrically connected to the input end of the second emitter follower, and the output end of the second emitter follower serves as the second follower output end of the buffer circuit.
  • the first emitter follower includes a seventh transistor and a second current source.
  • the base of the seventh triode is electrically connected to the first output terminal, the collector of the seventh triode is electrically connected to the power supply terminal, and the emitter of the seventh triode is connected to the The first end of the second current source is electrically connected to the first follower output end, and the second end of the second current source is grounded.
  • the second emitter follower includes an eighth triode and a third current source.
  • the base of the eighth triode is electrically connected to the second output terminal, the collector of the eighth triode is electrically connected to the power supply terminal, and the emitter of the eighth triode is connected to the The first end of the third current source is electrically connected to the second follower output end, and the second end of the third current source is grounded.
  • the embodiment of the present application also provides a delay circuit, the delay circuit includes the buffer circuit and the function circuit described in the first aspect, wherein the output terminal of the buffer circuit is configured to connect to the function circuit circuit; the functional circuit is a voltage-controlled delay unit, and the voltage-controlled delay unit is configured to delay an input signal and output it.
  • the buffer circuit used includes an input terminal, an output terminal, a power supply terminal, a drive unit, a load unit, and a negative capacitance unit.
  • the input terminal is configured to receive an input differential signal.
  • the output terminals are configured to connect functional circuits.
  • the power supply terminals are configured to be connected to the power supply.
  • a drive unit configured to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal.
  • the load unit is coupled between the output terminal and the power supply terminal.
  • the negative capacitance unit coupled between the power supply terminal and the output terminal, is configured to reduce the capacitance of the functional circuit.
  • FIG. 1 is a schematic diagram of a circuit structure of a buffer circuit provided in an embodiment of the present application
  • FIG. 2 is a schematic circuit structure diagram of another buffer circuit provided by the embodiment of the present application.
  • FIG. 3 is a schematic diagram of a circuit structure of another buffer circuit provided in an embodiment of the present application.
  • first element, module, unit, component or section discussed below could be termed a second element, module, unit, component or section without departing from the teachings of the present application. And when a second element, module, unit, component or section is discussed, it does not mean that the first element, module, unit, component or section necessarily exists in the present application.
  • FIG. 1 is a schematic circuit structure diagram of a buffer circuit provided by an embodiment of the present application.
  • the buffer circuit may include an input terminal, an output terminal, a power supply terminal VCC, a drive unit 11, a negative capacitance unit 12, and a load unit 13.
  • the input terminals are configured to input differential signals.
  • the output terminals are configured to connect functional circuits.
  • the power supply terminal VCC is configured to be connected to the power supply.
  • the driving unit 11 is configured to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal.
  • the load unit 13 is coupled between the output terminal and the power supply terminal.
  • the negative capacitance unit 12 is coupled between the power supply terminal and the output terminal, and configured to reduce the capacitance of the functional circuit.
  • the input terminals of the buffer circuit include a first input terminal VIN and a second input terminal VIP, and the input terminals are configured to receive input differential signals.
  • the output terminals include a first output terminal VON and a second output terminal VOP, and the output terminals are configured to provide an output differential signal to the functional circuit, so that the functional circuit can work normally.
  • the drive unit 11 can generate an output differential signal according to the input differential signal. For example, when the first input terminal VIN inputs a high level and the second input terminal VIP inputs a low level, the drive unit 11 can control the first output terminal VOP to output a low level.
  • the second output terminal VON outputs a high level; and when the first input terminal VIN inputs a low level and the second input terminal VIP inputs a high level, the drive unit 11 can control the first output terminal VOP to output a high level, and the second output Terminal VON outputs low level.
  • the load unit 13 is configured to generate a voltage drop, so that the corresponding output terminal can output high level and low level. At high frequencies, the functional circuit will have a larger equivalent capacitance relative to the buffer circuit, which affects the speed of signal transmission, so that the operating frequency of the buffer circuit is also lower.
  • the capacitance of the functional circuit can be greatly reduced, thereby increasing the speed of signal transmission, further improving the load carrying capacity, and improving the operation of the buffer circuit frequency.
  • the buffer circuit used includes an input terminal, an output terminal, a power supply terminal, a drive unit, a load unit, and a negative capacitance unit.
  • the input terminal is configured to be connected to an input differential signal
  • the output terminal is configured to be connected to a functional circuit
  • the power supply terminal is configured to be connected to a power supply.
  • a drive unit configured to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal.
  • the load unit is coupled between the output terminal and the power supply terminal.
  • the negative capacitance unit coupled between the power supply terminal and the output terminal, is configured to reduce the capacitance of the functional circuit.
  • the output terminals include a first output terminal VOP and a second output terminal VON.
  • the load unit 13 includes a first load R1 and a second load R2.
  • the negative capacitance unit 12 includes a first transistor Q5, a second transistor Q6, a first diode structure Q3 and a second diode structure Q4.
  • the first load R1, the first triode Q5 and the first diode structure Q3 are connected in series between the power supply terminal VCC and the first output terminal VOP.
  • the second load R2, the second transistor Q6 and the second diode structure Q4 are connected in series between the power supply terminal VCC and the second output terminal VON.
  • the base of the first triode Q5 is electrically connected to the collector of the second triode Q6, and the base of the second triode Q6 is electrically connected to the collector of the first triode Q5.
  • the first transistor Q5 and the second transistor Q6 form a cross pair structure
  • the first diode structure Q3 and the second diode structure Q4 are coupled to form a negative feedback capacitor
  • the negative feedback capacitor and the cross pair The tube structure forms a negative capacitance effect, so that the negative capacitance unit 12 can reduce the capacitance of the functional circuit and increase the working frequency of the snubber circuit.
  • the diode structure is used to couple to form a negative feedback capacitor, and the diode structure can also provide a voltage drop for the output branch where it is located, thereby reducing the power consumption of the snubber circuit.
  • the first end of the first load R1 is electrically connected to the power supply terminal VCC, and the second end of the first load R1 is electrically connected to the collector of the first transistor Q5 .
  • the emitter of the first triode Q5 is electrically connected to the first pole of the first diode structure Q3, and the second pole of the first diode structure Q3 is electrically connected to the first output terminal VOP.
  • a first end of the second load R2 is electrically connected to the power supply terminal VCC, and a second end of the second load R2 is electrically connected to the collector of the second transistor Q6.
  • the emitter of the second transistor Q6 is electrically connected to the first pole of the second diode structure Q4, and the second pole of the second diode structure Q4 is electrically connected to the second output terminal VON.
  • the first load R1, the first triode Q5 and the first diode structure Q3 are sequentially connected in series between the power supply terminal VCC and the first output terminal VOP
  • the second load R2 , the second triode Q6 and the second diode structure Q4 are sequentially connected in series between the power supply terminal VCC and the second output terminal VON.
  • Both the resistance values of the first load R1 and the second load R2 may be 50 ohms.
  • Both the first triode Q5 and the second triode Q6 can be NPN transistors, and both types can be the same.
  • FIG. 2 is a schematic circuit structure diagram of another buffer circuit provided in the embodiment of the present application.
  • the first pole of the first diode structure Q3 is connected to the power supply
  • the power supply terminal VCC is electrically connected
  • the second pole of the first diode structure Q3 is electrically connected to the collector of the first triode Q5.
  • the emitter of the first transistor Q5 is electrically connected to the first end of the first load R1, and the second end of the first load R1 is electrically connected to the first output terminal VOP.
  • the first pole of the second diode structure Q4 is electrically connected to the power supply terminal VCC, and the second pole of the second diode structure Q4 is electrically connected to the collector of the second transistor Q6.
  • the emitter of the second transistor Q6 is electrically connected to the first end of the second load R2, and the second end of the second load R2 is electrically connected to the second output terminal VON.
  • the first diode structure Q3, the first triode Q5 and the first load R1 are sequentially connected in series between the power supply terminal VCC and the first output terminal VOP, and the second diode structure Q4, The second transistor Q6 and the second load R2 are sequentially connected in series between the power supply terminal VCC and the second output terminal VON.
  • connection methods are also possible, as long as the negative capacitance unit can be used to reduce the capacitance of the functional circuit, and the first diode structure and the second diode structure are used to form the negative feedback capacitance and reduce the power consumption.
  • the first diode structure Q3 includes a third triode, and the base of the third triode is electrically connected to the collector of the third triode as a first transistor.
  • the first pole of a diode structure Q3, the emitter of the third triode serves as the second pole of the first diode structure Q3.
  • the second diode structure Q4 includes a fourth triode, the base of the fourth triode is electrically connected to the collector of the fourth triode as the first pole of the second diode structure Q4, the fourth three
  • the emitter of the pole tube is used as the second pole of the second diode structure Q4. Utilize the third triode and the fourth triode to form the first diode structure and the second diode structure respectively.
  • the temperature coefficient is close, and it can also play the role of temperature compensation.
  • the driving unit 11 includes a fifth transistor Q1 and a sixth transistor Q2 .
  • the input terminals include a first input terminal VIN and a second input terminal VIP.
  • the collector of the fifth transistor Q1 is electrically connected to the first output terminal VOP, the emitter of the fifth transistor Q1 is electrically connected to the emitter of the sixth transistor Q2, and the base of the fifth transistor Q1 is electrically connected to the
  • the first input terminal VIN is electrically connected, the collector of the sixth transistor Q2 is electrically connected to the second output terminal VON, and the base of the sixth transistor is electrically connected to the second input terminal VIP.
  • both the fifth transistor Q1 and the sixth transistor Q2 are driven by current.
  • the fifth transistor Q1 is turned on
  • the sixth triode Q2 is turned off, and a current flows through the first load R1, so that a voltage drop occurs on the first load R1, that is, the voltage output by the first output terminal VOP is lower than the voltage at the power supply terminal VCC, and Since the sixth triode Q2 is turned off, there is no current on the second load R2, and the voltage output by the second output terminal VON is equal to the voltage at the power supply terminal VCC, that is, the first output terminal VOP outputs a low level, and the second output terminal V Terminal VON outputs high level.
  • the fifth triode Q1 When the first input terminal VIN is at a low level and the second input terminal VIP is at a high level, the fifth triode Q1 is turned off, the sixth triode Q2 is turned on, and a current flows through the second load R2, so that the second A voltage drop occurs on the load R2, that is, the voltage output by the second output terminal VON is lower than the voltage at the power supply terminal VCC, and because the fifth transistor Q1 is turned off, there is no current on the first load R1, and the first output terminal VOP
  • the output voltage is equal to the voltage at the power supply terminal VCC, that is, the first output terminal VOP outputs a high level, and the second output terminal VON outputs a low level.
  • the buffer circuit further includes a first current source I1, a first terminal of the first current source I1 and an emitter of the fifth transistor Q1 and the sixth transistor Q2.
  • the emitter of the first current source I1 is electrically connected, and the second electrode of the first current source I1 is grounded.
  • the first current source I1 is configured to provide bias for the fifth transistor Q1 and the sixth transistor Q2, which can provide a stable static operating point.
  • the magnitude of the current of the first current source I1 affects the swing of the output voltage of the output terminal, and the magnitude of the swing will affect the transmission rate, distance and power consumption of the circuit.
  • the output current of the first current source I1 can be 16 mA.
  • FIG. 3 is a schematic circuit structure diagram of another buffer circuit provided in the embodiment of the present application, and the buffer circuit further includes a first emitter follower 14 and a second emitter follower 15 .
  • the first output terminal VOP is electrically connected to the input terminal of the first emitter follower 14 , and the output terminal of the first emitter follower 14 serves as the first following output terminal VOP1 of the buffer circuit.
  • the second output terminal VON is electrically connected to the input terminal of the second emitter follower 15, and the output terminal of the second emitter follower 15 serves as the second follower output terminal VON2 of the buffer circuit.
  • the output differential signal can be set to be output by the follower output end of the buffer circuit after passing through the first emitter follower 14 and the second emitter follower 15 respectively.
  • the functional circuit can be connected to the follower output terminal of the buffer circuit.
  • the first emitter follower 14 includes a seventh transistor Q7 and a second current source I2 .
  • the base of the seventh transistor Q7 is electrically connected to the first output terminal
  • the collector of the seventh transistor Q7 is electrically connected to the power supply terminal VCC
  • the emitter of the seventh transistor Q7 is electrically connected to the first output terminal of the second current source I2.
  • terminal and the first follower output terminal VOP1 are electrically connected, and the second terminal of the second current source I2 is grounded.
  • the second emitter follower 15 includes an eighth transistor Q8 and a third current source I3.
  • the base of the eighth triode Q8 is electrically connected to the second output terminal VON, the collector of the eighth triode Q8 is electrically connected to the power supply terminal VCC, and the emitter of the eighth triode Q8 is connected to the third current source I3
  • the first terminal of the current source I3 is electrically connected to the second following output terminal VON1, and the second terminal of the third current source I3 is grounded.
  • the function of the emitter follower can be realized by using the triode and the current source, the circuit structure is simple, easy to implement, and the cost of the snubber circuit can be greatly reduced.
  • the buffer circuit of this embodiment can be applied in a clock chain to improve the driving capability of the clock chain, and can also perform waveform shaping.
  • the embodiment of the present application also provides a delay circuit, the delay circuit includes the buffer circuit and the functional circuit provided in any embodiment of the present application, wherein the output terminal of the buffer circuit is configured to connect to the functional circuit, and the functional circuit includes a voltage-controlled delay
  • the voltage-controlled delay unit is configured to delay the input signal and then output it. Because it includes the delay circuit provided by any embodiment of the present application, it also has the same beneficial effect, so it will not be repeated here.

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Abstract

本申请披露了一种缓冲电路和延时电路。所述缓冲电路包括：输入端子，配置为接入输入差分信号；输出端子，配置为连接功能电路；供电电源端子，配置为接入供电电源；驱动单元，配置为响应所述输入端子处的输入差分信号并生成输出差分信号至所述输出端子；负载单元，耦合于所述输出端子与供电电源端子之间；负电容单元，耦合于所述供电电源端子与所述输出端子之间，配置为降低所述功能电路的电容。

Description

缓冲电路和延时电路
相关申请的交叉引用
本申请要求2021年12月30日申请的，申请号为202111652944.3，名称为“缓冲电路和延时电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请实施例涉及电路技术领域，尤其涉及一种缓冲电路和延时电路。
背景技术
缓冲电路能够将输入信号进行缓冲后输出，具有增大电路驱动能力和优化波形等优点，在各种电路中有着广泛的应用。
然而，现有的缓冲电路速度存在限制，工作频率较低，在更高频的场合应用效果不佳。
发明内容
本申请提供一种缓冲电路和延时电路，以提高缓冲电路的工作频率。
第一方面，本申请实施例提供了一种缓冲电路，所述缓冲电路包括输入端子、输出端子、供电电源端子、驱动单元、负载单元以及负电容单元。所述输入端子配置为接入输入差分信号，所述输出端子配置为连接功能电路，所述供电电源端子配置为接入供电电源。所述驱动单元，配置为响应所述输入端子处的输入差分信号并生成输出差分信号至所述输出端子。所述负载单元，耦合于所述输出端子与供电电源端子之间。所述负电容单元，耦合于所述供电电源端子与所述输出端子之间，配置为降低所述功能电路的电容。
在一些实施例中，所述输出端子包括第一输出端子和第二输出端子。所述负载单元包括第一负载和第二负载。所述负电容单元包括第一三极管、第二三极管、第一二极管结构和第二二极管结构。
所述第一负载、所述第一三极管和所述第一二极管结构串接于所述供电电源端子与所述第一输出端子之间。所述第二负载、所述第二三极管及所述第二二极管结构串接于所述供电电源端子与所述第二输出端子之间。
其中，所述第一三极管的基极与所述第二三极管的集电极电连接，所述第二三极管的基极与所述第一三极管的集电极电连接。
在一些实施例中，所述第一负载的第一端与所述供电电源端子电连接，所述第 一负载的第二端与所述第一三极管的集电极电连接；所述第一三极管的发射极与所述第一二极管结构的第一极电连接，所述第一二极管结构的第二极与所述第一输出端子电连接。
所述第二负载的第一端与所述供电电源端子电连接，所述第二负载的第二端与所述第二三极管的集电极电连接。所述第二三极管的发射极与所述第二二极管结构的第一极电连接，所述第二二极管结构的第二极与所述第二输出端子电连接。
在一些实施例中，所述第一二极管结构的第一极与所述供电电源端子电连接，所述第一二极管结构的第二极与所述第一三极管的集电极电连接；所述第一三极管的发射极与所述第一负载的第一端电连接，所述第一负载的第二端与所述第一输出端子电连接。
所述第二二极管结构的第一极与所述供电电源端子电连接，所述第二二极管结构的第二极与所述第二三极管的集电极电连接；所述第二三极管的发射极与所述第二负载的第一端电连接，所述第二负载的第二端与所述第二输出端子电连接。
在一些实施例中，所述第一二极管结构包括第三三极管，所述第三三极管的基极与所述第三三极管的集电极电连接后作为所述第一二极管结构的第一极，所述第三三极管的发射极作为所述第一二极管结构的第二极。
所述第二二极管结构包括第四三极管，所述第四三极管的基极与所述第四三极管的集电极电连接后作为所述第二二极管结构的第一极，所述第四三极管的发射极作为所述第二二极管结构的第二极。
在一些实施例中，所述驱动单元包括第五三极管和第六三极管。所述输入端子包括第一输入端子和第二输入端子。
所述第五三极管的集电极与所述第一输出端子电连接，所述第五三极管的发射极与所述第六三极管的发射极电连接，所述第五三极管的基极与所述第一输入端子电连接。
所述第六三极管的集电极与所述第二输出端子电连接，所述第六三极管的基极与所述第二输入端子电连接。
在一些实施例中，所述缓冲电路还包括第一电流源，所述第一电流源的第一端与所述第五三极管的发射极以及所述第六三极管的发射极电连接，所述第一电流源的第二极接地。
在一些实施例中，所述缓冲电路还包括第一射极跟随器和第二射极跟随器。所 述第一输出端子与所述第一射极跟随器的输入端电连接，所述第一射极跟随器的输出端作为所述缓冲电路的第一跟随输出端。所述第二输出端子与所述第二射极跟随器的输入端电连接，所述第二射极跟随器的输出端作为所述缓冲电路的第二跟随输出端。
在一些实施例中，所述第一射极跟随器包括第七三极管和第二电流源。所述第七三体管的基极与所述第一输出端子电连接，所述第七三极管的集电极与所述供电电源端子电连接，所述第七三极管的发射极与所述第二电流源的第一端以及所述第一跟随输出端电连接，所述第二电流源的第二端接地。
所述第二射极跟随器包括第八三极管和第三电流源。所述第八三极管的基极与所述第二输出端子电连接，所述第八三极管的集电极与所述供电电源端子电连接，所述第八三极管的发射极与所述第三电流源的第一端以及所述第二跟随输出端电连接，所述第三电流源的第二端接地。
第二方面，本申请实施例还提供了一种延时电路，所述延时电路包括第一方面所述的缓冲电路和功能电路，其中，所述缓冲电路的输出端子配置为连接所述功能电路；所述功能电路为压控延时单元，所述压控延时单元配置为将输入信号延时后输出。
本申请实施例的技术方案，采用的缓冲电路包括输入端子、输出端子、供电电源端子、驱动单元、负载单元以及负电容单元。输入端子配置为接入输入差分信号。输出端子配置为连接功能电路。供电电源端子配置为接入供电电源。驱动单元，配置为响应输入端子处的输入差分信号并生成输出差分信号至输出端子。负载单元，耦合于输出端子与供电电源端子之间。负电容单元，耦合于供电电源端子与输出端子之间，配置为降低功能电路的电容。通过在缓冲电路的供电电源端子与输出端子之间耦合负电容单元，能够极大地降低功能电路的电容，从而提高信号传输的速度，进而提高缓冲电路的工作频率。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在这些实施例中，相同的编号表示相同的结构，在附图中：
图1为本申请实施例提供的一种缓冲电路的电路结构示意图；
图2为本申请实施例提供的又一种缓冲电路的电路结构示意图；以及
图3为本申请实施例提供的又一种缓冲电路的电路结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也可能意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
应当明白，当器件被称为“连接到”或“耦合到”其它器件时，其可以直接地连接或耦合到其它器件，或者可以存在居间的器件。相反，当器件被称为“直接连接到”或“直接耦合到”其它器件时，则不存在居间的器件。应当明白，尽管可使用术语第一、第二、第三等描述各种器件、模块、单元、元件、部件和/或部分，这些器件、模块、单元、元件、部件和/或部分不应当被这些术语限制。这些术语仅仅用来区分其中的一个与另一个。因此，在不脱离本申请教导之下，下面讨论的第一元件、模块、单元、部件或部分可表示为第二元件、模块、单元、部件或部分。而当讨论的第二元件、模块、单元、部件或部分时，并不表明本申请必然存在第一元件、模块、单元、部件或部分。
图1为本申请实施例提供的一种缓冲电路的电路结构示意图，参考图1，缓冲电路可以包括输入端子、输出端子、供电电源端子VCC、驱动单元11、负电容单元12以及负载单元13。输入端子配置为输入差分信号。输出端子配置为连接功能电路。供电电源端子VCC配置为接入供电电源。驱动单元11，配置为响应输入端子处的输入差分信号并生成输出差分信号至输出端子。负载单元13，耦合于输出端子与供电电源端子之间。负电容单元12，耦合于供电电源端子与输出端子之间，配置为降低功能电路的电容。
具体地，缓冲电路的输入端子包括第一输入端子VIN和第二输入端子VIP，输入端子配置为接入输入差分信号。输出端子包括第一输出端子VON和第二输出端子VOP，输出端子配置为向功能电路提供输出差分信号，从而使得功能电路正常工作。驱动单元11能够根据输入差分信号生成输出差分信号，例如当第一输入端子VIN输入高电平，第二输入端子VIP输入低电平时，驱动单元11能够控制第一输出端子VOP输出低电平，第二输出端子VON输出高电平；而当第一输入端子VIN输入低电平，第二输入端子VIP输入高电平时，驱动单元11能够控制第一输出端子VOP输出高电平，第二输出端子VON输出低电平。负载单元13配置为产生一个压降，从而使得对应的输出端子能够输出高电平和低电平。在高频时，功能电路相对于缓冲电路将会存在较大的等效电容，影响信号传输的速度，从而使得缓冲电路的工作频率也较低。本实施例通过在缓冲电路的供电电源端子VCC与输出端子之间耦合负电容单元12，能够极大地降低功能电路的电容，从而提高信号传输的速度，进而提高带负载能力，提高缓冲电路的工作频率。
本实施例的技术方案，采用的缓冲电路包括输入端子、输出端子、供电电源端子、驱动单元、负载单元以及负电容单元。输入端子配置为接入输入差分信号，输出端子配置为连接功能电路，供电电源端子配置为接入供电电源。驱动单元，配置为响应输入端子处的输入差分信号并生成输出差分信号至输出端子。负载单元，耦合于输出端子与供电电源端子之间。负电容单元，耦合于供电电源端子与输出端子之间，配置为降低功能电路的电容。通过在缓冲电路的供电电源端子与输出端子之间耦合负电容单元，能够极大地降低功能电路的电容，从而提高信号传输的速度，进而提高带负载能力，提高缓冲电路的工作频率。
在一些实施例中，继续参考图1，输出端子包括第一输出端子VOP和第二输出端子VON。负载单元13包括第一负载R1和第二负载R2。负电容单元12包括第一三极管Q5、第二三极管Q6、第一二极管结构Q3和第二二极管结构Q4。第一负载R1、第一三极管Q5和第一二极管结构Q3串接于供电电源端子VCC与第一输出端子VOP之间。第二负载R2、第二三极管Q6级第二二极管结构Q4串接于供电电源端子VCC与第二输出端VON之间。其中，第一三极管Q5的基极与第二三极管Q6的集电极电连接，第二三极管Q6的基极与第一三极管Q5的集电极电连接。
具体地，第一三极管Q5和第二三极管Q6形成交叉对管结构，且第一二极管结构Q3和第二二极管结构Q4耦合形成负反馈电容，负反馈电容和交叉对管结构 形成负电容效应，进而使得负电容单元12能够降低功能电路的电容，提高缓冲电路的工作频率。另外，本实施例中利用二极管结构耦合形成负反馈电容，二极管结构还能为所处的输出支路提供一个压降，进而可以降低缓冲电路的功耗。
示例性地，如图1中所示，第一负载R1的第一端与供电电源端子VCC电连接，第一负载R1的第二端与第一三极管Q5的集电极电连接。第一三极管Q5的发射极与第一二极管结构Q3的第一极电连接，第一二极管结构Q3的第二极与第一输出端子VOP电连接。第二负载R2的第一端与供电电源端子VCC电连接，第二负载R2的第二端与第二三极管Q6的集电极电连接。第二三极管Q6的发射极与第二二极管结构Q4的第一极电连接，第二二极管结构Q4的第二极与第二输出端子VON电连接。
具体地，在本实施例中，第一负载R1、第一三极管Q5和第一二极管结构Q3依次串接于供电电源端子VCC与第一输出端子VOP之间，而第二负载R2、第二三极管Q6和第二二极管结构Q4依次串接于供电电源端子VCC与第二输出端子VON之间。第一负载R1和第二负载R2的阻值均可以是50欧姆。第一三极管Q5和第二三极管Q6均可以是NPN型三极管，且两者型号可相同。
在其它一些实施方式中，如图2所示，图2为本申请实施例提供的又一种缓冲电路的电路结构示意图，本实施例中，第一二极管结构Q3的第一极与供电电源端子VCC电连接，第一二极管结构Q3的第二极与第一三极管Q5的集电极电连接。第一三极管Q5的发射极与第一负载R1的第一端电连接，第一负载R1的第二端与第一输出端子VOP电连接。第二二极管结构Q4的第一极与供电电源端子VCC电连接，第二二极管结构Q4的第二极与第二三极管Q6的集电极电连接。第二三极管Q6的发射极与第二负载R2的第一端电连接，第二负载R2的第二端与第二输出端子VON电连接。在本实施例中，第一二极管结构Q3、第一三极管Q5和第一负载R1依次串接在供电电源端子VCC与第一输出端子VOP之间，第二二极管结构Q4、第二三极管Q6和第二负载R2依次串接在供电电源端子VCC和第二输出端子VON之间。当然，在其它一些实施方式中，还可以是其它的接法，只要能够利用负电容单元降低功能电路的电容，以及利用第一二极管结构、第二二极管结构构成负反馈电容并降低功耗即可。
在一些实施例中，继续参考图1和图2，第一二极管结构Q3包括第三三极管，第三三极管的基极与第三三极管的集电极电连接后作为第一二极管结构Q3的第一 极，第三三极管的发射极作为第一二极管结构Q3的第二极。第二二极管结构Q4包括第四三极管，第四三极管的基极与第四三极管的集电极电连接后作为第二二极管结构Q4的第一极，第四三极管的发射极作为第二二极管结构Q4的第二极。利用第三三极管和第四三极管分别形成第一二极管结构和第二二极管结构，除了能够作为二极管使用外，由于与第一三极管Q5、第二三极管Q6的温度系数接近，还能够起到温度补偿的作用。
在一些实施例中，继续参考图1和图2，驱动单元11包括第五三极管Q1和第六三极管Q2。输入端子包括第一输入端子VIN和第二输入端子VIP。第五三极管Q1的集电极与第一输出端子VOP电连接，第五三极管Q1的发射极与第六三极管Q2的发射极电连接，第五三极管Q1的基极与第一输入端子VIN电连接，第六三极管Q2的集电极与第二输出端子VON电连接，第六三极管的基极与第二输入端子VIP电连接。
具体地，第五三极管Q1和第六三极管Q2均为电流驱动的方式，当第一输入端子VIN为高电平，第二输入端子VIP为低电平时，第五三极管Q1导通，第六三极管Q2关断，第一负载R1上流过电流，使得第一负载R1上产生压降，也即第一输出端子VOP输出的电压小于供电电源端子VCC处的电压，而由于第六三极管Q2关断，第二负载R2上无电流，第二输出端子VON输出的电压等于供电电源端子VCC处的电压，也即第一输出端子VOP输出低电平，第二输出端子VON输出高电平。当第一输入端子VIN为低电平，第二输入端子VIP为高电平时，第五三极管Q1关断，第六三极管Q2导通，第二负载R2上流过电流，使得第二负载R2上产生压降，也即第二输出端子VON输出的电压小于供电电源端子VCC处的电压，而由于第五三极管Q1关断，第一负载R1上无电流，第一输出端子VOP输出的电压等于供电电源端子VCC处的电压，也即第一输出端子VOP输出高电平，第二输出端子VON输出低电平。
在一些实施例中，继续参考图1和图2，缓冲电路还包括第一电流源I1，第一电流源I1的第一端与第五三极管Q1的发射极以及第六三极管Q2的发射极电连接，第一电流源I1的第二极接地。
具体地，第一电流源I1配置为第五三极管Q1和第六三极管Q2提供偏置，可以提供稳定的静态工作点。第一电流源I1电流的大小影响输出端子的输出电压的摆幅，而摆幅的大小会影响传输的速率、距离以及电路的功耗等，第一电流源I1 输出电流可以是16毫安。
在一些实施例中，图3为本申请实施例提供的又一种缓冲电路的电路结构示意图，缓冲电路还包括第一射极跟随器14和第二射极跟随器15。第一输出端子VOP与第一射极跟随器14的输入端电连接，第一射级跟随器14的输出端作为缓冲电路的第一跟随输出端VOP1。第二输出端子VON与第二射极跟随器15的输入端电连接，第二射极跟随器15的输出端作为缓冲电路的第二跟随输出端VON2。
具体地，本实施例中可设置输出差分信号分别经过第一射极跟随器14和第二射极跟随器15后由缓冲电路的跟随输出端输出，通过增加射极跟随器，可以极大地提高缓冲电路的带负载能力，进一步扩大缓冲电路的应用范围。需要说明的是，当缓冲电路添加射极跟随器后，功能电路可连接在缓冲电路的跟随输出端。
示例性地，如图3所示，第一射极跟随器14包括第七三极管Q7和第二电流源I2。第七晶体管Q7的基极与第一输出端子电连接，第七三极管Q7的集电极与供电电源端子VCC电连接，第七三极管Q7的发射极与第二电流源I2的第一端以及第一跟随输出端VOP1电连接，第二电流源I2的第二端接地。第二射极跟随器15包括第八三极管Q8和第三电流源I3。第八三极管Q8的基极与第二输出端子VON电连接，第八三极管Q8的集电极与供电电源端子VCC电连接，第八三极管Q8的发射极与第三电流源I3的第一端以及第二跟随输出端VON1电连接，第三电流源I3的第二端接地。
具体地，本实施例中利用三极管和电流源即可实现射极跟随器的功能，电路结构简单，易于实现，可以极大地降低缓冲电路的成本。本实施例的缓冲电路可以应用在时钟链路中，提高时钟链路的驱动能力，还可以进行波形整形。
本申请实施例还提供了一种延时电路，延时电路包括本申请任意实施例提供的缓冲电路和功能电路，其中，缓冲电路的输出端子配置为连接功能电路，功能电路包括压控延时单元，压控延时单元配置为将输入信号延时后输出。因其包括本申请任意实施例提供的延时电路，因而也具有相同的有益效果，在此不再赘述。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附 的权利要求范围决定。

Claims (10)

  1. 一种缓冲电路，其特征在于，所述缓冲电路包括：
    输入端子、输出端子和供电电源端子，所述输入端子配置为接入输入差分信号，所述输出端子配置为连接功能电路，所述供电电源端子配置为接入供电电源；
    驱动单元，配置为响应所述输入端子处的输入差分信号并生成输出差分信号至所述输出端子；
    负载单元，耦合于所述输出端子与所述供电电源端子之间；
    负电容单元，耦合于所述供电电源端子与所述输出端子之间，配置为降低所述功能电路的电容。
  2. 根据权利要求1所述的缓冲电路，其特征在于，所述输出端子包括第一输出端子和第二输出端子；所述负载单元包括第一负载和第二负载；所述负电容单元包括第一三极管、第二三极管、第一二极管结构和第二二极管结构；
    所述第一负载、所述第一三极管和所述第一二极管结构串接于所述供电电源端子与所述第一输出端子之间；所述第二负载、所述第二三极管及所述第二二极管结构串接于所述供电电源端子与所述第二输出端子之间，
    其中，所述第一三极管的基极与所述第二三极管的集电极电连接，所述第二三极管的基极与所述第一三极管的集电极电连接。
  3. 根据权利要求2所述的缓冲电路，其特征在于，所述第一负载的第一端与所述供电电源端子电连接，所述第一负载的第二端与所述第一三极管的集电极电连接；所述第一三极管的发射极与所述第一二极管结构的第一极电连接，所述第一二极管结构的第二极与所述第一输出端子电连接；
    所述第二负载的第一端与所述供电电源端子电连接，所述第二负载的第二端与所述第二三极管的集电极电连接；所述第二三极管的发射极与所述第二二极管结构的第一极电连接，所述第二二极管结构的第二极与所述第二输出端子电连接。
  4. 根据权利要求2所述的缓冲电路，其特征在于，所述第一二极管结构的第一极与所述供电电源端子电连接，所述第一二极管结构的第二极与所述第一三极管的集电极电连接；所述第一三极管的发射极与所述第一负载的第一端电连接，所述第一负载的第二端与所述第一输出端子电连接；
    所述第二二极管结构的第一极与所述供电电源端子电连接，所述第二二极管结构的第二极与所述第二三极管的集电极电连接；所述第二三极管的发射极与所述第二负载的第一端电连接，所述第二负载的第二端与所述第二输出端子电连接。
  5. 根据权利要求3或4所述的缓冲电路，其特征在于，所述第一二极管结构包括第三三极管，所述第三三极管的基极与所述第三三极管的集电极电连接后作为所述第一二极管结构的第一极，所述第三三极管的发射极作为所述第一二极管结构的第二极；
    所述第二二极管结构包括第四三极管，所述第四三极管的基极与所述第四三极管的集电极电连接后作为所述第二二极管结构的第一极，所述第四三极管的发射极作为所述第二二极管结构的第二极。
  6. 根据权利要求1所述的缓冲电路，其特征在于，所述驱动单元包括第五三极管和第六三极管；所述输入端子包括第一输入端子和第二输入端子；
    所述第五三极管的集电极与所述第一输出端子电连接，所述第五三极管的发射极与所述第六三极管的发射极电连接，所述第五三极管的基极与所述第一输入端子电连接；
    所述第六三极管的集电极与所述第二输出端子电连接，所述第六三极管的基极与所述第二输入端子电连接。
  7. 根据权利要求6所述的缓冲电路，其特征在于，所述缓冲电路还包括第一电流源，所述第一电流源的第一端与所述第五三极管的发射极以及所述第六三极管的发射极电连接，所述第一电流源的第二极接地。
  8. 根据权利要求2所述的缓冲电路，其特征在于，所述缓冲电路还包括：
    第一射极跟随器和第二射极跟随器；
    所述第一输出端子与所述第一射极跟随器的输入端电连接，所述第一射极跟随器的输出端作为所述缓冲电路的第一跟随输出端；
    所述第二输出端子与所述第二射极跟随器的输入端电连接，所述第二射极跟随器的输出端作为所述缓冲电路的第二跟随输出端。
  9. 根据权利要求8所述的缓冲电路，其特征在于，所述第一射极跟随器包括第七三极管和第二电流源；所述第七三体管的基极与所述第一输出端子电连接，所述第七三极管的集电极与所述供电电源端子电连接，所述第七三极管的发射极与所述第二电流源的第一端以及所述第一跟随输出端电连接，所述第二电流源的第二端接地；
    所述第二射极跟随器包括第八三极管和第三电流源；所述第八三极管的基极与所述第二输出端子电连接，所述第八三极管的集电极与所述供电电源端子电连接， 所述第八三极管的发射极与所述第三电流源的第一端以及所述第二跟随输出端电连接，所述第三电流源的第二端接地。
  10. 一种延时电路，其特征在于，所述延时电路包括权利要求1-9任一项所述的缓冲电路和功能电路，其中，所述缓冲电路的输出端子配置为连接所述功能电路；所述功能电路为压控延时单元，所述压控延时单元配置为将输入信号延时后输出。
PCT/CN2022/119894 2021-12-30 2022-09-20 缓冲电路和延时电路 WO2023124276A1 (zh)

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