WO2023119622A1 - メモリアクセス方法およびメモリアクセス制御装置 - Google Patents

メモリアクセス方法およびメモリアクセス制御装置 Download PDF

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Publication number
WO2023119622A1
WO2023119622A1 PCT/JP2021/048185 JP2021048185W WO2023119622A1 WO 2023119622 A1 WO2023119622 A1 WO 2023119622A1 JP 2021048185 W JP2021048185 W JP 2021048185W WO 2023119622 A1 WO2023119622 A1 WO 2023119622A1
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Prior art keywords
rule
storage
memory
selection
data
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PCT/JP2021/048185
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English (en)
French (fr)
Japanese (ja)
Inventor
真崇 毛利
崇 山本
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Socionext Inc
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Socionext Inc
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Priority to PCT/JP2021/048185 priority Critical patent/WO2023119622A1/ja
Priority to CN202180105050.4A priority patent/CN118414610A/zh
Priority to JP2023568989A priority patent/JP7754203B2/ja
Publication of WO2023119622A1 publication Critical patent/WO2023119622A1/ja
Priority to US18/740,243 priority patent/US12443346B2/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to a memory access method and a memory access control device.
  • Memory interleave is a technique of dividing memory into multiple areas that can operate simultaneously and appropriately allocating access to memory to these areas, thereby improving overall access efficiency.
  • Patent Document 1 discloses a technique of referring to the lower bits of an access address (logical address) and determining the allocation destination area from the information of the lower bits. For example, lower 3 bits are referred to, and access is distributed to 8 areas from 8 types of 3-bit information. This scheme is simple to implement and works as intended if the access mode is for consecutive addresses. That is, it is possible to evenly distribute access to each area.
  • the access form is not for consecutive addresses but for a group of addresses such that the address difference increases by 8, such as X, X+8, X+16, X+24, .
  • the same area is always accessed.
  • Patent Document 2 discloses a technique for devising a conversion rule from an access address (logical address) to a physical address.
  • the present disclosure provides a memory access method and the like that can support various access modes.
  • a memory access method instructs to store one piece of data according to one first logical address in a first memory or a second memory having a physical address different from that of the first memory.
  • a first storage path selection step of performing a first selection of which of the data storage step and the second storage step to be executed, wherein the first storage step selects the first path according to the data storage instruction and storing the one data in the first memory via a second path, and the second storing step stores the one data in the second memory via a second path in accordance with the data storage instruction.
  • a step of storing data wherein the first selection is performed based on a first interleave rule or a second interleave rule for assigning a physical address to the first logical address in the first storage path selection step; , making the first selection based on the first interleaving rule for one or more of the data storage instructions, and performing the first selection for one or more of the subsequent data storage instructions based on the second interleaving rule and performing the first selection.
  • FIG. 1 is a configuration diagram showing an example of a memory access control device according to an embodiment.
  • FIG. 2 is a flow chart showing an example of a memory access method according to the embodiment.
  • FIG. 3 is a flow chart showing a specific example of the memory access method according to the embodiment.
  • FIG. 4 is a flowchart illustrating an example of read processing in the memory access method according to the embodiment.
  • a memory access method stores one piece of data according to one first logical address in a first memory or a second memory having a physical address different from that of the first memory.
  • the first storage path selection step is based on a first interleave rule or a second interleave rule for assigning a physical address to the first logical address. making a selection, making the first selection based on the first interleaving rule for one or more of the data storage instructions, and performing the second interleaving for the following one or more of the data storage instructions; The first selection is made based on rules.
  • the interleave rule can be switched, so various access modes can be supported.
  • the first interleave rule may be switched to the second interleave rule based on the history of the result of the first selection. Specifically, in the first storing route selection step, the number of times the first storing step is selected within a predetermined time and the second storing step within the predetermined time in the history of the result of the first selection. The first interleave rule may be switched to the second interleave rule when the difference from the number of times the step is selected becomes greater than a first predetermined number.
  • the bias in the first selection can be suppressed by switching the interleave rule. For example, when the difference in the number of times each storage step is selected within a predetermined period of time becomes large, it can be determined that the first selection is biased.
  • switching from the first interleave rule to the second interleave rule based on a history of the plurality of first logical addresses included in the plurality of data storage instructions. may Specifically, in the first storage path selection step, when the history of the plurality of first logical addresses has a predetermined pattern, the transition from the first interleave rule to the second interleave rule is performed.
  • the switching and the predetermined pattern may be set before starting the access operation to the first memory or the second memory.
  • the processing in the first storing step may be stopped and switched to the processing in the second storing step.
  • the predetermined condition is that the number of the unexecuted first storing steps after the first selection in the first storing path selection step is equal to the number of the unexecuted second storing steps. It may be greater than the number of steps by a second predetermined number.
  • the processing of a certain storage step when the processing of a certain storage step is being executed, it is possible to stop the processing of the certain storage step based on a predetermined condition and execute the processing of another storage step. Specifically, if the number of unexecuted storage steps increases after the first selection (that is, if there is a bias in the execution of the storage steps), the processing of the storage step is stopped. can be used to process another storage step. Therefore, bias in execution of the storing step can be suppressed.
  • the first storing step is a second storing path selection step of making a second selection of whether to continue the processing in the first storing step or switch to the processing in the second storing step.
  • the second selection may be made based on a third interleaving rule or a fourth interleaving rule.
  • the third interleaving rule prefers choosing to continue processing in the first storing step rather than choosing to switch to processing in the second storing step.
  • the fourth interleaving rule selects to continue processing in the first storing step rather than switching to processing in the second storing step. It may also be a rule that reduces the
  • the second selection of whether to continue the processing of a certain storage step or switch to the processing of another storage step can be made based on the interleave rule.
  • the interleaving rule can increase or decrease the number of selections for continuing the processing of a certain storage step, thereby suppressing bias in the execution of the storage step.
  • the number of the first storage steps that have not been performed is the number of the second storage steps that have not been performed.
  • a switch may be made from the third interleaving rule to the fourth interleaving rule when the number of storage steps is increased by a second predetermined number.
  • the second storage path selection step based on the state of accessibility to the first memory and the state of accessibility to the second memory, from the third interleave rule to the fourth interleave rule. You may switch to the interleaved rule.
  • the state of accessibility to the first memory and the state of accessibility to the second memory may be based on whether it is during a refresh period.
  • the state of accessibility to the first memory and the state of accessibility to the second memory may be based on whether it is during a retraining period.
  • the third interleave rule is changed to the fourth interleave rule. You can switch to rules.
  • the first storage path selection step further includes the first logical address included in the data storage instruction, and the first storage path based on any one of the first interleave rule and the second interleave rule. It may include a first address conversion recording step of recording combination information whether selection has been made. Alternatively, for example, the first storage path selection step further includes a second address conversion recording step of recording combination information of the first logical address and the assigned physical address included in the data storage instruction. may contain.
  • Such combination information can be stored for when reading data.
  • a data readout that issues a data readout instruction including the second logical address, which instructs to read one piece of data from the first memory or the second memory according to one second logical address.
  • an instruction step ; and a third selection of whether to execute either the first read step or the second read step in response to the data read instruction based on the second logical address included in the data read instruction.
  • a read path selection step wherein the first read step is a step of reading the one data from the first memory through the first path in response to the data read instruction.
  • the second reading step is a step of reading the one data from the second memory through the second path in response to the data read instruction;
  • the third selection may be made based on the combination information corresponding to the first logical address equal to two logical addresses.
  • the stored data when reading data, the stored data can be read by using the combination information stored when the data was stored.
  • a memory access control device stores one piece of data according to one first logical address in a first memory or a second memory having a physical address different from that of the first memory.
  • a data storage instruction unit for issuing a data storage instruction including the first logical address; and storing the one piece of data in the first memory through a first path according to the data storage instruction.
  • a first storage unit for storing, a second storage unit for storing the one data in the second memory through a second path according to the data storage instruction, and a data storage unit according to the data storage instruction , a first storage that performs a first selection of storage by the first storage unit or storage by the second storage unit based on the first logical address included in the data storage instruction; and a path selection section, wherein the first storage path selection section performs the first selection based on a first interleave rule or a second interleave rule for allocating a physical address to the first logical address. , making the first selection based on the first interleaving rule for one or more of the data storage instructions, and performing the first selection for one or more of the subsequent data storage instructions based on the second interleaving rule to make the first selection.
  • FIG. 1 is a configuration diagram showing an example of the memory access control device 1 according to the embodiment.
  • the memory access control device 1 divides the memory into a plurality of areas (banks) that can operate simultaneously, and appropriately distributes access to the memory to these areas, thereby improving the access efficiency as a whole. It is a device that is performed. To simplify the explanation, two areas of the storage devices 60a and 60b will be focused on as the plurality of areas, but accesses may be distributed among three or more areas.
  • the memory access control device 1 includes a master 10, a storage device selection unit 20, storage device control units 30a and 30b, a command monitoring unit 40, and rule holding units 51 and 52.
  • the memory access control device 1 may or may not include the storage devices 60a and 60b.
  • the memory access control device 1 is a computer including a processor, memory, and the like.
  • the memory is ROM (Read Only Memory), RAM (Random Access Memory), etc., and can store programs executed by the processor.
  • Master 10, storage device selection unit 20, storage device control units 30a and 30b, and command monitoring unit 40 are implemented by a processor that executes programs stored in memory.
  • the rule holding units 51 and 52 are implemented by memories, registers, and the like. Note that the rule holding units 51 and 52 may be memories separate from the memory in which the programs are stored.
  • the storage device 60a is a memory area called a bank, and is an example of a first memory.
  • the storage device 60b is a bank different from the storage device 60a, and is an example of a second memory.
  • the storage device 60a and the storage device 60b have different physical addresses.
  • the master 10 is an example of a data storage instruction unit that executes a data storage instruction step of issuing a data storage instruction instructing the storage device 60a or the storage device 60b to store one piece of data according to one first logical address. is.
  • the data storage instruction includes the first logical address.
  • the master 10 executes a data readout instruction step of issuing a data readout instruction to read out one piece of data from the storage device 60a or the storage device 60b according to one second logical address. is an example.
  • the data read instruction includes the second logical address.
  • the storage device selection unit 20 is a component that converts a logical address into a physical address and determines an access route. Specifically, in response to the data storage instruction, the storage device selection unit 20 causes the storage device control unit 30a to perform storage (first storage step) and storage based on the first logical address included in the data storage instruction.
  • the storage device selection unit 20 performs the first selection based on the first interleave rule or the second interleave rule for allocating the physical address to the first logical address held in the rule holding unit 51 .
  • the storage device selection unit 20 performs a first selection based on a first interleave rule for one or more data storage instructions, and performs a first selection based on a second interleave rule for one or more subsequent data storage instructions. A first selection is made based on In addition, in response to the data read instruction, the storage device selection unit 20 causes the storage device control unit 30a to read (first read step) based on the second logical address included in the data read instruction.
  • 30b is an example of a readout route selection unit that executes a readout route selection step for selecting which of the readouts (second readout step) is to be executed.
  • the storage device control unit 30a is an example of a first storage unit that executes a first storage step of storing one piece of data in the storage device 60a via a first path in response to a data storage instruction.
  • the first path is a path that connects the storage device selection unit 20 and the storage device 60a via the storage device control unit 30a.
  • Storage device control unit 30a is an example of a first reading unit that executes a first reading step of reading one piece of data from storage device 60a via a first path in response to a data reading instruction.
  • the storage device control unit 30a includes a command distribution unit 31a and a command storage unit 32a, and the storage device control unit 30a includes the command distribution unit 31a.
  • Processing in the storage step can be discontinued and switched to processing in the second storage step.
  • the predetermined condition is that after the first selection in the first storage path selection step, the number of unexecuted first storing steps is a second predetermined number greater than the number of unexecuted second storing steps. The only thing is to get bigger.
  • the command distribution unit 31a executes a second storage path selection step of selecting (referred to as a second selection) whether to continue processing in the storage device control unit 30a or switch to processing in the storage device control unit 30b. It is an example of a second storage path selection unit that performs storage path selection.
  • the command distribution unit 31 a performs the second selection based on the third interleave rule or the fourth interleave rule held in the rule holding unit 52 .
  • An access command is temporarily stored in the command storage unit 32a.
  • An access command is stored in the command storage section 32a when the command distribution section 31a selects to continue the processing in the storage device control section 30a.
  • the command storage unit 32a executes the access command when it becomes executable, thereby storing the data in the storage device 60a, and deletes the access command from the command storage unit 32a when the execution of the access command is completed.
  • the command storage unit 32a executes an access command depending on whether access to the storage device 60a is permitted or not.
  • the state of access availability is based on whether the storage device 60a is in the refresh period or whether the storage device controller 30a is in the retraining period for the storage device 60a.
  • the storage device control unit 30a adjusts the timing, etc., but normal access to the target storage device 60a is disabled.
  • access commands stored in the command storage section 32a may not be executed, and access commands may accumulate in the command storage section 32a.
  • the storage device control unit 30b is an example of a second storage unit that executes a second storage step of storing one piece of data in the storage device 60b via a second path in response to a data storage instruction.
  • the second path is a path that connects the storage device selection unit 20 and the storage device 60b via the storage device control unit 30b.
  • Storage device control unit 30b is an example of a second reading unit that executes a second reading step of reading one piece of data from storage device 60b via a second path in response to a data reading instruction.
  • the storage device control unit 30b includes a command distribution unit 31b and a command storage unit 32b, and the storage device control unit 30b includes the command distribution unit 31b.
  • Processing in the storage step can be discontinued and switched to processing in the first storage step.
  • the predetermined condition is that after the first selection in the second storage path selection step, the number of unexecuted second storing steps is a second predetermined number greater than the number of unexecuted first storing steps. The only thing is to get bigger.
  • the command distribution unit 31b performs a second storage path selection step for performing a second selection of whether to continue processing in the storage device control unit 30b or switch to processing in the storage device control unit 30a. It is an example of a route selection part.
  • the command distribution unit 31b makes a second selection based on the third interleave rule or the fourth interleave rule held in the rule holding unit 52.
  • An access command is temporarily stored in the command storage unit 32b.
  • An access command is stored in the command storage section 32b when the command distribution section 31b selects to continue the processing in the storage device control section 30b.
  • the command storage unit 32b executes the access command when it becomes executable, thereby storing the data in the storage device 60b, and deletes the access command from the command storage unit 32b when the execution of the access command is completed.
  • the command storage unit 32b executes an access command depending on whether access to the storage device 60b is permitted or not.
  • the state of accessibility is based on whether the storage device 60b is in the refresh period or whether the storage device 60b is in the retraining period. When the storage device 60b is in the refresh period or the retraining period, the access commands stored in the command storage section 32b may not be executed and the access commands may accumulate in the command storage section 32b.
  • the command monitoring unit 40 monitors the result of the first selection by the storage device selection unit 20. Specifically, the command monitoring unit 40 monitors the storage device control units 30a and 30b to determine whether execution of the first storage step has been selected by the storage device selection unit 20 or whether the second storage step has been performed. to monitor the results of what was selected to run. Then, the command monitoring unit 40 determines the optimum interleaving rule based on the history of the results of the first selection, and stores the determined interleaving rule in the rule holding unit 51 . For example, if another interleave rule is stored in the rule holding unit 51, the interleave rule is rewritten to the determined interleave rule.
  • the command monitoring unit 40 monitors a plurality of first logical addresses included in a plurality of data storage instructions. Specifically, the command monitoring unit 40 monitors the plurality of first logical addresses included in the data storage instructions sequentially issued by the master 10 by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines the optimum interleaving rule based on the history of multiple logical addresses, and stores the determined interleaving rule in the rule holding unit 51 .
  • the storage device selection unit 20 changes the interleave rule used when performing the first selection to the first interleave rule. can be switched from the first interleaving rule to the second interleaving rule.
  • the command monitoring unit 40 monitors the number of unexecuted first storing steps and the number of unexecuted second storing steps. Specifically, the command monitoring unit 40 monitors the number of unexecuted access commands for each of the command storage units 32a and 32b by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines the optimum interleaving rule based on the number of unexecuted access commands, and stores the determined interleaving rule in the rule holding unit 52 .
  • the command monitoring unit 40 monitors whether or not the storage device 60a can be accessed and whether or not the storage device 60b can be accessed. Specifically, the command monitoring unit 40 monitors the storage device control units 30a and 30b to determine whether the command storage unit 32a can access the storage device 60a and whether the command storage unit 32b can access the storage device 60b. Monitor the availability status. Then, the command monitoring unit 40 determines the optimum interleaving rule based on the status of each access, and stores the determined interleaving rule in the rule holding unit 52 .
  • the command monitoring unit 40 monitors the chip temperature of the storage device 60a and the chip temperature of the storage device 60b. Although not shown, specifically, the command monitoring unit 40 monitors the storage devices 60a and 60b (or monitors the output of a sensor that senses the chip temperature of the storage devices 60a and 60b). ), monitor the chip temperature of the storage device 60a and the chip temperature of the storage device 60b. Then, the command monitoring unit 40 determines the optimum interleaving rule based on each chip temperature, and stores the determined interleaving rule in the rule holding unit 52 .
  • the command distribution units 31a and 31b change the interleave rule used when making the second selection to the fourth interleave rule. It is possible to switch from an interleaving rule of 3 to a 4th interleaving rule.
  • the rule holding unit 51 holds the interleaving rule determined by the command monitoring unit 40.
  • one interleave rule is called a first interleave rule
  • an interleave rule different from the first interleave rule is called a second interleave rule.
  • the first interleave rule and the second interleave rule are rules for assigning physical addresses to the first logical addresses.
  • the rule holding unit 52 holds the interleaving rule determined by the command monitoring unit 40.
  • one interleave rule is called the third interleave rule
  • an interleave rule different from the third interleave rule is called the fourth interleave rule.
  • the third interleave rule for the command distribution unit 31a is more likely to choose to continue processing in the first storage step than to choose to switch to processing in the second storage step. It is a rule to let Specifically, the third interleaving rule includes a rule such that the processing in the first storing step is performed three times and the processing in the second storing step is performed twice, or a rule that the processing in the second storing step is performed twice. The rule is that the processing in the second storage step is performed once, while the processing in the step is performed five times.
  • the fourth interleaving rule for the command distribution unit 31a is to choose to continue processing in the first storage step less than to choose to switch to processing in the second storage step. It is a rule to let Specifically, the fourth interleaving rule is a rule such that the processing in the first storing step is performed twice, while the processing in the second storing step is performed three times, or The rule is that the processing in the second storage step is performed five times, while the processing in the step is performed once.
  • the third interleave rule for the command distribution unit 31b is to select continuation of the process in the second storage step more often than to select switching to the process in the first storage step.
  • the fourth interleave rule for the command distribution unit 31b is to select continuation of the processing in the second storage step and to select switching to the processing in the first storage step. It is a rule that makes less than
  • FIG. 2 is a flowchart showing an example of a memory access method according to the embodiment. Since the memory access method is a method executed by the memory access control device 1, FIG. 2 is also a flowchart showing an example of the operation of the memory access control device 1 according to the embodiment.
  • the master 10 issues a data storage instruction instructing the storage device 60a or storage device 60b to store one piece of data according to one first logical address (step S11: data storage instruction step).
  • the storage device selection unit 20 selects which of the first storage step and the second storage step is to be executed based on the first logical address included in the data storage instruction.
  • a first selection is made (step S12: first storage route selection step).
  • the storage device selection unit 20 performs the first selection based only on one first logical address included in one data storage instruction as the logical address.
  • the storage device selection unit 20 may perform the first selection based on a plurality of first logical addresses included in a plurality of data storage instructions as the logical addresses.
  • the storage device selector 20 makes the first selection based on the first interleave rule or the second interleave rule.
  • the storage device selection unit 20 first performs the first selection based on the first interleaving rule.
  • the storage device control unit 30a or 30b executes the selected storage step (step S13).
  • the storage device control section 30a executes the first storing step.
  • the first storing step is a step of storing one piece of data in the storage device 60a through the first route in response to a data storing instruction.
  • the storage device control unit 30b executes the second storing step.
  • the second storing step is a step of storing one piece of data in the storage device 60b through the second route in response to the data storing instruction.
  • the command monitoring unit 40 determines whether or not the condition for switching the interleave rule is satisfied (step S14). Conditions for switching interleave rules will be described later.
  • step S14 If it is determined that the condition for switching the interleave rule is not satisfied (No in step S14), the interleave rule is not switched, the next data storage instruction is issued in step S11, and the same interleave rule as the previous one (for example, the first interleave rule is used). The processing after step S12 is performed using the rule).
  • step S14 If it is determined that the condition for switching the interleave rule is satisfied (Yes in step S14), the storage device selection unit 20 switches the interleave rule (step S15), and in step S11, the next data storage instruction is issued, which is different from the previous one.
  • the processing after step S12 is performed using an interleave rule (for example, the second interleave rule).
  • the storage device selection unit 20 performs the first selection based on the first interleave rule for one or more data storage instructions, and the second selection for the following one or more data storage instructions.
  • a first selection is made based on the interleaving rules of .
  • a second selection is made between continuing the processing in the first storing step and switching to the processing in the second storing step, which will be explained in FIG.
  • FIG. 3 is a flowchart showing a specific example of the memory access method according to the embodiment. Note that FIG. 3 is also a flowchart showing a specific example of the operation of the memory access control device 1 according to the embodiment. Steps S21 to S24 of part A shown in FIG. 3 are processes performed by the storage device selection unit 20, and steps S25 to S29 of part B are performed by the storage device control unit 30a or 30b (specifically, command allocation). 31a or 31b).
  • the storage device selection unit 20 receives the access command issued by the master 10 (step S21).
  • the storage device selection unit 20 determines whether or not the interleave rule held in the rule holding unit 51 has been changed by the command monitoring unit 40 (step S22). For example, assume that the rule holding unit 51 holds a first interleave rule.
  • the command monitoring unit 40 determines that the difference between the number of times the first storage step is selected within a predetermined time and the number of times the second storage step is selected within a predetermined time in the history of the results of the first selection is the first is greater than a predetermined number, the interleave rule held in the rule holding unit 51 may be changed from the first interleave rule to the second interleave rule. That is, if the selection of either the first storage step or the second storage step by the storage device selection unit 20 is biased within a predetermined time, the first interleave rule is changed to the second interleave rule.
  • the command monitoring unit 40 sets the interleaving rule held in the rule holding unit 51 to the first may be changed from the first interleave rule to the second interleave rule.
  • the history of a plurality of first logical addresses is a list of one first logical address included in each of the data storage instructions sequentially issued from the master 10, arranged in order of issuance, and included in the latest data storage instruction. This is the history up to the first logical address that is stored.
  • the history of a plurality of first logical addresses includes, for example, logical addresses such as "...000”, “...001", “...010", and "...011".
  • the predetermined pattern is, for example, a pattern in specific bits of the plurality of first logical addresses, such as a pattern in the least significant bit.
  • a specific example of the predetermined pattern is a pattern in which the least significant bits of the plurality of first logical addresses are 0, 0, 0, 0, .
  • a first interleaving rule may choose to perform a first storing step when the least significant bit has a value of 0 and to perform a second storing step when the least significant bit has a value of 1.
  • the rule is to select
  • the second interleaving rule selects to perform the first storing step when the value of the bit immediately above the least significant bit is 0 and the value of the bit immediately above the least significant bit is 1.
  • the rule is that sometimes we choose to perform the second storage step.
  • the interleave rule held in the rule holding unit 51 is changed from the first interleave rule to the second interleave rule.
  • the bit above the least significant bit of the plurality of first logical addresses is 0, 1, 0, 1, . . . storage steps can be evenly selected.
  • the predetermined pattern is set before starting an access operation to the storage device 60a or 60b.
  • a predetermined pattern and interleave rule are set according to the type of access mode, and the interleave rule is switched by detecting access imbalance. .
  • the storage device selection unit 20 determines that the interleave rule held in the rule holding unit 51 has been changed by the command monitoring unit 40 (Yes in step S22), the storage device selection unit 20 uses the new rule (for example, the second interleave rule). A storage device to be accessed is selected (step S23).
  • the storage device selector 20 switches from the first interleave rule to the second interleave rule based on the history of the results of the first selection. Specifically, the storage device selection unit 20 selects the number of times the first storage step is selected within a predetermined period of time and the number of times the second storage step is selected within the predetermined period of time in the history of the results of the first selection. If the difference becomes greater than a first predetermined number, a switch will be made from the first interleaving rule to the second interleaving rule.
  • the storage device selector 20 changes the interleave rule from the first interleave rule to the second interleave rule based on the history of the plurality of first logical addresses included in the plurality of data storage instructions. Switch to the interleaved rule. Specifically, the storage device selector 20 switches from the first interleave rule to the second interleave rule when the history of the plurality of first logical addresses has a predetermined pattern.
  • the storage device selection unit 20 determines that the interleave rule held in the rule holding unit 51 has not been changed by the command monitoring unit 40 (No in step S22), the conventional rule (for example, the first interleave rule) is used. Then, the storage device to be accessed is selected (step S24).
  • the conventional rule for example, the first interleave rule
  • the command distribution unit 31a or 31b receives an access command from the storage device selection unit 20 (step S25).
  • the storage device selection unit 20 selects the first storage step as the first selection, and the command distribution unit 31a receives an access command.
  • the command distribution unit 31a determines whether or not the interleave rule held in the rule holding unit 52 has been changed by the command monitoring unit 40 (step S26). For example, assume that the rule holding unit 52 holds a third interleave rule.
  • the command monitoring unit 40 determines that the number of unexecuted first storage steps is a second predetermined number greater than the number of unexecuted second storage steps.
  • the interleave rule held in the rule holding unit 52 may be changed from the third interleave rule to the fourth interleave rule. That is, when the number of unexecuted access commands stored in the command storage unit 32a is larger than the number of unexecuted access commands stored in the command storage unit 32b by a second predetermined number, the The interleaving rule of 3 may be changed to the interleaving rule of 4th.
  • the command monitoring unit 40 changes the interleave rule held in the rule holding unit 52 from the third interleave rule to You may change to the 4th interleaving rule.
  • the state of access to the storage device 60a is during the refresh period or the retraining period
  • the state of access to the storage device 60b is the refresh period or the retraining period. If not, it may change from the third interleaving rule to the fourth interleaving rule.
  • the access command stored in the command storage unit 32a cannot be executed to store data in the storage device 60a. There is a possibility that the number of stored unexecuted access commands is larger than the number of unexecuted access commands stored in the command storage unit 32b. In such cases, the third interleaving rule may be changed to the fourth interleaving rule.
  • the command monitoring unit 40 changes the interleave rule held in the rule holding unit 52 from the third interleave rule to the third interleave rule.
  • 4 interleave rule may be used.
  • the chip temperature of the storage device 60a is high, the access commands stored in the command storage unit 32a are being executed with high frequency, and access commands may continue to be stored in the command storage unit 32a one after another. Therefore, the number of unexecuted access commands stored in the command storage unit 32a may be larger than the number of unexecuted access commands stored in the command storage unit 32b. In such cases, the third interleaving rule may be changed to the fourth interleaving rule.
  • step S26 access is made based on the new rule (for example, the fourth interleave rule).
  • a storage device to be used is selected (step S27). For example, in this case, the command distribution unit 31a does not store the access command in the command storage unit 32a, but stores the access command in the command storage unit 32b (step S29).
  • the command distribution unit 31a By changing the interleaving rule by the command monitoring unit 40, the command distribution unit 31a increases the number of unexecuted first storage steps after the first selection by the storage device selection unit 20 to the number of unexecuted second storage steps. If the number of steps is greater than the number of steps by a second predetermined number, then the third interleaving rule will be switched to the fourth interleaving rule. Alternatively, by changing the interleave rule by the command monitoring unit 40, the command distribution unit 31a switches from the third interleave rule to the fourth interleave rule based on the state of access permission to the storage device 60a and the state of access permission to the storage device 60b.
  • the command distribution unit 31a switches from the third interleave rule to the fourth interleave rule. Switch to the interleaved rule.
  • the command distribution unit 31a determines that the interleave rule held in the rule holding unit 52 has not been changed by the command monitoring unit 40 (No in step S26).
  • the command distribution unit 31a follows the conventional rule (for example, the third interleave rule).
  • a storage device to be accessed is selected (step S28). For example, in this case, the command distribution unit 31a continues storing access commands in the command storage unit 32a (step S29).
  • the command distribution units 31a and 31b select which of the storage devices 60a and 60b to store the data. Explain why you are choosing again.
  • the command distribution units 31a and 31b may be unnecessary.
  • the storage device controllers 30a and 30b may receive access commands from a plurality of masters. There is a risk that the execution of the storage step will be biased with the device control unit 30b, resulting in a decrease in access efficiency.
  • access to the storage devices 60a and 60b may not be possible (during the refresh period or during the retraining period), or for some other reason, the execution of the storage step may be biased, and the access efficiency may decrease.
  • the command distribution units 31a and 31b also select which of the storage devices 60a and 60b to store the data.
  • the status of whether or not access is permitted can be determined, for example, from the status of each of the storage device control units 30a and 30b.
  • the temperature of memory chips with high access frequency will be relatively high. By knowing the chip temperature, access imbalance can be determined. .
  • the storage device selection unit 20 executes a second address conversion recording step of recording combination information of the first logical address included in the data storage instruction and the assigned physical address.
  • the second address conversion recording step of recording the combination information of the first logical address and the assigned physical address included in the data storage instruction may be executed by the command distribution units 31a and 31b.
  • FIG. 4 is a flowchart showing an example of read processing in the memory access method according to the embodiment.
  • FIG. 4 is also a flowchart showing an example of read operation of the memory access control device 1 according to the embodiment.
  • the master 10 issues a data read instruction to read one piece of data from the storage device 60a or the storage device 60b according to one second logical address (step S31: data read instruction step).
  • storage device selection unit 20 determines which of the first read step and the second read step is to be executed based on the second logical address included in the data read instruction.
  • a third selection is made (step S32: reading route selection step).
  • the storage device selection unit 20 performs the third selection based on the combination information corresponding to the first logical address equal to the second logical address. That is, when data is read according to the second logical address equal to the first logical address at the time of data storage, the information at the time of data storage is referred to.
  • the storage device control unit 30a or 30b executes the selected read step (step S33).
  • the storage device control unit 30a executes the first read step.
  • the first read step is a step of reading one piece of data from storage device 60a through the first path in response to a data read instruction.
  • the storage device control section 30b executes the second reading step.
  • the second reading step is a step of reading one piece of data from storage device 60b through the second path in response to a data read instruction.
  • the interleave rule since the interleave rule is switched, various access modes can be supported. Further, the first selection of which of the first storing step and the second storing step is to be performed is made based on the interleave rule to be switched, so that bias in the first selection can be suppressed. Further, after the first selection, a second selection of whether to continue the processing in the first storing step or switch to the processing in the second storing step is performed, thereby suppressing bias in the execution of the storing step. can. In this way, access efficiency can be improved.
  • the processing in the first storing step is stopped, and the example is switched to the processing in the second storing step. good too.
  • the memory access control device 1 does not have to include the command distribution units 31a and 31b.
  • the present disclosure can be implemented as a program for causing a processor to execute the steps included in the memory access method.
  • the present disclosure can be implemented as a non-temporary computer-readable recording medium such as a CD-ROM recording the program.
  • each step is executed by executing the program using hardware resources such as the CPU, memory, and input/output circuits of the computer. . That is, each step is executed by the CPU obtaining data from a memory, an input/output circuit, or the like, performing an operation, or outputting the operation result to the memory, an input/output circuit, or the like.
  • each component included in the memory access control device 1 may be configured with dedicated hardware, or realized by executing a software program suitable for each component.
  • Each component may be realized by reading and executing a software program recorded in a recording medium such as a hard disk or a semiconductor memory by a program execution unit such as a CPU or processor.
  • a part or all of the functions of the memory access control device 1 according to the above embodiment are typically implemented as an LSI, which is an integrated circuit. These may be made into one chip individually, or may be made into one chip so as to include part or all of them. Further, circuit integration is not limited to LSIs, and may be realized by dedicated circuits or general-purpose processors.
  • An FPGA Field Programmable Gate Array
  • a reconfigurable processor that can reconfigure the connections and settings of the circuit cells inside the LSI may be used.
  • the present disclosure also includes various modifications in which a person skilled in the art makes modifications to each embodiment of the present disclosure, as long as they do not deviate from the gist of the present disclosure.
  • the present disclosure can be applied to devices in which memory interleaving is performed.
  • 1 memory access control device 10 master 20 storage device selection unit 30a, 30b storage device control unit 31a, 31b command distribution unit 32a, 32b command storage unit 40 command monitoring unit 51, 52 rule holding unit 60a, 60b storage device

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