JPWO2023119622A1 - - Google Patents
Info
- Publication number
- JPWO2023119622A1 JPWO2023119622A1 JP2023568989A JP2023568989A JPWO2023119622A1 JP WO2023119622 A1 JPWO2023119622 A1 JP WO2023119622A1 JP 2023568989 A JP2023568989 A JP 2023568989A JP 2023568989 A JP2023568989 A JP 2023568989A JP WO2023119622 A1 JPWO2023119622 A1 JP WO2023119622A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Networks & Wireless Communication (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/048185 WO2023119622A1 (ja) | 2021-12-24 | 2021-12-24 | メモリアクセス方法およびメモリアクセス制御装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023119622A1 true JPWO2023119622A1 (https=) | 2023-06-29 |
| JPWO2023119622A5 JPWO2023119622A5 (https=) | 2024-09-04 |
| JP7754203B2 JP7754203B2 (ja) | 2025-10-15 |
Family
ID=86901828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023568989A Active JP7754203B2 (ja) | 2021-12-24 | 2021-12-24 | メモリアクセス方法およびメモリアクセス制御装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US12443346B2 (https=) |
| JP (1) | JP7754203B2 (https=) |
| CN (1) | CN118414610A (https=) |
| WO (1) | WO2023119622A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20250101484A (ko) * | 2023-12-27 | 2025-07-04 | 삼성전자주식회사 | 컴퓨팅 장치 및 이의 동작 방법 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003323339A (ja) * | 2002-03-01 | 2003-11-14 | Sony Computer Entertainment Inc | メモリアクセス装置、半導体デバイス、メモリアクセス制御方法、コンピュータプログラム及び記録媒体 |
| US20150161045A1 (en) * | 2013-12-10 | 2015-06-11 | Lsi Corporation | Slice Formatting and Interleaving for Interleaved Sectors |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5377340A (en) | 1991-06-18 | 1994-12-27 | Hewlett-Packard Company | Method and apparatus for memory interleaving using an improved hashing scheme |
| US6912616B2 (en) | 2002-11-12 | 2005-06-28 | Hewlett-Packard Development Company, L.P. | Mapping addresses to memory banks based on at least one mathematical relationship |
-
2021
- 2021-12-24 JP JP2023568989A patent/JP7754203B2/ja active Active
- 2021-12-24 CN CN202180105050.4A patent/CN118414610A/zh active Pending
- 2021-12-24 WO PCT/JP2021/048185 patent/WO2023119622A1/ja not_active Ceased
-
2024
- 2024-06-11 US US18/740,243 patent/US12443346B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003323339A (ja) * | 2002-03-01 | 2003-11-14 | Sony Computer Entertainment Inc | メモリアクセス装置、半導体デバイス、メモリアクセス制御方法、コンピュータプログラム及び記録媒体 |
| US20150161045A1 (en) * | 2013-12-10 | 2015-06-11 | Lsi Corporation | Slice Formatting and Interleaving for Interleaved Sectors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118414610A (zh) | 2024-07-30 |
| WO2023119622A1 (ja) | 2023-06-29 |
| US20240329849A1 (en) | 2024-10-03 |
| US12443346B2 (en) | 2025-10-14 |
| JP7754203B2 (ja) | 2025-10-15 |
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