WO2023119574A1 - 半導体素子の駆動装置及び駆動方法 - Google Patents

半導体素子の駆動装置及び駆動方法 Download PDF

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Publication number
WO2023119574A1
WO2023119574A1 PCT/JP2021/047941 JP2021047941W WO2023119574A1 WO 2023119574 A1 WO2023119574 A1 WO 2023119574A1 JP 2021047941 W JP2021047941 W JP 2021047941W WO 2023119574 A1 WO2023119574 A1 WO 2023119574A1
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Prior art keywords
voltage
circuit
semiconductor element
period
short
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English (en)
French (fr)
Japanese (ja)
Inventor
陽平 三井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to PCT/JP2021/047941 priority Critical patent/WO2023119574A1/ja
Priority to JP2023568950A priority patent/JP7618064B2/ja
Priority to DE112021008544.1T priority patent/DE112021008544T5/de
Publication of WO2023119574A1 publication Critical patent/WO2023119574A1/ja
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

  • the present disclosure relates to a driving device and driving method for a semiconductor element.
  • Patent Document 1 International Publication No. 2017/026367 (Patent Document 1) describes a configuration in which a short circuit protection function by an RTC (Real-Time Current Control) circuit is combined with a power switching device of a semiconductor element.
  • the RTC circuit reduces the gate-source voltage of the semiconductor element when the drain current (main circuit current) of the semiconductor element becomes an overcurrent, thereby reducing the drain current.
  • the protection circuit described in Patent Document 1 can operate so that the element is not damaged by the surge voltage by reducing the voltage between the gate and the source when the short-circuit current is large.
  • the current flowing through the semiconductor element during operation of the short circuit protection circuit varies depending on the timing of occurrence of the short circuit and other conditions.
  • the protection circuit described in Patent Document 1 since the content of the protection operation against the occurrence of short-circuit current is constant, there is concern that power loss may occur more than necessary depending on the circumstances of the occurrence of the short-circuit. .
  • the present disclosure has been made to solve the above-described problems, and achieves both securing of protection performance and suppression of unnecessary power loss with respect to the protection function when an abnormality occurs in a semiconductor device. It is intended to
  • a driving device for a semiconductor element in which current flowing from a first main electrode to a second main electrode is controlled according to a voltage of a control electrode, includes a drive circuit, a protection circuit, and a selection circuit.
  • the drive circuit outputs one of a first voltage for turning on the semiconductor element and a second voltage for turning off the semiconductor element to the control electrode in accordance with a gate signal for controlling on/off of the semiconductor element.
  • the protection circuit performs a protection operation to turn off the semiconductor element when an abnormality occurs during the ON period of the semiconductor element.
  • the selection circuit switches the mode of protection operation by the protection circuit according to the driving state of the semiconductor element according to the turn-on command.
  • a method for driving a semiconductor device is provided.
  • a method of driving a semiconductor device in which current flowing from a first main electrode to a second main electrode is controlled according to a voltage of a control electrode, is provided by a method of driving a semiconductor device in which a first main electrode for turning on a semiconductor device is controlled in accordance with a turn-on command for the semiconductor device. a step of outputting a voltage to a control electrode; a step of executing a protection operation of turning off the semiconductor element when an abnormality occurs during an ON period of the semiconductor element; and a step of switching.
  • the protection function when an abnormality occurs in the semiconductor element ensures protection performance and unnecessary power loss. can be compatible with the suppression of
  • FIG. 1 is a block diagram illustrating the configuration of a driving device for a semiconductor element according to an embodiment
  • FIG. 2 is a circuit diagram illustrating a configuration example of a driving device according to Embodiment 1
  • FIG. 4 is an operation waveform diagram when the semiconductor element is turned on by the driving device according to the first embodiment
  • FIG. 5 is a flowchart for explaining control processing of the method for driving the semiconductor device according to the first embodiment
  • FIG. 7 is a circuit diagram illustrating a configuration example of a driving device according to Embodiment 2
  • FIG. 10 is an operation waveform diagram when the semiconductor element is turned on by the driving device according to the second embodiment
  • 10 is a flowchart for explaining control processing of a method for driving a semiconductor element according to Embodiment 2
  • FIG. 11 is a circuit diagram illustrating a configuration example of a driving device according to Embodiment 3;
  • FIG. 10 is an operation waveform diagram when the semiconductor element is turned on by the driving device according to the third embodiment;
  • FIG. 11 is a circuit diagram illustrating a configuration example of a drive device according to Embodiment 4;
  • FIG. 11 is a circuit diagram illustrating a configuration example of a drive device according to Embodiment 5;
  • FIG. 12 is an operation waveform diagram when the semiconductor element is turned on by the driving device according to the fifth embodiment;
  • FIG. 1 is a block diagram for explaining the configuration of a driving device for a semiconductor device according to this embodiment.
  • the drive device 10 controls the on/off of the semiconductor element 5 according to the gate signal Sg.
  • the semiconductor element 5 is composed of a MOSFET, and includes a gate (G) which is a control electrode, a drain (D) which is a first main electrode (high voltage side), and a second main electrode. (low voltage side) with a source (S).
  • G gate
  • D drain
  • S source
  • the current flowing from the first main electrode to the second main electrode is controlled according to the voltage of the control electrode.
  • a MOSFET can be made using a semiconductor substrate such as SiC (silicon carbide), Si, or GaN (gallium nitride), for example.
  • a current Id flowing from the first main electrode (D) to the second main electrode (S) of the semiconductor element 5 (hereinafter, also referred to as “drain current Id”) is the control electrode for the second main electrode (low voltage side). varies depending on the gate-source voltage Vgs (hereinafter also simply referred to as “gate voltage”), which is the voltage of .
  • the semiconductor element 5 is not limited to a MOSFET, and can be composed of an IGBT, a thyristor, or the like as long as it is a switching element in which the current between the main electrodes is controlled according to the voltage of the control electrode.
  • the control electrode is the gate, while the first main electrode is the "collector” and the second main electrode is the "emitter”.
  • the drive device 10 includes a drive circuit 100, a delay circuit 200, a selection circuit 300, and a protection circuit 400.
  • the drive device 10 outputs a drive voltage Vdv to the semiconductor element 5 .
  • the drive circuit 100 receives the gate signal Sg as an input and selects one of a first voltage (on drive voltage) V1 for turning on the semiconductor element 5 and a second voltage (off drive voltage) V2 for turning off the semiconductor element 5. , to the output node Nout electrically connected to the semiconductor element 5 via the gate resistor 6 .
  • the gate signal Sg is set to a logic high level (hereinafter simply referred to as "H level”) during the period when the semiconductor element 5 is turned on, and is set to a logic low level (hereinafter simply referred to as "H level”) during the period when the semiconductor element 5 is turned off. "L level”).
  • H level logic high level
  • H level a logic low level
  • the operation of the drive circuit 100 is also controlled by control signals Sa and Sbd from the protection circuit 400, which will be described later.
  • the delay circuit 200 receives the gate signal Sg and outputs a delayed gate signal Sgd to which a predetermined delay time has been added. Based on the delay gate signal Sgd from the delay circuit 200, the selection circuit 300 outputs selection signals S1 and S2 for switching the mode of protection operation by the protection circuit 400.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present disclosure.
  • the protection circuit 400 has an abnormality detection function of the semiconductor element 5 based on the voltage or current of the first main electrode (drain) of the semiconductor element 5, and outputs control signals Sa and Sbd to the drive circuit 100 when an abnormality is detected. Alternatively, by outputting the third voltage V3 to the output node Nout, a protective operation is performed to prevent the semiconductor element 5 from being damaged by overcurrent.
  • the protection circuit 400 operates based on the selection signals S1 and S2 from the selection circuit 300, and is configured to switch the protection operation according to the driving state of the semiconductor element 5.
  • FIG. As described below, for example, the driving state of the semiconductor element 5 related to protection control can be classified based on the elapsed time from the turn-on start timing at which the gate signal Sg changes from L level to H level.
  • FIG. 2 is a circuit diagram illustrating a specific configuration of the driving device 10A according to the first embodiment.
  • drive device 10A includes drive circuit 100A, delay circuit 200A, selection circuit 300A, and protection circuit 400A.
  • the drive circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400A correspond to examples of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.
  • the drive circuit 100A includes a switching control circuit 103, resistance elements 104 and 106, and switching elements 105 and 107 that are turned on and off complementarily.
  • a power supply 101 is connected between the power supply node Np and the GND node to generate an ON drive voltage (first voltage V1).
  • a power node Np supplies a first voltage V1.
  • the power supply 102 is connected between the GND node and the negative power supply node Nn to generate a negative bias off drive voltage (second voltage V2). That is, the second voltage V2 is a negative voltage (V2 ⁇ 0).
  • a negative power supply node Nn supplies a second voltage V2.
  • the GND node of the driving device 10A is at the same potential as the source (second main electrode) of the semiconductor element 5.
  • a switching element 105 composed of an N-type transistor and a resistance element 104 constituting an on-gate resistance are connected in series between a power supply node Np and an output node Nout.
  • a switching element 107 composed of a P-type transistor and a resistive element 106 constituting an off-gate resistor are connected in series between a negative power supply node Nn and an output node Nout.
  • the switching control circuit 103 generates the control signal Scn according to the gate signal Sg.
  • the control signal Scn is set to H level during the H level period of the gate signal Sg, and is set to L level during the L level period of the gate signal Sg.
  • the delay circuit 200A has a resistance element 201, a capacitor 202, and a trigger circuit 203.
  • a gate signal Sg is input to an RC circuit composed of a resistance element 201 and a capacitor 202 .
  • a trigger circuit 203 generates a delayed gate signal Sgd according to the output voltage of the RC circuit.
  • the delay gate signal Sgd is a signal obtained by adding a delay time TX according to the RC time constant to the gate signal Sg. That is, the delayed gate signal Sgd changes from the L level to the H level at the timing when the delay time TX has elapsed from the timing when the gate signal Sg changes from the L level to the H level.
  • Delay time TX can be adjusted by the resistance value of resistance element 201 and the capacitance value of capacitor 202 .
  • the selection circuit 300A has an inverting buffer 301 and a non-inverting buffer 302 .
  • the inverting buffer 301 outputs a selection signal S1 obtained by inverting the delayed gate signal Sgd from the delay circuit 200 .
  • the non-inverting buffer 302 outputs a select signal S2 having the same logic level as the delayed gate signal Sgd from the delay circuit 200.
  • the protection circuit 400A includes a logic gate 401 for generating a control signal Sa, a logic gate 402 for generating a control signal Sb, a delay circuit 403 for applying a delay time T1, a soft cutoff circuit 500, and a short circuit detection circuit 600A. including.
  • the short circuit detection circuit 600A includes resistive elements 601, 603, 604, a diode 602, a capacitor 605, and a comparator 609.
  • Resistance element 601 is connected between the drain of semiconductor element 5 and node N1.
  • Resistive element 603 is connected between nodes N1 and N2.
  • Resistance element 604 is connected between node N2 and negative power supply node Nn.
  • a diode 602 is connected between the node N1 and the output node Nout, and has an anode connected to the node N1 and a cathode connected to the output node Nout.
  • Capacitor 605 is connected in parallel with resistance element 604 between node N2 and negative power supply node Nn.
  • a comparator 609 generates a short circuit detection signal Soc based on the result of comparison between the voltage Vsig of the node N2 and the determination voltage Vt from the power supply 608. Specifically, when Vsig>Vt, a short-circuit state in which an overcurrent occurs in semiconductor element 5 is detected, and short-circuit detection signal Soc is set to H level.
  • the second voltage V2 which is a negative voltage
  • the drain-source voltage Vds (hereinafter also simply referred to as "drain voltage”) increases. Therefore, in the short circuit detection circuit 600A, the diode 602 becomes conductive, and the voltage Vsig of the node N2 is clamped to a voltage equivalent to the second voltage V2. Therefore, the state of Vsig ⁇ Vt is maintained, and the short-circuit detection signal Soc is fixed at L level.
  • the node N1 becomes a voltage obtained by dividing the drain voltage of the semiconductor element 5 by the resistance elements 601, 603, and 604, but is clamped to the first voltage V1 by the diode 602.
  • the resistance elements 603 and 604 and the capacitor 605 constitute a "filter circuit" having the potential of the node N1 as an input voltage.
  • the voltage Vsig of the node N2 corresponds to the output voltage of the filter circuit. That is, when the output node Nout is connected to the first voltage V1 and the drain voltage Vds is high, the voltage Vsig increases. Specifically, voltage Vsig rises with a slope according to a time constant (RC time constant) determined by the resistance values of resistance elements 603 and 604 and the capacitance value of capacitor 605 .
  • RC time constant time constant
  • the filter circuit continues to charge the capacitor 608 without stopping the charging as described above.
  • voltage Vsig continues to rise without taking the aforementioned maximum value. Therefore, the determination voltage Vt by the power supply 608 is determined based on the first voltage V1 and the time constant of the filter circuit including the resistance elements 603 and 604 and the capacitor 605 so that Vsig>Vt in the short-circuit state. Note that Vt>Vnml is set in order to prevent erroneous determination of normal switching. As a result, the short circuit detection signal Soc is maintained at the L level during the OFF period of the semiconductor element 5 and during the normal ON period, but changes to the H level when a short circuit occurs during the ON period.
  • the logic gate 401 outputs the AND operation result of the selection signal S1 (the inversion of the delay gate signal Sgd) from the inverting buffer 301 and the short circuit detection signal Soc as the control signal Sa.
  • the logic gate 402 outputs the AND operation result of the selection signal S2 (delayed gate signal Sgd) from the non-inverting buffer 302 and the short-circuit detection signal Soc as the control signal Sb.
  • the delay circuit 403 adds a predetermined delay time T1 to the control signal Sb output from the logic gate 402 to output a control signal Sbd.
  • the control signals Sa and Sbd are input to the switching control circuit 103.
  • the switching control circuit 103 changes the control signal Scn from H level to L level when the control signal Sa or Sbd changes from L level to H level during the H level period of the gate signal Sg.
  • the control signal Sb is input to the soft cutoff circuit 500 .
  • the soft cutoff circuit 500 has a resistor element 501, a diode 502, and a switching element 503 composed of an N-type transistor connected in series between an output node Nout and a negative power supply node Nn.
  • a control signal Sb is input to the gate of the N-type transistor forming the switching element 503 .
  • Diode 502 is connected with the forward direction from output node Nout to negative power supply node Nn.
  • the selection signal Since the selection signal S2 is at L level while S1 is at H level, when the short-circuit detection signal Soc changes to H level, the control signal Sa changes to H level.
  • switching control circuit 103 changes control signal Scn from H level to L level. At this time, since the control signal Sb is maintained at L level, the switching element 503 of the soft cutoff circuit 500 is maintained off.
  • the selection signal S2 is at H level, while the selection signal S1 is at L level.
  • the control signal Sb changes to H level.
  • switching element 503 is turned on to form a discharge path from output node Nout to negative power supply node Nn.
  • a voltage drop occurs in the resistance element 501, and the driving voltage Vdv of the output node Nout drops from the first voltage V1 to the third voltage V3 (V1>V3>V2).
  • the switching control circuit 103 changes the control signal Scn in response to the control signal Sbd being set to H level at the timing when the delay time T1 by the delay circuit 403 has passed since the control signal Sb changed to H level. Change from H level to L level. As a result, the switching element 107 is turned on, and the driving voltage Vdv of the output node Nout changes to the second voltage V2 (V2 ⁇ 0). In this way, the soft cutoff circuit 500 can temporarily lower the drive voltage Vdv to the third voltage V3 by operating according to the control signal Sb during the H level period of the control signal Scn.
  • FIG. 3 shows an operation waveform diagram when the semiconductor element is turned on by the driving device according to the first embodiment.
  • the normal waveforms are indicated by solid lines, and the waveforms when a short circuit occurs are indicated by dotted lines.
  • the turn-on operation is started when the gate signal Sg changes from L level to H level.
  • the driving device 10A outputs the second voltage V2 to the gate of the semiconductor element 5 as the driving voltage Vdv during the OFF period of the semiconductor element 5 up to time t1.
  • the driving voltage Vdv output from the driving device 10A to the gate of the semiconductor element 5 changes to the first voltage V1 in response to the gate signal Sg changing from L level to H level. Accordingly, the gate voltage Vgs rises from the second voltage V2, and after a mirror period in which the voltage rise temporarily stops, further rises to reach the first voltage V1.
  • drain current Id the drain current Id
  • drain voltage Vds the drain voltage Vsig at the short-circuit detection circuit 600A during normal turn-on
  • the drain current Id begins to flow when the gate voltage Vgs rises and exceeds the threshold voltage Vth of the semiconductor element 5, and reaches a steady value around the end of the mirror period.
  • the drain voltage Vds begins to drop at the timing when the drain current Id begins to flow, and drops in proportion to the change rate (dId/dt) of the drain current Id due to the parasitic inductance in the circuit. After that, it further decreases around the end of the mirror period, and becomes a steady state at Vds ⁇ 0.
  • the delay time TX by the delay circuit 200 elapses from time t1. That is, the period from time t1 to t2 corresponds to the turn-on period, and after time t2, the period until the gate signal Sg changes to L level corresponds to the steady-on period.
  • short-circuit detection circuit 600A detects Vsig>Vt and sets short-circuit detection signal Soc (FIG. 2) to H level.
  • Soc short-circuit detection signal
  • the switching element 107 is turned on in the drive circuit 100A, so that the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 becomes negative as indicated by the dotted line. It changes to the second voltage V2, which is a voltage. As a result, the gate voltage Vgs drops toward the second voltage V2, and the drain current Id also drops. The drain voltage Vds rises due to a surge voltage generated at the timing when the drain current Id turns to decrease, and then becomes the off-state voltage. Thus, during the turn-on period, the semiconductor device 5 is immediately turned off upon detection of a short circuit condition.
  • the switching element 503 is turned on in the soft cutoff circuit 500, so that the drive voltage Vdv output from the driving device 10A to the gate of the semiconductor element 5 changes from the first voltage V1 to the third voltage Vdv. It drops to voltage V3.
  • the gate voltage Vgs is lowered, so that the drain current Id is also lowered.
  • the control signal Sbd input to the switching control circuit 103 changes to H level.
  • the switching element 107 is turned on in the drive circuit 100A, so that the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 is changed to the second voltage V2 which is a negative voltage. change to As a result, the semiconductor element 5 is turned off, the gate voltage Vgs decreases toward the second voltage V2, and the drain current Id also decreases toward zero.
  • the amount of gate voltage drop at time t5 is suppressed, and the surge voltage can be suppressed by suppressing the drain current Id when turning off the semiconductor element 5 at time t6.
  • the drain current Id short-circuit current
  • the semiconductor element 5 is turned off immediately at the timing (time t5) when the short-circuit state is detected, the surge voltage increases and the drain voltage Vds exceeds the withstand voltage, which may damage the semiconductor element 5. .
  • the surge voltage can be suppressed by applying the soft cutoff circuit 500, so thermal protection in the short circuit state can be performed. Since it is possible to prevent the semiconductor element 5 from being destroyed by the surge voltage generated by the protection operation for , the protection function is ensured.
  • the protection operation turns off the semiconductor element 5 from a state in which the drain current Id is not as large as during the steady-on period. Therefore, by immediately turning off the semiconductor element 5 upon detection of a short-circuit state, the semiconductor element 5 is not destroyed by the surge voltage generated by the protection operation, and power loss (heat generation) generated by the protection operation is suppressed. be able to.
  • the turn-on period corresponds to an example of the "first period”
  • the control of the drive voltage Vdv after time ts corresponds to an example of the "first protection operation”. handle.
  • the steady-on period corresponds to an example of the "second period”
  • the control of the drive voltage Vdv after time t5 corresponds to an example of the "second protection operation”.
  • the delay time TX by the delay circuit 200A corresponds to an embodiment of the "first time”.
  • FIG. 4 shows a flowchart for explaining the control processing of the driving method of the semiconductor element 5 by the driving device 10A.
  • the driving device 10A waits for a turn-off command by the gate signal Sg in step (hereinafter simply referred to as "S") 100 during the OFF period of the semiconductor element 5 when the gate signal Sg is set to L level.
  • S a turn-on command
  • S100 makes a YES determination.
  • the processing after S110 for turning on the semiconductor element 5 is activated.
  • the turn-on command is not detected (NO determination in S100), and the processes after S110 are not started.
  • the drive circuit 100A (FIG. 2) turns on the switching element 105 and turns off the switching element 107 in S110.
  • Vdv be the first voltage V1. Accordingly, the driving device 10A outputs the first voltage V1 to the gate of the semiconductor element 5.
  • the driving device 10A determines whether or not a short-circuit state is detected during the turn-on period from when the turn-on command is received until the delay time TX by the delay circuit 200A elapses.
  • short-circuit detection signal Soc is set to H level by short-circuit detection circuit 600A between times t1 and t2 in FIG. 3, a YES determination is made in S120, and the process proceeds to S170.
  • the driving device 10A turns off the switching element 105 of the driving circuit 100A (FIG. 2) and turns on the switching element 107 to set the driving voltage Vdv to the second voltage V2. Accordingly, the driving device 10A outputs the second voltage V2 to the gate of the semiconductor element 5, thereby turning off the semiconductor element 5.
  • FIG. thus, the operation indicated by the dotted line between times t1 and t2 in FIG. 3 causes the semiconductor element 5 to be immediately turned off in response to the detection of the short circuit condition.
  • the drive device 10A In S120, if the short-circuit state is not detected even after the delay time TX by the delay circuit 200A has elapsed since the turn-on command (NO determination in S120), the drive device 10A generates a turn-off command in S130 and S160. It is determined whether or not a short circuit condition is detected until it is detected.
  • the delay time TX of the delay circuit 200A divides the turn-on period during which the protection operation is switched and the steady-on period according to the elapsed time from the turn-on start.
  • the delay time TX must be set longer than the time Ton required for the drain voltage Vds to drop to zero during normal operation. This required time Ton varies depending on the temperature and the drain current (at steady state), and increases at low temperatures and at high currents. Therefore, by conducting a switching test of the semiconductor element 5, it is possible to set so that TX>Ton is guaranteed.
  • a short-circuit tolerance Tsc [ ⁇ s] is described in a data sheet or the like. Since the short-circuit tolerance Tsc indicates the time margin until the element is destroyed when a short-circuit current flows, it is necessary to set the delay time TX ⁇ Tsc. Therefore, the delay time TX is set to Ton ⁇ TX ⁇ Tsc according to the specifications of the semiconductor device 5 and the switching test.
  • the driving device 10A detects the turn-off command and makes a YES determination in S160. If the short-circuit state is not detected until the turn-off command is detected (NO determination in S130 is maintained), a YES determination is made in S160, and the process proceeds to S170. In this case, the driving device 10A immediately turns off the semiconductor element 5 by outputting the second voltage V2 to the gate of the semiconductor element 5 in response to the turn-off command.
  • a YES determination is made in S130, and the process proceeds to S140.
  • the driving device 10A turns on the switching element 503 of the soft cutoff circuit 500 according to the control signal Sb that is set to H level according to the short circuit detection signal Soc.
  • the operation at time t5 in FIG. 3 is realized, and the driving device 10A can reduce the drain current Id of the semiconductor element 5 by outputting the third voltage V3 to the gate of the semiconductor element 5. .
  • the driving device 10A maintains the driving voltage Vdv at the third voltage during the period corresponding to the times t5 to t6 in FIG. 3 until the delay time T1 by the delay circuit 403 elapses (NO determination in S150).
  • the driving device 10A advances the process to S170, and outputs the second voltage V2 to the gate of the semiconductor element 5, thereby Turn off 5.
  • the delay time T1 by the delay circuit 403 can be set in consideration of this time lag.
  • the drive device 10A it is possible to classify the drive state of the semiconductor element 5 according to the elapsed time from the start of the turn-on operation, and switch between the two types of protection operations described above. Specifically, in the short-circuit protection operation at the time of turn-on, which cuts off a relatively small current, the power loss is reduced by immediately turning off the semiconductor element 5, and the steady-on state, which cuts off a large current. In the short circuit protection operation at time, the semiconductor element 5 can be protected from damage due to surges by applying a soft shutdown. As a result, in the protection function of the semiconductor element against the occurrence of a short-circuit current, it is possible to ensure both protection performance and suppression of unnecessary power loss.
  • FIG. 5 is a circuit diagram illustrating a specific configuration of drive device 10B according to the second embodiment.
  • drive device 10B includes drive circuit 100A, delay circuit 200A, selection circuit 300A, and protection circuit 400B.
  • the drive circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400B correspond to examples of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.
  • the drive device 10B differs from the drive device 10A shown in FIG. 2 in that it includes a protection circuit 400B instead of the protection circuit 400A.
  • the protection circuit 400B differs from the protection circuit 400A of FIG. 2 in that it includes a short circuit detection circuit 600B instead of the short circuit detection circuit 600A. Therefore, in the driving device 10B according to the second embodiment, the configuration for generating the short circuit detection signal Soc is different from that in the first embodiment (the driving device 10A). It is the same as the first embodiment.
  • the short circuit detection circuit 600B includes resistor elements 601, 603, 604, a diode 602, a capacitor 605, a power source 608, and a comparator 609 similar to the short circuit detection circuit 600A (FIG. 2), in addition to a capacitor 606 and an N-type transistor. and a switching element 607 composed of:
  • a capacitor 606 and a switching element 607 are connected in series between the node N2 and the negative power supply node Nn.
  • a selection signal S1 from the selection circuit 300A is input to the gate of the N-type transistor that constitutes the switching element 607 .
  • the capacitance of the node N2 is switched according to whether the switching element 607 is turned on or off. Specifically, during the turn-on period in which switching element 607 is turned on, the sum of the capacitances of capacitors 605 and 606 is added to node N2.
  • the sum of the capacitances of capacitors 605 and 606 in the second embodiment is designed to be equal to the capacitance of capacitor 606 in the first embodiment.
  • the resistor elements 603 and 604 and the capacitor 605 alone or both of the capacitors 605 and 606 form a "filter circuit" that receives the voltage of the node N1 as an input voltage.
  • the time constant of the filter circuit that generates the voltage Vsig of the node N2 from the drain voltage Vds is switched between the turn-on period and the steady-on period so that the time constant of the filter circuit is smaller than the turn-on period during the steady-on period.
  • the slope of the voltage Vsig input to the comparator 609 rising in conjunction with the drain voltage Vds is greater during the steady ON period than during the turn ON period.
  • FIG. 6 shows an operation waveform diagram when the semiconductor element is turned on by the driving device according to the second embodiment.
  • the normal waveforms are indicated by solid lines, and the waveforms when a short circuit occurs are indicated by dotted lines.
  • the short-circuit detection signal Soc (FIG. 5) is set to the H level, and after time t5, the semiconductor element 5 is turned off by applying a soft cutoff in the same manner as after time t5 in FIG. .
  • ⁇ T1 in FIG. 6 is shorter than ⁇ T0 in FIG. 3 due to the difference in the rate of increase of the voltage Vsig. That is, in the second embodiment, as compared with the first embodiment, it is possible to detect the occurrence of a short-circuit state early and activate soft cutoff.
  • FIG. 7 shows a flowchart for explaining the control process of the driving method of the semiconductor element 5 by the driving device 10B according to the second embodiment.
  • the driving device 10B differs in that it further executes the processing of S210 in addition to the control processing by the driving device 10A shown in FIG.
  • the determination in S120 is NO, that is, when the short-circuit state is not detected even after the delay time TX by the delay circuit 200A has elapsed from the start of the turn-on operation
  • the drive device 10B executes S210 and then performs the steps shown in FIG. Similar processing of S130 to S170 is executed.
  • the driving device 10B changes the short-circuit state detection condition by turning off the switching element 607 of the short-circuit detection circuit 600B at the transition timing (time t2 in FIG. 6) from the turn-on period to the steady-on period.
  • the rate of increase of the voltage Vsig in the short-circuit detection circuit 600B is increased. can.
  • the drain voltage Vds increases with a delay of the increase in the drain current Id.
  • the cut-off energy will increase. For this reason, it is desirable to detect the short circuit state as early as possible and suppress the energy required to cut off the short circuit during the steady-on state in which a large current is to be cut off.
  • the filter circuit that generates the input (voltage Vsig) to the comparator 609 of the short-circuit detection circuit 600B is turned on.
  • the configuration for switching the time constant of the filter circuit ie, the rate of increase of the voltage Vsig, is switched by switching the capacitance value added to the node N2.
  • a similar effect can be achieved by switching the value of .
  • FIG. 8 is a circuit diagram illustrating a specific configuration of the driving device 10C according to the third embodiment.
  • drive device 10C includes drive circuit 100A, delay circuit 200A, selection circuit 300A, and protection circuit 400C.
  • the drive circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400C are examples of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.
  • the drive device 10C differs from the drive device 10A shown in FIG. 2 in that it includes a protection circuit 400C instead of the protection circuit 400A.
  • the protection circuit 400C differs from the protection circuit 400A of FIG. 2 in that it includes a short circuit detection circuit 600C instead of the short circuit detection circuit 600A. Therefore, the driving device 10C according to the third embodiment also differs from the first embodiment (the driving device 10A) in the configuration for generating the short circuit detection signal Soc. , are the same as those in the first embodiment.
  • the short circuit detection circuit 600C includes resistance elements 601, 603, 604, a diode 602, a capacitor 605, and a comparator 609 similar to the short circuit detection circuit 600A (FIG. 2), as well as resistance elements 610 to 612 and an N-type transistor. and a switching element 613 composed of: On the other hand, in the short detection circuit 600C, the power supply 608 in FIG. 2 is not arranged.
  • the resistance element 610 is connected between the power supply node Np and the node N3 where the determination voltage Vt is generated.
  • Resistance element 611 is connected between node N3 and negative power supply node Nn.
  • Resistive element 612 and switching element 613 are connected in series between node N3 and negative power supply node Nn.
  • a selection signal S2 from the selection circuit 300B is input to the gate of the N-type transistor forming the switching element 613 .
  • the short-circuit detection circuit 600C differs from the short-circuit detection circuit 600A in FIG. 2 in that the determination voltage Vt is not a constant voltage from the power supply 608 but is switched between the turn-on period and the steady-on period.
  • the determination voltage Vt is switched by switching the voltage division ratio according to whether the switching element 613 is turned on or off. Specifically, since the switching element 613 is turned off during the turn-on period, the determination voltage Vt is generated by dividing (V1 ⁇ V2) by the resistance elements 610 and 611 .
  • the voltage Vsig input to the comparator 609 (+ terminal) is generated with the same configuration as the short circuit detection circuit 600A in FIG.
  • FIG. 9 shows an operation waveform diagram when the semiconductor element is turned on by the driving device according to the second embodiment.
  • the normal waveforms of the changes in the voltage and current during the turn-on operation according to the gate signal Sg are indicated by solid lines, and the waveforms when a short circuit occurs are indicated by dotted lines. shown.
  • the short circuit detection circuit 600C detects Vsig>Vt.
  • the short-circuit detection signal Soc (FIG. 5) is set to the H level, and after time t5, the semiconductor element 5 is turned off by applying a soft cutoff in the same manner as after time t5 in FIG. be.
  • the driving method of the semiconductor device 5 by the driving device 10C according to the third embodiment uses the same flowchart of FIG. can be realized by turning on the switching element 613 of the short circuit detection circuit 600C in S210.
  • the drain voltage It is possible to increase the detection speed of a short-circuit condition with increasing Vds. As a result, the time until the short-circuit state is detected is shortened. Therefore, as in the second embodiment, the effect of the protection operation for suppressing the interruption energy due to the protection operation during the steady ON period and not destroying the semiconductor element 5. can increase
  • Embodiment 4 As another example of the method of detecting the short circuit state of the semiconductor element 5, a configuration for detecting the short circuit state based on the drain current Id will be described.
  • FIG. 10 is a circuit diagram illustrating the configuration of a drive device 10D according to the fourth embodiment.
  • drive device 10D includes a drive circuit 100A, a delay circuit 200A, a selection circuit 300A and a protection circuit 400D.
  • the drive circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400D correspond to examples of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.
  • the drive device 10D differs from the drive device 10A shown in FIG. 2 in that it includes a protection circuit 400D instead of the protection circuit 400A.
  • Protection circuit 400D differs from protection circuit 400A in FIG. 2 in that short circuit detection circuit 700 is included instead of short circuit detection circuit 600A.
  • the driving device 10D differs from the first embodiment (the driving device 10A) in the configuration for generating the short-circuit detection signal Soc.
  • the short circuit detection circuit 700 includes a resistive element 702 , an amplifier 703 , a power supply 704 that outputs a determination voltage Vt, and a comparator 705 .
  • a sense cell 701 for detecting drain current is connected in parallel with the semiconductor element 5 .
  • the gate of the sense cell 701 is connected to the gate of the semiconductor element 5, and a sense current Idsn proportional to the drain current Id of the semiconductor element 5 flows through the sense cell 701 (Idsn ⁇ Id).
  • the resistance element 702 is connected in series with the sense cell 701 so that the sense current Idsn passes through it.
  • a sense current Idsn that is, a voltage Vdsn proportional to the drain current Id is generated across the resistance element 702 .
  • Amplifier 703 amplifies voltage Vdsn across resistance element 702 and outputs voltage Vsig. As a result, the voltage Vsig is also proportional to the drain current Id.
  • the resistive element 702 and the amplifier 703 can constitute an embodiment of the "voltage converter".
  • the comparator 705 Similar to the comparator 609 (FIG. 2), the comparator 705 generates the short circuit detection signal Soc based on the comparison result between the voltage Vsig and the determination voltage Vt. As a result, when Vsig>Vt, a short-circuit state in which an overcurrent occurs in the semiconductor element 5 is detected, and the short-circuit detection signal Soc is set to H level.
  • the protection operation in response to short-circuit detection signal Soc is similar to that of the first embodiment, and therefore detailed description will not be repeated.
  • Embodiment 4 is combined with Embodiment 1 to detect a short-circuit state based on the drain current, but Embodiment 3 can also be combined with Embodiment 4.
  • the third and fourth embodiments can be combined by generating the determination voltage Vt in the same manner as in the third embodiment.
  • Embodiment 5 Further, in the first to fourth embodiments, an example of classifying the driving state of the semiconductor element 5 based on the elapsed time from the turn-on start timing has been described, but other parameter values, such as gate voltage (Vgs) or gate From the current, it is also possible to distinguish between the driving state of the semiconductor element 5 related to protection control, that is, between the above-described turn-on period and steady-on period.
  • Vgs gate voltage
  • Vgs gate From the current
  • FIG. 11 is a circuit diagram illustrating a configuration example of a drive device 10E according to the fifth embodiment.
  • drive device 10E includes a drive circuit 100A, a delay circuit 200B, a selection circuit 300A and a protection circuit 400A.
  • the drive circuit 100A, the delay circuit 200B, the selection circuit 300A, and the protection circuit 400B correspond to examples of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.
  • the drive device 10E differs from the drive device 10A shown in FIG. 2 in that it includes a delay circuit 200B instead of the delay circuit 200A.
  • the delay circuit 200B generates the delay gate signal Sgd equivalent to that in FIG. 2 by a method different from that of the delay circuit 200A.
  • the driving device 10E according to the second embodiment differs from the first embodiment (the driving device 10A) in the configuration for generating the delayed gate signal Sgd for distinguishing between the turn-on period and the steady-on period. The rest of the configuration and the details of the protective operation during the turn-on period and the steady-on period are the same as those of the first embodiment.
  • the delay circuit 200B includes a comparator 215.
  • a comparator 215 outputs a delayed gate signal Sgd based on the comparison result between the gate voltage Vgs of the semiconductor element 5 and a reference value Vst corresponding to the output voltage of the power supply 212 .
  • the delay gate signal Sgd is input to the inverting buffer 301 and the non-inverting buffer 302 of the selection circuit 300A, as in the first embodiment.
  • the comparator 215 sets the delay gate signal Sgd to L level when Vgs ⁇ Vst, and to H level when Vgs>Vst.
  • FIG. 12 shows an operation waveform diagram when the semiconductor element is turned on by the driving device 10E shown in FIG. Solid and dotted waveforms of the drive voltage Vdv, gate voltage Vgs, drain current Id, drain voltage Vds, and voltage Vsig shown in FIG. 12 are the same as those shown in FIG. FIG. 12 differs from FIG. 3 in that transition of the delayed gate signal Sgd according to the gate voltage Vgs is shown.
  • the gate voltage Vgs starts changing from the second voltage V2 toward the first voltage V1 at the turn-on start timing (time t1) and rises to the first voltage V1 after the mirror period. .
  • the circuit operation in each of the turn-on period and the steady-on period is the same as in the first embodiment (driving device 10A) both in the normal state and in the occurrence of the short-circuit state. Therefore, detailed description will not be repeated.
  • the gate voltage Vgs changes due to the charging and discharging of the gate capacitance of the semiconductor element 5 due to the gate current Ig shown in FIG. Therefore, it is also possible to divide the turn-on period and the steady-on period according to the drive state of the semiconductor element 5 .
  • an input voltage proportional to the gate current Ig is input to the comparator 215, and the reference value Vst is set according to the turn-on characteristics of the gate current Ig.
  • the delay circuit 200B shown in FIG. 10 can also be arranged in place of the delay circuit 200A in the second to fourth embodiments, and the fifth embodiment can be combined with the second to fourth embodiments. It is possible.
  • each circuit element described in this embodiment can be arbitrarily configured by at least one of hardware processing and software processing as long as it has equivalent functions.

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JP2012023899A (ja) * 2010-07-15 2012-02-02 Fuji Electric Co Ltd 電力用半導体素子のゲート駆動回路
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JPH06276073A (ja) * 1993-01-21 1994-09-30 Hitachi Ltd Ｉｇｂｔの過電流保護装置
JP2012023899A (ja) * 2010-07-15 2012-02-02 Fuji Electric Co Ltd 電力用半導体素子のゲート駆動回路
JP2013240210A (ja) * 2012-05-16 2013-11-28 Denso Corp 駆動対象スイッチング素子の駆動装置
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