WO2023115888A1 - Flash型fpga的基于逻辑工艺的电平转换电路 - Google Patents

Flash型fpga的基于逻辑工艺的电平转换电路 Download PDF

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Publication number
WO2023115888A1
WO2023115888A1 PCT/CN2022/102650 CN2022102650W WO2023115888A1 WO 2023115888 A1 WO2023115888 A1 WO 2023115888A1 CN 2022102650 W CN2022102650 W CN 2022102650W WO 2023115888 A1 WO2023115888 A1 WO 2023115888A1
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Prior art keywords
voltage
signal
gate
drain
conversion module
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PCT/CN2022/102650
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English (en)
French (fr)
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曹正州
单悦尔
季振凯
孙静
贺春燕
李光明
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无锡中微亿芯有限公司
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Priority to US17/940,001 priority Critical patent/US12015404B2/en
Publication of WO2023115888A1 publication Critical patent/WO2023115888A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources

Definitions

  • the invention relates to the field of flash FPGA, in particular to a logic technology-based level conversion circuit of the flash FPGA.
  • Flash-type FPGA is a programmable logic circuit based on flash memory technology.
  • the programmable wiring switch matrix is composed of flash memory cells (flash cells). Through the configuration of flash cells, different flash switch paths are selected to realize user-programmable logical function.
  • the flash-type FPGA has a fast startup speed, and the circuit can quickly enter the working state after power-on, so it has become the mainstream of programmable logic devices and is widely used in the field of signal processing and control.
  • the flash-type FPGA provides users with logic with system equivalent gates ranging from hundreds of thousands to millions of gates, the operating frequency is up to 350MHz, and a large number of IP cores are provided.
  • the flash-type FPGA must be designed and manufactured based on the logic process, and cannot be like Flash memory (flash memory) is designed and manufactured on a specific process.
  • the erasing and programming of the flash cell requires a relatively high voltage, and the low voltage (VDD) control logic of the core needs to be converted into the positive high voltage and negative high voltage required for erasing and programming.
  • the logic process line cannot provide devices with various required voltages like the flash memory-specific process, so the flash FPGA must be designed based on the breakdown voltage (break-down voltage) of the logic process device, which the logic process usually provides.
  • the maximum operating voltage of the device is 5V, and the break-down voltage is 12V.
  • the feature of flash FPGA is that the flash cell array is distributed in small pieces in the whole chip.
  • the wiring of word lines and bit lines is relatively long and the load is relatively large. , the size of the word line and the bit line is relatively large, which also requires a relatively large drive and a relatively fast switching speed for the front stage of the word line and the bit line (ie, the level conversion circuit).
  • the erasing and programming of the flash cell requires a relatively high voltage, and the low voltage (VDD) control logic of the core needs to be converted into the positive high voltage and negative high voltage required for erasing and programming.
  • the logic process line cannot provide devices with various required voltages like the flash memory-specific process, so the flash FPGA must be designed based on the breakdown voltage (break-down voltage) of the logic process device, which the logic process usually provides.
  • the maximum operating voltage of the device is 5V, and the break-down voltage is 12V.
  • the flash FPGA is characterized by flash The cell array is distributed in small pieces in the whole chip.
  • the wiring of word lines and bit lines is relatively long and the load is relatively large. In order to ensure the drive of word lines and bit lines, the size of word lines and bit lines
  • the design is relatively large, which also requires a relatively large drive and a relatively fast conversion speed for the front stage of the word line and the bit line (ie, the level conversion circuit).
  • the present inventor proposes a level conversion circuit based on a logic process of a flash type FPGA for the above-mentioned problems and technical requirements, and the technical scheme of the present invention is as follows:
  • a level conversion circuit based on logic technology of a flash type FPGA characterized in that the level conversion circuit includes sequentially cascaded first-level conversion modules, intermediate-level conversion modules and driver-level conversion modules;
  • the first-level conversion module is used to convert the first signal of the input VDD-GND voltage domain into the second signal of the VP1-GND voltage domain and output it to the intermediate-level conversion module;
  • the intermediate-level conversion module is used to convert the input VP1 -The second signal in the GND voltage domain is converted into the third signal in the VP1-VN voltage domain and output to the driver stage conversion module;
  • the driver stage conversion module is used to convert the input third signal in the VP1-VN voltage domain into VP2- The driving signal of the VN voltage domain, and output the word line driving the flash FPGA;
  • the voltage combination includes the core low voltage VDD provided by the logic process, the intermediate voltage VP1 provided by the logic process, and the driver level voltage VP2 provided by the logic process. and a negative voltage VN, wherein GND is a ground voltage, and VP2 ⁇ VP1 ⁇ VDD.
  • the driver stage conversion module when performing a programming operation on a flash FPGA, the voltage values of the core low voltage VDD, the intermediate voltage VP1 and the driving stage voltage VP2 provided by the control logic process increase sequentially, and the voltage value of the driving stage voltage VP2 For the positive high voltage HV required for flash memory cell programming, the driver stage conversion module outputs the driving signal in the VP2-VN voltage domain to control the word line to apply the positive high voltage HV to the gate terminal of the flash memory cell to complete the programming operation.
  • the voltage values of the intermediate voltage VP1 and the driving stage voltage VP2 provided by the control logic process are equal to the voltage value of the core low voltage VDD, and the negative voltage provided by the control logic process
  • the voltage VN is the negative high voltage LV required for erasing the flash memory cell.
  • the drive stage conversion module outputs the driving signal in the VP2-VN voltage domain to control the word line to apply the negative high voltage LV to the gate terminal of the flash memory cell to complete the erase. delete operation.
  • the intermediate stage conversion module and the driver stage conversion module are respectively provided with voltage divider switches for voltage division, and the voltage divider switches in the two conversion modules are controlled by the grid voltage control Signal, the gate voltage control signal has different voltage values at different periods of a working cycle of the level conversion circuit to adjust the state of the voltage divider switch and reduce the working time of the devices in the level conversion circuit under the breakdown voltage.
  • the second signal and the third signal are both differential signals
  • the sources of the PMOS transistors P3, P4, P5, and P6 are connected and connected to the drains of the intermediate voltage VP1 and P4 Connect the drain of NMOS transistor N3, the source of N3 is connected to the drain of NMOS transistor N5; the drain of P5 is connected to the drain of NMOS transistor N4, the source of N4 is connected to the drain of NMOS transistor N6; the source of N5 and N6
  • the source is connected and connected to the negative voltage VN;
  • the drain of P3, the gate of P4, the drain of P5 and the gate of N5 are all connected, the drain of P6, the gate of P5, the drain of P4 and the gate of N6
  • the poles are all connected, the gate of P3 and the gate of P6 are used as a pair of differential pairs to obtain the second signal, the gate of N5 and the gate of N6 are used as a pair of differential pairs to output the third signal; N3 and N
  • the third signal and the driving signal are both differential signals
  • the sources of PMOS transistors P7 and P8 are connected to the driving stage voltage VP2
  • the drain of P7 is connected to the gate of P8 pole and the drain of NMOS transistor N7
  • the drain of P8 is connected to the gate of P7 and the drain of NMOS transistor N8
  • the source of N7 is connected to the drain of NMOS transistor N9
  • the source of N8 is connected to the drain of NMOS transistor N10
  • the source of N9 is connected to the source of N10 and connected to the negative voltage VN
  • the gate of N9 and the gate of N10 are used as a pair of differential pairs to obtain the third signal
  • the drain of N7 and the drain of N8 are used as a pair of differential
  • N7 and N8 are used as voltage divider switches in the drive stage conversion module
  • the gate of N7 is connected to the gate of N8 and is controlled by the gate voltage control signal.
  • the working cycle includes a level conversion phase and a maintenance phase in turn, and the level conversion phase is used to complete signals in different voltage domains.
  • the maintenance phase is used to maintain the state of the signal; in the maintenance phase of the work cycle, the voltage value of the gate voltage control signal is a negative voltage VN, and the voltage divider switches N3 and N4 in the intermediate conversion module are turned off, driving The voltage divider switches N7 and N8 in the level conversion module are turned off.
  • the state of the level conversion circuit is maintained by the voltage of the parasitic capacitance of the circuit without pull-down drive.
  • the charge on the parasitic capacitance maintains data but is smaller than the breakdown of the device voltage to protect P3, P4, P5 and P6 in the intermediate stage conversion module, and to protect P7 and P8 in the driver stage conversion module;
  • the parasitic capacitance in the intermediate stage conversion module includes the parasitic capacitance between P4 and N3 and the parasitic capacitance between P5 and N4 in the intermediate stage conversion module, and the parasitic capacitance in the driver stage conversion module includes P7 and N7 The parasitic capacitance between and the parasitic capacitance between P8 and N8.
  • the duration of the sustain phase is longer than the duration of the level conversion phase.
  • the first signal is a single-ended signal
  • the second signal is a differential signal.
  • the sources of PMOS transistors P1 and P2 are connected and connected to the intermediate voltage VP1, and the drain of P1
  • the gate of P2 is connected to the drain of NMOS transistor N1
  • the drain of P2 is connected to the gate of P1 and the drain of NMOS transistor N2
  • the source of N1 is connected to the source of N2 and connected to GND;
  • the source of the PMOS transistor P0 is connected to the core low voltage VDD, the drain of P0 is connected to the drain of the NMOS transistor N0, the source of N0 is connected to GND, the gate of P0 is connected to the gate of N0 to obtain the first signal, and the drain of P0
  • the pole outputs the inverse signal of the first signal and is connected to the gate of N1, and the gate of N2 obtains the first signal; the drain of P1 and the drain of P2 output the second signal as a differential pair.
  • This application discloses a level conversion circuit based on a logic process of a flash FPGA.
  • the level conversion circuit performs three-level level conversion through three conversion modules, and first converts to an intermediate voltage, and then converts to the highest voltage, reducing the The pressure of each level of conversion is reduced, the ability to drive the next level is guaranteed, the conversion speed is improved, and the last level provides a greater driving capacity.
  • the voltage divider switch tube is connected in series in the level conversion circuit to divide the voltage.
  • the timing control of the gate voltage control signal reduces the working time of the device under the breakdown voltage, thereby improving the reliability of the device.
  • FIG. 1 is a circuit diagram of a level shifting circuit in one embodiment.
  • FIG. 2 is a schematic diagram of voltage domain conversion of signals in the level conversion circuit of the present application when performing a programming operation on a flash FPGA.
  • FIG. 3 is a schematic diagram of voltage domain conversion of signals in the level conversion circuit of the present application when performing an erasing operation on a flash FPGA.
  • FIG. 4 is a schematic waveform diagram of the first signal, the second signal, the third signal, the fourth signal and the gate voltage control signal in the level conversion circuit of the present application.
  • the level conversion circuit includes sequentially cascaded first-level conversion modules, intermediate-level conversion modules and driver-level conversion mod.
  • the first-level conversion module is used to convert the input first signal Sig1 in the VDD-GND voltage domain into a second signal Sig2 in the VP1-GND voltage domain and output it to the intermediate-level conversion module.
  • the intermediate stage conversion module is used to convert the input second signal Sig2 in the VP1-GND voltage domain into a third signal Sig3 in the VP1-VN voltage domain and output it to the driving stage conversion module.
  • the driving stage conversion module is used to convert the input third signal Sig3 in the VP1-VN voltage domain into the driving signal Sig4 in the VP2-VN voltage domain, and output the word line for driving the flash FPGA.
  • the size of the devices in the driver stage conversion module is relatively large to ensure the driving capability.
  • the voltage combination includes the core low voltage VDD provided by the logic process, the intermediate voltage VP1 provided by the logic process, and the The driving stage voltage VP2 and the negative voltage VN.
  • VP2 ⁇ VP1 ⁇ VDD the negative voltage
  • GND means that the ground voltage is at zero level, and VN ⁇ 0.
  • the voltage values of the core low voltage VDD, the intermediate voltage VP1 and the driving stage voltage VP2 provided by the control logic process increase sequentially, VDD ⁇ VP1 ⁇ VP2.
  • the voltage domain relationship of each signal is shown in FIG. 2 .
  • the driving stage conversion module outputs the driving signal Sig4 in the VP2-VN voltage domain to control the word line to apply the positive high voltage HV to the gate terminal of the flash memory cell to complete the programming operation.
  • the output driving signal Sig4 controls the word line to apply 8.8V to the gate terminal of the flash memory unit.
  • the driving stage conversion module outputs the driving signal Sig4 in the VP2-VN voltage domain to control the word line to apply the negative high voltage LV to the gate terminal of the flash memory cell to complete the erasing operation.
  • the control word line applies -9.5V to the gate terminal of the flash memory cell.
  • the three-level level conversion is carried out through three conversion modules, firstly converted to the intermediate voltage, and then converted to the highest voltage, which reduces the pressure of each level of conversion, ensures the ability to drive the next level, improves the conversion speed, and The last stage provides greater drive capacity.
  • the input first signal Sig1 is a single-ended signal
  • the second signal Sig2 , the third signal Sig3 and the driving signal Sig4 are all differential signals.
  • the sources of PMOS transistors P1 and P2 are connected to the intermediate voltage VP1
  • the drain of P1 is connected to the gate of P2 and the drain of NMOS transistor N1
  • the drain of P2 The drain is connected to the gate of P1 and the drain of NMOS transistor N2
  • the source of N1 is connected to the source of N2 and connected to GND.
  • P1, P2, N1, N2 form a positive feedback structure of differential input.
  • the source of the PMOS transistor P0 is connected to the core low voltage VDD, the drain of P0 is connected to the drain of the NMOS transistor N0, the source of N0 is connected to GND, and the gate of P0 is connected to the gate of N0 to obtain the first signal Sig1.
  • P0 and N0 form an inverter, and the drain of P0 outputs the inverted signal Sig1_N of the first signal Sig1 and is connected to the gate of N1.
  • the gate of N2 acquires the first signal Sig1.
  • the drain of P1 and the drain of P2 output the second signal Sig2 as a differential pair, including Sig2_P and Sig2_N, the drain of P1 outputs Sig2_P which is in phase with the first signal Sig1, and the drain of P2 outputs Sig2_N.
  • the intermediate conversion module and the driver conversion module mainly include a differential input positive feedback structure, and the differential input positive feedback structure in the intermediate conversion module is respectively connected to the intermediate voltage VP1 and the negative voltage VN.
  • the positive feedback structure of the differential input of the driver stage conversion module is respectively connected to the driver stage voltage VP2 and the negative voltage VN.
  • the intermediate stage conversion module and the driver stage conversion module are respectively provided with voltage divider switches for voltage division, and the voltage divider switches in the two conversion modules are controlled by the gate voltage control signal V_CHG, the gate voltage control signal V_CHG has different voltage values in different periods of a working cycle of the level shifting circuit, so as to adjust the state of the voltage divider switch and reduce the working time of the devices in the level shifting circuit under the breakdown voltage. The reliability of devices in the level conversion circuit is thereby improved.
  • the sources of PMOS transistors P3, P4, P5, and P6 are connected to the intermediate voltage VP1
  • the drain of P4 is connected to the drain of NMOS transistor N3, and the source of N3 is connected to The drain of NMOS transistor N5.
  • the drain of P5 is connected to the drain of NMOS transistor N4, and the source of N4 is connected to the drain of NMOS transistor N6.
  • the source of N5 is connected to the source of N6 and connected to the negative voltage VN.
  • the drain of P3, the gate of P4, the drain of P5 and the gate of N5 are all connected, and the drain of P6, the gate of P5, the drain of P4 and the gate of N6 are all connected.
  • the gate of P3 and the gate of P6 are used as a differential pair to obtain the second signal Sig2, the gate of P3 is connected to the drain of P1 to obtain Sig2_P, and the gate of P6 is connected to the drain of P2 to obtain Sig2_N.
  • the gate of N5 and the gate of N6 are used as a differential pair to output the third signal Sig3 including Sig3_P and Sig3_N, the gate of N6 outputs Sig3_P which is in phase with the first signal Sig1, and the gate of N5 outputs another Sig3_N.
  • N3 and N4 are used as voltage-dividing switch tubes in the intermediate conversion module, and the gate of N3 is connected to the gate of N4 and is controlled by the gate voltage control signal V_CHG.
  • the sources of PMOS transistors P7 and P8 are connected to the driver stage voltage VP2
  • the drain of P7 is connected to the gate of P8 and the drain of NMOS transistor N7
  • the drain of P8 is connected to the gate of P7
  • the drain of NMOS transistor N8 is connected to the source of NMOS transistor N9
  • the source of N8 is connected to the drain of NMOS transistor N10
  • the source of N9 is connected to the source of N10 and connected to the negative voltage VN.
  • the gate of N9 and the gate of N10 are used as a differential pair to obtain the third signal Sig3, the gate of N9 is connected to the gate of N6 to obtain Sig3_P, and the gate of N10 is connected to the gate of N5 to obtain Sig3_N.
  • the drain of N7 and the drain of N8 are used as a pair of differential pairs to output the driving signal Sig4 including Sig4_P and Sig4_N, the drain of N8 outputs Sig4_P which is in phase with the first signal Sig1, and the drain of N7 outputs another Sig4_N.
  • N7 and N8 are used as voltage divider switches in the drive stage conversion module.
  • the gate of N7 is connected to the gate of N8 and is controlled by the gate voltage control signal V_CHG.
  • the working cycle includes a level conversion stage and a maintenance phase in turn.
  • the level conversion phase is used to complete the conversion of signals in different voltage domains, and the maintenance phase is used to maintain the state of the signal.
  • the voltage value of the gate voltage control signal V_CHG is equal to the intermediate voltage VP1, and when performing the programming operation, VDD ⁇ VP1 ⁇ VP2.
  • the positive high voltage HV in the drive stage conversion module cannot be transmitted to N9 and N10 due to the clamping of the voltage divider switch tubes N7 and N8.
  • the voltage difference between the gate, source and drain of N7, N8, N9 and N10 are smaller, and the safety voltage tolerances of N7, N8, N9, and N10 are increased.
  • the voltage value of the gate voltage control signal V_CHG is a negative voltage VN
  • the voltage divider switches N3 and N4 in the intermediate stage conversion module are turned off, and the drive stage conversion module
  • the voltage divider switches N7 and N8 are turned off.
  • the state of the level conversion circuit is maintained by the voltage of the parasitic capacitors C0, C1, C2, and C3 of the circuit without pull-down drive.
  • the charges on the parasitic capacitors C0, C1, C2, and C3 retain data but are less than the breakdown voltage of the device.
  • the parasitic capacitance in the intermediate conversion module includes a parasitic capacitance C0 between P4 and N3 and a parasitic capacitance C1 between P5 and N4 in the intermediate conversion module.
  • the parasitic capacitance C2 in the driver stage conversion module includes the parasitic capacitance between P7 and N7 and the parasitic capacitance C3 between P8 and N8.
  • the working cycle includes a level conversion stage and a maintenance phase in turn.
  • the level conversion phase is used to complete the conversion of signals in different voltage domains, and the maintenance phase is used to maintain the state of the signal. .
  • the voltage divider switches N3 and N4 in the intermediate conversion module are turned off, and the voltage divider switches N7 and N8 in the driver conversion module are turned off.
  • the state of the level conversion circuit is maintained by the voltage of the parasitic capacitors C0, C1, C2, and C3 of the circuit without pull-down drive.
  • the charges on the parasitic capacitors C0, C1, C2, and C3 retain data but are less than the breakdown voltage of the device.
  • the duration of the level conversion phase and the maintenance phase is set according to the actual situation. Generally, the duration of the level conversion phase is set to complete the conversion of the voltage domain of the signal and drive the word line circuit, and then add a certain design margin to determine the voltage. After the duration of the conversion phase is equalized, the remaining duration of a duty cycle is the maintenance phase. According to the actual simulation results, the longest time to complete the transition of the voltage domain of the signal is about 1.5us, so the level conversion stage can be set to 2us. If a working cycle has a total of 10us, the duration of the maintenance stage is 8us. In this example, it is also possible to set the level conversion phase to be 3us, and the duration of the sustaining phase to be 7us. But generally, in any working cycle, the duration of the sustain phase is longer than the duration of the level conversion phase, please refer to the waveform comparison schematic diagram shown in FIG. 4 .
  • VDD 1.5V
  • VP1 3.6V
  • VP2 8.8V
  • VN -2.5V
  • the voltage difference between VP2 and VN is 11.3V
  • the safe voltage margin of 12V from the breakdown voltage of a 5V device is 0.7V.
  • the gate terminal voltages of N3, N4, N7, and N8 are controlled by the gate voltage control signal V_CHG.
  • the 8.8V of VP2 cannot be transmitted to N9 and N10 due to the clamping of N7 and N8 in series.
  • VN -9.5V.
  • the differential pressure between VP2 and VN is 11 V, a safe voltage margin of 1V from the breakdown voltage of a 5V device 12V.
  • the gate terminal voltages of N3, N4, N7, and N8 are controlled by the gate voltage control signal V_CHG.
  • N3, N4, N7, and N8 are in the off state, thereby protecting P3, P4, P5, P6, P7, and P8 .

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Abstract

本发明公开了一种flash型FPGA的基于逻辑工艺的电平转换电路，涉及flash型FPGA领域，该电平转换电路通过三个转换模组进行三级电平转换，第一级转换模组用于将输入的VDD-GND电压域的第一信号转换为VP1-GND电压域的第二信号，中间级转换模组用于将输入的VP1-GND电压域的第二信号转换为VP1-VN电压域的第三信号，驱动级转换模组用于将输入的VP1-VN电压域的第三信号转换为VP2-VN电压域的驱动信号，并输出驱动的字线，降低了每级转换的压力，保证了驱动下一级的能力，提高了转换速度，并且最后一级提供了较大的驱动能力。

Description

flash型FPGA的基于逻辑工艺的电平转换电路 技术领域
本发明涉及flash型FPGA领域，尤其是一种flash型FPGA的基于逻辑工艺的电平转换电路。
 背景技术
flash型FPGA是基于flash存储技术的可编程逻辑电路，由flash存储单元（flash cell）构成可编程的布线开关矩阵，通过对flash cell的配置，选择不同的flash开关通路，从而实现用户的可编程逻辑功能。
flash型FPGA启动速度快，上电后电路能够快速的进入工作状态，所以成为了可编程逻辑器件的主流，广泛应用于信号处理和控制领域。flash型FPGA为用户提供系统等效门数从几十万到几百万门的逻辑，工作频率最高达350MHz，并且提供大量IP核，flash型FPGA必须基于逻辑工艺进行设计和制造，而不能像flash存储器（flash memory）在特定的工艺上进行设计和制造。
flash cell的擦除和编程需要比较高的电压，需要将内核的低电压（VDD）控制逻辑转换成擦除和编程所需的正高电压、负高电压。而逻辑工艺线不能像flash存储器特定的工艺那样提供各种所需电压的器件，所以flash型FPGA必须采用基于逻辑工艺器件的击穿电压（break-down电压）进行设计，逻辑工艺通常所能提供器件的最高工作电压为5V，break-down电压在12V。同时flash型FPGA的特点是flash cell阵列在整个芯片中是按一小块一小块的分散布局，字线和位线的走线比较长、负载比较大，为了保证字线和位线的驱动，字线和位线的尺寸设计的比较大，这也需要字线和位线的前级（即电平转换电路）有比较大的驱动和比较快的转换速度。
 技术问题
flash cell的擦除和编程需要比较高的电压，需要将内核的低电压（VDD）控制逻辑转换成擦除和编程所需的正高电压、负高电压。而逻辑工艺线不能像flash存储器特定的工艺那样提供各种所需电压的器件，所以flash型FPGA必须采用基于逻辑工艺器件的击穿电压（break-down电压）进行设计，逻辑工艺通常所能提供器件的最高工作电压为5V，break-down电压在12V。同时flash型FPGA的特点是flash cell阵列在整个芯片中是按一小块一小块的分散布局，字线和位线的走线比较长、负载比较大，为了保证字线和位线的驱动，字线和位线的尺寸设计的比较大，这也需要字线和位线的前级（即电平转换电路）有比较大的驱动和比较快的转换速度。
 技术解决方案
本发明人针对上述问题及技术需求，提出了一种flash型FPGA的基于逻辑工艺的电平转换电路，本发明的技术方案如下：
一种flash型FPGA的基于逻辑工艺的电平转换电路，其特征在于，电平转换电路包括依次级联的第一级转换模组、中间级转换模组和驱动级转换模组；
第一级转换模组用于将输入的VDD-GND电压域的第一信号转换为VP1-GND电压域的第二信号输出给中间级转换模组；中间级转换模组用于将输入的VP1-GND电压域的第二信号转换为VP1-VN电压域的第三信号输出给驱动级转换模组；驱动级转换模组用于将输入的VP1-VN电压域的第三信号转换为VP2-VN电压域的驱动信号，并输出驱动flash型FPGA的字线；
控制逻辑工艺输出对应的电压组合以完成对flash型FPGA的擦除操作或编程操作，电压组合包括逻辑工艺提供的内核低电压VDD、逻辑工艺提供的中间电压VP1、逻辑工艺提供的驱动级电压VP2以及负电压VN，其中，GND为接地电压，VP2≥VP1≥VDD。
其进一步的技术方案为，在对flash型FPGA执行编程操作时，控制逻辑工艺提供的内核低电压VDD、中间电压VP1和驱动级电压VP2的电压值依次升高，且驱动级电压VP2的电压值为flash存储单元编程所需的正高电压HV，驱动级转换模组输出VP2-VN电压域的驱动信号控制字线将正高电压HV施加到flash存储单元的栅端，以完成编程操作。
其进一步的技术方案为，在对flash型FPGA执行擦除操作时，控制逻辑工艺提供的中间电压VP1和驱动级电压VP2的电压值与内核低电压VDD的电压值相等，控制逻辑工艺提供的负电压VN为flash存储单元擦除所需的负高电压LV，驱动级转换模组输出VP2-VN电压域的驱动信号控制字线将负高电压LV施加到flash存储单元的栅端，以完成擦除操作。
其进一步的技术方案为，中间级转换模组和驱动级转换模组中分别设置有用于分压的分压开关管，且两个转换模组中的分压开关管均受控于栅压控制信号，栅压控制信号在电平转换电路的一个工作周期的不同时段为不同的电压值，以调节分压开关管的状态，减少电平转换电路中的器件在击穿电压下的工作时长。
其进一步的技术方案为，第二信号和第三信号均为差分信号，在中间级转换模组中，PMOS管P3、P4、P5、P6的源极相连并连接中间电压VP1，P4的漏极连接NMOS管N3的漏极，N3的源极连接NMOS管N5的漏极；P5的漏极连接NMOS管N4的漏极，N4的源极连接NMOS管N6的漏极；N5的源极和N6的源极相连并连接负电压VN；P3的漏极、P4的栅极、P5的漏极以及N5的栅极均相连，P6的漏极、P5的栅极、P4的漏极以及N6的栅极均相连，P3的栅极和P6的栅极作为一对差分对用于获取第二信号，N5的栅极和N6的栅极作为一对差分对用于输出第三信号；N3和N4作为中间级转换模组中的分压开关管，N3的栅极和N4的栅极相连并受控于栅压控制信号。
其进一步的技术方案为，第三信号和驱动信号均为差分信号，在驱动级转换模组中，PMOS管P7和P8的源极相连并连接驱动级电压VP2，P7的漏极连接P8的栅极以及NMOS管N7的漏极，P8的漏极连接P7的栅极以及NMOS管N8的漏极，N7的源极连接NMOS管N9的漏极，N8的源极连接NMOS管N10的漏极，N9的源极和N10的源极相连并连接负电压VN；N9的栅极和N10的栅极作为一对差分对用于获取第三信号，N7的漏极和N8的漏极作为一对差分对用于输出驱动信号；N7和N8作为驱动级转换模组中的分压开关管，N7的栅极和N8的栅极相连并受控于栅压控制信号。
其进一步的技术方案为，在对flash型FPGA执行编程操作或擦除操作的任意一个工作周期内，工作周期依次包括电平转换阶段和维持阶段，电平转换阶段用于完成不同电压域的信号的转换，维持阶段用于维持信号的状态；在工作周期的维持阶段内，栅压控制信号的电压值为负电压VN，中间级转换模组中的分压开关管N3和N4关断，驱动级转换模组中的分压开关管N7和N8关断，电平转换电路的状态依靠电路的寄生电容的电压来保持而没有下拉驱动，寄生电容上存在的电荷保持数据但小于器件的击穿电压，以保护中间级转换模组中的P3、P4、P5和P6，以及保护驱动级转换模组中的P7和P8；
其中，中间级转换模组中的寄生电容包括中间级转换模组中的P4和N3之间的寄生电容以及P5和N4之间的寄生电容，驱动级转换模组中的寄生电容包括P7和N7之间的寄生电容以及P8和N8之间的寄生电容。
其进一步的技术方案为，在对flash型FPGA执行编程操作或擦除操作的任意一个工作周期内，在工作周期开始的电平转换阶段内，栅压控制信号的电压值等于中间电压VP1；则在对flash型FPGA执行编程操作时，驱动级转换模组中的正高电压HV由于分压开关管N7和N8的钳位而不能传递到N9和N10上，提高N7、N8、N9、N10的安全电压容限。
其进一步的技术方案为，在任意一个工作周期内，维持阶段的时长大于电平转换阶段的时长。
其进一步的技术方案为，第一信号为单端信号，第二信号为差分信号，在第一级转换模组中，PMOS管P1和P2的源极相连并连接中间电压VP1，P1的漏极连接P2的栅极和NMOS管N1的漏极，P2的漏极连接P1的栅极和NMOS管N2的漏极，N1的源极和N2的源极相连并连接GND；
PMOS管P0的源极连接内核低电压VDD，P0的漏极连接NMOS管N0的漏极，N0的源极连接GND，P0的栅极和N0的栅极相连并获取第一信号，P0的漏极输出第一信号的反相信号并连接N1的栅极，N2的栅极获取第一信号；P1的漏极和P2的漏极作为一对差分对输出第二信号。
 有益效果
本申请公开了一种flash型FPGA的基于逻辑工艺的电平转换电路，该电平转换电路通过三个转换模组进行三级电平转换，先转换到中间电压，再转换到最高电压，降低了每级转换的压力，保证了驱动下一级的能力，提高了转换速度，并且最后一级提供了较大的驱动能力。
另外，考虑到电平转换电路是基于器件的击穿电压进行设计的，而器件不能长时间工作在击穿电压下，因此在电平转换电路中串联分压开关管进行分压，同时结合对栅压控制信号进行时序控制，减少器件在击穿电压下的工作时间，从而提高了器件的可靠性。
 附图说明
图1是一个实施例中的电平转换电路的电路图。
图2是在对flash型FPGA执行编程操作时，本申请的电平转换电路中的信号的电压域转换示意图。
图3是在对flash型FPGA执行擦除操作时，本申请的电平转换电路中的信号的电压域转换示意图。
图4是本申请的电平转换电路中的第一信号、第二信号、第三信号、第四信号以及栅压控制信号的波形示意图。
 本发明的实施方式
下面结合附图对本发明的具体实施方式做进一步说明。
本申请公开了一种flash型FPGA的基于逻辑工艺的电平转换电路，请参考图1，该电平转换电路包括依次级联的第一级转换模组、中间级转换模组和驱动级转换模组。第一级转换模组用于将输入的VDD-GND电压域的第一信号Sig1转换为VP1-GND电压域的第二信号Sig2输出给中间级转换模组。中间级转换模组用于将输入的VP1-GND电压域的第二信号Sig2转换为VP1-VN电压域的第三信号Sig3输出给驱动级转换模组。驱动级转换模组用于将输入的VP1-VN电压域的第三信号Sig3转换为VP2-VN电压域的驱动信号Sig4，并输出驱动flash型FPGA的字线。驱动级转换模组中的器件的尺寸都较大，以保证驱动能力。
在工作过程中，控制逻辑工艺输出对应的电压组合以完成对flash型FPGA的擦除操作或编程操作，电压组合包括逻辑工艺提供的内核低电压VDD、逻辑工艺提供的中间电压VP1、逻辑工艺提供的驱动级电压VP2以及负电压VN。VP2≥VP1≥VDD。其中，GND为接地电压为零电平，VN＜0。
在对flash型FPGA执行编程操作时，控制逻辑工艺提供的内核低电压VDD、中间电压VP1和驱动级电压VP2的电压值依次升高，VDD<VP1<VP2。且驱动级电压VP2的电压值为flash存储单元编程所需的正高电压HV，VP2=HV。则各路信号的电压域关系如图2所示。在这种状态下，驱动级转换模组输出VP2-VN电压域的驱动信号Sig4控制字线将正高电压HV施加到flash存储单元的栅端，以完成编程操作。比如典型的，flash存储单元编程所需的正高电压HV=8.8V，则可以控制VDD=1.5V，VP1=3.6V，VP2=8.8V，VN=-2.5V，则此时驱动级转换模组输出驱动信号Sig4控制字线将8.8V施加到flash存储单元的栅端。
在对flash型FPGA执行擦除操作时，控制逻辑工艺提供的中间电压VP1和驱动级电压VP2的电压值与内核低电压VDD的电压值相等，VDD=VP1=VP2。控制逻辑工艺提供的负电压VN为flash存储单元擦除所需的负高电压LV，VN=LV。则各路信号的电压域关系如图3所示。在这种状态下，驱动级转换模组输出VP2-VN电压域的驱动信号Sig4控制字线将负高电压LV施加到flash存储单元的栅端，以完成擦除操作。比如典型的，flash存储单元编程所需的负高电压LV=-9.5V，则可以控制VDD= VP1= VP2=1.5V，VN=-9.5V，则此时驱动级转换模组输出驱动信号Sig4控制字线将-9.5V施加到flash存储单元的栅端。
由此通过三个转换模组进行三级电平转换，先转换到中间电压，再转换到最高电压，降低了每级转换的压力，保证了驱动下一级的能力，提高了转换速度，并且最后一级提供了较大的驱动能力。
在一个实施例中，输入的第一信号Sig1为单端信号，第二信号Sig2、第三信号Sig3和驱动信号Sig4均为差分信号。则如图1所示，在第一级转换模组中，PMOS管P1和P2的源极相连并连接中间电压VP1，P1的漏极连接P2的栅极和NMOS管N1的漏极，P2的漏极连接P1的栅极和NMOS管N2的漏极，N1的源极和N2的源极相连并连接GND。P1、P2、N1、N2构成差分输入的正反馈结构。PMOS管P0的源极连接内核低电压VDD，P0的漏极连接NMOS管N0的漏极，N0的源极连接GND，P0的栅极和N0的栅极相连并获取第一信号Sig1。P0和N0构成反相器，P0的漏极输出第一信号Sig1的反相信号Sig1_N并连接N1的栅极。N2的栅极获取第一信号Sig1。P1的漏极和P2的漏极作为一对差分对输出第二信号Sig2，包括Sig2_P和Sig2_N，P1的漏极输出与第一信号Sig1同相的Sig2_P，P2的漏极输出Sig2_N。
中间级转换模组和驱动级转换模组主要包括差分输入的正反馈结构，中间级转换模组中的差分输入的正反馈结构分别连接中间电压VP1和负电压VN。驱动级转换模组的差分输入的正反馈结构分别连接驱动级电压VP2以及负电压VN。在一个实施例中，中间级转换模组和驱动级转换模组中分别设置有用于分压的分压开关管，且两个转换模组中的分压开关管均受控于栅压控制信号V_CHG，栅压控制信号V_CHG在电平转换电路的一个工作周期的不同时段为不同的电压值，以调节分压开关管的状态，减少电平转换电路中器件在击穿电压下的工作时间，从而提高了电平转换电路中的器件的可靠性。
如图1所示，在中间级转换模组中，PMOS管P3、P4、P5、P6的源极相连并连接中间电压VP1，P4的漏极连接NMOS管N3的漏极，N3的源极连接NMOS管N5的漏极。P5的漏极连接NMOS管N4的漏极，N4的源极连接NMOS管N6的漏极。N5的源极和N6的源极相连并连接负电压VN。P3的漏极、P4的栅极、P5的漏极以及N5的栅极均相连，P6的漏极、P5的栅极、P4的漏极以及N6的栅极均相连。P3的栅极和P6的栅极作为一对差分对用于获取第二信号Sig2，P3的栅极连接P1的漏极获取Sig2_P，P6的栅极连接P2的漏极获取Sig2_N。N5的栅极和N6的栅极作为一对差分对用于输出第三信号Sig3包括Sig3_P和Sig3_N，N6的栅极输出与第一信号Sig1同相的Sig3_P，N5的栅极输出另一路Sig3_N。N3和N4作为中间级转换模组中的分压开关管，N3的栅极和N4的栅极相连并受控于栅压控制信号V_CHG。
在驱动级转换模组中，PMOS管P7和P8的源极相连并连接驱动级电压VP2，P7的漏极连接P8的栅极以及NMOS管N7的漏极，P8的漏极连接P7的栅极以及NMOS管N8的漏极，N7的源极连接NMOS管N9的漏极，N8的源极连接NMOS管N10的漏极，N9的源极和N10的源极相连并连接负电压VN。N9的栅极和N10的栅极作为一对差分对用于获取第三信号Sig3，N9的栅极连接N6的栅极获取Sig3_P，N10的栅极连接N5的栅极获取Sig3_N。N7的漏极和N8的漏极作为一对差分对用于输出驱动信号Sig4包括Sig4_P和Sig4_N，N8的漏极输出与第一信号Sig1同相的Sig4_P，N7的漏极输出另一路Sig4_N。N7和N8作为驱动级转换模组中的分压开关管，N7的栅极和N8的栅极相连并受控于栅压控制信号V_CHG。
在对flash型FPGA执行编程操作的一个工作周期内，工作周期依次包括电平转换阶段和维持阶段，电平转换阶段用于完成不同电压域的信号的转换，维持阶段用于维持信号的状态。（1）在工作周期开始的T0~T1时段的电平转换阶段，栅压控制信号V_CHG的电压值等于中间电压VP1，而在执行编程操作时，VDD<VP1<VP2。驱动级转换模组中的正高电压HV由于分压开关管N7和N8的钳位而不能传递到N9和N10上，此时N7、N8、N9、N10的栅、源、漏之间的压差都较小，提高N7、N8、N9、N10的安全电压容限。（2）在工作周期的T1~T2时段的维持阶段，栅压控制信号V_CHG的电压值为负电压VN，中间级转换模组中的分压开关管N3和N4关断，驱动级转换模组中的分压开关管N7和N8关断。电平转换电路的状态依靠电路的寄生电容C0、C1、C2、C3的电压来保持而没有下拉驱动，寄生电容C0、C1、C2、C3上存在的电荷保持数据但小于器件的击穿电压，以保护中间级转换模组中的P3、P4、P5和P6，以及保护驱动级转换模组中的P7和P8。
其中，中间级转换模组中的寄生电容包括中间级转换模组中的P4和N3之间的寄生电容C0以及P5和N4之间的寄生电容C1。驱动级转换模组中的寄生电容C2包括P7和N7之间的寄生电容以及P8和N8之间的寄生电容C3。
在对flash型FPGA执行擦除操作的一个工作周期内，工作周期依次包括电平转换阶段和维持阶段，电平转换阶段用于完成不同电压域的信号的转换，维持阶段用于维持信号的状态。（1）在工作周期开始的T0~T1时段的电平转换阶段，栅压控制信号V_CHG的电压值等于中间电压VP1，而在执行擦除操作时，VDD=VP1=VP2。（2）在工作周期的T1~T2时段的维持阶段，栅压控制信号V_CHG的电压值为负电压VN，而在执行擦除操作时，VN=负高电压LV。与执行编程操作类似，中间级转换模组中的分压开关管N3和N4关断，驱动级转换模组中的分压开关管N7和N8关断。电平转换电路的状态依靠电路的寄生电容C0、C1、C2、C3的电压来保持而没有下拉驱动，寄生电容C0、C1、C2、C3上存在的电荷保持数据但小于器件的击穿电压，以保护中间级转换模组中的P3、P4、P5和P6，以及保护驱动级转换模组中的P7和P8。
电平转换阶段和维持阶段的时长根据实际情况设定，一般设定电平转换阶段的时长为完成信号的电压域的转换并且驱动字线电路的时长、再增加一定的设计裕量，确定电平转换阶段的时长后，一个工作周期剩下的时长都为维持阶段。根据实际仿真结果，完成信号的电压域的转换最长时长在1.5us左右，所以可以设定电平转换阶段为2us，若一个工作周期共有10us，则维持阶段的时长为8us。在此实例中，也可以设定电平转换阶段为3us、维持阶段的时长为7us。但一般的，在任意一个工作周期内，维持阶段的时长大于电平转换阶段的时长，请参考图4所示的波形对比示意图。
在一个实例中，在对flash型FPGA执行编程操作的一个工作周期内，VDD=1.5V，VP1=3.6V，VP2=8.8V，VN=-2.5V。VP2和VN之间的压差为11.3V，距离5V器件的击穿电压12V的安全电压容限为0.7V。通过栅压控制信号V_CHG对N3、N4、N7、N8的栅端电压进行控制，在每个工作周期开始的小半周期的电平转换阶段T0~T1内，V_CHG=VP1=3.6V。VP2的8.8V由于串联的N7、N8的钳位而不能传递到N9、N10上，此时N7、N8、N9、N10的栅、源、漏之间的压差都较小，具有较大的安全电压容限。在每个工作周期剩余的大半周期的维持阶段T1~T2内，V_CHG= VN =-2.5V，N3、N4、N7、N8处于关闭状态，从而保护了P3、P4、P5、P6、P7、P8。
在对flash型FPGA执行擦除操作的一个工作周期内，VDD= VP1= VP2=1.5V，VN=-9.5V。VP2和VN之间的压差为11 V，距离5V器件的击穿电压12V的安全电压容限为1V。通过栅压控制信号V_CHG对N3、N4、N7、N8的栅端电压进行控制，在每个工作周期开始的小半周期的电平转换阶段T0~T1内，V_CHG=VP1=1.5V。在每个工作周期剩余的大半周期的维持阶段T1~T2内，V_CHG=VN=-9.5V，N3、N4、N7、N8处于关闭状态，从而保护了P3、P4、P5、P6、P7、P8。
以上所述仅是本申请的优选实施方式，本发明不限于以上实施例。可以理解，本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本发明的保护范围之内。

Claims (10)

  1. 一种flash型FPGA的基于逻辑工艺的电平转换电路，其特征在于，所述电平转换电路包括依次级联的第一级转换模组、中间级转换模组和驱动级转换模组；
    所述第一级转换模组用于将输入的VDD-GND电压域的第一信号转换为VP1-GND电压域的第二信号输出给所述中间级转换模组；所述中间级转换模组用于将输入的VP1-GND电压域的第二信号转换为VP1-VN电压域的第三信号输出给所述驱动级转换模组；所述驱动级转换模组用于将输入的VP1-VN电压域的第三信号转换为VP2-VN电压域的驱动信号，并输出驱动flash型FPGA的字线；
    控制逻辑工艺输出对应的电压组合以完成对flash型FPGA的擦除操作或编程操作，电压组合包括逻辑工艺提供的内核低电压VDD、逻辑工艺提供的中间电压VP1、逻辑工艺提供的驱动级电压VP2以及负电压VN，其中，GND为接地电压，VP2≥VP1≥VDD。
  2. 根据权利要求1所述的电平转换电路，其特征在于，在对所述flash型FPGA执行编程操作时，控制逻辑工艺提供的内核低电压VDD、中间电压VP1和驱动级电压VP2的电压值依次升高，且所述驱动级电压VP2的电压值为flash存储单元编程所需的正高电压HV，所述驱动级转换模组输出VP2-VN电压域的驱动信号控制字线将正高电压HV施加到flash存储单元的栅端，以完成编程操作。
  3. 根据权利要求1所述的电平转换电路，其特征在于，在对所述flash型FPGA执行擦除操作时，控制逻辑工艺提供的中间电压VP1和驱动级电压VP2的电压值与内核低电压VDD的电压值相等，控制逻辑工艺提供的负电压VN为flash存储单元擦除所需的负高电压LV，所述驱动级转换模组输出VP2-VN电压域的驱动信号控制字线将负高电压LV施加到flash存储单元的栅端，以完成擦除操作。
  4. 根据权利要求1所述的电平转换电路，其特征在于，所述中间级转换模组和驱动级转换模组中分别设置有用于分压的分压开关管，且两个转换模组中的分压开关管均受控于栅压控制信号，所述栅压控制信号在所述电平转换电路的一个工作周期的不同时段为不同的电压值，以调节所述分压开关管的状态，减少所述电平转换电路中的器件在击穿电压下的工作时长。
  5. 根据权利要求4所述的电平转换电路，其特征在于，所述第二信号和所述第三信号均为差分信号，在所述中间级转换模组中，PMOS管P3、P4、P5、P6的源极相连并连接所述中间电压VP1，P4的漏极连接NMOS管N3的漏极，N3的源极连接NMOS管N5的漏极；P5的漏极连接NMOS管N4的漏极，N4的源极连接NMOS管N6的漏极；N5的源极和N6的源极相连并连接所述负电压VN；P3的漏极、P4的栅极、P5的漏极以及N5的栅极均相连，P6的漏极、P5的栅极、P4的漏极以及N6的栅极均相连，P3的栅极和P6的栅极作为一对差分对用于获取所述第二信号，N5的栅极和N6的栅极作为一对差分对用于输出所述第三信号；N3和N4作为所述中间级转换模组中的分压开关管，N3的栅极和N4的栅极相连并受控于所述栅压控制信号。
  6. 根据权利要求4所述的电平转换电路，其特征在于，所述第三信号和所述驱动信号均为差分信号，在所述驱动级转换模组中，PMOS管P7和P8的源极相连并连接所述驱动级电压VP2，P7的漏极连接P8的栅极以及NMOS管N7的漏极，P8的漏极连接P7的栅极以及NMOS管N8的漏极，N7的源极连接NMOS管N9的漏极，N8的源极连接NMOS管N10的漏极，N9的源极和N10的源极相连并连接所述负电压VN；N9的栅极和N10的栅极作为一对差分对用于获取所述第三信号，N7的漏极和N8的漏极作为一对差分对用于输出所述驱动信号；N7和N8作为所述驱动级转换模组中的分压开关管，N7的栅极和N8的栅极相连并受控于所述栅压控制信号。
  7. 根据权利要求5或6所述的电平转换电路，其特征在于，在对所述flash型FPGA执行编程操作或擦除操作的任意一个工作周期内，所述工作周期依次包括电平转换阶段和维持阶段，所述电平转换阶段用于完成不同电压域的信号的转换，所述维持阶段用于维持信号的状态；
    在所述工作周期的维持阶段内，所述栅压控制信号的电压值为所述负电压VN，所述中间级转换模组中的分压开关管N3和N4关断，所述驱动级转换模组中的分压开关管N7和N8关断，所述电平转换电路的状态依靠电路的寄生电容的电压来保持而没有下拉驱动，寄生电容上存在的电荷保持数据但小于器件的击穿电压，以保护所述中间级转换模组中的P3、P4、P5和P6，以及保护所述驱动级转换模组中的P7和P8；
    其中，所述中间级转换模组中的寄生电容包括所述中间级转换模组中的P4和N3之间的寄生电容以及P5和N4之间的寄生电容，所述驱动级转换模组中的寄生电容包括P7和N7之间的寄生电容以及P8和N8之间的寄生电容。
  8. 根据权利要求7所述的电平转换电路，其特征在于，在对所述flash型FPGA执行编程操作或擦除操作的任意一个工作周期内，在所述工作周期的电平转换阶段内，所述栅压控制信号的电压值等于所述中间电压VP1；则在对所述flash型FPGA执行编程操作时，所述驱动级转换模组中的正高电压HV由于分压开关管N7和N8的钳位而不能传递到N9和N10上，提高N7、N8、N9、N10的安全电压容限。
  9. 根据权利要求8所述的电平转换电路，其特征在于，在任意一个工作周期内，所述维持阶段的时长大于所述电平转换阶段的时长。
  10. 根据权利要求1所述的电平转换电路，其特征在于，所述第一信号为单端信号，所述第二信号为差分信号，在第一级转换模组中，PMOS管P1和P2的源极相连并连接所述中间电压VP1，P1的漏极连接P2的栅极和NMOS管N1的漏极，P2的漏极连接P1的栅极和NMOS管N2的漏极，N1的源极和N2的源极相连并连接GND；
    PMOS管P0的源极连接所述内核低电压VDD，P0的漏极连接NMOS管N0的漏极，N0的源极连接GND，P0的栅极和N0的栅极相连并获取所述第一信号，P0的漏极输出所述第一信号的反相信号并连接N1的栅极，N2的栅极获取所述第一信号；P1的漏极和P2的漏极作为一对差分对输出所述第二信号。
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