WO2023115402A1 - 驱动背板及其制备方法、显示装置及其制备方法 - Google Patents

驱动背板及其制备方法、显示装置及其制备方法 Download PDF

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Publication number
WO2023115402A1
WO2023115402A1 PCT/CN2021/140565 CN2021140565W WO2023115402A1 WO 2023115402 A1 WO2023115402 A1 WO 2023115402A1 CN 2021140565 W CN2021140565 W CN 2021140565W WO 2023115402 A1 WO2023115402 A1 WO 2023115402A1
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WIPO (PCT)
Prior art keywords
layer
base substrate
flexible film
conductive
film layer
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PCT/CN2021/140565
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English (en)
French (fr)
Inventor
杜建华
薛金祥
卢鑫泓
刘英伟
赵梦
吴昊
关峰
吕杨
王超璐
Original Assignee
京东方科技集团股份有限公司
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Priority to CN202180004111.8A priority Critical patent/CN116648740A/zh
Priority to PCT/CN2021/140565 priority patent/WO2023115402A1/zh
Publication of WO2023115402A1 publication Critical patent/WO2023115402A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a driving backplane and a method for preparing the driving backplane, a display device including the driving backplane, and a method for manufacturing the display device.
  • MLED Micro Light-Emitting Diode, micro-light-emitting diode; or Mini Light-Emitting Diode, sub-millimeter light-emitting diode
  • MLED Micro Light-Emitting Diode, micro-light-emitting diode
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, and provide a driving backplane and a manufacturing method of the driving backplane, a display device including the driving backplane, and a manufacturing method of the display device.
  • a method for preparing a driving backplane including:
  • a base substrate is provided, the base substrate has a first surface and a second surface oppositely arranged, and a side surface is connected between the first surface and the second surface;
  • first opening comprising a first part, a second part and a third part connected in sequence
  • a conductive layer is formed on the side of the flexible film layer away from the base substrate, and the conductive layer is formed in at least part of the first opening to form a conductive strip;
  • At least the flexible film layer and the conductive layer around the conductive strip are removed.
  • the preparation method before patterning the flexible film layer, the preparation method further includes:
  • the material of the isolation layer is inorganic, and the material of the flexible film layer is organic.
  • the preparation method after patterning the flexible film layer, the preparation method further includes:
  • the preparation method before removing part of the base substrate, the preparation method further includes:
  • the preparation method further includes:
  • the edge connecting the side surface with the first surface and the edge connecting the side surface with the second surface are processed to form chamfers.
  • At least removing the flexible film layer and the conductive layer around the conductive strip includes:
  • the preparation method further includes:
  • a set tension is applied to the end of the flexible film layer bent to the second surface, so that the flexible film layer is attached to the base substrate.
  • the preparation method further includes:
  • a plurality of switch units arranged in an array and a plurality of connection wires are formed on one side of the base substrate, and the connection wires are connected between the switch units and the conductive strips;
  • the protective material layer forms a protective layer
  • the metal layer forms a connecting pin
  • An insulating layer group is formed on a side of the protective layer away from the base substrate, and the insulating layer group is patterned to form a via hole, and the via hole is connected to the protective layer.
  • the protective material layer is made of oxide.
  • the set etching amount of the protective material layer is greater than the set etching amount of the metal layer, so that the protective material layer and the metal layer are sequentially After the patterning process, the orthographic projection of the protection layer on the base substrate is located within the orthographic projection of the side of the connecting pin away from the base substrate on the base substrate.
  • the preparation method before forming a metal layer on a side of the switch unit away from the base substrate, the preparation method further includes:
  • the metal layer is formed on a side of the first conductive layer away from the base substrate;
  • the first conductive layer is patterned to form conductive pins.
  • a driving backplane is provided, and the driving backplane is prepared by any one of the preparation methods described above.
  • the drive backplane includes:
  • the base substrate has a first surface and a second surface oppositely arranged, and a side surface is connected between the first surface and the second surface;
  • a buffer layer located on the side of the flexible film layer away from the base substrate;
  • the conductive strip is arranged on at least one end of the base substrate, the conductive strip includes a first conductive part, a second conductive part and a third conductive part connected in sequence, and the first conductive part is arranged on the first conductive part.
  • the second conductive part is arranged on the side surface, and the third conductive part is arranged on the second surface.
  • the drive backplane further includes:
  • the isolation layer is arranged between the flexible film layer and the buffer layer.
  • the drive backplane further includes:
  • a plurality of switch units arranged in an array and a plurality of connection wires are arranged on the side of the buffer layer away from the base substrate, and the connection wires are connected between the switch units and the conductive strips;
  • connection pin is provided on a side of the switch unit away from the base substrate, and the connection pin is connected to the switch unit;
  • a protective layer is provided on the side of the connection pin away from the base substrate;
  • the insulating layer group is arranged on the side of the protective layer away from the base substrate, and the insulating layer group is provided with a via hole, and the via hole is connected to the protective layer.
  • a method for manufacturing a display device including:
  • the driving backplane is formed by preparing the driving backplane described in any one of the above methods;
  • a light-emitting device is mounted on one side of the driving backplane, and the light-emitting device is connected to the connecting pins.
  • a display device which is manufactured by the above-mentioned method for manufacturing a display device.
  • the light emitting device is a micro light emitting diode.
  • FIG. 1 is a schematic block diagram of an exemplary embodiment of a manufacturing method of a driving backplane of the present disclosure.
  • FIG. 2 is a schematic structural view of the flexible film layer after patterning in the manufacturing method of the driving backplane of the present disclosure.
  • FIG. 3 is a partial cross-sectional structural schematic diagram after patterning the flexible film layer and the isolation layer in the manufacturing method of the driving backplane of the present disclosure.
  • 4-9 are structural schematic diagrams of various steps of forming a switch unit in the display area in the manufacturing method of the driving backplane of the present disclosure.
  • 10-16 are structural schematic diagrams of each step of the side lead process in the manufacturing method of the driving backplane of the present disclosure.
  • Fig. 17 is a schematic structural diagram of an example implementation of the drive backplane of the present disclosure.
  • FIG. 18 is a schematic block diagram of an exemplary embodiment of a manufacturing method of a display device of the present disclosure.
  • FIG. 19 is a schematic structural view of the driving backplane of the present disclosure after the protective layer is removed.
  • FIG. 20 is a schematic structural diagram of an exemplary embodiment of a display device of the present disclosure.
  • Substrate substrate 101, first surface; 102, second surface; 103, side surface; 1a, substrate motherboard;
  • the first conductive layer 111. Conductive pins;
  • the second insulating layer 15. The second planarization layer; 151. The seventh via hole; 152. The eighth via hole;
  • Conductive layer 171. Conductive strip; 1711. First conductive part; 1712. Second conductive part; 1713. Third conductive part;
  • AA display area
  • FA non-display area
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • 3D sputtering can be performed on the end of the base substrate where the side leads need to be formed to form a conductive layer, and then the side conductive strips can be formed by laser etching, but the width of the laser is relatively large, so the etching accuracy is insufficient.
  • the solid particles formed after laser ablation of the conductive layer are not easy to remove, and may fall to the display area AA to affect the display, and may adhere to the conductive strip to affect the conductive effect; in addition, It is also possible to use a disposable mask as a mask, and then perform 3D sputtering to form conductive strips, but the mask needs to be aligned, which increases the alignment process, thereby increasing costs and reducing efficiency.
  • the bottleneck process of MLED lies in reducing the seam distance, and the seam distance is limited by technology such as side lead technology.
  • the improvement of the side lead process is very beneficial to reduce the seam size.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a drive backplane. Referring to FIG. 1 , the method may include the following steps:
  • Step S10 providing a base substrate 1 , the base substrate 1 has a first surface 101 and a second surface 102 oppositely disposed, and a side surface 103 is connected between the first surface 101 and the second surface 102 .
  • Step S20 forming a flexible film layer 16 on the first surface 101, and patterning the flexible film layer 16 to form a first opening 161, the first opening 161 includes a first part 1611, The second part 1612 and the third part 1613 .
  • Step S30 bending part of the flexible film layer 16 to the second surface 102, so that the first part 1611 is opposite to the first surface 101, and the second part 1612 is opposite to the side 103, The third portion 1613 is opposite to the second surface 102 .
  • Step S40 using the flexible film layer 16 as a mask to form a conductive layer 17 on the side of the flexible film layer 16 away from the base substrate 1, and the conductive layer 17 is formed on at least part of the first Conductive strips 171 are formed in the openings 161 .
  • Step S50 at least removing the flexible film layer 16 and the conductive layer 17 around the conductive strip 171 .
  • the flexible film layer 16 formed on one side of the base substrate is used as a mask to directly form the side conductive strip 171 on at least one end of the base substrate 1 without alignment process, whereby simplifying the process, further reducing the cost and improving the efficiency; and the precision of the patterning treatment is high, so the precision of the formed conductive strip 171 is high, which can meet the requirements of high-precision products; in addition, the patterning treatment will not produce etching foreign matter, The display effect and conductive effect will not be affected by etching foreign matter.
  • Step S10 providing a base substrate 1 , the base substrate 1 has a first surface 101 and a second surface 102 oppositely disposed, and a side surface 103 is connected between the first surface 101 and the second surface 102 .
  • the substrate motherboard 1a is set relatively large, and other structures of multiple driving backplanes can be formed on one substrate motherboard 1a.
  • the dotted line in the figure represents a driving backplane Occupies the area of the substrate motherboard 1a.
  • a plurality of base substrates 1 are formed after cutting the base mother plate 1a.
  • the base substrate 1 can be set as a rectangular plate, and the base substrate 1 has a first face 101 and a second face 102 oppositely arranged, and the first face 101 and the second face 102 are both rectangular; on the first face 101 and the second face There are four sides 103 connected between 102, and the four sides 103 are all rectangular.
  • the base substrate 1 may be set as a circular plate or an elliptical plate. In this case, the first surface 101 and the second surface 102 are both circular or elliptical. There is only one side surface 103 between the first surface 101 and the second surface 102; the base substrate 1 may also have other shapes, which will not be described here.
  • the base substrate 1 may include a display area AA and a non-display area FA, and the display area AA is connected to the non-display area FA. It should be noted that the division of the display area AA and the non-display area FA in the figure is only schematic, for the convenience of understanding, and does not constitute a limitation to the present disclosure.
  • the material of the base substrate 1 may include inorganic materials, for example, the inorganic materials may be glass, quartz, or metal.
  • the material of the base substrate 1 may also include organic materials, for example, the organic materials may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate Resin materials such as ester and polyethylene naphthalate.
  • the base substrate 1 may be formed of multiple material layers, for example, the base substrate 1 may include multiple base layers, and the material of the base layer may be any one of the above-mentioned materials.
  • the base substrate 1 can also be set as a single layer, which can be any one of the above materials.
  • Step S20 forming a flexible film layer 16 on the first surface 101, and patterning the flexible film layer 16 to form a first opening 161, the first opening 161 may include sequentially connected first parts 1611 , the second part 1612 and the third part 1613 .
  • the flexible film layer 16 is formed on the first surface 101 of the base substrate 1 through a coating process.
  • the material of the flexible film layer 16 can be organic matter, including but not limited to PI (polyimide), and the thickness of the flexible film layer 16 can be greater than or equal to 5 microns and less than or equal to 20 microns.
  • an isolation layer 20 is formed on the side of the flexible film layer 16 away from the base substrate 1 by deposition, sputtering and other processes.
  • the rate at which the isolation layer 20 is patterned is less than the rate at which the flexible film layer 16 is patterned.
  • the rate of the patterning process may be an etching rate, that is, the etching rate of the isolation layer 20 is lower than the etching rate of the flexible film layer 16 .
  • the thickness of the isolation layer 20 may be greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.
  • the material of the isolation layer 20 can be inorganic substances, including but not limited to metals, for example, Al, Mo, etc.
  • the material of the isolation layer 20 can also be silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the isolation layer 20 can also be made of other materials, as long as the rate of patterning the isolation layer 20 is lower than the rate of patterning the flexible film layer 16 .
  • the inorganic isolation layer 20 is not easy to break during the multiple bending process in the subsequent process.
  • the isolation layer 20 may not be formed on the side of the flexible film layer 16 away from the base substrate 1 . That is, after the flexible film layer 16 is formed, the flexible film layer 16 is directly patterned.
  • the flexible film layer 16 and the isolation layer 20 can cover the entire substrate mother board 1a, and then remove unnecessary parts during the subsequent patterning process.
  • patterning the flexible film layer 16 and the isolation layer 20 corresponds to forming the first opening 161 and the second opening 202, specifically: forming on the side of the isolation layer 20 away from the base substrate 1 18 layers of photoresist, place a mask on the side of the photoresist 18 away from the base substrate 1, then illuminate the photoresist layer 18, and develop the photoresist layer 18 to remove the illuminated photoresist glue 18; finally, the flexible film layer 16 and the isolation layer 20 are etched using the photoresist layer 18 as a mask.
  • the isolation layer 20 can be pre-etched first to form a smaller second opening on the isolation layer 20; then, the flexible film layer 16 is etched with a gas different from the above-mentioned etching, and the flexible film layer is etched.
  • the etching rate of the gas of 16 to the isolation layer 20 is very small, as shown in FIG.
  • the etching amount of the flexible film layer 16 is greater than the etching amount of the isolation layer 20, so that the isolation layer 20 forms a protrusion 201 protruding from the flexible film layer 16 at the second opening 202, that is, the second opening 202 is smaller than Edges of the first opening 161 and the second opening 202 are located within the edges of the first opening 161 .
  • the first opening 161 can be a plurality of vias, and the vias can be elongated; the vias can include a first part 1611, a second part 1612 and a third part 1613; the second part 1612 Connected between the first part 1611 and the third part 1613, the ends of the first part 1611 and the third part 1613 away from the second part 1612 can be configured as square via holes, and the second part 1612 can be configured as rectangular via holes.
  • the first opening 161 may also be a notch (that is, an opening that is not closed), and the notch may be elongated; the specific shape of the notch may be the same as that of the above-mentioned via hole, except that the second The side away from the second part 1612 of the three parts 1613 is set as an opening, so that the entire first opening 161 is formed as an opening with a gap; also, the first part 1611 and the third part 1613 are away from the end of the second part 1612
  • the part can be set as a circular via hole or an oval via hole.
  • the flexible film layer 16 and the isolation layer 20 in other areas can be removed, for example, part of the display can be removed.
  • the flexible film layer 16 and the isolation layer 20 in the area AA that is, retain the part of the flexible film layer 16 and the isolation layer 20 located in the display area AA. Retaining part of the flexible film layer 16 and the isolation layer 20 can prevent the flexible film layer 16 and the isolation layer 20 from being pulled off during the side lead process.
  • a light-shielding layer 2 can be formed on the first surface of the base substrate;
  • a buffer layer 3 is formed on the side of the isolation layer 20 away from the base substrate 1 and the side of the light shielding layer 2 away from the base substrate 1 , and the isolation layer 20 is covered by the buffer layer 3 .
  • the buffer layer 3 can be formed on the side of the light shielding layer 2 away from the base substrate 1; in the case where the isolation layer 20 is not formed, The buffer layer 3 can be formed on the side of the flexible film layer 16 away from the base substrate 1 and the side of the light-shielding layer 2 away from the base substrate 1 .
  • the switch unit may include a capacitor and at least two thin film transistors, and the thin film transistor may include an active layer 4, a gate 6, a source 81 and a drain;
  • the active layer 4, the active layer 4 may include a channel portion 42 and conductor portions 41 disposed at both ends of the channel portion 42, a gate insulating layer 5 is formed on the side of the active layer 4 away from the base substrate 1, and
  • a gate 6 is formed on one side of the gate insulating layer 5, and a connection line 61 is formed on a side of the buffer layer 3 away from the base substrate 1 while forming the gate 6, and a connection line 61 is formed on a side of the gate 6 away from the base substrate 1.
  • An interlayer dielectric layer 7 is formed, a first via hole 71 and a second via hole 72 are formed on the interlayer dielectric layer 7, the first via hole 71 is connected to the conductor portion 41, and the second via hole 72 is connected to the connection line 61; a ground line 83, a source electrode 81 and a drain electrode 82 are formed on the side of the interlayer dielectric layer 7 away from the base substrate 1, and the source electrode 81 and the drain electrode 82 are respectively connected through two first via holes 71 To the two conductor parts 41 , the ground wire 83 is connected to the connection wire 61 through the second via hole 72 .
  • source 81 and the “drain 82 ” may be interchanged when using thin film transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in this specification, “source 81” and “drain 82” can be interchanged with each other.
  • the connecting wires can include grid wires, data wires, power wires, etc.; Simultaneously formed, the data line and the power line may be formed at the same time as the source electrode 81 and the drain electrode 82 are formed.
  • the connecting portion 19 connecting the conductive strip 171 and the connecting wire is formed, and the connecting portion 19 is formed on the end of the first part 1611 of the first opening 161 close to the display area AA and the end of the second opening 202. Near the end of display area AA.
  • a first planarization layer 9 is formed on the side away from the base substrate 1 of the switch unit, and a third via hole 91 and a fourth via hole 92 are formed on the first planarization layer 9;
  • a first insulating layer 10 is formed on one side of the base substrate 1 , and a fifth via hole and a sixth via hole 1002 are formed on the first insulating layer 10 .
  • the first conductive layer 11 is formed on the side of the insulating layer away from the base substrate 1, the first conductive layer 11 is connected to the source and the drain through two third via holes 91, and the first conductive layer 11 is connected to the source and drain through the fourth via hole 92 Connect to ground 83.
  • the first conductive layer 11 may be a nickel-molybdenum alloy. The first conductive layer 11 can prevent the subsequently formed metal layer 12 from seeping into the film layer below the metal layer 12 .
  • the metal layer 12 is deposited on the side of the first conductive layer 11 away from the base substrate 1.
  • the material of the metal layer 12 can be copper, of course, it can also be other metal materials; during the high temperature annealing process, the metal layer 12 is prone to natural Oxidation, the electrical conductivity of the metal layer 12 after natural oxidation is relatively poor, and in the subsequent gold chemical process, the adhesion to gold is poor, thereby affecting the performance of the driving backplane; but, if the high temperature annealing process is not performed, it will This results in abnormalities in the thin film transistor, for example, divergence of the transfer curve, positive or negative Vth bias, and the like.
  • the protective material layer 13 is deposited on the side of the metal layer 12 away from the base substrate 1.
  • the material of the protective material layer 13 can be oxide, for example, can be IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide), ITZO (Indium Gallium Zinc Oxide), ITZO (Indium Gallium Zinc Oxide), Tin Zinc Oxide, indium tin zinc oxide), etc.; IGZO and ITZO can react quickly with dilute acid.
  • the protective material layer 13 can also be other oxides.
  • the thickness of the protective material layer 13 is greater than or equal to 10 nm and less than or equal to 50 nm. When depositing and forming the protective material layer 13 , it is not necessary to add O 2 for reactive sputtering, and the metal layer 12 will not be oxidized.
  • the protective material layer 13 can protect the metal layer 12 to avoid natural oxidation of the metal layer 12, so that the high-temperature annealing process can be performed on the driving backplane, thereby preventing the thin film transistor from having discrete transfer curves, positive Vth bias or Abnormalities such as negative bias.
  • a photoresist 18 is formed on the side of the metal layer 12 away from the base substrate 1, and a mask is placed on the side of the photoresist 18 away from the base substrate 1, using the mask as a mask
  • the photoresist 18 is exposed and developed, and then the protective material layer 13, the metal layer 12 and the first conductive layer 11 are sequentially etched using the remaining photoresist 18 as a mask, that is, the protective material layer 13 is etched first to form a protective layer 131 , and then etch the metal layer 12 and the first conductive layer 11 , the metal layer 12 is etched to form the connecting pin 121 , and the first conductive layer 11 is etched to form the conductive pin 111 .
  • the set etching amount of the protective material layer 13 is greater than the set etched amount of the metal layer 12, so that after the protective material layer 13 and the metal layer 12 are patterned sequentially, the front surface of the protective layer 131 on the base substrate 1
  • the projection is located within the orthographic projection of the side of the connection pin 121 away from the base substrate 1 on the base substrate 1 .
  • the metal layer 12 is thicker, when the metal layer 12 is etched, the etching time is longer, and it is easy to form a circular truncated or truncated structure with a smaller upper part and a larger lower part.
  • the metal layer 12 is etched to form a circular structure.
  • the diameter of the side of the connecting pin 121 away from the base substrate 1 is R1
  • the diameter of the side of the connecting pin 121 close to the base substrate 1 is R2
  • R1 is smaller than R2 .
  • the protective material layer 13 also maintains the same setting etching amount as the metal layer 12, for example, the protective material layer 13 can be etched to form a circular plate, the diameter of the circular plate is R2, and the diameter of the protective layer 131 is larger than the connecting pin 121 is away from the diameter R1 of the side of the base substrate 1, so that the edge of the protective layer 131 protrudes beyond the edge of the connecting pin 121, and when the second insulating layer 14 is formed by subsequent deposition, the second insulating layer 14 is easy to break, so that it cannot The connection pin 121 is insulated and protected.
  • the etching amount refers to the etching amount in a direction parallel to the surface of the base substrate 1 facing the metal layer 12 .
  • the orthographic projection of the protective layer 131 on the base substrate 1 be located within the orthographic projection of the side of the connection pin 121 away from the base substrate 1 on the base substrate 1, that is, the protective layer 131 may be on the base substrate 1
  • the orthographic projection of the connecting pin 121 is completely coincident with the orthographic projection of the side of the connecting pin 121 away from the base substrate 1 on the base substrate 1, and the orthographic projection of the protective layer 131 on the base substrate 1 is located where the connecting pin 121 is far away from the base substrate.
  • the orthographic projection of one side of 1 on the base substrate 1 that is, the orthographic projection of the protective layer 131 on the base substrate 1 is smaller than the orthographic projection of the side of the connection pin 121 away from the base substrate 1 on the base substrate 1 .
  • the second insulating layer 14 can be prevented from breaking, so that the second insulating layer 14 can provide insulation protection for the connecting pin 121 .
  • the photoresist 18 is removed.
  • the second insulating layer 14 is formed on the side of the protective layer 131 away from the base substrate, and the second planarization layer 15 is formed on the side of the second insulating layer 14 away from the base substrate, and the second planarization
  • the layer 15 and the second insulating layer 14 are patterned to form a seventh via hole 151 and an eighth via hole 152 , the seventh via hole 151 can be connected to the source 81 , and the eighth via hole 152 can be connected to the ground line 83 .
  • the substrate motherboard 1a can be cut to form a plurality of substrate substrates 1, and then the side lead process is performed.
  • Step S30 bending part of the flexible film layer 16 to the second surface 102, so that the first part 1611 is opposite to the first surface 101, and the second part 1612 is opposite to the side 103, The third portion 1613 is opposite to the second surface 102 .
  • the flexible film layer 16 and the isolation layer 20 are bent to the side away from the second surface 102, so that part of the flexible film layer 16 is separated from the base substrate 1; then, referring to FIG. As shown in 11, the exposed part of the base substrate 1 can be removed by cutting, so that one end of the flexible film layer 16 protrudes from the base substrate 1, that is, after the flexible film layer 16 is flattened, the second part 1612 and the third part 1613
  • the orthographic projection on the first plane does not overlap with the orthographic projection of the base substrate 1 on the first plane, and the first plane is a plane parallel to the base substrate 1 .
  • the side surface 103 of the base substrate 1 is ground, so that the edge connecting the side surface 103 of the base substrate 1 and the first surface 101 forms a chamfer, and the side surface 103 of the base substrate 1 and the first surface 101 are chamfered.
  • the edges connected to the second surface 102 are also chamfered; the above-mentioned chamfers may be oblique chamfers or round chamfers.
  • the chamfering makes the connection between the first surface 101 and the side 103 and the second surface 102 and the side 103 more gentle, and the subsequently formed conductive layer 17 is bent from the first surface 101 to the side 103, and from the side 103 to the side 103.
  • the second surface 102 is also relatively gentle, so as to prevent the conductive layer 17 from forming a corner with a small angle and being easily broken.
  • the second portion 1612 of the first opening 161 is opposite to the side 103
  • the third portion 1613 of the first opening 161 is opposite to the second surface 102 .
  • a set tensile force can be applied to the flexible film layer 16 and the isolation layer 20, that is, a tensile force parallel to the base substrate 1 is applied to the end of the flexible film layer 16 bent to the second surface 102, so that the bent flexible film layer 16 It is completely attached to the base substrate 1 , and a gap is formed between the flexible film layer 16 and the base substrate 1 .
  • the conductive material will not only be deposited on the base substrate 1 not covered by the flexible film layer 16, but also be formed on the substrate 1 through the gap.
  • the strips 171 may be connected together causing a short circuit between the two conductive strips 171 .
  • the flexible film layer 16 is completely bonded to the base substrate 1, so that the above-mentioned defects can be avoided.
  • Step S40 using the flexible film layer 16 as a mask to form a conductive layer 17 on the side of the flexible film layer 16 away from the base substrate 1, and the conductive layer 17 is formed on at least part of the first Conductive strips 171 are formed in the openings 161 .
  • the arrow shows the sputtering direction in the figure
  • the flexible film layer 16 is used as a mask
  • the flexible film layer 16 is used as a shielding layer
  • two shielding layers are set in the display area AA.
  • Plates 21, one shielding plate 21 is disposed on the second surface of the base substrate, and the other shielding plate 21 is disposed on the side of the protective layer 131 away from the base substrate, so as to avoid the formation of conductive material in the display area AA.
  • a sputtering device On the side of the flexible film layer 16 away from the base substrate 1, mainly the side of the flexible film layer 16 that is provided with the first opening 161 away from the base substrate 1 is provided with a sputtering device, and multiple sputtering devices can be provided.
  • a sputtering device forms a semi-encirclement to surround the end of the base substrate 1 that needs to form a conductive strip 171, and a plurality of sputtering devices sputters conductive materials from multiple directions to the first opening 161 of the flexible film layer 16 to conduct electricity.
  • the material forms the conductive layer 17 , and the conductive layer formed in the first opening 161 is a conductive strip 171 .
  • the conductive layer 17 can be a three-layer structure, the first layer is titanium, the second layer is copper, and the third layer is titanium; it can be formed by sputtering in three periods in one sputtering process.
  • the conductive strip 171 may include a first conductive portion 1711 , a second conductive portion 1712 and a third conductive portion 1713 connected in sequence, the first conductive portion 1711 is formed in the first portion 1611 of the first opening 161 , And it is located on the first surface 101; the area of the first conductive portion 1711 away from the second conductive portion 1712 is larger, and can be used as a connection pad.
  • the second conductive portion 1712 is formed in the second portion 1612 of the first opening 161 and is located on the side surface 103 ; the third conductive portion 1713 is formed in the third portion 1613 of the first opening 161 and is located on the second surface 102 , The area of the third conductive portion 1713 away from the second conductive portion 1712 is larger, and can also serve as a connection pad.
  • the isolation layer 20 forms a protruding part 201 protruding from the flexible film layer 16 after patterning, and when the conductive layer 17 and the conductive strip 171 are formed by sputtering, the protruding part 201 shielding, so that the conductive layer 17 formed on the side of the isolation layer 20 away from the base substrate and the conductive strip 171 formed in the first opening 161 break, and when the flexible film layer 16 is peeled off later, the flexible film layer 16 will not Take the conductive strip 171 away to ensure the stability of the conductive strip 171 .
  • Step S50 at least removing the flexible film layer 16 and the conductive layer 17 around the conductive strip 171 .
  • the flexible film layer 16 is peeled off from the second surface 102, the end surface and part of the first surface 101, so that at least a part of the flexible film layer 16 formed with the first opening 161 is separated from the lining. Then, as shown in FIG. 16 , the flexible film layer 16 and the conductive layer 17 peeled off are cut off; thereby the flexible film layer 16 and the conductive layer 17 around the conductive strip 171 are removed; while the conductive strip 171 is still attached. On the first surface 101 , the end surface and the second surface 102 of the base substrate 1 .
  • the flexible film layer 16 and the conductive layer 17 are not disposed in the display area AA, the flexible film layer 16 and the conductive layer 17 can also be completely peeled off, and only the conductive layer 17 remains.
  • Article 171 in the case that the flexible film layer 16 and the conductive layer 17 are not disposed in the display area AA, the flexible film layer 16 and the conductive layer 17 can also be completely peeled off, and only the conductive layer 17 remains.
  • the preparation of the driving backplane is completed, and the preparation of the conductive strips 171 by the above method does not require alignment, thereby simplifying the process and reducing the cost; moreover, the formed conductive strips 171 have high precision and will not produce etching foreign matter.
  • exemplary embodiments of the present disclosure provide a driving backplane, as shown in FIG. 17 , the driving backplane is prepared by any one of the preparation methods described above.
  • the drive backplane may include a base substrate 1, a light-shielding layer 2 and a flexible film layer 16 arranged on one side of the base substrate 1, and an isolation layer is provided on the side of the flexible film layer 16 away from the base substrate 1.
  • the flexible film layer 16 is provided with a first opening 161
  • the isolation layer 2 is provided with a second opening 202
  • the second opening 202 is opposite to the first opening 161
  • a connecting portion 19 is provided inside.
  • Conductive strips 171 are provided on the end of the base substrate 1 where the connecting portion 19 is provided, and the conductive strips 171 are connected to the connecting portions 19 in a one-to-one correspondence.
  • the isolation layer 20 may not be provided.
  • the conductive strip 171 includes a first conductive part 1711, a second conductive part 1712 and a third conductive part 1713 connected in sequence, the first conductive part 1711 is arranged on the first surface 101, the second conductive part 1712 is arranged on the side 103, and the third conductive The portion 1713 is separately disposed on the second surface 102 .
  • the first conductive portion 1711 is connected to the connection portion 19 .
  • a buffer layer 3 is arranged on the side of the light-shielding layer 2 away from the base substrate 1 and the side of the isolation layer away from the base substrate 1.
  • a buffer layer 3 is provided on the side of the light-shielding layer 2 away from the base substrate 1 and the side of the flexible film layer 16 away from the base substrate 1 .
  • the switch unit may include a capacitor and at least two thin film transistors, and the thin film transistor may include an active layer 4, a gate 6, a source 81 and a drain;
  • the active layer 4 and the connecting wire 61, the active layer 4 may include a channel portion 42 and conductor portions 41 arranged at both ends of the channel portion 42, and a gate insulating layer is provided on the side of the active layer 4 away from the base substrate 1 Layer 5, a gate 6 is provided on one side of the gate insulating layer 5, an interlayer dielectric layer 7 is provided on the side of the gate 6 away from the base substrate 1, and a second interlayer dielectric layer is provided on the interlayer dielectric layer 7.
  • a via hole 71 and a second via hole 72 the first via hole 71 is connected to the conductor part 41, and the second via hole 72 is connected to the connection line 61; it is provided on the side of the interlayer dielectric layer 7 away from the base substrate 1
  • the thin-film transistor described in this specification is a top-gate thin-film transistor.
  • the thin-film transistor may also be a bottom-gate or double-gate type, and the specific structure thereof will not be described here. repeat.
  • the connecting wires may include gate wires, data wires, power wires, etc.; the connecting wires are connected between the switch unit and the connecting portion 19, and the electrical signals are transmitted through the conductive strip 171, the connecting portion 19 and the connecting wires.
  • a first planarization layer 9 is provided on the side away from the base substrate 1 of the switch unit, and a plurality of third via holes 91 and fourth via holes 92 are provided on the first planarization layer 9;
  • a first insulating layer 10 is disposed on the side away from the base substrate 1 , and a plurality of fifth via holes 1001 and sixth via holes 1002 are disposed on the first insulating layer 10 .
  • Conductive pins 111 are provided on the side of the first insulating layer 10 away from the base substrate 1, and the two conductive pins 111 are respectively connected to the source 81 and the drain 82 through the third via hole 91 and the fifth via hole 1001. , the other conductive pin 111 is connected to the ground wire 83 through the fourth via hole 92 and the sixth via hole 1002 .
  • the conductive pin 111 may be nickel molybdenum alloy.
  • connection pin 121 is arranged on the side of the conductive pin 1111 away from the base substrate 1, and the material of the connection pin 121 can be copper.
  • a protective layer 131 is provided on the side of the connection pin 121 away from the base substrate 1.
  • the material of the protective layer 131 can be oxide, for example, can be IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide, Indium Tin Zinc Oxide) etc.
  • a second insulating layer 14 is provided on the side of the protective layer 131 away from the base substrate, and a second planarization layer 15 is provided on the side of the second insulating layer 14 away from the base substrate.
  • the second planarization layer 15 and the second The insulating layer 14 forms an insulating layer group, and the insulating layer group is provided with a seventh via hole 151 and an eighth via hole 152 , the seventh via hole 151 can be connected to the source 81 , and the eighth via hole 152 can be connected to the ground line 83 .
  • exemplary embodiments of the present disclosure provide a method for manufacturing a display device.
  • the method may include the following steps:
  • a driving backplane is formed by any one of the methods for preparing a driving backplane described above.
  • Step S520 removing at least part of the protective layer 131 to expose at least part of the connection pins 121 .
  • Step S530 installing a light emitting device 22 on one side of the driving backplane, and the light emitting device 22 is connected to the connection pin 121 .
  • the protective layer 131 can be corroded by low-concentration sulfuric acid to remove the protective layer 131 to expose the connection pins 121 ; moreover, the low-concentration sulfuric acid will not damage the connection pins 121 .
  • the flux is printed on the side of the driving backplane by stencil printing and then a certain pressure is applied to paste the light-emitting device 22, that is, the light-emitting device 22 is pasted to the side of the driving backplane by "mass transfer";
  • the light emitting device 22 is connected to the connection pin 121, specifically, the light emitting device 22 has an anode and a cathode, the anode of the light emitting device 22 can be connected to the connection pin 121 connected to the source, and the cathode of the light emitting device 22 can be connected to the ground wire 83 connection pin 121 connection.
  • exemplary embodiments of the present disclosure provide a display device, as shown in FIG. 20 , which is manufactured by the above-mentioned method for manufacturing a display device.
  • the display device can include a driving backplane, a light emitting device 22 arranged on one side of the driving backplane, the light emitting device 22 can be a micro light emitting diode, and the micro light emitting diode can be a micro light emitting diode (Micro Light-Emitting Diode), and the chip size is reduced to Below 50 ⁇ m; it can also be a sub-millimeter light-emitting diode (Mini Light-Emitting Diode), which is an LED device with a chip size between 50 and 200 ⁇ m.
  • a driving backplane a light emitting device 22 arranged on one side of the driving backplane
  • the light emitting device 22 can be a micro light emitting diode
  • the micro light emitting diode can be a micro light emitting diode (Micro Light-Emitting Diode)
  • the chip size is reduced to Below 50 ⁇ m; it can also be a sub-millimeter light-emitting di
  • a circuit board 23 is also provided on the side of the driving backplane away from the light-emitting device 22.
  • the circuit board 23 is provided with connection pads, controllers and various components, and the controller and various components are electrically connected to the connection pads.
  • the pad is connected to the third conductive portion 1713 of the conductive strip 171 , and their connection can be bonded with an anisotropic conductive adhesive.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. The specific use of the corresponding selection, will not repeat them here.

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Abstract

一种驱动背板及其制备方法、显示装置及其制备方法；驱动背板的制备方法包括：提供一衬底基板（1），衬底基板（1）具有相对设置的第一面（101）和第二面（102），第一面（101）和第二面（102）之间连接有侧面（103）；在第一面（101）形成柔性膜层（16），并对柔性膜层（16）进行图案化处理形成第一开口部（161），第一开口（161）部包括依次连接的第一部分（1611）、第二部分（1612）和第三部分（1613）；将部分柔性膜层（16）折弯至第二面（102），以使第一部分（1611）与第一面（101）相对，第二部分（1612）与侧面（103）相对，第三部分（1613）与第二面（102）相对；以柔性膜层（16）为掩模，在柔性膜层（16）远离衬底基板（1）的一侧形成导电层（17），且导电层（17）形成在至少部分第一开口部（161）内以形成导电条（171）；至少去除导电条（171）周围的柔性膜层（16）和导电层（17）。该制备方法工艺简单、精度较高、不会产生刻蚀异物。

Description

驱动背板及其制备方法、显示装置及其制备方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种驱动背板及驱动背板的制备方法、包括该驱动背板的显示装置及显示装置的制备方法。
背景技术
MLED(Micro Light-Emitting Diode，微型发光二极管；或Mini Light-Emitting Diode，次毫米发光二极管)显示装置在亮度、分辨率、对比度、能耗、使用寿命、响应速度和热稳定性等方面具有很大的优势，因此，使用范围越来越广。
但是，目前MLED的侧边引线工艺很难满足客户的要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种驱动背板及驱动背板的制备方法、包括该驱动背板的显示装置及显示装置的制备方法。
根据本公开的一个方面，提供了一种驱动背板的制备方法，包括：
提供一衬底基板，所述衬底基板具有相对设置的第一面和第二面，所述第一面和所述第二面之间连接有侧面；
在所述第一面形成柔性膜层，并对所述柔性膜层进行图案化处理形成第一开口部，所述第一开口部包括依次连接的第一部分、第二部分和第三部分；
将部分所述柔性膜层折弯至所述第二面，以使所述第一部分与所述第一面相对，所述第二部分与所述侧面相对，所述第三部分与所述第二面相对；
以所述柔性膜层为掩模，在所述柔性膜层远离所述衬底基板的一侧 形成导电层，且所述导电层形成在至少部分所述第一开口部内以形成导电条；
至少去除所述导电条周围的所述柔性膜层和所述导电层。
在本公开的一种示例性实施例中，在对所述柔性膜层进行图案化处理之前，所述制备方法还包括：
在所述柔性膜层远离所述衬底基板的一侧形成隔离层；
对所述柔性膜层进行图案化处理的同时对所述隔离层进行图案化处理，以使所述隔离层形成第二开口部，且对所述隔离层进行图案化处理的速率小于对所述柔性膜层进行图案化处理的速率，以使所述隔离层靠近所述第二开口部的一侧形成突出于所述柔性膜层的突出部。
在本公开的一种示例性实施例中，所述隔离层的材质是无机物，所述柔性膜层的材质是有机物。
在本公开的一种示例性实施例中，在对所述柔性膜层进行图案化处理之后，所述制备方法还包括：
去除部分所述衬底基板，以使所述第二部分和所述第三部分在第一平面的正投影与所述衬底基板在所述第一平面的正投影无交叠，所述第一平面与所述衬底基板平行。
在本公开的一种示例性实施例中，在去除部分所述衬底基板之前，所述制备方法还包括：
将所述柔性膜层向远离所述第二面一侧折弯，使得部分所述柔性膜层与所述衬底基板分离。
在本公开的一种示例性实施例中，在去除部分所述衬底基板之后，所述制备方法还包括：
对所述侧面与所述第一面连接的棱边和所述侧面与所述第二面连接的棱边进行处理形成倒角。
在本公开的一种示例性实施例中，所述至少去除所述导电条周围的所述柔性膜层和所述导电层，包括：
将所述柔性膜层从所述第二面、所述端面以及至少部分所述第一面剥离；
至少切除所述导电条周围的的所述柔性膜层和所述导电层。
在本公开的一种示例性实施例中，在将部分所述柔性膜层折弯至所述第二面之后，所述制备方法还包括：
在所述柔性膜层的折弯至所述第二面的端部施加设定拉力，以使所述柔性膜层与所述衬底基板贴合。
在本公开的一种示例性实施例中，在对所述柔性膜层进行图案化处理形成第一开口部之后，所述制备方法还包括：
在所述衬底基板的一侧形成多个阵列排布的开关单元和多个连接导线，所述连接导线连接于所述开关单元与所述导电条之间；
在所述开关单元远离所述衬底基板的一侧形成金属层，所述金属层连接至所述开关单元；
在所述金属层远离所述衬底基板的一侧形成保护材料层；
依次对所述保护材料层和所述金属层进行图案化处理，所述保护材料层形成保护层，所述金属层形成连接引脚；
在所述保护层远离衬底基板的一侧形成绝缘层组，并对所述绝缘层组进行图案化处理形成过孔，所述过孔连通至所述保护层。
在本公开的一种示例性实施例中，所述保护材料层的材质是氧化物。
在本公开的一种示例性实施例中，所述保护材料层的设定刻蚀量大于所述金属层的设定刻蚀量，以使依次对所述保护材料层和所述金属层进行图案化处理后，所述保护层在所述衬底基板上的正投影，位于所述连接引脚远离所述衬底基板的一面在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，在所述开关单元远离所述衬底基板的一侧形成金属层之前，所述制备方法还包括：
在所述开关单元远离所述衬底基板的一侧形成所述第一导电层，所述金属层形成在所述第一导电层远离所述衬底基板的一侧；
在对所述金属层进行图案化处理的同时，对所述第一导电层进行图案化处理形成导电引脚。
根据本公开的另一个方面，提供了一种驱动背板，所述驱动背板通上述任意一项所述的制备方法制备而成。
在本公开的一种示例性实施例中，所述驱动背板包括：
衬底基板，具有相对设置的第一面和第二面，所述第一面和所述第 二面之间连接有侧面；
柔性膜层，设于所述第一面；
缓冲层，设于所述柔性膜层远离所述衬底基板的一侧；
导电条，设于所述衬底基板的至少一端部，所述导电条包括依次连接的第一导电部分、第二导电部分和第三导电部分，所述第一导电部分设于所述第一面，所述第二导电部分设于所述侧面，所述第三导电部分设于所述第二面。
在本公开的一种示例性实施例中，所述驱动背板还包括：
隔离层，设于所述柔性膜层与所述缓冲层之间。
在本公开的一种示例性实施例中，所述驱动背板还包括：
多个阵列排布的开关单元和多个连接导线，设于所述缓冲层远离所述衬底基板的一侧，所述连接导线连接于所述开关单元与所述导电条之间；
连接引脚，设于所述开关单元远离所述衬底基板的一侧，所述连接引脚连接至所述开关单元；
保护层，设于所述连接引脚远离所述衬底基板的一侧；
绝缘层组，设于所述保护层远离衬底基板的一侧，所述绝缘层组设置有过孔，所述过孔连通至所述保护层。
根据本公开的另一个方面，提供了一种显示装置的制备方法，包括：
通过上述任意一项所述的驱动背板的制备方法制备形成驱动背板；
去除至少部分保护层，以使至少部分所述连接引脚裸露；
在所述驱动背板的一侧安装发光器件，所述发光器件与所述连接引脚连接。
根据本公开的另一个方面，提供了一种显示装置，通过上述所述的显示装置的制备方法制备而成。
在本公开的一种示例性实施例中，所述发光器件为微型发光二极管。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开驱动背板的制备方法一示例实施方式的流程示意框图。
图2为本公开驱动背板的制备方法中对柔性膜层进行图案化处理后的结构示意图。
图3为本公开驱动背板的制备方法中对柔性膜层和隔离层进行图案化处理后的局部剖视结构示意图。
图4-图9为本公开驱动背板的制备方法中在显示区形成开关单元的各个步骤的结构示意图。
图10-图16为本公开驱动背板的制备方法中侧边引线工艺各个步骤的结构示意图。
图17为本公开驱动背板一示例实施方式的结构示意图。
图18为本公开显示装置的制备方法一示例实施方式的流程示意框图。
图19为本公开驱动背板去除保护层后的结构示意图。
图20为本公开显示装置一示例实施方式的结构示意图。
附图标记说明：
1、衬底基板；101、第一面；102、第二面；103、侧面；1a、衬底母板；
2、遮光层；3、缓冲层；
4、有源层；41、导体部；42、沟道部；
5、栅绝缘层；6、栅极；61、连接线；
7、层间介电层；71、第一过孔；72、第二过孔；
81、源极；82、漏极；83、地线；
9、第一平坦化层；91、第三过孔；92、第四过孔；
10、第一绝缘层；1001、第五过孔；1002、第六过孔；
11、第一导电层；111、导电引脚；
12、金属层；121、连接引脚；
13、保护材料层；131、保护层；
14、第二绝缘层；15、第二平坦化层；151、第七过孔；152、第八过孔；
16、柔性膜层；161、第一开口部；1611、第一部分；1612、第二部分；1613、第三部分；
17、导电层；171、导电条；1711、第一导电部分；1712、第二导电部分；1713、第三导电部分；
18、光刻胶；19、连接部；
20、隔离层；201、突出部；202、第二开口部；
21、遮挡板；22、发光器件；23、电路板；
AA、显示区；FA、非显示区。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括 在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，可以在衬底基板的需要形成侧边引线的端部进行3D溅射形成导电层，然后通过激光刻蚀形成侧边导电条，但是激光的宽度较大，因此，刻蚀精度欠佳，不适合精度要求较高的产品；而且，激光烧蚀导电层后形成的固体颗粒不容易去除，可能会落至显示区AA影响显示，有可能附着在导电条上影响导电效果；另外，也可以采用一次性的掩模板作为掩模，然后进行3D溅射形成导电条，但是掩模板需要进行对位，增加了对位工艺，从而增加了成本、降低了效率。
另外，MLED的瓶颈工艺在于减小拼缝距离，拼缝距离又受到侧边引线工艺等技术限制。侧边引线工艺的改进对于减小拼缝尺寸非常有利。
本公开示例实施方式提供了一种驱动背板的制备方法，参照图1所示，该制备方法可以包括以下步骤：
步骤S10，提供一衬底基板1，所述衬底基板1具有相对设置的第一面101和第二面102，所述第一面101和所述第二面102之间连接有侧面103。
步骤S20，在所述第一面101形成柔性膜层16，并对所述柔性膜层16进行图案化处理形成第一开口部161，所述第一开口部161包括依次连接的第一部分1611、第二部分1612和第三部分1613。
步骤S30，将部分所述柔性膜层16折弯至所述第二面102，以使所述第一部分1611与所述第一面101相对，所述第二部分1612与所述侧面103相对，所述第三部分1613与所述第二面102相对。
步骤S40，以所述柔性膜层16为掩模，在所述柔性膜层16远离所述衬底基板1的一侧形成导电层17，且所述导电层17形成在至少部分所述第一开口部161内以形成导电条171。
步骤S50，至少去除所述导电条171周围的所述柔性膜层16和所述导电层17。
本公开的驱动背板及其制备方法，以形成在衬底基板一侧的柔性膜层16为掩模直接在衬底基板1的至少一端形成侧边的导电条171，不需 要对位工艺，从而简化工艺，进而降低成本、提高效率；而且图案化处理精度较高，因此形成的导电条171的精度较高，能够满足高精度产品的要求；另外，图案化处理不会产生刻蚀异物，不会由于刻蚀异物影响显示效果和导电效果。
下面对驱动背板的制备方法的各个步骤进行详细说明。
步骤S10，提供一衬底基板1，所述衬底基板1具有相对设置的第一面101和第二面102，所述第一面101和所述第二面102之间连接有侧面103。
在本示例实施方式中，参照图2所示，衬底母板1a设置的较大，可以在一个衬底母板1a上形成多个驱动背板的其他结构，图中虚线为一个驱动背板所占衬底母板1a的区域。将衬底母板1a切割后形成多个衬底基板1。
衬底基板1可以设置为矩形板，衬底基板1具有相对设置的第一面101和第二面102，第一面101和第二面102均是矩形；在第一面101和第二面102之间连接有四个侧面103，四个侧面103均是长方形。当然，在本公开的其他示例实施方式中，衬底基板1可以设置为圆形板或椭圆形板，这种情况下，第一面101和第二面102均是圆形或椭圆形，连接在第一面101和第二面102之间的侧面103为一个；衬底基板1还可以是其他形状，在此不一一说明。
衬底基板1可以包括显示区AA和非显示区FA，显示区AA与非显示区FA连接。需要说明的是图中对显示区AA和非显示区FA的划分只是示意性的，为了方便理解，并不构成对本公开的限定。
衬底基板1的材料可以包括无机材料，例如，该无机材料可以为玻璃、石英或金属等。衬底基板1的材料还可以包括有机材料，例如，该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。该衬底基板1可以由多层材料层形成，例如衬底基板1可以包括多层基底层，基底层的材料可以是上述的任意一种材料。当然，衬底基板1还可以设置为单层，可以是上述任一一种材料。
步骤S20，在所述第一面101形成柔性膜层16，并对所述柔性膜层 16进行图案化处理形成第一开口部161，所述第一开口部161可以包括依次连接的第一部分1611、第二部分1612和第三部分1613。
在本示例实施方式中，参照图2所示，在衬底基板1的第一面101通过涂覆工艺形成柔性膜层16。柔性膜层16的材质可以有机物，包括但不限于PI(聚酰亚胺)，柔性膜层16的厚度可以大于等于5微米且小于等于20微米。
参照图3所示，在柔性膜层16远离衬底基板1的一侧通过沉积、溅射等工艺形成隔离层20。对隔离层20进行图案化处理的速率小于对柔性膜层16进行图案化处理的速率。图案化处理的速率可以是刻蚀速率，即对隔离层20的刻蚀速率小于对柔性膜层16的刻蚀速率。
隔离层20的厚度可以大于等于0.5微米且小于等于2微米。隔离层20的材质可以是无机物，包括但不限于金属，具体例如，可以是Al、Mo等等，隔离层20的材质还可以氧化硅、氮化硅、氮氧化硅等等。当然，隔离层20还可以是其他材质，只要对隔离层20进行图案化处理的速率小于对柔性膜层16进行图案化处理的速率即可。无机物的隔离层20在后续工艺的多次折弯过程中不容易折断。
需要说明的是，在本公开的另外一些示例实施方式中，在柔性膜层16远离衬底基板1的一侧可以不形成隔离层20。即形成柔性膜层16后，直接对柔性膜层16进行图案化处理。
柔性膜层16和隔离层20可以覆盖整个衬底母板1a，然后在后续图案化处理的过程中去除不需要的部分。
参照图3所示，对柔性膜层16以及隔离层20进行图案化处理对应形成第一开口部161和第二开口部202，具体为：在隔离层20的远离衬底基板1的一侧形成光刻胶18层，在光刻胶18层的远离衬底基板1的一侧安放掩模板，然后光照光刻胶层18，并对光刻胶层18进行显影，以去除被光照的光刻胶18；最后以光刻胶层18为掩模对柔性膜层16和隔离层20进行刻蚀。
可以先对隔离层20进行预刻蚀，在隔离层20上形成一个较小的第二开口部；然后，采用与上述刻蚀不同的气体对柔性膜层16进行刻蚀，刻蚀柔性膜层16的气体对隔离层20的刻蚀速率很小，参照图3所示， 由于，对隔离层20进行刻蚀的速率小于对柔性膜层16进行刻蚀的速率，因此，在相同的刻蚀时间后，对柔性膜层16的刻蚀量大于对隔离层20的刻蚀量，使得隔离层20在第二开口部202形成突出于柔性膜层16突出部201，即第二开口部202小于第一开口部161，第二开口部202的边沿位于与第一开口部161的边沿内。
参照图2所示，第一开口部161可以是多个过孔，该过孔可以是长条形；该过孔可以包括第一部分1611、第二部分1612和第三部分1613；第二部分1612连接于第一部分1611和第三部分1613之间，第一部分1611和第三部分1613远离第二部分1612的端部可以设置为正方形过孔，第二部分1612可以设置为长方形过孔。
另外，在本公开的另外一些示例实施方式中，第一开口部161也可以是缺口(即不封闭的开口)，缺口可以是长条形；缺口的具体形状与上述过孔可以相同，只是第三部分1613的远离第二部分1612的一侧设置为开口状，使得整个第一开口部161形成为具有缺口的开口部；还有，第一部分1611和第三部分1613远离第二部分1612的端部可以设置为圆形过孔或椭圆形过孔。
在对柔性膜层16以及隔离层20进行图案化处理对应形成第一开口部161和第二开口部202的同时，可以去除其他区域的柔性膜层16和隔离层20，例如，可以去除部分显示区AA的柔性膜层16和隔离层20，即保留位于显示区AA的部分柔性膜层16和隔离层20。保留部分柔性膜层16和隔离层20可以防止侧边引线工艺的时候柔性膜层16和隔离层20被拉扯掉。
在本示例实施方式中，参照图4所示，完成对柔性膜层16以及隔离层20的图案化处理之后，可以在衬底基板的第一面形成遮光层2；然后可以在位于显示区AA的隔离层20远离衬底基板1的一侧以及遮光层2远离衬底基板1的一侧形成缓冲层3，通过缓冲层3将隔离层20覆盖。当然，在将柔性膜层16和隔离层20没有形成在显示区AA的情况下，可以在遮光层2远离衬底基板1的一侧形成缓冲层3；在没有形成隔离层20的情况下，可以在柔性膜层16远离衬底基板1的一侧以及遮光层2远离衬底基板1的一侧形成缓冲层3。
在缓冲层3的远离衬底基板1的一侧形成多个阵列排布的开关单元和多个连接导线。开关单元可以包括电容和至少两个薄膜晶体管，薄膜晶体管可以包括有源层4、栅极6、源极81以及漏极；具体来讲，在缓冲层3的远离衬底基板1的一侧形成有源层4，有源层4可以包括沟道部42以及设置在沟道部42两端的导体部41，在有源层4的远离衬底基板1的一侧形成有栅绝缘层5，在栅绝缘层5的一侧形成有栅极6，形成栅极6的同时在缓冲层3的远离衬底基板1的一侧形成连接线61，在栅极6的远离衬底基板1的一侧形成有层间介电层7，在层间介电层7上形成有第一过孔71和第二过孔72，第一过孔71连通至导体部41，第二过孔72连通至连接线61；在层间介电层7的远离衬底基板1的一侧形成有地线83、源极81和漏极82，源极81和漏极82分别通过两个第一过孔71连接至两个导体部41，地线83通过第二过孔72连接至连接线61。
需要说明的是，在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极81”及“漏极82”的功能有时互相调换。因此，在本说明书中，“源极81”和“漏极82”可以互相调换。
连接导线可以包括栅线、数据线、电源线等等；连接导线连接于开关单元与导电条171之间，通过导电条171和连接导线进行电信号的传输，栅线可以在形成栅极6的同时形成，数据线和电源线可以在形成源极81和漏极82的同时形成。
另外，在形成连接导线的同时，形成连接导电条171和连接导线的连接部19，连接部19形成在第一开口部161的第一部分1611的靠近显示区AA的一端和第二开口部202的靠近显示区AA的一端。
在开关单元远离衬底基板1的一侧形成有第一平坦化层9，在第一平坦化层9上形成有第三过孔91和第四过孔92；在第一平坦化层9远离衬底基板1的一侧形成有第一绝缘层10，在第一绝缘层10上形成有第五过孔和第六过孔1002。
在绝缘层远离衬底基板1的一侧形成第一导电层11，第一导电层11通过两个第三过孔91连接至源极和漏极，第一导电层11通过第四过孔 92连接至地线83。第一导电层11可以是镍钼合金。第一导电层11可以阻止后续形成的金属层12渗至金属层12之下的膜层。
在第一导电层11远离衬底基板1的一侧沉积形成金属层12，金属层12的材质可以是铜，当然，还可以是其他金属材质；在高温退火工艺时，金属层12容易发生自然氧化，自然氧化后的金属层12的导电性能较差，而且在后续化金工艺过程中，对金的附着力较差，从而影响驱动背板的性能；但是，如果不进行高温退火工艺，会导致薄膜晶体管出现异常，例如，出现转移曲线离散、Vth正偏或负偏等。
在金属层12远离衬底基板1的一侧沉积形成保护材料层13，保护材料层13的材质可以氧化物，例如，可以是IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，氧化铟锡锌)等；IGZO和ITZO与稀酸能够快速反应。当然，保护材料层13还可以是其他氧化物。保护材料层13的厚度大于等于10nm且小于等于50nm。在沉积形成保护材料层13时，不需要加入O2进行反应型溅射，不会对金属层12产生氧化作用。
在高温退火工艺时，保护材料层13可以对金属层12进行保护，避免金属层12发生自然氧化，从而可以对驱动背板进行高温退火工艺，进而避免薄膜晶体管出现转移曲线离散、Vth正偏或负偏等异常。
参照图5-图7所示，在金属层12远离衬底基板1的一侧形成光刻胶18，在光刻胶18远离衬底基板1的一侧安放掩模板，以掩模板为掩模对光刻胶18进行曝光显影，然后以剩余的光刻胶18为掩模依次对保护材料层13、金属层12和第一导电层11进行刻蚀，即先刻蚀保护材料层13形成保护层131，然后刻蚀金属层12和第一导电层11，金属层12刻蚀形成连接引脚121，第一导电层11刻蚀形成导电引脚111。保护材料层13的设定刻蚀量大于金属层12的设定刻蚀量，以使依次对保护材料层13和金属层12进行图案化处理后，保护层131在衬底基板1上的正投影，位于连接引脚121远离衬底基板1的一面在衬底基板1上的正投影之内。
由于金属层12的厚度较厚，在对金属层12进行刻蚀的时候，刻蚀时间较长，容易形成上部较小下部较大的圆台或棱台结构，例如，金属 层12刻蚀形成圆台形的连接引脚121，连接引脚121远离衬底基板1的一面的直径为R1，连接引脚121靠近衬底基板1的一面的直径为R2，且R1小于R2。如果保护材料层13还保持与金属层12相同的设定刻蚀量，例如，保护材料层13可以刻蚀形成圆形板，圆形板的直径为R2，保护层131的直径大于连接引脚121远离衬底基板1的一面的直径R1，使得保护层131的边沿会突出于连接引脚121的边沿，在后续沉积形成第二绝缘层14的时候，第二绝缘层14容易断裂，从而无法对连接引脚121进行绝缘保护。
需要说明的是，刻蚀量指的是与衬底基板1朝向金属层12的表面平行的方向上的刻蚀量。
因此，在对保护材料层13进行刻蚀的时候，尽量保证对保护材料层13有一定的过刻量，即保护材料层13的设定刻蚀量大于金属层12的设定刻蚀量；使得保护层131在衬底基板1上的正投影位于连接引脚121远离衬底基板1的一面在衬底基板1上的正投影之内，即，可以是保护层131在衬底基板1上的正投影与连接引脚121远离衬底基板1的一面在衬底基板1上的正投影完全重合，也可以保护层131在衬底基板1上的正投影位于连接引脚121远离衬底基板1的一面在衬底基板1上的正投影内，也就是保护层131在衬底基板1上的正投影小于连接引脚121远离衬底基板1的一面在衬底基板1上的正投影。
从而可以在后续形成第二绝缘层14的时候，避免第二绝缘层14断裂，从而使得第二绝缘层14能够对连接引脚121进行绝缘保护。
参照图8所示，去除光刻胶18。参照图9所示，在保护层131远离衬底基板的一侧形成第二绝缘层14，在第二绝缘层14远离衬底基板的一侧形成第二平坦化层15，并对第二平坦化层15和第二绝缘层14进行图案化处理形成第七过孔151和第八过孔152，第七过孔151可以连通至源极81，第八过孔152可以连通至地线83。
完成开关单元等等的制备后，可以将衬底母板1a切割形成多个衬底基板1，然后进行侧边引线工艺。
步骤S30，将部分所述柔性膜层16折弯至所述第二面102，以使所述第一部分1611与所述第一面101相对，所述第二部分1612与所述侧 面103相对，所述第三部分1613与所述第二面102相对。
在本示例实施方式中，参照图10所示，将柔性膜层16以及隔离层20向远离第二面102一侧折弯，使得部分柔性膜层16与衬底基板1分离；然后，参照图11所示，可以通过切割方法去除裸露的部分衬底基板1，使柔性膜层16的一端突出于衬底基板1，即使得柔性膜层16展平后，第二部分1612和第三部分1613在第一平面的正投影与衬底基板1在第一平面的正投影无交叠，第一平面是与衬底基板1平行的平面。最后，参照图12所示，对衬底基板1的侧面103进行磨边，使得衬底基板1的侧面103与第一面101连接的棱边形成有倒角，衬底基板1的侧面103与第二面102连接的棱边也形成有倒角；上述倒角可以是斜倒角，也可以是圆倒角。倒角使得第一面101与侧面103以及第二面102与侧面103之间的连接较为平缓，后续形成的导电层17的从第一面101折弯至侧面103，以及从侧面103折弯至第二面102也会较为平缓，避免导电层17形成角度较小的折弯拐角而容易折断。
在本示例实施方式中，参照图13所示，将柔性膜层16以及隔离层20的远离显示区AA的一端折弯至第二面102，并使第一开口部161的第一部分1611与第一面101相对，第一开口部161的第二部分1612与侧面103相对，第一开口部161的第三部分1613与第二面102相对。
可以对柔性膜层16以及隔离层20施加设定的拉力，即对柔性膜层16折弯至第二面102的一端施加与衬底基板1平行的拉力，使得折弯后的柔性膜层16与衬底基板1完全贴合，避免柔性膜层16与衬底基板1形成有间隙。在柔性膜层16与衬底基板1形成有间隙的情况下，后续形成导电层17时，导电材料不仅会沉积在没有被柔性膜层16覆盖的衬底基板1上，还会通过间隙形成在被柔性膜层16覆盖的衬底基板1上，从而影响后续形成的导电层17的精度；而且在相邻两个第一开口部161之间的间距较小的情况下，形成的两个导电条171可能会连接在一起，导致两个导电条171产生短路。柔性膜层16与衬底基板1完全贴合，即可避免上述不良的发生。
步骤S40，以所述柔性膜层16为掩模，在所述柔性膜层16远离所述衬底基板1的一侧形成导电层17，且所述导电层17形成在至少部分 所述第一开口部161内以形成导电条171。
在本示例实施方式中，参照图13所示，图中箭头所示为溅射方向，以柔性膜层16为掩模，即将柔性膜层16作为遮挡层；且在显示区AA设置两个遮挡板21，一个遮挡板21设置在衬底基板的第二面，另一个遮挡板21设置在保护层131的远离衬底基板的一侧，避免导电材料形成在显示区AA。在柔性膜层16远离衬底基板1的一侧，主要是设置第一开口部161的柔性膜层16的远离衬底基板1的一侧设置溅射装置，溅射装置可以设置多个，多个溅射装置形成一个半包围将衬底基板1的需要形成导电条171的端部包围，多个溅射装置从多个方向向柔性膜层16的第一开口部161溅射导电材料，导电材料形成导电层17，形成在第一开口部161内的导电层为导电条171。
导电层17可以是三层结构，第一层为钛，第二层为铜，第三层为钛；可以在一次溅射工艺中分三个时段溅射形成。
参照图14所示，导电条171可以包括依次连接的第一导电部分1711、第二导电部分1712以及第三导电部分1713，第一导电部分1711形成在第一开口部161的第一部分1611内，且位于第一面101；第一导电部分1711的远离第二导电部分1712的面积较大，可以作为连接焊盘。第二导电部分1712形成在第一开口部161的第二部分1612内，且位于侧面103；第三导电部分1713形成在第一开口部161的第三部分1613内，且位于第二面102，第三导电部分1713的远离第二导电部分1712的面积较大，也可以作为连接焊盘。
参照图14所示，由于设置有隔离层20，隔离层20经过图案化处理后形成突出于柔性膜层16形成突出部201，在溅射形成导电层17和导电条171时，由于突出部201的遮挡，使得形成在隔离层20远离衬底基板一侧的导电层17与形成在第一开口部161内的导电条171断裂，在后续剥离柔性膜层16的时候，柔性膜层16不会将导电条171带离，从而保证导电条171的稳定性。
步骤S50，至少去除所述导电条171周围的所述柔性膜层16和所述导电层17。
在本示例实施方式中，参照图15所示，将柔性膜层16从第二面102、 端面以及部分第一面101剥离，至少使得形成有第一开口部161的一部分柔性膜层16从衬底基板1上剥离；然后，参照图16所示，切除剥离的柔性膜层16和导电层17；从而使得导电条171周围的柔性膜层16和导电层17被去除；而导电条171仍然附着在衬底基板1的第一面101、端面和第二面102。
当然，在本公开的其他一些示例实施方式中，在柔性膜层16和导电层17没有设置在显示区AA的情况下，也可以将柔性膜层16和导电层17完全剥离去除，仅保留导电条171。
至此完成驱动背板的制备，通过上述方法制备导电条171，不需要对位，从而简化工艺，进而降低成本；而且，形成的导电条171精度较高，不会产生刻蚀异物。
需要说明的是，尽管在附图中以特定顺序描述了本公开中驱动背板的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
基于同一发明构思，本公开示例实施方式提供了一种驱动背板，参照图17所示，该驱动背板通过上述任意一项所述的制备方法制备而成。
具体来讲，该驱动背板可以包括衬底基板1，设置在衬底基板1一侧的遮光层2和柔性膜层16，在柔性膜层16远离衬底基板1的一侧设置有隔离层20，柔性膜层16设置有第一开口部161，隔离层2设置有第二开口部202，第二开口部202与第一开口部161相对设置，第二开口部202和第一开口部161内设置有连接部19。在衬底基板1的设有连接部19的端部设置有导电条171，导电条171与连接部19一一对应地连接。当然，也可以不设置隔离层20。
导电条171包括依次连接的第一导电部分1711、第二导电部分1712和第三导电部分1713，第一导电部分1711设于第一面101，第二导电部分1712设于侧面103，第三导电部1713分设于第二面102。第一导电部分1711与连接部19连接。
在遮光层2远离衬底基板1的一侧和隔离层远离衬底基板1的一侧 设置有缓冲层3。在不设置隔离层20的情况下，在遮光层2远离衬底基板1的一侧和柔性膜层16远离衬底基板1的一侧设置有缓冲层3。
在缓冲层3的远离衬底基板1的一侧设置多个阵列排布的开关单元和多个连接导线。开关单元可以包括电容和至少两个薄膜晶体管，薄膜晶体管可以包括有源层4、栅极6、源极81以及漏极；具体来讲，在缓冲层3的远离衬底基板1的一侧设置有源层4和连接线61，有源层4可以包括沟道部42以及设置在沟道部42两端的导体部41，在有源层4的远离衬底基板1的一侧设置有栅绝缘层5，在栅绝缘层5的一侧设置有栅极6，在栅极6的远离衬底基板1的一侧设置有层间介电层7，在层间介电层7上设置有第一过孔71和第二过孔72，第一过孔71连通至导体部41，第二过孔72连通至连接线61；在层间介电层7的远离衬底基板1的一侧设置有地线83、源极81和漏极82，源极81和漏极82分别通过两个第一过孔71连接至两个导体部41，地线83通过第二过孔72连接至连接线61，将地线83设置为双层结构可以减小电阻，而且在一条线断路的情况下，另一条线可以进行信号传输，不影响显示。
需要说明的是，本说明书中说明的薄膜晶体管为顶栅型薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是底栅型或双栅型，对其具体结构在此不再赘述。
连接导线可以包括栅线、数据线、电源线等等；连接导线连接于开关单元与连接部19之间，通过导电条171、连接部19和连接导线进行电信号的传输。
在开关单元远离衬底基板1的一侧设置有第一平坦化层9，在第一平坦化层9上设置有多个第三过孔91和第四过孔92；在第一平坦化层9远离衬底基板1的一侧设置有第一绝缘层10，在第一绝缘层10上设置有多个第五过孔1001和第六过孔1002。
在第一绝缘层10远离衬底基板1的一侧设置有导电引脚111，两个导电引脚111通过均第三过孔91和第五过孔1001分别连接至源极81和漏极82，另一个导电引脚111通过第四过孔92和第六过孔1002连接至地线83。导电引脚111可以是镍钼合金。
在导电引脚1111远离衬底基板1的一侧设置有连接引脚121，连接 引脚121的材质可以是铜。
在连接引脚121远离衬底基板1的一侧设置有保护层131，保护层131的材质可以氧化物，例如，可以是IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，氧化铟锡锌)等。
在保护层131远离衬底基板的一侧设有第二绝缘层14，在第二绝缘层14远离衬底基板的一侧设有第二平坦化层15，第二平坦化层15和第二绝缘层14形成绝缘层组，绝缘层组上设有第七过孔151和第八过孔152，第七过孔151可以连通至源极81，第八过孔152可以连通至地线83。
基于同一发明构思，本公开示例实施方式提供了一种显示装置的制备方法，参照图18所示，该制备方法可以包括以下步骤：
步骤S510，通过上述任意一项所述的驱动背板的制备方法制备形成驱动背板。
步骤S520，去除至少部分保护层131，以使至少部分所述连接引脚121裸露。
步骤S530，在驱动背板的一侧安装发光器件22，所述发光器件22与所述连接引脚121连接。
驱动背板的制备过程上述已经进行了详细说明，因此，此处不再赘述。
在本示例实施方式中，参照图19所示，可以通低浓度的硫酸腐蚀保护层131，以去除保护层131使连接引脚121裸露；而且，低浓度的硫酸不会损伤连接引脚121。
参照图20所示，在驱动背板的一侧通过钢网印刷助焊剂然后施加一定的压力粘贴发光器件22，也就是通过“巨量转移”将发光器件22粘贴到驱动背板的一侧；发光器件22与连接引脚121连接，具体地，发光器件22具有阳极和阴极，发光器件22的阳极可以与连接至源极的连接引脚121连接，发光器件22的阴极可以与连接至地线83的连接引脚121连接。
基于同一发明构思，本公开示例实施方式提供了一种显示装置，参照图20所示，该显示装置通过上述所述的显示装置的制备方法制备而成。
该显示装置可以包括驱动背板，设于驱动背板一侧的发光器件22，发光器件22可以是微型发光二极管，微型发光二极管可以是微型发光二极管(Micro Light-Emitting Diode)，芯片尺寸缩减至50μm以下；也可以是次毫米发光二极管(Mini Light-Emitting Diode)，是芯片尺寸介于50～200μm之间的LED器件。
在驱动背板远离发光器件22的一侧还设置有电路板23，电路板23设置有连接焊盘、控制器和各种元器件，控制器和各种元器件电连接至连接焊盘，连接焊盘与导电条171的第三导电部1713连接，它们的连接可以采用各向异性导电胶粘接。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，还可以包括其他必要的部件和组成，以显示器为例，具体例如外壳、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种驱动背板的制备方法，其中，包括：
    提供一衬底基板，所述衬底基板具有相对设置的第一面和第二面，所述第一面和所述第二面之间连接有侧面；
    在所述第一面形成柔性膜层，并对所述柔性膜层进行图案化处理形成第一开口部，所述第一开口部包括依次连接的第一部分、第二部分和第三部分；
    将部分所述柔性膜层折弯至所述第二面，以使所述第一部分与所述第一面相对，所述第二部分与所述侧面相对，所述第三部分与所述第二面相对；
    以所述柔性膜层为掩模，在所述柔性膜层远离所述衬底基板的一侧形成导电层，且所述导电层形成在至少部分所述第一开口部内以形成导电条；
    至少去除所述导电条周围的所述柔性膜层和所述导电层。
  2. 根据权利要求1所述的驱动背板的制备方法，其中，在对所述柔性膜层进行图案化处理之前，所述制备方法还包括：
    在所述柔性膜层远离所述衬底基板的一侧形成隔离层；
    对所述柔性膜层进行图案化处理的同时对所述隔离层进行图案化处理，以使所述隔离层形成第二开口部，且对所述隔离层进行图案化处理的速率小于对所述柔性膜层进行图案化处理的速率，以使所述隔离层在所述第二开口部形成突出于所述柔性膜层的突出部。
  3. 根据权利要求2所述的驱动背板的制备方法，其中，所述隔离层的材质是无机物，所述柔性膜层的材质是有机物。
  4. 根据权利要求1所述的驱动背板的制备方法，其中，在对所述柔性膜层进行图案化处理之后，所述制备方法还包括：
    去除部分所述衬底基板，以使所述第二部分和所述第三部分在第一平面的正投影与所述衬底基板在所述第一平面的正投影无交叠，所述第一平面与所述衬底基板平行。
  5. 根据权利要求4所述的驱动背板的制备方法，其中，在去除部分所述衬底基板之前，所述制备方法还包括：
    将所述柔性膜层向远离所述第二面一侧折弯，使得部分所述柔性膜层与所述衬底基板分离。
  6. 根据权利要求4所述的驱动背板的制备方法，其中，在去除部分所述衬底基板之后，所述制备方法还包括：
    对所述侧面与所述第一面连接的棱边和所述侧面与所述第二面连接的棱边进行处理形成倒角。
  7. 根据权利要求6所述的驱动背板的制备方法，其中，所述至少去除所述导电条周围的所述柔性膜层和所述导电层，包括：
    将所述柔性膜层从所述第二面、所述端面以及至少部分所述第一面剥离；
    至少切除所述导电条周围的的所述柔性膜层和所述导电层。
  8. 根据权利要求1所述的驱动背板的制备方法，其中，在将部分所述柔性膜层折弯至所述第二面之后，所述制备方法还包括：
    在所述柔性膜层的折弯至所述第二面的端部施加设定拉力，以使所述柔性膜层与所述衬底基板贴合。
  9. 根据权利要求1所述的驱动背板的制备方法，其中，在对所述柔性膜层进行图案化处理形成第一开口部之后，所述制备方法还包括：
    在所述衬底基板的一侧形成多个阵列排布的开关单元和多个连接导线，所述连接导线连接于所述开关单元与所述导电条之间；
    在所述开关单元远离所述衬底基板的一侧形成金属层，所述金属层连接至所述开关单元；
    在所述金属层远离所述衬底基板的一侧形成保护材料层；
    依次对所述保护材料层和所述金属层进行图案化处理，所述保护材料层形成保护层，所述金属层形成连接引脚；
    在所述保护层远离衬底基板的一侧形成绝缘层组，并对所述绝缘层组进行图案化处理形成过孔，所述过孔连通至所述保护层。
  10. 根据权利要求9所述的驱动背板的制备方法，其中，所述保护材料层的材质是氧化物。
  11. 根据权利要求9所述的驱动背板的制备方法，其中，所述保护材料层的设定刻蚀量大于所述金属层的设定刻蚀量，以使依次对所述保 护材料层和所述金属层进行图案化处理后，所述保护层在所述衬底基板上的正投影，位于所述连接引脚远离所述衬底基板的一面在所述衬底基板上的正投影之内。
  12. 根据权利要求9所述的驱动背板的制备方法，其中，在所述开关单元远离所述衬底基板的一侧形成金属层之前，所述制备方法还包括：
    在所述开关单元远离所述衬底基板的一侧形成所述第一导电层，所述金属层形成在所述第一导电层远离所述衬底基板的一侧；
    在对所述金属层进行图案化处理的同时，对所述第一导电层进行图案化处理形成导电引脚。
  13. 一种驱动背板，其中，所述驱动背板通过权利要求1～12任意一项所述的制备方法制备而成。
  14. 根据权利要求13所述的驱动背板，其中，所述驱动背板包括：
    衬底基板，具有相对设置的第一面和第二面，所述第一面和所述第二面之间连接有侧面；
    柔性膜层，设于所述第一面；
    缓冲层，设于所述柔性膜层远离所述衬底基板的一侧；
    导电条，设于所述衬底基板的至少一端部，所述导电条包括依次连接的第一导电部分、第二导电部分和第三导电部分，所述第一导电部分设于所述第一面，所述第二导电部分设于所述侧面，所述第三导电部分设于所述第二面。
  15. 根据权利要求14所述的驱动背板，其中，所述驱动背板还包括：
    隔离层，设于所述柔性膜层与所述缓冲层之间。
  16. 根据权利要求14所述的驱动背板，其中，所述驱动背板还包括：
    多个阵列排布的开关单元和多个连接导线，设于所述缓冲层远离所述衬底基板的一侧，所述连接导线连接于所述开关单元与所述导电条之间；
    连接引脚，设于所述开关单元远离所述衬底基板的一侧，所述连接引脚连接至所述开关单元；
    保护层，设于所述连接引脚远离所述衬底基板的一侧；
    绝缘层组，设于所述保护层远离衬底基板的一侧，所述绝缘层组设 置有过孔，所述过孔连通至所述保护层。
  17. 一种显示装置的制备方法，其中，包括：
    通过权利要求1～12任意一项所述的驱动背板的制备方法制备形成驱动背板；
    去除至少部分保护层，以使至少部分所述连接引脚裸露；
    在所述驱动背板的一侧安装发光器件，所述发光器件与所述连接引脚连接。
  18. 一种显示装置，其中，通过权利要求17所述的显示装置的制备方法制备而成。
  19. 根据权利要求18所述的显示装置，其中，所述发光器件为微型发光二极管。
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US20140152588A1 (en) * 2012-11-30 2014-06-05 Samsung Display Co., Ltd. Flexible touch screen panel and fabricating method thereof
CN112309967A (zh) * 2020-10-16 2021-02-02 深圳市华星光电半导体显示技术有限公司 背光模组及其制作方法
CN112467061A (zh) * 2020-11-25 2021-03-09 京东方科技集团股份有限公司 显示面板的制备方法、显示面板和显示装置
CN113380779A (zh) * 2021-06-08 2021-09-10 京东方科技集团股份有限公司 驱动基板、发光装置及其制备方法

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US20140152588A1 (en) * 2012-11-30 2014-06-05 Samsung Display Co., Ltd. Flexible touch screen panel and fabricating method thereof
CN112309967A (zh) * 2020-10-16 2021-02-02 深圳市华星光电半导体显示技术有限公司 背光模组及其制作方法
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