WO2023109824A1 - 稳压装置 - Google Patents

稳压装置 Download PDF

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Publication number
WO2023109824A1
WO2023109824A1 PCT/CN2022/138736 CN2022138736W WO2023109824A1 WO 2023109824 A1 WO2023109824 A1 WO 2023109824A1 CN 2022138736 W CN2022138736 W CN 2022138736W WO 2023109824 A1 WO2023109824 A1 WO 2023109824A1
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Prior art keywords
switch
voltage
output
gate
terminal
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PCT/CN2022/138736
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English (en)
French (fr)
Inventor
王强
刘子白
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乐鑫信息科技（上海）股份有限公司
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Publication of WO2023109824A1 publication Critical patent/WO2023109824A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Definitions

  • the present application relates to circuit technology, in particular to a voltage stabilizing device.
  • a low dropout or low dropout regulator (Low Dropout Regulator, LDO Regulator) is a linear regulator used to provide a constant output voltage.
  • LDO voltage regulator has low static power consumption and small area, and can maintain low output impedance and noise, and is widely used in various circuits.
  • the embodiment of the present application provides a voltage stabilizing device, which is used to solve the problem of rapid recovery after the output voltage drops.
  • a voltage stabilizing device has a power supply terminal and an output terminal, wherein a power supply voltage is provided at the power supply terminal of the voltage stabilizing device, and the output terminal is used to connect to a load and provide an output voltage
  • the voltage stabilizing device includes: an NMOS transistor having a drain connected to the power supply terminal of the voltage stabilizing device, a gate and a source connected to the output terminal of the voltage stabilizing device; a first regulating circuit comprising: a voltage dividing circuit, It is connected between the output terminal of the voltage stabilizing device and ground, and the voltage dividing circuit is used to generate a feedback voltage based on the output voltage of the output terminal of the voltage stabilizing device; and an error amplifier having A first input terminal, a second input terminal and an output terminal, wherein a reference voltage is provided at the first input terminal of the error amplifier, the second input terminal is connected to the voltage divider circuit, and the error amplifier The output terminal of the NMOS transistor is connected to the gate
  • the charge pump further includes: a clock input terminal, the charge pump is configured to receive a clock signal through the clock input terminal, and after being turned on, according to the A clock signal increases the voltage at the gate of the NMOS transistor, thereby increasing the output voltage of the voltage regulator.
  • the charge pump further includes: a first switch group including a plurality of switches; a second switch group including a plurality of a switch; a first capacitor coupled with the first switch group between the power supply terminal of the voltage stabilizing device and the ground, and between the output terminal of the charge pump and the ground; A second capacitor, which is coupled with the second switch group between the power supply terminal of the voltage stabilizing device and the ground, and between the output terminal of the charge pump and the ground; wherein, When the charge pump is turned on and the clock signal is a first level signal, the switches in the first switch group and the second switch group are selectively controlled to charge the first capacitor and the second two capacitors are discharged; and when the charge pump is turned on and the clock signal is a second level signal, the switches in the first switch group and the second switch group are selectively controlled to make the first switch group A capacitor is discharged and the second capacitor is charged; and wherein, when the enable control signal is a third level signal, the charge pump
  • the first switch group includes a first switch, a second switch, a third switch, and a fourth switch, wherein the The first end of the first switch is connected to the power supply end of the voltage stabilizing device, the second end of the first switch is connected to the positive pole of the first capacitor, and the negative pole of the first capacitor is connected to the first capacitor.
  • the first end of the second switch is connected, the second end of the second switch is connected to the ground, the first end of the third switch is connected to the power supply end of the voltage stabilizing device, and the third switch
  • the second end of the fourth switch is connected to the negative pole of the first capacitor, the first end of the fourth switch is connected to the positive pole of the first capacitor, the second end of the fourth switch is connected to the The output end of the charge pump is connected; and the second switch group includes a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein the first end of the fifth switch is connected to the voltage stabilizing device connected to the power supply terminal, the second terminal of the fifth switch is connected to the positive pole of the second capacitor, the negative pole of the second capacitor is connected to the first terminal of the sixth switch, and the sixth switch
  • the second end of the seventh switch is connected to the ground, the first end of the seventh switch is connected to the power supply end of the voltage stabilizing device, the second end of the seventh switch is connected to the second capacitor of the second capacitor connected to the negative pole
  • the charge pump further includes: a gate control circuit, which includes the enable control terminal, the clock input terminal, the first An output control terminal and a second output control terminal; wherein, the first output control terminal is connected to the control terminals of the first switch, the second switch, the seventh switch, and the eighth switch, so The second output control terminal is connected to the control terminals of the third switch, the fourth switch, the fifth switch and the sixth switch.
  • a gate control circuit which includes the enable control terminal, the clock input terminal, the first An output control terminal and a second output control terminal; wherein, the first output control terminal is connected to the control terminals of the first switch, the second switch, the seventh switch, and the eighth switch, so The second output control terminal is connected to the control terminals of the third switch, the fourth switch, the fifth switch and the sixth switch.
  • the gate control circuit further includes: a "NOT” gate, a first "NAND” gate, a second “AND” Gate, the third “AND” gate and the fourth "AND” gate; wherein, the first input end of the first "AND” gate is connected to the clock input end, the first "AND” gate of the The second input end is connected to the output end of the second "NAND” gate, the output end of the first "NAND” gate is connected to the first input end of the second "NAND” gate and the third The first input terminal of the "AND” gate; the input terminal of the "NOT” gate is connected to the clock input terminal, and the output terminal of the "NOT” gate is connected to the second of the second "AND” gate.
  • the output terminal of the second "AND” gate is connected to the first input terminal of the fourth "AND” gate; the first input terminal of the third “AND” gate is connected to the fourth "AND” gate The second input end of the “AND” gate is connected to the enable control end, the output end of the third “AND” gate is the first output end of the gate control circuit, and the fourth "AND” gate The output terminal of is the second output terminal of the gate control circuit.
  • the second adjustment circuit further includes: a clock circuit configured to output the clock signal.
  • the second regulating circuit further includes :
  • a hysteretic comparator having a first input, a second input and an output, wherein a first threshold voltage and a second threshold voltage are provided at the first input of the hysteretic comparator, the first The threshold voltage is less than the second threshold voltage, the second input terminal of the hysteresis comparator is connected to the output terminal of the voltage stabilizing device, and the output terminal of the hysteresis comparator is connected to the charge the enable control terminal of the pump; wherein the hysteretic comparator is configured to generate the output signal based on the output voltage, the first threshold voltage, and the second threshold voltage of the voltage stabilizing device, The output signal is used as the enable control signal of the charge pump.
  • the hysteresis comparator is further configured to, when the output voltage of the voltage stabilizing device is not greater than the first outputting a third level signal when the threshold voltage is reached, and outputting a fourth level signal when the output voltage of the voltage stabilizing device is not less than the second threshold voltage.
  • the charge pump is configured to be turned on when the enable control signal is the third level signal, so as to increase the The voltage at the gate, thereby increasing and restoring the output voltage of the voltage stabilizing device after the output voltage of the voltage stabilizing device drops.
  • the second adjustment circuit further comprising: a controller configured to acquire information indicating that the output voltage of the voltage stabilizing device will drop at a first time, and generate a third level when a second time before the first time is reached signal to the enable control terminal; the charge pump is further configured to turn on when receiving the third level signal, so as to increase the voltage at the gate, whereby the regulated increasing the output voltage of the voltage stabilizing means before the output voltage of the means decreases.
  • the controller is further configured to provide a clock signal to a clock input end of the charge pump.
  • the information indicating that the output voltage of the voltage stabilizing device will drop at the first time is based on the The information that the load of the voltage stabilizing device will change in the first time.
  • the controller is configured to start driving the load at the first time.
  • the controller is configured to adjust one or more of the following parameters in the charge pump: capacitance, clock Frequency, opening time.
  • the voltage stabilizing device provided by the embodiments of the present application can rapidly increase the output voltage by controlling the second regulation circuit including the charge pump after the output voltage drops, so as to ensure the normal operation of the load.
  • FIG. 1 is a schematic diagram of a circuit structure of an existing LDO regulator.
  • FIG. 2 is a schematic diagram of the timing relationship between the output voltage and the gate voltage of the LDO regulator in FIG. 1 .
  • FIG. 3 is a schematic diagram of a circuit structure of a voltage stabilizing device according to an embodiment of the present application.
  • 4A and 4B are schematic diagrams of the circuit structure of the charge pump according to the embodiment of the present application.
  • FIG. 5 is a schematic diagram of the timing relationship between the clock signal of the charge pump and the gate voltage of the NMOS transistor according to the embodiment of the present application.
  • FIG. 6 is a schematic diagram of signal relationships of the voltage stabilizing device in FIG. 3 .
  • Fig. 7 is a schematic structural diagram of another voltage stabilizing device according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of signal relationships of the voltage stabilizing device in FIG. 7 .
  • FIG. 1 is a schematic diagram of a circuit structure of an existing LDO regulator 10 ′.
  • the LDO regulator 10' includes: an error amplifier 14', an NMOS transistor 11' and a voltage divider circuit (not marked).
  • the NMOS transistor 11' is coupled between the power supply terminal 110' and the output terminal 111' of the LDO regulator 10', the power supply terminal 110' of the LDO regulator 10' is provided with a supply voltage V DDA , and the output terminal 111' is used for output output voltage V DD .
  • a load or a load circuit (not marked in the figure) is connected between the output terminal 111' of the LDO regulator 10' and the ground 13'.
  • the voltage divider circuit and the error amplifier 14' are coupled between the output terminal 111' of the LDO voltage regulator 10' and the gate 112' of the NMOS transistor 11' to form an analog feedback loop for regulation by feedback to output a stable output voltage V DD .
  • the voltage dividing circuit includes resistors 121' and 122', and the resistors 121' and 122' are connected in series between the output terminal 111' and the ground 13', and a reference voltage is provided at the first input terminal 141' of the error amplifier 14' V REF , the second input terminal 142' of the error amplifier 14' is connected between the resistors 121' and 122', and the output terminal 143' of the error amplifier 14' is connected to the gate 112' of the NMOS transistor 11'.
  • the output voltage V DD of the LDO regulator 10' can be calculated using the following formula (1):
  • R 1 represents the resistance value of the resistor 121 ′
  • R 2 represents the resistance value of the resistor 122 ′.
  • the time is too long (for example, the time between t0 and t1 Not less than 10 ⁇ s), which may cause the load circuit to fail to work normally or affect the performance of the load circuit.
  • one existing solution is to use an off-chip decoupling capacitor with a large capacitance value (for example, 0.1 ⁇ F to 10 ⁇ F) to reduce the magnitude of the output voltage V DD drop, but this will greatly increase the use of cost.
  • Another solution is to increase the bandwidth of the analog feedback loop to reduce the recovery time of the output voltage V DD , but this will greatly increase the static power consumption.
  • embodiments of the present application provide a voltage stabilizing device, which is described in detail as follows.
  • FIG. 3 is a schematic diagram of a circuit structure of a voltage stabilizing device 10 according to an embodiment of the present application.
  • the voltage stabilizing device 10 has a power supply terminal 110 and an output terminal 111, wherein the power supply voltage V DDA can be provided at the power supply terminal 110 of the voltage stabilizing device 10, and the output terminal 111 is used to connect to a load (or load circuit) to provide an output voltage V DD .
  • the voltage stabilizing device 10 includes an NMOS transistor 11 , a first regulation circuit and a second regulation circuit.
  • the NMOS transistor 11 has a drain (not marked) connected to the power terminal 110 of the voltage stabilizing device 10 , a gate 112 and a source (not marked) connected to the output terminal 111 of the voltage stabilizing device 10 .
  • the first regulation circuit includes a voltage divider circuit and an error amplifier 14 . Wherein, the voltage divider circuit is connected between the output terminal 111 of the voltage stabilizing device 10 and the ground 13, for generating a feedback voltage based on the output voltage VDD of the output terminal 111 of the voltage stabilizing device 10, and providing the feedback voltage to the error amplifier 14.
  • the voltage dividing circuit is a voltage dividing resistor network, including a resistor 121 and a resistor 122, and the resistor 121 and the resistor 122 are connected in series and coupled between the output terminal 111 of the voltage stabilizing device 10 and the ground 13 between.
  • the voltage dividing circuit may include more or less resistors according to actual needs, and the number and types of the resistors are not limited thereto, and will not be repeated here.
  • R 1 represents the resistance value of the resistor 121
  • R 2 represents the resistance value of the resistor 122
  • the values of R 1 and R 2 can be selected according to the actual needs of the circuit, and are not specifically limited here.
  • the ground 13 may be a common ground terminal (which may be a digital ground or an analog ground) or a voltage reference node in the circuit.
  • the error amplifier 14 includes a first input terminal 141 , a second input terminal 142 and an output terminal 143 .
  • the reference voltage V REF is provided at the first input terminal 141 of the error amplifier 14
  • the second input terminal 142 is connected with the voltage dividing circuit.
  • the second input terminal 142 of the error amplifier 14 is coupled to the node between the resistor 121 and the resistor 122 to obtain a feedback voltage.
  • the error amplifier 14 is used to compare the reference voltage V REF at the first input terminal 141 with the feedback voltage at the second input terminal 142 to output a corresponding driving voltage through the output terminal 143 to control and adjust the output current of the NMOS transistor 11, thereby The output voltage of the NMOS transistor 11 is controlled.
  • it can be known that the output voltage V DD can be changed by adjusting the resistance values of the resistors 121 and 122 .
  • the reference voltage V REF is converted from the power supply voltage V DDA provided by the power supply terminal 110 of the voltage stabilizing device 10 .
  • the reference voltage V REF can be provided by an independent voltage source.
  • the second regulation circuit includes a charge pump 15 .
  • the charge pump 15 is configured to selectively turn on based on the variation of the output voltage V DD to regulate the output voltage V DD of the voltage stabilizing device 10 .
  • the charge pump has an enable control terminal 151 and an output terminal 152 , wherein the enable control terminal 151 is used to receive an enable control signal, and the output terminal 152 of the charge pump 15 is connected to the gate 112 of the NMOS transistor 11 .
  • the first regulation circuit (that is, the analog feedback loop) may only rely on the first regulation due to the slow feedback regulation after the response The circuit will make the dropped output voltage V DD unable to recover in time.
  • the second regulation circuit in the voltage stabilizing device 10 can turn on the charge pump 15 according to the drop of the output voltage V DD to regulate the output voltage V DD , for example, The output voltage after the drop is quickly increased and recovered, and the normal operation or performance of the load circuit is guaranteed.
  • the charge pump 15 further includes a clock input terminal 153 .
  • the charge pump is configured to receive a clock signal through the clock input terminal 153 and increase the voltage V GATE at the gate 112 of the NMOS transistor 11 according to the clock signal after being turned on, thereby increasing the output voltage V DD of the voltage regulator.
  • the second adjustment circuit includes a clock circuit, which is an independent clock circuit, and is used to provide the clock signal to the charge pump 15 .
  • the second regulation circuit further includes a hysteresis comparator 16 .
  • the hysteresis comparator 16 has a first input terminal 161, a second input terminal 162 and an output terminal 163, a first threshold voltage V L and a second threshold voltage V H are provided at the first input terminal 161, the first threshold voltage V L is less than the second threshold voltage V H , the second input terminal 162 of the hysteresis comparator 16 is connected to the output terminal 111 of the voltage stabilizing device 10 to obtain the output voltage V DD , the output terminal 163 of the hysteresis comparator 16 is connected to the charge pump 15 to make Can control terminal 151.
  • the hysteresis comparator 16 generates an output signal based on the output voltage V DD , the first threshold voltage V L and the second threshold voltage V H of the voltage stabilizing device 10 , and the output signal serves as an enable control signal of the charge pump 15 .
  • the values of the first threshold voltage V L and the second threshold voltage V H can be selected according to actual conditions.
  • the output voltage V DD is the preset voltage or the stable output voltage V' (ie, )
  • the value of the first threshold voltage V L can be set to be smaller than the stable output voltage V'.
  • the value of the second threshold voltage V H can be set to be greater than, less than or equal to the stable output voltage V'.
  • the difference between the value of V H and the stable output voltage V' should not be too large, for example, the absolute value of the difference between the second threshold voltage V H and the stable output voltage V' should not exceed the stable output voltage about 5% of V'.
  • the hysteresis comparator 16 compares the dropped output voltage V DD with the first threshold voltage V L , and when the output voltage V DD does not When greater than the first threshold voltage V L , the hysteresis comparator 16 outputs a third level signal through the output terminal 162 to turn on the charge pump 15, and outputs a fourth level signal to turn off the charge pump when the output voltage V DD is greater than the second threshold voltage 15 (eg, the case after the output voltage V DD is quickly restored by turning on the charge pump 15 ).
  • the voltage V GATE at the gate 112 of the NMOS transistor 11 is increased, so that the output current of the NMOS transistor 11 increases, thereby increasing and recovering the output voltage V DD .
  • the third-level signal represents a high-level signal that enables the charge pump 15 to be turned on (or works normally)
  • the fourth-level signal represents that the charge pump 15 cannot be turned on (or normally operated) relative to the third-level signal. normal operation) low-level signal.
  • the third level signal is a level or voltage representing logic "1”
  • the fourth level signal is a level or voltage representing logic "0”.
  • the charge pump 15 can also be turned on when receiving a low-level signal, and turned off when receiving a high-level signal, which can be selected according to the actual needs of the voltage stabilizing device.
  • 4A and 4B are schematic circuit diagrams of the charge pump 15 according to the embodiment of the present application.
  • the charge pump 15 includes: a first switch group, a second switch group, a first capacitor 41 and a second capacitor 42 .
  • the first switch group includes a plurality of switches
  • the second switch group includes a plurality of switches.
  • the first capacitor 41 and the first switch group are coupled between the power terminal 110 of the voltage stabilizing device 10 and the ground 13 , and between the output terminal 152 of the charge pump 15 and the ground 13 .
  • the second capacitor 41 and the second switch group are coupled between the power terminal 110 of the voltage stabilizing device 10 and the ground 13 , and between the output terminal 152 of the charge pump 15 and the ground 13 .
  • the switches in the first switch group and the second switch group are selectively controlled so that the first capacitor 41 is charged and the second capacitor 42 is discharged; and when When the charge pump 15 is turned on and the clock signal is a signal of the second level, the switches in the first switch group and the second switch group are selectively controlled to discharge the first capacitor 41 and charge the second capacitor 42 .
  • the enable control signal is a signal of the third level
  • the charge pump 15 is turned on; when the enable control signal is a signal of the fourth level, the charge pump 15 is turned off.
  • the first level signal represents a high level signal
  • the second level signal represents a low level signal relative to the first level signal.
  • a high level signal is a level or voltage representing logic "1”
  • a low level signal is a level or voltage representing logic "0”.
  • the first level signal may also be a low level signal
  • the second level signal is correspondingly a high level signal, which can be selected according to the actual needs of the voltage stabilizing device 10 .
  • the high-level signal received by the enabling control terminal 151 may be the same as the high-level signal received by the clock input terminal 153, and the low-level signal received by the enabling control terminal 151 may be the same as the high-level signal received by the clock input terminal 153.
  • the received low level signal can be the same.
  • the high-level signal received by the enabling control terminal 151 may be different from the high-level signal received by the clock input terminal 153, and the low-level signal received by the enabling control terminal 151 and the low-level signal received by the clock input terminal 153 may be different.
  • the flat signals can be different.
  • the voltage V GATE at the gate 112 of the NMOS transistor 11 is raised or increased by the discharge of the first capacitor 41 or the second capacitor 42 , thereby rapidly increasing the output voltage V DD .
  • the first switch group includes switches 51 , 52 , 53 and 54 .
  • the first end of the switch 51 is connected to the power supply terminal 110 of the voltage stabilizing device 10
  • the second end of the switch 51 is connected to the positive pole of the first capacitor 41
  • the negative pole of the first capacitor 41 is connected to the first end of the switch 52
  • the switch The second end of the switch 52 is connected to the ground 13
  • the first end of the switch 53 is connected to the power supply end 110 of the voltage stabilizing device 10
  • the second end of the switch 53 is connected to the negative pole of the first capacitor 41
  • the first end of the switch 54 is connected to the first end of the first capacitor 41.
  • the anode of a capacitor 41 is connected
  • the second terminal of the switch 54 is connected with the output terminal 152 of the charge pump 15 .
  • the second switch group includes switches 55 , 56 , 57 and 58 .
  • the first terminal of the switch 55 is connected with the power terminal 110 of the voltage stabilizing device 10
  • the second terminal of the switch 56 is connected with the positive pole of the second capacitor 42
  • the negative pole of the second capacitor 42 is connected with the first terminal of the switch 56
  • the switch The second end of 56 is connected to ground 13.
  • the first end of switch 57 is connected to input end 152 of voltage stabilizing device 10
  • the second end of switch 57 is connected to the negative pole of second capacitor 42
  • the first end of switch 58 is connected to The anode of the second capacitor 42 is connected
  • the second terminal of the switch 58 is connected with the output terminal 152 of the charge pump 15 .
  • the enable control signal is the third level signal and the clock signal is the first level signal
  • the switch 51, the switch 52, the switch 57 and the switch 58 are closed, and the switch 53, the switch 54, the switch 55 and the Switches 56 (constituting switch set S2) are open.
  • the enable control signal is a third level signal and the clock signal is a second level signal
  • the switch 51, the switch 52, the switch 57 and the switch 58 that is, the switch set S1 are disconnected, and the switch 53, the switch 54, the switch 55 and switch 56 (ie, switch set S2) are closed.
  • the enable control signal is a signal of the fourth level
  • all the switches in the switch set S1 and the switch set S2 are turned off, that is, the charge pump 15 is turned off or stops working.
  • the charge pump 15 also includes a gate control circuit.
  • the gate control circuit includes an enable control terminal 151 , a clock input terminal 153 , a first output control terminal, and a second output control terminal.
  • the first output control terminal is connected to the control terminals (not shown) of the switch 51, the switch 52, the switch 57 and the switch 58
  • the second output control terminal is connected to the control terminals of the switch 53, the switch 54, the switch 55 and the switch 56 ( not shown) connection.
  • the gate control circuit controls the switch set S1 and the switch set S2 to selectively turn on or turn off according to the state of the clock signal.
  • the gate control circuit includes: a "NOT" gate 61 , a first “AND” gate 62 , a second “AND” gate 63 , a third “AND” gate 64 and a fourth "AND” gate 65 .
  • the first input end 621 of the first “NAND” gate 62 is connected to the clock input end 153 of the charge pump 15, and the second input end 622 of the first “NAND” gate 62 is connected to the second "NAND” gate
  • the output terminal 633 of 63, the output terminal 623 of the first "NAND” gate 62 is connected to the first input terminal 631 of the second "NAND” gate 63 and the first input terminal 641 of the third "AND” gate 64.
  • the input end 611 of "NOR” gate 61 is connected to the clock input end 153 of charge pump 15, the output end 612 of "NOR” gate 61 is connected to the second input end 632 of the second "NAND” gate 63, the second "AND”
  • the output terminal 633 of the NOT gate 63 is connected to the first input terminal 651 of the fourth “AND” gate 65 .
  • the second input terminal 642 of the third “AND” gate 64 and the second input terminal 652 of the fourth “AND” gate 65 are connected to the enable control terminal 151 .
  • the output terminal 643 of the third “AND” gate 64 is the first output terminal of the gate control circuit, and the output terminal 653 of the fourth "AND” gate 65 is the second output terminal of the gate control circuit.
  • the signal output through the output terminal 643 is used to connect with the control terminal of the switch in the switch set S1 to control the switch on or off of the switch set S1; the signal output through the output terminal 653 is used to communicate with the switch set S2 The control ends of the switches of the switches are connected to control the conduction or disconnection of the switches of the switch set S2.
  • FIG. 5 is a schematic diagram of the timing relationship between the clock signal Clock and the gate voltage V GATE of the charge pump 15 of the voltage stabilizing device 10 according to the embodiment of the present application.
  • the enable control signal of the enable input terminal 151 of the charge pump 15 is at a low level (such as represented by a logic “0”), the charge pump 15 is turned off, and all switches in the charge pump 15 (such as shown in Figure 4A) are all disconnected.
  • the enable control signal of the enable input 151 of the charge pump 15 is at a high level (for example, represented by a logic “1”) and the clock signal is at a low level (for example, represented by a logic “0”), that is, in During the first duration T1, the switches (i.e., switches 51, 52, 57, and 58) in the switch set S1 in FIG. and 56) are disconnected, and the first capacitor 41 is charged.
  • the charge pump 15 since the charge pump 15 is turned on for the first time, there is no charge in the second capacitor 42, and the second capacitor 42 will not discharge. At this time, the charge pump 15 will not increase the gate voltage V GATE .
  • the switches in the switch set S1 in FIG. 4A That is, the switches 51, 52, 57 and 58) are turned off, the switches in the switch set S2 (ie, the switches 53, 54, 55 and 56) are turned on or closed, the first capacitor 41 is discharged, and the second capacitor 42 is charged. Discharging the first capacitor 41 will transfer charges to the gate 112 of the NMOS transistor 11 , thereby increasing the gate voltage V GATE .
  • the switches in the switch set S1 in FIG. 4A that is, the switch 51 , 52, 57 and 58
  • the switches in the switch set S2 ie, switches 53, 54, 55 and 56
  • the first capacitor 41 is charged
  • the second capacitor 42 is discharged. Discharging the second capacitor 42 will transfer charge to the gate 112 of the NMOS transistor 11 , thereby increasing the gate voltage V GATE .
  • the gate voltage V GATE is elevated at each duration T1 and T2, thus forming a ladder structure until the enable control signal is at a low level or The maximum output voltage of the charge pump is reached, whereby the charge pump 15 increases and recovers the output voltage V DD of the voltage stabilizing device 10 after the output voltage V DD of the voltage stabilizing device 10 drops.
  • FIG. 6 is a schematic diagram of the timing relationship of various parameters of the voltage stabilizing device 10 according to the embodiment of the present application.
  • the load becomes larger instantaneously, causing the output voltage V DD to drop.
  • the hysteresis comparator 16 compares the output voltage V DD with the first threshold voltage V L , and when the output voltage V DD is not greater than the first threshold voltage V L at time t12, the hysteresis comparator 16 outputs a high-level signal to the enabler of the charge pump 15
  • the energy control terminal 151 is turned on, and the charge pump 15 is turned on.
  • the gate voltage VGATE rises rapidly in a stepwise manner, and correspondingly, the output voltage V DD also rapidly rises and recovers in a stepwise manner after falling.
  • the hysteresis comparator 16 outputs a low-level signal to the enable control terminal 151 of the charge pump 15, and the charge pump 15 is turned off or stops working, thereby The gate voltage V GATE and the output voltage V DD stop rising.
  • the second threshold voltage V H is greater than the preset voltage of the output voltage V DD or the stable output voltage V' (that is, )
  • the gate voltage V GATE and the output voltage V DD drop slowly until they return to the preset voltage or the stable output voltage at t13 (that is, ).
  • the recovery time of the output voltage V DD of the voltage stabilizing device 10 is t11-t0, which is much shorter than the recovery time t1-t0 of the output voltage V DD of the LDO voltage regulator of FIG. 1 in FIG. 2 .
  • the charge pump 15 has no static power consumption, compared with the LDO regulator in FIG. 1 , the static power consumption of the added hysteretic comparator 16 is much smaller than that of the increased analog loop bandwidth.
  • the frequency of the clock signal may be 40 MHz.
  • the capacitance C1 of the first capacitor 41 can be 30fF to 480fF, and the first capacitor 41 is adjustable.
  • the capacitance C2 of the second capacitor 42 can be 30fF to 480fF, and the second capacitor 42 is adjustable.
  • the voltage recovery time when the charge pump is not used is greater than 10 ⁇ s, and the voltage stabilizing device 10 according to the embodiment of the present invention can make the output voltage quickly recover to the time not less than the second threshold voltage V H after falling (that is, t11- t0) drops sharply, for example not greater than 100 ns.
  • the absolute value of the difference between the second threshold voltage V H and the preset voltage or the stable output voltage V' does not exceed the preset voltage or the stable output voltage V' (that is, ) in the range of about 5%
  • the output voltage V DD can be restored to be greater than the preset voltage or the stable output voltage V', can be smaller than the preset voltage or the stable output voltage V', or can also be restored to be equal to the preset voltage Or stabilize the output voltage V' so that the recovery time is not greater than 100ns.
  • the NMOS transistor may also use other transistor types, such as a bipolar transistor (Bipolar), a field effect transistor (FET), and the like.
  • Bipolar bipolar transistor
  • FET field effect transistor
  • FIG. 7 is a schematic diagram of a circuit structure of a voltage stabilizing device 20 according to another embodiment of the present application.
  • the difference of the voltage stabilizing device 20 is that the second regulation circuit includes a controller 21 to replace the hysteresis comparator 16 in the voltage stabilizing device 10 .
  • the controller 21 has a first output terminal 211 and a second output terminal 212 .
  • the first output terminal 211 of the controller 21 is connected to the enable control terminal 151 of the charge pump 15
  • the second output terminal 212 of the controller 21 is connected to the clock input terminal 153 of the charge pump 15 .
  • the controller 21 acquires information indicating that the output voltage V DD of the voltage stabilizing device 20 will drop at the first time, and generates and outputs a third level signal to the enable control terminal 151 at the second time before the first time,
  • the charge pump 15 is turned on when receiving the third level signal to increase the gate voltage V GATE , thereby increasing the output voltage of the voltage stabilizing device 20 before the output voltage V DD of the voltage stabilizing device 20 drops.
  • the output voltage V DD can be pre-compensated.
  • the output voltage V DD can still be kept above the preset voltage or the stable output voltage V' after the drop. normal operation of the load circuit. It is especially suitable when the load circuit is not sensitive to too high output voltage V DD (that is, the power supply voltage of the load circuit), but is more sensitive to too low output voltage V DD .
  • the information indicating that the output voltage V DD of the voltage stabilizing device 20 will drop at the first time is based on the information that the load or load circuit of the voltage stabilizing device 20 will change at the first time.
  • the controller 21 stores the information or task that the load or the load circuit will be driven or started at the first time, when the task is started, the timer or timer (not shown) in the trigger controller 21 is timed, And when the second time is reached, a third level signal is generated and output to turn on the charge pump 15, so as to increase the output voltage VDD in advance before the first time is reached (that is, before the output voltage drops).
  • FIG. 8 is a schematic diagram of the timing relationship of various parameters of the voltage stabilizing device 20 according to the embodiment of the present application.
  • the working principle of the voltage stabilizing device 20 is as follows.
  • the controller 21 obtains or stores information that the load of the voltage stabilizing device 20 will increase at time t0 (that is, the controller 21 knows that the load will increase at time t0), and the controller 21 generates a high level at time t22 before time t0
  • the signal is output to the enable control terminal 151 of the charge pump 15 through the first output terminal 211, and the controller 21 provides the clock signal to the clock input terminal 153 of the charge pump 15 through the second output terminal 212 at the same time, and the charge pump 15 is enabled to control Terminal 151 is turned on when it is at a high level, and as described above with respect to FIG. 4A, FIG. 4B and FIG . DD is stepped up.
  • the controller 21 generates a low-level signal and outputs it to the enable control terminal 151 of the charge pump 15 through the first output terminal 211, and the charge pump 15 is turned off when the received enable control signal is at a low level, thereby Stop raising the gate voltage V GATE .
  • the voltage stabilizing device 20 starts to drive the load or the load circuit, and the output voltage V DD drops rapidly, but since the output voltage V DD has been raised to a higher value before the time t0, the drop of the output voltage V DD at the time t0 remains at the preset voltage after above. However, through the first regulating circuit, the output voltage V DD slowly decreases and recovers to the preset voltage at time t1
  • the controller 21 can be configured to increase the gate voltage V GATE and the lift-up range of the output voltage by adjusting one or more of the following parameters: the first capacitor 41 in the charge pump 15 The capacitance of the capacitor, the capacitance of the second capacitor 42 in the charge pump 15, the frequency of the clock signal, and the turn-on time t22.
  • the frequency of the clock signal may be 40 MHz.
  • the capacitance of the first capacitor 41 can be 30fF to 480fF, and the first capacitor 41 is adjustable.
  • the capacitance of the second capacitor 42 can be 30fF to 480fF, and the second capacitor 42 is adjustable.
  • the embodiment of the present application also provides a power supply device, including a power supply and a voltage stabilizing device 10 .
  • An embodiment of the present application also provides a system, including the above-mentioned power supply device and a load circuit.
  • the embodiment of the present application also provides a power supply device, including a power supply and a voltage stabilizing device 20 .
  • An embodiment of the present application also provides a system, including the above-mentioned power supply device and a load circuit.

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Abstract

一种稳压装置(10)，在稳压装置(10)的电源端(110)提供电源电压，输出端(111)连接到负载并提供输出电压，稳压装置(10)包括NMOS晶体管(11)，具有连接到电源端(110)的漏极、栅极(112)和连接到输出端(111)的源极；第一调节电路，包括分压电路，其连接于稳压装置(10)的输出端(111)与接地(13)之间，分压电路基于稳压装置(10)的输出端(111)的输出电压产生反馈电压；以及误差放大器(14)，在误差放大器(14)的第一输入端(141)处提供参考电压，误差放大器(14)的第二输入端(142)与分压电路连接，误差放大器(14)的输出端(143)与栅极(112)连接；以及第二调节电路，包括电荷泵(15)，使能控制端(151)经配置以接收使能控制信号，电荷泵(15)的输出端(152)连接到栅极(112)，电荷泵(15)经配置以根据使能控制信号选择性地开启以调节稳压装置(10)的输出电压。

Description

稳压装置 技术领域
本申请涉及电路技术，尤其涉及稳压装置。
背景技术
低压降或低压差稳压器(Low Dropout Regulator,LDO Regulator)是一种线性稳压器，用于提供恒定的输出电压。LDO稳压器具有较低的静态功耗和较小的面积，并能保持较低的输出阻抗和噪声，广泛应用于各种电路中。
然而，当LDO稳压器的负载由小变大时，其输出电压会降低，随后会在其中的模拟反馈环路的作用下逐渐恢复。当LDO稳压器的负载瞬间变大而导致输出电压迅速下降时，模拟反馈环路由于响应后反馈调节较慢，使下降后的输出电压无法及时恢复，从而使负载电路无法正常工作或影响负载电路的工作性能。因此，如何解决LDO稳压器的上述问题是很有必要的。
发明内容
本申请的实施例提供了一种稳压装置，用于解决输出电压下降后迅速恢复的问题。
根据本申请的第一方面，提供了一种稳压装置。该稳压装置具有电源端和输出端，其中，在所述稳压装置的所述电源端处提供电源电压，所述输出端用于连接到负载并提供输出电压，所述稳压装置包括：NMOS晶体管，其具有连接到所述稳压装置的所述电源端的漏极、栅极和连接到所述稳压装置的所述输出端的源极；第一调节电路，其包括：分压电路，其连接于所述稳压装置的所述输出端与接地之间，所述分压电路用于基于所述稳压装置的所述输出端的所述输出电压产生反馈电压；以及误差放大器，其具有第一输入端、第二输入端和输出端，其中，在所述误差放大器的所述第一输入端处提供参考电压，所述第二输入端与所述分压电路连接，所述误差放大器的所述输出端与所述NMOS晶体管的所述栅极连接；以及第二调节电路，其包括： 电荷泵，其具有使能控制端和输出端，其中，所述使能控制端经配置以接收使能控制信号，所述电荷泵的所述输出端连接到所述栅极，所述电荷泵经配置以根据所述使能控制信号选择性地开启以调节所述稳压装置的所述输出电压。
结合第一方面，在第一种可能的实现方式中，所述电荷泵进一步包括：时钟输入端，所述电荷泵经配置以通过所述时钟输入端接收时钟信号，并在开启后根据所述时钟信号提高所述NMOS晶体管的所述栅极处的电压，借此以提高所述稳压装置的所述输出电压。
结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述电荷泵进一步包括：第一开关组，其包括多个开关；第二开关组，其包括多个开关；第一电容器，其与所述第一开关组耦合于所述稳压装置的所述电源端与所述接地之间，以及耦合于所述电荷泵的输出端与所述接地之间；第二电容器，其与所述第二开关组耦合于所述稳压装置的所述电源端与所述接地之间，以及耦合于所述电荷泵的输出端与所述接地之间；其中，当所述电荷泵开启且所述时钟信号为第一电平信号时，所述第一开关组和所述第二开关组中的开关被选择性地控制以使第一电容器充电且所述第二电容器放电；以及当所述电荷泵开启且所述时钟信号为第二电平信号时，所述第一开关组和所述第二开关组中的开关被选择性地控制以使所述第一电容器放电且所述第二电容器充电；以及其中，当所述使能控制信号为第三电平信号时，所述电荷泵开启，以及当所述使能控制信号为第四电平信号时，所述电荷泵关闭。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述第一开关组包括第一开关、第二开关、第三开关和第四开关，其中，所述第一开关的第一端与所述稳压装置的所述电源端连接，所述第一开关的第二端与所述第一电容器的正极连接，所述第一电容器的负极与所述第二开关的第一端连接，所述第二开关的第二端与所述接地连接，所述第三开关的第一端与所述稳压装置的所述电源端连接，所述第三开关的第二端与所述第一电容器的所述负极连接，所述第四开关的第一端与所述第一电容器的所述正极连接，所述第四开关的所述第二端与所述电荷泵的所述输出端连接；以及 所述第二开关组包括第五开关、第六开关、第七开关和第八开关，其中所述第五开关的第一端与所述稳压装置的所述电源端连接，所述第五开关的第二端与所述第二电容器的正极连接，所述第二电容器的负极与所述第六开关的第一端连接，所述第六开关的第二端与所述接地连接，所述第七开关的第一端与所述稳压装置的所述电源端连接，所述第七开关的第二端与所述第二电容器的所述负极连接，所述第八开关的第一端与所述第二电容器的所述正极连接，所述第八开关的第二端与所述电荷泵的所述输出端连接；其中，当所述使能控制信号为第三电平信号且所述时钟信号为第一电平信号时，所述第一开关、所述第二开关、所述第七开关和所述第八开关闭合，所述第三开关、所述第四开关、所述第五开关和所述第六开关断开；当所述使能控制信号为所述第三电平信号且所述时钟信号为第二电平信号时，所述第一开关、所述第二开关、所述第七开关和所述第八开关断开，所述第三开关、所述第四开关、所述第五开关和所述第六开关闭合；以及当所述使能控制信号为第四电平信号时，所述第一开关组和所述第二开关组中的所有开关均断开。
结合第一方面的第三种可能的实现方式，在第四种可能的实现方式中，所述电荷泵进一步包括：门控制电路，其包括所述使能控制端、所述时钟输入端、第一输出控制端和第二输出控制端；其中，所述第一输出控制端与所述第一开关、所述第二开关、所述第七开关和所述第八开关的控制端连接，所述第二输出控制端与所述第三开关、所述第四开关、所述第五开关和所述第六开关的控制端连接。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述门控制电路进一步包括：“非”门、第一“与非”门、第二“与非”门、第三“与”门和第四“与”门；其中，所述第一“与非”门的第一输入端连接到所述时钟输入端，所述第一“与非”门的第二输入端连接到所述第二“与非”门的输出端，所述第一“与非”门的输出端连接到第二“与非”门的第一输入端和所述第三“与”门的第一输入端；所述“非”门的输入端连接到所述时钟输入端，所述“非”门的输出端连接到所述第二“与非”门的第二输入端，所述第二“与非”门的输出端连接到所述第四“与”门的第一输入 端；所述第三“与”门的第一输入端和所述第四"与"门的第二输入端连接到所述使能控制端，所述第三“与”门的输出端为所述门控制电路的所述第一输出端，所述第四"与"门的输出端为所述门控制电路的所述第二输出端。
结合第一方面的第一种可能的实现方式，在第六种可能的实现方式中，所述第二调节电路还包括：时钟电路，所述时钟电路经配置以输出所述时钟信号。
结合第一方面或者第一方面的第一种可能的实现方式至第六种可能的实现方式中的任一种实现方式，在第七种可能的实现方式中，所述第二调节电路进一步包括：
迟滞比较器，其具有第一输入端、第二输入端和输出端，其中，在所述迟滞比较器的所述第一输入端处提供第一门限电压和第二门限电压，所述第一门限电压小于所述第二门限电压，所述迟滞比较器的所述第二输入端连接到所述稳压装置的所述输出端，所述迟滞比较器的所述输出端连接到所述电荷泵的所述使能控制端；其中，所述迟滞比较器经配置以基于所述稳压装置的所述输出电压、所述第一门限电压和所述第二门限电压产生所述输出信号，所述输出信号作为所述电荷泵的所述使能控制信号。
结合第一方面的第七种可能的实现方式，在第八种可能的实现方式中，所述迟滞比较器进一步经配置以在当所述稳压装置的所述输出电压不大于所述第一门限电压时输出第三电平信号，以及在所述稳压装置的所述输出电压不小于所述第二门限电压时输出第四电平信号。
结合第一方面的第八种可能的实现方式，在第九种可能的实现方式中，所述电荷泵经配置以在所述使能控制信号为所述第三电平信号时开启以提高所述栅极处的电压，借此以在所述稳压装置的所述输出电压下降后提高和恢复所述稳压装置的所述输出电压。
结合第一方面或者第一方面的第一种可能的实现方式至第六种可能的实现方式中的任一种可能的实现方式，在第十种可能的实现方式中，所述第二调节电路进一步包括：控制器，其经配置以获取指示所述稳压装置的所述输出电压将在第一时间下降的信息，并在到达所述第一时间前的第二时间时产 生第三电平信号至所述使能控制端；所述电荷泵进一步经配置以在接收到所述第三电平信号时开启，以提高所述栅极处的所述电压，借此以在所述稳压装置的所述输出电压下降前提高所述稳压装置的所述输出电压。
结合第一方面的第十种可能的实现方式，在第十一种可能的实现方式中，所述控制器进一步经配置以提供时钟信号至所述电荷泵的时钟输入端。
结合第一方面的第十一种可能的实现方式，在第十二种可能的实现方式中，指示所述稳压装置的所述输出电压将在所述第一时间下降的信息是基于所述稳压装置的负载将在第一时间变化的信息。
结合第一方面的第十二种可能的实现方式，在第十三种可能的实现方式中，所述控制器经配置以在所述第一时间启动驱动所述负载。
结合第一方面的第十种可能的实现方式，在第十四种可能的实现方式中，所述控制器经配置以调整所述电荷泵中的以下参数中的一个或多个：电容、时钟频率、开启时间。
本申请的实施例提供的稳压装置可以在输出电压下降后，通过控制包括电荷泵的第二调节电路以迅速提高输出电压，保证负载的正常工作。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。应理解，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有的LDO稳压器的电路结构示意图。
图2是图1中的LDO稳压器的输出电压与栅极电压的时序关系示意图。
图3是本申请的实施例的一种稳压装置的电路结构示意图。
图4A和4B是本申请的实施例的电荷泵的电路结构示意图。
图5是本申请的实施例的电荷泵的时钟信号与NMOS晶体管的栅极电压的时序关系的示意图。
图6是图3的稳压装置的各信号关系的示意图。
图7是根据本申请的实施例的另一种稳压装置的结构示意图。
图8是图7中的稳压装置的各信号关系的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1为现有的一种LDO稳压器10'的电路结构示意图。该LDO稳压器10'包括：误差放大器14'、NMOS晶体管11'和分压电路(未标识)。NMOS晶体管11'耦合至LDO稳压器10'的电源端110'与输出端111'之间，LDO稳压器10'的电源端110'提供有电源电压V DDA，其输出端111'用于输出输出电压V DD。其中，负载或负载电路(图中未标识)连接至LDO稳压器10'的输出端111'与接地13'之间。分压电路和误差放大器14'耦合至LDO稳压器10'的输出端111'与NMOS晶体管11'的栅极112'之间以形成模拟反馈环路，以用于通过反馈调节，输出稳定的输出电压V DD。其中，分压电路包括电阻器121'和122'，电阻器121'和122'串联于输出端111'与接地13'之间，误差放大器14'的第一输入端141'处提供有参考电压V REF，误差放大器14'的第二输入端142'连接至电阻器121'与电阻器122'之间，误差放大器14'的输出端143'连接至NMOS晶体管11'的栅极112'。LDO稳压器10'的输出电压V DD可以采用如下公式(1)进行计算：
Figure PCTCN2022138736-appb-000001
其中，R 1表示电阻器121'的电阻值，R 2表示电阻器122'的电阻值。
当LDO稳压器10'连接负载或负载电路，或者负载由小变大时，其输出电压会降低，随后会在其中的模拟反馈环路的作用下逐渐恢复。然而，如图2所示，在当LDO稳压器10'的负载在t0时刻瞬间变大而导致输出电压V DD迅速下降的情况下，受限于模拟反馈环路的带宽，模拟反馈环路响应后反馈 调节慢，只能缓慢抬升V GATE，在t1时刻输出电压V DD恢复正常，由于输出电压在t0至t1之间持续处于低值，时间过长(例如，t0至t1之间的时间不小于10μs)，从而可能导致负载电路无法正常工作或影响负载电路的工作性能。
针对上述问题，现有的一种解决方案是使用具有较大电容值(比如，0.1μF至10μF)的片外去耦电容器，以减小输出电压V DD降低的幅度，但这会大幅提高使用成本。另一种解决方案是增加模拟反馈环路的带宽，以减少输出电压V DD的恢复时间，但这会较大的增加静态功耗。
对此，为了至少解决上述问题，本申请的实施例提供了一种稳压装置，具体描述如下。
图3是本申请的实施例的一种稳压装置10的电路结构示意图。该稳压装置10具有电源端110和输出端111，其中，在稳压装置10的电源端110处可以提供电源电压V DDA，输出端111用于连接到负载(或者负载电路)以提供输出电压V DD。
稳压装置10包括NMOS晶体管11、第一调节电路和第二调节电路。NMOS晶体管11具有连接到稳压装置10的电源端110的漏极(未标识)、栅极112和连接到稳压装置10的输出端111的源极(未标识)。第一调节电路包括分压电路和误差放大器14。其中，分压电路连接于稳压装置10的输出端111与接地13之间，以用于基于稳压装置10的输出端111的输出电压V DD产生反馈电压，并将反馈电压提供至误差放大器14。在本申请的实施例中，分压电路为分压电阻器网络，包括电阻器121和电阻器122，电阻器121和电阻器122串联并耦合于稳压装置10的输出端111与接地13之间。
在本申请的其他实施例中，根据实际需要，分压电路可以包括更多或更少的电阻器，电阻器的数量和种类并不限定于此，这里不再赘述。其中，R 1表示电阻器121的电阻值，R 2表示电阻器122的电阻值，R 1和R 2的值可以根据电路实际需要进行选择，这里不做具体限定。接地13可以是电路中的公共接地端(可以为数字地或模拟地)或电压参考节点。
误差放大器14包括第一输入端141、第二输入端142和输出端143。其 中，在误差放大器14的第一输入端141处提供参考电压V REF，第二输入端142与分压电路连接。具体地，误差放大器14的第二输入端142耦合至电阻器121和电阻器122之间的节点处以获取反馈电压。误差放大器14用于比较第一输入端141处的参考电压V REF与第二输入端142处的反馈电压以通过输出端143输出对应的驱动电压，以控制和调节NMOS晶体管11的输出电流，从而控制NMOS晶体管11的输出电压。其中，根据公式(1)可知，通过调节电阻器121和122的阻值可以改变输出电压V DD。
在本申请的实施例中，参考电压V REF由稳压装置10的电源端110处提供的电源电压V DDA变换得到。在本申请的一些实施例中，参考电压V REF可以由独立的电压源提供。
第二调节电路包括电荷泵15。电荷泵15经配置以基于输出电压V DD的变化选择性地开启以调节稳压装置10的输出电压V DD。电荷泵具有使能控制端151和输出端152，其中，使能控制端151用于接收使能控制信号，电荷泵15的输出端152连接到NMOS晶体管11的栅极112。
针对图1的描述的问题，在对于负载瞬间变大而导致输出电压V DD迅速下降的情况下，第一调节电路(即模拟反馈环路)可能由于响应后反馈调节慢，仅依靠第一调节电路会使下降后的输出电压V DD无法及时恢复。此时，除了第一调节电路外，当输出电压V DD迅速下降后，稳压装置10中的第二调节电路可以根据输出电压V DD的下降开启电荷泵15以调节输出电压V DD，比如，使下降后的输出电压迅速提高恢复，保证负载电路的正常工作或工作性能。
在本申请的实施例中，电荷泵15进一步包括时钟输入端153。电荷泵经配置以通过时钟输入端153接收时钟信号，并在开启后根据时钟信号提高NMOS晶体管11的栅极112处的电压V GATE，借此以提高稳压装置的输出电压V DD。在本申请的一些实施例中，第二调节电路包括时钟电路，该时钟电路为独立的时钟电路，其用于提供该时钟信号至电荷泵15。
在本申请的一些实施例中，第二调节电路进一步包括迟滞比较器16。迟滞比较器16具有第一输入端161、第二输入端162和输出端163，在第一输 入端161处提供有第一门限电压V L和第二门限电压V H，第一门限电压V L小于第二门限电压V H，迟滞比较器16的第二输入端162连接到稳压装置10的输出端111以获取输出电压V DD，迟滞比较器16的输出端163连接到电荷泵15的使能控制端151。其中，迟滞比较器16基于稳压装置10的输出电压V DD、第一门限电压V L和第二门限电压V H产生输出信号，该输出信号作为电荷泵15的使能控制信号。其中第一门限电压V L和第二门限电压V H的取值可以根据实际情况进行选择。
在一些实施例中，当稳压装置10稳定工作时(即，负载无变化或者输出电压保持稳定)的输出电压V DD为预设电压或稳定输出电压V'(即，
Figure PCTCN2022138736-appb-000002
Figure PCTCN2022138736-appb-000003
)，第一门限电压V L的数值可以被设置为小于稳定输出电压V'。第二门限电压V H的数值可以被设置为大于、小于或等于稳定输出电压V'。在本申请的实施例中，V H的数值与稳定输出电压V'的差值不宜过大，比如，第二门限电压V H与稳定输出电压V'的差值的绝对值不超过稳定输出电压V'的约5％。
然而，在本申请的实施例中，当稳压装置10的输出电压V DD突然下降后，迟滞比较器16比较下降后的输出电压V DD与第一门限电压V L，当输出电压V DD不大于第一门限电压V L时，迟滞比较器16通过输出端162输出第三电平信号以开启电荷泵15，当输出电压V DD大于第二门限电压时输出第四电平信号以关闭电荷泵15(如，在通过开启电荷泵15之后迅速恢复输出电压V DD后的情况)。电荷泵15在开启之后提高NMOS晶体管11的栅极112处的电压V GATE，使得NMOS的晶体管11的输出电流增大，从而提高和恢复输出电压V DD。
需要说明的是，第三电平信号表示能够使电荷泵15开启(或正常工作)的高电平信号，第四电平信号表示相对于第三电平信号的不能使电荷泵15开启(或正常工作)的低电平信号。比如，第三电平信号为表示逻辑“1”的电平或电压，第四电平信号为表示逻辑“0”的电平或电压。在本申请的一些实施例中，电荷泵15也可以在接收到低电平信号时开启，以及在接收到高电平信号时关闭，可以根据稳压装置的实际需要进行选择。
图4A和4B为本申请的实施例的电荷泵15的电路示意图。
如图4A所示，电荷泵15包括：第一开关组、第二开关组、第一电容器41和第二电容器42。第一开关组包括多个开关，第二开关组包括多个开关。第一电容器41与第一开关组耦合于稳压装置10的电源端110与接地13之间，以及耦合于电荷泵15的输出端152与接地13之间。第二电容器41与第二开关组耦合于稳压装置10的电源端110与接地13之间，以及耦合于电荷泵15的输出端152与接地13之间。其中，电荷泵15开启且时钟信号为第一电平信号时，第一开关组和第二开关组中的开关被选择性地控制以使第一电容器41充电和第二电容器42放电；以及当电荷泵15开启且时钟信号为第二电平信号时，第一开关组和第二开关组中的开关被选择性地控制以使第一电容器41放电和第二电容器42充电。其中，如前所述，使能控制信号为第三电平信号时，电荷泵15开启；使能控制信号为第四电平信号时，电荷泵15关闭。
需要说明的是，第一电平信号表示高电平信号，第二电平信号表示相对于第一电平信号的低电平信号。比如，高电平为表示逻辑“1”的电平或电压，低电平信号为表示逻辑“0”的电平或电压。在本申请的一些实施例中，第一电平信号也可以为低电平信号，第二电平信号相应地为高电平信号，可以根据稳压装置10的实际需要进行选择。需要说明的是，在一些示例中，使能控制端151接收的高电平信号与时钟输入端153的高电平信号可以相同，使能控制端151接收的低电平信号与时钟输入端153接收的低电平信号可以相同。在其他示例中，使能控制端151接收的高电平信号与时钟输入端153的高电平信号可以不相同，使能控制端151接收的低电平信号与时钟输入端153接收的低电平信号可以不相同。
在电荷泵开启后，通过第一电容器41或第二电容器42的放电抬高或提高NMOS晶体管11的栅极112处的电压V GATE，从而迅速提高输出电压V DD。
具体地，第一开关组包括开关51、52、53和54。其中，开关51的第一端与稳压装置10的电源端110连接，开关51的第二端与第一电容器41的正极连接，第一电容器41的负极与开关52的第一端连接，开关52的第二 端与接地13连接，开关53的第一端与稳压装置10的电源端110连接，开关53的第二端与第一电容器41的负极连接，开关54的第一端与第一电容器41的正极连接，开关54的第二端与电荷泵15的输出端152连接。
第二开关组包括开关55、56、57和58。其中，开关55的第一端与稳压装置10的电源端110连接，开关56的第二端与第二电容器42的正极连接，第二电容器42的负极与开关56的第一端连接，开关56的第二端与接地13连接.，开关57的第一端与稳压装置10的输入端152连接，开关57的第二端与第二电容器42的负极连接，开关58的第一端与第二电容器42的正极连接，开关58的第二端与电荷泵15的输出端152连接。
当使能控制信号为第三电平信号且时钟信号为第一电平信号时，开关51、开关52、开关57和开关58(构成开关集合S1)闭合，开关53、开关54、开关55和开关56(构成开关集合S2)断开。当使能控制信号为第三电平信号且时钟信号为第二电平信号时，开关51、开关52、开关57和开关58(即，开关集合S1)断开，开关53、开关54、开关55和开关56(即，开关集合S2)闭合。当使能控制信号为第四电平信号时，开关集合S1和开关集合S2中的所有开关均断开，即电荷泵15关闭或停止工作。
如图4B所示，电荷泵15还包括门控制电路。门控制电路包括使能控制端151、时钟输入端153、第一输出控制端、第二输出控制端。其中，第一输出控制端与开关51、开关52、开关57和开关58的控制端(未示出)连接，第二输出控制端与开关53、开关54、开关55和开关56的控制端(未示出)连接。其中，门控制电路根据时钟信号的状态控制开关集合S1和开关集合S2选择性地开启或断开。
具体地，门控制电路包括：“非”门61、第一“与非”门62、第二“与非”门63、第三“与”门64和第四“与”门65。其中，第一“与非”门62的第一输入端621连接到电荷泵15的时钟输入端153，第一“与非”门62的第二输入端622连接到第二“与非”门63的输出端633，第一“与非”门62的输出端623连接到第二“与非”门63的第一输入端631和第三“与”门64的第一输入端641。“非”门61的输入端611连接到电荷泵15的时钟 输入端153，“非”门61的输出端612连接到第二“与非”门63的第二输入端632，第二“与非”门63的输出端633连接到第四“与”门65的第一输入端651。第三“与”门64的第二输入端642和第四“与”门65的第二输入端652连接到使能控制端151。第三“与”门64的输出端643为门控制电路的第一输出端，第四“与”门65的输出端653为门控制电路的第二输出端。其中，通过输出端643输出的信号用于与开关集合S1中的开关的控制端连接以控制开关集合S1的开关的导通或断开；通过输出端653输出的信号用于与开关集合S2中的开关的控制端连接以控制开关集合S2的开关的导通或断开。
图5为本申请的实施例的稳压装置10的电荷泵15的时钟信号Clock和栅极电压V GATE的时序关系的示意图。
如图5所示，当电荷泵15的使能输入端151的使能控制信号为低电平(比如采用逻辑“0”表示)时，电荷泵15关闭，电荷泵15中的所有开关(如图4A所示)均断开。当电荷泵15的使能输入端151的使能控制信号为高电平(比如，采用逻辑“1”表示)且时钟信号为低电平(比如，采用逻辑“0”表示)时，即在第一个持续时间T1时，图4A中的开关集合S1中的开关(即，开关51、52、57和58)导通或闭合，开关集合S2中的开关(即，开关53、54、55和56)断开，第一电容器41充电。需要说明的时，对于第一个持续时间T1，由于电荷泵15初次开启，第二电容器42中无电荷，第二电容器42不会放电，此时，电荷泵15不会提升栅极电压V GATE。
当电荷泵15的使能控制端151的使能控制信号为高电平且时钟信号为高电平时，比如，在随后的第一个T2时间内，图4A中的开关集合S1中的开关(即，开关51、52、57和58)断开，开关集合S2中的开关(即，开关53、54、55和56)导通或闭合，第一电容器41放电，第二电容器42充电。第一电容器41放电会使电荷向NMOS晶体管11的栅极112处转移，从而提高栅极电压V GATE。
接着，在下一个持续时间T1，即电荷泵15的使能控制端151的使能控制信号为高电平且时钟信号为低电平时，图4A中的开关集合S1中的开关 (即，开关51、52、57和58)导通，开关集合S2中的开关(即，开关53、54、55和56)断开，第一电容器41充电，第二电容器42放电。第二电容器42放电会使电荷向NMOS晶体管11的栅极112处转移，从而提高栅极电压V GATE。
当使能控制信号为高电平且时钟信号持续输入时，栅极电压V GATE在每个持续时间T1和T2均被抬高，从而形成阶梯式结构，直至使能控制信号为低电平或者达到电荷泵的最大输出电压，借此，电荷泵15在稳压装置10的输出电压V DD下降后提高和恢复稳压装置10的输出电压V DD。
图6为本申请的实施例的稳压装置10的各参数的时序关系示意图。
如图6所示，在t0时刻时，负载瞬间变大，导致输出电压V DD下降。迟滞比较器16比较输出电压V DD与第一门限电压V L，当在t12时刻输出电压V DD不大于第一门限电压V L时，迟滞比较器16输出高电平信号至电荷泵15的使能控制端151，电荷泵15开启，根据针对图5的上述描述，栅极电压VGATE迅速阶梯式抬升，相应地，下降后的输出电压V DD也迅速阶梯式抬升和恢复。
随后，在t11时刻，当输出电压V DD不小于第二门限电压V H时，迟滞比较器16输出低电平信号至电荷泵15的使能控制端151，电荷泵15关闭或停止工作，从而栅极电压V GATE和输出电压V DD停止抬升。需要说明的是，当第二门限电压V H大于输出电压V DD的预设电压或稳定输出电压V'(即，
Figure PCTCN2022138736-appb-000004
Figure PCTCN2022138736-appb-000005
)时，在第一调节电路的作用下，栅极电压V GATE和输出电压V DD缓慢下降，直至在t13时刻恢复至预设电压或稳定输出电压(即，
Figure PCTCN2022138736-appb-000006
)。
在本申请的实施例中，稳压装置10的输出电压V DD恢复的时间为t11-t0，远小于图2中的针对图1的LDO稳压器的输出电压V DD的恢复时间t1-t0。此外，由于电荷泵15没有静态功耗，与图1中的LDO稳压器相比，增加的迟滞比较器16的静态功耗远小于采用增加模拟环路带宽的静态功耗。
在本申请的一些实施例中，时钟信号的频率可以为40MHz。第一电容器41的电容C1可以为30fF至480fF，并且第一电容器41可调。第二电容器42的电容C2可以为30fF至480fF，并且第二电容器42可调。例如，在未使 用电荷泵的电压恢复时间大于10μs，而根据本发明实施例的稳压装置10可以使得输出电压在下降后迅速恢复到不小于第二门限电压V H的时间(即，t11-t0)大幅下降，例如不大于100ns。其中，需要说明的是，根据上文中第二门限电压V H与预设电压或稳定输出电压V'的差值的绝对值不超过预设电压或稳定输出电压V'(即，
Figure PCTCN2022138736-appb-000007
)的约5％的范围的情况下，输出电压V DD可以恢复到大于预设电压或稳定输出电压V'，可以小于预设电压或稳定输出电压V'，或者也可以恢复到等于预设电压或稳定输出电压V'，使得恢复时间不大于100ns。
在本申请的一些实施例中，NMOS晶体管也可以采用其他晶体管类型，比如，双极性晶体管(Bipolar)、场效应晶体管(FET)等。
图7为本申请的另一实施例的稳压装置20的电路结构示意图。
如图7所示，与上述的稳压装置10相比，稳压装置20的区别之处在于：第二调节电路包括控制器21，以取代稳压装置10中的迟滞比较器16。
其中，控制器21具有第一输出端211和第二输出端212。控制器21的第一输出端211与电荷泵15的使能控制端151连接，控制器21的第二输出端212与电荷泵15的时钟输入端153连接。
在控制器21获取指示稳压装置20的输出电压V DD将在第一时间下降的信息，并在到达第一时间前的第二时间产生并输出第三电平信号至使能控制端151，电荷泵15在接收到第三电平信号时开启，以提高栅极电压V GATE，借此以在稳压装置20的输出电压V DD下降前提高稳压装置20的输出电压。
通过上述方式，可以预先补偿输出电压V DD，当负载迅速变大导致输出电压V DD迅速下降时，使输出电压V DD在下降后也仍然保持在预设电压或稳定输出电压V'以上，维持负载电路的正常工作。在当负载电路对过高的输出电压V DD(即负载电路的供电电压)不敏感，而对过低的输出电压V DD比较敏感时，尤其合适。
在本申请的实施例中，指示稳压装置20的输出电压V DD将在第一时间下降的信息是基于稳压装置20的负载或负载电路将在第一时间变化的信息。具体地，控制器21存储有负载或负载电路将在第一时间被驱动或启动的信 息或任务，在该任务启动时，触发控制器21中的计时器或定时器(未示出)计时，并在到达第二时间时产生并输出第三电平信号以开启电荷泵15，借此以在到达第一时间之前(即输出电压下降之前)提前提高输出电压VDD。
需要说明的是，除了控制器21外，稳压装置20中的其他电路部分与稳压装置10中的除迟滞比较器16的电路部分的功能相同，具体见上文中的描述。另外，尽管电路组成元件和功能相同，但根据电路实际需要，元件的参数值可以相同，也可以不同。
图8为本申请的实施例的稳压装置20的各参数的时序关系示意图。
参考图7和图8，稳压装置20的工作原理如下。
控制器21获取或存储有稳压装置20的负载将在t0时刻变大的信息(即控制器21知晓负载将在t0时刻变大)，控制器21在t0时刻之前的t22时刻产生高电平信号并通过第一输出端211输出至电荷泵15的使能控制端151，同时控制器21通过第二输出端212提供时钟信号至电荷泵15的时钟输入端153，电荷泵15在使能控制端151为高电平时开启，并如上述针对图4A、图4B和图5的描述，电荷泵15根据时钟信号阶梯式地抬高NMOS晶体管11的栅极电压V GATE，相应地，输出电压V DD阶梯式地被抬高。
随后，在t23时刻，控制器21产生低电平信号并通过第一输出端211输出至电荷泵15的使能控制端151，电荷泵15在接收的使能控制信号为低电平时关闭，从而停止抬升栅极电压V GATE。
在t0时刻，稳压装置20启动驱动负载或负载电路，输出电压V DD迅速降低，但由于在t0时刻之前输出电压V DD已经被抬升至较高的值，输出电压V DD在t0时刻的下降后仍然保持在预设电压
Figure PCTCN2022138736-appb-000008
之上。然而，通过第一调节电路，输出电压V DD缓慢降低，并在t1时刻恢复到预设电压
Figure PCTCN2022138736-appb-000009
Figure PCTCN2022138736-appb-000010
将图8与图2对比可知，本申请的实施例的稳压装置20启动驱动负载或负载电路导致输出电压V DD下降时，输出电压V DD不会低于预设电压或稳定输出电压V'，对于特定负载电路(即对输出电压V DD高于预设电压不敏感的负载电路)，高于预设电压并不会使负载电路失效，从而可以保证负载电 路在输出电压V DD下降后仍然正常工作。另外，与针对图1中的LDO稳压器增加带宽导致增加静态功耗的方式相比，稳压装置20中的电荷泵15和控制器21均没有静态功耗，从而稳压装置20不会增加静态功耗。
在本申请的一些实施例中，控制器21可以经配置以通过调整以下参数中的一者或多者以提高栅极电压V GATE和输出电压的抬升幅度：电荷泵15中的第一电容器41的电容、电荷泵15中的第二电容器42的电容、时钟信号的频率、开启时间t22。其中，时钟信号的频率可以为40MHz。第一电容器41的电容可以为30fF至480fF，第一电容器41可调。第二电容器42的电容可以为30fF至480fF，第二电容器42可调。
本申请的实施例还提供了一种电源供电设备，包括电源和稳压装置10。本申请的实施例还提供了一种系统，包括上述的电源供电设备和负载电路。
本申请的实施例还提供了一种电源供电设备，包括电源和稳压装置20。本申请的实施例还提供了一种系统，包括上述的电源供电设备和负载电路。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然无需创造性劳动就可以对前述各实施例所记载的技术方案进行修改，或对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本申请的各实施例的技术方案的精神和范围。

Claims (15)

  1. 一种稳压装置，其具有电源端和输出端，其中，在所述稳压装置的所述电源端处提供电源电压，所述输出端用于连接到负载并提供输出电压，特征在于，所述稳压装置包括：
    NMOS晶体管，其具有连接到所述稳压装置的所述电源端的漏极、栅极和连接到所述稳压装置的所述输出端的源极；
    第一调节电路，其包括：
    分压电路，其连接于所述稳压装置的所述输出端与接地之间，所述分压电路用于基于所述稳压装置的所述输出端的所述输出电压产生反馈电压；以及
    误差放大器，其具有第一输入端、第二输入端和输出端，其中，在所述误差放大器的所述第一输入端处提供参考电压，所述第二输入端与所述分压电路连接，所述误差放大器的所述输出端与所述NMOS晶体管的所述栅极连接；以及
    第二调节电路，其包括：
    电荷泵，其具有使能控制端和输出端，其中，所述使能控制端经配置以接收使能控制信号，所述电荷泵的所述输出端连接到所述栅极，所述电荷泵经配置以根据所述使能控制信号选择性地开启以调节所述稳压装置的所述输出电压。
  2. 根据权利要求1所述的稳压装置，其特征在于，所述电荷泵进一步包括：
    时钟输入端，所述电荷泵经配置以通过所述时钟输入端接收时钟信号，并在开启后根据所述时钟信号提高所述NMOS晶体管的所述栅极处的电压，借此以提高所述稳压装置的所述输出电压。
  3. 根据权利要求2所述的稳压装置，其特征在于，所述电荷泵进一步包括：
    第一开关组，其包括多个开关；
    第二开关组，其包括多个开关；
    第一电容器，其与所述第一开关组耦合于所述稳压装置的所述电源端与所述接地之间，以及耦合于所述电荷泵的输出端与所述接地之间；
    第二电容器，其与所述第二开关组耦合于所述稳压装置的所述电源端与所述接地之间，以及耦合于所述电荷泵的输出端与所述接地之间；
    其中，当所述电荷泵开启且所述时钟信号为第一电平信号时，所述第一开关组和所述第二开关组中的开关被选择性地控制以使第一电容器充电且所述第二电容器放电；以及当所述电荷泵开启且所述时钟信号为第二电平信号时，所述第一开关组和所述第二开关组中的开关被选择性地控制以使所述第一电容器放电且所述第二电容器充电；以及
    其中，当所述使能控制信号为第三电平信号时，所述电荷泵开启，以及当所述使能控制信号为第四电平信号时，所述电荷泵关闭。
  4. 根据权利要求3所述的稳压装置，其特征在于，所述第一开关组包括第一开关、第二开关、第三开关和第四开关，其中，所述第一开关的第一端与所述稳压装置的所述电源端连接，所述第一开关的第二端与所述第一电容器的正极连接，所述第一电容器的负极与所述第二开关的第一端连接，所述第二开关的第二端与所述接地连接，所述第三开关的第一端与所述稳压装置的所述电源端连接，所述第三开关的第二端与所述第一电容器的所述负极连接，所述第四开关的第一端与所述第一电容器的所述正极连接，所述第四开关的所述第二端与所述电荷泵的所述输出端连接；以及
    所述第二开关组包括第五开关、第六开关、第七开关和第八开关，其中所述第五开关的第一端与所述稳压装置的所述电源端连接，所述第五开关的第二端与所述第二电容器的正极连接，所述第二电容器的负极与所述第六开关的第一端连接，所述第六开关的第二端与所述接地连接，所述第七开关的第一端与所述稳压装置的所述电源端连接，所述第七开关的第二端与所述第二电容器的所述负极连接，所述第八开关的第一端与所述第二电容器的所述正极连接，所述第八开关的第二端与所述电荷泵的所述输出端连接；
    其中，当所述使能控制信号为第三电平信号且所述时钟信号为第一电平 信号时，所述第一开关、所述第二开关、所述第七开关和所述第八开关闭合，所述第三开关、所述第四开关、所述第五开关和所述第六开关断开；
    当所述使能控制信号为所述第三电平信号且所述时钟信号为第二电平信号时，所述第一开关、所述第二开关、所述第七开关和所述第八开关断开，所述第三开关、所述第四开关、所述第五开关和所述第六开关闭合；以及
    当所述使能控制信号为第四电平信号时，所述第一开关组和所述第二开关组中的所有开关均断开。
  5. 根据权利要求4所述的稳压装置，其特征在于，所述电荷泵进一步包括：
    门控制电路，其包括所述使能控制端、所述时钟输入端、第一输出控制端和第二输出控制端；
    其中，所述第一输出控制端与所述第一开关、所述第二开关、所述第七开关和所述第八开关的控制端连接，所述第二输出控制端与所述第三开关、所述第四开关、所述第五开关和所述第六开关的控制端连接。
  6. 根据权利要求5所述的稳压装置，其特征在于，所述门控制电路进一步包括：
    “非”门、第一“与非”门、第二“与非”门、第三“与”门和第四“与”门；
    其中，所述第一“与非”门的第一输入端连接到所述时钟输入端，所述第一“与非”门的第二输入端连接到所述第二“与非”门的输出端，所述第一“与非”门的输出端连接到第二“与非”门的第一输入端和所述第三“与”门的第一输入端；
    所述“非”门的输入端连接到所述时钟输入端，所述“非”门的输出端连接到所述第二“与非”门的第二输入端，所述第二“与非”门的输出端连接到所述第四"与"门的第一输入端；
    所述第三“与”门的第二输入端和所述第四“与”门的第二输入端连接到所述使能控制端，所述第三“与”门的输出端为所述门控制电路的所述第一输出端，所述第四“与”门的输出端为所述门控制电路的所述第二输出端。
  7. 根据权利要求2所述的稳压装置，其特征在于，所述第二调节电路还包括：
    时钟电路，所述时钟电路经配置以输出所述时钟信号。
  8. 根据权利要求1-7任一项所述的稳压装置，其特征在于，所述第二调节电路进一步包括：
    迟滞比较器，其具有第一输入端、第二输入端和输出端，其中，在所述迟滞比较器的所述第一输入端处提供第一门限电压和第二门限电压，所述第一门限电压小于所述第二门限电压，所述迟滞比较器的所述第二输入端连接到所述稳压装置的所述输出端，所述迟滞比较器的所述输出端连接到所述电荷泵的所述使能控制端；
    其中，所述迟滞比较器经配置以基于所述稳压装置的所述输出电压、所述第一门限电压和所述第二门限电压产生所述输出信号，所述输出信号作为所述电荷泵的所述使能控制信号。
  9. 根据权利要求8所述的稳压装置，其特征在于，所述迟滞比较器进一步经配置以在当所述稳压装置的所述输出电压不大于所述第一门限电压时输出第三电平信号，以及在所述稳压装置的所述输出电压不小于所述第二门限电压时输出第四电平信号。
  10. 根据权利要求9所述的稳压装置，其特征在于，所述电荷泵经配置以在所述使能控制信号为所述第三电平信号时开启以提高所述栅极处的电压，借此以在所述稳压装置的所述输出电压下降后提高和恢复所述稳压装置的所述输出电压。
  11. 根据权利要求1-7任一项所述的稳压装置，其特征在于，所述第二调节电路进一步包括：
    控制器，其经配置以获取指示所述稳压装置的所述输出电压将在第一时间下降的信息，并在到达所述第一时间前的第二时间时产生第三电平信号至所述使能控制端；
    所述电荷泵进一步经配置以在接收到所述第三电平信号时开启，以提高所述栅极处的所述电压，借此以在所述稳压装置的所述输出电压下降前提高 所述稳压装置的所述输出电压。
  12. 根据权利要求11所述的稳压装置，其特征在于，所述控制器进一步经配置以提供时钟信号至所述电荷泵的时钟输入端。
  13. 根据权利要求12所述的稳压装置，其特征在于，指示所述稳压装置的所述输出电压将在所述第一时间下降的信息是基于所述稳压装置的负载将在第一时间变化的信息。
  14. 根据权利要求13所述的稳压装置，其特征在于，所述控制器经配置以在所述第一时间启动驱动所述负载。
  15. 根据权利要求11所述的稳压装置，其特征在于，所述控制器经配置以调整所述电荷泵中的以下参数中的一个或多个：电容、时钟频率、开启时间。
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