WO2023109570A1 - 赝配高迁移率晶体管、低噪声放大器及相关装置 - Google Patents

赝配高迁移率晶体管、低噪声放大器及相关装置 Download PDF

Info

Publication number
WO2023109570A1
WO2023109570A1 PCT/CN2022/136830 CN2022136830W WO2023109570A1 WO 2023109570 A1 WO2023109570 A1 WO 2023109570A1 CN 2022136830 W CN2022136830 W CN 2022136830W WO 2023109570 A1 WO2023109570 A1 WO 2023109570A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
phemt
doped
channel layer
channel
Prior art date
Application number
PCT/CN2022/136830
Other languages
English (en)
French (fr)
Inventor
于明朗
滕腾
叶键伟
余杰
周小敏
徐煜思
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22906320.1A priority Critical patent/EP4451341A1/en
Priority to KR1020247022324A priority patent/KR20240117599A/ko
Priority to CN202280076882.2A priority patent/CN118369768A/zh
Publication of WO2023109570A1 publication Critical patent/WO2023109570A1/zh
Priority to US18/742,080 priority patent/US20240332412A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to the technical field of semiconductor devices, in particular to a pseudo high-mobility transistor, a low-noise amplifier and related devices.
  • intermodulation distortion intermodulation distortion
  • IMD intermodulation distortion
  • the embodiment of the present application provides a pseudo high-mobility transistor PHEMT, a low-noise amplifier and related devices, by making the conduction band energy level of the channel layer smaller than the Fermi energy when the output current of the PHEMT is smaller than the first threshold stage, thereby improving the linearity of the PHEMT when the output current is small, thereby reducing the intermodulation distortion caused by the nonlinearity of the LNA.
  • the embodiment of the present application provides a pseudo high mobility transistor PHEMT, including:
  • the lower barrier layer is connected to the channel layer;
  • the first isolation layer is used to isolate the first doped layer from the channel layer
  • the first doped layer is used to provide a two-dimensional electron gas
  • the conduction band energy level of the channel layer is lower than the Fermi energy level.
  • the conduction band energy level of the channel layer when the output current of the PHEMT is less than the first threshold is smaller than the Fermi level, thereby improving the small output current
  • the linearity of PHEMT and then reduce the intermodulation distortion caused by LNA non-linearity.
  • the lower barrier layer is directly connected to the channel layer.
  • the gradient of the energy level of the channel layer along the thickness direction is smaller, so that the conduction band energy level of the channel layer is smaller than the Fermi level when working with a small current.
  • the first doped layer is silicon-doped with a doping concentration of 3e 12 cm ⁇ 2 to 5e 12 cm ⁇ 2 .
  • the doping concentration of the first doping layer may also be 5e 12 cm ⁇ 2 to 6e 12 cm ⁇ 2 .
  • the gain of the PHEMT is increased by increasing the concentration of the first doped layer.
  • the lower barrier layer is connected to the channel layer through a second isolation layer and a second doped layer, and the second isolation layer is used to isolate the channel layer from the A second doped layer, the second doped layer is used to provide a two-dimensional electron gas.
  • the above-mentioned PHEMT is a double-doped PHEMT, such as a double delta-doped PHEMT.
  • the doping concentration of the first doping layer is 3.5e 12 cm -2 to 4.5e 12 cm -2
  • the doping concentration of the second doping layer is 3e 11 cm -2 2 to 5e 11 cm -2 .
  • the doping concentration of the first doping layer is 4e 12 cm -2 to 6e 12 cm -2
  • the doping concentration of the second doping layer is 2e 8 cm -2 to 3e 11 cm ⁇ 2 .
  • a ratio of the doping concentration of the first doped layer to the doping concentration of the second doped layer is greater than a preset value.
  • the preset value is a positive number greater than 6, for example, 9, 10, 15, 30, 70, 100, 150 and so on.
  • the doping concentration of the lower doped layer (the second doped layer) is reduced or the upper doped layer (the first doped layer) and the lower doped layer are increased while the total doping concentration remains unchanged or does not decrease.
  • the ratio of the doping concentration of the layer (the second doped layer) makes the gradient of the energy level of the channel layer along the thickness direction smaller, so that the conduction band energy level of the channel layer is smaller than the Fermi energy level.
  • the thickness of the channel layer is 15nm-20nm, or 18nm-20nm, or 20nm-25nm. For example, 18nm.
  • the conduction band energy level of the channel layer when the output current of the PHEMT is less than the second threshold, the conduction band energy level of the channel layer generally decreases along the thickness direction.
  • the above-mentioned PHEMT by increasing the thickness of the channel layer, avoids the accumulation of electrons under the channel layer when the device is in operation, so that the electron distribution is more uniform, thereby improving the linearity of the PHEMT.
  • the PHEMT further includes: a cap layer, a source, a drain, and a gate; wherein, the cap layer is disposed on the side of the upper barrier layer away from the channel layer and opened The hole is used to provide an ohmic contact; the gate is arranged in the through hole; the source and the drain are both arranged on the side of the cap layer away from the upper barrier layer and are respectively located at the on both sides of the through hole.
  • the channel layer is made of indium gallium arsenide; the upper barrier layer or the lower barrier layer or the isolation layer is aluminum gallium arsenide.
  • the embodiment of the present application further provides a low noise amplifier, including: the PHEMT described in the first aspect or any possible implementation of the first aspect.
  • an embodiment of the present application further provides a radio frequency circuit, including: the low noise amplifier as described in the second aspect.
  • the embodiment of the present application also provides a radio frequency chip, including: the PHEMT as described in the first aspect or any possible implementation of the first aspect, the low-noise amplifier as described in the second aspect, and the low-noise amplifier as described in the first aspect. At least one of the radio frequency circuits described in the three aspects.
  • the embodiment of the present application also provides an electronic device, which is characterized in that it includes: the PHEMT described in the first aspect or any possible implementation of the first aspect, and the low-noise device described in the second aspect
  • the amplifier is at least one of the radio frequency circuit described in the third aspect and the radio frequency chip described in the fourth aspect.
  • FIG. 1 is a schematic illustration of an intermodulation signal generated on a receiving link at an antenna end provided by an embodiment of the present application.
  • FIG. 2A is a schematic structural diagram of a double delta-doped PHEMT provided in the prior art.
  • FIG. 2B is an example diagram of a DC output characteristic curve of the PHEMT shown in FIG. 2A .
  • Fig. 2C is a schematic diagram of the energy band structure of the PHEMT shown in Fig. 2A.
  • FIG. 2D is an exemplary graph of the curves of the OIP3 value of the PHEMT shown in FIG. 2A at different output currents.
  • Fig. 3 is a schematic diagram of defining OIP3 values in the prior art.
  • FIG. 4 is a schematic structural diagram of a cross-section of a single delta-doped PHEMT provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a cross-section of a double delta-doped PHEMT provided in an embodiment of the present application.
  • FIG. 6 is an example diagram of the curves of the OIP3 values of the double delta-doped PHEMT provided by the prior art and the single delta-doped PHEMT provided by the implementation of the present application under different output currents.
  • Fig. 7A is an example diagram of energy bands of a double delta-doped PHEMT provided by the prior art.
  • FIG. 7B is an exemplary energy band diagram of a single delta-doped PHEMT provided in an embodiment of the present application.
  • FIG. 7C is an example diagram of the conduction band structure at the channel layer of a single delta-doped PHEMT and a double delta-doped PHEMT provided by the embodiment of the present application.
  • Fig. 8 is a graph showing the concentration distribution of electrons when the output current is 60mA/mm in double ⁇ -doped PHEMTs with channel layer thicknesses of 12nm and 18nm respectively.
  • FIG. 9 is a schematic diagram of a circuit structure of an LNA provided by an embodiment of the present application.
  • Fig. 10 is a schematic diagram of a wireless radio frequency system provided by an embodiment of the present application.
  • the duplexer is also called an antenna duplexer, and its function is to isolate the transmission signal transmitted through the shared antenna from the received signal received through the shared antenna, so as to ensure that both the transmission link and the reception link can work simultaneously. If the interference caused by the intermodulation signal to the received signal is reduced by improving the isolation of the duplexer, it is necessary to increase the cavity of the duplexer, which will increase the volume of the duplexer and greatly increase the cost.
  • Another method is to reduce the leakage signal and the intermodulation signal generated by the received signal that cannot be completely suppressed by the filter by increasing the linearity of the low-noise amplifier (LNA).
  • LNA low-noise amplifier
  • the linearity of the LNA is determined by the die of the transistor.
  • the transistor can be a pseudomorphic high electron mobility transistor (PHEMT).
  • GaAs gallium arsenide
  • the epitaxial layers of the die are buffer layer, lower barrier layer, lower delta-doped layer, and lower isolation layer from top to bottom. layer, channel layer (channel layer), upper isolation layer, upper delta-doped layer, upper barrier layer and cap layer.
  • the buffer layer on the substrate can be gallium arsenide or aluminum gallium arsenide, which is used to reduce the defects of the substrate from entering other layers of the PHEMT; the lower barrier layer and the upper barrier layer It can be aluminum gallium arsenide (AlGaAs), used to prevent two-dimensional electron gas from entering the buffer layer; both the lower delta-doped layer and the upper delta-doped layer can be silicon (Si) doped, used to provide two-dimensional electron gas;
  • the upper and lower isolation layers can be aluminum gallium arsenide (AlGaAs), which is used to isolate the doped layer from the channel layer; the channel layer can be indium gallium arsenide (InGaAs); the cap layer can be highly doped arsenic GaN, which connects the source and drain.
  • FIG. 2B it is the DC output characteristic curve of the PHEMT shown in FIG. 2A.
  • five different gate voltages are marked in Fig. 2B to distinguish the five working states of the PHEMT, namely the off state 1, the state about to be turned on 2, the on state 3, the fully on state 4 and the linear working state 5 .
  • FIG. 2C it is a schematic diagram of the energy band structure of the PHEMT shown in FIG. 2A in five different working states. It should be understood that only the conduction band structure of each layer is shown in each energy band structure diagram in FIG. 2C, and from left to right, that is, along the thickness direction, there are cap layer, upper barrier layer, upper ⁇ -doped layer, conduction bands of the upper isolation layer, the channel layer, the lower isolation layer, the lower delta-doped layer and the lower barrier layer. Only the positions of the upper delta-doped layer, the lower delta-doped layer and the channel layer are marked in the figure.
  • the conduction band energy level of the channel layer is much higher than the Fermi level Ef; as the gate voltage increases, when the PHEMT is about to turn on state 2, the channel layer The conduction band energy level of the channel layer is about to touch the Fermi level Ef; as the gate voltage further increases, when the conduction band energy level of the channel layer is partly lower than the Fermi level Ef, a certain amount of free Electronics, at this time, the PHEMT is in the open state 3; when the gate voltage is further increased, the conduction band structure in the channel layer will change from the form of high left and right low in the open state 3 to a fully open state 4 and a linear working state In the state of 5, the carriers tend to be located on the upper side of the channel layer (ie, the left side in FIG. 2D , that is, the side adjacent to the upper isolation layer).
  • the working state of the LNA device is limited to an output current density of 60-100mA/mm, that is, the vicinity of the PHEMT open state 3 in Figure 2C.
  • the output current at the working point is limited to around 60-100mA/mm. Due to the high electron mobility of PHEMT, only a small two-dimensional electron gas is required. The concentration can reach the working state current, so that the working point is mostly near the turn-on voltage of PHEMT. However, the linearity of PHEMT in this range is low, which cannot meet the application requirements.
  • the linearity of PHEMT is represented by the output 3rd order intercept point (OIP3). The higher the OIP3, the better the linearity.
  • OIP3 output 3rd order intercept point
  • LNA Low noise amplifier
  • the received signal from the antenna is generally very weak. To amplify such a weak signal, the most important thing is to ensure the signal quality, which requires the LNA not to introduce too much noise, otherwise the signal will be further deteriorated and demodulation cannot be performed.
  • the LNA uses transistors and field effect transistors.
  • the LNA adopts a pseudomorphic high electron mobility transistor (PHEMT).
  • PHEMT pseudomorphic high electron mobility transistor
  • the intermodulation signal is the intermodulation frequency signal generated by the interaction between the non-modulated signal and the useful signal after passing through the nonlinear device. Since the frequency of the intermodulation signal is very close to the useful signal, it is difficult to be suppressed by the filter at the back end. As shown in Figure 1, when the received signal (that is, the useful signal) and the transmitted signal (that is, the interference signal) leaked into the receiving chain pass through the LNA at the same time, due to the nonlinear effect, the intermodulation signal generated by the two signals Sometimes the frequency is exactly equal to or close to the frequency of the received signal and passes through the receiver smoothly. Among them, the third-order intermodulation is the most serious, and the resulting interference is called intermodulation interference.
  • PHEMT is an improvement on high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • 2DEG two-dimensional electron gas
  • FIG. 2A it is a typical double delta-doped PHEMT.
  • the linearity of PHEMT can be characterized by the output 3rd order intercept point (OIP3), the higher the value of OIP3, the better the linearity.
  • OIP3 can be obtained from the PHEMT RF input and output curves by drawing. As shown in FIG. 3 , specifically, two curves are drawn, one is the plot of the amplified signal power at the input frequency against the input power, and the other is the plot of the third-order intermodulation signal against the input power.
  • the linear amplification signal curve is a straight line with a slope of 1
  • the third-order intermodulation signal curve is a straight line with a slope of 3.
  • the output signal power corresponding to their intersection point is the OIP3 value.
  • the output current referred to in various embodiments of the present application is also referred to as the current output from the drain.
  • Small output current also referred to as small current for short, means that the output current is less than the first threshold or less than the second threshold, where the first threshold or the second threshold can be the current density when the PHEMT is just turned on, or the output current of the PHEMT
  • the density is 40mA/mm-200mA/mm, or 60mA/mm-100mA/mm.
  • the first threshold may or may not be equal to the second threshold.
  • the minimum output current is 60 mA/mm as an example for illustration.
  • the current appearing in each embodiment of the present application also refers to the current density.
  • the embodiment of the present application adjusts the energy band structure of the channel layer of the PHEMT by designing the thickness and material of each layer structure in the PHEMT, especially the thickness of the epitaxial layer, the doping concentration of the doped layer, etc., so that the PHEMT can operate at a small output
  • the conduction band energy level of the channel layer is smaller than the Fermi level, so that with the increase of the gate voltage, the increase of the electron concentration near the Fermi level has a greater influence on the electron concentration of the channel layer. Small, thereby improving the linearity of PHEMT. From the conduction band structure, the conduction band gradient of the channel layer is smaller in the on state 3.
  • the main factors affecting the energy band structure of the channel layer include the following:
  • Doping concentrations of upper/lower doped layers will change the degree of bending of the energy band of its upper layer structure. For example, an increase in the doping concentration of the upper doped layer will make the energy band of the upper barrier layer bend more, that is, the energy level of the upper barrier layer has a larger gradient along the thickness direction; The higher the doping concentration of the layer, the greater the bending of the energy band of the channel layer, and the greater the gradient of the energy level of the channel layer along the thickness direction.
  • reducing the concentration of the lower doped layer can make the energy band bending of the channel layer smaller, that is, the gradient of the energy level of the channel layer along the thickness direction is smaller, so that when the output current is small, the channel layer The conduction band energy level is smaller than the Fermi level.
  • the ratio of the doping concentration of the upper/lower doping layer In order to meet the requirement that the conduction band energy level of the channel layer of the PHEMT is lower than the Fermi level when the PHEMT works at a small current, the doping concentration of the lower doped layer will be reduced. However, the total doping concentration of the upper/lower doped layer It will affect the carrier concentration, thereby affecting the performance of the device. On the other hand, the higher the doping concentration, the higher the turn-on voltage of the device. Therefore, the total doping concentration can neither be too low nor too high.
  • the thickness of the channel layer will affect the distribution of electrons and current.
  • a thicker channel layer can avoid the accumulation of electrons under the channel layer when the device is working, so that the electron distribution is more uniform, thereby improving the linearity of the PHEMT.
  • the embodiments of the present application provide the following solutions to adjust the energy band structure of the channel layer, so that the conduction band energy levels of the channel layer are all lower than the Fermi energy level when the channel layer operates with a small current.
  • Solution 1 remove the lower doped layer, so that the gradient of the energy level of the channel layer along the thickness direction is smaller, so that the conduction band energy level of the channel layer is smaller than the Fermi level when working with a small current.
  • Solution 2 without reducing the total doping concentration, reduce the doping concentration of the lower doped layer or increase the ratio of the doping concentration of the upper doped layer to the lower doped layer.
  • Solution 3 increasing the thickness of the channel layer.
  • the above scheme can improve the linearity of PHEMT by adjusting the thickness and doping concentration of each layer structure in PHEMT, so that the conduction band energy level of the channel layer is lower than the Fermi level when it works at a small current, thereby improving the linearity of PHEMT
  • the linearity of the formed LNA reduces the intermodulation signal output by the LNA and improves the quality of the signal.
  • the schematic diagram of the cross-section of the PHEMT is adjusted by using the above-mentioned scheme one, or a combination of scheme one and adjusting the thickness of the upper barrier layer and/or upper isolation layer, and at least one of the above-mentioned scheme two and scheme three The band structure of the channel layer.
  • the PHEMT is single delta-doped, including a substrate 1, a buffer layer 2, a lower barrier layer 3, a channel layer 4, an upper isolation layer 5, a first Doped layer 6 , upper barrier layer 7 and cap layer 8 , source 9 and drain 10 disposed on cap layer 8 , and gate 11 disposed on upper barrier layer 7 .
  • GaAs-based PHEMT the function, composition and thickness of each layer are explained separately:
  • the substrate 1 may be a gallium arsenide (GaAs) wafer.
  • GaAs gallium arsenide
  • the buffer layer 2 can be gallium arsenide (GaAs) or aluminum gallium arsenide (Al x Ga 1-x As), where 0 ⁇ x ⁇ 1, the buffer layer 2 can prevent defects of the substrate 1 from entering the die of the PHEMT.
  • the doping concentration of Al in the buffer layer gradually increases along the direction away from the substrate 1 , which can reduce defects caused by lattice mismatch between the substrate 1 and the lower barrier layer 3 .
  • the lower barrier layer 3 can be aluminum gallium arsenide (Al x Ga 1-x As), its forbidden band width is greater than that of the channel layer 4, and is used to form a heterojunction with the channel layer 4, which is an antijunction .
  • the thickness of the lower barrier layer 3 may be 10-50 nm or 10-25 nm, for example, 17 nm, 20 nm and so on.
  • the highest doping concentration of Al in the buffer layer 2 is not greater than the doping concentration of Al in the lower barrier layer 3 .
  • the channel layer 4 may be indium gallium arsenide (In y Ga 1-y As), where 0 ⁇ y ⁇ 1, for example, the range of y may be 0.1-0.5, for example, y is 0.22, 0.3.
  • the thickness of the channel layer 4 may be greater than 8 nm or 12 nm and less than the critical thickness of the channel epitaxial layer.
  • the critical thickness is 20 nm, and the critical thickness increases as the indium content decreases.
  • the thickness of the channel layer 4 may be 8nm-30nm, or 12m-30nm or 15nm-20nm, for example, 17nm, 18nm, 20nm, 24nm and so on.
  • the distribution of electrons and current in the channel layer 4 can be improved, thereby avoiding the accumulation of electrons under the channel layer 4, reducing the vertical (that is, the stacking direction of the PHEMT) current, thereby improving the linearity of the PHEMT Spend.
  • the channel layer 4 is In 0.22 Ga 0.78 As with a thickness of 18 nm.
  • the upper isolation layer 5 is used to isolate the channel layer 4 and the first doped layer 6, so as to prevent the doping impurities of the first doped layer 6 from entering the channel layer 4.
  • the upper isolation layer 5 can be aluminum gallium arsenide, and its thickness can be It is 2nm-6nm, such as 4nm and 6nm.
  • the upper isolation layer 5 is also referred to as a first isolation layer.
  • the first doped layer 6 can be delta-doped, also known as the upper delta-doped layer, which can be silicon-doped, by growing a thin layer of silicon on the upper isolation layer 5 as a doping impurity for the After being ionized, it provides a two-dimensional electron gas. Its thickness may be several atoms, and its thickness is less than 2 nm, for example, 1 nm or less.
  • the doping concentration of the first doped layer 6 is the sum of the doping concentrations of the two doping layers in the double delta-doped PHEMT in the prior art, or the doping concentration is 3e 12 cm ⁇ 2 to 5e 12 cm -2 , or 5e 12 cm -2 to 6e 12 cm -2 , 1e 12 cm -2 to 3e 12 cm -2 , 4.6e 12 cm -2 to 5.5e 12 cm -2 , 5.5e 12 cm -2 to 6.5e 12 cm -2 , exemplarily, 4.5e 12 cm -2 .
  • the upper barrier layer 7 can be aluminum gallium arsenide (Al x Ga 1-x As), its forbidden band width is greater than the forbidden band width of the channel layer 4, and it is used to combine with the first doped layer 6 and the upper isolation layer 5 Together with the channel layer 4 to form a heterojunction, which is a positive junction. Its thickness may be 10nm-30nm or 10-25nm, such as 15nm, 17nm, 20nm and so on.
  • the capping layer 8 may be heavily doped gallium arsenide (n+-GaAs) with a thickness of 5nm-10nm for providing an ohmic contact.
  • the cap layer 8 is provided with a through hole, the gate 11 is arranged in the through hole and is not in contact with the cap layer 8, the source electrode 9 and the drain electrode 10 are both arranged on the side of the cap layer 8 away from the upper barrier layer 7 and are respectively located in the through hole. both sides of the hole.
  • the source 9, the drain 10, and the gate 11 are all conductive metals, and the gate 11 is used to provide the gate voltage for the PHEMT.
  • the gate voltage is greater than the turn-on voltage, the source 9 and the drain 10 are conducted. , the output drain current.
  • the lower barrier layer 3 is directly connected to the channel layer 4 .
  • directly connected refers to direct contact, that is, no other layer structure is included between the lower barrier layer 3 and the channel layer 4 .
  • the buffer layer 2, the lower barrier layer 3, the upper isolation layer 5, and the upper barrier layer 7 can all use aluminum gallium arsenide (Al x Ga 1-x As), the Al in each layer The doping concentration can be the same or different, which is not limited here.
  • the lower barrier layer 3, the upper isolation layer 5, and the upper barrier layer 7 are all made of Al 0.22 Ga 0.78 As.
  • the single delta-doped PHEMT provided in the embodiment of the present application has a doped positive junction (upper Barrier layer 7/first doped layer 6/upper isolation layer 5/channel layer 4) and an undoped anti-junction (channel layer 4/lower barrier layer 3), when the gate voltage is greater than the turn-on voltage
  • the doped impurity is ionized, the discontinuity of the conduction band caused by the difference in the forbidden band width of the upper barrier layer 7 and the channel layer 4 makes electrons transfer to the side of the channel layer, thereby forming a two-dimensional electron gas , the source 9 and the drain 10 are turned on, and the drain current is output.
  • the embodiment of the present application is based on the adjustment mechanism of the energy band structure of the above-mentioned channel layer, removes the lower doped layer, selects a suitable concentration of the upper doped layer (that is, the first doped layer 6), and selects a suitable channel layer 4 , the thickness of the upper barrier layer 7 and the upper isolation layer 5, etc., the conduction band energy level of the channel layer 4 of the obtained single ⁇ -doped PHEMT is smaller than the Fermi level when the output current is a small current, or the channel layer The conduction band energy level at the boundary between 4 and the upper isolation layer 5 is smaller than the Fermi level.
  • the conduction band energy level of the channel layer 4 generally decreases along the thickness direction.
  • the thickness direction in the embodiment of the present application refers to the direction from the cap layer to the substrate, which can be referred to the direction indicated in FIG. 4; the approximate decrease can include the following two situations:
  • the conduction band energy level of the channel layer 4 decreases along the thickness direction, that is, the farther away from the upper barrier layer, the lower the conduction band energy level decreases.
  • the conduction band energy level of the channel layer 4 has a downward trend overall/macroscopically along the thickness direction, that is, the barrier layer is farther away in a small area/microscopic distance but the conduction band energy level is higher.
  • the thickness of the upper barrier layer 7 is 3-7nm
  • the thickness of the upper isolation layer 5 is 4nm
  • the doping concentration of the first doped layer 6 is 3.0-4.5e12cm-2
  • the thickness of the channel layer is 12nm
  • the thickness of the upper barrier layer 7 is 5 nm
  • the thickness of the upper isolation layer 5 is 3-5 nm
  • the doping concentration of the first doped layer 6 is 3.0-4.5e12 cm-2
  • the thickness of the channel layer is 8 ⁇ 14nm.
  • the embodiment of the present application provides a single delta-doped PHEMT, in which only the upper barrier layer 7 is subjected to delta Doping, by removing the lower doped layer, reduces the conduction band energy level gradient of the channel layer 4 along the thickness direction, so that the linearity of the PHEMT can be improved for small output currents without affecting the gain (ie gm transconductance) Spend.
  • the distribution of electrons and currents in the channel layer 4 can be improved, thereby avoiding the accumulation of electrons under the channel layer 4, reducing the vertical (that is, the stacking direction of the PHEMT) current, and further Improve the linearity of PHEMT.
  • another PHEMT provided by the embodiment of the present application can be a double-doped PHEMT, which can also include a second doped layer 12 in addition to the layer structure shown in Figure 4 And the lower isolation layer 13.
  • Both the first doped layer 6 and the second doped layer 12 may be delta-doped, therefore, the first doped layer 6 is also called the upper delta-doped layer 6, and the second doped layer 12 is also called the lower delta-doped layer.
  • the doping concentration of the first doped layer 6 is greater than that of the second doped layer 12 .
  • the lower isolation layer 13 is used to isolate the second doped layer 12 and the channel layer 4 , preventing the doping impurities of the second doped layer 12 from entering the channel layer 4 .
  • the lower isolation layer 13 may be aluminum gallium arsenide, and its thickness may be 2nm-6nm, for example, 4nm.
  • the lower isolation layer 13 is also referred to as a second isolation layer.
  • buffer layer 2, the lower barrier layer 3, the upper isolation layer 5, the lower isolation layer 13, and the upper barrier layer 7 can all use aluminum gallium arsenide, the doping concentration of Al in each layer can be Same or different, not limited here.
  • the double delta-doped PHEMT provided in the embodiment of the present application has a doped positive junction (upper barrier layer 7/first doped layer 6/upper isolation layer 5/channel layer 4) and a doped antijunction (channel layer 4/lower isolation layer 13/second doped layer 12/lower barrier Layer 3), when the gate voltage is greater than the turn-on voltage, the doped impurities are ionized, and the conduction band discontinuity caused by the difference in the forbidden band width of the barrier layer and the channel layer 4 makes electrons transfer to the channel One side of the layer, thereby forming a two-dimensional electron gas, the source 9 and the drain 10 are turned on, and the drain current is output.
  • the energy band structure of the channel layer is adjusted by adopting the above-mentioned scheme three.
  • the PHEMT shown in FIG. exceeds the relaxation limit of the InGaAs epitaxial channel layer), so that the conduction band energy level of the channel layer 4 is smaller than the Fermi level when the output current of the double ⁇ -doped PHEMT is a small current.
  • the thickness of the channel layer 4 is 8nm-30nm, or 12nm-30nm or 15nm-20nm, exemplarily, 17nm, 18nm, 20nm, 24nm and so on.
  • the thickness or critical thickness of the channel layer 4 is related to the content of indium, the lower the content of indium, the thicker it is.
  • the channel layer 4 is In 0.22 Ga 0.78 As with a thickness of 18 nm.
  • the above-mentioned double delta-doped PHEMT can improve the distribution of electrons and current in the channel layer 4 by increasing the thickness of the channel layer 4, thereby avoiding the accumulation of electrons under the channel layer 4, reducing the current in the thickness direction, and greatly improving Linearity of PHEMT.
  • the above scheme 2 is adopted to adjust the energy band structure of the channel layer, so that the conduction band energy level of the channel layer 4 is lower than the Fermi level when the output current of the double ⁇ -doped PHEMT is small.
  • the doping concentration of the first doped layer 6 is 3.5 ⁇ 4.5e 12 cm ⁇ 2
  • the doping concentration of the second doped layer 12 is 3 ⁇ 5e 11 cm ⁇ 2 .
  • the doping concentration ratio of the first doped layer 6 and the second doped layer 12 is greater than a preset value, and the preset value is not less than 6, for example 9, 10, 15, 30, 70, 100, 150 etc.
  • the doping concentration of the first doped layer 6 is 4e 12 cm ⁇ 2 to 6e 12 cm ⁇ 2
  • the doping concentration of the second doped layer 12 is 2e 8 cm ⁇ 2 to 3e 11 cm ⁇ 2 , or 1e 6 cm -2 to 1e 11 cm -2 , or 1e 6 cm -2 to 1e 8 cm -2 .
  • the doping concentration of the first doped layer 6 is 3.5-4.5e 12 cm -2 , or 4.5-6e 12 cm -2 , or 4.6-5.5e 12 cm -2 of the second doped layer 12
  • the doping concentration is 2e 8 cm ⁇ 2 to 3e 11 cm ⁇ 2 .
  • the above-mentioned double delta-doped PHEMT reduces the energy level gradient of the channel layer 4 caused by the second doped layer 12 by adjusting the doping concentration of the upper/lower delta-doped layer and the ratio of the doping concentration, so that the device operates at a small current During operation, the conduction band energy level of the channel layer 4 is smaller than the Fermi energy level, thereby improving the linearity of the device.
  • the energy band structure of the channel layer is adjusted by using the combination of the above-mentioned scheme two and scheme three, so that the conduction band energy level of the channel layer 4 is less than that of the double delta-doped PHEMT when the output current is a small current.
  • meter energy level Exemplarily, the thickness of the channel layer is 18 nm, the doping concentration of the first doped layer 6 is 3.5 ⁇ 4.5e 12 cm ⁇ 2 , and the doping concentration of the second doped layer 12 is 2e 8 cm ⁇ 2 to 3e 11 cm -2 .
  • the doping concentration ratio of the first doped layer 6 and the second doped layer 12 is set to be greater than a preset value, and the preset value is not less than 6, for example 9.
  • the above-mentioned double delta-doped PHEMT reduces the energy level gradient of the channel layer 4 caused by the lower doped layer by adjusting the doping concentration and the ratio of the doping concentration of the upper/lower doped layer, so that when the device works at a small current,
  • the conduction band energy level of the channel layer 4 is smaller than the Fermi energy level, thereby improving the linearity of the device.
  • the combination of scheme two and/or scheme three and adjusting the thickness of the upper barrier layer and/or the upper isolation layer is used to adjust the energy band structure of the channel layer, so that the double delta-doped PHEMT is When the output current is a small current, the conduction band energy level of the channel layer 4 is smaller than the Fermi energy level.
  • the thickness of the upper barrier layer 7 is 3-7 nm
  • the thickness of the upper isolation layer 5 is 3-5 nm
  • the doping concentration of the first doped layer 6 is 3.0-4.5e 12 cm -2
  • the second doped The doping concentration of the impurity layer 12 is 3-5e 11 cm -2
  • the thickness of the channel layer is 18nm.
  • the thickness of the upper barrier layer 7 is 3-7 nm
  • the thickness of the upper isolation layer 5 is 3-5 nm
  • the doping concentration of the first doped layer 6 is 3.0-4.5e 12 cm -2
  • the second The doping concentration of the doping layer is 2e 8 cm -2 to 3e 11 cm -2
  • the thickness of the channel layer is 14-20nm.
  • the upper barrier layer 7 has a thickness of 5 nm
  • the upper isolation layer 5 has a thickness of 4 nm
  • the doping concentration of the first doped layer 6 is 3.0-4.5e 12 cm -2
  • the doping concentration of the second doped layer The doping concentration is 2e 8 cm -2 to 3e 11 cm -2
  • the thickness of the channel layer is 14-20nm.
  • the conduction band energy level of the channel layer 4 when the PHEMT outputs a small current, the conduction band energy level of the channel layer 4 generally decreases along the thickness direction.
  • the above-mentioned layer structures in FIG. 4 or FIG. 5 can also use other materials and have other thicknesses, for example, they can also be ternary, quaternary or multi-component compounds of gallium arsenide.
  • the PHEMT is a gallium phosphide (GaP)-based PHEMT.
  • the upper doped layer or the upper ⁇ -doped layer described in FIG. 4 and FIG. 5 corresponds to the first doped layer 6, and the lower doped layer or the lower ⁇ -doped layer corresponds to the second Miscellaneous 12.
  • the OIP3 value of the single ⁇ -doped PHEMT proposed in the embodiment of the present application has been significantly improved, and when the output drain current is 60-100mA, the OIP3 value has been increased by more than 5dBm.
  • Figure 6 compares the simulation results of the OIP3 value of the double delta-doped PHEMT in the prior art with the simulation results of the OIP3 value of the single delta-doped PHEMT provided in the embodiment of the present application.
  • the OIP3 value of the single delta-doped PHEMT provided in the embodiment of the present application has an increase of more than 5 dBm when the output current is between 50 mA and 200 mA.
  • Figure 7A is the energy band diagram of the double delta-doped PHEMT in the prior art
  • Figure 7B is the energy band diagram of the single delta-doped PHEMT provided by the embodiment of the present application
  • Figure 7C compares the double delta-doped PHEMT and The conduction band structure at the channel layer of a single delta-doped PHEMT. It should be understood that as the gate voltage increases, the Fermi energy level increases, where the position of the Fermi energy level when the drain current (that is, the output current) is 60 mA is marked in FIGS. 7A-7C .
  • the space charge will be concentrated and distributed at the ⁇ -doped position, the energy band on the left side of the ⁇ -doped position will be bent.
  • the output current is 60mA
  • the conduction band structure of the single-delta-doped PHEMT at the channel is closer to a square, while the double-delta-doped PHEMT is closer to a triangle, see Figure 7C Middle shaded area. Since the electron concentration in the channel layer is proportional to the area of the polygon surrounded by the conduction band and the Fermi level, the square conduction band structure has a higher linearity.
  • the conduction band of the single delta doped PHEMT channel will be larger than that of the double delta doped PHEMT channel
  • the conduction band of the channel is lower than the Fermi level, and the electrons near the Fermi level have a Fermi-Dirac distribution, that is, near the Fermi level (see the dotted box area in Figure 7C), the probability of electrons appearing is 0.5, when the electron is less than the Fermi level, the probability of electron appearance is 1. In this way, the appearance probability of electrons near the Fermi level has a certain nonlinearity with the change of the gate voltage.
  • the electrons near the Fermi level in the conduction band structure of the PHEMT channel designed with single delta doping The proportion in the band structure is lower, so the single delta doping design away from the Fermi level can provide higher linearity.
  • FIG. 8 shows the distribution diagram of electron concentration when the output current is 60mA/mm in double ⁇ -doped PHEMTs with channel layer thicknesses of 12nm and 18nm respectively. It can be seen from Figure 8 that when the PHEMT works at an output current of 60mA/mm, a large number of electrons gather under the channel layer of the PHEMT with a channel layer thickness of 12nm, and the current in the channel has a large z-direction component. In contrast, when the PHEMT is working, the electron distribution in the channel layer of the PHEMT with a channel layer thickness of 18nm is more uniform, thereby reducing the component of the current in the channel in the z direction and reducing the control of the gate on the channel current. Complexity, improve the linearity of PHEMT.
  • the embodiment of the present application also provides an LNA, as shown in FIG. 9 , including an input matching network, a bias circuit, a PHEMT and an output matching network, wherein the PHEMT may be the PHEMT shown in FIG. 4 or FIG. 5 above.
  • the bias circuit is used to provide the bias voltage required for normal operation of the PHEMT, that is, to set the gate, source and drain of the PHEMT at the required potential;
  • the input matching network is used to realize the signal source output impedance and the LNA input
  • the matching between the impedances enables the LNA to obtain the maximum excitation power;
  • the output matching network is used to transform the external load resistance into the optimal load resistance required by the amplifier to ensure the maximum output power.
  • the embodiment of the present application also provides a receiver or transceiver, and the receiver or transceiver may include the LNA as shown in FIG. 9 .
  • the receiver or transceiver may further include a duplexer, a band-pass filter, a digital-to-analog converter (ADC), and the like.
  • ADC digital-to-analog converter
  • the LNA can be applied to a radio frequency system. As shown in FIG. 10, the radio frequency system can be divided into a transmission chain and a reception chain.
  • the application scenario of this application is that the low noise amplifier LNA in the reception chain of the radio frequency system can be
  • the LNA shown in FIG. 9 is used to amplify the signal received by the antenna.
  • the transmission link may include a power amplifier (power amplifier, PA), a driver (driver), at least one filter (filter), at least one mixer (mixer), at least one local oscillator (local oscillator, LO) , at least one amplifier (amplifier, AMP) and the like.
  • the receiving chain may include a low noise amplifier LNA, at least one filter, at least one mixer, at least one local oscillator (local oscillator, LO), at least one amplifier, and the like.
  • at least one filter may include an image rejection filter (image rejection filter), an intermediate frequency filter (IF filter) or other filters.
  • FIG. 10 is only for illustration, and the radio frequency system may also have other circuit structures, and may also include fewer components than those in FIG. 10 , which is not limited here.
  • the present application also provides a radio frequency circuit, the circuit includes the PHEMT as shown in Figure 4 or Figure 5 or includes the LNA as shown in Figure 9, which is applied in the field of wireless communication, and is used to process signals received through the antenna And/or control the antenna to transmit signals.
  • the present application also provides a radio frequency chip, which is used to process the signal received by the receiving antenna and send it to the processor, and receive instructions from the processor to control the transmitting antenna to transmit the signal.
  • the present application also provides an electronic device, which can be a mobile phone, a tablet computer, an e-reader, a TV, a notebook computer, a digital camera, a vehicle-mounted device, a wearable device, a base station, a router, etc.
  • the electronic device may include at least one of the above-mentioned PHEMT, LNA, wireless radio frequency system, radio frequency circuit and radio frequency chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

本申请提供了一种赝配高迁移率晶体管PHEMT、低噪声放大器及相关装置，PHEMT包括：沟道层，分别设置于所述沟道层两侧的下势垒层和上势垒层，所述下势垒层与所述沟道层连接；以及，设置于所述沟道层和所述上势垒层之间的第一隔离层和第一掺杂层，所述第一隔离层用于隔离所述第一掺杂层和所述沟道层，所述第一掺杂层用于提供二维电子气，其中，在PHEMT的输出电流小于第一阈值时的所述沟道层的导带能级小于费米能级，以提高小输出电流时PHEMT的线性度，进而降低由于LNA非线性引起的交调失真。

Description

赝配高迁移率晶体管、低噪声放大器及相关装置
本申请要求于2021年12月14日提交中国专利局、申请号为202111529775.4、申请名称为“赝配高迁移率晶体管、低噪声放大器及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，尤其涉及一种赝配高迁移率晶体管、低噪声放大器及相关装置。
背景技术
如图1所示，在无线通信产品天线端的接收链路上，接收信号在经过低噪声放大器LNA时，会与泄露进接收链路中的发射信号产生互调信号，进而产生互调失真(intermodulation distortion，IMD)。这是由于LNA的非线性特质造成的。其中，由于其三阶交调产物的频率与接收信号的频率十分接近，无法被接收链路中后续的滤波器所抑制，进而在链路上对接收信号产生干扰。
发明内容
本申请实施例提供了一种赝配高迁移率晶体管PHEMT、低噪声放大器及相关装置，通过使在PHEMT的输出电流小于第一阈值时的所述沟道层的导带能级小于费米能级，进而提高小输出电流时PHEMT的线性度，进而降低由于LNA非线性引起的交调失真。
第一方面，本申请实施例提供了一种赝配高迁移率晶体管PHEMT，包括：
沟道层；
分别设置于所述沟道层两侧的下势垒层和上势垒层，所述下势垒层与所述沟道层连接；以及，
设置于所述沟道层和所述上势垒层之间的第一隔离层和第一掺杂层，所述第一隔离层用于隔离所述第一掺杂层和所述沟道层，所述第一掺杂层用于提供二维电子气；
其中，在所述PHEMT的输出电流小于第一阈值时的所述沟道层的导带能级小于费米能级。
上述PHEMT，通过该对沟道层的能级结构的调整时，使得在PHEMT的输出电流小于第一阈值时的所述沟道层的导带能级小于费米能级，进而提高小输出电流时PHEMT的线性度，进而降低由于LNA非线性引起的交调失真。
在一种可能的实现中，所述下势垒层与所述沟道层直接连接。
上述PHEMT，通过去掉下掺杂层，以使沟道层的能级沿着厚度方向的梯度更小，使得在小电流工作时沟道层的导带能级均小于费米能级。
在一种可能的实现中，所述第一掺杂层为硅掺杂，掺杂浓度为3e 12cm -2至5e 12cm -2。
在一种可能的实现中，第一掺杂层的掺杂浓度还可以是5e 12cm -2至6e 12cm -2。
上述PHEMT，通过增大第一掺杂层的浓度，提高PHEMT的增益。
在一种可能的实现中，所述下势垒层与所述沟道层通过第二隔离层和第二掺杂层连接， 所述第二隔离层用于隔离所述沟道层和所述第二掺杂层，所述第二掺杂层用于提供二维电子气。
上述PHEMT为双掺杂PHEMT，例如双δ掺杂PHEMT。
在一种可能的实现中，所述第一掺杂层的掺杂浓度为3.5e 12cm -2至4.5e 12cm -2，所述第二掺杂层的掺杂浓度为3e 11cm -2至5e 11cm -2。
在一种可能的实现中，所述第一掺杂层的掺杂浓度为4e 12cm -2至6e 12cm -2，所述第二掺杂层的掺杂浓度为2e 8cm -2至3e 11cm -2。
在一种可能的实现中，所述第一掺杂层的掺杂浓度与所述第二掺杂层的掺杂浓度之比大于预设值。
可选地，该预设值为大于6的正数，例如，为9、10、15、30、70、100、150等。
上述PHEMT，在总掺杂浓度不变或不降低的情况下，降低下掺杂层(第二掺杂层)的掺杂浓度或提高上掺杂层(第一掺杂层)与下掺杂层(第二掺杂层)的掺杂浓度的比值，以使沟道层的能级沿着厚度方向的梯度更小，使得在小电流工作时沟道层的导带能级均小于费米能级。
在一种可能的实现中，所述沟道层的厚度为15nm-20nm，或为18nm-20nm、或为20nm-25nm。例如，为18nm。
在一种可能的实现中，在所述PHEMT的输出电流小于第二阈值时的所述沟道层的导带能级沿厚度方向大致下降。
上述PHEMT，通过增大沟道层的厚度，避免器件在工作时沟道层下方电子的积累，使得电子分布更均匀，从而提高PHEMT的线性度。
在一种可能的实现中，PHEMT还包括：帽层、源极、漏极和栅极；其中，所述帽层设置于所述上势垒层背离所述沟道层的一侧并开设通孔，用于提供欧姆接触；所述栅极设置于所述通孔内；所述源极和所述漏极均设置于所述帽层背离所述上势垒层的一侧且分别位于所述通孔的两侧。
在一种可能的实现中，还包括：所述沟道层的材料为砷化铟镓；所述上势垒层或所述下势垒层或所述隔离层为砷化铝镓。
第二方面，本申请实施例还提供了一种低噪声放大器，包括：如第一方面或第一方面任意一种可能的实现所述的PHEMT。
第三方面，本申请实施例还提供了一种射频电路，包括：如第二方面所述的低噪声放大器。
第四方面，本申请实施例还提供了一种射频芯片，包括：如第一方面或第一方面任意一种可能的实现所述的PHEMT、如第二方面所述的低噪声放大器，如第三方面所述的射频电路中的至少一种。
第五方面，本申请实施例还提供了一种电子设备，其特征在于，包括：如第一方面或第一方面任意一种可能的实现所述的PHEMT、如第二方面所述的低噪声放大器，如第三方面所述的射频电路和如第四方面所述的射频芯片中的至少一种。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是本申请实施例提供的一种天线端接收链路上产生的互调信号的示意性说明图。
图2A是现有技术提供的一种双δ掺杂的PHEMT的结构示意图。
图2B是图2A所示的PHEMT的直流输出特性曲线的示例图。
图2C是图2A所示的PHEMT的能带结构示意图。
图2D是图2A所示的PHEMT的OIP3值在不同的输出电流下的曲线的示例图。
图3是现有技术定义OIP3值的示意图。
图4是本申请实施例提供的一种单δ掺杂PHEMT的截面的结构示意图。
图5是本申请实施例提供的一种双δ掺杂PHEMT的截面的结构示意图。
图6是现有技术提供的双δ掺杂的PHEMT与本申请实施提供的单δ掺杂的PHEMT的OIP3值分别在不同的输出电流下的曲线示例图。
图7A是现有技术提供的双δ掺杂的PHEMT的能带示例图。
图7B是本申请实施例提供的一种单δ掺杂的PHEMT的能带示例图。
图7C是本申请实施例提供的一种单δ掺杂的PHEMT和双δ掺杂的PHEMT在沟道层处的导带结构示例图。
图8是沟道层厚度分别为12nm和18nm的双δ掺杂的PHEMT在输出电流为60mA/mm时电子的浓度分布图。
图9是本申请实施例提供的一种LNA的电路结构示意图。
图10是本申请实施例提供的一种无线射频系统的示意图。
具体实施方式
通常有两种方法来降低互调信号对接收信号产生的干扰。
一种方法是：通过提高双工器的隔离度来降低泄露进接收链路中的发射信号。其中，双工器又称为天线共用器，其作用是将通过共用天线发射的发射信号和通过该共用天线接收的接收信号相隔离，以确保发射链路和接收链路都能够同时工作。若通过提高双工器的隔离度来降低互调信号对接收信号产生的干扰，则需要增加双工器的腔体，此时会增加双工器的体积，也会大幅提升成本。
另一种方法是：通过提高低噪声放大器(LNA)的线性度来降低泄露信号和接收信号产生的无法被滤波器完全抑制的互调信号。LNA的线性度是由晶体管的管芯决定的。晶体管可以采用赝配高迁移率晶体管(pseudomorphichigh electron mobility transistor，PHEMT)。
典型的砷化镓(GaAs)基PHEMT的结构，如图2A所示，其管芯外延层由上至下分别为缓冲层(buffer layer)、下势垒层、下δ掺杂层、下隔离层、沟道层(channel layer)、上隔离层、上δ掺杂层、上势垒层和帽层。其中，对于砷化镓(GaAs)基PHEMT，衬底上的缓冲层可以是砷化镓或砷化铝镓，用于减少衬底的缺陷进入PHEMT其他层；下势垒层和上势垒层可以是砷化铝镓(AlGaAs)，用于阻止二维电子气进入缓冲层；下δ掺杂层和上δ掺杂层均可以是硅(Si)掺杂，用于提供二维电子气；上隔离层和下隔离层可以是砷化铝镓(AlGaAs)，用于隔离掺杂层与沟道层；沟道层可以是砷化铟镓(InGaAs)；帽层可以是高掺杂的砷化镓，其连接源极和漏极。通过栅极电压控制沟道层中的电子浓度，可以控制源极和漏极间的输出电流，进而实现信号放大的功能。如图2B所示，为图2A所示的PHEMT的直流输出特性曲线。示例性地，图2B中标注了5个不同栅极电压，分别区分PHEMT的5个工作状态，分别为关闭状态①、即将开启的状态②、开启状态③、完全开启状态④和线性工作状态⑤。
如图2C所示，为图2A所示的PHEMT在5个不同工作状态下的能带结构示意图。应理解，在图2C中的各个能带结构图中仅示出各个层的导带结构，从左到右，即沿厚度方向，依次为帽层、上势垒层、上δ掺杂层、上隔离层、沟道层、下隔离层、下δ掺杂层和下势垒层的导带。图中仅标注了上δ掺杂层、下δ掺杂层和沟道层的位置。
如图2C所示，在PHEMT处于关闭状态①时，沟道层的导带能级远高于费米能级Ef；随着栅极电压增加，到PHEMT即将开启的状态②时，沟道层的导带能级即将接触到费米能级Ef；随着栅极电压进一步增加，在沟道层的导带能级部分低于费米能级Ef时，沟道层中出现一定数量的自由电子，此时，PHEMT处于开启状态③；当栅极电压进一步提高时，沟道层中的导带结构会从开启状态③时左高右低的形态依次变为完全开启状态④和线性工作状态⑤时的形态，即载流子会更倾向位于沟道层的上侧(即图2D中左侧，也即邻接上隔离层的一侧)。
而为满足射频系统接收链路中的低功耗与低噪声的要求，LNA器件的工作状态被限制在输出电流密度为60～100mA/mm附近，即图2C中PHEMT开启状态③的附近。
为满足LNA在射频电路中低功耗与低噪声系数的要求，工作点的输出电流被限制在60～100mA/mm附近，由于PHEMT高电子迁移率的特点，只需很小的二维电子气浓度即可达到工作状态电流，导致工作点大多处于PHEMT的开启电压附近，然而，该范围内PHEMT的线性度较低，不能满足应用的要求。以输出三阶截获点(output 3rd order intercept point，OIP3)来表征PHEMT的线性度，OIP3越高，线性度越好。由图2B所示的直流输出特性曲线计算可得到如图2A所示的PHEMT的OIP3值在不同的输出电流下的曲线，如图2D所示。由图2D可见，该PHEMT在输出电流为60mA时，OIP3值在36dBm左右，不能满足不小于41dBm的要求。故而，如何提高小输出电流时，即PHEMT刚开启时器件的线性度是当下亟待解决的技术问题。
如下对本申请实施例涉及的技术术语进行介绍。
(1)LNA
LNA是构成无线通信系统的重要电路，是一种噪声系数很低的放大器，其作用是将天线接收到的信号进行放大。来自天线的接收信号一般都很微弱。对这样微弱的信号进行放大，最重要的是保证信号质量，这就要求LNA不能引入太多的噪声，否则将使信号进一步恶化，导致无法进行解调。
LNA大多采用晶体管、场效应晶体管。本申请实施例中LNA采用赝配高迁移率晶体管(pseudomorphichigh electron mobility transistor，PHEMT)。
(2)互调信号
互调信号是非调制信号与有用信号经过非线性器件后，相互作用产生的互调频率信号。由于互调信号的频率与有用信号非常接近，因而难以被后端的滤波器抑制。如图1所示，在接收信号(即有用信号)和泄露进接收链路的中的发射信号(即干扰信号)同时经过LNA时，由于非线性的作用，这两个信号产生的互调信号的频率有时会恰好等于或接近接收信号的频率而顺利通过接收机，其中三阶互调最严重，由此形成的干扰，称为互调干扰。
(3)PHEMT
PHEMT是对高电子迁移率晶体管(high electron mobility transistor，HEMT)的一种改进。PHEMT具有双异质结的结构，其二维电子气2DEG有势阱两边的双重限制作用，从而相比HEMT具有更高的电子面密度；同时，其电子迁移率也较高。
如图2A所示为一种典型的双δ掺杂的PHEMT。
(4)OIP3
PHEMT的线性度可以由输出三阶截获点(output 3rd order intercept point，OIP3)来表征，OIP3值越高则线性度越好。OIP3的值可以通过绘图法从PHEMT射频输入输出曲线上获得。如图3所示，具体地，绘制两条曲线，一条是在输入频率下的放大信号功率对输入功率作图，另一条是三阶交调信号对输入功率作图。在对数坐标系中，线性放大信号曲线表现为斜率为1的直线，三阶交调信号曲线表现为斜率为3的直线，它们的交点对应的输出信号功率即为OIP3值。
(5)输出电流
本申请各个实施例中所指的输出电流也称为从漏极输出的电流。小输出电流，也简称为小电流，是指输出电流小于第一阈值或小于第二阈值，其中，第一阈值或第二阈值均可以是在PHEMT刚开启时的电流密度，或者PHEMT的输出电流密度为40mA/mm-200mA/mm，或者为60mA/mm-100mA/mm。第一阈值可以等于或不等于第二阈值。本申请实施例以小输出电流为60mA/mm为例来说明。本申请各个实施例中出现的电流也均指电流密度。
本申请实施例通过设计PHEMT中各个层结构的厚度、材料等，尤其是外延层的厚度、掺杂层的掺杂浓度等结构设计调节PHEMT的沟道层的能带结构，使得PHEMT在小输出电流工作时沟道层的导带能级均小于费米能级，从而使得随着栅极电压的增大，费米能级附近的电子浓度的增量对沟道层的电子浓度的影响更小，进而提高PHEMT的线性度。从导带结构上观察在开启状态③时沟道层的导带梯度更小。
如下说明沟道层的能带结构的调节机制。
影响沟道层的能带结构的主要因素包含以下几种：
a，沟道层与栅极之间的距离。该距离会影响沟道层的能级的高低。
b，上/下掺杂层的掺杂浓度。其中，掺杂层会改变其上层结构的能带的弯曲程度。例如，上掺杂层的掺杂浓度升高，会使得上势垒层的能带弯曲程度更大，即上势垒层的能级沿着厚度方向的梯度更大；又例如，下掺杂层的掺杂浓度升高，会使得沟道层的能带弯曲程度更大，沟道层的能级沿着厚度方向的梯度更大。因此，降低下掺杂层的浓度，可以使得沟道层的能带弯曲程度更小，即沟道层的能级沿着厚度方向的梯度更小，使得在小输出电流工作时沟道层的导带能级均小于费米能级。
c，上/下掺杂层的掺杂浓度的比值。为了达到PHEMT在小电流工作时沟道层的导带能级均小于费米能级这一要求，会降低下掺杂层的掺杂浓度，然而，上/下掺杂层的总掺杂浓度会影响载流子浓度，从而影响器件的性能。另一方面，掺杂浓度越高，器件的开启电压也会越高。因此，总掺杂浓度不能太低，也不能太高。
d，沟道层的厚度。沟道层的厚度会影响电子、电流的分布。较厚的沟道层可以避免器件在工作时沟道层下方电子的积累，使得电子分布更均匀，从而提高PHEMT的线性度。
因此，结合上述几个因素，本申请实施例提供了如下几种方案来调节沟道层的能带结构，使得其在小电流工作时沟道层的导带能级均小于费米能级。
方案一：去掉下掺杂层，以使沟道层的能级沿着厚度方向的梯度更小，使得在小电流工作时沟道层的导带能级均小于费米能级。
方案二：在总掺杂浓度不降低的情况下，降低下掺杂层的掺杂浓度或提高上掺杂层与下掺杂层的掺杂浓度的比值。
方案三：增加沟道层的厚度。
以及，上述方案一、二和三的组合，以及，调节上势垒层和/或上隔离层的厚度与上述方案一、二和三中的至少一种方案的组合等。
上述方案通过调节PHEMT中各个层结构的厚度、掺杂浓度，使得其在小电流工作时沟道层的导带能级均小于费米能级，就可以提高PHEMT的线性度，进而提高由PHEMT形成的LNA的线性度，降低LNA输出的互调信号，提高信号的质量。
下面将结合本申请实施例中的附图，对本申请实施例进行清楚、详细地描述。
如图4所示PHEMT的截面的结构示意图，采用上述方案一，或方案一与调节上势垒层和/或上隔离层的厚度、上述方案二和方案三中的至少一种的组合来调节沟道层的能带结构。
如图4所示，该PHEMT为单δ掺杂，包括衬底1，依次设置于该衬底1上的缓冲层2、下势垒层3、沟道层4、上隔离层5、第一掺杂层6、上势垒层7和帽层8，设置于帽层8上的源极9和漏极10，以及设置于上势垒层7上的栅极11。下面以GaAs基PHEMT为例，对各个层的功能、成分和厚度等分别进行说明：
衬底1可以是砷化镓(GaAs)晶圆。
缓冲层2可以砷化镓(GaAs)或砷化铝镓(Al xGa 1-xAs)，其中，0<x<1，缓冲层2可以阻挡衬底1的缺陷进入PHEMT的管芯。通常，缓冲层中的Al的掺杂浓度随着远离衬底1方向逐步增加，可以减少由于衬底1与下势垒层3之间的晶格不匹配导致的缺陷。
下势垒层3可以是砷化铝镓(Al xGa 1-xAs)，其禁带宽度大于沟道层4的禁带宽度，用于与沟道层4形成异质结，为反结。下势垒层3的厚度可以是10-50nm或10-25nm，示例性地，为17nm、20nm等。
示例性地，缓冲层2中Al的最高掺杂浓度不大于下势垒层3中Al的掺杂浓度。
沟道层4可以是砷化铟镓(In yGa 1-yAs)，其中，0<y<1，例如，y取值范围可以是0.1-0.5，示例性地，y为0.22、0.3。
在一些实施例中，沟道层4的厚度可以是大于8nm或12nm且小于沟道外延层的临界厚度。例如，针对由In 0.22Ga 0.78As构成的沟道层，其临界厚度为20nm作用，随着铟含量的降低，临界厚度增大。可选地，沟道层4的厚度可以是8nm-30nm、或12m-30nm或15nm-20nm，示例性地，为17nm、18nm、20nm、24nm等。通过增加沟道层4的厚度，可以改善沟道层4内电子、电流的分布，从而避免电子在沟道层4下方的堆积，降低纵向(即PHEMT的层叠方向)电流，从而提高PHEMT的线性度。
示例性地，沟道层4为In 0.22Ga 0.78As，厚度为18nm。
上隔离层5用于隔离沟道层4和第一掺杂层6，避免第一掺杂层6的掺杂杂质进入沟道层4，上隔离层5可以是砷化铝镓，其厚度可以是2nm-6nm，例如为4nm、6nm。上隔离层5也称为第一隔离层。
第一掺杂层6，可以是δ掺杂，也称为上δ掺杂层，可以为硅掺杂，通过在上隔离层5上生长一层很薄的硅作为掺杂杂质，用于在被电离后提供二维电子气。其厚度可以是几个原子，其厚度小于2nm，例如,为1nm或小于1nm。
示例性地，第一掺杂层6的掺杂浓度是现有技术中双δ摻杂PHEMT中两层掺杂层的掺杂浓度之和，或者掺杂浓度为3e 12cm -2至5e 12cm -2，或为5e 12cm -2至6e 12cm -2，1e 12cm -2至3e 12cm -2，4.6e 12cm -2至5.5e 12cm -2，5.5e 12cm -2至6.5e 12cm -2，示例性地，为4.5e 12cm -2。
上势垒层7，可以是砷化铝镓(Al xGa 1-xAs)，其禁带宽度大于沟道层4的禁带宽度，用于和第一掺杂层6、上隔离层5一起与沟道层4形成异质结，为正结。其厚度可以是10nm-30 nm或10-25nm，例如为15nm、17nm、20nm等。
帽层8可以是重掺杂的砷化镓(n+-GaAs)，其厚度可以是5nm-10nm，用于提供欧姆接触。
帽层8开设通孔，栅极11设置于该通孔内且与帽层8不接触，源极9和漏极10均设置于帽层8背离上势垒层7的一侧且分别位于通孔的两侧。
其中，源极9、漏极10、栅极11均为导电金属，栅极11用于为PHEMT提供栅极电压，当栅极电压大于开启电压时，源极9和漏极10之间导通，输出漏极电流。
在本申请实施例中，下势垒层3与沟道层4是直接连接的。这里“直接连接”是指，直接接触，也即下势垒层3与沟道层4之间不包含其他层结构。
需要说明的是，虽然，缓冲层2、下势垒层3、上隔离层5、上势垒层7均可以采用砷化铝镓(Al xGa 1-xAs)，但各个层中Al的掺杂浓度可以相同或不同，这里不作限定。例如，下势垒层3、上隔离层5、上势垒层7均采用Al 0.22Ga 0.78As。
本申请实施例提供的单δ摻杂PHEMT，由于上势垒层7、下势垒层3的禁带宽度均大于沟道层4，使得单δ摻杂PHEMT具有一个摻杂的正结(上势垒层7/第一掺杂层6/上隔离层5/沟道层4)和一个未掺杂的反结(沟道层4/下势垒层3)，在栅极电压大于开启电压时，摻杂的杂质电离，由于上势垒层7和沟道层4的禁带宽度不同所导致的导带的不连性，使得电子转移到沟道层一侧，从而形成二维电子气，源极9和漏极10导通，输出漏极电流。
本申请实施例基于上述沟道层的能带结构的调节机制，去除下掺杂层，选定合适的上掺杂层(即第一掺杂层6)浓度，选定合适的沟道层4、上势垒层7和上隔离层5的厚度等，所得到的单δ摻杂PHEMT在输出电流为小电流时沟道层4的导带能级小于费米能级，或者，沟道层4与上隔离层5的边界处的导带能级小于费米能级。可选地，在PHEMT在输出电流为小电流时沟道层4的导带能级沿厚度方向大致下降。其中，本申请实施例中厚度方向是指从帽层到衬底的方向，可以参见图4中所指示的方向；大致下降可以包括如下两种情况：
①沟道层4的导带能级沿厚度方向降低，即距离上势垒层越远，导带能级越低下降。
②沟道层4的导带能级沿厚度方向整体/宏观呈下降趋势，即允许小区域内/微观距离上势垒层较远但导带能级较高。
示例性地，上势垒层7的厚度为3～7nm，上隔离层5的厚度为4nm，第一掺杂层6的掺杂浓度为3.0～4.5e12cm-2，沟道层的厚度为12nm，
又示例性地，上势垒层7的厚度为5nm，上隔离层5的厚度为3～5nm，第一掺杂层6的掺杂浓度为3.0～4.5e12cm-2，沟道层的厚度为8～14nm。
不同于现有技术中的双δ掺杂PHEMT，本申请实施例提供了一种单δ摻杂PHEMT，在总掺杂浓度不变或不降低的情况下，仅仅对上势垒层7进行δ掺杂，通过去掉下掺杂层，降低沟道层4的导带能级沿厚度方向梯度，以在不影响增益(即gm跨导)的情况下，可以提高针对小输出电流时PHEMT的线性度。
进一步地，通过增加沟道层4厚度，可以改善沟道层4内电子、电流的分布，从而避免电子在沟道层4下方的堆积，降低纵向(即PHEMT的层叠方向)电流，可以进一步地提高PHEMT的线性度。
如图5所示，为本申请实施例提供的另一种PHEMT，该PHEMT可以是双掺杂的PHEMT，其除包括图4所示的各个层结构外，还可以包括第二掺杂层12和下隔离层13。
第一掺杂层6和第二掺杂层12可以均为δ掺杂，因而，第一掺杂层6也称为上δ掺杂层 6，第二掺杂层12也称为下δ掺杂层12，其均可以采用硅掺杂，分别通过在上隔离层5和下势垒层3上生长一层很薄的硅作为掺杂杂质，均用于在被电离后提供二维电子气。其厚度均可以是几个原子，小于2nm，例如,为1nm或小于1nm。第一掺杂层6的掺杂浓度大于第二掺杂层12。
下隔离层13用于隔离第二掺杂层12和沟道层4，防止第二掺杂层12的掺杂杂质进入到沟道层4。下隔离层13可以是砷化铝镓，其厚度可以是2nm-6nm，例如为4nm。下隔离层13也称为第二隔离层。
需要说明的是，虽然，缓冲层2、下势垒层3、上隔离层5、下隔离层13、上势垒层7均可以采用砷化铝镓，但各个层中Al的掺杂浓度可以相同或不同，这里不作限定。
本申请实施例提供的双δ摻杂PHEMT，由于上势垒层7、下势垒层3的禁带宽度均大于沟道层4，使得双δ摻杂PHEMT具有一个摻杂的正结(上势垒层7/第一掺杂层6/上隔离层5/沟道层4)和一个掺杂的反结(沟道层4/下隔离层13/第二掺杂层12/下势垒层3)，在栅极电压大于开启电压时，摻杂的杂质电离，由于势垒层和和沟道层4的禁带宽度不同所导致的导带的不连性，使得电子转移到沟道层一侧，从而形成二维电子气，源极9和漏极10导通，输出漏极电流。
在一些实施例中，通过采用上述方案三来调节沟道层的能带结构，如图5所示的PHEMT中，沟道层4的厚度大于12nm小于沟道外延层的临界厚度(也即不超出InGaAs外延沟道层的驰豫限度)，使得双δ摻杂PHEMT在输出电流为小电流时沟道层4的导带能级小于费米能级。例如，沟道层4的厚度为8nm-30nm、或12nm-30nm或15nm-20nm，示例性地，为17nm、18nm、20nm、24nm等。沟道层4的厚度或临界厚度与铟的含量有关，铟的含量越低，越厚。示例性地，沟道层4为In 0.22Ga 0.78As，厚度为18nm。
上述双δ摻杂PHEMT，通过增加沟道层4厚度，可以改善沟道层4内电子、电流的分布，从而避免电子在沟道层4下方的堆积，降低厚度方向上的电流，可以地提高PHEMT的线性度。
在又一些实施例中，采用上述方案二来调节沟道层的能带结构，使得双δ摻杂PHEMT在输出电流为小电流时沟道层4的导带能级小于费米能级。
示例性地，第一掺杂层6的掺杂浓度为3.5～4.5e 12cm -2，第二掺杂层12的掺杂浓度为3～5e 11cm -2。
示例性，第一掺杂层6与第二掺杂层12的掺杂浓度比大于预设值，该预设值不小于6，示例性地为9、10、15、30、70、100、150等。
又示例性地，第一掺杂层6的掺杂浓度为4e 12cm -2～6e 12cm -2，第二掺杂层12的掺杂浓度为2e 8cm -2至3e 11cm -2，或为1e 6cm -2至1e 11cm -2，或为1e 6cm -2至1e 8cm -2。
又示例性地，第一掺杂层6的掺杂浓度为3.5～4.5e 12cm -2，或4.5～6e 12cm -2，或4.6～5.5e 12cm -2第二掺杂层12的掺杂浓度为2e 8cm -2至3e 11cm -2。
上述双δ摻杂PHEMT，通过调节上/下δ掺杂层的掺杂浓度、掺杂浓度的比值，降低第二掺杂层12引起的沟道层4的能级梯度，使得器件在小电流工作时，沟道层4的导带能级小于费米能级，从而提高器件的线性度。
在又一些实施例中，采用上述方案二与方案三的结合来调节沟道层的能带结构，使得双δ摻杂PHEMT在输出电流为小电流时沟道层4的导带能级小于费米能级。示例性地，沟道层的厚度为18nm，第一掺杂层6的掺杂浓度为3.5～4.5e 12cm -2，第二掺杂层12的掺杂浓度为2e 8cm -2至3e 11cm -2。或者，设置第一掺杂层6与第二掺杂层12的掺杂浓度比大于预设值，该 预设值不小于6，示例性地为9。
上述双δ摻杂PHEMT，通过调节上/下掺杂层的掺杂浓度、掺杂浓度的比值，降低下掺杂层引起的沟道层4的能级梯度，使得器件在小电流工作时，沟道层4的导带能级小于费米能级，从而，提高器件的线性度。
在又一些实施例中，采用方案二和/或方案三，与调节上势垒层和/或上隔离层的厚度的组合，来调节沟道层的能带结构，使得双δ摻杂PHEMT在输出电流为小电流时沟道层4的导带能级小于费米能级。
示例性地，上势垒层7的厚度为3～7nm，上隔离层5的厚度为3～5nm，第一掺杂层6的掺杂浓度为3.0～4.5e 12cm -2，第二掺杂层12的掺杂浓度为3～5e 11cm -2，沟道层的厚度为18nm。
又示例性地，上势垒层7的厚度为3～7nm，上隔离层5的厚度为3～5nm，第一掺杂层6的掺杂浓度为3.0～4.5e 12cm -2，第二掺杂层的掺杂浓度为2e 8cm -2至3e 11cm -2，沟道层的厚度为14～20nm。
又示例性地，上势垒层7的厚度为5nm，上隔离层5的厚度为4nm，第一掺杂层6的掺杂浓度为3.0～4.5e 12cm -2，第二掺杂层的掺杂浓度为2e 8cm -2至3e 11cm -2，沟道层的厚度为14～20nm。
进一步地，上述各个实施例中，在PHEMT在小输出电流时沟道层4的导带能级沿厚度方向大致下降。
在另一些实施例中，上述图4或图5中的各个层结构还可以采用其他材料，具备其他厚度，例如，也可以是砷化镓的三元、四元或多元化合物。又例如，PHEMT为磷化镓(GaP)基PHEMT。
需要说明的是，上述图4和图5中描述的上掺杂层或上δ掺杂层均对应于第一掺杂层6，下掺杂层或下δ掺杂层均对应于第二掺杂层12。
还需要说明的是，为描述清楚，图4和图5中各个层的厚度不对应其真实厚度或厚度比例，具体厚度的范围以上述各个层规定的厚度为准。
与现有技术相比，本申请实施例提出的单δ掺杂PHEMT的OIP3值有显著的提升，在输出的漏极电流为60～100mA时，其OIP3值均有大于5dBm的提升。具体数据如图6所示。图6比对了现有技术中的双δ掺杂PHEMT的OIP3值的仿真结果和本申请实施例提供的单δ掺杂PHEMT的OIP3值的仿真结果，可见，相对于现有技术的双δ掺杂PHEMT，本申请实施例提供的单δ掺杂PHEMT的OIP3值在输出电流为在50mA～200mA之间时均有大于5dBm的提升。
下面结合图7A-图7C说明单δ掺杂提高PHEMT线性度的原理。
图7A为现有技术中双δ掺杂的PHEMT的能带图，图7B为本申请实施例提供的单δ掺杂的PHEMT的能带图，图7C比对了双δ掺杂的PHEMT和单δ掺杂的PHEMT在沟道层处的导带结构。应理解，随着栅极电压的增大，费米能级升高，其中，在图7A-图7C均标出了漏极电流(也即输出电流)为60mA时费米能级的位置。
由于空间电荷会在δ掺杂位置集中分布，造成δ掺杂处左侧的能带发生弯曲。当输出电流为60mA时，从能带结构上来看即表现为单δ掺杂的PHEMT在沟道处的导带结构更接近四方形，而双δ掺杂的PHEMT则更接近三角形，参见图7C中阴影区域。由于沟道层中的电子浓度与导带和费米能级围成的多边形面积成正比，因此在栅极电压的变化过程中，四方形 的导带结构比三角形的导带结构具有更高的线性度。
这是由于单δ掺杂的PHEMT沟道中的电子全部由上δ掺杂层提供，所以为了达到相同的输出电流，单δ掺杂设计的PHEMT沟道的导带会比双δ掺杂PHEMT沟道的导带更低于费米能级，而在费米能级附近的电子存在费米-狄拉克分布，即在费米能级附近(参见图7C中虚线框区域)，电子出现的概率为0.5，在小于费米能级时，电子出现的概率为1。这样，使费米能级附近电子的出现概率随着栅极电压的变化存在一定非线性，然而，单δ掺杂设计的PHEMT沟道的导带结构中费米能级附近的电子在整个导带结构中的占比更低，因此远离费米能级的单δ掺杂设计可以提供更高的线性度。
下面结合图8说明增加沟道层的厚度提高PHEMT线性度的原理。
图8示出了沟道层厚度分别为12nm和18nm的双δ掺杂的PHEMT在输出电流为60mA/mm时电子的浓度分布图。由图8可见，在PHEMT在输出电流为60mA/mm工作时，沟道层厚度分别为12nm的PHEMT的沟道层下方聚集了大量电子，沟道中电流存在较大的z方向分量。与之相比，在PHEMT工作时，沟道层厚度分别为18nm的PHEMT的沟道层中电子分布更加均匀，从而降低沟道中电流在z方向上的分量，降低栅极对沟道电流控制的复杂度，提高PHEMT的线性度。
下面介绍本申请实施例提供的PHEMT的应用场景。
本申请实施例还提供了一种LNA，如图9所示，包括输入匹配网络、偏置电路、PHEMT和输出匹配网络，其中PHEMT可以是上述图4或图5所示的PHEMT。其中，偏置电路用于为PHEMT提供正常工作所需要的偏置电压，即设置PHEMT的栅极、源极和漏极处于所要求的电位；输入匹配网络用于实现信号源输出阻抗与LNA输入阻抗之间的匹配，使LNA获得最大的激励功率；输出匹配网络用于将外接负载电阻变换为放大器所需的最佳负载电阻，以保证输出功率最大。
本申请实施例还提供了一种接收器或收发器，该接收器或收发器可以包括如图9所示的LNA。可选地，接收器或收发器还可以包括双工器、带通滤波器、数模转换器(ADC)等。
该LNA可以应用于无线射频系统，如图10所示，无线射频系统可以分为发射链路和接收链路，本申请的应用场景为无线射频系统的接收链路中的低噪声放大器LNA可以是如图9所示的LNA，用于实现将天线接收到的信号放大。
其中，发射链路可以包括功率放大器(power amplifier，PA)、驱动器(driver)、至少一个滤波器(filter)、至少一个混频器(mixer)、至少一个本机振荡器(local oscillato，LO)、至少一个放大器(amplifier，AMP)等。接收链路可以包括低噪声放大器LNA，至少一个滤波器、至少一个混频器、至少一个本机振荡器(local oscillato，LO)、至少一个放大器等。其中，至少一个滤波器可以包括镜频抑制滤波器(image rejection filter)、中频滤波器(IF filter)或其他滤波器等。
应理解，图10仅为示例性说明，无线射频系统还可以为是其他电路结构，还可以包括比图10更少的器件，这里不作限定。
本申请还提供了一种射频电路，该电路包括如图4或图5所示的PHEMT或包括如图9所示的LNA，应用于无线通信领域，用于对通过天线接收到的信号进行处理和/或控制天线发射信号。
本申请还提供了一种射频芯片，该射频芯片用于对接收天线接收到的信号进行处理并将 其发送给处理器，以及接收处理器的指令，控制发射天线发射信号。
本申请还提供了一种电子设备，该电子设备可以是手机、平板电脑、电子阅读器、电视、笔记本电脑、数码相机、车载设备、可穿戴设备、基站、路由器等包含射频功能或无线通信功能的设备，该电子设备可以包括上述PHEMT、LNA、无线射频系统、射频电路和射频芯片中的至少一种。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种赝配高迁移率晶体管PHEMT，其特征在于，包括：
    沟道层；
    分别设置于所述沟道层两侧的下势垒层和上势垒层，所述下势垒层与所述沟道层连接；以及，
    设置于所述沟道层和所述上势垒层之间的第一隔离层和第一掺杂层，所述第一隔离层用于隔离所述第一掺杂层和所述沟道层，所述第一掺杂层用于提供二维电子气；
    其中，在所述PHEMT的输出电流小于第一阈值时的所述沟道层的导带能级小于费米能级。
  2. 根据权利要求1所述的PHEMT，其特征在于，所述下势垒层与所述沟道层直接连接。
  3. 根据权利要求2所述的PHEMT，其特征在于，所述第一掺杂层为硅掺杂，掺杂浓度为3e 12cm -2至5e 12cm -2。
  4. 根据权利要求1所述的PHEMT，其特征在于，所述下势垒层与所述沟道层通过第二隔离层和第二掺杂层连接，所述第二隔离层用于隔离所述沟道层和所述第二掺杂层，所述第二掺杂层用于提供二维电子气。
  5. 根据权利要求4所述的PHEMT，其特征在于，所述第一掺杂层的掺杂浓度为3.5e 12cm -2至4.5e 12cm -2，所述第二掺杂层的掺杂浓度为3e 11cm -2至5e 11cm -2。
  6. 根据权利要求4所述的PHEMT，其特征在于，所述第一掺杂层的掺杂浓度与所述第二掺杂层的掺杂浓度之比大于预设值。
  7. 根据权利要求6所述的PHEMT，其特征在于，所述预设值大于9。
  8. 根据权利要求3-7任一项所述的PHEMT，其特征在于，所述第一掺杂层的浓度和所述第二掺杂层的浓度的取值使得所述PHEMT在开启状态时所述沟道层的导带能级低于费米能级。
  9. 根据权利要求1-8任一项所述的PHEMT，其特征在于，所述沟道层的厚度为15nm-20nm。
  10. 根据权利要求1-9任一项所述的PHEMT，其特征在于，在所述PHEMT的输出电流小于第二阈值时的所述沟道层的导带能级沿厚度方向大致下降。
  11. 根据权利要求1-10任意一项所述的PHEMT，其特征在于，还包括：帽层、源极、漏极和栅极；其中，所述帽层设置于所述上势垒层背离所述沟道层的一侧并开设通孔，用于提供欧姆接触；所述栅极设置于所述通孔内；所述源极和所述漏极均设置于所述帽层背离所述上势垒层的一侧且分别位于所述通孔的两侧。
  12. 根据权利要求1-11任意一项所述的PHEMT，其特征在于，还包括：所述沟道层的材料为砷化铟镓；所述上势垒层或所述下势垒层或所述隔离层为砷化铝镓。
  13. 一种低噪声放大器，其特征在于，包括：如权利要求1-12任意一项所述的PHEMT。
  14. 一种射频电路，其特征在于，包括：如权利要求13所述的低噪声放大器。
  15. 一种射频芯片，其特征在于，包括：如权利要求1-12任意一项所述的PHEMT、如权利要求13所述的低噪声放大器和如权利要求14所述的射频电路中的至少一种。
  16. 一种电子设备，其特征在于，包括：如权利要求1-12任意一项所述的PHEMT、如权利要求13所述的低噪声放大器、如权利要求14所述的射频电路和如权利要求15所述的射频芯片中的至少一种。
PCT/CN2022/136830 2021-12-14 2022-12-06 赝配高迁移率晶体管、低噪声放大器及相关装置 WO2023109570A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP22906320.1A EP4451341A1 (en) 2021-12-14 2022-12-06 Pseudomorphic high electron mobility transistor, low-noise amplifier and related device
KR1020247022324A KR20240117599A (ko) 2021-12-14 2022-12-06 부정형 고전자 이동도 트랜지스터, 저잡음 증폭기 및 관련 장치
CN202280076882.2A CN118369768A (zh) 2021-12-14 2022-12-06 赝配高迁移率晶体管、低噪声放大器及相关装置
US18/742,080 US20240332412A1 (en) 2021-12-14 2024-06-13 Pseudomorphic high electron mobility transistor, low noise amplifier, and related apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111529775.4A CN114373804A (zh) 2021-12-14 2021-12-14 赝配高迁移率晶体管、低噪声放大器及相关装置
CN202111529775.4 2021-12-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/742,080 Continuation US20240332412A1 (en) 2021-12-14 2024-06-13 Pseudomorphic high electron mobility transistor, low noise amplifier, and related apparatus

Publications (1)

Publication Number Publication Date
WO2023109570A1 true WO2023109570A1 (zh) 2023-06-22

Family

ID=81139533

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/136830 WO2023109570A1 (zh) 2021-12-14 2022-12-06 赝配高迁移率晶体管、低噪声放大器及相关装置

Country Status (5)

Country Link
US (1) US20240332412A1 (zh)
EP (1) EP4451341A1 (zh)
KR (1) KR20240117599A (zh)
CN (3) CN114373804A (zh)
WO (1) WO2023109570A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114373804A (zh) * 2021-12-14 2022-04-19 华为技术有限公司 赝配高迁移率晶体管、低噪声放大器及相关装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326345A (ja) * 2000-05-16 2001-11-22 Hitachi Cable Ltd 化合物半導体エピタキシャルウェハ及びｈｅｍｔ
CN102610640A (zh) * 2011-11-29 2012-07-25 中国科学院微电子研究所 一种高驱动电流的iii-v族金属氧化物半导体器件
US20150129889A1 (en) * 2013-11-13 2015-05-14 Sumitomo Electric Industries, Ltd. Semiconductor device and semiconductor substrate
CN107078062A (zh) * 2014-11-04 2017-08-18 索尼公司 半导体器件、天线开关电路和无线通信装置
US20190267480A1 (en) * 2018-02-26 2019-08-29 Duet Microelectronics Inc. Anti-barrier-conduction (abc) spacers for high electron-mobility transistors (hemts)
US20190267481A1 (en) * 2018-02-26 2019-08-29 Duet Microelectronics LLC Field-Effect Transistors (FETs)
CN114373804A (zh) * 2021-12-14 2022-04-19 华为技术有限公司 赝配高迁移率晶体管、低噪声放大器及相关装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312237A3 (en) * 1987-10-13 1989-10-25 AT&T Corp. Interface charge enhancement in delta-doped heterostructure
JP2914049B2 (ja) * 1992-10-27 1999-06-28 株式会社デンソー ヘテロ接合を有する化合物半導体基板およびそれを用いた電界効果トランジスタ
US6849866B2 (en) * 1996-10-16 2005-02-01 The University Of Connecticut High performance optoelectronic and electronic inversion channel quantum well devices suitable for monolithic integration
JP4766743B2 (ja) * 2000-12-20 2011-09-07 新日本無線株式会社 ヘテロ接合電界効果トランジスタ
CN100342547C (zh) * 2004-06-08 2007-10-10 中国科学院半导体研究所 高击穿电压的高电子迁移率晶体管
US8120066B2 (en) * 2006-10-04 2012-02-21 Selex Sistemi Integrati S.P.A. Single voltage supply pseudomorphic high electron mobility transistor (PHEMT) power device and process for manufacturing the same
CN101221983A (zh) * 2007-01-10 2008-07-16 中国科学院微电子研究所 实空间转移高电子迁移率场效应晶体管材料
CN101814434B (zh) * 2010-03-04 2011-08-17 中国电子科技集团公司第五十五研究所 一种制造氮面极性AlN/AlInN复合背势垒氮化镓场效应管的方法
JP6056435B2 (ja) * 2012-12-07 2017-01-11 ソニー株式会社 半導体装置
WO2015192888A1 (en) * 2014-06-17 2015-12-23 Brolis Semiconductors Ltd High-mobility semiconductor heterostructures

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326345A (ja) * 2000-05-16 2001-11-22 Hitachi Cable Ltd 化合物半導体エピタキシャルウェハ及びｈｅｍｔ
CN102610640A (zh) * 2011-11-29 2012-07-25 中国科学院微电子研究所 一种高驱动电流的iii-v族金属氧化物半导体器件
US20150129889A1 (en) * 2013-11-13 2015-05-14 Sumitomo Electric Industries, Ltd. Semiconductor device and semiconductor substrate
CN107078062A (zh) * 2014-11-04 2017-08-18 索尼公司 半导体器件、天线开关电路和无线通信装置
US20190267480A1 (en) * 2018-02-26 2019-08-29 Duet Microelectronics Inc. Anti-barrier-conduction (abc) spacers for high electron-mobility transistors (hemts)
US20190267481A1 (en) * 2018-02-26 2019-08-29 Duet Microelectronics LLC Field-Effect Transistors (FETs)
CN114373804A (zh) * 2021-12-14 2022-04-19 华为技术有限公司 赝配高迁移率晶体管、低噪声放大器及相关装置

Also Published As

Publication number Publication date
CN114373804A (zh) 2022-04-19
KR20240117599A (ko) 2024-08-01
CN219144184U (zh) 2023-06-06
EP4451341A1 (en) 2024-10-23
US20240332412A1 (en) 2024-10-03
CN118369768A (zh) 2024-07-19

Similar Documents

Publication Publication Date Title
Tan et al. 94-GHz 0.1-mu m T-gate low-noise pseudomorphic InGaAs HEMTs
US8169002B2 (en) High electron mobility transistor and method for fabricating the same
US20240332412A1 (en) Pseudomorphic high electron mobility transistor, low noise amplifier, and related apparatus
Wang et al. Improvement of power performance of GaN HEMT by using quaternary InAlGaN barrier
JPH1056168A (ja) 電界効果トランジスタ
CN111868931A (zh) 高度缩放的线性GaN HEMT结构
Thome et al. InGaAs MOSHEMT W-band LNAs on silicon and gallium arsenide substrates
Xu et al. Design and fabrication of double modulation doped InAlAs/lnGaAs/InAs heterojunction FETs for high-speed and millimeter-wave applications
Lu et al. A review of GaN RF devices and power amplifiers for 5G communication applications
WO2019208034A1 (ja) スイッチングトランジスタ及び半導体モジュール
Takahashi et al. Improvement of RF and noise characteristics using a cavity structure in InAlAs/InGaAs HEMTs
Hsu et al. Study of low noise with high linearity AlGaN/GaN HEMTs by optimizing Γ-Gate structure for Ka-Band applications
Cha InP high electron mobility transistors for cryogenic low-noise and low-power amplifiers
US8193566B2 (en) Semiconductor device
Suzuki et al. Wide-band transimpedance amplifiers using AlGaAs/In/sub x/Ga/sub 1-x/As pseudomorphic 2-DEG FET's
Borg et al. Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain
Harrouche et al. GaN‐based HEMTs for millimeter‐wave applications
JP2002313815A (ja) 電界効果トランジスタ及び高周波モジュール
WO2008007335A2 (en) High electron mobility transistor.
US10170610B1 (en) Pseudomorphic high electron mobility transistor with low contact resistance
Dubey et al. Analysis of AlGaN/GaN Based HEMT for Millimeter-Wave Applications
US5751030A (en) Field effect transistor
US20240313069A1 (en) Semiconductor component and electronic device
Lu et al. High Power Linearity and Low Leakage Current of AlN/GaN/InGaN Coupling Channel HEMTs with N 2 O Oxidation Treatment
Dubey et al. Analysis of High Frequency AlGaN/GaN-Based HEMT for Resistive Load Inverter

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22906320

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2024535470

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20247022324

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2022906320

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2022906320

Country of ref document: EP

Effective date: 20240715