WO2015192888A1

WO2015192888A1 - High-mobility semiconductor heterostructures

Info

Publication number: WO2015192888A1
Application number: PCT/EP2014/062672
Authority: WO
Inventors: Augustinas VIZBARAS; Kristijonas Vizbaras
Original assignee: Brolis Semiconductors Ltd
Priority date: 2014-06-17
Filing date: 2014-06-17
Publication date: 2015-12-23

Abstract

A design concept and method of fabrication of a semiconductor heterostructure containing a two-dimensional electron gas (2DEG), two-dimensional hole gas (2DHG), or a two-dimensional electron/ hole gas (2DEHG). The heterostructure contains a quantum well layer (20) with 2DEG, 2DHG, or 2DEHG embedded between two doped charge reservoir layers and at least one remote charge reservoir layer. Such scheme allows reducing the number of scattering ions in the proximity of the quantum well as well a possibility for a symmetric potential for the electron or hole wavefunction in the quantum well, leading to a significant improvement in carrier mobility in a broad range of 2DEG or 2DHG concentration in the quantum well. Embodiments of the invention may be applied to the fabrication of galvano-magnetic sensors, HEMT, pHEMT, and MESFET devices.

Description

High-mobility semiconductor heterostructures Field of the invention

Embodiments of the invention relate generally to semiconductor structures, and particularly to high mobility semiconductor heterostructures. Background of the invention

Two-dimensional electron gas systems such as quantum wells, exhibit quantized electronic states in one dimension and have a step-like density of states. The charge carriers are thus localized in one dimension (i.e., growth direction) and can freely move in the in-plane directions. See U.S. Patent No. 5,442,221.

Localized charge carriers exhibit high in-plane mobility in the wide charge carrier concentration range, which can be precisely controlled by means of conventional epitaxial crystal growth. Carrier mobility is limited by carrier scattering mechanisms which are typically domi nated by optical phonon scattering, ionized impurity scattering and alloy scattering where alloys containing more than 2 atoms are used - i.e. ternary (3 atoms), quaternary (4 atoms) and quinternary (5 atoms) alloys. See M. Hayne et al.

"Remote impurity scattering in modulation-doped GaAs/Al_xGai-_xAs heterojunctions", Phys. Rev. B., Vol. 57, No. 23, 1998; and A. K. Saxena, A. R. Adams, "Determination of alloy scattering potential in Gai-_xAl_xAs alloys," 7. Appl. Phys., Vol. 58, 2640, 1985.

Increasing carrier mobilities is a key challenge in semiconductor device fabrication processes. See, e.g., K. -J. Friedland, R. Hey, H. Kostial, R. Klann, and K. Ploog, "New Concept for the reduction of impurity scattering in remotely doped GaAs quantum wells," Phys. Rev. Lett., Vol. 77, No. 22, 1996, and U.S. Patent Nos. 4,912,451; 5,657,189; 7,388,235; and 6,316,124.

Summary

In an aspect, embodiments of the invention include a semiconductor heterostructure having a layer structure. The layer structure has a first charge reservoir layer, a second charge reservoir layer and a third charge reservoir layer disposed over a substrate, each charge reservoir layer including a dopant type of, e.g., donors and acceptors. An undoped quantum well layer is disposed between two of the charge reservoir layers. One or more of the following features may be included. The two charge reservoir layers between which the quantum well layer is disposed include a first type of dopant, an interface between a top surface of the layer structure and air include a second type of surface states, and the first and second types are different. A sheet doping density of the charge reservoir layer remote from the quantum well layer is substantially equal to a surface state sheet density of the layer structure.

The charge reservoir layer remote from the quantum well layer may include a first type of dopant, an interface between the substrate and the layer structure may include a second type of interface states, and the first type may be different from the second type. A sheet carrier density of the charge reserve layer disposed closest to the substrate is substantially equal to an interface state sheet density of the interface.

The substrate may be lattice-matched to the layer structure, e.g., the layer structure may include (AIGaln)(As)-containing layers disposed on a GaAs substrate or (AIGaIn) (AsP) -containing layers disposed on an InP substrate.

The substrate may not be lattice-matched to the layer structure. The layer structure may include (AIGaln)(AsSb)-containing layers disposed on a GaAs substrate.

The two charge reservoir layers proximate the quantum well layer may include dopants of the same type at substantially equal concentrations.

The charge reservoir layer remote from the quantum well layer may have a doping type and concentration that enables the incorporation of a reduced dopant concentration in the two charge reservoir layers proximate the quantum well layer in comparison to a heterostructure without the remote charge reservoir layer, while maintaining constant a carrier concentration in the quantum well layer.

A plurality of layers may be disposed between one of the charge reservoir layers proximate the quantum layer and the charge reservoir layer remote from the quantum well layer. A spacer layer including, e.g., aluminum, may be disposed between one of the charge reservoir layers proximate the quantum well layer and the charge reservoir layer remote from the quantum well layer. An upper barrier layer and/or a cap layer may be disposed over the third charge reservoir layer. The upper barrier layer may include aluminum. The cap layer may be substantially free of aluminum. The quantum well layer may include at least a ternary composition, with the layer structure further including a first binary material layer disposed between the quantum well layer and one of the two proximate charge reservoir layers. A second binary material layer may be disposed between the quantum well layer and the second of the two proximate charge layers. An electronic device may include the semiconductor heterostructure. The electronic device may include a magnetic sensor, e.g., a galvano-magnetic sensor. The electronic device may be a transistor, such as a high-electron-mobility transistor, a pseudomorphic high-electron-mobility transistor, or a metal-oxide- semiconductor field effect transistor.

In another aspect, embodiments of the invention include a method for manufacturing a semiconductor heterostructure, the method including forming sequentially a first, a second, and a third charge reservoir layer over a substrate, each charge reservoir layer comprising a dopant type , e.g., donors or acceptors. An undoped quantum well layer is formed between two of the charge reservoir layers.

One or more of the following features may be included. Forming at least one of the charge reservoir layers may include forming a delta-doped layer, e.g., by molecular beam epitaxy or metalorganic chemical vapor deposition.

Forming at least one of the charge reservoir layers may include growing an undoped layer and subsequently doping the undoped layer. The undoped layer may be formed by molecular beam epitaxy or metalorganic chemical vapor deposition, and the undoped layer may be formed by ion implantation and/or diffusion. Forming at least one of the charge reservoir layers may include forming a doped layer by molecular beam epitaxy or metalorganic chemical vapor deposition.

The quantum well layer may be formed between the first and second charge reservoir layers.

Alternatively, the quantum well layer may be formed between the second and third charge reservoir layers. A spacer layer may be formed between one of the charge reservoir layers proximate the quantum well layer and the charge reservoir layer remote from the quantum well layer.

An upper barrier layer and/or a cap layer may be formed over the third charge reservoir layer. Brief Description of Drawings

Figures la, lb, 2, 5 and 6 are schematic diagrams illustrating exemplary heterostructures in accordance with embodiments of the invention;

Figure 1 shows a simplified high-mobility semiconductor heterostructure with three charge layers cross section for two different cases: (a) when the remote charge layer is used to compensate surface depletion and (b) to compensate for carrier enrichment from the substrate-heterostructure interface.

Figure 2 shows a schematic cross section of an example AIGaAs/GalnAs/GaAs lattice-matched high- mobility heterostructure.

Figure 5 shows a schematic cross-section of a high-mobility heterostructure metamorphically grown on a non native substrate. The metamorphic interface is indicated by 101b.

Figure 6 shows an example of metamorphic high-mobility semiconductor heterostructure.

Figures 3a and 3b are graphs illustrating band structures for a structure with two charge layers in accordance with the prior art and the structure of Figure 2 with three charge layers, respectively;

Figure 3 shows a band structure for the high-mobility semiconductor heterostructure: (a) prior art with two charge layers and (b) structure with 3 charge layers. Full layer structure for calculation is shown in Fig. 3.

Figure 4 is a graph illustrating electron mobilities attained in accordance with an embodiment of the invention and with a prior art structure;

Figure 4 shows experimental room-temperature electron mobility data for a prior art structure with two charge layers and a structure with three charge layers.

Figures 7a and 7b are graphs of experimental data obtained for a metamorphic high-mobility structure.

Figure 7 shows experimental data for metamorphic high-mobility structure, (a) Carrier mobility vs. carrier concentration in the remote charge layer and (b) carrier concentration in the quantum well vs. carrier concentration in the remote charge layer. Figures 8a and 8b are schematic diagrams illustrating a Hall effect sensor incorporating a high-mobility semiconductor heterostructure in accordance with an embodiment of the invention. Figure 8 shows a Schematic example of hall effect sensor based on high-mobility semiconductor heterostructure. (a) top view; (b) cross section.

Detailed Description

Embodiments of the invention include a structure concept that reduces the effect of ionized impurity scattering and, in certain cases, alloy scattering mechanisms. The described concept and method of manufacturing enable the achievement of high charge carrier mobility in a wide carrier concentration range in a reproducible and controlled way in both lattice-matched material systems as well as strongly mismatched systems, i.e., metamorphic systems in which thick buffer layers act as virtual substrates.

High-mobility semiconductor heterostructures typically include at least one low-bandgap layer embedded between two higher bandgap materials, forming a quantum well with a two-dimensional electron gas (2DEG), a two-dimensional hole gas (2DHG), or a type I quantum well with two-dimensional electron/hole carrier gas. For maximum performance in terms of mobility, the charge carriers are supplied by introducing impurities into one or both of the surrounding high-bandgap layers to reduce the 2DEG scattering by ionized impurity atoms. For optimal performance, the 2DEG resides in the ground state of the quantum well. The wavefunction is preferably kept symmetric to reduce the overlap with the surrounding materials and remote ionized impurities. However, due to interface effects, such as surface depletion or carrier enrichment due to a relaxed substrate-layer stack interface, this may be difficult to fulfill.

Embodiments of the invention include a third charge layer, which is remote from the quantum well and is doped to compensate the interface effect. In the case of surface depletion, this layer is preferably positioned remote from the quantum well and closer to the top surface of the semiconductor-air interface.

In particular, referring to Figs, la and lb, a semiconductor heterostructure 5 may include a layer structure 7 disposed over a substrate 10. Referring to Fig. la, in an embodiment, a first charge reservoir layer 15 is disposed over the substrate 10. An undoped quantum well layer 20 is disposed over the first charge reservoir layer 15 and below second charge reservoir layer 25.

A third charge reservoir layer 30 is disposed over the second charge reservoir layer 25. In this embodiment, the remote charge layer is the third charge reservoir layer 30, i.e., the charge reservoir layer farthest from the substrate. The presence of the remote charge reservoir layer 30, which is doped with impurity atoms (typically donors) to a certain concentration (e.g., to at least 10¹¹ cm^"2), allows reducing the donor ion concentration in the two charge reservoir layers, surrounding the quantum well, e.g., the first and second charge reservoir layers 15, 25, while maintaining the 2DEG sheet carrier concentration in the quantum well constant. Referring to Fig. lb, in an alternative embodiment, the quantum well layer 20 may be disposed between the second and third charge reservoir layers 25, 30. In this embodiment, the remote charge layer is the first charge reservoir layer 15, i.e., the charge reservoir layer closest to the substrate.

A specific exemplary structure with three charge layers is shown in Fig. 2, and a comparison of carrier mobilities attained with an experimental structure to mobilities attained with a prior art structure is shown in Fig. 4.

The lattice-matched high-mobility semiconductor heterostructure can be, for example, realized in a lll-V material system, such as (AIGaln)i(As)i on a GaAs substrate (Fig. 2) or (AIGaln)i(AsP)i on an InP substrate. Here the in-plane lattice constants of the substrate and of the epitaxial layers are the same and no relaxation occurs. In an embodiment in which the epitaxial structure is grown on a GaAs substrate, the Al concentration in the barrier AIGaAs material may be below 40 %. For an embodiment with an InP substrate, the Al concentration in the barrier material may not exceed 60%.

A high-mobility semiconductor heterostructure such as the structure depicted in Fig. 2 may be manufactured by conventional epitaxial growth techniques such as molecular beam epitaxy (MBE) or metal-organic vapor phase epitaxy (MOVPE). The growth is carried out on a semi-insulating substrate 10, including a suitable material, such as ll-VI or lll-V compounds or group IV elements. In the illustrated example, substrate 10 may be composed of GaAs. A superlattice 12 including a periodic repetition of thin high bandgap and low band gap material pairs is formed over the substrate 10. The superlattice is preferably sufficiently thick to suppress the propagation of threading dislocations from the

imperfections in the semi-insulating substrate 10. A suitable choice of materials for the superlattice may be AIAs as a high bandgap material and GaAs as a low bandgap material, as shown in Fig. 2.

Typically, a superlattice thickness in the range of at least 10-50 nm is sufficient to suppress the threading dislocation propagation.

The superlattice layer 12 is followed by a bulk buffer layer 13, typically composed of a high quality epitaxial material with a bandgap energy higher than that of the quantum well layer 20. In the exemplary structure illustrated in Figure 2, the buffer layer 13 is formed of GaAs. The thickness of the bulk buffer layer 13 is chosen to be sufficiently thick to allow a dislocation-free surface and as thin as possible (to reduce growth time) while allowing a dislocation-free surface, e.g., between 50 nm - 1000 nm. The lower buffer layer 13 is followed by growth of high-bandgap material lower barrier layer 14, typically Al-containing alloy (AIGaln)i(AsSb)i, where the Al concentration in the alloy is non-zero and is chosen to facilitate proper electron confinement in the narrow bandgap quantum well. In Fig. 2 this layer is AIGaAs, lattice matched to the GaAs substrate 10. In an embodiment, a thickness of this layer is at least 1 nm, e.g., about 10 nm.

After the desired thickness of lower barrier layer 14 is attained, growth is interrupted and the wafer surface is exposed only to the dopant atoms, forming a 2D layer of impurity atoms of the desired type, typically n-type, to form the first charge reservoir layer 15. In some embodiments, a thickness of this 2D delta-doping layer is less than 1 monolayer. For example, the first charge reservoir layer 15 may be delta-doped with silicon atoms, acting as a donor type impurity Since electrons have a greater mobility than holes, n-type material is typically preferable for high-mobility structures, with donor-type impurities. Alternatively, the first charge reservoir layer 15 may be formed by depositing a suitable compound layer, e.g., a lll-V layer such as GaAs, and then implanting impurity atoms, e.g., n-type dopants such as silicon. In embodiments in which the first charge reservoir layer is formed of a bulk layer, a thickness of this layer is preferably greater than 1 monolayer, e.g., several nanometers.

Formation of first charge reservoir layer 15 may be followed by growth of a high bandgap spacer layer 16, which typically has the same composition as the lower barrier layer 14. The purpose of spacer layer 16 is to physically separate the first charge reservoir layer 15, where the ionized donor atoms are present, from the quantum well layer 20. A quantum well thickness may be selected from a range of at least a few monolayers (at least 1 nm), up to 30 nm. A thickness of the spacer layer may be at least 1 nm, e.g., 5 nm.

In the exemplary structure depicted in Fig. 3, the undoped quantum well layer 20 may be composed of a ternary material such as (Galn)iAsi. In case of use of ternary quantum well material, in which both gallium and indium concentrations are non-zero, alloy scattering may be present and limit the maximum carrier mobility, and is enhanced at the interface between the high-bandgap Al-containing layer 16, where a quaternary AIGalnAs interface is present.

To avoid excess scattering at the interfaces, first and second binary material insert layers 19a, 19b, for example GaAs, can be embedded between spacer layer 16 and quantum well layer 20 and between quantum well layer 20 and spacer layer 21, respectively. The thicknesses of the lattice matched first and second binary insert 19a, 19b and the spacer layer 16 together are preferably sufficient to confine the exponential tail of the electronic wavefunction in the ground state of the quantum well. A combined thickness of these layers of a few to ten monolayers may be sufficient After the quantum well layer 20 is grown, a second binary material insert layer 19b is formed, followed by the growth of a high bandgap spacer layer 21. The spacer layer 21 may be formed from a group Ill- containing material, such as an Al-containing material. For improved performance the thickness of the first binary material insert layer 19a is preferably the same as that of binary insert layer 19b, and the spacer layer 16 thickness is preferably the same as that of spacer layer 21. A symmetric potential is desired due to the symmetric nature of the electronic wavefunction in the ground state of the quantum well. Accordingly, the growth of the second spacer layer 21 is followed by the addition of a second delta-doped charge reservoir layer 25, which, ideally has the same impurity (i.e., dopant) type and concentration as the first charge reservoir layer 15 to induce a symmetric potential. Both of these charge layers serve as charge supply layer for the quantum well. In some embodiments, doping concentrations of the two charge supply layers may be selected from a range of 10^u cm-² - 10¹³ cm-².

To counteract the surface depletion effect and to avoid the addition of excess donor atoms, additional functional layers may be added to the conventional high-mobility heterostructure, i.e., structures with only two charge reservoir layers. In particular, after the second charge reservoir layer 25 is formed, the high-bandgap material layer 26, e.g., an Al-containing material such as AIGaAs, is continued to be grown, followed by a third charge reservoir layer 30, which is a Si-delta doped charge layer, with sheet donor concentration subsequently equal to the surface state sheet density . The intermediate spacer layer 26 may be sufficiently thick to decouple the charger reservoir 2 layer 25 and charge reservoir 3 layer 30. Typically, a thickness in the range of 10-1000 nm is sufficient. The third charge reservoir layer may be capped with a high-bandgap Al-containing upper barrier layer 35, followed by an Al-free capping layer 36, typically binary GaAs or ternary InGaAs, to avoid surface oxidation. The upper barrier layer 35 typically has a thickness of 10-50 nm, and a thickness of the capping layer 36 can range from few nm to 10 nm which are sufficient. The structure with three charge reservoir layers described herein allows decoupling the inclusion of a desired carrier density in the quantum well layer and the compensation of the surface states to avoid the surface depletion. In real structures, surface depletion, which is a result of Fermi level pinning at the surface layer of the structure, may lead to a carrier depletion in the quantum well layer. In the (AIGaln)i(As)i case as illustrated in Fig.2, the surface states are acceptor type. Thus an increase in the donor concentration in the second charge reservoir layer 25 is necessary to compensate for carrier depletion in the quantum well layer. However, the addition of donor atoms may lead to an increase in ionized impurity ion concentration, which in turn increases the carrier scattering rate by ionized impurities and limits the maximum mobility. Moreover, the potential becomes asymmetric and induces the asymmetry in the wavefunction of the ground state, leading to a larger penetration of the wavefunction into the spacer layer 16 (Fig. 3a) where excess scattering by ionized impurity atoms in layer 25 occurs and limits the maximum carrier mobility. To counteract the asymmetry of the potential and the excess donor ions, embodiments of the invention include a third charge reservoir layer, positioned remote from the quantum well layer.

The impurity sheet carrier concentration of the remote charge layer is preferably kept substantially equal to the sheet density of the surface states at the top layer - air interface. The presence of the remote charge reservoir layer allows the realization of a symmetric charge supply from the two charge layers surrounding the quantum well layer and a more symmetric potential of the 2DEG ground state (Fig. 3b), compared to a typical prior art case in which only two charge layers are used (Fig. 3a). In the prior art case, in order to compensate for the surface depletion, the second charge layer 25 which is grown above the quantum well layer is typically doped much more (2-4 times more than the first charge reservoir layer 15). This leads to asymmetric potential of the quantum and larger overlap of the 2DEG wavefunction with the barrier material and the ionized impurity atoms in the surrounding charge layers (Fig. 3b). This results in increased 2DEG scattering rate and lower mobility.

In summary, ideally, in a semiconductor heterostructure containing a quantum well, the lowest energy state for the charge carriers is the ground state of the quantum well. Thus, if one were to aim for a structure with a desired carrier concentration N in the quantum well, it would be reasonable to dope the two surrounding charge layers with dopant ion concentration of N/2 each for a symmetric charge supply and potential around the quantum well.

However, in real cases, interface effects play a role. Accordingly, in the case of surface depletion, the Fermi level becomes pinned close to midgap due to surface states, leading to charge extraction from the two charge supply layers surrounding the quantum well, and in turn, to an asymmetric potential for the ground state in the quantum well. This results in a carrier concentration in the quantum well being less than the desired N. In prior art cases, to overcome surface depletion, one of the two charge supply layers was doped substantially higher to compensate for the carrier extraction, while maintaining a constant carrier concentration in the quantum well (desired N). However, this may lead to excess impurity ions, this excess scattering and lower mobility. If, in accordance to embodiments of the invention, a remote charge layer is present (i.e., formed during the crystal growth process), it immediately compensates for the Fermi level pinning, maintaining a symmetric potential for the quantum well and allowing doping of the two charge supply layers to N/2 each. In a similar manner, embodiments of the invention are at equilibrium once layer growth is complete with respect to other interface effects - i.e., antisite defects, metamorphic interface, etc. Examples

Example 1: if the surface state sheet density is 10¹² cm^"2, then to achieve the carrier concentration of 10¹² cm^"2 in the quantum well, the first charge reservoir layer 15 is preferably doped 5xlO^u cm^"2 and the charge reservoir 2 layer 25 is preferably intentionally doped at least 1.5 x 10¹² cm^"2, which is a factor of 3 higher than the required nominal doping, meaning that also the number of ionized impurity scattering centers is a factor of 3 higher.

Example 2: If this concept is applied to the example discussed for the dual charge reservoir structure, then to achieve the 2D carrier density in the quantum well of 10¹² cm^"2, it is sufficient to dope the first charge reservoir layer 15 and the second charge reservoir layer 20 with donor concentration of 0.5 x 10¹² cm^"2 each, and dope the third charge reservoir layer 30 with donor concentration of 10¹² cm^"2 to fully compensate the surface states. This allows the achievement of a fully symmetric potential as well as the reduction in scattering centers due to ionized impurity ions by a factor of 3. In turn, once the surface states are fully compensated by the inclusion of third charge reservoir layer 30, the carrier concentration in the quantum well layer can be precisely controlled by adjusting the doping level in the first and second charge reservoir layers 15, 25. Experimental room-temperature mobility data for prior art structure with two charge layers and for the new structure with an additional remote charge layer is shown in Fig. 4

It is clearly demonstrated that once the symmetry of the potential is maintained, and the number of ionized donor atoms is kept low, the carrier mobility is kept constant regardless of carrier concentration in the quantum well for a wide concentration range. In cases where a quantum well material has a lattice constant different from the lattice constant of the substrate material and lattice-matched growth is not possible, strongly mismatched - metamorphic growth can be used. Such growth conditions lead to a completely relaxed interface between the substrate and the layer structure. An example of a metamorphic structure is a layer structure with an InAs or InSb quantum well grown on a GaAs substrate. Metamorphic structures may provide the advantage of using very high-mobility materials such as for example InAs or InSb on commercially available, low-cost substrates such as GaAs.

Fig. 5 illustrates an exemplary embodiment of the invention in which metamorphic growth is used. A relaxed interface 101b is defined between substrate 10 and the layer structure 7. In this embodiment, the lattice constant of the layer structure 7 differs significantly from the lattice constant of the substrate 10. Accordingly, the large lattice mismatch may lead to the formation of threading dislocations that may propagate into the layer structure. Depending on the material of layer structure 7, threading dislocations at the interface 101b result in interface states due to antisite defects that can be acceptorlike (for example when the layers above the interface 101b are gallium-rich, aluminum-rich or both gallium and aluminum-rich, i.e. gallium antimonide, aluminum antmonide, aluminum gallium antimonide) or donor-like (indium-rich layer structure 7, for example InGaAs, InAs, etc.). Such interface states modify the carrier concentration in the quantum well layer 20 by either depleting or enriching with carriers, depending on the interface state type. Embodiments of the invention include a separate remote charge reservoir layer 15, positioned close to the interface 101b. The remote charge reservoir layer 15 is preferably doped with an opposite type of impurity at a substantially equal concentration as the interface state carrier concentration.

In order to improve the layer quality by reducing threading dislocation densities, a thicker buffer layer than in lattice-matched structures may be preferred.

A typical example of a metamorphic high-mobility semiconductor heterostructure is given in Fig. 6 and experimental data for carrier mobility and carrier concentration in the quantum well as a function of charge concentration in the remote charge layer is given in Fig. 7. The structure in Fig. 6 may be manufactured by conventional epitaxial crystal growth technique such as molecular beam epitaxy or metal-organic vapor phase epitaxy. A plurality of buffer layers may be formed on a semi-insulating substrate 10, such as GaAs. The thickness and composition of the buffer layers may be determined by one skilled in the art. In this particular case, first buffer layer 11 is lattice-matched to the substrate, and may be, for example, GaAs, with a thickness selected from a range of at least 10 nm - several 100s nm, followed by the formation of a high-bandgap lattice-matched material 12, such as AIAs, which may be at least 10 nm thick, e.g., 100 nm. The high-bandgap buffer layer 12 is used as nucleation layer for the following high-bandgap, lattice-mismatched buffer layer 13, for example AlSb. AlSb grows favorably on AIAs and metamorphic interface results in lower density of dislocations. See, e.g., G.Tuttle, H. Kroemer, J. H. English, "Effects of interface layer sequencing on the transport properties of InAs/AISb quantum wells: evidence for antisite donors at the InAs/AISb interface," J. Appl. Phys., 67, 3032 (1990).

A thick buffer layer 14 is grown on lattice-mismatched buffer layer 13. The thick buffer layer 14 has a lattice constant of the desired virtual substrate, for instance GaSb as in Fig. 6. This layer is preferably sufficiently thick to minimize threading dislocation propagation but at the same time as thin as possible to minimize growth time. An appropriate thickness of the virtual substrate, i.e., of the thick buffer layer, depends on exact growth conditions, and may range from at least 50 nm to a several hundred nm.

Due to a metamorphic nature of the structure, the antisite defects created by threading dislocations result in p-type background impurities in the GaSb buffer layer 14 and n-type impurities in the InAs quantum well layer 20 as shown in the exemplary structure of Fig. 6. This leads to excess carrier concentration in the quantum well layer and, in turn, a decrease in mobility. To counteract this effect a first charge reservoir layer 15, i.e., a remote charge reservoir layer, is included, which can be either bulk or delta-doped with impurities of the opposite type then the interface states due to antisite defect formation. In the structure shown in Fig. 6 the remote charge reservoir layer 15 is delta-doped with Tellurium, acting as a donor in GaSb and AlSb. The impurity concentration in remote charge reservoir layer 15 is preferably substantially equal to the interface state density. An exact carrier density resulting from the interface strongly depends on actual growth conditions. In some embodiments, the carrier density is at least 10¹⁵ cm^"3 and may be as high as 10¹⁸cm^"3.

Formation of the first charge reservoir layer 15 is followed by growth of a high-bandgap first barrier layer 16, which acts as a barrier to the quantum well layer 20. An example of a suitable high-bandgap material is AlSb. The thickness of the high-bandgap first barrier layer 16 may be selected from a range of 1 nm - several hundred nm; a few tens of nm is typically sufficient.

The second charge reservoir layer 25 is formed on the high-bandgap first barrier layer 16. The second charge reservoir layer 25 is delta doped with impurities and acts as a charge supply layer to the quantum well layer 20. For highest carrier mobility, donor type of impurities are preferred, for example Te. A spacer layer 17 is formed over the second charge layer 25. The spacer layer 17 may be formed from a high-bandgap material, typically the same material as is used to form the high-bandgap first barrier layer 16, e.g., AlSb. The purpose of the spacer layer 17 is to spatially separate ionized donor atoms in the second charge layer 25 from the quantum well layer 20, which is grown following spacer layer 17. The spacer layer 17 is preferably sufficiently thick to minimize the 2DEG wavefunction overlap with the donor ions in layer 25. Depending on the structure, the spacer may be at least 1 nm thick, e.g., 5-10 nm thick.

The quantum well layer 20 may be formed from low-bandgap material with a low-effective mass and as high a carrier mobility as possible, e.g., a binary or a ternary material. A good choice for the quantum well is indium arsenide. Since the ground state of the quantum well has a symmetric wavefunction, a symmetric potential of the quantum well is desirable. For this purpose the growth of the quantum well is followed by growing an upper spacer layer 21, identical to the spacer layer 17, which is then followed by adding a third charge reservoir layer 30, which acts as a second charge supply layer to the quantum well layer 20. The thickness of the quantum well may be chosen such that the wavefunction of the 2DEG ground state does not penetrate the surrounding barrier materials of the spacer layer 17 and upper spacer layer 21. If the interface states are compensated by the remote first charge reservoir layer 15, the donor concentration in the third charge reservoir layer 30 is kept substantially the same as in second charge layer 25, providing symmetric potential and charge supply in the same manner as in the lattice-matched case. Formation of the third charge reservoir 30 is followed by growth of the upper barrier layer 35 which typically includes a high bandgap material, preferably of the same composition as the spacer layers 17, 21, e.g., AlSb. The upper barrier layer 35 acts as a barrier to the quantum well, i.e., provides confinement in the growth direction for the 2 dimensional electron gas (2DEG) carriers. Keeping the composition of the upper barrier layer 35 the same as that of the high-bandgap first barrier layer 16 is simpler from a manufacturing standpoint, as well as also ensuring a symmetric potential for the 2DEG.

The structure is finalized with a lower bandgap, aluminum-free cap layer 36, which is preferably thick enough to provide proper passivation of the layer structure to avoid oxidation, e.g., at least 1 nm thick. To avoid rapid oxidation, the cap layer 36 may be made from an aluminum-free material, such as GaSb.

Referring to Figures 7a and 7b, a maximum mobility is reached when the remote charge reservoir layer carrier concentration is substantially equal to the carrier density produced by the interface states. The presence of the interface states and the effect of compensation is clearly seen in Fig. 7b, where carrier concentration in the quantum well is plotted as a function of carrier concentration in the remote charge reservoir layer, e.g., first charge reservoir layer A clear minimum can be seen at a N ~ 2.8el7 cm^"3. This minimum corresponds to the carrier concentration substantially equal to the interface state density due to antisite defect formation by threading dislocations. Once this situation is reached, a maximum in the carrier mobility is observed (Fig. 7a) and a minimum in the quantum well carrier concentration (Fig 7b). Further increasing the doping level in the first charge reservoir layer 15 leads to an increase in quantum well carrier concentration and a reduction i n mobility due to excess carrier- carrier scattering. In the case where no interface states exist, a monotonic increase of carrier concentration in the quantum well is seen as the doping level in the remote charge reservoir layer increases. In the illustrated case, the interface states resulted in carrier concentration of ~ 2.8el7 cm^"3, corresponding to a carrier mobility of 14 000 cm²/Vs. This carrier mobility value is 30 % higher in comparison to a prior art case, when the remote charge layer is absent (corresponds to N = 0 cm^"3 in Fig. 6). The heterostructures described above can be used for a variety of device applications such as galvanomagnetic sensors, high-electron-mobility transistors ("H EMTs"), metal-semiconductor field effect transistors ("M ESFETs"), and pseudomorphic high-electron-mobility transistors ("pH EMTs").

An example of a simple galvanomagnetic device, also referred to as a Hall effect sensor, is shown in Fig. 8. Here, a planar configuration Hall cross structure with 4 contacts is realized. A voltage is applied between two diagonally disposed contacts, for example contacts 1 and 3. In case magnetic field B, perpendicular to the quantum well plane is present, it will result in a voltage drop between the other contact pair, for example contacts 2 and 4, due to a Hall effect. This voltage drop is typically called the Hall voltage. The magnitude of this voltage is proportional to the strength of the magnetic field, carrier mobility, and carrier concentration. The important device parameter for Hall sensors is the current and voltage sensitivity, which reflects the change in the Hall voltage as a function of the change of the magnetic field strength at a fixed bias voltage or current point. Voltage sensitivity is directly proportional to carrier mobility, whereas current sensitivity is inversely proportional to the carrier concentration. Therefore heterostructures with high-mobility in a wide carrier concentration range are desired for high-sensitivity Hall sensors. Hall sensors, such as the device shown in Fig. 8, can be fabricated by realizing a lattice-matched or metamorphic semiconductor heterostructure by epitaxial growth as described in detail above. The epitaxial wafer, including the substrate and layer structure, is then passivated with a dielectric material, for example silicon dioxide or silicon nitride and spin-coated with photoresist, and contact holes are developed in the photoresist. Using the photoresist layer as a mask, the contact holes are etched into the semiconductor layer structure by wet-chemical or dry etching. The etching preferably stops at the quantum well layer 20. The etching step is followed with contact hole sidewall passivation, keeping an open area at the bottom of the contact hole by use of photolithography and dielectric etching. Then, non-blocking ohmic contact pads are defined with appropriate materials, for example TiPtAu or GeAuNiAu, etc. The processing of lattice-matched and metamorphic structure is identical, except for the latter case the second charge layer 25 is positioned below the quantum well layer 20 and is not etched through.

The described embodiments of the invention are intended to be merely exemplary and numerous variations and modifications will be apparent to those skilled in the art. All such variations and modifications are intended to be within the scope of the present invention as defined in the appended claims.

Claims

1. A semiconductor heterostructure, comprising: a layer structure including: a first charge reservoir layer, a second charge reservoir layer and a third charge reservoir layer disposed over a substrate, each charge reservoir layer comprising a dopant type selected from the group consisting of donors and acceptors; and an undoped quantum well layer disposed between two of the charge reservoir layers.

2. The semiconductor heterostructure of claim 1, wherein (i) the two charge reservoir layers between which the quantum well layer is disposed comprise a first type of dopant, (ii) an interface between a top surface of the layer structure and air comprises a second type of surface states, and (iii) the first and second types are different.

3. The semiconductor heterostructure of claim 1 or claim 2, wherein a sheet doping density of the charge reservoir layer remote from the quantum well layer is substantially equal to a surface state sheet density of the layer structure.

4. The semiconductor heterostructure of any preceding claim wherein (i) the charge reservoir layer remote from the quantum well layer comprises a first type of dopant, (ii) an interface between the substrate and the layer structure comprises a second type of interface states, and (iii) the first type is different from the second type.

5. The semiconductor heterostructure of claim 4, wherein a sheet carrier density of the charge reservoir layer disposed closest to the substrate is substantially equal to an interface state sheet density of the interface.

6. The semiconductor heterostructure of any of claims 1 to 3, wherein the charge reservoir layer remote from the quantum well layer has a dopant type and concentration that enables the incorporation of a reduced dopant concentration in the two charge reservoir layers proximate the quantum well layer in comparison to a heterostructure without the remote charge reservoir layer, while maintaining constant a carrier concentration in the quantum well layer.

7. The semiconductor heterostructure of any preceding claim, wherein the substrate is lattice- matched to the layer structure.

8. The semiconductor heterostructure of claim 7, wherein the layer structure comprises at least one of (AIGaln)(As)-containing layers disposed on a GaAs substrate and (AIGaln)(AsP)-containing layers disposed on an InP substrate.

9. The semiconductor heterostructure of any of claims 1 to 6, wherein the substrate is not lattice- matched to the layer structure.

10. The semiconductor heterostructure of claim 9, wherein the layer structure comprises

(AIGaln)(AsSb)-containing layers disposed on a GaAs substrate.

11. The semiconductor heterostructure of any preceding claim, wherein the two charge reservoir layers proximate the quantum well layer comprise dopants of the same type at substantially equal concentrations.

12. The semiconductor heterostructure of any preceding claim, further comprising a plurality of layers disposed between one of the charge reservoir layers proximate the quantum layer and the charge reservoir layer remote from the quantum well layer.

13. The semiconductor heterostructure of any preceding claim, further comprising a spacer layer disposed between one of the charge reservoir layers proximate the quantum well layer and the charge reservoir layer remote from the quantum well layer.

14. The semiconductor heterostructure of claim 13, wherein the spacer layer comprises aluminum.

15. The semiconductor heterostructure of any preceding claim, further including at least one of an upper barrier layer and a cap layer disposed over the third charge reservoir layer.

16. The semiconductor heterostructure of claim 15, wherein the upper barrier layer comprises aluminum.

17. The semiconductor heterostructure of claim 15, wherein the cap layer is substantially free of aluminum.

18. The semiconductor heterostructure of any preceding claim, wherein the quantum well layer comprises at least a ternary composition, the layer structure further comprising a first binary material layer disposed between the quantum well layer and one of the two proximate charge reservoir layers.

19. The semiconductor heterostructure of claim 18, further comprising a second binary material layer disposed between the quantum well layer and the second of the two proximate charge reservoir layers.

20. An electronic device comprising the semiconductor heterostructure of any preceding claim.

21. The electronic device of claim 20, wherein the electronic device comprises a magnetic sensor.

22. The electronic device of claim 21, wherein the magnetic sensor comprises a galvano-magnetic sensor.

23. The electronic device of claim 20, wherein the electronic device comprises a transistor.

24. The electronic device of claim 23, wherein the transistor comprises at least one of a high- electron-mobility transistor, a pseudomorphic high-electron-mobility transistor, or a metal-oxide- semiconductor field effect transistor.

25. A method for manufacturing a semiconductor heterostructure, the method comprising the steps of: forming sequentially a first, a second, and a third charge reservoir layer over a substrate, each charge reservoir layer comprising a dopant type selected from the group consisting of donors and acceptors; and forming an undoped quantum well layer between two of the charge reservoir layers

26. The method of claim 25, wherein forming at least one of the charge reservoir layers comprises forming a delta-doped layer.

27. The method of claim 26, wherein forming the delta-doped layer comprises at least one of molecular beam epitaxy and metalorganic chemical vapor deposition.

28. The method of claim 25, wherein forming at least one of the charge reservoir layers comprises growing an undoped layer and subsequently doping the undoped layer.

29. The method of claim 28, wherein (i) growing the undoped layer comprises at least one of molecular beam epitaxy and metalorganic chemical vapor deposition; and (ii) doping the undoped layer comprises at least one of ion implantation and diffusion.

30. The method of claim 25, wherein forming at least one of the charge reservoir layers comprises forming a doped layer by at least one of molecular beam epitaxy and metalorganic chemical vapor deposition.

31. The method of any of claims 25 to 30, wherein the quantum well layer is formed between the first and second charge reservoir layers.

32. The method of any of claims 25 to 30, wherein the quantum well layer is formed between the second and third charge reservoir layers.

33. The method of any of claims 25 to 32, further comprising forming a spacer layer between one the charge reservoir layers proximate the quantum well layer and the charge reservoir layer remote from the quantum well layer.

34. The method of any of claims 25 to 32, further comprising forming at least one of an upper barrier layer and a cap layer over the third charge reservoir layer.