WO2023109231A1 - 显示面板的驱动方法及显示装置 - Google Patents

显示面板的驱动方法及显示装置 Download PDF

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Publication number
WO2023109231A1
WO2023109231A1 PCT/CN2022/120043 CN2022120043W WO2023109231A1 WO 2023109231 A1 WO2023109231 A1 WO 2023109231A1 CN 2022120043 W CN2022120043 W CN 2022120043W WO 2023109231 A1 WO2023109231 A1 WO 2023109231A1
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WIPO (PCT)
Prior art keywords
data
voltage
data line
pixel
data voltage
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PCT/CN2022/120043
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English (en)
French (fr)
Inventor
周留刚
王会明
孙建伟
汪俊
梁云云
李清
权宇
黄艳庭
陈韫璐
潘正汝
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Publication of WO2023109231A1 publication Critical patent/WO2023109231A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving method of a display panel and a display device.
  • a display such as a liquid crystal display (Liquid Crystal Display, LCD), generally includes a plurality of pixels.
  • Each pixel may include: a red sub-pixel, a green sub-pixel and a blue sub-pixel.
  • the display brightness of each sub-pixel is controlled, so as to display the color image by mixing the required displayed colors.
  • the display data input a data voltage to the data line, so that the sub-pixels electrically connected to the data line are charged with the corresponding data voltage; wherein, the data voltage input on the data line is divided into a plurality of voltage groups, Each of the voltage groups includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; the data voltages in the two adjacent voltage groups input to the same data line The corresponding polarities are different; the polarities of the voltage groups corresponding to two adjacent data lines are different.
  • the driving method also includes:
  • a reference voltage is input before the data voltage is input to the data line.
  • the driving method also includes:
  • the reference voltage is input before the first data voltage of the voltage group is input to the data line.
  • the data voltage is formed by dividing a first power supply voltage and a second power supply voltage; wherein, the first power supply voltage is smaller than the second power supply voltage;
  • the reference voltage is a voltage between the first power supply voltage and the second power supply voltage.
  • the reference voltage is a midpoint voltage between the first power supply voltage and the second power supply voltage.
  • the driving method also includes:
  • the voltage value of the first data voltage after superimposing the compensation voltage is greater than the first data voltage
  • the voltage value of the first data voltage after being superimposed with the compensation voltage is smaller than the first data voltage.
  • the compensation voltages superimposed corresponding to the first data voltages of the same polarity are the same.
  • the absolute values of the compensation voltages corresponding to each of the voltage groups are the same.
  • the duration of the data line being loaded with the data voltage and the duration of sub-pixels corresponding to the data voltage being turned on have a non-overlapping duration
  • the first data voltage loaded on the data line has a first non-overlapping duration
  • the remaining data voltages loaded on the data line have a second non-overlapping duration; wherein, the The first non-overlapping duration is shorter than the second non-overlapping duration.
  • the first non-overlapping duration of the first data voltage corresponding to positive polarity is shorter than the first non-overlapping duration of the first data voltage corresponding to negative polarity.
  • the timing controller is configured to: acquire and output the display data of the current display frame; and divide the data voltage input on the data line into a plurality of voltage groups, each of the voltage groups includes at least two adjacent Data voltages, the data voltages in the same voltage group have the same polarity; the data voltages in two adjacent voltage groups input to the same data line have different polarities; two adjacent data lines According to the rule that the polarity of the voltage group corresponding to the line is different, a polarity inversion signal is generated and output;
  • the display panel includes a source driving circuit; wherein, the source driving circuit is configured to receive the display data and the polarity inversion signal; according to the display data and the polarity inversion signal, input to the data line the data voltage, so that the sub-pixels electrically connected to the data line are charged with the corresponding data voltage.
  • the source driver circuit includes: a data processing circuit and a plurality of voltage output circuits; wherein each of the data lines is electrically connected to the voltage output circuits in one-to-one correspondence;
  • the data processing circuit is configured to receive the display data, and output corresponding display data to each of the voltage output circuits according to the display data;
  • the voltage output circuit is configured to receive the polarity inversion signal and the display data output by the data processing circuit, and according to the polarity inversion signal and the display data output by the data processing circuit, The connected data lines input data voltages sequentially, so that the sub-pixels electrically connected to the data lines are charged with corresponding data voltages.
  • the source driving circuit further includes: a first charge sharing circuit
  • the first charge sharing circuit is configured to receive a first reference control signal, and under the control of the first reference control signal, input a reference voltage before inputting each of the data voltages to an electrically connected data line.
  • the reference voltage is triggered by the first set edge of the first reference control signal, and input to the corresponding data line;
  • the data voltage is triggered by the second set edge of the first reference control signal, and input to the corresponding data line;
  • the first set edge is a rising edge
  • the second set edge is a falling edge
  • the first set edge is a falling edge
  • the second set edge is a rising edge
  • the first charge sharing circuit includes a first switching transistor
  • the gate of the first switching transistor is configured to receive the first reference control signal
  • the first pole of the first switching transistor is configured to receive the reference voltage
  • the second pole of the first switching transistor Electrically connected with the data line.
  • the source driving circuit further includes: a second charge sharing circuit
  • the second charge sharing circuit is configured to receive a second reference control signal, and under the control of the second reference control signal, input the first data of each of the voltage groups to each of the data lines voltage before inputting the reference voltage.
  • the second reference control signal is the polarity inversion signal.
  • the second charge sharing circuit includes a second switching transistor
  • the gate of the second switching transistor is configured to receive the second reference control signal, the first pole of the second switching transistor is configured to receive the reference voltage, and the second pole of the second switching transistor Electrically connected with the data line.
  • the voltage output circuit includes a first output circuit and a second output circuit; wherein each of the data lines is electrically connected to the first output circuit and the second output circuit in one-to-one correspondence;
  • the first output circuit is configured to input a data voltage corresponding to a positive polarity to an electrically connected data line according to the polarity inversion signal and the display data;
  • the second output circuit is configured to input a data voltage corresponding to a negative polarity to an electrically connected data line according to the polarity inversion signal and the display data.
  • the first output circuit includes: a first digital-to-analog conversion circuit and a first amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the first digital-to-analog conversion a circuit electrically connected between the second power supply voltage and the midpoint voltage terminal;
  • the first digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, and generate a data voltage corresponding to a positive polarity. output;
  • the first amplifier is configured to receive the data voltage output by the first digital-to-analog conversion circuit, amplify the received data voltage, and input it to the electrically connected data line.
  • the second output circuit includes: a second digital-to-analog conversion circuit and a second amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the second digital-to-analog conversion a circuit electrically connected between the first power supply voltage and the midpoint voltage terminal;
  • the second digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, and generate a data voltage corresponding to a negative polarity. output;
  • the second amplifier is configured to receive the data voltage output by the second digital-to-analog conversion circuit, amplify the received data voltage, and input it to the electrically connected data line.
  • FIG. 1 is some structural schematic diagrams of a display panel in an embodiment of the present disclosure
  • FIG. 2 is another structural schematic diagram of a display panel in an embodiment of the present disclosure
  • FIG. 3 is another structural schematic diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure.
  • FIG. 5 is some flowcharts of a driving method of a display panel in an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of some data voltages in an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of other data voltages in an embodiment of the present disclosure.
  • FIG. 8 is another timing diagram of signals in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a source driving circuit in an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • Fig. 11a is another timing diagram of signals in an embodiment of the present disclosure.
  • Fig. 11b is another timing diagram of signals in the embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 13 is another structural schematic diagram of the source driving circuit in the embodiment of the present disclosure.
  • FIG. 14 is a timing diagram of some other signals in the embodiment of the present disclosure.
  • FIG. 15 is another structural schematic diagram of the source driving circuit in the embodiment of the present disclosure.
  • FIG. 16 is a timing diagram of some other signals in an embodiment of the present disclosure.
  • FIG. 17 is a timing diagram of some other signals in the embodiment of the present disclosure.
  • FIG. 18 is a timing diagram of some other signals in the embodiment of the present disclosure.
  • the display device may include a display panel 100 and a timing controller 200 .
  • the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), a plurality of data lines DA (for example, DA1, DA2, DA3), gate
  • the driving circuit 110 and the source driving circuit 120 are coupled to the gate lines GA1 , GA2 , GA3 , GA4 respectively, and the source driving circuit 120 is coupled to the data lines DA1 , DA2 , DA3 respectively.
  • the timing controller 200 can input a control signal to the gate driving circuit 110 through a level shift (Level Shift) circuit, thereby driving the gate lines GA1, GA2, GA3, GA4.
  • the timing controller 200 inputs signals to the source driving circuit 120 so that the source driving circuit 120 inputs data voltages to the data lines, thereby charging the sub-pixels SPX and causing the sub-pixels SPX to input corresponding data voltages to realize the screen display function.
  • the number of source driving circuits 120 can be set to two, wherein one source driving circuit 120 is connected to half the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines.
  • three, four, or more source driving circuits 120 can also be provided, which can be designed and determined according to the requirements of practical applications, and are not limited here.
  • each pixel unit includes a plurality of sub-pixels SPX.
  • a pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that color mixing can be performed through red, green, blue and white to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the practical application environment, which is not limited here.
  • each sub-pixel SPX includes a transistor 01 and a pixel electrode 02 .
  • one row of sub-pixels SPX corresponds to one gate line
  • one column of sub-pixels SPX corresponds to one data line.
  • the gate of the transistor 01 is electrically connected to the corresponding gate line
  • the source of the transistor 01 is electrically connected to the corresponding data line
  • the drain of the transistor 01 is electrically connected to the pixel electrode 02.
  • the pixel array structure of the present disclosure can also be It is a double-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, there are data lines between two adjacent columns of pixels, and some adjacent two rows of pixels.
  • the data lines are not included between the pixels in the columns, and the specific arrangement structure of the pixels and the data lines, and the arrangement of the scanning lines are not limited.
  • the display panel in the embodiments of the present disclosure may be a liquid crystal display panel.
  • a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate.
  • the voltage difference can form an electric field, so that the liquid crystal molecules are under the action of the electric field to deflect.
  • the liquid crystal molecules are deflected in different degrees due to the electric fields of different intensities, resulting in different transmittances of the sub-pixels SPX, so that the sub-pixels SPX can achieve brightness of different gray scales, thereby realizing screen display.
  • the display panel in the embodiment of the present disclosure is a liquid crystal display panel
  • the pixel unit includes a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX as an example for illustration, but readers should know that the liquid crystal display panel includes The color of the sub-pixel SPX is not limited to this.
  • Grayscale generally divides the brightness change between the darkest and the brightest into several parts for easy screen brightness control.
  • the displayed image consists of three colors of red, green, and blue, each of which can show different brightness levels, and the combination of red, green, and blue at different brightness levels can form different colors.
  • the number of gray scale bits of the liquid crystal display panel is 6 bits
  • the three colors of red, green and blue have 64 (ie 2 6 ) gray scales respectively, and the 64 gray scale values are 0-63 respectively.
  • the number of gray scale digits of the liquid crystal display panel is 8 bits, and the three colors of red, green, and blue have 256 (ie, 2 8 ) gray scales respectively, and the 256 gray scale values are 0-255 respectively.
  • the number of grayscale digits of the liquid crystal display panel is 10 bits, and the three colors of red, green, and blue have 1024 (ie, 2 10 ) grayscales respectively, and these 1024 grayscale values are 0-1023 respectively.
  • the number of grayscale digits of the liquid crystal display panel is 12 bits, and the three colors of red, green, and blue have 4096 (ie, 2 12 ) grayscales respectively, and the 4096 grayscale values are 0-4093 respectively.
  • the liquid crystal molecules at the sub-pixel SPX can be made to be positive, and the sub-pixel The polarity corresponding to the data voltage Vda1 in the pixel SPX is positive.
  • the liquid crystal molecules at the sub-pixel SPX can be made to have a negative polarity, and then the polarity corresponding to the data voltage Vda2 in the sub-pixel SPX is negative.
  • the common electrode voltage can be 8.3V.
  • a data voltage of 8.8V-16V is input to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be made positive, and the 8.8V-16V
  • the data voltage is a data voltage corresponding to positive polarity. If a data voltage of 0.6V-7.8V is input into the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be negatively polarized, and the data voltage of 0.6V-7.8V is data corresponding to the negative polarity. Voltage.
  • the sub-pixel SPX can use the data voltage of positive polarity to realize the maximum gray scale value (that is, 255 grayscale value) brightness. If a data voltage of 0.6V is input to the pixel electrode of the sub-pixel SPX, the sub-pixel SPX can use the data voltage of negative polarity to achieve the brightness of the maximum gray scale value (ie 255 gray scale values).
  • the common electrode voltage is 8.3V
  • the data voltage corresponding to the positive polarity of the 0 grayscale value may be 8.8V, corresponding to 0
  • the data voltage of the negative polarity of the gray scale value may be 7.8V.
  • the data voltage of the 0 grayscale value and the common electrode voltage may also be the same. In practical applications, it can be determined according to the needs of practical applications, and no limitation is made here.
  • the data voltage may be formed by dividing the first power supply voltage and the second power supply voltage.
  • the first power supply voltage VY1 is smaller than the second power supply voltage VY2.
  • the midpoint voltage terminal HAVDD may be a voltage signal additionally input from an external signal source through a pin of the chip.
  • the voltage of the midpoint voltage terminal HAVDD may be 1/2*(VY2-VY1).
  • the voltage of the midpoint voltage terminal HAVDD can also fluctuate within a certain range up and down 1/2*(VY2-VY1), which is not limited here.
  • the data voltage corresponding to the positive polarity may be formed by dividing the voltage of the midpoint voltage terminal HAVDD and the second power supply voltage
  • the data voltage corresponding to the negative polarity may be formed by dividing the voltage of the midpoint voltage terminal HAVDD and the first power supply voltage.
  • the power supply voltage is divided to form.
  • the data voltage corresponding to the negative polarity realizing the maximum gray scale value may be the first power supply voltage VY1.
  • the data voltage corresponding to the negative polarity for realizing the maximum gray scale value may also be greater than the first power supply voltage VY1.
  • a data voltage corresponding to a positive polarity realizing a maximum grayscale value may be the second power supply voltage VY2.
  • the data voltage corresponding to the positive polarity to realize the maximum gray scale value may also be smaller than the second power supply voltage VY2.
  • the first power supply voltage VY1 can be made to be the ground voltage 0V
  • the second power supply voltage VY2 can be made to be the high power supply voltage AVDD
  • the voltage VHAVDD of the point voltage terminal HAVDD can be equal to 1/2*AVDD or can be at 1/2 *AVDD fluctuates within a certain range.
  • the data voltage 0.6V-7.8V corresponding to the negative polarity can be generated by dividing the voltage between 0V-VHAVDD
  • the data voltage 8.8V-16V corresponding to the positive polarity can be generated by dividing the voltage between VHAVDD-AVDD Generated by partial pressure.
  • VHAVDD may be the same as Vcom, or there may be a smaller voltage difference (for example, 0.1V, 0.5V) between VHAVDD and Vcom, etc., which is not limited herein.
  • the red sub-pixel R11 , the green sub-pixel G11 , and the blue sub-pixel B11 constitute a pixel unit
  • the red sub-pixel R12 , the green sub-pixel G12 , and the blue sub-pixel B12 constitute a pixel unit
  • the red sub-pixel R21, the green sub-pixel G21, and the blue sub-pixel B21 constitute a pixel unit
  • the red sub-pixel R22, the green sub-pixel G22, and the blue sub-pixel B22 constitute a pixel unit.
  • the red sub-pixel R31, the green sub-pixel G31, and the blue sub-pixel B31 constitute a pixel unit
  • the red sub-pixel R32, the green sub-pixel G32, and the blue sub-pixel B32 constitute a pixel unit
  • the red sub-pixel R41, the green sub-pixel G41, and the blue sub-pixel B41 constitute a pixel unit
  • the red sub-pixel R42, the green sub-pixel G42, and the blue sub-pixel B42 constitute a pixel unit
  • the red sub-pixel R51, the green sub-pixel G51, and the blue sub-pixel B51 constitute a pixel unit
  • the red sub-pixel R52, the green sub-pixel G52, and the blue sub-pixel B52 constitute a pixel unit.
  • the red sub-pixel R61, the green sub-pixel G61, and the blue sub-pixel B61 constitute a pixel unit
  • the red sub-pixel R62, the green sub-pixel G62, and the blue sub-pixel B62 constitute a pixel
  • the subpixels in areas Q1, Q3, Q4, and Q5 input data voltages of 127 grayscales
  • the green subpixels in area Q2 input data voltages of 255 grayscales
  • the rest of the subpixels input When the data voltage of the grayscale value is 0, taking column inversion as an example, the input of the red sub-pixel electrically connected to the data line DA1 corresponds to the data voltage of positive polarity, and the input of the green sub-pixel electrically connected to the data line DA2 corresponds to the data voltage of negative polarity.
  • the input of the blue sub-pixel electrically connected to the line DA3 corresponds to the data voltage of positive polarity
  • the input of the red sub-pixel electrically connected to the data line DA4 corresponds to the data voltage of negative polarity
  • the input of the green sub-pixel electrically connected to the data line DA5 corresponds to the data voltage of positive polarity
  • the blue sub-pixel electrically connected to the data line DA6 inputs a data voltage corresponding to a negative polarity.
  • the data lines DA2 , DA3 , DA5 , and DA6 and the sub-pixels electrically connected thereto will be described below as examples.
  • VDA2 represents the data voltage transmitted on the data line DA2
  • VDA3 represents the data voltage transmitted on the data line DA3
  • VDA5 represents the data voltage transmitted on the data line DA5
  • VDA6 represents the data voltage transmitted on the data line DA6.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA5 , so that the green sub-pixel G12 is input with the data voltage Vda21 .
  • the negative polarity data voltage Vda11 corresponding to 127 grayscale values is transmitted on the data line DA6, so that the blue sub-pixel B11 inputs the data voltage Vda11.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA5 , so that the green sub-pixel G22 is input with the data voltage Vda21 .
  • the negative polarity data voltage Vda11 corresponding to 127 gray scale values is transmitted on the data line DA6, so that the blue sub-pixel B22 inputs the data voltage Vda11.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA5, so that the green sub-pixel G32 is input with the data voltage Vda21.
  • the negative polarity data voltage Vda11 corresponding to 127 grayscale values is transmitted on the data line DA6, so that the blue sub-pixel B32 inputs the data voltage Vda11.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA5, so that the green sub-pixel G42 inputs the data voltage Vda21.
  • the negative polarity data voltage Vda11 corresponding to 127 grayscale values is transmitted on the data line DA6, so that the blue sub-pixel B42 inputs the data voltage Vda11.
  • the green sub-pixel G51, blue sub-pixel B51, green sub-pixel G52, and blue sub-pixel B52 are turned on, and the data line DA2 transmits negative polarity data corresponding to 255 gray scale values
  • the voltage Vda12 is used to make the green sub-pixel G51 input the data voltage Vda12.
  • the positive polarity data voltage Vda22 corresponding to 0 gray scale value is transmitted on the data line DA3, so that the blue sub-pixel B51 inputs the data voltage Vda22.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA5 , so that the green sub-pixel G52 inputs the data voltage Vda21 .
  • the negative polarity data voltage Vda11 corresponding to 127 grayscale values is transmitted on the data line DA6, so that the blue sub-pixel B52 inputs the data voltage Vda11.
  • the green sub-pixel G61, blue sub-pixel B61, green sub-pixel G62, and blue sub-pixel B62 are turned on, and the data line DA2 transmits the negative polarity signal corresponding to the gray scale value of 127.
  • the data voltage Vda11 is used to make the green sub-pixel G61 input the data voltage Vda11.
  • the positive polarity data voltage Vda21 corresponding to 127 grayscale values is transmitted on the data line DA3, so that the blue sub-pixel B61 inputs the data voltage Vda21.
  • the positive polarity data voltage Vda21 corresponding to 127 gray scale values is transmitted on the data line DA5, so that the green sub-pixel G62 inputs the data voltage Vda21.
  • the negative polarity data voltage Vda11 corresponding to 127 grayscale values is transmitted on the data line DA6, so that the blue sub-pixel B62 inputs the data voltage Vda11.
  • VG11 in FIG. 4 represents the actual voltage value on the pixel electrode in the green sub-pixel G11
  • VB12 represents the actual voltage value on the pixel electrode in the blue sub-pixel B12.
  • the data voltage Vda11 already charged on the pixel electrode in the cell is also pulled down, so that the voltage after being pulled is lower than Vda11. Since these two pulls of the data voltage on the pixel electrode in the green sub-pixel G11 are both downward, the pulling directions are the same and cannot cancel each other out, so the voltage of the pixel electrode in the green sub-pixel G11 after being pulled is greater than Less than Vda11.
  • the data voltage on the data line DA5 is always the positive data voltage Vda21 with a grayscale value of 127.
  • the data voltage on the data line DA6 is always the negative polarity data voltage Vda11 with a grayscale value of 127.
  • the coupling capacitor Cpd12 acts, it will not transfer the data already charged to the pixel electrode in the green sub-pixel G12. Voltage Vda11 is pulled. Therefore, the voltage on the pixel electrode in the green sub-pixel G12 can be relatively stable at the data voltage Vda11.
  • the voltage of the pixel electrode in the green sub-pixel G11 in the region Q1 after being pulled is lower than Vda11.
  • the voltage on the pixel electrode of the green sub-pixel G12 in the region Q5 can be relatively stable at the data voltage Vda11. Therefore, the luminance of the green sub-pixel G11 in the area Q1 is different from the luminance of the green sub-pixel G12 in the area Q5 , so that the problem of color shift occurs, thus improving the display effect.
  • An embodiment of the present disclosure provides a method for driving a display panel, as shown in FIG. 5 , which may include the following steps:
  • the display data includes a digital voltage form of a data voltage corresponding to each sub-pixel one-to-one.
  • a data voltage is input to each data line, so that the sub-pixels electrically connected to each data line are charged with the corresponding data voltage.
  • the data voltage is sequentially input to the data line, so that the sub-pixels electrically connected to the data line can input the corresponding data voltage.
  • the data voltage on the input data line is divided into multiple voltage groups, each voltage group includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; the input The data voltages in two adjacent voltage groups on the same data line correspond to different polarities; the corresponding voltage groups on two adjacent data lines have different polarities.
  • each voltage group may include two adjacent data voltages.
  • data voltage VR11-1 and data voltage VR21-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VR31-1 and data voltage VR41-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VR51-1 and The data voltage VR61-1 can be used as a voltage group and corresponds to a negative polarity.
  • the data voltage VG11-1 corresponding to the green sub-pixel G11, the data voltage VG21-1 corresponding to the green sub-pixel G21, the data voltage VG31-1 corresponding to the green sub-pixel G31, and the data voltage corresponding to the green sub-pixel G41 are sequentially transmitted on the data line DA2 VG41-1, the data voltage VG51-1 corresponding to the green sub-pixel G51, and the data voltage VG61-1 corresponding to the green sub-pixel G61.
  • data voltage VG11-1 and data voltage VG21-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VG31-1 and data voltage VG41-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VG51-1 and The data voltage VG61-1 can be regarded as a voltage group and corresponds to a positive polarity.
  • the data voltage VB11-1 corresponding to the blue sub-pixel B11, the data voltage VB21-1 corresponding to the blue sub-pixel B21, the data voltage VB31-1 corresponding to the blue sub-pixel B31, and the data voltage VB31-1 corresponding to the blue sub-pixel B41 are sequentially transmitted on the data line DA3.
  • data voltage VB11-1 and data voltage VB21-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VB31-1 and data voltage VB41-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VB51-1 and The data voltage VB61-1 can be used as a voltage group and corresponds to a negative polarity.
  • the data line DA4 sequentially transmits the data voltage VR12-1 corresponding to the red sub-pixel R12, the data voltage VR22-1 corresponding to the red sub-pixel R22, the data voltage VR32-1 corresponding to the red sub-pixel R32, and the data voltage corresponding to the red sub-pixel R42.
  • data voltage VR12-1 and data voltage VR22-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VR32-1 and data voltage VR42-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VR52-1 and The data voltage VR62-1 can be regarded as a voltage group and corresponds to positive polarity.
  • the data voltage VG12-1 corresponding to the green sub-pixel G12, the data voltage VG22-1 corresponding to the green sub-pixel G22, the data voltage VG32-1 corresponding to the green sub-pixel G32, and the data voltage corresponding to the green sub-pixel G42 are sequentially transmitted on the data line DA5 VG42-1, the data voltage VG52-1 corresponding to the green sub-pixel G52, and the data voltage VG62-1 corresponding to the green sub-pixel G62.
  • data voltage VG12-1 and data voltage VG22-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VG32-1 and data voltage VG42-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VG52-1 and The data voltage VG62-1 can be regarded as a voltage group and corresponds to a negative polarity.
  • the data voltage VB12-1 corresponding to the blue sub-pixel B12, the data voltage VB22-1 corresponding to the blue sub-pixel B22, the data voltage VB32-1 corresponding to the blue sub-pixel B32, and the data voltage VB32-1 corresponding to the blue sub-pixel B42 are sequentially transmitted on the data line DA6.
  • data voltage VB12-1 and data voltage VB22-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VB32-1 and data voltage VB42-1 can be used as a voltage group and correspond to negative polarity
  • data voltage VB52-1 and The data voltage VB62-1 can be regarded as a voltage group and corresponds to positive polarity.
  • each voltage group may include three adjacent data voltages.
  • “+” represents positive polarity
  • "-” represents negative polarity
  • the data corresponding to the red sub-pixel R11 is sequentially transmitted on the data line DA1 Voltage VR11-1, data voltage VR21-1 corresponding to red sub-pixel R21, data voltage VR31-1 corresponding to red sub-pixel R31, data voltage VR41-1 corresponding to red sub-pixel R41, data voltage VR51 corresponding to red sub-pixel R51 -1 and the data voltage VR61-1 corresponding to the red sub-pixel R61.
  • the data voltage VR11-1, the data voltage VR21-1 and the data voltage VR31-1 can be used as a voltage group and correspond to the negative polarity
  • the data voltage VR41-1, the data voltage VR51-1 and the data voltage VR61-1 can be used as a voltage group and corresponds to positive polarity.
  • the data voltage VG11-1 corresponding to the green sub-pixel G11, the data voltage VG21-1 corresponding to the green sub-pixel G21, the data voltage VG31-1 corresponding to the green sub-pixel G31, and the data voltage corresponding to the green sub-pixel G41 are sequentially transmitted on the data line DA2 VG41-1, the data voltage VG51-1 corresponding to the green sub-pixel G51, and the data voltage VG61-1 corresponding to the green sub-pixel G61.
  • data voltage VG11-1, data voltage VG21-1 and data voltage VG31-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VG41-1, data voltage VG51-1 and data voltage VG61-1 can be used as a voltage group group and corresponds to negative polarity.
  • the data voltage VB11-1 corresponding to the blue sub-pixel B11, the data voltage VB21-1 corresponding to the blue sub-pixel B21, the data voltage VB31-1 corresponding to the blue sub-pixel B31, and the data voltage VB31-1 corresponding to the blue sub-pixel B41 are sequentially transmitted on the data line DA3.
  • the data voltage VB11-1, the data voltage VB21-1 and the data voltage VB31-1 can be used as a voltage group and correspond to the negative polarity
  • the data voltage VB41-1, the data voltage VB51-1 and the data voltage VB61-1 can be used as a voltage group and corresponds to positive polarity.
  • the data line DA4 sequentially transmits the data voltage VR12-1 corresponding to the red sub-pixel R12, the data voltage VR22-1 corresponding to the red sub-pixel R22, the data voltage VR32-1 corresponding to the red sub-pixel R32, and the data voltage corresponding to the red sub-pixel R42.
  • the data voltage VR12-1, the data voltage VR22-1 and the data voltage VR32-1 can be used as a voltage group and correspond to the positive polarity
  • the data voltage VR42-1, the data voltage VR52-1 and the data voltage VR62-1 can be used as a voltage group and corresponds to negative polarity.
  • the data line DA5 sequentially transmits the data voltage VG12-1 corresponding to the green sub-pixel G12, the data voltage VG22-1 corresponding to the green sub-pixel G22, the data voltage VG32-1 corresponding to the green sub-pixel G32, and the data voltage corresponding to the green sub-pixel G42.
  • the data voltage VG12-1, the data voltage VG22-1 and the data voltage VG32-1 can be used as a voltage group and correspond to the negative polarity
  • the data voltage VG42-1, the data voltage VG52-1 and the data voltage VG62-1 can be used as a voltage group group and corresponds to positive polarity.
  • the data voltage VB12-1 corresponding to the blue sub-pixel B12, the data voltage VB22-1 corresponding to the blue sub-pixel B22, the data voltage VB32-1 corresponding to the blue sub-pixel B32, and the data voltage VB32-1 corresponding to the blue sub-pixel B42 are sequentially transmitted on the data line DA6.
  • data voltage VB12-1, data voltage VB22-1, and data voltage VB32-1 can be used as a voltage group and correspond to positive polarity
  • data voltage VB42-1, data voltage VB52-1, and data voltage VB62-1 can be used as a voltage group group and corresponds to negative polarity
  • each voltage group may also include four, five or other adjacent data voltages, which may be determined according to requirements of practical applications, and are not limited here.
  • the voltage groups corresponding to two adjacent data lines have different polarities, which may mean that the corresponding polarities of the data voltages input to the two data lines at the same time are different.
  • the data voltage VR11-1 on the data line DA1 the data voltage VG11-1 on the data line DA2
  • the data voltage VB11-1 on the data line DA3 the data voltage VR12-1 on the data line DA4
  • the data voltage on the data line DA5 The data voltage VG12-1 on the data line DA6 and the data voltage VB12-1 on the data line DA6 are simultaneously input.
  • the data voltage VR21-1 on the data line DA1 the data voltage VG21-1 on the data line DA2, the data voltage VB21-1 on the data line DA3, the data voltage VR22-1 on the data line DA4, the data voltage on the data line DA5
  • the data voltage VG22-1 on the data line DA6 and the data voltage VB22-1 on the data line DA6 are simultaneously input.
  • the data voltage VR31-1 on the data line DA1 the data voltage VG31-1 on the data line DA2, the data voltage VB31-1 on the data line DA3, the data voltage VR32-1 on the data line DA4, the data voltage on the data line DA5
  • the data voltage VG32-1 on the data line DA6 and the data voltage VB32-1 on the data line DA6 are simultaneously input.
  • the data voltage VR41-1 on the data line DA1 the data voltage VG41-1 on the data line DA2, the data voltage VB41-1 on the data line DA3, the data voltage VR42-1 on the data line DA4, and the data voltage on the data line DA5
  • the data voltage VG42-1 on the data line DA6 and the data voltage VB42-1 on the data line DA6 are simultaneously input.
  • the data voltage VR51-1 on the data line DA1 the data voltage VG51-1 on the data line DA2, the data voltage VB51-1 on the data line DA3, the data voltage VR52-1 on the data line DA4, the data voltage on the data line DA5
  • the data voltage VG52-1 on the data line DA6 and the data voltage VB52-1 on the data line DA6 are simultaneously input.
  • the data voltage VR61-1 on the data line DA1 the data voltage VG61-1 on the data line DA2, the data voltage VB61-1 on the data line DA3, the data voltage VR62-1 on the data line DA4, and the data voltage on the data line DA5
  • the data voltage VG62-1 on the data line DA6 and the data voltage VB62-1 on the data line DA6 are simultaneously input.
  • VDA2 represents the data voltage transmitted on the data line DA2
  • VDA3 represents the data voltage transmitted on the data line DA3
  • VDA5 represents the data voltage transmitted on the data line DA5
  • VDA6 represents the data voltage transmitted on the data line DA6.
  • VG11 represents the actual voltage value on the pixel electrode in the green sub-pixel G11
  • VB12 represents the actual voltage value on the pixel electrode in the blue sub-pixel B12.
  • the green sub-groups in the area Q5 can be made
  • the data voltage charged in the pixel G12 can cancel each other between pulling down and pulling up, so that the voltage on the pixel electrode can be relatively stable, and thus the brightness of the green sub-pixel G12 can be relatively stable.
  • the voltage in the area Q1 can be made
  • the data voltage charged in the green sub-pixel G11 can be alternately changed between pulling down and pulling up, so that the brightness of the green sub-pixel G11 can appear alternating complementary color flicker every time it passes through a voltage group, which can be expressed macroscopically as No color cast, thus improving the color cast phenomenon.
  • the timing controller 200 may acquire the display data of the current display frame F0, and store the display data corresponding to the current display frame in the form of digital voltage.
  • the timing controller 200 can divide the data voltage on the input data line into multiple voltage groups, each voltage group includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; The polarities of the data voltages in the two adjacent voltage groups of the data line are different; the rule that the polarity of the voltage groups corresponding to the two adjacent data lines is different generates a polarity inversion signal POL1 (as shown in Figure 10) .
  • the timing controller 200 sends the display data in the form of a digital signal and the generated polarity inversion signal POL1 to the source driving circuit 120, and the source driving circuit 120 can receive the display data and the polarity inversion signal POL1 sent by the timing controller 200, thereby According to the display data, the polarity inversion signal and the data loading signal TP, the data voltage can be input to the data line, so that the sub-pixels electrically connected to the data line are charged with the corresponding data voltage.
  • the source driving circuit 120 may invert the polarity of the data voltage loaded on the data line in response to the falling edge of the polarity inversion signal POL1, and load data on the data line in response to the falling edge of the data loading signal TP. Voltage.
  • the source driving circuit 120 may also reverse the polarity of the data voltage loaded on the data line in response to the above-mentioned edge of the polarity reversal signal POL1 .
  • the source driving circuit 120 can also load the data voltage to the data line in response to the rising edge of the data loading signal TP. These can be determined according to actual application requirements, and are not limited here.
  • the source driving circuit 120 may include: a data processing circuit 121 and a plurality of voltage output circuits (such as 122-1, 122-2); wherein, Each data line is electrically connected to the voltage output circuit one by one (for example, the data line DA1 is electrically connected to the voltage output circuit 122-1, and the data line DA2 is electrically connected to the voltage output circuit 122-2).
  • the data processing circuit 121 can receive display data, and output corresponding display data to each voltage output circuit according to the display data. It is also possible to optimize the display data and output the optimized display data to each voltage output circuit.
  • the voltage output circuit can receive the polarity inversion signal POL1 and the display data output by the data processing circuit 121, and according to the polarity inversion signal and the display data output by the data processing circuit 121, sequentially input data voltages to the electrically connected data lines, so that The sub-pixels electrically connected to the data lines are charged with corresponding data voltages.
  • the data processing circuit 121 can generate the data loading signal TP according to the display data, and output the data loading signal TP, the polarity inversion signal POL1 and the display data corresponding to the sub-pixels electrically connected to the data line DA1 to the voltage output circuit 122-1
  • the voltage output circuit 122-1 can control the display data to be loaded on the data line DA1 through the data loading signal TP, and control the corresponding polarity inversion of the display data through the polarity inversion signal POL1.
  • the data processing circuit 121 can generate the data loading signal TP according to the display data, and output the data loading signal TP, the polarity inversion signal POL1 and the display data corresponding to the sub-pixel electrically connected to the data line DA2 to the voltage output circuit 122-2 , the voltage output circuit 122-2 can control the display data to be loaded on the data line DA2 through the data loading signal TP, and control the corresponding polarity inversion of the display data through the polarity inversion signal POL1.
  • the voltage output circuit may include a first output circuit 123 and a second output circuit 124; wherein each data line is electrically connected to the first output circuit 123 and the second output circuit 124 in a one-to-one correspondence.
  • the second output circuit 124; and, the first output circuit 123 is configured to input a data voltage corresponding to a positive polarity to the electrically connected data line according to the polarity inversion signal and the display data.
  • the second output circuit 124 is configured to input the data voltage corresponding to the negative polarity to the electrically connected data line according to the polarity inversion signal and the display data.
  • the voltage output circuit 122-1 includes a first output circuit 123 and a second output circuit 124, and the first output circuit 123 can input a voltage corresponding to the positive polarity to the electrically connected data line DA1 according to the polarity inversion signal POL1 and display data. data voltage. Moreover, the second output circuit 124 can input a data voltage corresponding to a negative polarity to the electrically connected data line DA1 according to the polarity inversion signal POL1 and the display data.
  • the first output circuit 123 may include: a first digital-to-analog conversion circuit DAC-P and a second amplifier OP-P; wherein, the first digital-to-analog conversion circuit DAC-P circuit It is connected between the second power supply voltage and the midpoint voltage HAVDD.
  • the first digital-to-analog conversion circuit DAC-P is configured to receive the polarity inversion signal and the display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, and generate and output data voltage corresponding to a positive polarity.
  • the second amplifier OP-P is configured to receive the data voltage output by the first digital-to-analog conversion circuit DAC-P, amplify the received data voltage, and input it to the electrically connected data line.
  • the second output circuit 124 may include: a second digital-to-analog conversion circuit DAC-N and a second amplifier OP-N; wherein, the second digital-to-analog conversion circuit DAC-N circuit It is connected between the first power supply voltage and the midpoint voltage HAVDD.
  • the second digital-to-analog conversion circuit DAC-N is configured to receive the polarity inversion signal and display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, and generate and output data voltage corresponding to negative polarity.
  • the second amplifier OP-N is configured to receive the data voltage output by the second digital-to-analog conversion circuit DAC-N, amplify the received data voltage, and input it to the electrically connected data line.
  • ga1 represents the signal loaded on the gate line GA1
  • ga2 represents the signal loaded on the gate line GA2
  • ga3 represents the signal loaded on the gate line GA3
  • ga4 represents the signal loaded on the gate line GA4
  • ga5 represents the signal loaded on the gate line GA5
  • ga6 represents the signal loaded on the gate line GA6.
  • da1 represents the data voltage loaded on the data line DA1
  • da2 represents the data voltage loaded on the data line DA2.
  • the high level of the signals ga1 - ga6 can be used as a gate turn-on signal to control the transistors in the sub-pixels to be turned on.
  • a gate turn-on signal may be sequentially applied to the gate lines GA1 - GA6 .
  • the display frame F0 when the signal ga1 on the gate line GA1 outputs a high-level gate-on signal, the transistors in the red sub-pixel R11 and the green sub-pixel G11 are turned on. And in the time period T1 corresponding to the high level of the signal ga1, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R11, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • a digital-to-analog conversion circuit DAC-P the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R11 into a data voltage Vr11 of analog voltage through digital-to-analog conversion, and control the data voltage Vr11 through the data loading signal TP It is loaded on the data line DA1, and the polarity of the data voltage Vr11 is controlled to be negative by the polarity inversion signal POL1.
  • the data line DA1 is loaded with the data voltage Vr11 corresponding to the negative polarity of the display data, so that the red sub-pixel R11 receives the data voltage Vr11.
  • the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G11, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2.
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G11 into an analog data voltage Vg11 through digital-to-analog conversion, and control the data voltage Vg11 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg11 to be positive.
  • the data line DA2 is loaded with the data voltage Vg11 corresponding to the positive polarity of the display data, so that the green sub-pixel G11 receives the data voltage Vg11.
  • the signal ga2 on the gate line GA2 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R21 and the green sub-pixel G21 are turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R21 to precharge the red sub-pixel R21.
  • the data voltage Vg11 is simultaneously input into the green sub-pixel G21 to precharge the green sub-pixel G21.
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R31 and the green sub-pixel G31 are turned on.
  • the data voltage Vr11 is simultaneously input into the red sub-pixel R31 to precharge the red sub-pixel R31.
  • the data voltage Vg11 is simultaneously input into the green sub-pixel G31 to precharge the green sub-pixel G31.
  • the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R21, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • the digital-to-analog conversion circuit DAC-P, the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R21 into the data voltage Vr21 of analog voltage through digital-to-analog conversion, and control the loading of the data voltage Vr21 through the data loading signal TP On the data line DA1, and the polarity of the data voltage Vr21 is controlled to be negative by the polarity inversion signal POL1.
  • the negative polarity data voltage Vr21 corresponding to the display data is applied to the data line DA1, so that the red sub-pixel R21 is charged with the data voltage Vr21.
  • the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G21, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2.
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G21 into an analog data voltage Vg21 through digital-to-analog conversion, and control the data voltage Vg21 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg21 to be positive.
  • the data line DA2 is loaded with the data voltage Vg21 corresponding to the positive polarity of the display data, so that the green sub-pixel G21 is charged with the data voltage Vg21.
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R31 and the green sub-pixel G31 are turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R31 to precharge the red sub-pixel R31.
  • the data voltage Vg21 is simultaneously input into the green sub-pixel G31 to precharge the green sub-pixel G31.
  • the signal ga4 on the gate line GA4 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R41 and the green sub-pixel G41 are turned on.
  • the data voltage Vr21 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the data voltage Vg21 is simultaneously input into the green sub-pixel G41 to precharge the green sub-pixel G41.
  • the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R31, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • the digital-to-analog conversion circuit DAC-P, the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R31 into the data voltage Vr31 of analog voltage through digital-to-analog conversion, and control the loading of the data voltage Vr31 through the data loading signal TP On the data line DA1, and the polarity of the data voltage Vr31 is controlled to be positive by the polarity inversion signal POL1.
  • the data processing circuit 121 After the data voltage Vr31 is amplified by the second amplifier OP-P, the positive data voltage Vr31 corresponding to the display data is applied to the data line DA1, so that the red sub-pixel R31 is charged with the data voltage Vr31. Moreover, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G31, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2.
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G31 into the data voltage Vg31 of analog voltage through digital-to-analog conversion, and control the data voltage Vg31 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg31 to be negative.
  • the negative polarity data voltage Vg31 corresponding to the display data is applied to the data line DA2, so that the green sub-pixel G31 is charged with the data voltage Vg31.
  • the signal ga4 on the gate line GA4 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R41 and the green sub-pixel G41 are turned on.
  • the data voltage Vr31 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the data voltage Vg31 is simultaneously input into the green sub-pixel G41 to precharge the green sub-pixel G41.
  • the signal ga5 on the gate line GA5 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R51 and the green sub-pixel G51 are turned on.
  • the data voltage Vr31 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data voltage Vg31 is simultaneously input into the green sub-pixel G51 to precharge the green sub-pixel G51.
  • the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R41, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • the digital-to-analog conversion circuit DAC-P, the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R41 into the data voltage Vr41 of analog voltage through digital-to-analog conversion, and control the loading of the data voltage Vr41 through the data loading signal TP On the data line DA1, and the polarity of the data voltage Vr41 is controlled to be positive by the polarity inversion signal POL1.
  • the data line DA1 is loaded with the data voltage Vr41 corresponding to the positive polarity of the display data, so that the red sub-pixel R41 is charged with the data voltage Vr41.
  • the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G41, the data loading signal TP and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2, the first digital-to-analog
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G41 into an analog data voltage Vg41 through digital-to-analog conversion, and control the data voltage Vg41 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg41 to be negative.
  • the negative polarity data voltage Vg41 corresponding to the display data is applied to the data line DA2, so that the green sub-pixel G41 is charged with the data voltage Vg41.
  • the signal ga5 on the gate line GA5 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R51 and the green sub-pixel G51 are turned on.
  • the data voltage Vr41 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data voltage Vg41 is simultaneously input into the green sub-pixel G51 to precharge the green sub-pixel G51.
  • the signal ga6 on the gate line GA6 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R61 and the green sub-pixel G61 are turned on.
  • the data voltage Vr41 is simultaneously input into the red sub-pixel R61 to precharge the red sub-pixel R61.
  • the data voltage Vg41 is simultaneously input into the green sub-pixel G61 to precharge the green sub-pixel G61.
  • the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R51, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • the digital-to-analog conversion circuit DAC-P, the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R51 into the data voltage Vr51 of analog voltage through digital-to-analog conversion, and control the loading of the data voltage Vr51 through the data loading signal TP On the data line DA1, and the polarity of the data voltage Vr51 is controlled to be negative by the polarity inversion signal POL1.
  • the negative polarity data voltage Vr51 corresponding to the display data is applied to the data line DA1, so that the red sub-pixel R51 is charged with the data voltage Vr51.
  • the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G51, the data loading signal TP and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2, the first digital-to-analog
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G51 into an analog data voltage Vg51 through digital-to-analog conversion, and control the data voltage Vg51 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg51 to be positive.
  • the data line DA2 is loaded with the data voltage Vg51 corresponding to the positive polarity of the display data, so that the green sub-pixel G51 is charged with the data voltage Vg51.
  • the signal ga6 on the gate line GA6 outputs a high-level gate-on signal, and the transistors in the red sub-pixel R61 and the green sub-pixel G61 are turned on.
  • the data voltage Vr51 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data voltage Vg51 is simultaneously input into the green sub-pixel G61 to precharge the green sub-pixel G61.
  • the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R61, the data loading signal TP and the polarity inversion signal POL1 to the first voltage output circuit 122-1.
  • the digital-to-analog conversion circuit DAC-P, the first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R61 into the data voltage Vr61 of analog voltage through digital-to-analog conversion, and control the loading of the data voltage Vr61 through the data loading signal TP On the data line DA1, and the polarity of the data voltage Vr61 is controlled to be negative by the polarity inversion signal POL1.
  • the negative polarity data voltage Vr61 corresponding to the display data is applied to the data line DA1, so that the red sub-pixel R61 is charged with the data voltage Vr61. And precharge the next red sub-pixel.
  • the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G61, the data loading signal TP and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2, and the first digital-to-analog
  • the conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G61 into the data voltage Vg61 of analog voltage through digital-to-analog conversion, and control the data voltage Vg61 to be loaded on the data line DA2 through the data loading signal TP, and through the polarity inversion signal POL1 controls the polarity of the data voltage Vg61 to be positive.
  • the positive data voltage Vg61 corresponding to the display data is applied to the data line DA2, so that the green sub-pixel G61 is charged with the data voltage Vg61. And precharge the next green sub-pixel.
  • two adjacent data lines may be short-circuited to discharge the charges.
  • the voltage on the two data lines will change to the common electrode voltage Vcom after the two data lines are short-circuited to release the charges.
  • Vcom common electrode voltage
  • the data line DA1 can be changed from Vcom to 0.6V, and the data line DA2 can be changed from Vcom is 16V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is the common electrode voltage Vcom of 8.3V.
  • the data line DA1 can be changed from Vcom to 16V, and the data line DA2 can be changed from Vcom to 0.6V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 can be the common electrode voltage Vcom of 8.3V.
  • the data line DA1 can be changed from Vcom to 16V, and the data line DA2 can be changed from Vcom to 0.6V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is the common electrode voltage Vcom of 8.3V.
  • the data line DA1 can be changed from Vcom to 0.6V, and the data line DA2 can be changed from Vcom is 16V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is the common electrode voltage Vcom of 8.3V.
  • the data line DA1 can be changed from Vcom to 0.6V, and the data line DA2 can be changed from Vcom is 16V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is the common electrode voltage Vcom of 8.3V.
  • the data voltages loaded on two adjacent data lines are asymmetrical, after the two data lines are short-circuited to release the charge, the voltage on the two data lines will deviate from the common electrode voltage Vcom .
  • Vcom common electrode voltage
  • the data voltage is loaded on the data line next time, it will change from a voltage deviated from Vcom to the data voltage to be loaded, thus resulting in uneven charging of the data line. For example, as shown in FIG. 10 and FIG.
  • the data line DA1 can be changed from 6.3V less than Vcom to 0.6V, so that the data line DA2 changes from 6.3V less than Vcom to 12V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is 6.3V, which is lower than the common electrode voltage Vcom.
  • the data line DA1 can be changed from 6.3V less than Vcom to 16V, and the data line DA2 Change from 6.3V less than Vcom to 4.6V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is 10.3V, which is greater than the common electrode voltage Vcom.
  • the data line DA1 can be changed from 10.3V greater than Vcom to 16V, so that the data line DA2 From 10.3V greater than Vcom to 4.6V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is 10.3V, which is greater than the common electrode voltage Vcom.
  • the data line DA1 can be changed from 10.3V greater than Vcom to 0.6V, so that the data line DA2 changes from 10.3V greater than Vcom to 12V.
  • the data line DA1 and the data line DA2 are short-circuited to release the charge, so that the voltage on the data line DA1 and the data line DA2 is 6.3V, which is lower than the common electrode voltage Vcom.
  • the data line DA1 can be changed from 6.3V less than Vcom to 0.6V, so that the data line DA2 changes from 6.3V less than Vcom to 12V.
  • the reference point when the data line DA1 and the data line DA2 are charged is sometimes larger than Vcom, and sometimes smaller than Vcom, causing the problem of uneven charging.
  • the driving method provided by the embodiment of the present disclosure may further include: inputting a reference voltage before inputting a data voltage to the data line.
  • the charges on the data lines can be released without short-circuiting adjacent data lines.
  • each data voltage loaded on the data line can be charged from the reference point of the reference voltage, so as to improve charging uniformity.
  • the reference voltage VG is input to the data line DA1
  • the reference voltage VG is input to the data line DA2 .
  • the data voltage Vr11 is applied to the data line DA1
  • the data voltage Vg11 is applied to the data line DA2.
  • the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2.
  • the data voltage Vr21 is applied to the data line DA1
  • the data voltage Vg21 is applied to the data line DA2.
  • the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2.
  • the data voltage Vr31 is applied to the data line DA1, and the data voltage Vg31 is applied to the data line DA2. The rest are the same and will not be repeated here.
  • the reference voltage is a voltage between the first power supply voltage and the second power supply voltage. In this way, each data voltage loaded on the data line can be charged from the reference point of the reference voltage, so as to improve charging uniformity.
  • the reference voltage is a midpoint voltage HAVDD between the first power supply voltage and the second power supply voltage. Since the midpoint voltage HAVDD may be equal to Vcom, the difference between the midpoint voltage HAVDD and Vcom may be small, so that the data voltages are all charged from the midpoint voltage HAVDD, and the charging uniformity is further improved.
  • the source driving circuit may further include: a first charge sharing circuit 125; wherein, the first charge sharing circuit 125 is configured to receive the first reference control signal VS1, and Under the control of a reference control signal VS1, the reference voltage is input before each data voltage is input to the electrically connected data line.
  • the first charge sharing circuit 125 may include a first switch transistor M1; wherein, the gate of the first switch transistor M1 is configured to receive the first reference control signal VS1, and the first pole of the first switch transistor M1 is configured to To receive the reference voltage, the second pole of the first switching transistor M1 is electrically connected to the data line.
  • the first switch transistor M1 may be an N-type transistor or a P-type transistor, and the first pole may be a source, and the second pole may be a drain, or the first pole may be a drain, and the second pole may be a drain. can be the source.
  • the reference voltage is triggered by the rising edge of the first reference control signal VS1 and input to the corresponding data line.
  • the data voltage is triggered by the falling edge of the first reference control signal VS1 and input to the corresponding data line.
  • the first reference control signal VS1 may be the data loading signal TP.
  • the first switch transistor M1 is turned on, and the reference voltage VG is input to the data line DA1 .
  • the first switch transistor M1 In the T1 phase, triggered by the falling edge of the data loading signal TP, the first switch transistor M1 is turned off, and the data voltage Vr11 is loaded on the data line DA1. Before the T2 stage, triggered by the rising edge of the data loading signal TP, the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In the T2 phase, triggered by the falling edge of the data loading signal TP, the first switching transistor M1 is turned off, and the data voltage Vr21 is loaded on the data line DA1. Before the stage T3, triggered by the rising edge of the data loading signal TP, the first switch transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In the T3 phase, triggered by the falling edge of the data loading signal TP, the first switching transistor M1 is turned off, and the data voltage Vr31 is loaded on the data line DA1. The rest are the same and will not be repeated here.
  • the reference voltage is triggered by the falling edge of the first reference control signal VS1 and input to the corresponding data line.
  • the data voltage is triggered by the rising edge of the first reference control signal VS1 and inputted to the corresponding data line. Its implementation is roughly the same as the above, and will not be repeated here.
  • the embodiments of the present disclosure provide some other embodiments of driving methods of the display panel, which are modified for the implementation manners in the above-mentioned embodiments.
  • the following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the reference voltage is input before the first data voltage of the voltage group is input to the data line.
  • the charges on the data lines can be released without short-circuiting adjacent data lines.
  • each voltage group loaded on the data line can be charged from the reference point of the reference voltage, so as to improve charging uniformity.
  • the reference voltage VG is input to the data line DA1
  • the reference voltage VG is input to the data line DA2 .
  • the data voltage Vr11 is applied to the data line DA1
  • the data voltage Vg11 is applied to the data line DA2.
  • the data voltage Vr21 is applied to the data line DA1, and the data voltage Vg21 is applied to the data line DA2.
  • the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2.
  • the data voltage Vr31 is applied to the data line DA1, and the data voltage Vg31 is applied to the data line DA2. The rest are the same and will not be repeated here.
  • the data voltage VR11-1 is the first voltage group in the voltage group composed of the data voltage VR11-1 and the data voltage VR21-1.
  • data voltage The data voltage VR31-1 serves as the first data voltage in a voltage group consisting of the data voltage VR31-1 and the data voltage VR41-1.
  • the data voltage VR51-1 serves as the first data voltage in a voltage group consisting of the data voltage VR51-1 and the data voltage VR61-1.
  • the data voltage VG11-1 serves as the first data voltage in the voltage group consisting of the data voltage VG11-1 and the data voltage VG21-1.
  • the data voltage VG31-1 serves as the first data voltage in a voltage group consisting of the data voltage VG31-1 and the data voltage VG41-1.
  • the data voltage VG51-1 serves as the first data voltage in a voltage group consisting of the data voltage VG51-1 and the data voltage VG61-1.
  • taking the voltage group may include three adjacent data voltages as an example, for the data line DA1, the data voltage VR11-1 is composed of the data voltage VR11-1, the data voltage VR21-1 and the data voltage VR31-1.
  • the data voltage VR41-1 serves as the first data voltage in a voltage group consisting of the data voltage VR41-1, the data voltage VR51-1 and the data voltage VR61-1.
  • the data voltage VG11-1 is used as the first data voltage in the voltage group consisting of the data voltage VG11-1, the data voltage VG21-1 and the data voltage VG31-1.
  • the data voltage VG41-1 serves as the first data voltage in a voltage group consisting of the data voltage VG41-1, the data voltage VG51-1, and the data voltage VG61-1.
  • the source driving circuit further includes: a second charge sharing circuit 126; wherein, the second charge sharing circuit 126 is configured to receive the second reference control signal VS2, and Under the control of the reference control signal VS2, the reference voltage is input to each data line before the first data voltage of each voltage group is input.
  • the second charge sharing circuit 126 includes a second switch transistor M2; wherein, the gate of the second switch transistor M2 is configured to receive the second reference control signal VS2, and the first pole of the second switch transistor M2 is configured to Receiving the reference voltage, the second pole of the second switching transistor M2 is electrically connected to the data line.
  • the first pole may be a source and the second pole may be a drain, or the first pole may be a drain and the second pole may be a source.
  • the reference voltage is triggered by the rising edge of the second reference control signal VS2 and input to the corresponding data line.
  • the data voltage is triggered by the falling edge of the data loading signal TP, and is input to the corresponding data line.
  • the second reference control signal VS2 may be the polarity inversion signal POL1.
  • the second switching transistor M2 is turned on, and the reference voltage VG is input to the data line DA1 .
  • the first switching transistor M1 In the T1 phase, triggered by the rising edge of the polarity inversion signal POL1 , the first switching transistor M1 is turned off, and triggered by the falling edge of the data loading signal TP, the data voltage Vr11 is loaded on the data line DA1 . In the T2 phase, triggered by the falling edge of the data loading signal TP, the data voltage Vr21 is loaded on the data line DA1. Before the T3 stage, triggered by the rising edge of the polarity inversion signal POL1 , the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1 .
  • the first switching transistor M1 In the T3 phase, triggered by the rising edge of the polarity inversion signal POL1 , the first switching transistor M1 is turned off, and triggered by the falling edge of the data loading signal TP, the data voltage Vr31 is loaded on the data line DA1 . The rest are the same and will not be repeated here.
  • Embodiments of the present disclosure provide further embodiments of display panel driving methods, which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the data line DA1 is loaded with Vr11 of negative polarity.
  • the data line DA1 is loaded with Vr21 of negative polarity.
  • the data line DA1 is loaded with positive polarity Vr31.
  • the data line DA1 is loaded with Vr41 of positive polarity.
  • the data line DA1 is loaded with Vr51 of negative polarity.
  • the data line DA1 is loaded with Vr61 of negative polarity.
  • the red sub-pixel R31 is pre-charged with the voltage Vr21, and then Vr31 needs to be charged.
  • Vr21 is switched from Vr21 to Vr31, although Vr21 is pre-charged, because the negative polarity Vr21 is switched to the positive polarity Vr31, the voltage changes from low to high, and the change is too large.
  • Red sub-pixel R31 needs to charge Vr31. more difficult.
  • the red sub-pixel R41 is pre-charged with the voltage Vr31, and then Vr41 needs to be charged.
  • red sub-pixel R41 When the red sub-pixel R41 is switched from Vr31 to Vr41, Vr31 is pre-charged, but because the positive Vr31 is switched to positive Vr41, the voltage changes little, and it is easier for the red sub-pixel R41 to charge Vr41.
  • the red sub-pixel R51 is pre-charged with the voltage Vr41, and then Vr51 needs to be charged.
  • the red sub-pixel R51 is switched from Vr41 to Vr51, although Vr41 is pre-charged, but because the positive polarity Vr41 is switched to the negative polarity Vr51, the voltage changes from high to low, and the change is too large. Red sub-pixel R51 needs to charge Vr51. more difficult.
  • the red sub-pixel R61 is pre-charged with the voltage Vr51, and then Vr61 needs to be charged.
  • Vr51 is pre-charged, but since the negative polarity Vr51 is switched to negative polarity Vr61, the voltage change is small, and it is easier for the red sub-pixel R61 to charge Vr61.
  • the charging rate of the red sub-pixel R31 is lower than that of the red sub-pixel R41, and the charging rate of the red sub-pixel R51 is lower than that of the red sub-pixel R61. As a result, the charging rate of the sub-pixels is not uniform.
  • the driving method may further include: superimposing a compensation voltage on the data line when the first data voltage of the voltage group is input to the data line.
  • the voltage value of the first data voltage after superimposing the compensation voltage is greater than the first data voltage
  • the first data voltage corresponds to the negative polarity
  • the first data voltage is smaller than the first data voltage.
  • the superimposed compensation voltages corresponding to the first data voltages of the same polarity are the same.
  • the superimposed compensation voltages corresponding to the positive polarity first data voltages are the same.
  • the compensation voltages superimposed on the first data voltage corresponding to the negative polarity are the same.
  • the absolute values of the compensation voltages corresponding to each voltage group are the same.
  • the reference voltage VG is input to the data line DA1 , and the reference voltage VG is input to the data line DA2 .
  • the data voltage Vr11 and the compensation voltage VC1 are applied to the data line DA1
  • the data voltage Vg11 and the compensation voltage VC2 are applied to the data line DA2.
  • the data voltage Vr21 is applied to the data line DA1
  • the data voltage Vg21 is applied to the data line DA2.
  • the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2.
  • the data voltage Vr31 and the compensation voltage VC2 are applied to the data line DA1, and the data voltage Vg31 and the compensation voltage VC1 are applied to the data line DA2.
  • Embodiments of the present disclosure provide further embodiments of display panel driving methods, which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the overlapping duration is the charging duration of the sub-pixels.
  • the overlapping duration increases, that is, the charging duration of the sub-pixel increases, which increases the charging rate of the sub-pixel.
  • the first data voltage loaded on the data line has a first non-overlapping duration
  • the remaining data voltages loaded on the data lines have a second non-overlapping duration.
  • the first non-overlapping duration corresponding to each voltage group may be the same, and the second non-overlapping duration corresponding to each voltage group may be the same.
  • Vr11 and Vr21 are used as a voltage group
  • Vr11 is used as the first data voltage in the voltage group
  • Vr12 is used as the rest of the data voltages in the voltage group
  • the duration t21 of the gate turn-on signal corresponding to the red sub-pixel R11 has a first non-overlapping duration GOE1 .
  • the duration t12 of Vr21 being applied to the data line DA1 and the duration t22 of the gate-on signal corresponding to the red sub-pixel R21 have a second non-overlapping duration GOE2 .
  • Vg11 and Vg21 are used as a voltage group, Vg11 is used as the first data voltage in the voltage group, and Vg12 is used as the remaining data voltages in the voltage group, then the sustaining time t31 for Vg11 to be loaded on the data line DA2 is the same as the green sub-
  • the duration t21 of the gate-on signal corresponding to the pixel G11 has a first non-overlapping duration GOE1 .
  • the sustaining duration t32 of Vg21 applied to the data line DA2 and the sustaining duration t22 of the gate-on signal corresponding to the green sub-pixel G21 have a second non-overlapping duration GOE2 .
  • GOE1 ⁇ GOE2, t31 t32.
  • the first non-overlapping duration of the first data voltage corresponding to the positive polarity may also be made shorter than the first non-overlapping duration of the first data voltage corresponding to the negative polarity.
  • switching from a positive data voltage to a negative data voltage is equivalent to discharging, which is faster than switching from a negative data voltage to a positive data voltage. Therefore, by making the positive data voltage correspond to the first
  • the first non-overlapping duration of each data voltage is shorter than the first non-overlapping duration of the first data voltage corresponding to the negative polarity, so that the charging rate of the data voltage corresponding to the positive polarity can be greater than that of the data voltage corresponding to the negative polarity Rate. Thereby, the brightness is further uniformed.
  • Vr11 and Vr21 are used as a voltage group
  • Vr11 is used as the first data voltage in the voltage group
  • Vr12 is used as the remaining data voltages in the voltage group
  • Vr11 is loaded to the data line DA1
  • the sustaining period t11 above and the sustaining period t21 of the gate-on signal corresponding to the red sub-pixel R11 have a first non-overlapping period GOE11 .
  • Vg11 and Vg21 are used as a voltage group
  • Vg11 is used as the first data voltage in the voltage group
  • Vg12 is used as the remaining data voltages in the voltage group
  • the duration t31 for Vg11 to be applied to the data line DA2 is the same as that of the green sub-pixel G11
  • the corresponding duration t21 of the gate-on signal has a first non-overlapping duration GOE21 .
  • the charging rate of the data voltage corresponding to the positive polarity can be greater than that of the data voltage corresponding to the negative polarity.
  • the brightness is further uniformed.

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Abstract

公开了一种显示面板的驱动方法及显示装置，显示面板的驱动方法包括：获取当前显示帧的显示数据（S100）；根据显示数据，对数据线输入数据电压，以使数据线电连接的子像素充入对应的数据电压（S200）；其中，将输入数据线上的数据电压分为多个电压组，每个电压组包括相邻的至少两个数据电压，同一电压组中的数据电压对应的极性相同，输入同一数据线的相邻的两个电压组的数据电压对应的极性不同，相邻两条数据线上对应的电压组极性不同。

Description

显示面板的驱动方法及显示装置
相关申请的交叉引用
本申请要求在2021年12月16日提交中国专利局、申请号为202111542703.3、申请名称为“显示面板的驱动方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法及显示装置。
背景技术
在诸如液晶显示器(Liquid Crystal Display，LCD)等显示器中，一般包括多个像素。每个像素可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的显示数据，以控制每个子像素的显示亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本公开实施例提供的显示面板的驱动方法，包括：
获取当前显示帧的显示数据；
根据所述显示数据，对数据线输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压；其中，将输入所述数据线上的数据电压分为多个电压组，每个所述电压组包括相邻的至少两个数据电压，同一所述电压组中的数据电压对应的极性相同；输入同一所述数据线的相邻两个所述电压组中的数据电压对应的极性不同；相邻两条所述数据线上对应的所述电压组极性不同。
在一些示例中，所述驱动方法还包括：
在对所述数据线输入所述数据电压之前输入基准电压。
在一些示例中，所述驱动方法还包括：
在对所述数据线输入所述电压组的第一个数据电压之前输入所述基准电压。
在一些示例中，所述数据电压是通过将第一电源电压和第二电源电压分压形成的；其中，所述第一电源电压小于所述第二电源电压；
所述基准电压为所述第一电源电压和所述第二电源电压之间的电压。
在一些示例中，所述基准电压为所述第一电源电压和所述第二电源电压之间的中点电压。
在一些示例中，所述驱动方法还包括：
在对所述数据线输入所述电压组的第一个数据电压时，在所述数据线上叠加补偿电压；
其中，在所述第一个数据电压对应正极性时，所述第一个数据电压叠加所述补偿电压后的电压值大于所述第一个数据电压；
在所述第一个数据电压对应负极性时，所述第一个数据电压叠加所述补偿电压后的电压值小于所述第一个数据电压。
在一些示例中，不同所述电压组中，对应同一极性的所述第一数据电压叠加的所述补偿电压相同。
在一些示例中，每一个所述电压组对应的所述补偿电压的绝对值相同。
在一些示例中，所述数据线加载所述数据电压的维持时长与所述数据电压对应的子像素打开的维持时长具有非交叠时长；
同一所述电压组中，加载到所述数据线上的第一个数据电压具有第一非交叠时长，加载到所述数据线上的其余数据电压具有第二非交叠时长；其中，所述第一非交叠时长小于所述第二非交叠时长。
在一些示例中，对应正极性的所述第一个数据电压的所述第一非交叠时长小于对应负极性的所述第一个数据电压的所述第一非交叠时长。
本公开实施例提供的显示装置，包括：
时序控制器，被配置为：获取当前显示帧的显示数据并输出；以及基于 将输入所述数据线上的数据电压分为多个电压组，每个所述电压组包括相邻的至少两个数据电压，同一所述电压组中的数据电压对应的极性相同；输入同一所述数据线的相邻两个所述电压组中的数据电压对应的极性不同；相邻两条所述数据线上对应的所述电压组极性不同的规则，生成极性翻转信号并输出；
显示面板，包括源极驱动电路；其中，所述源极驱动电路被配置为接收所述显示数据和所述极性翻转信号；根据所述显示数据和所述极性翻转信号，对数据线输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压。
在一些示例中，所述源极驱动电路包括：数据处理电路以及多个电压输出电路；其中，每一条所述数据线一一对应电连接所述电压输出电路；
所述数据处理电路被配置为接收所述显示数据，并根据所述显示数据，对各所述电压输出电路输出对应的显示数据；
所述电压输出电路被配置为接收所述极性翻转信号和所述数据处理电路输出的所述显示数据，根据所述极性翻转信号和所述数据处理电路输出的所述显示数据，对电连接的数据线依次输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压。
在一些示例中，所述源极驱动电路还包括：第一电荷共享电路；
所述第一电荷共享电路被配置为接收第一基准控制信号，并在所述第一基准控制信号的控制下，在对电连接的数据线输入每一个所述数据电压之前输入基准电压。
在一些示例中，所述基准电压受所述第一基准控制信号的第一设定沿触发，输入到对应的所述数据线上；
所述数据电压受所述第一基准控制信号的第二设定沿触发，输入到对应的所述数据线上；
其中，所述第一设定沿为上升沿，所述第二设定沿为下降沿；
或者，所述第一设定沿为下降沿，所述第二设定沿为上升沿。
在一些示例中，所述第一电荷共享电路包括第一开关晶体管；
所述第一开关晶体管的栅极被配置为接收所述第一基准控制信号，所述第一开关晶体管的第一极被配置为接收所述基准电压，所述第一开关晶体管的第二极与数据线电连接。
在一些示例中，所述源极驱动电路还包括：第二电荷共享电路；
所述第二电荷共享电路被配置为接收第二基准控制信号，并在所述第二基准控制信号的控制下，在对每一条所述数据线输入每一个所述电压组的第一个数据电压之前输入所述基准电压。
在一些示例中，所述第二基准控制信号为所述极性翻转信号。
在一些示例中，所述第二电荷共享电路包括第二开关晶体管；
所述第二开关晶体管的栅极被配置为接收所述第二基准控制信号，所述第二开关晶体管的第一极被配置为接收所述基准电压，所述第二开关晶体管的第二极与数据线电连接。
在一些示例中，所述电压输出电路包括第一输出电路和第二输出电路；其中，每一条所述数据线一一对应电连接所述第一输出电路和所述第二输出电路；
所述第一输出电路被配置为根据所述极性翻转信号和所述显示数据，对电连接的数据线输入对应正极性的数据电压；
所述第二输出电路被配置为根据所述极性翻转信号和所述显示数据，对电连接的数据线输入对应负极性的数据电压。
在一些示例中，所述第一输出电路包括：第一数模转换电路和第一放大器；其中，第一电源电压和第二电源电压之间具有中点电压端，所述第一数模转换电路电连接于第二电源电压和所述中点电压端之间；
所述第一数模转换电路被配置为接收所述极性翻转信号和所述显示数据，根据所述极性翻转信号，将所述显示数据进行数模转换后产生对应正极性的数据电压并输出；
所述第一放大器被配置为接收所述第一数模转换电路输出的数据电压， 并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
在一些示例中，所述第二输出电路包括：第二数模转换电路和第二放大器；其中，第一电源电压和第二电源电压之间具有中点电压端，所述第二数模转换电路电连接于第一电源电压和所述中点电压端之间；
所述第二数模转换电路被配置为接收所述极性翻转信号和所述显示数据，根据所述极性翻转信号，将所述显示数据进行数模转换后产生对应负极性的数据电压并输出；
所述第二放大器被配置为接收所述第二数模转换电路输出的数据电压，并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
附图说明
图1为本公开实施例中的显示面板的一些结构示意图；
图2为本公开实施例中的显示面板的另一些结构示意图；
图3为本公开实施例中的显示面板的又一些结构示意图；
图4为本公开实施例中的一些信号时序图；
图5为本公开实施例中的显示面板的驱动方法的一些流程图；
图6为本公开实施例中的一些数据电压的示意图；
图7为本公开实施例中的另一些数据电压的示意图；
图8为本公开实施例中的另一些信号时序图；
图9为本公开实施例中的源极驱动电路的一些结构示意图；
图10为本公开实施例中的又一些信号时序图；
图11a为本公开实施例中的又一些信号时序图；
图11b为本公开实施例中的又一些信号时序图；
图12为本公开实施例中的又一些信号时序图；
图13为本公开实施例中的源极驱动电路的另一些结构示意图；
图14为本公开实施例中的又一些信号时序图；
图15为本公开实施例中的源极驱动电路的又一些结构示意图；
图16为本公开实施例中的又一些信号时序图；
图17为本公开实施例中的又一些信号时序图；
图18为本公开实施例中的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1与图2，显示装置可以包括显示面板100以及时序控制器200。其中，显示面板100可以包括多个阵列排布的像素单元，多条栅线GA(例如，GA1、GA2、GA3、GA4)、多条数据线DA(例如，DA1、DA2、DA3)、栅极驱动电路110以及源极驱动电路120。栅极驱动电路110分别与栅线GA1、GA2、GA3、GA4耦接，源极驱动电路120分别与数据线DA1、DA2、DA3耦接。其中，时序控制器200可以通过电平转换(Level Shift)电路向栅极驱 动电路110输入控制信号，从而驱动栅线GA1、GA2、GA3、GA4。时序控制器200向源极驱动电路120输入信号，以使源极驱动电路120向数据线输入数据电压，从而对子像素SPX充电，使子像素SPX输入相应的数据电压，实现画面显示功能。示例性地，源极驱动电路120可以设置为2个，其中一个源极驱动电路120连接一半数量的数据线，另一个源极驱动电路120连接另一半数量的数据线。当然，源极驱动电路120也可以设置3个、4个、或更多个，其可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，每个像素单元包括多个子像素SPX。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
参见图2所示，每个子像素SPX中包括晶体管01和像素电极02。其中，一行子像素SPX对应一条栅线，一列子像素SPX对应一条数据线。晶体管01的栅极与对应的栅线电连接，晶体管01的源极与对应的数据线电连接，晶体管01的漏极与像素电极02电连接，需要说明的是，本公开像素阵列结构还可以是双栅结构，即相邻两行像素之间设置两条栅极线，此排布方式可以减少一半的数据线，即包含相邻两列像素之间有的数据线，有的相邻两列像素之间不包括数据线，具体像素排布结构和数据线，扫描线的排布方式不限定。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板。示例性地，液晶显示面板一般包括对盒的上基板和下基板，以及封装在上基板和下基板之间的液晶分子。在显示画面时，由于加载在各子像素SPX的像素电极上的数据电压和公共电极上的公共电极电压之间具有电压差，该电压差可以形成电场，从而使液晶分子在该电场的作用下进行偏转。由于不同强度的电场使液晶分子的偏转程度不同，从而导致子像素SPX的透过率不同，以使 子像素SPX实现不同灰阶的亮度，进而实现画面显示。
下面均以本公开实施例中的显示面板为液晶显示面板，且像素单元包括红色子像素SPX、绿色子像素SPX、蓝色子像素SPX为例进行说明，但是读者应知，液晶显示面板中包括的子像素SPX的颜色并不局限于此。
灰阶，一般是将最暗与最亮之间的亮度变化区分为若干份，以便于进行屏幕亮度管控。例如，以显示的图像由红、绿、蓝三种颜色组成，其中每一个颜色都可以显现出不同的亮度级别，并且不同亮度层次的红、绿、蓝组合起来，可以形成不同的色彩。例如，液晶显示面板的灰阶位数为6bit，则红、绿、蓝这三种颜色分别具有64(即2 6)个灰阶，这64个灰阶值分别为0～63。液晶显示面板的灰阶位数为8bit，则红、绿、蓝这三种颜色分别具有256(即2 8)个灰阶，这256个灰阶值分别为0～255。液晶显示面板的灰阶位数为10bit，则红、绿、蓝这三种颜色分别具有1024(即2 10)个灰阶，这1024个灰阶值分别为0～1023。液晶显示面板的灰阶位数为12bit，则红、绿、蓝这三种颜色分别具有4096(即2 12)个灰阶，这4096个灰阶值分别为0～4093。
示例性地，以一个子像素SPX为例，在该子像素SPX的像素电极中输入的数据电压Vda1大于公共电极电压Vcom时，可以使该子像素SPX处的液晶分子为正极性，则该子像素SPX中的数据电压Vda1对应的极性为正极性。在子像素SPX的像素电极中输入的数据电压Vda2小于公共电极电压Vcom时，可以使该子像素SPX处的液晶分子为负极性，则该子像素SPX中的数据电压Vda2对应的极性为负极性。例如，公共电极电压可以为8.3V，若在该子像素SPX的像素电极中输入了8.8V～16V的数据电压，可以使该子像素SPX处的液晶分子为正极性，则8.8V～16V的数据电压为对应正极性的数据电压。若在该子像素SPX的像素电极中输入了0.6V～7.8V的数据电压，可以使该子像素SPX处的液晶分子为负极性，则0.6V～7.8V的数据电压为对应负极性的数据电压。示例性地，以8bit的0～255灰阶为例，若在子像素SPX的像素电极中输入16V的数据电压时，该子像素SPX可以采用正极性的数据电压实现最大灰阶值(即255灰阶值)的亮度。若在子像素SPX的像素电极中输入0.6V 的数据电压时，该子像素SPX可以采用负极性的数据电压实现最大灰阶值(即255灰阶值)的亮度。需要说明的是，0灰阶值的数据电压与公共电极电压之间可能具有电压差，例如，公共电极电压为8.3V，对应0灰阶值的正极性的数据电压可以为8.8V，对应0灰阶值的负极性的数据电压可以为7.8V。当然，0灰阶值的数据电压与公共电极电压也可以相同。在实际应用中，可以根据实际应用的需要进行确定，在此不作限定。
示例性地，数据电压可以是通过将第一电源电压和第二电源电压分压形成。其中，第一电源电压VY1小于第二电源电压VY2。例如，第一电源电压VY1与第二电源电压VY2之间具有一个中点电压端HAVDD。该中点电压端HAVDD可以是额外通过外部信号源通过芯片的引脚输入的电压信号。并且，中点电压端HAVDD的电压可以为1/2*(VY2-VY1)。或者，中点电压端HAVDD的电压也可以在1/2*(VY2-VY1)上下一定范围内波动，在此不作限定。
示例性地，对应正极性的数据电压可以是通过将中点电压端HAVDD的电压与第二电源电压分压形成，对应负极性的数据电压可以是通过将中点电压端HAVDD的电压与第一电源电压分压形成。例如，实现最大灰阶值的对应负极性的数据电压可以是第一电源电压VY1。例如，实现最大灰阶值的对应负极性的数据电压也可以大于第一电源电压VY1。例如，实现最大灰阶值的对应正极性的数据电压可以是第二电源电压VY2。例如，实现最大灰阶值的对应正极性的数据电压也可以小于第二电源电压VY2。示例性地，可以使第一电源电压VY1为接地电压0V，可以使第二电源电压VY2为高电源电压AVDD，其中点电压端HAVDD的电压VHAVDD可以等于1/2*AVDD或者可以在1/2*AVDD上下的一定范围内波动。并且，对应负极性的数据电压0.6V～7.8V可以是通过将0V～VHAVDD之间的电压通过分压产生，对应正极性的数据电压8.8V～16V可以是通过将VHAVDD～AVDD之间的电压通过分压产生。需要说明的是，VHAVDD可以与Vcom相同，或者，VHAVDD可以与Vcom之间具有较小的电压差(例如，0.1V、0.5V)等，在此不作限定。
下面以像素单元包括红色子像素，绿色子像素以及蓝色子像素为例进行说明。如图3所示，红色子像素R11、绿色子像素G11、以蓝色子像素B11为一个像素单元，红色子像素R12、绿色子像素G12、以蓝色子像素B12为一个像素单元。红色子像素R21、绿色子像素G21、以蓝色子像素B21为一个像素单元，红色子像素R22、绿色子像素G22、以蓝色子像素B22为一个像素单元。红色子像素R31、绿色子像素G31、以蓝色子像素B31为一个像素单元，红色子像素R32、绿色子像素G32、以蓝色子像素B32为一个像素单元。红色子像素R41、绿色子像素G41、以蓝色子像素B41为一个像素单元，红色子像素R42、绿色子像素G42、以蓝色子像素B42为一个像素单元。红色子像素R51、绿色子像素G51、以蓝色子像素B51为一个像素单元，红色子像素R52、绿色子像素G52、以蓝色子像素B52为一个像素单元。红色子像素R61、绿色子像素G61、以蓝色子像素B61为一个像素单元，红色子像素R62、绿色子像素G62、以蓝色子像素B62为一个像素单元。
结合图3与图4所示，在区域Q1、Q3、Q4、Q5中的子像素输入127灰阶的数据电压，区域Q2中的绿色子像素输入255灰阶值的数据电压且其余子像素输入0灰阶值的数据电压时，以列翻转为例，数据线DA1电连接的红色子像素输入对应正极性的数据电压，数据线DA2电连接的绿色子像素输入对应负极性的数据电压，数据线DA3电连接的蓝色子像素输入对应正极性的数据电压，数据线DA4电连接的红色子像素输入对应负极性的数据电压，数据线DA5电连接的绿色子像素输入对应正极性的数据电压，数据线DA6电连接的蓝色子像素输入对应负极性的数据电压。下面以数据线DA2、DA3、DA5以及DA6及其电连接的子像素为例进行说明。在图4中，VDA2代表数据线DA2上传输的数据电压，VDA3代表数据线DA3上传输的数据电压，VDA5代表数据线DA5上传输的数据电压，VDA6代表数据线DA6上传输的数据电压。
在显示帧F01中，在GA1控制第一行子像素打开时，则有绿色子像素G11、蓝色子像素B11、绿色子像素G12、蓝色子像素B12打开，数据线DA2 上传输对应127灰阶值的负极性的数据电压Vda11，以使绿色子像素G11输入该数据电压Vda11。数据线DA3上传输对应127灰阶值的正极性的数据电压Vda21，以使蓝色子像素B11输入该数据电压Vda21。数据线DA5上传输对应127灰阶值的正极性的数据电压Vda21，以使绿色子像素G12输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B11输入该数据电压Vda11。
在GA2控制第二行子像素打开时，则有绿色子像素G21、蓝色子像素B21、绿色子像素G22、蓝色子像素B22打开，数据线DA2上传输对应255灰阶值的负极性的数据电压Vda12，以使绿色子像素G21输入该数据电压Vda12。数据线DA3上传输对应0灰阶值的正极性的数据电压Vda22，以使蓝色子像素B21输入该数据电压Vda22。数据线DA5上传输对应127灰阶值的正极性的数据电压Vda21，以使绿色子像素G22输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B22输入该数据电压Vda11。
在GA3控制第三行子像素打开时，则有绿色子像素G31、蓝色子像素B31、绿色子像素G32、蓝色子像素B32打开，数据线DA2上传输对应255灰阶值的负极性的数据电压Vda12，以使绿色子像素G31输入该数据电压Vda12。数据线DA3上传输对应0灰阶值的正极性的数据电压Vda22，以使蓝色子像素B31输入该数据电压Vda22。数据线DA5上传输对应127灰阶值的正极性的数据电压Vda21，以使绿色子像素G32输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B32输入该数据电压Vda11。
在GA4控制第四行子像素打开时，则有绿色子像素G41、蓝色子像素B41、绿色子像素G42、蓝色子像素B42打开，数据线DA2上传输对应255灰阶值的负极性的数据电压Vda12，以使绿色子像素G41输入该数据电压Vda12。数据线DA3上传输对应0灰阶值的正极性的数据电压Vda22，以使蓝色子像素B41输入该数据电压Vda22。数据线DA5上传输对应127灰阶值的正极性 的数据电压Vda21，以使绿色子像素G42输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B42输入该数据电压Vda11。
在GA5控制第五行子像素打开时，则有绿色子像素G51、蓝色子像素B51、绿色子像素G52、蓝色子像素B52打开，数据线DA2上传输对应255灰阶值的负极性的数据电压Vda12，以使绿色子像素G51输入该数据电压Vda12。数据线DA3上传输对应0灰阶值的正极性的数据电压Vda22，以使蓝色子像素B51输入该数据电压Vda22。数据线DA5上传输对应127灰阶值的正极性的数据电压Vda21，以使绿色子像素G52输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B52输入该数据电压Vda11。
在GA6控制第六行子像素打开时，则有绿色子像素G61、蓝色子像素B61、绿色子像素G62、蓝色子像素B62打开，数据线DA2上传输对应127灰阶值的负极性的数据电压Vda11，以使绿色子像素G61输入该数据电压Vda11。数据线DA3上传输对应127灰阶值的正极性的数据电压Vda21，以使蓝色子像素B61输入该数据电压Vda21。数据线DA5上传输对应127灰阶值的正极性的数据电压Vda21，以使绿色子像素G62输入该数据电压Vda21。数据线DA6上传输对应127灰阶值的负极性的数据电压Vda11，以使蓝色子像素B62输入该数据电压Vda11。
由于像素电极与其相邻的数据线之间具有耦合电容，例如，绿色子像素G11中的像素电极与数据线DA2之间具有耦合电容Cpd11，绿色子像素G11中的像素电极与数据线DA3之间具有耦合电容Cpd12。结合图4以及上述描述可知，图4中的VG11代表绿色子像素G11中的像素电极上实际的电压值，VB12代表蓝色子像素B12中的像素电极上实际的电压值。数据线DA2上的数据电压由127灰阶值的负极性的数据电压Vda11跳变为255灰阶值的负极性的数据电压Vda12时，由于耦合电容Cpd11的作用，会将绿色子像素G11中的像素电极上已经充入的数据电压Vda11向下拉动，使拉动候的电压小于 Vda11。并且，数据线DA3上的数据电压由127灰阶值的正极性的数据电压Vda21跳变为0灰阶值的正极性的数据电压Vda22时，由于耦合电容Cpd12的作用，会将绿色子像素G11中的像素电极上已经充入的数据电压Vda11也向下拉动，使拉动候的电压小于Vda11。由于这两次对绿色子像素G11中的像素电极上的数据电压的拉动均是向下拉动，其拉动方向相同，不能相互抵消，因此绿色子像素G11中的像素电极在被拉动后的电压要小于Vda11。
例如，绿色子像素G12中的像素电极与数据线DA5之间具有耦合电容Cpd21，绿色子像素G12中的像素电极与数据线DA6之间具有耦合电容Cpd22。数据线DA5上的数据电压一直为127灰阶值的正极性的数据电压Vda21，虽然具有耦合电容Cpd21，但是并不会将绿色子像素G12中的像素电极上已经充入的数据电压Vda11进行拉动。并且，数据线DA6上的数据电压一直为127灰阶值的负极性的数据电压Vda11，虽然耦合电容Cpd12的作用，但是也并不会将绿色子像素G12中的像素电极上已经充入的数据电压Vda11进行拉动。因此，绿色子像素G12中的像素电极上的电压可以比较稳定的处于数据电压Vda11。
综上，区域Q1中的绿色子像素G11中的像素电极在被拉动后的电压要小于Vda11。而区域Q5中绿色子像素G12中的像素电极上的电压可以比较稳定的处于数据电压Vda11。因此，区域Q1中的绿色子像素G11的亮度与区域Q5中绿色子像素G12的亮度不同，从而出现色偏的问题，因此显示效果。
本公开实施例提供了显示面板的驱动方法，如图5所示，可以包括如下步骤：
S100、获取当前显示帧的显示数据。示例性地，该显示数据包括每一个子像素一一对应的数据电压的数字电压形式。
S200、根据显示数据，对数据线输入数据电压，以使数据线电连接的子像素充入对应的数据电压。示例性地，根据显示数据，对每一条数据线输入数据电压，以使每一条数据线电连接的子像素充入对应的数据电压。针对一条数据线，对该数据线依次输入数据电压，以使该数据线电连接的子像素可 以输入相应的数据电压。
在本公开实施例中，将输入数据线上的数据电压分为多个电压组，每个电压组包括相邻的至少两个数据电压，同一电压组中的数据电压对应的极性相同；输入同一数据线的相邻两个电压组中的数据电压对应的极性不同；相邻两条数据线上对应的电压组极性不同。示例性地，每个电压组可以包括相邻的两个数据电压。结合图3与图6所示，以数据线DA2、DA3、DA5以及DA6为例，以“+”代表正极性，“-”代表负极性，数据线DA1上依次传输红色子像素R11对应的数据电压VR11-1、红色子像素R21对应的数据电压VR21-1、红色子像素R31对应的数据电压VR31-1、红色子像素R41对应的数据电压VR41-1、红色子像素R51对应的数据电压VR51-1以及红色子像素R61对应的数据电压VR61-1。其中，数据电压VR11-1和数据电压VR21-1可以作为一个电压组且对应负极性，数据电压VR31-1和数据电压VR41-1可以作为一个电压组且对应正极性，数据电压VR51-1和数据电压VR61-1可以作为一个电压组且对应负极性。
数据线DA2上依次传输绿色子像素G11对应的数据电压VG11-1、绿色子像素G21对应的数据电压VG21-1、绿色子像素G31对应的数据电压VG31-1、绿色子像素G41对应的数据电压VG41-1、绿色子像素G51对应的数据电压VG51-1以及绿色子像素G61对应的数据电压VG61-1。其中，数据电压VG11-1和数据电压VG21-1可以作为一个电压组且对应正极性，数据电压VG31-1和数据电压VG41-1可以作为一个电压组且对应负极性，数据电压VG51-1和数据电压VG61-1可以作为一个电压组且对应正极性。
数据线DA3上依次传输蓝色子像素B11对应的数据电压VB11-1、蓝色子像素B21对应的数据电压VB21-1、蓝色子像素B31对应的数据电压VB31-1、蓝色子像素B41对应的数据电压VB41-1、蓝色子像素B51对应的数据电压VB51-1以及蓝色子像素B61对应的数据电压VB61-1。其中，数据电压VB11-1和数据电压VB21-1可以作为一个电压组且对应负极性，数据电压VB31-1和数据电压VB41-1可以作为一个电压组且对应正极性，数据电压VB51-1和数 据电压VB61-1可以作为一个电压组且对应负极性。
数据线DA4上依次传输红色子像素R12对应的数据电压VR12-1、红色子像素R22对应的数据电压VR22-1、红色子像素R32对应的数据电压VR32-1、红色子像素R42对应的数据电压VR42-1、红色子像素R52对应的数据电压VR52-1以及红色子像素R62对应的数据电压VR62-1。其中，数据电压VR12-1和数据电压VR22-1可以作为一个电压组且对应正极性，数据电压VR32-1和数据电压VR42-1可以作为一个电压组且对应负极性，数据电压VR52-1和数据电压VR62-1可以作为一个电压组且对应正极性。
数据线DA5上依次传输绿色子像素G12对应的数据电压VG12-1、绿色子像素G22对应的数据电压VG22-1、绿色子像素G32对应的数据电压VG32-1、绿色子像素G42对应的数据电压VG42-1、绿色子像素G52对应的数据电压VG52-1以及绿色子像素G62对应的数据电压VG62-1。其中，数据电压VG12-1和数据电压VG22-1可以作为一个电压组且对应负极性，数据电压VG32-1和数据电压VG42-1可以作为一个电压组且对应正极性，数据电压VG52-1和数据电压VG62-1可以作为一个电压组且对应负极性。
数据线DA6上依次传输蓝色子像素B12对应的数据电压VB12-1、蓝色子像素B22对应的数据电压VB22-1、蓝色子像素B32对应的数据电压VB32-1、蓝色子像素B42对应的数据电压VB42-1、蓝色子像素B52对应的数据电压VB52-1以及蓝色子像素B62对应的数据电压VB62-1。其中，数据电压VB12-1和数据电压VB22-1可以作为一个电压组且对应正极性，数据电压VB32-1和数据电压VB42-1可以作为一个电压组且对应负极性，数据电压VB52-1和数据电压VB62-1可以作为一个电压组且对应正极性。
示例性地，每个电压组可以包括相邻的三个数据电压。结合图3与图7所示，以数据线DA2、DA3、DA5以及DA6为例，以“+”代表正极性，“-”代表负极性，数据线DA1上依次传输红色子像素R11对应的数据电压VR11-1、红色子像素R21对应的数据电压VR21-1、红色子像素R31对应的数据电压VR31-1、红色子像素R41对应的数据电压VR41-1、红色子像素R51对应的 数据电压VR51-1以及红色子像素R61对应的数据电压VR61-1。其中，数据电压VR11-1、数据电压VR21-1以及数据电压VR31-1可以作为一个电压组且对应负极性，数据电压VR41-1、数据电压VR51-1和数据电压VR61-1可以作为一个电压组且对应正极性。
数据线DA2上依次传输绿色子像素G11对应的数据电压VG11-1、绿色子像素G21对应的数据电压VG21-1、绿色子像素G31对应的数据电压VG31-1、绿色子像素G41对应的数据电压VG41-1、绿色子像素G51对应的数据电压VG51-1以及绿色子像素G61对应的数据电压VG61-1。其中，数据电压VG11-1、数据电压VG21-1以及数据电压VG31-1可以作为一个电压组且对应正极性，数据电压VG41-1、数据电压VG51-1和数据电压VG61-1可以作为一个电压组且对应负极性。
数据线DA3上依次传输蓝色子像素B11对应的数据电压VB11-1、蓝色子像素B21对应的数据电压VB21-1、蓝色子像素B31对应的数据电压VB31-1、蓝色子像素B41对应的数据电压VB41-1、蓝色子像素B51对应的数据电压VB51-1以及蓝色子像素B61对应的数据电压VB61-1。其中，数据电压VB11-1、数据电压VB21-1以及数据电压VB31-1可以作为一个电压组且对应负极性，数据电压VB41-1、数据电压VB51-1和数据电压VB61-1可以作为一个电压组且对应正极性。
数据线DA4上依次传输红色子像素R12对应的数据电压VR12-1、红色子像素R22对应的数据电压VR22-1、红色子像素R32对应的数据电压VR32-1、红色子像素R42对应的数据电压VR42-1、红色子像素R52对应的数据电压VR52-1以及红色子像素R62对应的数据电压VR62-1。其中，数据电压VR12-1、数据电压VR22-1以及数据电压VR32-1可以作为一个电压组且对应正极性，数据电压VR42-1、数据电压VR52-1和数据电压VR62-1可以作为一个电压组且对应负极性。
数据线DA5上依次传输绿色子像素G12对应的数据电压VG12-1、绿色子像素G22对应的数据电压VG22-1、绿色子像素G32对应的数据电压VG32-1、 绿色子像素G42对应的数据电压VG42-1、绿色子像素G52对应的数据电压VG52-1以及绿色子像素G62对应的数据电压VG62-1。其中，数据电压VG12-1、数据电压VG22-1以及数据电压VG32-1可以作为一个电压组且对应负极性，数据电压VG42-1、数据电压VG52-1和数据电压VG62-1可以作为一个电压组且对应正极性。
数据线DA6上依次传输蓝色子像素B12对应的数据电压VB12-1、蓝色子像素B22对应的数据电压VB22-1、蓝色子像素B32对应的数据电压VB32-1、蓝色子像素B42对应的数据电压VB42-1、蓝色子像素B52对应的数据电压VB52-1以及蓝色子像素B62对应的数据电压VB62-1。其中，数据电压VB12-1、数据电压VB22-1以及数据电压VB32-1可以作为一个电压组且对应正极性，数据电压VB42-1、数据电压VB52-1和数据电压VB62-1可以作为一个电压组且对应负极性。
在实际应用中，每个电压组也可以包括相邻的四个、五个或其他数量的数据电压，其可以根据实际应用的需求进行确定，在此不作限定。
在本公开实施例中，相邻两条数据线上对应的电压组极性不同，指的可以是同时输入这两条数据线的数据电压对应的极性不同。例如，数据线DA1上的数据电压VR11-1、数据线DA2上的数据电压VG11-1、数据线DA3上的数据电压VB11-1、数据线DA4上的数据电压VR12-1、数据线DA5上的数据电压VG12-1、以及数据线DA6上的数据电压VB12-1同时输入。之后，据线DA1上的数据电压VR21-1、数据线DA2上的数据电压VG21-1、数据线DA3上的数据电压VB21-1、据线DA4上的数据电压VR22-1、数据线DA5上的数据电压VG22-1、以及数据线DA6上的数据电压VB22-1同时输入。之后，据线DA1上的数据电压VR31-1、数据线DA2上的数据电压VG31-1、数据线DA3上的数据电压VB31-1、据线DA4上的数据电压VR32-1、数据线DA5上的数据电压VG32-1、以及数据线DA6上的数据电压VB32-1同时输入。之后，据线DA1上的数据电压VR41-1、数据线DA2上的数据电压VG41-1、数据线DA3上的数据电压VB41-1、据线DA4上的数据电压VR42-1、数据线 DA5上的数据电压VG42-1、以及数据线DA6上的数据电压VB42-1同时输入。之后，据线DA1上的数据电压VR51-1、数据线DA2上的数据电压VG51-1、数据线DA3上的数据电压VB51-1、据线DA4上的数据电压VR52-1、数据线DA5上的数据电压VG52-1、以及数据线DA6上的数据电压VB52-1同时输入。之后，据线DA1上的数据电压VR61-1、数据线DA2上的数据电压VG61-1、数据线DA3上的数据电压VB61-1、据线DA4上的数据电压VR62-1、数据线DA5上的数据电压VG62-1、以及数据线DA6上的数据电压VB62-1同时输入。
示例性地，结合图8所示，VDA2代表数据线DA2上传输的数据电压，VDA3代表数据线DA3上传输的数据电压，VDA5代表数据线DA5上传输的数据电压，VDA6代表数据线DA6上传输的数据电压。VG11代表绿色子像素G11中的像素电极上实际的电压值，VB12代表蓝色子像素B12中的像素电极上实际的电压值。通过将数据线DA5上的负极性的电压组和正极性的电压组交替输入，以及将数据线DA6上的正极性的电压组和负极性的电压组交替输入，可以使区域Q5中的绿色子像素G12充入的数据电压可以在向下拉动和向上拉动之间相互抵消，从而可以使像素电极上的电压可以比较稳定，进而可以使绿色子像素G12的亮度比较稳定。以及，通过将数据线DA2上的负极性的电压组和正极性的电压组交替输入，以及将数据线DA3上的正极性的电压组和负极性的电压组交替输入，可以使区域Q1中的绿色子像素G11充入的数据电压可以在向下拉动和向上拉动之间交替变化，从而可以使绿色子像素G11的亮度每经过一个电压组出现交替互补色闪动，这样在宏观上可以表现为无色偏，从而改善色偏现象。
在本公开实施例中，时序控制器200可以获取当前显示帧F0的显示数据，并将当前显示帧对应的显示数据以数字电压的形式进行存储。时序控制器200可以基于将输入数据线上的数据电压分为多个电压组，每个电压组包括相邻的至少两个数据电压，同一电压组中的数据电压对应的极性相同；输入同一数据线的相邻两个电压组中的数据电压对应的极性不同；相邻两条数据线上对应的电压组极性不同的规则，生成极性翻转信号POL1(如图10中所示)。 时序控制器200将数字信号形式的显示数据和生成的极性翻转信号POL1发送给源极驱动电路120，源极驱动电路120可以接收时序控制器200发送的显示数据和极性翻转信号POL1，从而可以根据显示数据和极性翻转信号以及数据加载信号TP，对数据线输入数据电压，以使数据线电连接的子像素充入对应的数据电压。示例性地，源极驱动电路120可以响应于极性翻转信号POL1的下降沿对加载到数据线上的数据电压的极性进行翻转，以及响应于数据加载信号TP的下降沿对数据线加载数据电压。当然，源极驱动电路120也可以响应于极性翻转信号POL1的上述沿对加载到数据线上的数据电压的极性进行翻转。源极驱动电路120也可以响应于数据加载信号TP的上升沿对数据线加载数据电压。这些可以根据实际应用的需求进行确定，在此不作限定。
在本公开实施例中，结合图2与图9以及图10所示，源极驱动电路120可以包括：数据处理电路121以及多个电压输出电路(如122-1、122-2)；其中，每一条数据线一一对应电连接电压输出电路(如数据线DA1电连接电压输出电路122-1，数据线DA2电连接电压输出电路122-2)。并且，数据处理电路121可以接收显示数据，并根据显示数据，对各电压输出电路输出对应的显示数据。也可以对显示数据进行优化处理，并将优化处理后的显示数据输出给各电压输出电路。并且，电压输出电路可以接收极性翻转信号POL1和数据处理电路121输出的显示数据，根据极性翻转信号和数据处理电路121输出的显示数据，对电连接的数据线依次输入数据电压，以使数据线电连接的子像素充入对应的数据电压。例如，数据处理电路121可以根据显示数据产生数据加载信号TP，并将数据加载信号TP、极性翻转信号POL1以及与数据线DA1电连接的子像素对应的显示数据输出给电压输出电路122-1，电压输出电路122-1可以通过数据加载信号TP来控制显示数据加载于数据线DA1上，以及通过极性翻转信号POL1来控制显示数据对应的极性翻转。以及，数据处理电路121可以根据显示数据产生数据加载信号TP，并将数据加载信号TP、极性翻转信号POL1以及与数据线DA2电连接的子像素对应的显示数据输出给电压输出电路122-2，电压输出电路122-2可以通过数据加载信号TP 来控制显示数据加载于数据线DA2上，以及通过极性翻转信号POL1来控制显示数据对应的极性翻转。
在本公开实施例中，结合图2与图9所示，电压输出电路可以包括第一输出电路123和第二输出电路124；其中，每一条数据线一一对应电连接第一输出电路123和第二输出电路124；并且，第一输出电路123被配置为根据极性翻转信号和显示数据，对电连接的数据线输入对应正极性的数据电压。以及，第二输出电路124被配置为根据极性翻转信号和显示数据，对电连接的数据线输入对应负极性的数据电压。例如，电压输出电路122-1包括第一输出电路123和第二输出电路124，该第一输出电路123可以根据极性翻转信号POL1和显示数据，对电连接的数据线DA1输入对应正极性的数据电压。并且，该第二输出电路124可以根据极性翻转信号POL1和显示数据，对电连接的数据线DA1输入对应负极性的数据电压。
在本公开实施例中，如图9所示，第一输出电路123可以包括：第一数模转换电路DAC-P和第二放大器OP-P；其中，第一数模转换电路DAC-P电连接于第二电源电压和中点电压HAVDD之间。并且，第一数模转换电路DAC-P被配置为接收极性翻转信号和显示数据，根据极性翻转信号，将显示数据进行数模转换后产生对应正极性的数据电压并输出。以及，第二放大器OP-P被配置为接收第一数模转换电路DAC-P输出的数据电压，并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
在本公开实施例中，如图9所示，第二输出电路124可以包括：第二数模转换电路DAC-N和第二放大器OP-N；其中，第二数模转换电路DAC-N电连接于第一电源电压和中点电压HAVDD之间。并且，第二数模转换电路DAC-N被配置为接收极性翻转信号和显示数据，根据极性翻转信号，将显示数据进行数模转换后产生对应负极性的数据电压并输出。以及，第二放大器OP-N被配置为接收第二数模转换电路DAC-N输出的数据电压，并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
下面以数据线DA1和DA2及其电连接的子像素为例，结合图3、图9与 图10对本公开实施例提供的显示面板的工作过程进行说明。ga1代表栅线GA1上加载的信号，ga2代表栅线GA2上加载的信号，ga3代表栅线GA3上加载的信号，ga4代表栅线GA4上加载的信号，ga5代表栅线GA5上加载的信号，ga6代表栅线GA6上加载的信号。da1代表数据线DA1上加载的数据电压，da2代表数据线DA2上加载的数据电压。并且，信号ga1～ga6中的高电平可以作为栅极开启信号，以控制子像素中的晶体管导通。可以依次对栅线GA1～GA6加载栅极开启信号。
在显示帧F0中，栅线GA1上的信号ga1输出高电平的栅极开启信号时，红色子像素R11和绿色子像素G11中的晶体管导通。且在信号ga1的高电平对应的T1时间段中，数据处理电路121将红色子像素R11对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将红色子像素R11对应的显示数据经过数模转换为模拟电压的数据电压Vr11，通过数据加载信号TP来控制数据电压Vr11加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr11的极性为负极性。数据电压Vr11再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的负极性的数据电压Vr11，以使红色子像素R11输入数据电压Vr11。并且，数据处理电路121将绿色子像素G11对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G11对应的显示数据经过数模转换为模拟电压的数据电压Vg11，通过数据加载信号TP来控制数据电压Vg11加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg11的极性为正极性。数据电压Vg11再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的正极性的数据电压Vg11，以使绿色子像素G11输入数据电压Vg11。以及，在T1时间段中，栅线GA2上的信号ga2输出高电平的栅极开启信号，红色子像素R21和绿色子像素G21中的晶体管导通。数据电压Vr11同时输入到红色子像素R21中，以对红色子像素R21进行预充电。并且，数 据电压Vg11同时输入到绿色子像素G21中，以对绿色子像素G21进行预充电。以及，在T1时间段中，栅线GA3上的信号ga3输出高电平的栅极开启信号，红色子像素R31和绿色子像素G31中的晶体管导通。数据电压Vr11同时输入到红色子像素R31中，以对红色子像素R31进行预充电。并且，数据电压Vg11同时输入到绿色子像素G31中，以对绿色子像素G31进行预充电。
在信号ga2的高电平对应的T2时间段中，数据处理电路121将红色子像素R21对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将红色子像素R21对应的显示数据经过数模转换为模拟电压的数据电压Vr21，通过数据加载信号TP来控制数据电压Vr21加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr21的极性为负极性。数据电压Vr21再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的负极性的数据电压Vr21，以使红色子像素R21充入数据电压Vr21。并且，数据处理电路121将绿色子像素G21对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G21对应的显示数据经过数模转换为模拟电压的数据电压Vg21，通过数据加载信号TP来控制数据电压Vg21加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg21的极性为正极性。数据电压Vg21再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的正极性的数据电压Vg21，以使绿色子像素G21充入数据电压Vg21。以及，在T2时间段中，栅线GA3上的信号ga3输出高电平的栅极开启信号，红色子像素R31和绿色子像素G31中的晶体管导通。数据电压Vr21同时输入到红色子像素R31中，以对红色子像素R31进行预充电。并且，数据电压Vg21同时输入到绿色子像素G31中，以对绿色子像素G31进行预充电。以及，在T2时间段中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41和绿色子像素G41中的晶体管导通。 数据电压Vr21同时输入到红色子像素R41中，以对红色子像素R41进行预充电。并且，数据电压Vg21同时输入到绿色子像素G41中，以对绿色子像素G41进行预充电。
在信号ga3的高电平对应的T3时间段中，数据处理电路121将红色子像素R31对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将红色子像素R31对应的显示数据经过数模转换为模拟电压的数据电压Vr31，通过数据加载信号TP来控制数据电压Vr31加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr31的极性为正极性。数据电压Vr31再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的正极性的数据电压Vr31，以使红色子像素R31充入数据电压Vr31。并且，数据处理电路121将绿色子像素G31对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G31对应的显示数据经过数模转换为模拟电压的数据电压Vg31，通过数据加载信号TP来控制数据电压Vg31加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg31的极性为负极性。数据电压Vg31再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的负极性的数据电压Vg31，以使绿色子像素G31充入数据电压Vg31。以及，在T3时间段中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41和绿色子像素G41中的晶体管导通。数据电压Vr31同时输入到红色子像素R41中，以对红色子像素R41进行预充电。并且，数据电压Vg31同时输入到绿色子像素G41中，以对绿色子像素G41进行预充电。以及，在T3时间段中，栅线GA5上的信号ga5输出高电平的栅极开启信号，红色子像素R51和绿色子像素G51中的晶体管导通。数据电压Vr31同时输入到红色子像素R51中，以对红色子像素R51进行预充电。并且，数据电压Vg31同时输入到绿色子像素G51中，以对绿色子像素G51进行预充电。
在信号ga4的高电平对应的T4时间段中，数据处理电路121将红色子像素R41对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将红色子像素R41对应的显示数据经过数模转换为模拟电压的数据电压Vr41，通过数据加载信号TP来控制数据电压Vr41加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr41的极性为正极性。数据电压Vr41再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的正极性的数据电压Vr41，以使红色子像素R41充入数据电压Vr41。并且，数据处理电路121将绿色子像素G41对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G41对应的显示数据经过数模转换为模拟电压的数据电压Vg41，通过数据加载信号TP来控制数据电压Vg41加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg41的极性为负极性。数据电压Vg41再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的负极性的数据电压Vg41，以使绿色子像素G41充入数据电压Vg41。以及，在T4时间段中，栅线GA5上的信号ga5输出高电平的栅极开启信号，红色子像素R51和绿色子像素G51中的晶体管导通。数据电压Vr41同时输入到红色子像素R51中，以对红色子像素R51进行预充电。并且，数据电压Vg41同时输入到绿色子像素G51中，以对绿色子像素G51进行预充电。以及，在T4时间段中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61和绿色子像素G61中的晶体管导通。数据电压Vr41同时输入到红色子像素R61中，以对红色子像素R61进行预充电。并且，数据电压Vg41同时输入到绿色子像素G61中，以对绿色子像素G61进行预充电。
在信号ga5的高电平对应的T5时间段中，数据处理电路121将红色子像素R51对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P 可以将红色子像素R51对应的显示数据经过数模转换为模拟电压的数据电压Vr51，通过数据加载信号TP来控制数据电压Vr51加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr51的极性为负极性。数据电压Vr51再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的负极性的数据电压Vr51，以使红色子像素R51充入数据电压Vr51。并且，数据处理电路121将绿色子像素G51对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G51对应的显示数据经过数模转换为模拟电压的数据电压Vg51，通过数据加载信号TP来控制数据电压Vg51加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg51的极性为正极性。数据电压Vg51再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的正极性的数据电压Vg51，以使绿色子像素G51充入数据电压Vg51。以及，在T5时间段中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61和绿色子像素G61中的晶体管导通。数据电压Vr51同时输入到红色子像素R51中，以对红色子像素R51进行预充电。并且，数据电压Vg51同时输入到绿色子像素G61中，以对绿色子像素G61进行预充电。
在信号ga6的高电平对应的T6时间段中，数据处理电路121将红色子像素R61对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出电路122-1中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将红色子像素R61对应的显示数据经过数模转换为模拟电压的数据电压Vr61，通过数据加载信号TP来控制数据电压Vr61加载于数据线DA1上，以及通过极性翻转信号POL1来控制数据电压Vr61的极性为负极性。数据电压Vr61再经过第二放大器OP-P的放大处理后，对数据线DA1加载对应显示数据的负极性的数据电压Vr61，以使红色子像素R61充入数据电压Vr61。并对下一个红色子像素进行预充电。并且，数据处理电路121将绿色子像素G61对应的显示数据、数据加载信号TP以及极性翻转信号POL1输出给电压输出 电路122-2中的第一数模转换电路DAC-P，第一数模转换电路DAC-P可以将绿色子像素G61对应的显示数据经过数模转换为模拟电压的数据电压Vg61，通过数据加载信号TP来控制数据电压Vg61加载于数据线DA2上，以及通过极性翻转信号POL1来控制数据电压Vg61的极性为正极性。数据电压Vg61再经过第二放大器OP-P的放大处理后，对数据线DA2加载对应显示数据的正极性的数据电压Vg61，以使绿色子像素G61充入数据电压Vg61。并对下一个绿色子像素进行预充电。
其余子像素的实施方式依次类推，直至整个显示面板中的子像素完成充入数据电压，在此不作赘述。
在本公开实施例中，在对数据线加载完一行子像素对应的数据电压后，可以将相邻两条数据线短接，以释放电荷。在相邻的两条数据线上的数据电压对称时，这两条数据线短接释放电荷后，会使这两条数据线上的电压变化为公共电极电压Vcom。在数据线下一次加载数据电压时，会从Vcom变化到所要加载的数据电压，以使数据线可以充电均匀。例如，结合图10与图11a所示，在T1阶段中，数据线DA1上加载的数据电压Vr11为0.6V，数据线DA2上加载的数据电压Vg11为16V时，在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的公共电极电压Vcom。在T2阶段中，数据线DA1上加载的数据电压Vr21为0.6V，数据线DA2上加载的数据电压Vg21为16V时，可以使数据线DA1从Vcom变化为0.6V，使数据线DA2从Vcom变化为16V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的公共电极电压Vcom。在T3阶段中，数据线DA1上加载的数据电压Vr31为16V，数据线DA2上加载的数据电压Vg31为0.6V时，可以使数据线DA1从Vcom变化为16V，使数据线DA2从Vcom变化为0.6V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的 公共电极电压Vcom。在T4阶段中，数据线DA1上加载的数据电压Vr41为16V，数据线DA2上加载的数据电压Vg41为0.6V时，可以使数据线DA1从Vcom变化为16V，使数据线DA2从Vcom变化为0.6V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的公共电极电压Vcom。在T5阶段中，数据线DA1上加载的数据电压Vr51为0.6V，数据线DA2上加载的数据电压Vg51为16V时，可以使数据线DA1从Vcom变化为0.6V，使数据线DA2从Vcom变化为16V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的公共电极电压Vcom。在T6阶段中，数据线DA1上加载的数据电压Vr61为0.6V，数据线DA2上加载的数据电压Vg61为16V时，可以使数据线DA1从Vcom变化为0.6V，使数据线DA2从Vcom变化为16V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为8.3V的公共电极电压Vcom。
在本公开实施例中，若相邻的两条数据线上加载的数据电压不对称时，这两条数据线短接释放电荷后，会使这两条数据线上的电压偏离公共电极电压Vcom。在数据线下一次加载数据电压时，会从偏离Vcom的电压处变化到所要加载的数据电压，从而导致数据线充电不均匀。例如，结合图10与图11b所示，在T1阶段中，数据线DA1上加载的数据电压Vr11为0.6V，数据线DA2上加载的数据电压Vg11为12V时，在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为6.3V，小于公共电极电压Vcom。在T2阶段中，数据线DA1上加载的数据电压Vr21为0.6V，数据线DA2上加载的数据电压Vg21为12V时，可以使数据线DA1从小于Vcom的6.3V变化为0.6V，使数据线DA2从小于Vcom的6.3V变化为12V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使 数据线DA1和数据线DA2上的电压为6.3V，小于公共电极电压Vcom。在T3阶段中，数据线DA1上加载的数据电压Vr31为16V，数据线DA2上加载的数据电压Vg31为4.6V时，可以使数据线DA1从小于Vcom的6.3V变化为16V，使数据线DA2从小于Vcom的6.3V变化为4.6V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为10.3V，大于公共电极电压Vcom。在T4阶段中，数据线DA1上加载的数据电压Vr31为16V，数据线DA2上加载的数据电压Vg31为4.6V时，可以使数据线DA1从大于Vcom的10.3V变化为16V，使数据线DA2从大于Vcom的10.3V变化为4.6V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为10.3V，大于公共电极电压Vcom。在T5阶段中，数据线DA1上加载的数据电压Vr21为0.6V，数据线DA2上加载的数据电压Vg21为12V时，可以使数据线DA1从大于Vcom的10.3V变化为0.6V，使数据线DA2从大于Vcom的10.3V变化为12V。在数据线DA1和数据线DA2加载数据电压后，将数据线DA1和数据线DA2进行短接，释放电荷，可以使数据线DA1和数据线DA2上的电压为6.3V，小于公共电极电压Vcom。在T6阶段中，数据线DA1上加载的数据电压Vr21为0.6V，数据线DA2上加载的数据电压Vg21为12V时，可以使数据线DA1从小于Vcom的6.3V变化为0.6V，使数据线DA2从小于Vcom的6.3V变化为12V。这样导致数据线DA1和数据线DA2充电时的基准点有时大于Vcom，有时小于Vcom，造成充电不均匀的问题。
为了解决该问题，本公开实施例提供的驱动方法还可以包括：在对数据线输入数据电压之前输入基准电压。这样可以不需要将相邻的数据线进行短接，即可将数据线上的电荷进行释放。并且，可以使数据线上加载的各数据电压均从基准电压这个基准点上进行充电，以提高充电均匀性。示例性地，结合图12所示，在T1阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T1阶段中，数据线DA1上加载的数据电 压Vr11，以及数据线DA2上加载的数据电压Vg11。在T2阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T2阶段中，数据线DA1上加载的数据电压Vr21，以及数据线DA2上加载的数据电压Vg21。在T3阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T3阶段中，数据线DA1上加载的数据电压Vr31，以及数据线DA2上加载的数据电压Vg31。其余同理，在此不作赘述。
在本公开实施例中，基准电压为第一电源电压和第二电源电压之间的电压。这样可以使数据线上加载的各数据电压均从基准电压这个基准点上进行充电，以提高充电均匀性。
在本公开实施例中，基准电压为第一电源电压和第二电源电压之间的中点电压HAVDD。由于中点电压HAVDD可能会等于Vcom，中点电压HAVDD有可能与Vcom相差较少，这样使数据电压均从中点电压HAVDD开始充电，进一步提高充电均匀性。
在本公开实施例中，如图13所示，源极驱动电路还可以包括：第一电荷共享电路125；其中，第一电荷共享电路125被配置为接收第一基准控制信号VS1，并在第一基准控制信号VS1的控制下，在对电连接的数据线输入每一个数据电压之前输入基准电压。示例性地，第一电荷共享电路125可以包括第一开关晶体管M1；其中，第一开关晶体管M1的栅极被配置为接收第一基准控制信号VS1，第一开关晶体管M1的第一极被配置为接收基准电压，第一开关晶体管M1的第二极与数据线电连接。需要说明的是，第一开关晶体管M1可以为N型晶体管或P型晶体管，并且第一极可以为源极，第二极可以为漏极，或者，第一极可以为漏极，第二极可以为源极。
在本公开实施例中，基准电压受第一基准控制信号VS1的上升沿触发，输入到对应的数据线上。并且，数据电压受第一基准控制信号VS1的下降沿触发，输入到对应的数据线上。例如，第一基准控制信号VS1可以为数据加载信号TP。结合图12与图13所示，在T1阶段之前，受数据加载信号TP的上升沿触发，第一开关晶体管M1导通，对数据线DA1输入基准电压VG。 在T1阶段中，受数据加载信号TP下降沿触发，第一开关晶体管M1截止，数据线DA1上加载的数据电压Vr11。在T2阶段之前，受数据加载信号TP的上升沿触发，第一开关晶体管M1导通，对数据线DA1输入基准电压VG。在T2阶段中，受数据加载信号TP的下降沿触发，第一开关晶体管M1截止，数据线DA1上加载的数据电压Vr21。在T3阶段之前，受数据加载信号TP的上升沿触发，第一开关晶体管M1导通，对数据线DA1输入基准电压VG。在T3阶段中，受数据加载信号TP的下降沿触发，第一开关晶体管M1截止，数据线DA1上加载的数据电压Vr31。其余同理，在此不作赘述。
在本公开实施例中，基准电压受第一基准控制信号VS1的下降沿触发，输入到对应的数据线上。并且，数据电压受第一基准控制信号VS1的上升沿触发，输入到对应的数据线上。其实施方式大致与上述相同，在此不作赘述。
本公开实施例提供了另一些显示面板的驱动方法的实施例，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，在对数据线输入电压组的第一个数据电压之前输入基准电压。这样可以不需要将相邻的数据线进行短接，即可将数据线上的电荷进行释放。并且，可以使数据线上加载的各电压组均从基准电压这个基准点上进行充电，以提高充电均匀性。示例性地，结合图14所示，在T1阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T1阶段中，数据线DA1上加载的数据电压Vr11，以及数据线DA2上加载的数据电压Vg11。在T2阶段中，数据线DA1上加载的数据电压Vr21，以及数据线DA2上加载的数据电压Vg21。在T3阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T3阶段中，数据线DA1上加载的数据电压Vr31，以及数据线DA2上加载的数据电压Vg31。其余同理，在此不作赘述。
示例性地，以电压组可以包括相邻的两个数据电压为例，针对数据线DA1，数据电压VR11-1作为由数据电压VR11-1和数据电压VR21-1组成的电压组 中的第一个数据电压。数据电压VR31-1作为由数据电压VR31-1和数据电压VR41-1组成的电压组中的第一个数据电压。数据电压VR51-1作为由数据电压VR51-1和数据电压VR61-1组成的电压组中的第一个数据电压。针对数据线DA2，数据电压VG11-1作为由数据电压VG11-1和数据电压VG21-1组成的电压组中的第一个数据电压。数据电压VG31-1作为由数据电压VG31-1和数据电压VG41-1组成的电压组中的第一个数据电压。数据电压VG51-1作为由数据电压VG51-1和数据电压VG61-1组成的电压组中的第一个数据电压。
示例性地，以电压组可以包括相邻的三个数据电压为例，针对数据线DA1，数据电压VR11-1作为由数据电压VR11-1、数据电压VR21-1以及数据电压VR31-1组成的电压组中的第一个数据电压。数据电压VR41-1作为由数据电压VR41-1、数据电压VR51-1和数据电压VR61-1组成的电压组中的第一个数据电压。针对数据线DA2，数据电压VG11-1作为由数据电压VG11-1、数据电压VG21-1以及数据电压VG31-1组成的电压组中的第一个数据电压。数据电压VG41-1作为由数据电压VG41-1、数据电压VG51-1和数据电压VG61-1组成的电压组中的第一个数据电压。
在本公开实施例中，如图15所示，源极驱动电路还包括：第二电荷共享电路126；其中，第二电荷共享电路126被配置为接收第二基准控制信号VS2，并在第二基准控制信号VS2的控制下，在对每一条数据线输入每一个电压组的第一个数据电压之前输入基准电压。示例性地，第二电荷共享电路126包括第二开关晶体管M2；其中，第二开关晶体管M2的栅极被配置为接收第二基准控制信号VS2，第二开关晶体管M2的第一极被配置为接收基准电压，第二开关晶体管M2的第二极与数据线电连接。需要说明的是，第二开关晶体管M2，并且第一极可以为源极，第二极可以为漏极，或者，第一极可以为漏极，第二极可以为源极。
在本公开实施例中，基准电压受第二基准控制信号VS2的上升沿触发，输入到对应的数据线上。并且，数据电压受数据加载信号TP的下降沿触发，输入到对应的数据线上。例如，第二基准控制信号VS2可以为极性翻转信号 POL1。结合图14与图15所示，在T1阶段之前，受极性翻转信号POL1的上升沿触发，第二开关晶体管M2导通，对数据线DA1输入基准电压VG。在T1阶段中，受极性翻转信号POL1的上升沿触发，第一开关晶体管M1截止，受数据加载信号TP下降沿触发，数据线DA1上加载的数据电压Vr11。在T2阶段中，受数据加载信号TP的下降沿触发，数据线DA1上加载的数据电压Vr21。在T3阶段之前，受极性翻转信号POL1的上升沿触发，第一开关晶体管M1导通，对数据线DA1输入基准电压VG。在T3阶段中，受极性翻转信号POL1的上升沿触发，第一开关晶体管M1截止，受数据加载信号TP的下降沿触发，数据线DA1上加载的数据电压Vr31。其余同理，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法的实施例，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
结合图10所示，以数据线DA1为例，在T1阶段中，数据线DA1加载负极性的Vr11。在T2阶段中，数据线DA1加载负极性的Vr21。在T3阶段中，数据线DA1加载正极性的Vr31。在T4阶段中，数据线DA1加载正极性的Vr41。在T5阶段中，数据线DA1加载负极性的Vr51。在T6阶段中，数据线DA1加载负极性的Vr61。其中，红色子像素R31预充了电压Vr21，之后需要充入Vr31。在红色子像素R31由Vr21切换到Vr31时，虽然预充了Vr21，但是由于是负极性的Vr21切换为正极性的Vr31，电压从低变高，变化太大，红色子像素R31要充电Vr31会比较困难。红色子像素R41预充了电压Vr31，之后需要充入Vr41。在红色子像素R41由Vr31切换到Vr41时，预充了Vr31，但是由于是正极性的Vr31切换为正极性的Vr41，电压变化不大，红色子像素R41要充电Vr41会比较容易。而红色子像素R51预充了电压Vr41，之后需要充入Vr51。在红色子像素R51由Vr41切换到Vr51时，虽然预充了Vr41，但是由于是正极性的Vr41切换为负极性的Vr51，电压从高变低，变化太大，红色子像素R51要充电Vr51会比较困难。红色子像素R61预充了电压Vr51，之后需要充入Vr61。在红色子像素R61由Vr51切换到Vr61时，预充了Vr51， 但是由于是负极性的Vr51切换为负极性的Vr61，电压变化不大，红色子像素R61要充电Vr61会比较容易。这样导致红色子像素R31的充电率小于红色子像素R41的充电率，红色子像素R51的充电率小于红色子像素R61的充电率。从而导致子像素的充电率不均匀。
为了提高子像素的充电率的均一性，在本公开实施例中，驱动方法还可以包括：在对数据线输入电压组的第一个数据电压时，在数据线上叠加补偿电压。其中，在第一个数据电压对应正极性时，第一个数据电压叠加补偿电压后的电压值大于第一个数据电压，以及，在第一个数据电压对应负极性时，第一个数据电压叠加补偿电压后的电压值小于第一个数据电压。这样可以通过过驱动的方式，提高子像素的充电率的均一性。
在本公开实施例中，不同电压组中，对应同一极性的第一数据电压叠加的补偿电压相同。例如，不同电压组中，对应正极性的第一数据电压叠加的补偿电压相同。不同电压组中，对应负极性的第一数据电压叠加的补偿电压相同。进一步地，每一个电压组对应的补偿电压的绝对值相同。
示例性地，结合图16所示，在T1阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T1阶段中，数据线DA1上加载的数据电压Vr11和补偿电压VC1，以及数据线DA2上加载的数据电压Vg11和补偿电压VC2。在T2阶段中，数据线DA1上加载的数据电压Vr21，以及数据线DA2上加载的数据电压Vg21。在T3阶段之前，对数据线DA1输入基准电压VG，以及对数据线DA2输入基准电压VG。在T3阶段中，数据线DA1上加载的数据电压Vr31和补偿电压VC2，以及数据线DA2上加载的数据电压Vg31和补偿电压VC1。并且，Vr11+VC1<Vr11，Vg11+VC2>Vg11，Vr31+VC2>Vr31，Vg31+VC1<Vg31，|VC1|＝|VC2|。其余同理，在此不作赘述。
本公开实施例提供了又一些显示面板的驱动方法的实施例，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
为了提高子像素的充电率的均一性，在本公开实施例中，结合图17所示，数据线加载数据电压的维持时长与数据电压对应的子像素打开的维持时长之间具有交叠时长，该交叠时长为子像素的充电时长。数据线加载数据电压的维持时长与数据电压对应的子像素打开的维持时长具有非交叠时长。若非交叠时长变长，则交叠时长缩短，即子像素的充电时长缩短，会降低子像素的充电率。若非交叠时长变短，则交叠时长增加，即子像素的充电时长增加，会提高子像素的充电率。在具体实施时，可以使同一电压组中，加载到数据线上的第一个数据电压具有第一非交叠时长，加载到数据线上的其余数据电压具有第二非交叠时长。通过使第一非交叠时长小于第二非交叠时长。可以提高第一个数据电压对应的子像素的充电率，降低其余数据电压对应的子像素的充电率，从而尽可能的使不同的子像素的充电率相互趋近，甚至相同，进而提高子像素的充电率的均一性。
示例性地，可以使各电压组对应的第一非交叠时长相同，使各电压组对应的第二非交叠时长相同。结合图17所示，Vr11和Vr21作为一个电压组时，Vr11作为该电压组中的第一个数据电压，Vr12作为该电压组中的其余数据电压，则Vr11加载到数据线DA1上的维持时长t11与红色子像素R11对应的栅极开启信号的维持时长t21具有第一非交叠时长GOE1。Vr21加载到数据线DA1上的维持时长t12与红色子像素R21对应的栅极开启信号的维持时长t22具有第二非交叠时长GOE2。并且，GOE1<GOE2，t11＝t12，t21＝t22。以及，Vg11和Vg21作为一个电压组时，Vg11作为该电压组中的第一个数据电压，Vg12作为该电压组中的其余数据电压，则Vg11加载到数据线DA2上的维持时长t31与绿色子像素G11对应的栅极开启信号的维持时长t21具有第一非交叠时长GOE1。Vg21加载到数据线DA2上的维持时长t32与绿色子像素G21对应的栅极开启信号的维持时长t22具有第二非交叠时长GOE2。并且，GOE1<GOE2，t31＝t32。
在本公开实施例中，也可以使对应正极性的第一个数据电压的第一非交叠时长小于对应负极性的第一个数据电压的第一非交叠时长。在具体应用中， 由正极性的数据电压切换为负极性的数据电压，相当于放电，会比由负极性的数据电压切换为正极性的数据电压快，因此，通过使正极性对应的第一个数据电压的第一非交叠时长小于负极性对应的第一个数据电压的第一非交叠时长，这样可以使正极性对应的数据电压的充电率可以大于负极性对应的数据电压的充电率。从而进一步使亮度均匀。
示例性地，结合图18所示，Vr11和Vr21作为一个电压组时，Vr11作为该电压组中的第一个数据电压，Vr12作为该电压组中的其余数据电压，则Vr11加载到数据线DA1上的维持时长t11与红色子像素R11对应的栅极开启信号的维持时长t21具有第一非交叠时长GOE11。Vg11和Vg21作为一个电压组时，Vg11作为该电压组中的第一个数据电压，Vg12作为该电压组中的其余数据电压，则Vg11加载到数据线DA2上的维持时长t31与绿色子像素G11对应的栅极开启信号的维持时长t21具有第一非交叠时长GOE21。并且，GOE11<GOE21，t11＝t31，t21＝t22。这样可以使正极性对应的数据电压的充电率可以大于负极性对应的数据电压的充电率。从而进一步使亮度均匀。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (21)

  1. 一种显示面板的驱动方法，包括：
    获取当前显示帧的显示数据；
    根据所述显示数据，对数据线输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压；其中，将输入所述数据线上的数据电压分为多个电压组，每个所述电压组包括相邻的至少两个数据电压，同一所述电压组中的数据电压对应的极性相同；输入同一所述数据线的相邻两个所述电压组中的数据电压对应的极性不同；相邻两条所述数据线上对应的所述电压组极性不同。
  2. 如权利要求1所述的驱动方法，其中，所述驱动方法还包括：
    在对所述数据线输入所述数据电压之前输入基准电压。
  3. 如权利要求1所述的驱动方法，其中，所述驱动方法还包括：
    在对所述数据线输入所述电压组的第一个数据电压之前输入所述基准电压。
  4. 如权利要求2或3所述的驱动方法，其中，所述数据电压是通过将第一电源电压和第二电源电压分压形成的；其中，所述第一电源电压小于所述第二电源电压；
    所述基准电压为所述第一电源电压和所述第二电源电压之间的电压。
  5. 如权利要求4所述的驱动方法，其中，所述基准电压为所述第一电源电压和所述第二电源电压之间的中点电压HAVDD。
  6. 如权利要求1-5任一项所述的驱动方法，其中，所述驱动方法还包括：
    在对所述数据线输入所述电压组的第一个数据电压时，在所述数据线上叠加补偿电压；
    其中，在所述第一个数据电压对应正极性时，所述第一个数据电压叠加所述补偿电压后的电压值大于所述第一个数据电压；
    在所述第一个数据电压对应负极性时，所述第一个数据电压叠加所述补 偿电压后的电压值小于所述第一个数据电压。
  7. 如权利要求6所述的驱动方法，其中，不同所述电压组中，对应同一极性的所述第一数据电压叠加的所述补偿电压相同。
  8. 如权利要求7所述的驱动方法，其中，每一个所述电压组对应的所述补偿电压的绝对值相同。
  9. 如权利要求1-8任一项所述的驱动方法，其中，所述数据线加载所述数据电压的维持时长与所述数据电压对应的子像素打开的维持时长具有非交叠时长；
    同一所述电压组中，加载到所述数据线上的第一个数据电压具有第一非交叠时长，加载到所述数据线上的其余数据电压具有第二非交叠时长；其中，所述第一非交叠时长小于所述第二非交叠时长。
  10. 如权利要求9所述的驱动方法，其中，对应正极性的所述第一个数据电压的所述第一非交叠时长小于对应负极性的所述第一个数据电压的所述第一非交叠时长。
  11. 一种显示装置，包括：
    时序控制器，被配置为：获取当前显示帧的显示数据并输出；以及基于将输入所述数据线上的数据电压分为多个电压组，每个所述电压组包括相邻的至少两个数据电压，同一所述电压组中的数据电压对应的极性相同；输入同一所述数据线的相邻两个所述电压组中的数据电压对应的极性不同；相邻两条所述数据线上对应的所述电压组极性不同的规则，生成极性翻转信号并输出；
    显示面板，包括源极驱动电路；其中，所述源极驱动电路被配置为接收所述显示数据和所述极性翻转信号；根据所述显示数据和所述极性翻转信号，对数据线输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压。
  12. 如权利要求11所述的显示装置，其中，所述源极驱动电路包括：数据处理电路以及多个电压输出电路；其中，每一条所述数据线一一对应电连 接所述电压输出电路；
    所述数据处理电路被配置为接收所述显示数据，并根据所述显示数据，对各所述电压输出电路输出对应的显示数据；
    所述电压输出电路被配置为接收所述极性翻转信号和所述数据处理电路输出的所述显示数据，根据所述极性翻转信号和所述数据处理电路输出的所述显示数据，对电连接的数据线输入数据电压，以使所述数据线电连接的子像素充入对应的数据电压。
  13. 如权利要求12所述的显示装置，其中，所述源极驱动电路还包括：第一电荷共享电路；
    所述第一电荷共享电路被配置为接收第一基准控制信号，并在所述第一基准控制信号的控制下，在对电连接的数据线输入每一个所述数据电压之前输入基准电压。
  14. 如权利要求13所述的显示装置，其中，所述基准电压受所述第一基准控制信号的第一设定沿触发，输入到对应的所述数据线上；
    所述数据电压受所述第一基准控制信号的第二设定沿触发，输入到对应的所述数据线上；
    其中，所述第一设定沿为上升沿，所述第二设定沿为下降沿；
    或者，所述第一设定沿为下降沿，所述第二设定沿为上升沿。
  15. 如权利要求14所述的显示装置，其中，所述第一电荷共享电路包括第一开关晶体管；
    所述第一开关晶体管的栅极被配置为接收所述第一基准控制信号，所述第一开关晶体管的第一极被配置为接收所述基准电压，所述第一开关晶体管的第二极与数据线电连接。
  16. 如权利要求12所述的显示装置，其中，所述源极驱动电路还包括：第二电荷共享电路；
    所述第二电荷共享电路被配置为接收第二基准控制信号，并在所述第二基准控制信号的控制下，在对每一条所述数据线输入每一个所述电压组的第 一个数据电压之前输入所述基准电压。
  17. 如权利要求16所述的显示装置，其中，所述第二基准控制信号为所述极性翻转信号。
  18. 如权利要求17所述的显示装置，其中，所述第二电荷共享电路包括第二开关晶体管；
    所述第二开关晶体管的栅极被配置为接收所述第二基准控制信号，所述第二开关晶体管的第一极被配置为接收所述基准电压，所述第二开关晶体管的第二极与数据线电连接。
  19. 如权利要求12-18任一项所述的显示装置，其中，所述电压输出电路包括第一输出电路和第二输出电路；其中，每一条所述数据线一一对应电连接所述第一输出电路和所述第二输出电路；
    所述第一输出电路被配置为根据所述极性翻转信号和所述显示数据，对电连接的数据线输入对应正极性的数据电压；
    所述第二输出电路被配置为根据所述极性翻转信号和所述显示数据，对电连接的数据线输入对应负极性的数据电压。
  20. 如权利要求19所述的显示装置，其中，所述第一输出电路包括：第一数模转换电路和第二放大器；其中，第一电源电压和第二电源电压之间具有中点电压端，所述第一数模转换电路电连接于第二电源电压和所述中点电压端之间；
    所述第一数模转换电路被配置为接收所述极性翻转信号和所述显示数据，根据所述极性翻转信号，将所述显示数据进行数模转换后产生对应正极性的数据电压并输出；
    所述第二放大器被配置为接收所述第一数模转换电路输出的数据电压，并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
  21. 如权利要求20所述的显示装置，其中，所述第二输出电路包括：第二数模转换电路和第二放大器；其中，第一电源电压和第二电源电压之间具有中点电压端，所述第二数模转换电路电连接于第一电源电压和所述中点电 压端之间；
    所述第二数模转换电路被配置为接收所述极性翻转信号和所述显示数据，根据所述极性翻转信号，将所述显示数据进行数模转换后产生对应负极性的数据电压并输出；
    所述第二放大器被配置为接收所述第二数模转换电路输出的数据电压，并将接收到的数据电压进行放大处理后，输入到电连接的数据线上。
PCT/CN2022/120043 2021-12-16 2022-09-20 显示面板的驱动方法及显示装置 WO2023109231A1 (zh)

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