WO2023168586A1 - 显示面板的驱动方法及显示装置 - Google Patents

显示面板的驱动方法及显示装置 Download PDF

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Publication number
WO2023168586A1
WO2023168586A1 PCT/CN2022/079671 CN2022079671W WO2023168586A1 WO 2023168586 A1 WO2023168586 A1 WO 2023168586A1 CN 2022079671 W CN2022079671 W CN 2022079671W WO 2023168586 A1 WO2023168586 A1 WO 2023168586A1
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Prior art keywords
data
voltage
rate
sub
pixel
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PCT/CN2022/079671
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English (en)
French (fr)
Inventor
缪应蒙
廖燕平
陈东川
姚树林
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000402.4A priority Critical patent/CN117157698A/zh
Priority to PCT/CN2022/079671 priority patent/WO2023168586A1/zh
Priority to US18/024,480 priority patent/US20240290294A1/en
Publication of WO2023168586A1 publication Critical patent/WO2023168586A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving method of a display panel and a display device.
  • Each pixel unit may include: red sub-pixels, green sub-pixels, and blue sub-pixels. By controlling the brightness corresponding to each sub-pixel, the desired display color is mixed to display a color image.
  • the display data load a data voltage to the data line in the display panel, so that each sub-pixel in the display panel is charged with a corresponding data voltage;
  • first target duration between the end time of the voltage conversion edge when the data line is loaded with the data voltage of positive polarity and the start time of the data charging phase corresponding to the sub-pixel charged with the data voltage of positive polarity;
  • second target duration between the end time of the voltage conversion edge when the data line is loaded with the negative polarity data voltage and the start time of the data charging phase corresponding to the sub-pixel charged with the negative polarity data voltage; the second The target duration is greater than the first target duration.
  • the voltage conversion rate of the voltage conversion edge when the data line is loaded with a data voltage of positive polarity is the first conversion rate
  • the voltage conversion rate of the voltage conversion edge when the data line is loaded with a negative polarity data voltage is the second conversion rate
  • the starting time of the voltage conversion edge when the data line is loaded with a data voltage of positive polarity is located after the starting time of the data charging phase corresponding to the sub-pixel charged with the data voltage of positive polarity; and the data line is loaded with a data voltage of positive polarity. There is a first interval between the start time of the voltage conversion edge when the data voltage is used and the start time of the data charging phase corresponding to the sub-pixel charged with the positive polarity data voltage;
  • the starting time of the voltage conversion edge when the data line is loaded with a negative polarity data voltage is located after the starting time of the data charging phase corresponding to the sub-pixel charged with the negative polarity data voltage; and the data line is loaded with a negative polarity.
  • Loading data voltages to data lines in the display panel according to the display data includes:
  • the data lines in the display panel are Load data voltage.
  • the second slew rate is determined to be less than the first slew rate.
  • determining the first slew rate and the second slew rate includes:
  • the determined second interval duration is greater than the first interval duration.
  • determining the first interval duration and the second interval duration includes:
  • the determined second slew rate is less than the first slew rate, and the determined second interval duration is equal to the first interval duration.
  • determining the first slew rate, the second slew rate, the first interval duration, and the second interval duration includes:
  • the determined second slew rate is equal to the first slew rate, and the determined second interval duration is greater than the first interval duration.
  • determining the first slew rate, the second slew rate, the first interval duration, and the second interval duration includes:
  • the data voltage is triggered by a setting edge of a data trigger signal and is input to the data line;
  • the setting edge is one of a rising edge and a falling edge;
  • the starting time of the voltage conversion edge of the data voltage is aligned with the corresponding setting edge.
  • Display panel including source driver circuit
  • timing controller configured to obtain display data of the picture to be displayed in the current display frame; and send the display data to the source driving circuit;
  • the source driving circuit is configured to load data voltages to data lines in the display panel according to the display data, so that each sub-pixel in the display panel is charged with the corresponding data voltage;
  • first target duration between the end time of the voltage conversion edge when the data line is loaded with the data voltage of positive polarity and the start time of the data charging phase corresponding to the sub-pixel charged with the data voltage of positive polarity;
  • second target duration between the end time of the voltage conversion edge when the data line is loaded with the negative polarity data voltage and the start time of the data charging phase corresponding to the sub-pixel charged with the negative polarity data voltage; the second The target duration is greater than the first target duration.
  • the display panel includes a source driver circuit
  • the timing controller is further configured to determine the first slew rate, the second slew rate, the first interval duration, and the second interval duration, and output a first slew rate corresponding to the first slew rate.
  • a rate control signal, a second rate control signal corresponding to the second slew rate, a first duration control signal corresponding to the first interval duration, and a second duration control signal corresponding to the second interval duration are provided to the source.
  • Drive circuit
  • the source driver circuit is further configured to receive the first rate control signal, the second rate control signal, the first duration control signal, the second duration control signal and the display data. , loading data voltages on the data lines in the display panel, so that each sub-pixel in the display panel is charged with the corresponding data voltage.
  • the source driving circuit includes: multiple voltage output units, one of the data lines is electrically connected to one of the voltage output units;
  • the voltage output unit is configured to receive the first rate control signal, the second rate control signal, the first duration control signal, the second duration control signal, and based on the display data,
  • the electrically connected data lines are loaded with a data voltage.
  • the voltage output unit includes: a digital-to-analog conversion circuit, a data output circuit, a first decoder, and a second decoder;
  • the digital-to-analog conversion circuit is configured to receive the display data, perform digital-to-analog conversion on the received display data, and output it to the data output circuit;
  • the first decoder is configured to decode a first rate conversion signal according to the first rate control signal
  • the second decoder is configured to decode a second rate conversion signal according to the second rate control signal
  • the data output circuit is configured to receive the first rate conversion signal, the first duration control signal, the second rate conversion signal and the second duration control signal; and according to the first rate conversion signal and the first duration control signal, based on the display data output by the digital-to-analog conversion circuit, outputting a data voltage corresponding to the positive polarity to the electrically connected data line; and, based on the second rate conversion signal and the second The duration control signal outputs a data voltage corresponding to the negative polarity to the electrically connected data line based on the display data output by the digital-to-analog conversion circuit.
  • Figure 1 is a schematic structural diagram of a display device in an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a display panel in an embodiment of the present disclosure
  • Figure 3 is some signal timing diagrams in embodiments of the present disclosure.
  • Figure 4 is another signal timing diagram in an embodiment of the present disclosure.
  • Figure 5 is another signal timing diagram in an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of some transistors in an embodiment of the present disclosure.
  • Figure 7 is another signal timing diagram in an embodiment of the present disclosure.
  • Figure 8 is some flowcharts of driving methods in embodiments of the present disclosure.
  • Figure 9 is another signal timing diagram in an embodiment of the present disclosure.
  • Figure 10 is another signal timing diagram in an embodiment of the present disclosure.
  • Figure 11 is some further signal timing diagrams in embodiments of the present disclosure.
  • FIG. 12 is another structural schematic diagram of a display device in an embodiment of the present disclosure.
  • the display device may include a display panel 100 and a timing controller 200 .
  • the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4, GA5, GA6), a plurality of data lines DA (for example, DA1, DA2, DA3 , DA4, DA5, DA6, DA7), the gate driving circuit 110 and the source driving circuit 120.
  • the gate driving circuit 110 is coupled to the gate lines GA (for example, GA1, GA2, GA3, GA4, GA5, GA6) respectively
  • the source driving circuit 120 is coupled to the data lines DA (for example, DA1, DA2, DA3, DA4, DA5) respectively.
  • the timing controller 200 can input a control signal to the gate driving circuit 110, so that the gate driving circuit 110 inputs a signal to the gate line GA (for example, GA1, GA2, GA3, GA4, GA5, GA6) to drive the gate line.
  • GA eg, GA1, GA2, GA3, GA4, GA5, GA6.
  • the timing controller can obtain the display data of the picture to be displayed in the current display frame, and the timing controller 200 sends the obtained display data to the source driving circuit 120, so that the source driving circuit 120 can make the source driving circuit 120 send the display data to the screen according to the display data.
  • the data lines in the display panel are loaded with data voltage, thereby charging the sub-pixels, so that each sub-pixel is charged with the corresponding data voltage to realize the screen display function.
  • the source driving circuit 120 may be provided with multiple source driving circuits, and different source driving circuits are connected to different data lines.
  • two source driving circuits 120 may be provided, one source driving circuit 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines.
  • there can also be three, four, or more source driving circuits 120 which can be designed and determined according to actual application requirements, and are not limited here.
  • each pixel unit includes a plurality of sub-pixels.
  • the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that the colors of red, green, blue and white can be mixed to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.
  • a transistor pixel electrode may be included in each sub-pixel.
  • a row of sub-pixels is coupled to a gate line.
  • the odd-numbered rows of sub-pixels in the column of sub-pixels are coupled to the data line located on the left side of the column of sub-pixels
  • the even-numbered rows of sub-pixels are coupled to the data lines located on the left side of the column of sub-pixels. Data line on the right.
  • the odd-numbered rows of subpixels in the column of subpixels are coupled to the data lines located on the right side of the column of subpixels, and the even-numbered rows of subpixels are coupled to the data lines located on the left side of the column of subpixels.
  • the gate electrode of the transistor is electrically connected to the corresponding gate line
  • the source electrode of the transistor is electrically connected to the corresponding data line
  • the drain electrode of the transistor is electrically connected to the pixel electrode.
  • the pixel array structure of the present disclosure can also be a double pixel array structure. Gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce the number of data lines by half, that is, it includes some data lines between two adjacent columns of pixels and some adjacent two columns of pixels. Data lines are not included.
  • the specific pixel arrangement structure and data lines, and the arrangement of scan lines are not limited.
  • the display panel in the embodiment of the present disclosure may be a liquid crystal display panel, an OLED display panel, etc., which is not limited here.
  • Gray scale generally divides the brightness change between the darkest and the brightest into several parts to facilitate screen brightness control.
  • the displayed image is composed of three colors: red, green, and blue. Each color can show different brightness levels, and the combination of red, green, and blue with different brightness levels can form different colors.
  • the gray scale number of the liquid crystal display panel is 6 bits, so the three colors of red, green, and blue each have 64 (that is, 2 6 ) gray scales, and these 64 gray scale values are 0 to 63 respectively.
  • the gray scale number of the LCD panel is 8 bits, so the three colors of red, green, and blue each have 256 (that is, 2 8 ) gray scales, and these 256 gray scale values are 0 to 255 respectively.
  • the gray scale number of the liquid crystal display panel is 10 bits, so the three colors of red, green, and blue each have 1024 (that is, 2 10 ) gray scales, and these 1024 gray scale values are 0 to 1023 respectively.
  • the gray scale number of the liquid crystal display panel is 12 bits, so the three colors of red, green and blue respectively have 4096 (ie 2 12 ) gray scales, and these 4096 gray scale values are 0 to 4093 respectively.
  • the liquid crystal molecules at the sub-pixel when the data voltage input into the pixel electrode of the sub-pixel is greater than the common electrode voltage, the liquid crystal molecules at the sub-pixel can be made to have a positive polarity, and the data in the sub-pixel The polarity corresponding to the voltage is positive.
  • the liquid crystal molecules at the sub-pixel can be made to have a negative polarity, and then the polarity corresponding to the data voltage in the sub-pixel is negative.
  • the common electrode voltage can be 8.3V.
  • the liquid crystal molecules at the sub-pixel can be made to have a positive polarity, then the data voltage of 8.3V ⁇ 16V is the data voltage corresponding to positive polarity. If a data voltage of 0.6V to 8.3V is input into the pixel electrode of the subpixel, the liquid crystal molecules at the subpixel can be made to have a negative polarity, and the data voltage of 0.6V to 8.3V is a data voltage corresponding to the negative polarity.
  • the sub-pixel can correspond to the brightness of the maximum gray scale value of the positive polarity. If a data voltage of 0.6V is input to the pixel electrode of a subpixel, the subpixel can correspond to the brightness of the maximum grayscale value of the negative polarity. In this way, the display panel can implement frame flipping, column flipping, row flipping, dot flipping, etc. according to the corresponding polarity of the sub-pixels.
  • the display panel displays a picture
  • a reload screen for example, a screen displayed when the gray scale values of two adjacent rows differ greatly, taking 8bit as an example, the reload screen can be a screen where the gray scale values of two adjacent rows differ by 127 gray).
  • the screen is displayed above the level value
  • serialization will occur, and problems such as line afterimages will occur when the display panel displays a black and white checkerboard screen.
  • the following description takes the pixel unit including red sub-pixels, green sub-pixels and blue sub-pixels as an example.
  • the red sub-pixel R11, the green sub-pixel G11, and the blue sub-pixel B11 are one pixel unit
  • the red sub-pixel R12, the green sub-pixel G12, and the blue sub-pixel B12 are one pixel unit.
  • the red sub-pixel R21 and the green sub-pixel G21 take the blue sub-pixel B21 as one pixel unit
  • the red sub-pixel R22 and the green sub-pixel G22 take the blue sub-pixel B22 as one pixel unit.
  • the red sub-pixel R31 and the green sub-pixel G31 use the blue sub-pixel B31 as one pixel unit; the red sub-pixel R32 and the green sub-pixel G32 use the blue sub-pixel B32 as one pixel unit.
  • the red sub-pixel R41 and the green sub-pixel G41 take the blue sub-pixel B41 as one pixel unit, and the red sub-pixel R42 and the green sub-pixel G42 take the blue sub-pixel B42 as one pixel unit.
  • the red sub-pixel R51, the green sub-pixel G51, and the blue sub-pixel B51 serve as one pixel unit; the red sub-pixel R52, the green sub-pixel G52, and the blue sub-pixel B52 serve as one pixel unit.
  • the red sub-pixel R61, the green sub-pixel G61, and the blue sub-pixel B61 serve as one pixel unit; the red sub-pixel R62, the green sub-pixel G62, and the blue sub-pixel B62 serve as one pixel unit.
  • green sub-pixel G11, red sub-pixel R21, green sub-pixel G31, red sub-pixel R41, green sub-pixel G51, and red sub-pixel R61 are coupled to the data line DA2.
  • the blue sub-pixel B11, the green sub-pixel G21, the blue sub-pixel B31, the green sub-pixel G41, the blue sub-pixel B51, and the green sub-pixel G61 are coupled to the data line DA3.
  • the red sub-pixel R12, the blue sub-pixel B21, the red sub-pixel R32, the blue sub-pixel B41, the red sub-pixel R52, and the blue sub-pixel B61 are coupled to the data line DA4.
  • the green sub-pixel G12, the red sub-pixel R22, the green sub-pixel G32, the red sub-pixel R42, the green sub-pixel G52, and the red sub-pixel R62 are coupled to the data line DA5.
  • the blue sub-pixel B12, the green sub-pixel G22, the blue sub-pixel B32, the green sub-pixel G42, the blue sub-pixel B52, and the green sub-pixel G62 are coupled to the data line DA6.
  • the sub-pixels in the first row correspond to a gray-scale value of 0, the sub-pixels in the second row correspond to a gray-scale value of 192, the sub-pixels in the third row correspond to a gray-scale value of 0, and the sub-pixels in the fourth row correspond to a gray-scale value of 192.
  • the five rows of sub-pixels correspond to 0 gray-scale values, and the sixth row of sub-pixels correspond to 192 gray-scale values.
  • the overload screen is taken as an example. As shown in Figures 2 to 4, the process of driving the display panel to display the overload screen can be as follows. describe.
  • ga1 represents the signal loaded on gate line GA1
  • ga2 represents the signal loaded on gate line GA2
  • ga3 represents the signal loaded on gate line GA3,
  • ga4 represents the signal loaded on gate line GA4,
  • ga5 represents the signal loaded on gate line GA5,
  • ga6 represents the signal loaded on gate line GA6.
  • Vda2 represents the data voltage loaded on the data line DA2, and
  • Vda3 represents the data voltage loaded on the data line DA3.
  • the high level in the signals ga1 to ga6 can be used as a gate turn-on signal to control the conduction of the transistor in the sub-pixel.
  • the data line DA2 connected to the green subpixel G11 is loaded with the data voltage V02 corresponding to the gray scale value of 0, so that the green subpixel G11 inputs the target data voltage V02.
  • the signal ga2 on the gate line GA2 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R21 is turned on.
  • the data voltage V02 is simultaneously input into the red sub-pixel R21 to precharge the red sub-pixel R21.
  • the data line DA3 connected to the blue sub-pixel B11 is loaded with the data voltage V02 corresponding to the gray scale value of 0, so that the blue sub-pixel B11 inputs the target data voltage.
  • the signal ga2 on the gate line GA2 outputs a high-level gate-on signal, and the transistor in the green sub-pixel G21 is turned on.
  • the data voltage V02 is simultaneously input into the green sub-pixel G21 to precharge the green sub-pixel G21.
  • the data line DA2 connected to the red sub-pixel R21 is loaded with the data voltage V01 corresponding to the 192 gray scale value, so that the red sub-pixel R21 is charged with the target data voltage V01 .
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistor in the green sub-pixel G31 is turned on.
  • the data voltage V01 is simultaneously input into the green sub-pixel G31 to precharge the green sub-pixel G31.
  • the data line DA3 connected to the green sub-pixel G21 is loaded with the data voltage V01 corresponding to the gray scale value of 192, so that the green sub-pixel G21 is charged with the target data voltage V01 .
  • the signal ga3 on the gate line GA3 outputs a high-level gate-on signal, and the transistor in the blue sub-pixel B31 is turned on.
  • the data voltage V01 is simultaneously input into the blue sub-pixel B31 to precharge the blue sub-pixel B31.
  • the data line DA2 connected to the green sub-pixel G31 is loaded with the data voltage V02 corresponding to the gray scale value of 0, so that the green sub-pixel G31 is charged with the target data voltage V02 .
  • the signal ga4 on the gate line GA4 outputs a high-level gate-on signal, and the transistor in the red sub-pixel R41 is turned on.
  • the data voltage V02 is simultaneously input into the red sub-pixel R41 to precharge the red sub-pixel R41.
  • the data line DA3 connected to the blue sub-pixel B31 is loaded with the data voltage V02 corresponding to the gray scale value of 0, so that the blue sub-pixel B31 is charged with the target data.
  • the signal ga4 on the gate line GA4 outputs a high-level gate-on signal, and the transistor in the green sub-pixel G41 is turned on.
  • the data voltage V02 is simultaneously input into the green sub-pixel G41 to precharge the green sub-pixel G41.
  • the data line DA2 connected to the red sub-pixel R41 is loaded with the data voltage V01 corresponding to the 192 gray scale value, so that the red sub-pixel R41 is charged with the target data voltage V01 .
  • the signal ga5 on the gate line GA5 outputs a high-level gate turn-on signal, and the transistor in the green sub-pixel G51 is turned on.
  • the data voltage V01 is simultaneously input into the green sub-pixel G51 to precharge the green sub-pixel G51.
  • the data line DA3 connected to the green sub-pixel G41 is loaded with the data voltage V01 corresponding to the gray scale value of 192, so that the green sub-pixel G41 is charged with the target data voltage V01 .
  • the signal ga5 on the gate line GA5 outputs a high-level gate turn-on signal, and the transistor in the blue sub-pixel B51 is turned on.
  • the data voltage V01 is simultaneously input into the blue sub-pixel B51 to precharge the blue sub-pixel B51.
  • the data line DA2 connected to the green sub-pixel G51 is loaded with the data voltage V02 corresponding to the gray scale value of 0, so that the green sub-pixel G51 is charged with the target data voltage V02. .
  • the signal ga6 on the gate line GA6 outputs a high-level gate turn-on signal, and the transistor in the red sub-pixel R61 is turned on.
  • the data voltage V02 is simultaneously input into the red sub-pixel R51 to precharge the red sub-pixel R51.
  • the data voltage V02 corresponding to the gray scale value of 0 is loaded on the data line DA3 connected to the blue sub-pixel B51, so that the blue sub-pixel B51 is charged with input data.
  • the signal ga6 on the gate line GA6 outputs a high-level gate-on signal, and the transistor in the green sub-pixel G61 is turned on.
  • the data voltage V02 is simultaneously input into the green sub-pixel G61 to precharge the green sub-pixel G61.
  • the data line DA2 connected to the red sub-pixel R61 is loaded with the data voltage V01 corresponding to the 192 gray scale value, so that the red sub-pixel R61 is charged with the target data voltage V01 , and precharge the next sub-pixel.
  • the data line DA3 connected to the green sub-pixel G61 is loaded with the data voltage V01 corresponding to the 192 gray scale value, so that the green sub-pixel G61 is charged with the target data voltage V01 , and precharge the next sub-pixel.
  • the implementation methods of the remaining sub-pixels are deduced in sequence until the sub-pixels in the entire display panel are completely charged with data voltage, which will not be described again here.
  • Vda2' in Figure 3 represents the ideal charging of the sub-pixel connected to the data line DA2
  • Vda2" represents the actual charging of the sub-pixel connected to the data line DA2
  • Figure 4 Vda3' in represents the ideal charging of the sub-pixel connected to the data line DA3
  • Vda3" represents the actual charging of the sub-pixel connected to the data line DA3. It can be seen from this that if the data voltage of the previous row precharged by the sub-pixel is not completely refreshed by the target data voltage to be charged, the sub-pixel will be undercharged and will appear serial.
  • ga2 represents the signal transmitted on the gate line GA2 in the ideal state
  • ga2' represents the signal transmitted on the gate line GA2 in the actual state
  • Vda2 represents the signal transmitted on the data line DA2 in the T12 stage. signal of.
  • the red subpixel R21 corresponds to the target data voltage V01 of 192 grayscale values
  • the green subpixel G31 corresponds to the target data voltage V02 of the 0 grayscale value. In this way, after the red sub-pixel R21 is charged with the target data voltage V01, the target data voltage V02 corresponding to the green sub-pixel G31 is input to the data line DA2.
  • a subpixel to which a target data voltage of positive polarity is input is defined as a positive polarity subpixel
  • a subpixel to which a target data voltage of negative polarity is input is defined as a negative polarity subpixel.
  • the source and drain of the transistor are arranged in a symmetrical structure, so that the source and drain are equivalent.
  • the voltage VG applied to its gate can be 30V
  • the voltage VD1 of one of its source and drain can be 16V
  • the voltage VD1 of its source and drain can be 16V.
  • the voltage VG loaded on its gate can be 30V
  • the voltage VD2 of one of its source and drain can be 0V
  • the voltage VS2 of the other of its source and drain can be 8V.
  • the bias voltage of the transistor TFT2 when working is greater than the bias voltage of the transistor TFT1 when working, thus causing the on-state current of the transistor TFT2 to be greater than the on-state current of the transistor TFT1 when working, thus making the negative polarity sub-pixel charge better than the positive polarity sub-pixel. of charging.
  • the voltage between its source and drain is also in a very small state (about 1V).
  • TFT1 Basically in off state. Therefore, the charging time tc1 of the positive polarity subpixel is shorter than the charging time tc2 of the negative polarity subpixel, so that the charging of the negative polarity subpixel is better than the charging of the positive polarity subpixel.
  • the display panel will have poor display problems.
  • embodiments of the present disclosure provide a driving method for a display panel. As shown in FIG. 8 , the method may include the following steps:
  • the acquired display data may include a one-to-one digital signal form for each sub-pixel carrying a data voltage carrying a corresponding gray scale value.
  • the grayscale value corresponding to each sub-pixel can be determined based on the display data of each sub-pixel.
  • the data voltage of the corresponding gray-scale value can be input to the data line, so that the green sub-pixel G21 charges the target data voltage of the corresponding gray scale value.
  • the display panel driving method since the end time of the voltage conversion edge when the data line is loaded with a positive data voltage and the start time of the data charging phase corresponding to the sub-pixel charged with the positive data voltage There is a first target duration, and there is a second target duration between the end time of the voltage conversion edge when the data line is loaded with the negative polarity data voltage and the start time of the data charging phase corresponding to the sub-pixel charged with the negative polarity data voltage, by Making the second target duration longer than the first target duration can make the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage.
  • the charging rate of the positive polarity sub-pixel is increased, thereby minimizing the difference in charging rate between the positive polarity sub-pixel and the negative polarity sub-pixel, and improving the problem of poor display of the display panel.
  • a subpixel charged with a positive polarity data voltage may refer to a positive polarity subpixel. That is to say, this sub-pixel is a sub-pixel in which the target data voltage V11 is charged to a positive polarity.
  • a subpixel charged with a negative polarity data voltage may refer to a negative polarity subpixel. That is to say, this sub-pixel is a sub-pixel in which the charging target data voltage V12 has a negative polarity.
  • SB1 represents the voltage conversion edge when the data line DA2 is loaded with a positive data voltage, and when the data line DA2 switches from the previous data voltage to the positive data voltage V11, there will be a charge and discharge process. The process forms the voltage conversion edge SB1.
  • SB2 represents the voltage transition edge when the data voltage of negative polarity is loaded on the data line DA2.
  • the data line DA2 switches from the previous data voltage to the negative data voltage V12, there will be a charge and discharge process, and the charge and discharge process forms the voltage switching edge SB2.
  • the time for the negative polarity subpixel to be charged to the maximum value of the target data voltage can be later than the time for the positive polarity subpixel to be charged to the maximum value of the target data voltage, which can be equivalent to reducing
  • the charging rate of negative polarity sub-pixels increases the charging rate of positive polarity sub-pixels, thereby minimizing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels, and improving the problem of poor display of the display panel.
  • the voltage conversion rate of the voltage conversion edge SB1 when the data line is loaded with a data voltage of positive polarity can be set as the first conversion rate, and the data line is loaded with a data voltage of negative polarity.
  • the voltage slew rate at the voltage conversion edge SB2 is set to the second slew rate. In this way, the data voltage of positive polarity can be loaded onto the data line according to the first conversion rate, and the data voltage of negative polarity can be loaded onto the data line according to the second conversion rate.
  • the starting time of the voltage conversion edge when the data line is loaded with a data voltage of positive polarity is located after the starting time of the data charging phase corresponding to the sub-pixel charged with the data voltage of positive polarity, and the data line is loaded with a positive polarity. There is a first interval between the start time of the voltage conversion edge when the data voltage is positive and the start time of the data charging phase corresponding to the sub-pixel charged with the data voltage of positive polarity.
  • the starting time of the voltage conversion edge when the data line is loaded with a negative polarity data voltage is after the start time of the data charging phase corresponding to the sub-pixel charged with a negative polarity data voltage, and the data line is loaded with a negative polarity data voltage.
  • the starting time of the voltage conversion edge SB1 when the data line DA2 is loaded with the data voltage V11 of positive polarity is located at the data corresponding to the sub-pixel that is to be charged with the data voltage V11 of positive polarity as the target data voltage.
  • first interval GOE1 between the start time of the voltage conversion edge SB1 when the data line DA2 is loaded with the positive data voltage V11 and the start time of the data charging phase T12 .
  • the start time of the voltage conversion edge SB2 when the data line DA2 is loaded with the negative data voltage V12 is located after the start time of the data charging phase T12 corresponding to the sub-pixel to be charged with the negative data voltage V12 as the target data voltage.
  • second interval GOE2 between the start time of the voltage conversion edge SB2 when the data line DA2 is loaded with the negative data voltage V12 and the start time of the data charging phase T12. In this way, it can be determined according to the first interval duration GOE1 when to load the data voltage of positive polarity onto the data line, and according to the second interval duration GOE2 it can be determined when to load the data voltage of negative polarity onto the data line.
  • step S100 and before step S200 it may also include determining the first slew rate and the second slew rate to determine the loading of the positive polarity data voltage and the negative polarity data voltage. Data line rate.
  • the determined first slew rate and second slew rate can be used to load data voltages on the data lines in the display panel according to the display data. Therefore, the second target duration t2 is greater than the first target duration t1, so that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage.
  • the charging rate of negative polarity sub-pixels increases the charging rate of positive polarity sub-pixels, thereby minimizing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels, and improving the problem of poor display of the display panel.
  • the determined second slew rate may be made smaller than the first slew rate.
  • the time it takes to load the negative polarity data voltage V12 to the data line and charge to the target value is longer than the time it takes to load the positive polarity data voltage V11 to the data line and charge to the target value.
  • the time used is such that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • determining the first slew rate and the second slew rate may include: selecting two set voltage slew rates from a plurality of different pre-stored set voltage slew rates, and converting the selected two set voltage slew rates.
  • the larger of the two set voltage conversion rates is used as the first conversion rate, and the smaller of the two selected set voltage conversion rates is used as the second conversion rate.
  • the set voltage conversion rates K_2 and K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, and K_4, and the set voltage conversion rate K_3 can be used as the first conversion rate, Set the voltage slew rate K_2 as the second slew rate.
  • the timing controller may also determine a first slew rate and a second slew rate.
  • a first rate control signal represented by a digital signal is generated based on the determined first conversion rate
  • a second rate control signal represented by a digital signal is generated based on the determined second conversion rate. and outputting a first rate control signal corresponding to the first slew rate and a second rate control signal corresponding to the second slew rate to the source driver circuit.
  • the source driving circuit can receive the first rate control signal and the second rate control signal represented by digital signals, so that the source driving circuit can make the source driving circuit respond to the received first rate control signal, the second rate control signal and the display data. , loading the data voltage on the data line in the display panel, so that each sub-pixel in the display panel is charged with the corresponding data voltage.
  • the source driving circuit 120 may include: multiple voltage output units 121 , and one data line is electrically connected to one voltage output unit.
  • the voltage output unit is configured to load the data voltage on the electrically connected data line based on the received first rate control signal, the second rate control signal and the display data.
  • the data line DA1 is electrically connected to one voltage output unit 121
  • the data line DA2 is electrically connected to another voltage output unit 121.
  • the voltage output unit 121 can load corresponding data to the electrically connected data line DA1 based on the received first rate control signal, the second rate control signal and the display data. Voltage.
  • the voltage output unit 121 may output a data voltage corresponding to the positive polarity to the data line DA1 based on the display data according to the first rate conversion signal. And, according to the second rate conversion signal and based on the display data, a data voltage corresponding to the negative polarity is output to the data line DA1. It should be noted that the working principles of the voltage output units 121 connected to the other data lines are basically the same as the working principles of the voltage output unit 121 and will not be described again here.
  • the voltage output unit 121 may include: a digital-to-analog conversion circuit 1211, a data output circuit 1212, a first decoder 1213, and a second decoder 1214, wherein the first decoder may adopt digital
  • the first rate control signal represented by the signal is decoded to obtain the first rate conversion signal, and the first rate conversion signal is output to the data output circuit 1212 .
  • the second decoder may decode the second rate conversion signal according to the second rate control signal represented by the digital signal, and output the second rate conversion signal to the data output circuit 1212 .
  • the digital-to-analog conversion circuit 1211 can receive display data represented by digital signals, perform digital-to-analog conversion on the received display data to obtain display data represented by analog voltages, and output the display data represented by analog voltages to the data output circuit. 1212.
  • the data output circuit 1212 may receive the first and second rate converted signals and a display output. And according to the first rate conversion signal and the display data output by the digital-to-analog conversion circuit, a data voltage corresponding to the positive polarity is output to the electrically connected data line. And according to the second rate conversion signal, based on the display data output by the digital-to-analog conversion circuit, output a data voltage corresponding to the negative polarity to the electrically connected data line.
  • Table 1 shows the digital signals corresponding to different set voltage conversion rates.
  • the digital signal corresponding to the set voltage conversion rate K_1 can be 0000
  • the digital signal corresponding to the set voltage conversion rate K_2 can be 0101
  • the digital signal corresponding to the set voltage conversion rate K_3 can be 1010
  • the set voltage conversion rate K_4 The corresponding digital signal can be 1111.
  • the timing controller 200 stores Table 1. After determining the set voltage slew rate After K_3 is used as the first conversion rate, 1010 can be sent to the first decoder 1213 as the first rate control signal. After receiving 1010, the first decoder 1213 can decode the first rate conversion signal corresponding to 1010. The first rate conversion signal is sent to the data output circuit 1212. This allows the data output circuit 1212 to convert the signal according to the first rate and output the data voltage corresponding to the positive polarity to the electrically connected data line based on the display data output by the digital-to-analog conversion circuit.
  • the timing controller 200 may send 0101 as the second rate control signal to the first decoder 1213 .
  • the first decoder 1213 can decode the second rate conversion signal corresponding to 0101.
  • the second rate conversion signal is sent to the data output circuit 1212. This allows the data output circuit 1212 to convert the signal according to the second rate and output the data voltage corresponding to the negative polarity to the electrically connected data line based on the display data output by the digital-to-analog conversion circuit.
  • Table 1 is only for example. In actual applications, it can also adopt other forms of expression and is not limited here.
  • the data voltage can be triggered by the set edge of the data trigger signal and input to the data line.
  • the setting edge is one of a rising edge and a falling edge, and the starting time of the voltage conversion edge at the time of the data voltage is aligned with the corresponding setting edge.
  • the setting edge can be set to a falling edge, and then the data voltage is triggered by the falling edge of the data trigger signal TP1 and is input to the data line.
  • the setting edge can also be set to a rising edge, then the data voltage is triggered by the rising edge of the data trigger signal TP1 and is input to the data line.
  • the pulse width of the data trigger signal TP1 corresponding to the positive polarity data voltage and the negative polarity data voltage can be made the same, and the same data trigger signal TP1 can be used for triggering, reducing the data triggering
  • the signal design is more difficult and the calculation amount and power consumption are reduced.
  • a one-to-one digital signal form carrying a data voltage carrying a corresponding grayscale value for each sub-pixel of the picture to be displayed can be obtained.
  • the grayscale value corresponding to each sub-pixel can be determined based on the display data.
  • the set voltage conversion rate K_2, K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, K_4, and the set voltage conversion rate K_3 is used as the first conversion rate, and the set voltage conversion rate K_2 is used as the second conversion rate.
  • the second slew rate corresponding to the voltage conversion edge SB2 is smaller than the first slew rate corresponding to the voltage conversion edge SB1.
  • the first conversion rate (such as the set voltage conversion rate K_3) can be used to load the data voltage V11 to the data line
  • the second conversion rate (such as the set voltage conversion rate K_2) can be used to load the data line Data voltage V12, so that the voltage transition edge SB2 that jumps to data voltage V11 can be steeper than the voltage transition edge SB2 that jumps to data voltage V12, so that compared with the voltage transition edge SB2 that makes the voltage on the data line jump to data voltage V12
  • the target value can make the voltage on the data line jump to the target value of data voltage V11 in advance, so that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage is later than the time when the positive polarity sub-pixel is charged to the maximum value of the target data voltage.
  • this can be equivalent to reducing the charging rate of negative polarity sub-pixels and increasing the charging rate of positive polarity sub-pixels, thereby reducing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels as much as possible, and improving the problem of poor display of the display panel.
  • Embodiments of the present disclosure provide other driving methods for display panels, which are modified from the implementations in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • step S100 and before step S200 it may also include determining the first interval duration and the second interval duration to determine the loading of the positive polarity data voltage and the negative polarity data voltage. time on the data line.
  • the determined first interval duration and the second interval duration can be used to load the data voltage on the data lines in the display panel according to the display data. Therefore, the second target duration t2 is greater than the first target duration t1, so that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage.
  • the charging rate of negative polarity sub-pixels increases the charging rate of positive polarity sub-pixels, thereby minimizing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels, and improving the problem of poor display of the display panel.
  • the determined second interval duration GOE2 can be made greater than the first interval duration GOE1.
  • the positive data voltage V11 can be loaded to the data line after the first interval GOE1, so as to switch the previous data voltage to the current data voltage V11.
  • the data line starts to be loaded with the negative polarity data voltage V12, so as to switch the previous data voltage to the current data voltage V12. This can further make the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • the charging rate of the pixel is reduced as much as possible, so that the difference in charging rate between the positive sub-pixel and the negative sub-pixel is reduced as much as possible, thereby improving the problem of poor display of the display panel.
  • determining the first interval duration and the second interval duration may include: selecting two set interval durations from a plurality of different pre-stored set interval durations, and combining the selected two set interval durations. The larger of the fixed interval durations is used as the second interval duration, and the smaller of the two selected interval durations is used as the first interval duration.
  • two set interval durations Y_2 and Y_3 can be selected from the set interval durations Y_1, Y_2, Y_3, and Y_4, and the set interval duration Y_2 can be used as the first interval duration, and the set interval duration Y_3 can be used as Second interval duration.
  • the data voltage can be triggered by the set edge of the data trigger signal and input to the data line.
  • the setting edge is one of a rising edge and a falling edge, and the starting time of the voltage conversion edge at the time of the data voltage is aligned with the corresponding setting edge.
  • the setting edge can be set to a falling edge
  • the falling edge of the data trigger signal TP11 can be used to trigger the positive polarity data voltage to be input to the data line
  • the data trigger signal TP12 can be used.
  • the falling edge triggers the negative polarity data voltage input to the data line.
  • one pulse of the data trigger signal TP11 corresponds to one pulse of the data trigger signal TP12, and the rising edge of each pulse of the data trigger signal TP11 is aligned with the rising edge of the corresponding pulse in the data trigger signal TP12, so that the data trigger
  • the falling edge of each pulse of signal TP12 is located after the falling edge of the corresponding pulse of data trigger signal TP11.
  • the interval duration between the falling edge of each pulse of the data trigger signal TP12 and the falling edge of the corresponding pulse in the data trigger signal TP11 is GOE2-GOE1.
  • the setting edge can also be set to a rising edge, which is not limited here.
  • Table 2 shows the digital signals corresponding to different set interval durations.
  • the digital signal corresponding to the set interval duration Y_1 can be 0001
  • the digital signal corresponding to the set interval duration Y_2 can be 0010
  • the digital signal corresponding to the set interval duration Y_3 can be 0110
  • the digital signal corresponding to the set interval duration Y_4 Can be 0111.
  • the timing controller 200 stores Table 2, and the timing controller 200 determines the set interval After duration Y_2 is used as the first interval duration, 0010 can be used as the first duration control signal. This 0010 is also sent to the data output circuit 1212. In this way, the data output circuit 1212 can output the data voltage corresponding to the positive polarity to the electrically connected data line according to 0010 and based on the display data output by the digital-to-analog conversion circuit. And, after determining the set interval duration Y_3 as the second interval duration, the timing controller 200 may use 0110 as the second duration control signal. This 0110 is also sent to the data output circuit 1212.
  • a one-to-one digital signal form carrying a data voltage carrying a corresponding grayscale value for each sub-pixel of the picture to be displayed can be obtained.
  • the grayscale value corresponding to each sub-pixel can be determined based on the display data.
  • the second interval duration GOE2 can be greater than the first interval duration GOE1, so that after entering the data charging stage, the positive polarity data voltage V11 can be loaded to the data line after the first interval duration GOE1 (such as setting the interval duration Y_2). , and the negative polarity data voltage V12 can be started to be loaded on the data line after the second interval time GOE2 (such as the set interval time Y_3).
  • the voltage on the data line can be made to jump to the target value of the data voltage V11 further in advance, so that the negative polarity sub-pixel is charged to the maximum value of the target data voltage.
  • the value time is later than the time when the positive polarity sub-pixel is charged to the maximum value of the target data voltage. This can be equivalent to reducing the charging rate of the negative polarity sub-pixel and increasing the charging rate of the positive polarity sub-pixel, thereby making the gap between the positive polarity sub-pixel and the negative polarity sub-pixel.
  • the charging rate difference is reduced as much as possible to improve the problem of poor display on the display panel.
  • Embodiments of the present disclosure provide further driving methods for display panels, which are modified from the implementation methods in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • step S100 and before step S200 it may also include determining the first slew rate, the second slew rate, the first interval duration, and the second interval duration to determine the positive polarity data. voltage and the time and rate at which negative polarity data voltages are loaded onto the data lines. In this way, the determined first slew rate, second slew rate, first interval duration, and second interval duration can be used to load data voltages to the data lines in the display panel according to the display data.
  • the second target duration t2 is greater than the first target duration t1, so that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage.
  • This can be equivalent to reducing
  • the charging rate of negative polarity sub-pixels increases the charging rate of positive polarity sub-pixels, thereby minimizing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels, and improving the problem of poor display of the display panel.
  • the determined second slew rate may be made smaller than the first slew rate.
  • the time it takes to load the negative polarity data voltage V12 to the data line and charge to the target value is longer than the time it takes to load the positive polarity data voltage V11 to the data line and charge to the target value.
  • the time used is such that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • the determined second interval duration may be equal to the first interval duration. In this way, after entering the data charging stage, the data line can be loaded with positive data voltage and negative data voltage within the same period of time.
  • multiple different set voltage conversion rates are pre-stored in the timing controller.
  • the multiple different pre-stored set voltage slew rates may include: set voltage slew rate K_1, set voltage slew rate K_2, set voltage slew rate K_3...set voltage slew rate K_n.
  • n is an integer greater than 1.
  • multiple different set interval durations are pre-stored in the timing controller.
  • multiple different pre-stored set interval durations may include: set interval duration Y_1, set interval duration Y_2, set interval duration Y_3...set interval duration K_m.
  • m is an integer greater than 1.
  • determining the first slew rate, the second slew rate, the first interval duration and the second interval duration may include: selecting two settings from a plurality of different pre-stored voltage slew rates. A constant voltage conversion rate is used, the larger of the two selected voltage conversion rates is used as the first conversion rate, and the smaller of the two selected voltage conversion rates is used as the second conversion rate. and selecting one set interval duration from a plurality of different pre-stored set interval durations as the first interval duration and the second interval duration respectively.
  • the set voltage conversion rates K_2 and K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, and K_4, and the set voltage conversion rate K_3 can be used as the third voltage conversion rate.
  • a slew rate, the voltage slew rate K_2 is set as the second slew rate.
  • the set interval duration Y_2 can be selected from the set interval durations Y_1, Y_2, Y_3, and Y_4, and the set interval duration Y_2 can be used as the first interval duration, and the set interval duration Y_2 can be used as the second interval duration.
  • the timing controller may also determine a first slew rate, a second slew rate, a first interval duration, and a second interval duration. and generate a first rate control signal represented by a digital signal according to the determined first conversion rate, generate a second rate control signal represented by a digital signal according to the determined second conversion rate, and generate a second rate control signal represented by a digital signal according to the determined first interval duration.
  • a first duration control signal represented by a digital signal is used, and a second duration control signal represented by a digital signal is generated according to the determined second interval duration.
  • the source driving circuit can receive the first rate control signal, the second rate control signal, the first duration control signal and the second duration control signal expressed by digital signals, so that the source driving circuit can receive the first rate control signal according to the received first rate control signal.
  • the rate control signal, the second rate control signal, the first duration control signal, the second duration control signal and the display data load data voltages to the data lines in the display panel, so that each sub-pixel in the display panel is charged with the corresponding data voltage.
  • the source driving circuit 120 may include: multiple voltage output units 121 , and one data line is electrically connected to one voltage output unit.
  • the voltage output unit is configured to load the data voltage to the electrically connected data line based on the received first rate control signal, second rate control signal, first duration control signal, and second duration control signal based on the display data.
  • the data line DA1 is electrically connected to one voltage output unit 121
  • the data line DA2 is electrically connected to another voltage output unit 121.
  • the voltage output unit 121 can display data based on the received first rate control signal, second rate control signal, first duration control signal, and second duration control signal.
  • the voltage output unit 121 may output a data voltage corresponding to the positive polarity to the data line DA1 based on the display data according to the first rate conversion signal and the first duration control signal. And, according to the second rate conversion signal and the second duration control signal, based on the display data, a data voltage corresponding to the negative polarity is output to the data line DA1. It should be noted that the working principles of the voltage output units 121 connected to the other data lines are basically the same as the working principles of the voltage output unit 121 and will not be described again here.
  • the voltage output unit 121 may include: a digital-to-analog conversion circuit 1211, a data output circuit 1212, a first decoder 1213, and a second decoder 1214, wherein the first decoder may adopt digital
  • the first rate control signal represented by the signal is decoded to obtain the first rate conversion signal, and the first rate conversion signal is output to the data output circuit 1212 .
  • the second decoder may decode the second rate conversion signal according to the second rate control signal represented by the digital signal, and output the second rate conversion signal to the data output circuit 1212 .
  • the digital-to-analog conversion circuit 1211 can receive display data represented by digital signals, perform digital-to-analog conversion on the received display data to obtain display data represented by analog voltages, and output the display data represented by analog voltages to the data output circuit. 1212.
  • the data output circuit 1212 may receive the first rate conversion signal, the first duration control signal, the second rate conversion signal, the second duration control signal, and a display output. And according to the first rate conversion signal and the first duration control signal, based on the display data output by the digital-to-analog conversion circuit, a data voltage corresponding to the positive polarity is output to the electrically connected data line. and outputting a data voltage corresponding to the negative polarity to the electrically connected data line based on the display data output by the digital-to-analog conversion circuit according to the second rate conversion signal and the second duration control signal.
  • Table 1 shows the digital signals corresponding to different set voltage conversion rates.
  • Table 2 shows the digital signals corresponding to different set interval lengths.
  • the digital signal corresponding to the set voltage conversion rate K_1 can be 0000
  • the digital signal corresponding to the set voltage conversion rate K_2 can be 0101
  • the digital signal corresponding to the set voltage conversion rate K_3 can be 1010
  • the set voltage conversion rate K_4 The corresponding digital signal can be 1111.
  • the digital signal corresponding to the set interval duration Y_1 can be 0001, the digital signal corresponding to the set interval duration Y_2 can be 0010, the digital signal corresponding to the set interval duration Y_3 can be 0110, and the digital signal corresponding to the set interval duration Y_4 can be 0111.
  • the timing controller 200 stores Table 1 and Table 2. After determining the set voltage conversion rate K_3 as the first conversion rate, 1010 can be sent to the first decoder as the first rate control signal. Device 1213. After receiving 1010, the first decoder 1213 can decode the first rate conversion signal corresponding to 1010. The first rate conversion signal is sent to the data output circuit 1212.
  • the timing controller 200 may use 0010 as the first duration control signal. This 0010 is also sent to the data output circuit 1212. This allows the data output circuit 1212 to output the data voltage corresponding to the positive polarity to the electrically connected data line according to the first rate conversion signal and 0010 and based on the display data output by the digital-to-analog conversion circuit. And, after determining the set voltage slew rate K_2 as the second slew rate, the timing controller 200 may send 0101 as the second rate control signal to the first decoder 1213 . After receiving 0101, the first decoder 1213 can decode the second rate conversion signal corresponding to 0101.
  • the second rate conversion signal is sent to the data output circuit 1212. Furthermore, after determining the set interval duration Y_2 as the second interval duration, the timing controller 200 may use 0010 as the second duration control signal. This 0010 is also sent to the data output circuit 1212. This allows the data output circuit 1212 to output the data voltage corresponding to the negative polarity to the electrically connected data line according to the second rate conversion signal and 0010 and based on the display data output by the digital-to-analog conversion circuit. It should be noted that Table 1 and Table 2 are only for examples. In actual applications, they can also adopt other forms of expression and are not limited here.
  • the grayscale value corresponding to each sub-pixel can be determined based on the display data.
  • the set voltage conversion rate K_2, K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, K_4, and the set voltage conversion rate K_3 is used as the first conversion rate, and the set voltage conversion rate K_2 is used as the second conversion rate.
  • the set interval duration Y_2 can be selected from the set interval durations Y_1, Y_2, Y_3, and Y_4, and the set interval duration Y_2 can be used as the first interval duration, and the set interval duration Y_2 can be used as the second interval duration.
  • the second interval duration GOE2 can be equal to the first interval duration GOE1, and the second slew rate corresponding to the voltage conversion edge SB2 can be smaller than the first slew rate corresponding to the voltage conversion edge SB1.
  • the data voltage V11 and the data voltage V12 can be loaded to the data line at the same time.
  • the data line is loaded with the data voltage V11 using the first conversion rate (such as the set voltage conversion rate K_3), and the data voltage V12 is loaded on the data line using the second conversion rate (such as the set voltage conversion rate K_2), so that the data line can be loaded with the data voltage V11.
  • the voltage conversion edge SB2 that jumps to the data voltage V11 is steeper than the voltage conversion edge SB2 that jumps to the data voltage V12. In this way, compared with making the voltage on the data line jump to the target value of the data voltage V12, the data can be made in advance.
  • the voltage on the line jumps to the target value of data voltage V11, so that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage is later than the time when the positive polarity sub-pixel is charged to the maximum value of the target data voltage.
  • This can be equivalent to reducing
  • the charging rate of negative polarity sub-pixels increases the charging rate of positive polarity sub-pixels, thereby minimizing the difference in charging rates between positive polarity sub-pixels and negative polarity sub-pixels, and improving the problem of poor display of the display panel.
  • Embodiments of the present disclosure provide other driving methods for display panels, which are modified from the implementations in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the determined second slew rate may be made smaller than the first slew rate.
  • the time it takes to load the negative polarity data voltage V12 to the data line and charge to the target value is greater than the time it takes to load the positive polarity data voltage V11 to the data line and charge to the target value.
  • the time used is such that the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 is later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • determining the first slew rate and the second slew rate may include: selecting two set voltage slew rates from a plurality of different pre-stored set voltage slew rates, and converting the selected two set voltage slew rates.
  • the larger of the two set voltage conversion rates is used as the first conversion rate, and the smaller of the two selected set voltage conversion rates is used as the second conversion rate.
  • the set voltage conversion rates K_2 and K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, and K_4, and the set voltage conversion rate K_3 can be used as the first conversion rate, Set the voltage slew rate K_2 as the second slew rate.
  • the determined second interval duration GOE2 can be made greater than the first interval duration GOE1.
  • the positive data voltage V11 can be loaded to the data line after the first interval GOE1, so as to switch the previous data voltage to the current data voltage V11.
  • the data line starts to be loaded with the negative polarity data voltage V12, so as to switch the previous data voltage to the current data voltage V12. This can further make the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • the charging rate of the pixel is reduced as much as possible, so that the difference in charging rate between the positive sub-pixel and the negative sub-pixel is reduced as much as possible, thereby improving the problem of poor display of the display panel.
  • determining the first interval duration and the second interval duration may include: selecting two set interval durations from a plurality of different pre-stored set interval durations, and combining the selected two set interval durations. The larger of the fixed interval durations is used as the second interval duration, and the smaller of the two selected interval durations is used as the first interval duration.
  • two set interval durations Y_2 and Y_3 can be selected from the set interval durations Y_1, Y_2, Y_3, and Y_4, and the set interval duration Y_2 can be used as the first interval duration, and the set interval duration Y_3 can be used as Second interval duration.
  • the data voltage can be triggered by the set edge of the data trigger signal and input to the data line.
  • the setting edge is one of a rising edge and a falling edge, and the starting time of the voltage conversion edge at the time of the data voltage is aligned with the corresponding setting edge.
  • the setting edge can be set to a falling edge
  • the falling edge of the data trigger signal TP11 can be used to trigger the positive polarity data voltage to be input to the data line
  • the data trigger signal TP12 can be used.
  • the falling edge triggers the negative polarity data voltage input to the data line.
  • one pulse of the data trigger signal TP11 corresponds to one pulse of the data trigger signal TP12, and the rising edge of each pulse of the data trigger signal TP11 is aligned with the rising edge of the corresponding pulse in the data trigger signal TP12, so that the data trigger
  • the falling edge of each pulse of signal TP12 is located after the falling edge of the corresponding pulse of data trigger signal TP11.
  • the interval duration between the falling edge of each pulse of the data trigger signal TP12 and the falling edge of the corresponding pulse in the data trigger signal TP11 is GOE2-GOE1.
  • the setting edge can also be set to a rising edge, which is not limited here.
  • the grayscale value corresponding to each sub-pixel can be determined based on the display data.
  • the set voltage conversion rate K_2, K_3 can be selected from the set voltage conversion rates K_1, K_2, K_3, K_4, and the set voltage conversion rate K_3 is used as the first conversion rate, and the set voltage conversion rate K_2 is used as the second conversion rate.
  • the second interval duration GOE2 can be greater than the first interval duration GOE1
  • the second slew rate corresponding to the voltage conversion edge SB2 can be smaller than the first slew rate corresponding to the voltage conversion edge SB1.
  • the data line can be loaded with the positive data voltage V11 after the first interval length GOE1 (such as the set interval length Y_2), and the first conversion rate (such as the set voltage conversion rate K_3 ) switches the previous data voltage to the current data voltage V11.
  • the negative polarity data voltage V12 can be loaded to the data line after the second interval length GOE2 (such as the set interval length Y_3), and the second conversion rate (such as the set voltage conversion rate K_2) Switch the previous data voltage to the current data voltage V12.
  • the voltage on the data line can be made to jump to the target value of the data voltage V11 further in advance, so that the negative polarity sub-pixel is charged to the maximum value of the target data voltage.
  • the value time is later than the time when the positive polarity sub-pixel is charged to the maximum value of the target data voltage.
  • Embodiments of the present disclosure provide further driving methods for display panels, which are modified from the implementation methods in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the determined second interval duration GOE2 can be made greater than the first interval duration GOE1.
  • the positive data voltage V11 can be loaded to the data line after the first interval GOE1, so as to switch the previous data voltage to the current data voltage V11.
  • the data line starts to be loaded with the negative polarity data voltage V12, so as to switch the previous data voltage to the current data voltage V12. This can further make the time when the negative polarity sub-pixel is charged to the maximum value of the target data voltage V12 later than the time when the positive polarity sub-pixel is charged into the maximum value of the target data voltage V11.
  • the charging rate of the pixel is reduced as much as possible, so that the difference in charging rate between the positive sub-pixel and the negative sub-pixel is reduced as much as possible, thereby improving the problem of poor display of the display panel.
  • determining the first interval duration and the second interval duration may include: selecting two set interval durations from a plurality of different pre-stored set interval durations, and combining the selected two set interval durations. The larger of the fixed interval durations is used as the second interval duration, and the smaller of the two selected interval durations is used as the first interval duration.
  • two set interval durations Y_2 and Y_3 can be selected from the set interval durations Y_1, Y_2, Y_3, and Y_4, and the set interval duration Y_2 can be used as the first interval duration, and the set interval duration Y_3 can be used as Second interval duration.
  • the determined second slew rate may be equal to the first slew rate.
  • the time it takes for the negative polarity data voltage V12 to be loaded onto the data line to charge to the target value is equal to the time it takes for the positive polarity data voltage V11 to be loaded onto the data line to charge to the target value. time taken.
  • determining the first slew rate and the second slew rate may include: selecting a set voltage slew rate from a plurality of different pre-stored set voltage slew rates as the first slew rate. and a second slew rate.
  • the set voltage conversion rate K_2 can be selected from the set voltage conversion rates K_1, K_2, K_3, and K_4, and the set voltage conversion rate K_2 can be used as the first conversion rate, and the set voltage conversion rate K_2 can be used as the first conversion rate.
  • the voltage slew rate K_2 is set as the second slew rate.
  • the data voltage can be triggered by the set edge of the data trigger signal and input to the data line.
  • the setting edge is one of a rising edge and a falling edge, and the starting time of the voltage conversion edge at the time of the data voltage is aligned with the corresponding setting edge.
  • the setting edge can be set to a falling edge
  • the falling edge of the data trigger signal TP11 can be used to trigger the positive polarity data voltage to be input to the data line
  • the data trigger signal TP12 can be used.
  • the falling edge triggers the negative polarity data voltage input to the data line.
  • one pulse of the data trigger signal TP11 corresponds to one pulse of the data trigger signal TP12, and the rising edge of each pulse of the data trigger signal TP11 is aligned with the rising edge of the corresponding pulse in the data trigger signal TP12, so that the data trigger
  • the falling edge of each pulse of signal TP12 is located after the falling edge of the corresponding pulse of data trigger signal TP11.
  • the interval duration between the falling edge of each pulse of the data trigger signal TP12 and the falling edge of the corresponding pulse in the data trigger signal TP11 is GOE2-GOE1.
  • the setting edge can also be set to a rising edge, which is not limited here.
  • the set voltage conversion rate K_2 can be selected from the set voltage conversion rates K_1, K_2, K_3, and K_4, and the set voltage conversion rate K_2 is used as the first conversion rate, and the set voltage conversion rate K_2 is used as the second conversion rate.
  • the second interval duration GOE2 can be greater than the first interval duration GOE1
  • the second slew rate corresponding to the voltage conversion edge SB2 can be equal to the first slew rate corresponding to the voltage conversion edge SB1.
  • the data line can be loaded with the positive data voltage V11 after the first interval length GOE1 (such as the set interval length Y_2), and the first conversion rate (such as the set voltage conversion rate K_2 ) switches the previous data voltage to the current data voltage V11.
  • the negative polarity data voltage V12 can be loaded to the data line after the second interval length GOE2 (such as the set interval length Y_3), and the second conversion rate (such as the set voltage conversion rate K_2) Switch the previous data voltage to the current data voltage V12.
  • the voltage on the data line can jump to the target value of data voltage V11 in advance, so that the negative polarity sub-pixel is charged to the maximum value of the target data voltage.
  • the time is later than the time when the positive polarity sub-pixel is charged to the maximum value of the target data voltage.
  • This can be equivalent to reducing the charging rate of the negative polarity sub-pixel and increasing the charging rate of the positive polarity sub-pixel, thereby increasing the gap between the positive polarity sub-pixel and the negative polarity sub-pixel.
  • the difference in charging rates is reduced as much as possible to improve the problem of poor display on the display panel.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

一种显示面板的驱动方法及显示装置，包括：在当前显示帧中获取待显示画面的显示数据（S100）；根据显示数据，对显示面板中的数据线加载数据电压，使显示面板中的各子像素充入相应的数据电压（S200）；其中，数据线加载正极性的数据电压时的电压转换边沿的结束时刻与充入正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长；数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长；第二目标时长大于第一目标时长。

Description

显示面板的驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法及显示装置。
背景技术
在诸如液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器中，一般包括多个像素单元。每个像素单元可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本公开实施例提供的显示面板的驱动方法，包括：
在当前显示帧中获取待显示画面的显示数据；
根据所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压；
其中，所述数据线加载正极性的数据电压时的电压转换边沿的结束时刻与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长；所述数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长；所述第二目标时长大于所述第一目标时长。
在一些示例中，所述数据线加载正极性的数据电压时的电压转换边沿的电压转换速率为第一转换速率；
所述数据线加载负极性的数据电压时的电压转换边沿的电压转换速率为第二转换速率；
所述数据线加载正极性的数据电压时的电压转换边沿的开始时刻位于充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之后；且 所述数据线加载正极性的数据电压时的电压转换边沿的开始时刻与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一间隔时长；
所述数据线加载负极性的数据电压时的电压转换边沿的开始时刻位于充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之后；且所述数据线加载负极性的数据电压时的电压转换边沿的开始时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二间隔时长；
在所述在当前显示帧中获取待显示画面的显示数据之后，且在所述根据所述显示数据，对所述显示面板中的数据线加载数据电压之前，还包括：
确定所述第一转换速率与所述第二转换速率，和/或所述第一间隔时长与第二间隔时长；
所述根据所述显示数据，对所述显示面板中的数据线加载数据电压，包括：
采用确定出的所述第一转换速率与所述第二转换速率，和/或所述第一间隔时长与所述第二间隔时长，根据所述显示数据，对所述显示面板中的数据线加载数据电压。
在一些示例中，确定出的所述第二转换速率小于所述第一转换速率。
在一些示例中，所述确定所述第一转换速率和所述第二转换速率，包括：
从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为所述第一转换速率，将选取的两个设定电压转换速率中较小的作为所述第二转换速率。
在一些示例中，确定出的所述第二间隔时长大于所述第一间隔时长。
在一些示例中，所述确定所述第一间隔时长和所述第二间隔时长，包括：
从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为所述第二间隔时长，将选取的两个设定间隔时长中较小的作为所述第一间隔时长。
在一些示例中，确定出的所述第二转换速率小于所述第一转换速率，确定出的所述第二间隔时长等于所述第一间隔时长。
在一些示例中，所述确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，包括：
从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为所述第一转换速率，将选取的两个设定电压转换速率中较小的作为所述第二转换速率；
从预先存储的多个不同的设定间隔时长中选取一个设定间隔时长，分别作为所述第一间隔时长和所述第二间隔时长。
在一些示例中，确定出的所述第二转换速率等于所述第一转换速率，确定出的所述第二间隔时长大于所述第一间隔时长。
在一些示例中，所述确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，包括：
从预先存储的多个不同的设定电压转换速率中选取一个设定电压转换速率，分别作为所述第一转换速率和所述第二转换速率；
从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为所述第二间隔时长，将选取的两个设定间隔时长中较小的作为所述第一间隔时长。
在一些示例中，所述数据电压受数据触发信号的设定沿触发，输入到所述数据线上；所述设定沿为上升沿和下降沿中的一个；
所述数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。
本公开实施例提供的显示装置，包括：
显示面板，包括源极驱动电路；
时序控制器，被配置为在当前显示帧中获取待显示画面的显示数据；并将所述显示数据发送给所述源极驱动电路；
所述源极驱动电路被配置为根据所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压；
其中，所述数据线加载正极性的数据电压时的电压转换边沿的结束时刻与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长；所述数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长；所述第二目标时长大于所述第一目标时长。
在一些示例中，所述显示面板包括源极驱动电路；
所述时序控制器还被配置为确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，并输出对应所述第一转换速率的第一速率控制信号、对应所述第二转换速率的第二速率控制信号、对应所述第一间隔时长的第一时长控制信号以及对应所述第二间隔时长的第二时长控制信号给所述源极驱动电路；
所述源极驱动电路还被配置为根据接收到的所述第一速率控制信号、所述第二速率控制信号、所述第一时长控制信号、所述第二时长控制信号以及所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压。
在一些示例中，所述源极驱动电路包括：多个电压输出单元，一条所述数据线电连接一个所述电压输出单元；
所述电压输出单元被配置为根据接收到的所述第一速率控制信号、所述第二速率控制信号、所述第一时长控制信号、所述第二时长控制信号，基于所述显示数据，对电连接的数据线加载数据电压。
在一些示例中，所述电压输出单元包括：数模转换电路、数据输出电路、第一解码器以及第二解码器；
所述数模转换电路被配置为接收所述显示数据，并将接收到的所述显示数据进行数模转换后的，输出给所述数据输出电路；
所述第一解码器被配置为根据所述第一速率控制信号，解码出第一速率转换信号；
所述第二解码器被配置为根据所述第二速率控制信号，解码出第二速率 转换信号；
所述数据输出电路被配置为接收所述第一速率转换信号、所述第一时长控制信号、所述第二速率转换信号以及所述第二时长控制信号；并根据所述第一速率转换信号和所述第一时长控制信号，基于所述数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压；以及，根据所述第二速率转换信号和所述第二时长控制信号，基于所述数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。
附图说明
图1为本公开实施例中的显示装置的一些结构示意图；
图2为本公开实施例中的显示面板的一些结构示意图；
图3为本公开实施例中的一些信号时序图；
图4为本公开实施例中的另一些信号时序图；
图5为本公开实施例中的又一些信号时序图；
图6为本公开实施例中的一些晶体管的结构示意图；
图7为本公开实施例中的又一些信号时序图；
图8为本公开实施例中的驱动方法的一些流程图；
图9为本公开实施例中的又一些信号时序图；
图10为本公开实施例中的又一些信号时序图；
图11为本公开实施例中的又一些信号时序图；
图12为本公开实施例中的显示装置的另一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所 描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1以及图2所示，显示装置可以包括显示面板100以及时序控制器200。其中，显示面板100可以包括多个阵列排布的像素单元，多条栅线GA(例如，GA1、GA2、GA3、GA4、GA5、GA6)、多条数据线DA(例如，DA1、DA2、DA3、DA4、DA5、DA6、DA7)、栅极驱动电路110以及源极驱动电路120。栅极驱动电路110分别与栅线GA(例如，GA1、GA2、GA3、GA4、GA5、GA6)耦接，源极驱动电路120分别与数据线DA(例如，DA1、DA2、DA3、DA4、DA5、DA6、DA7)耦接。其中，时序控制器200可以向栅极驱动电路110输入控制信号，从而使栅极驱动电路110向栅线GA(例如，GA1、GA2、GA3、GA4、GA5、GA6)输入信号，以驱动栅线GA(例如，GA1、GA2、GA3、GA4、GA5、GA6)。示例性地，时序控制器可以在当前显示帧中获取待显示画面的显示数据，并且时序控制器200向源极驱动电路120发送获取到的显示数据，可以使源极驱动电路120根据显示数据向显示面板中的数据线加载数据电压，从而对子像素充电，使各子像素充入相应的数据电压，实现画面显示功能。
示例性地，源极驱动电路120可以设置为多个，不同源极驱动电路连接 不同的数据线。例如，源极驱动电路120可以设置为2个，其中一个源极驱动电路120连接一半数量的数据线，另一个源极驱动电路120连接另一半数量的数据线。当然，源极驱动电路120也可以设置3个、4个、或更多个，其可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，每个像素单元包括多个子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
示例性地，每个子像素中可以包括晶体管像素电极。其中，一行子像素对应耦接一条栅线，以一列子像素为例，该列子像素中的奇数行子像素耦接位于该列子像素左侧的数据线，偶数行子像素耦接位于该列子像素右侧的数据线。或者，该列子像素中的奇数行子像素耦接位于该列子像素右侧的数据线，偶数行子像素耦接位于该列子像素左侧的数据线。并且，晶体管的栅极与对应的栅线电连接，晶体管的源极与对应的数据线电连接，晶体管的漏极与像素电极电连接，需要说明的是，本公开像素阵列结构还可以是双栅结构，即相邻两行像素之间设置两条栅极线，此排布方式可以减少一半的数据线，即包含相邻两列像素之间有的数据线，有的相邻两列像素之间不包括数据线，具体像素排布结构和数据线，扫描线的排布方式不限定。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板、OLED显示面板等，在此不作限定。
灰阶，一般是将最暗与最亮之间的亮度变化区分为若干份，以便于进行屏幕亮度管控。例如，以显示的图像由红、绿、蓝三种颜色组成，其中每一个颜色都可以显现出不同的亮度级别，并且不同亮度层次的红、绿、蓝组合起来，可以形成不同的色彩。例如，液晶显示面板的灰阶位数为6bit，则红、绿、蓝这三种颜色分别具有64(即2 6)个灰阶，这64个灰阶值分别为0～63。 液晶显示面板的灰阶位数为8bit，则红、绿、蓝这三种颜色分别具有256(即2 8)个灰阶，这256个灰阶值分别为0～255。液晶显示面板的灰阶位数为10bit，则红、绿、蓝这三种颜色分别具有1024(即2 10)个灰阶，这1024个灰阶值分别为0～1023。液晶显示面板的灰阶位数为12bit，则红、绿、蓝这三种颜色分别具有4096(即2 12)个灰阶，这4096个灰阶值分别为0～4093。
以液晶显示面板中的一个子像素为例，在该子像素的像素电极中输入的数据电压大于公共电极电压时，可以使该子像素处的液晶分子为正极性，则该子像素中的数据电压对应的极性为正极性。在子像素的像素电极中输入的数据电压小于公共电极电压时，可以使该子像素处的液晶分子为负极性，则该子像素中的数据电压对应的极性为负极性。例如，公共电极电压可以为8.3V，若在该子像素的像素电极中输入了8.3V～16V的数据电压，可以使该子像素处的液晶分子为正极性，则8.3V～16V的数据电压为对应正极性的数据电压。若在该子像素的像素电极中输入了0.6V～8.3V的数据电压，可以使该子像素处的液晶分子为负极性，则0.6V～8.3V的数据电压为对应负极性的数据电压。示例性地，以8bit的0～255灰阶为例，若在子像素的像素电极中输入16V的数据电压时，该子像素可以对应正极性的最大灰阶值的亮度。若在子像素的像素电极中输入0.6V的数据电压时，该子像素可以对应负极性的最大灰阶值的亮度。这样可以根据控制子像素对应的极性，使显示面板实现帧翻转方式、列翻转方式、行翻转方式、点翻转方式等。
在显示面板显示画面时，可能会由于子像素的充电率的差异导致的画面显示不良的问题。例如，在显示面板显示重载画面(例如相邻两行的灰阶值相差较大时显示的画面，如以8bit为例，重载画面可以为在相邻两行的灰阶值相差127灰阶值以上时显示的画面)时会产生串行，在显示面板显示黑白棋盘格画面时会产生线残像等问题。
以显示面板显示重载画面为例，下面以像素单元包括红色子像素，绿色子像素以及蓝色子像素为例进行说明。如图2所示，红色子像素R11、绿色子像素G11、以蓝色子像素B11为一个像素单元，红色子像素R12、绿色子像 素G12、以蓝色子像素B12为一个像素单元。红色子像素R21、绿色子像素G21、以蓝色子像素B21为一个像素单元，红色子像素R22、绿色子像素G22、以蓝色子像素B22为一个像素单元。红色子像素R31、绿色子像素G31、以蓝色子像素B31为一个像素单元，红色子像素R32、绿色子像素G32、以蓝色子像素B32为一个像素单元。红色子像素R41、绿色子像素G41、以蓝色子像素B41为一个像素单元，红色子像素R42、绿色子像素G42、以蓝色子像素B42为一个像素单元。红色子像素R51、绿色子像素G51、以蓝色子像素B51为一个像素单元，红色子像素R52、绿色子像素G52、以蓝色子像素B52为一个像素单元。红色子像素R61、绿色子像素G61、以蓝色子像素B61为一个像素单元，红色子像素R62、绿色子像素G62、以蓝色子像素B62为一个像素单元。
示例性地，如图2所示，绿色子像素G11、红色子像素R21、绿色子像素G31、红色子像素R41、绿色子像素G51、红色子像素R61与数据线DA2耦接。蓝色子像素B11、绿色子像素G21、蓝色子像素B31、绿色子像素G41、蓝色子像素B51、绿色子像素G61与数据线DA3耦接。红色子像素R12、蓝色子像素B21、红色子像素R32、蓝色子像素B41、红色子像素R52、蓝色子像素B61与数据线DA4耦接。绿色子像素G12、红色子像素R22、绿色子像素G32、红色子像素R42、绿色子像素G52、红色子像素R62与数据线DA5耦接。蓝色子像素B12、绿色子像素G22、蓝色子像素B32、绿色子像素G42、蓝色子像素B52、绿色子像素G62与数据线DA6耦接。
示例性地，以第一行子像素对应0灰阶值，第二行子像素对应192灰阶值，第三行子像素对应0灰阶值，第四行子像素对应192灰阶值，第五行子像素对应0灰阶值，第六行子像素对应192灰阶值显示形成的重载画面为例，结合图2至图4所示，驱动显示面板显示该重载画面时的过程可以如下描述。ga1代表栅线GA1上加载的信号，ga2代表栅线GA2上加载的信号，ga3代表栅线GA3上加载的信号，ga4代表栅线GA4上加载的信号，ga5代表栅线GA5上加载的信号，ga6代表栅线GA6上加载的信号。Vda2代表数据线DA2 上加载的数据电压，Vda3代表数据线DA3上加载的数据电压。并且，信号ga1～ga6中的高电平可以作为栅极开启信号，以控制子像素中的晶体管导通。以一个显示帧F01、数据线DA2和DA3、数据线DA2和DA3连接的子像素为例，栅线GA1上的信号ga1输出高电平的栅极开启信号时，绿色子像素G11和蓝色子像素B11中的晶体管导通。
在信号ga1的高电平对应的数据充电阶段T11中，对绿色子像素G11连接的数据线DA2加载对应0灰阶值的数据电压V02，以使绿色子像素G11输入目标数据电压V02。以及，在数据充电阶段T11中，栅线GA2上的信号ga2输出高电平的栅极开启信号，红色子像素R21中的晶体管导通。数据电压V02同时输入到红色子像素R21中，以对红色子像素R21进行预充电。并且，在信号ga1的高电平对应的数据充电阶段T11中，对蓝色子像素B11连接的数据线DA3加载对应0灰阶值的数据电压V02，以使蓝色子像素B11输入目标数据电压V02。以及，在数据充电阶段T11中，栅线GA2上的信号ga2输出高电平的栅极开启信号，绿色子像素G21中的晶体管导通。数据电压V02同时输入到绿色子像素G21中，以对绿色子像素G21进行预充电。
以及，在信号ga2的高电平对应的数据充电阶段T12中，对红色子像素R21连接的数据线DA2加载对应192灰阶值的数据电压V01，以使红色子像素R21充入目标数据电压V01。以及，在数据充电阶段T12中，栅线GA3上的信号ga3输出高电平的栅极开启信号，绿色子像素G31中的晶体管导通。数据电压V01同时输入到绿色子像素G31中，以对绿色子像素G31进行预充电。并且，在信号ga2的高电平对应的数据充电阶段T12中，对绿色子像素G21连接的数据线DA3加载对应192灰阶值的数据电压V01，以使绿色子像素G21充入目标数据电压V01。以及，在数据充电阶段T12中，栅线GA3上的信号ga3输出高电平的栅极开启信号，蓝色子像素B31中的晶体管导通。数据电压V01同时输入到蓝色子像素B31中，以对蓝色子像素B31进行预充电。
以及，在信号ga3的高电平对应的数据充电阶段T13中，对绿色子像素 G31连接的数据线DA2加载对应0灰阶值的数据电压V02，以使绿色子像素G31充入目标数据电压V02。以及，在数据充电阶段T13中，栅线GA4上的信号ga4输出高电平的栅极开启信号，红色子像素R41中的晶体管导通。数据电压V02同时输入到红色子像素R41中，以对红色子像素R41进行预充电。并且，在信号ga3的高电平对应的数据充电阶段T13中，对蓝色子像素B31连接的数据线DA3加载对应0灰阶值的数据电压V02，以使蓝色子像素B31充入目标数据电压V02。以及，在数据充电阶段T13中，栅线GA4上的信号ga4输出高电平的栅极开启信号，绿色子像素G41中的晶体管导通。数据电压V02同时输入到绿色子像素G41中，以对绿色子像素G41进行预充电。
以及，在信号ga4的高电平对应的数据充电阶段T14中，对红色子像素R41连接的数据线DA2加载对应192灰阶值的数据电压V01，以使红色子像素R41充入目标数据电压V01。以及，在数据充电阶段T14中，栅线GA5上的信号ga5输出高电平的栅极开启信号，绿色子像素G51中的晶体管导通。数据电压V01同时输入到绿色子像素G51中，以对绿色子像素G51进行预充电。并且，在信号ga4的高电平对应的数据充电阶段T14中，对绿色子像素G41连接的数据线DA3加载对应192灰阶值的数据电压V01，以使绿色子像素G41充入目标数据电压V01。以及，在数据充电阶段T14中，栅线GA5上的信号ga5输出高电平的栅极开启信号，蓝色子像素B51中的晶体管导通。数据电压V01同时输入到蓝色子像素B51中，以对蓝色子像素B51进行预充电。
以及，在信号ga5的高电平对应的数据充电阶段T15中，对绿色子像素G51连接的数据线DA2加载对应0灰阶值的数据电压V02，以使绿色子像素G51充入目标数据电压V02。以及，在数据充电阶段T15中，栅线GA6上的信号ga6输出高电平的栅极开启信号，红色子像素R61中的晶体管导通。数据电压V02同时输入到红色子像素R51中，以对红色子像素R51进行预充电。并且，在信号ga5的高电平对应的数据充电阶段T15中，对蓝色子像素B51连接的数据线DA3加载对应0灰阶值的数据电压V02，以使蓝色子像素B51 充目标入数据电压V02。以及，在数据充电阶段T15中，栅线GA6上的信号ga6输出高电平的栅极开启信号，绿色子像素G61中的晶体管导通。数据电压V02同时输入到绿色子像素G61中，以对绿色子像素G61进行预充电。
以及，在信号ga6的高电平对应的数据充电阶段T16中，对红色子像素R61连接的数据线DA2加载对应192灰阶值的数据电压V01，以使红色子像素R61充入目标数据电压V01，并对下一个子像素进行预充电。并且，在信号ga6的高电平对应的数据充电阶段T16中，对绿色子像素G61连接的数据线DA3加载对应192灰阶值的数据电压V01，以使绿色子像素G61充入目标数据电压V01，并对下一个子像素进行预充电。其余子像素的实施方式依次类推，直至整个显示面板中的子像素完成充入数据电压，在此不作赘述。
通过上述描述可知，结合图3与图4所示，图3中的Vda2’代表数据线DA2连接的子像素的理想状态的充电，Vda2”代表数据线DA2连接的子像素的实际充电。图4中的Vda3’代表数据线DA3连接的子像素的理想状态的充电，Vda3”代表数据线DA3连接的子像素的实际充电。由此可知，子像素预充的上一行数据电压，若没有完全被其所要充入的目标数据电压刷新，会引起该子像素出现充电不足，则会表现出串行。
通过上述描述可知，结合图5所示，ga2代表栅线GA2上传输的理想状态下的信号，ga2’代表栅线GA2上传输的实际状态下的信号，Vda2代表数据线DA2上在T12阶段传输的信号。其中，在T12阶段中红色子像素R21对应的192灰阶值的目标数据电压V01，在T13阶段中，绿色子像素G31对应0灰阶值的目标数据电压V02。这样在红色子像素R21充入目标数据电压V01后，绿色子像素G31对应的目标数据电压V02输入到了数据线DA2上。然而，在实际应用中，栅线GA2上传输的信号ga2’的下降沿会出现较大的延迟(Delay)，导致绿色子像素G31对应的目标数据电压V02输入到了数据线DA2上后，红色子像素R21还未完全关闭，从而导致红色子像素R21充入绿色子像素G31对应的目标数据电压V02，从而产生充电率不足，导致串行，造成上述重载画面中的黑线不够黑，白线不够白。甚至在串行较严重时，导致上 述重载画面为所有行全亮。
以及，在驱动显示面板显示时，可以采用不同的翻转方式来避免液晶极化。将输入正极性的目标数据电压的子像素定义为正极性子像素，将输入负极性的目标数据电压的子像素定义为负极性子像素。在实际应用中，正极性子像素与负极性子像素之间的充电率也会存在差异。由于正极性子像素中的晶体管TFT1与负极性子像素中的晶体管TFT2所处的偏压状态不一致，从而导致晶体管TFT1和晶体管TFT2的开态电流有差异。通常，在显示面板的布局(Layout)结构中，晶体管的源极和漏极采用对称结构设置，从而使源极和漏极等效。例如，结合图6所示，晶体管TFT1工作时，其栅极加载的电压VG的电压可以为30V，其源极和漏极中的一个的电压VD1可以为16V，其源极和漏极中的另一个的电压VS1可以为8V，则晶体管TFT1工作时的偏压为VG-VS1＝22V。晶体管TFT2工作时，其栅极加载的电压VG的电压可以为30V，其源极和漏极中的一个的电压VD2可以为0V，其源极和漏极中的另一个的电压VS2可以为8V，则晶体管TFT2工作时的偏压为VG-VD2＝30V。这样使得晶体管TFT2工作时的偏压大于晶体管TFT1工作时的偏压，从而导致晶体管TFT2工作时的开态电流大于晶体管TFT1工作时的开态电流，进而使得负极性子像素的充电优于正极性子像素的充电。
以及，结合图6与图7所示，在实际应用中，栅线上传输的信号ga0的下降沿会出现较大的延迟，使得晶体管的栅极电压VG在关断的过程中持续下降，导致晶体管TFT1和晶体管TFT2的关断时间不一致，从而导致负极性子像素与正极性子像素的充电存在差异。具体为：针对晶体管TFT1，当VG由30V下降至16V时，晶体管TFT1的偏压为VG-VD1＝0V，此时，其源极与漏极之间的电压也处于很小的状态(约1V)，TFT1基本处于关断状态。针对晶体管TFT2，当VG由30V下降至0V时，晶体管TFT2的偏压为VG-VD2＝0V，此时，其源极与漏极之间的电压也处于很小的状态(约1V)，TFT1基本处于关断状态。因此，正极性子像素的充电时间tc1小于负极性子像素的充电时间tc2，从而造成负极性子像素的充电优于正极性子像素的充电。
综上，由于子像素之间存在充电率差异的问题，导致显示面板会存在显示不良的问题。为了改善充电率差异的问题，本公开实施例提供了显示面板的驱动方法，结合图8所示，可以包括如下步骤：
S100、在当前显示帧中获取待显示画面的显示数据。
示例性地，获取到的显示数据可以包括每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据各子像素的显示数据，确定中各子像素对应的灰阶值。
S200、根据显示数据，对显示面板中的数据线加载数据电压，使显示面板中的各子像素充入相应的数据电压。
示例性地，以绿色子像素G21为例，可以根据上述获取到的绿色子像素G21对应的显示数据中的灰阶值，对数据线输入对应的灰阶值的数据电压，以使绿色子像素G21充入对应的灰阶值的目标数据电压。其余子像素同理，在此不作赘述。
本公开实施例提供的显示面板的驱动方法，由于数据线加载正极性的数据电压时的电压转换边沿的结束时刻与充入正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长，数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长，通过使第二目标时长大于第一目标时长，可以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
示例性地，结合图9所示，充入正极性的数据电压的子像素指的可以是正极性子像素。也就是说，该子像素是充入目标数据电压V11为正极性的子像素。充入负极性的数据电压的子像素指的可以是负极性子像素。也就是说，该子像素是充入目标数据电压V12为负极性的子像素。SB1代表数据线DA2 上加载正极性的数据电压时的电压转换边沿，并且，在数据线DA2由上一个数据电压切换为该正极性的数据电压V11时，会存在充放电的过程，该充放电过程形成了电压转换边沿SB1。SB2代表数据线DA2上加载负极性的数据电压时的电压转换边沿。并且，数据线DA2由上一个数据电压切换为该负极性的数据电压V12，会存在充放电的过程，该充放电过程形成了压转换边沿SB2。其中，数据线DA2加载正极性的数据电压V11时的电压转换边沿SB1的结束时刻与要充入该正极性的数据电压V11作为目标数据电压的子像素对应的数据充电阶段T12的开始时刻之间具有第一目标时长t1。数据线DA2加载负极性的数据电压V12时的电压转换边沿SB2的结束时刻与充入该负极性的数据电压V12作为目标数据电压的子像素对应的数据充电阶段T12的开始时刻之间具有第二目标时长t2。通过使第二目标时长t2大于第一目标时长t1，可以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，结合图9所示，可以将数据线加载正极性的数据电压时的电压转换边沿SB1的电压转换速率设置为第一转换速率，将数据线加载负极性的数据电压时的电压转换边沿SB2的电压转换速率设置为第二转换速率。这样可以根据第一转换速率将正极性的数据电压加载到数据线上，根据第二转换速率将负极性的数据电压加载到数据线上。
在本公开一些实施例中，数据线加载正极性的数据电压时的电压转换边沿的开始时刻位于充入正极性的数据电压的子像素对应的数据充电阶段的开始时刻之后，且数据线加载正极性的数据电压时的电压转换边沿的开始时刻与充入正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一间隔时长。以及，数据线加载负极性的数据电压时的电压转换边沿的开始时刻位于充入负极性的数据电压的子像素对应的数据充电阶段的开始时刻之后，且数据线加载负极性的数据电压时的电压转换边沿的开始时刻与充入 负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二间隔时长。示例性地，结合图9所示，数据线DA2加载正极性的数据电压V11时的电压转换边沿SB1的开始时刻位于要充入该正极性的数据电压V11作为目标数据电压的子像素对应的数据充电阶段T12的开始时刻之后。并且，数据线DA2加载正极性的数据电压V11时的电压转换边沿SB1的开始时刻与数据充电阶段T12的开始时刻之间具有第一间隔时长GOE1。以及，数据线DA2加载负极性的数据电压V12时的电压转换边沿SB2的开始时刻位于要充入该负极性的数据电压V12作为目标数据电压的子像素对应的数据充电阶段T12的开始时刻之后。并且，数据线DA2加载负极性的数据电压V12时的电压转换边沿SB2的开始时刻与数据充电阶段T12的开始时刻之间具有第二间隔时长GOE2。这样可以根据第一间隔时长GOE1决定何时将正极性的数据电压加载到数据线上，以及根据第二间隔时长GOE2决定何时将负极性的数据电压加载到数据线上。
在本公开一些实施例中，在步骤S100之后，且在步骤S200之前，还可以包括确定第一转换速率和第二转换速率，以确定出正极性的数据电压和负极性的数据电压的加载到数据线上速率。这样可以采用确定出的第一转换速率和第二转换速率，根据显示数据，对显示面板中的数据线加载数据电压。从而实现第二目标时长t2大于第一目标时长t1，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，可以使确定出的第二转换速率小于第一转换速率。示例性地，结合图9所示，这样可以使负极性的数据电压V12加载到数据线上充电为目标值时所用的时间大于使正极性的数据电压V11加载到数据线上充电为目标值时所用的时间，以使负极性子像素充入目标数据电压V12的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间， 这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，确定第一转换速率和第二转换速率，可以包括：从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为第一转换速率，将选取的两个设定电压转换速率中较小的作为第二转换速率。示例性地，以n＝4为例，可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。
示例性地，时序控制器还可以确定第一转换速率与第二转换速率。并根据确定出的第一转换速率生成采用数字信号表示的第一速率控制信号，根据确定出的第二转换速率生成采用数字信号表示的第二速率控制信号。并将对应第一转换速率的第一速率控制信号、对应第二转换速率的第二速率控制信号输出给源极驱动电路。这样可以使源极驱动电路接收采用数字信号表示的第一速率控制信号、第二速率控制信号，从而可以使源极驱动电路根据接收到的第一速率控制信号、第二速率控制信号以及显示数据，对显示面板中的数据线加载数据电压，使显示面板中的各子像素充入相应的数据电压。
示例性地，如图12所示，源极驱动电路120可以包括：多个电压输出单元121，一条数据线电连接一个电压输出单元。其中，电压输出单元被配置为根据接收到的第一速率控制信号、第二速率控制信号，基于显示数据，对电连接的数据线加载数据电压。例如，数据线DA1电连接一个电压输出单元121，数据线DA2电连接另一个电压输出单元121。以数据线DA1连接的电压输出单元121为例，该电压输出单元121可以根据接收到的第一速率控制信号、第二速率控制信号，基于显示数据，对电连接的数据线DA1加载相应的数据电压。例如，该电压输出单元121可以根据第一速率转换信号，基于显示数据，向数据线DA1输出对应正极性的数据电压。以及，根据第二速率转换信 号，基于显示数据，向数据线DA1输出对应负极性的数据电压。需要说明的是，其余数据线连接的电压输出单元121的工作原理与该电压输出单元121的工作原理基本相同，在此不作赘述。
示例性地，如图12所示，电压输出单元121可以包括：数模转换电路1211、数据输出电路1212、第一解码器1213以及第二解码器1214，其中，第一解码器可以根据采用数字信号表示的第一速率控制信号，解码出第一速率转换信号，并将第一速率转换信号输出给数据输出电路1212。第二解码器可以根据采用数字信号表示的第二速率控制信号，解码出第二速率转换信号，并将第二速率转换信号输出给数据输出电路1212。数模转换电路1211可以接收采用数字信号表示的显示数据，并将接收到的显示数据进行数模转换后得到采用模拟电压表示的显示数据，并将采用模拟电压表示的显示数据输出给数据输出电路1212。数据输出电路1212可以接收第一速率转换信号与第二速率转换信号以及显示输出。并根据第一速率转换信号，基于数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压。以及根据第二速率转换信号，基于数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。
示例性地，以n＝4例，表一示意出了不同设定电压转换速率对应的数字信号。其中，设定电压转换速率K_1对应的数字信号可以为0000，设定电压转换速率K_2对应的数字信号可以为0101，设定电压转换速率K_3对应的数字信号可以为1010，设定电压转换速率K_4对应的数字信号可以为1111。
示例性地，以将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率为例，时序控制器200存储了表一，在确定了设定电压转换速率K_3作为第一转换速率后，可以将1010作为第一速率控制信号发送给第一解码器1213。第一解码器1213接收到1010后，可以解码出对应1010的第一速率转换信号。该第一速率转换信号发送给数据输出电路1212。这样可以使数据输出电路1212可以根据第一速率转换信号，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压。 以及，时序控制器200在确定了设定电压转换速率K_2作为第二转换速率后，可以将0101作为第二速率控制信号发送给第一解码器1213。第一解码器1213接收到0101后，可以解码出对应0101的第二速率转换信号。该第二速率转换信号发送给数据输出电路1212。这样可以使数据输出电路1212可以根据第二速率转换信号，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。需要说明的是，表一仅是为了示例，在实际应用中，其还可以采用其他表现形式，在此不作限定。
设定电压转换速率 数字信号
K_1 0000
K_2 0101
K_3 1010
K_4 1111
表一
在本公开一些实施例中，可以使数据电压受数据触发信号的设定沿触发，输入到数据线上。并且，设定沿为上升沿和下降沿中的一个，以及，数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。示例性地，结合图9所示，可以使设定沿设置为下降沿，则数据电压受数据触发信号TP1的下降沿触发，输入到数据线上。或者，也可以使设定沿设置为上升沿，则数据电压受数据触发信号TP1的上升沿触发，输入到数据线上。由于第一间隔时长和第二间隔时长相同，可以使正极性的数据电压和负极性的数据电压对应的数据触发信号TP1的脉冲宽度相同，则可以采用同一数据触发信号TP1进行触发，降低数据触发信号的设计难度，降低计算量和功耗。
示例性地，结合图9所示，以n＝4为例，在当前显示帧可以获取到待显示画面的每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据显示数据，确定中各子像素对应的灰阶值。可以从设定 电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。以及使电压转换边沿SB2对应的第二转换速率小于电压转换边沿SB1对应的第一转换速率。这样在进入数据充电阶段后，可以采用第一转换速率(如设定电压转换速率K_3)对数据线加载数据电压V11，以及采用第二转换速率(如设定电压转换速率K_2)对数据线加载数据电压V12，从而可以使跳变为数据电压V11的电压转换边沿SB2比跳变为数据电压V12的电压转换边沿SB2要陡一些，这样相比使数据线上的电压跳变为数据电压V12的目标值，可以提前使数据线上的电压跳变为数据电压V11的目标值，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
本公开实施例提供了另一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在步骤S100之后，且在步骤S200之前，还可以包括确定第一间隔时长和第二间隔时长，以确定出正极性的数据电压和负极性的数据电压的加载到数据线上的时间。这样可以采用确定出的第一间隔时长以及第二间隔时长，根据显示数据，对显示面板中的数据线加载数据电压。从而实现第二目标时长t2大于第一目标时长t1，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，示例性地，结合图10所示，可以使确定出的第二间隔时长GOE2大于第一间隔时长GOE1。这样在进入数据充电阶段后，可 以经过第一间隔时长GOE1后开始对数据线加载正极性的数据电压V11，以将上一个的数据电压切换为当前的数据电压V11。以及经过第二间隔时长GOE2后开始对数据线加载负极性的数据电压V12，以将上一个的数据电压切换为当前的数据电压V12。这样可以进一步使负极性子像素充入目标数据电压V12的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，确定第一间隔时长、第二间隔时长，可以包括：从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为第二间隔时长，将选取的两个设定间隔时长中较小的作为第一间隔时长。示例性地，可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长。
在本公开一些实施例中，可以使数据电压受数据触发信号的设定沿触发，输入到数据线上。并且，设定沿为上升沿和下降沿中的一个，以及，数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。示例性地，结合图10所示，可以使设定沿设置为下降沿，可以采用数据触发信号TP11的下降沿来触发正极性的数据电压输入到数据线上，以及可以采用数据触发信号TP12的下降沿来触发负极性的数据电压输入到数据线上。其中，数据触发信号TP11的一个脉冲对数据触发信号TP12的一个脉冲一一对应，并使数据触发信号TP11的各脉冲的上升沿与数据触发信号TP12中对应脉冲的上升沿对其，使数据触发信号TP12的各脉冲的下降沿位于数据触发信号TP11中对应脉冲的下降沿之后。且，数据触发信号TP12的各脉冲的下降沿与数据触发信号TP11中对应脉冲的下降沿之间的间隔时长为GOE2-GOE1。或者，也可以使设定沿设置为上升沿，在此不作限定。
示例性地，以m＝4为例，表二示意出了不同设定间隔时长对应的数字信 号。其中，设定间隔时长Y_1对应的数字信号可以为0001，设定间隔时长Y_2对应的数字信号可以为0010，设定间隔时长Y_3对应的数字信号可以为0110，设定间隔时长Y_4对应的数字信号可以为0111。
示例性地，以设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长为例，时序控制器200存储了表二，时序控制器200在确定了设定间隔时长Y_2作为第一间隔时长后，可以将0010作为第一时长控制信号。该0010也发送给数据输出电路1212。这样可以使数据输出电路1212可以根据0010，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压。以及，时序控制器200在确定了设定间隔时长Y_3作为第二间隔时长后，可以将0110作为第二时长控制信号。该0110也发送给数据输出电路1212。这样可以使数据输出电路1212可以根据0110，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。需要说明的是，表二仅是为了示例，在实际应用中，其还可以采用其他表现形式，在此不作限定。
设定间隔时长 数字信号
Y_1 0001
Y_2 0010
Y_3 0110
Y_4 0111
表二
示例性地，结合图10所示，以m＝4为例，在当前显示帧可以获取到待显示画面的每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据显示数据，确定中各子像素对应的灰阶值。可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间 隔时长。这样可以使第二间隔时长GOE2大于第一间隔时长GOE1，这样在进入数据充电阶段后，可以经过第一间隔时长GOE1(如设定间隔时长Y_2)后开始对数据线加载正极性的数据电压V11，以及，可以经过第二间隔时长GOE2(如设定间隔时长Y_3)后开始对数据线加载负极性的数据电压V12。这样相比使数据线上的电压跳变为数据电压V12的目标值，可以进一步提前使数据线上的电压跳变为数据电压V11的目标值，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，在步骤S100之后，且在步骤S200之前，还可以包括确定第一转换速率、第二转换速率、第一间隔时长以及第二间隔时长，以确定出正极性的数据电压和负极性的数据电压的加载到数据线上的时间和速率。这样可以采用确定出的第一转换速率、第二转换速率、第一间隔时长以及第二间隔时长，根据显示数据，对显示面板中的数据线加载数据电压。从而实现第二目标时长t2大于第一目标时长t1，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，可以使确定出的第二转换速率小于第一转换速率。示例性地，结合图9所示，这样可以使负极性的数据电压V12加载到数据线上充电为目标值时所用的时间大于使正极性的数据电压V11加载到数据线上充电为目标值时所用的时间，以使负极性子像素充入目标数据电压V12 的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，可以使确定出的第二间隔时长等于第一间隔时长。这样在进入数据充电阶段后，可以经过同一时长开始对数据线加载正极性的数据电压和负极性的数据电压。
在本公开一些实施例中，时序控制器中预先存储了多个不同的设定电压转换速率。示例性地，预先存储的多个不同的设定电压转换速率可以包括：设定电压转换速率K_1，设定电压转换速率K_2，设定电压转换速率K_3……设定电压转换速率K_n。其中，n为大于1的整数。并且，可以使设定电压转换速率K_1至K_n依次增加。例如，以n＝4为例，K_1<K_2<K_3<K_4。在实际应用中，n的具体数值也可以设置为2、3、5等，其可以根据实际应用的需求进行确定，在此不作限定。
在本公开一些实施例中，依次增加的设定电压转换速率中的每两个设定电压转换速率之间的差值可以相同。示例性地，以n＝4为例，可以使K_2-K_1＝K_3-K_2＝K_4-K_3。这样可以采用阶梯式增加电压转换边沿的电压转换速率。
在本公开一些实施例中，时序控制器中预先存储了多个不同的设定间隔时长。示例性地，预先存储的多个不同的设定间隔时长可以包括：设定间隔时长Y_1，设定间隔时长Y_2，设定间隔时长Y_3……设定间隔时长K_m。其中，m为大于1的整数。并且，可以使设定间隔时长Y_1至Y_m依次增加。例如，以m＝4为例，Y_1<Y_2<Y_3<Y_4。在实际应用中，m的具体数值也可以设置为2、3、5等，其可以根据实际应用的需求进行确定，在此不作限定。
在本公开一些实施例中，依次增加的设定间隔时长中的每两个设定间隔时长之间的差值可以相同。示例性地，以m＝4为例，可以使Y_2-Y_1＝Y_3-Y_2＝Y_4-Y_3。这样可以采用阶梯式增加电压转换边沿的开始时刻与对 应的数据充电阶段的开始时刻之间的时长。
在本公开一些实施例中，确定第一转换速率、第二转换速率、第一间隔时长以及第二间隔时长，可以包括：从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为第一转换速率，将选取的两个设定电压转换速率中较小的作为第二转换速率。以及，从预先存储的多个不同的设定间隔时长中选取一个设定间隔时长，分别作为第一间隔时长和第二间隔时长。示例性地，以n＝4，m＝4为例，可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。以及，可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取设定间隔时长Y_2，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_2作为第二间隔时长。
示例性地，时序控制器还可以确定第一转换速率、第二转换速率、第一间隔时长以及第二间隔时长。并根据确定出的第一转换速率生成采用数字信号表示的第一速率控制信号，根据确定出的第二转换速率生成采用数字信号表示的第二速率控制信号，根据确定出的第一间隔时长生成采用数字信号表示的第一时长控制信号，以及根据确定出的第二间隔时长生成采用数字信号表示的第二时长控制信号。并将对应第一转换速率的第一速率控制信号、对应第二转换速率的第二速率控制信号、对应第一间隔时长的第一时长控制信号以及对应第二间隔时长的第二时长控制信号输出给源极驱动电路。这样可以使源极驱动电路接收采用数字信号表示的第一速率控制信号、第二速率控制信号、第一时长控制信号以及第二时长控制信号，从而可以使源极驱动电路根据接收到的第一速率控制信号、第二速率控制信号、第一时长控制信号、第二时长控制信号以及显示数据，对显示面板中的数据线加载数据电压，使显示面板中的各子像素充入相应的数据电压。
示例性地，如图12所示，源极驱动电路120可以包括：多个电压输出单元121，一条数据线电连接一个电压输出单元。其中，电压输出单元被配置为 根据接收到的第一速率控制信号、第二速率控制信号、第一时长控制信号、第二时长控制信号，基于显示数据，对电连接的数据线加载数据电压。例如，数据线DA1电连接一个电压输出单元121，数据线DA2电连接另一个电压输出单元121。以数据线DA1连接的电压输出单元121为例，该电压输出单元121可以根据接收到的第一速率控制信号、第二速率控制信号、第一时长控制信号、第二时长控制信号，基于显示数据，对电连接的数据线DA1加载相应的数据电压。例如，该电压输出单元121可以根据第一速率转换信号和第一时长控制信号，基于显示数据，向数据线DA1输出对应正极性的数据电压。以及，根据第二速率转换信号和第二时长控制信号，基于显示数据，向数据线DA1输出对应负极性的数据电压。需要说明的是，其余数据线连接的电压输出单元121的工作原理与该电压输出单元121的工作原理基本相同，在此不作赘述。
示例性地，如图12所示，电压输出单元121可以包括：数模转换电路1211、数据输出电路1212、第一解码器1213以及第二解码器1214，其中，第一解码器可以根据采用数字信号表示的第一速率控制信号，解码出第一速率转换信号，并将第一速率转换信号输出给数据输出电路1212。第二解码器可以根据采用数字信号表示的第二速率控制信号，解码出第二速率转换信号，并将第二速率转换信号输出给数据输出电路1212。数模转换电路1211可以接收采用数字信号表示的显示数据，并将接收到的显示数据进行数模转换后得到采用模拟电压表示的显示数据，并将采用模拟电压表示的显示数据输出给数据输出电路1212。数据输出电路1212可以接收第一速率转换信号、第一时长控制信号、第二速率转换信号、第二时长控制信号以及显示输出。并根据第一速率转换信号和第一时长控制信号，基于数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压。以及根据第二速率转换信号和第二时长控制信号，基于数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。
示例性地，以n＝4，m＝4为例，表一示意出了不同设定电压转换速率对应 的数字信号。表二示意出了不同设定间隔时长对应的数字信号。其中，设定电压转换速率K_1对应的数字信号可以为0000，设定电压转换速率K_2对应的数字信号可以为0101，设定电压转换速率K_3对应的数字信号可以为1010，设定电压转换速率K_4对应的数字信号可以为1111。设定间隔时长Y_1对应的数字信号可以为0001，设定间隔时长Y_2对应的数字信号可以为0010，设定间隔时长Y_3对应的数字信号可以为0110，设定间隔时长Y_4对应的数字信号可以为0111。
示例性地，以将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率，将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_2作为第二间隔时长为例，时序控制器200存储了表一和表二，在确定了设定电压转换速率K_3作为第一转换速率后，可以将1010作为第一速率控制信号发送给第一解码器1213。第一解码器1213接收到1010后，可以解码出对应1010的第一速率转换信号。该第一速率转换信号发送给数据输出电路1212。并且，时序控制器200在确定了设定间隔时长Y_2作为第一间隔时长后，可以将0010作为第一时长控制信号。该0010也发送给数据输出电路1212。这样可以使数据输出电路1212可以根据第一速率转换信号和0010，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压。以及，时序控制器200在确定了设定电压转换速率K_2作为第二转换速率后，可以将0101作为第二速率控制信号发送给第一解码器1213。第一解码器1213接收到0101后，可以解码出对应0101的第二速率转换信号。该第二速率转换信号发送给数据输出电路1212。并且，时序控制器200在确定了设定间隔时长Y_2作为第二间隔时长后，可以将0010作为第二时长控制信号。该0010也发送给数据输出电路1212。这样可以使数据输出电路1212可以根据第二速率转换信号和0010，并基于数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。需要说明的是，表一和表二仅是为了示例，在实际应用中，其还可以采用其他表现形式，在此不作限定。
示例性地，结合图9所示，以n＝4，m＝4为例，在当前显示帧可以获取到待显示画面的每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据显示数据，确定中各子像素对应的灰阶值。可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。以及，可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取设定间隔时长Y_2，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_2作为第二间隔时长。这样可以使第二间隔时长GOE2等于第一间隔时长GOE1，以及使电压转换边沿SB2对应的第二转换速率小于电压转换边沿SB1对应的第一转换速率。这样在进入数据充电阶段后，可以同时开始对数据线加载数据电压V11和数据电压V12。并且，采用第一转换速率(如设定电压转换速率K_3)对数据线加载数据电压V11，以及采用第二转换速率(如设定电压转换速率K_2)对数据线加载数据电压V12，从而可以使跳变为数据电压V11的电压转换边沿SB2比跳变为数据电压V12的电压转换边沿SB2要陡一些，这样相比使数据线上的电压跳变为数据电压V12的目标值，可以提前使数据线上的电压跳变为数据电压V11的目标值，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
本公开实施例提供了另一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，可以使确定出的第二转换速率小于第一转换速率。示例性地，结合图10所示，这样可以使负极性的数据电压V12加载到数据线上充电为目标值时所用的时间大于使正极性的数据电压V11加载到数据线上充电为目标值时所用的时间，以使负极性子像素充入目标数据电压V12 的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，确定第一转换速率、第二转换速率，可以包括：从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为第一转换速率，将选取的两个设定电压转换速率中较小的作为第二转换速率。示例性地，以n＝4为例，可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。
在本公开一些实施例中，示例性地，结合图10所示，可以使确定出的第二间隔时长GOE2大于第一间隔时长GOE1。这样在进入数据充电阶段后，可以经过第一间隔时长GOE1后开始对数据线加载正极性的数据电压V11，以将上一个的数据电压切换为当前的数据电压V11。以及经过第二间隔时长GOE2后开始对数据线加载负极性的数据电压V12，以将上一个的数据电压切换为当前的数据电压V12。这样可以进一步使负极性子像素充入目标数据电压V12的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，确定第一间隔时长、第二间隔时长，可以包括：从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为第二间隔时长，将选取的两个设定间隔时长中较小的作为第一间隔时长。示例性地，可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长。
在本公开一些实施例中，可以使数据电压受数据触发信号的设定沿触发，输入到数据线上。并且，设定沿为上升沿和下降沿中的一个，以及，数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。示例性地，结合图10所示，可以使设定沿设置为下降沿，可以采用数据触发信号TP11的下降沿来触发正极性的数据电压输入到数据线上，以及可以采用数据触发信号TP12的下降沿来触发负极性的数据电压输入到数据线上。其中，数据触发信号TP11的一个脉冲对数据触发信号TP12的一个脉冲一一对应，并使数据触发信号TP11的各脉冲的上升沿与数据触发信号TP12中对应脉冲的上升沿对其，使数据触发信号TP12的各脉冲的下降沿位于数据触发信号TP11中对应脉冲的下降沿之后。且，数据触发信号TP12的各脉冲的下降沿与数据触发信号TP11中对应脉冲的下降沿之间的间隔时长为GOE2-GOE1。或者，也可以使设定沿设置为上升沿，在此不作限定。
示例性地，结合图10所示，以n＝4，m＝4为例，在当前显示帧可以获取到待显示画面的每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据显示数据，确定中各子像素对应的灰阶值。可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2、K_3，并将设定电压转换速率K_3作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。以及，从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长。这样可以使第二间隔时长GOE2大于第一间隔时长GOE1，以及使电压转换边沿SB2对应的第二转换速率小于电压转换边沿SB1对应的第一转换速率。这样在进入数据充电阶段后，可以经过第一间隔时长GOE1(如设定间隔时长Y_2)后开始对数据线加载正极性的数据电压V11，并采用第一转换速率(如设定电压转换速率K_3)将上一个的数据电压切换为当前的数据电压V11。以及，在进入数据充电阶段后，可以经过第二间隔时长GOE2(如设定间隔时长Y_3)后开始对数据线加载负极性的数据电压V12，并采用第二转换速率(如设定电压转换速率K_2)将 上一个的数据电压切换为当前的数据电压V12。这样相比使数据线上的电压跳变为数据电压V12的目标值，可以进一步提前使数据线上的电压跳变为数据电压V11的目标值，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
本公开实施例提供了又一些显示面板的驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开一些实施例中，示例性地，结合图11所示，可以使确定出的第二间隔时长GOE2大于第一间隔时长GOE1。这样在进入数据充电阶段后，可以经过第一间隔时长GOE1后开始对数据线加载正极性的数据电压V11，以将上一个的数据电压切换为当前的数据电压V11。以及经过第二间隔时长GOE2后开始对数据线加载负极性的数据电压V12，以将上一个的数据电压切换为当前的数据电压V12。这样可以进一步使负极性子像素充入目标数据电压V12的最大值的时间晚于正极性子像素充入目标数据电压V11的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
在本公开一些实施例中，确定第一间隔时长、第二间隔时长，可以包括：从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为第二间隔时长，将选取的两个设定间隔时长中较小的作为第一间隔时长。示例性地，可以从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长。
在本公开一些实施例中，可以使确定出的第二转换速率等于第一转换速 率。示例性地，结合图11所示，这样可以使负极性的数据电压V12加载到数据线上充电为目标值时所用的时间等于使正极性的数据电压V11加载到数据线上充电为目标值时所用的时间。
在本公开一些实施例中，确定第一转换速率、第二转换速率，可以包括：从预先存储的多个不同的设定电压转换速率中选取一个设定电压转换速率，分别作为第一转换速率和第二转换速率。示例性地，以n＝4为例，可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2，并将设定电压转换速率K_2作为第一转换速率，以及将设定电压转换速率K_2作为第二转换速率。
在本公开一些实施例中，可以使数据电压受数据触发信号的设定沿触发，输入到数据线上。并且，设定沿为上升沿和下降沿中的一个，以及，数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。示例性地，结合图11所示，可以使设定沿设置为下降沿，可以采用数据触发信号TP11的下降沿来触发正极性的数据电压输入到数据线上，以及可以采用数据触发信号TP12的下降沿来触发负极性的数据电压输入到数据线上。其中，数据触发信号TP11的一个脉冲对数据触发信号TP12的一个脉冲一一对应，并使数据触发信号TP11的各脉冲的上升沿与数据触发信号TP12中对应脉冲的上升沿对其，使数据触发信号TP12的各脉冲的下降沿位于数据触发信号TP11中对应脉冲的下降沿之后。且，数据触发信号TP12的各脉冲的下降沿与数据触发信号TP11中对应脉冲的下降沿之间的间隔时长为GOE2-GOE1。或者，也可以使设定沿设置为上升沿，在此不作限定。
示例性地，结合图11所示，以n＝4，m＝4为例，在当前显示帧可以获取到待显示画面的每一个子像素一一对应的携带有相应灰阶值的数据电压的数字信号形式。这样可以根据显示数据，确定中各子像素对应的灰阶值。可以从设定电压转换速率K_1、K_2、K_3、K_4中选取设定电压转换速率K_2，并将设定电压转换速率K_2作为第一转换速率，将设定电压转换速率K_2作为第二转换速率。以及，从设定间隔时长Y_1、Y_2、Y_3、Y_4中选取两个 设定间隔时长Y_2和Y_3，并将设定间隔时长Y_2作为第一间隔时长，以及将设定间隔时长Y_3作为第二间隔时长。这样可以使第二间隔时长GOE2大于第一间隔时长GOE1，以及使电压转换边沿SB2对应的第二转换速率等于电压转换边沿SB1对应的第一转换速率。这样在进入数据充电阶段后，可以经过第一间隔时长GOE1(如设定间隔时长Y_2)后开始对数据线加载正极性的数据电压V11，并采用第一转换速率(如设定电压转换速率K_2)将上一个的数据电压切换为当前的数据电压V11。以及，在进入数据充电阶段后，可以经过第二间隔时长GOE2(如设定间隔时长Y_3)后开始对数据线加载负极性的数据电压V12，并采用第二转换速率(如设定电压转换速率K_2)将上一个的数据电压切换为当前的数据电压V12。这样相比使数据线上的电压跳变为数据电压V12的目标值，可以提前使数据线上的电压跳变为数据电压V11的目标值，以使负极性子像素充入目标数据电压的最大值的时间晚于正极性子像素充入目标数据电压的最大值的时间，这样可以等同于降低负极性子像素的充电率，提高正极性子像素的充电率，从而使正极性子像素和负极性子像素之间的充电率差异尽可能降低，改善显示面板的显示不良的问题。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的 装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种显示面板的驱动方法，包括：
    在当前显示帧中获取待显示画面的显示数据；
    根据所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压；
    其中，所述数据线加载正极性的数据电压时的电压转换边沿的结束时刻与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长；所述数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长；所述第二目标时长大于所述第一目标时长。
  2. 如权利要求1所述的显示面板的驱动方法，其中，所述数据线加载正极性的数据电压时的电压转换边沿的电压转换速率为第一转换速率；
    所述数据线加载负极性的数据电压时的电压转换边沿的电压转换速率为第二转换速率；
    所述数据线加载正极性的数据电压时的电压转换边沿的开始时刻位于充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之后；且所述数据线加载正极性的数据电压时的电压转换边沿的开始时刻与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一间隔时长；
    所述数据线加载负极性的数据电压时的电压转换边沿的开始时刻位于充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之后；且所述数据线加载负极性的数据电压时的电压转换边沿的开始时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二间隔时长；
    在所述在当前显示帧中获取待显示画面的显示数据之后，且在所述根据所述显示数据，对所述显示面板中的数据线加载数据电压之前，还包括：
    确定所述第一转换速率与所述第二转换速率，和/或所述第一间隔时长与所述第二间隔时长；
    所述根据所述显示数据，对所述显示面板中的数据线加载数据电压，包括：
    采用确定出的所述第一转换速率与所述第二转换速率，和/或所述第一间隔时长与所述第二间隔时长，根据所述显示数据，对所述显示面板中的数据线加载数据电压。
  3. 如权利要求2所述的显示面板的驱动方法，其中，确定出的所述第二转换速率小于所述第一转换速率。
  4. 如权利要求3所述的显示面板的驱动方法，其中，所述确定所述第一转换速率和所述第二转换速率，包括：
    从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为所述第一转换速率，将选取的两个设定电压转换速率中较小的作为所述第二转换速率。
  5. 如权利要求2-4任一项所述的显示面板的驱动方法，其中，确定出的所述第二间隔时长大于所述第一间隔时长。
  6. 如权利要求5所述的显示面板的驱动方法，其中，所述确定所述第一间隔时长和所述第二间隔时长，包括：
    从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为所述第二间隔时长，将选取的两个设定间隔时长中较小的作为所述第一间隔时长。
  7. 如权利要求2所述的显示面板的驱动方法，其中，确定出的所述第二转换速率小于所述第一转换速率，确定出的所述第二间隔时长等于所述第一间隔时长。
  8. 如权利要求7所述的显示面板的驱动方法，其中，所述确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，包括：
    从预先存储的多个不同的设定电压转换速率中选取两个设定电压转换速率，并将选取的两个设定电压转换速率中较大的作为所述第一转换速率，将选取的两个设定电压转换速率中较小的作为所述第二转换速率；
    从预先存储的多个不同的设定间隔时长中选取一个设定间隔时长，分别作为所述第一间隔时长和所述第二间隔时长。
  9. 如权利要求2所述的显示面板的驱动方法，其中，确定出的所述第二转换速率等于所述第一转换速率，确定出的所述第二间隔时长大于所述第一间隔时长。
  10. 如权利要求9所述的显示面板的驱动方法，其中，所述确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，包括：
    从预先存储的多个不同的设定电压转换速率中选取一个设定电压转换速率，分别作为所述第一转换速率和所述第二转换速率；
    从预先存储的多个不同的设定间隔时长中选取两个设定间隔时长，并将选取的两个设定间隔时长中较大的作为所述第二间隔时长，将选取的两个设定间隔时长中较小的作为所述第一间隔时长。
  11. 如权利要求1-10任一项所述的显示面板的驱动方法，其中，所述数据电压受数据触发信号的设定沿触发，输入到所述数据线上；所述设定沿为上升沿和下降沿中的一个；
    所述数据电压时的电压转换边沿的开始时刻与对应的设定沿对齐。
  12. 一种显示装置，包括：
    显示面板，包括源极驱动电路；
    时序控制器，被配置为在当前显示帧中获取待显示画面的显示数据；并将所述显示数据发送给所述源极驱动电路；
    所述源极驱动电路被配置为根据所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压；
    其中，所述数据线加载正极性的数据电压时的电压转换边沿的结束时刻 与充入所述正极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第一目标时长；所述数据线加载负极性的数据电压时的电压转换边沿的结束时刻与充入所述负极性的数据电压的子像素对应的数据充电阶段的开始时刻之间具有第二目标时长；所述第二目标时长大于所述第一目标时长。
  13. 如权利要求12所述的显示装置，其中，所述显示面板包括源极驱动电路；
    所述时序控制器还被配置为确定所述第一转换速率、所述第二转换速率、所述第一间隔时长以及所述第二间隔时长，并输出对应所述第一转换速率的第一速率控制信号、对应所述第二转换速率的第二速率控制信号、对应所述第一间隔时长的第一时长控制信号以及对应所述第二间隔时长的第二时长控制信号给所述源极驱动电路；
    所述源极驱动电路还被配置为根据接收到的所述第一速率控制信号、所述第二速率控制信号、所述第一时长控制信号、所述第二时长控制信号以及所述显示数据，对所述显示面板中的数据线加载数据电压，使所述显示面板中的各子像素充入相应的数据电压。
  14. 如权利要求13所述的显示装置，其中，所述源极驱动电路包括：多个电压输出单元，一条所述数据线电连接一个所述电压输出单元；
    所述电压输出单元被配置为根据接收到的所述第一速率控制信号、所述第二速率控制信号、所述第一时长控制信号、所述第二时长控制信号，基于所述显示数据，对电连接的数据线加载数据电压。
  15. 如权利要求14所述的显示装置，其中，所述电压输出单元包括：数模转换电路、数据输出电路、第一解码器以及第二解码器；
    所述数模转换电路被配置为接收所述显示数据，并将接收到的所述显示数据进行数模转换后的，输出给所述数据输出电路；
    所述第一解码器被配置为根据所述第一速率控制信号，解码出第一速率转换信号；
    所述第二解码器被配置为根据所述第二速率控制信号，解码出第二速率 转换信号；
    所述数据输出电路被配置为接收所述第一速率转换信号、所述第一时长控制信号、所述第二速率转换信号以及所述第二时长控制信号；并根据所述第一速率转换信号和所述第一时长控制信号，基于所述数模转换电路输出的显示数据，向电连接的数据线输出对应正极性的数据电压；以及，根据所述第二速率转换信号和所述第二时长控制信号，基于所述数模转换电路输出的显示数据，向电连接的数据线输出对应负极性的数据电压。
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