WO2023103059A1 - 背光源以及显示装置 - Google Patents

背光源以及显示装置 Download PDF

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Publication number
WO2023103059A1
WO2023103059A1 PCT/CN2021/139356 CN2021139356W WO2023103059A1 WO 2023103059 A1 WO2023103059 A1 WO 2023103059A1 CN 2021139356 W CN2021139356 W CN 2021139356W WO 2023103059 A1 WO2023103059 A1 WO 2023103059A1
Authority
WO
WIPO (PCT)
Prior art keywords
pads
signal output
light
signal input
wiring
Prior art date
Application number
PCT/CN2021/139356
Other languages
English (en)
French (fr)
Inventor
刘净
邓红照
崔正波
陈昊
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/622,802 priority Critical patent/US20240027834A1/en
Priority to JP2021577689A priority patent/JP2024506422A/ja
Publication of WO2023103059A1 publication Critical patent/WO2023103059A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133612—Electrical details
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/3413—Details of control of colour illumination sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other

Definitions

  • the present application relates to the technical field of display panels, in particular to a backlight source and a display device.
  • Mini Light Emitting Diode also known as “submillimeter light emitting diode” refers to an LED with a grain (chip) size of 50 microns to 200 microns.
  • the application direction includes Mini LED display screen and LCD with Mini LED backlight screen. Since the Mini LED display has excellent performance in terms of energy consumption, color gamut, and contrast, the process is not as difficult as the Micro LED display. LED is so big, so Mini LED is expected to become the leading product for LCD upgrade.
  • Existing backlight products on the market are based on two or more layers of metal wiring.
  • the metal routing method of two or more layers has problems such as easy short-circuiting between different metal layers and high cost.
  • the channels of existing driver ICs on the market are not compatible with single-layer metal designs.
  • Embodiments of the present application provide a backlight source and a display device to solve the problems of easy short-circuit between different metal layers and high cost of backlight products in the prior art.
  • An embodiment of the present application provides a backlight, and the backlight includes:
  • the circuit layer is arranged on the substrate;
  • the driving chip is arranged on the circuit layer and is located between the adjacent light emitting units, and is used to drive the light emitting units to emit light; wherein, the circuit layer includes signal input wiring and signal output wiring arranged on the same layer line, a plurality of light control lines and corresponding signal input pads, signal output pads and a plurality of light control pads, the signal input lines are connected to the signal input pads, and the signal output lines are connected to the signal output lines.
  • the signal output pads are connected, the light control lines are connected to the light control pads, the signal input pads, the signal output pads and the light control pads are respectively connected to the driver chip
  • a plurality of the light control pads are respectively located at a plurality of ends of the driving chip close to the light emitting unit, and the signal input wiring and the signal output wiring are located between the light control pads. for transmitting signals to the driver chip.
  • the circuit layer further includes: data wires and data pads connected to the data wires, wherein the data pads are arranged on the plurality of light control pads between the pads, and the data routing and the multiple light control routings, the signal input routing and the signal output routing are all arranged on the same layer, the signal input routing and the signal output The traces are on the same extension line.
  • the data traces and the plurality of light control traces, the signal input traces and the signal output traces are not interleaved with each other.
  • the circuit layer further includes: a power supply line, and a power pad connected to the power line, wherein the power supply pad is arranged on the plurality of light control between the pads, and the power wiring and the plurality of light control wirings, the signal input wiring and the signal output wiring are arranged on the same layer.
  • the power supply wiring and the plurality of light control wirings, the signal input wiring and the signal output wiring are not interlaced with each other.
  • the circuit layer further includes: ground traces and ground pads connected to the ground traces, the backlight also includes a plurality of partitions, each of the partitions The shape is quadrangular, including 4 light-emitting units, which are respectively distributed in the four corners of the partition, and each partition includes 4 light-controlling pads, and the 4 light-controlling pads define quadrangular pads
  • the ground pad, the signal input pad and the signal output pad are all arranged in the pad area.
  • the multiple partitions are arranged in multiple columns, and the circuit layer further includes auxiliary ground wiring, and the ground wiring of the last partition of each column of the partitions The end of the is connected to the auxiliary ground trace.
  • the multiple partitions are arranged in multiple rows, wherein the signal output wiring of the last partition of the first row of partitions is connected to the last of the second row of partitions The signal input wiring of the partition.
  • the multiple partitions are arranged in multiple rows, and in each row of the partitions, the signal output wiring of the previous partition is connected to the signal input wiring of the next partition.
  • the circuit layer includes high potential wirings, each of the high potential wirings is located between adjacent light emitting units and is connected to the other end of the light emitting units at the same time.
  • the light emitting unit includes a plurality of mini Light Emitting Diodes (mini Light Emitting Diode, mini-LED).
  • the present application provides a display device, including a backlight, and a liquid crystal display panel disposed on the backlight, wherein the backlight includes: a substrate;
  • circuit layer disposed on the substrate
  • the driving chip is arranged on the circuit layer and is located between the adjacent light emitting units, and is used to drive the light emitting units to emit light; wherein, the circuit layer includes signal input wiring and signal output wiring arranged on the same layer line, a plurality of light control lines and corresponding signal input pads, signal output pads and a plurality of light control pads, the signal input lines are connected to the signal input pads, and the signal output lines are connected to the signal output lines.
  • the signal output pads are connected, the light control lines are connected to the light control pads, the signal input pads, the signal output pads and the light control pads are respectively connected to the driver chip
  • a plurality of the light control pads are respectively located at a plurality of ends of the driving chip close to the light emitting unit, and the signal input wiring and the signal output wiring are located between the light control pads. for transmitting signals to the driver chip.
  • the backlight source further includes a backlight control unit connected to the driving chip to provide brightness data of the driving chip.
  • the liquid crystal display panel further includes a liquid crystal control unit connected to the liquid crystal display panel to control the liquid crystal display panel to display.
  • the display device in some embodiments of the present application further includes an image signal source, wherein both the backlight control unit and the liquid crystal control unit are connected to the image signal source, and the liquid crystal control unit is used to control the liquid crystal display panel
  • the image data provided by the image signal source is displayed, and the backlight control unit is used for performing regional dimming in accordance with the image data provided by the image signal source.
  • the backlight source and the display device provided by the present application include signal input wiring, signal output wiring, multiple light control wiring and corresponding A signal input pad, a signal output pad, and a plurality of light control pads, the plurality of light control pads are respectively located at multiple ends of the drive chip close to the light emitting unit, the signal input wiring, the The signal output wiring is located between the light control pads and is used for transmitting signals to the driving chip. It only needs to change the pin position of the existing driver chip on the market, without redesigning the driver chip itself, it can meet the requirements of single-layer metal wiring, the cost is low, and there is no short circuit between different metal layers. rate problem.
  • FIG. 1 is a schematic structural diagram of a backlight source provided by an embodiment of the present application
  • Fig. 2 is a schematic structural diagram of a substrate and a circuit layer provided in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a partition provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a circuit layer structure in a partition provided by an embodiment of the present application.
  • Fig. 5 is a schematic cross-sectional structure diagram of the partition along the AA line of Fig. 3;
  • FIG. 6 is a schematic diagram of a circuit layer structure in a partition provided by another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a circuit layer structure in a partition provided by another embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of a backlight provided by another embodiment of the present application.
  • Fig. 9 is a schematic structural diagram of a backlight provided by another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more.
  • the term “comprise” and any variations thereof, are intended to cover a non-exclusive inclusion.
  • connection should be understood in a broad sense, for example, it can be a support connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 wherein, FIG. 2 and FIG. 4 do not show the driver chip DU so that the wiring under the driver chip DU can be clearly shown in the figure.
  • the embodiment of the present application provides a backlight source 100, and the backlight source 100 includes a substrate SB, a circuit layer CL, a plurality of light emitting units LU and a driving chip DU.
  • the circuit layer CL is arranged on the substrate SB; a plurality of light-emitting unit LU arrays are arranged on the circuit layer CL; the driving chip DU is arranged on the circuit layer CL, including a plurality of pins PN and located adjacent to the light-emitting Between the units LU, it is used to drive the light-emitting unit LU to emit light; wherein, the circuit layer CL includes a signal input line DIL, a signal output line DOL, a plurality of light control lines OL and corresponding signal lines arranged on the same layer.
  • Input pad DIP, signal output pad DOP and multiple light control pads OP the signal input trace DIL is connected to the signal input pad DIP, the signal output trace DOL is connected to the signal output pad
  • the light control line OL is connected to the light control pad OP, the signal input pad DIP, the signal output pad DOP and the light control pad OP are respectively connected to the driver chip DU
  • the plurality of light control pads OP are respectively located at multiple ends of the driving chip DU close to the light emitting unit LU, the signal input wiring DIL and the signal output wiring DOL are located at the light control pads
  • the pads OP are used for transmitting signals to the driving chip DU.
  • the plurality of light control traces OL, the ground traces GL, the signal input traces DIL and the signal output traces DOL are all arranged on the same layer, for example, one layer is arranged on the substrate SB
  • the pattern of the plurality of light control lines OL, the ground lines GL, the signal input lines DIL and the signal output lines DOL is formed through the exposure and development process of the metal copper film. It can meet the requirements of single-layer metal wiring, the cost is low, and there is no yield problem such as short circuit between different metal layers.
  • the circuit layer CL includes high-potential wiring HL, and each of the high-potential wiring HL is located between adjacent light-emitting units LU and connected to the light-emitting units at the same time the other end of the LU.
  • the ground pad GP, the signal input pad DIP and the signal output pad DOP are all arranged on the plurality of light control pads between the OPs, so that the plurality of light-control pads OP is located at the outermost side of the pad area PA, therefore, the wiring required for the driving chip DU arranged between the plurality of light-emitting units LU, such as the The ground traces GL, the signal input traces DIL, and the signal output traces DOL can run between two adjacent rows of light-emitting units LU and directly pull the traces from the fan-out area FA to the edge of the substrate SB, It will not intersect with the light-control wiring OL or high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wiring, with low cost and no yield problems such as short-circuiting between different metal layers .
  • the light emitting unit LU is a mini light emitting diode (mini Light Emitting Diode, mini-LED).
  • the light emitting unit LU is a light emitting diode (Light Emitting Diode, LED), an organic light emitting diode (Organic Light Emitting Diode, OLED) or Micro Light Emitting Diode (Micro Light Emitting Diode, micro-LED), etc., the present application is not limited thereto.
  • the number of light-emitting components such as mini-LED or micro-LED in the light-emitting unit LU is at least one, and can also be two lights, four lights, six lights, eight lights, ten lights, twelve lights, fourteen lights, sixteen lights One of a kind.
  • a plurality of light-emitting components can be connected in series, or first connected in series and then in parallel to form multiple rows of light-emitting components, the application is not limited thereto.
  • the distance between each lamp is also not limited.
  • the materials of the substrate SB include glass, printed circuit board (Printed Circuit Board, PCB) or BT resin board (Bismaleimide Triazine, BT).
  • the circuit layer CL is disposed on the substrate SB.
  • the light emitting unit LU and the driving chip DU are disposed on the circuit layer CL.
  • the driver chip DU is packaged in Ball Grid Array (BGA), Lead Frame, Surface Mounted Devices package (SMD package) or other packaging methods.
  • BGA Ball Grid Array
  • SMD package Surface Mounted Devices package
  • the drawings of the present application all take the BGA package as an example, but the present application is not limited thereto.
  • the multiple pins PN of the driver chip DU refer to pins in a lead frame package or solder balls in a ball grid array package.
  • the packaging size of the driving chip DU is smaller than 1500 ⁇ m*1500 ⁇ m.
  • the signal input wiring DIL is used to provide the brightness data required by the driving chip DU for each light emitting unit LU and the corresponding address data of the light emitting unit LU. And in a cascaded manner, the signal is transmitted from the signal output line DOL to the driver chip DU of the next partition MD.
  • the circuit layer CL further includes: data wiring DL and a data connection connecting the data wiring DL.
  • Pad DP Pad DP.
  • the data wiring DL is used to provide the driver chip DU with pulse-width modulation (Pulse-Width Modulation, PWM), address data or scanning signals, etc., depending on the design of the driver chip DU, and the present application is not limited thereto.
  • the data pad DP is disposed between the plurality of light control pads OP, and the data line DL and the plurality of light control lines OL, the signal input line DIL and the signal output
  • the wires DOL are all arranged on the same layer, and one of the plurality of pins PN of the driving chip DU contacts the data pad DP.
  • the signal input wiring DIL and the signal output wiring DOL are located on the same extension line.
  • another data structure of the signal input wiring DIL, the signal output wiring DOL, and the data wiring DL is a daisy chain structure (Daisy Chain), and the address passes through the signal input wiring DIL, The signal output line DOL is transmitted, and the luminance data is transmitted to all the driving chips DU through the data line DL at the same time, the application is not limited thereto.
  • the data lines DL and the plurality of light control lines OL, the signal input lines DIL, and the signal output lines DOL are not connected to each other. staggered. Specifically, the data lines DL, the plurality of light control lines OL, the signal input lines DIL and the signal output lines DOL are used to transmit different signals from each other, so they must be insulated from each other. The data lines DL, the plurality of light control lines OL, the signal input lines DIL and the signal output lines DOL are all disposed on the same metal layer, so there is no crossing between lines.
  • the circuit layer CL further includes: a power line PL, and a power pad PP connected to the power line PL.
  • the power line PL is used to provide the power required for the operation of the driving chip DU itself.
  • the power pad PP is disposed between the plurality of light control pads OP, and the power line PL is connected to the plurality of light control lines OL, the signal input line DIL and the signal output
  • the traces DOL are all arranged on the same layer, and one of the plurality of pins PN of the driving chip DU contacts the power pad PP.
  • the power supply line PL and the plurality of light control lines OL, the signal input line DIL, and the signal output line DOL are not connected to each other. staggered.
  • the circuit layer CL further includes a ground line GL and a ground pad GP connected to the ground line GL, and the backlight further includes a plurality of partitions MD.
  • each of the subregions MD is quadrangular in shape, includes four light emitting units LU, and are respectively distributed in the four corners of the subregion MD, and each of the subregions MD It includes 4 light control pads OP, the 4 light control pads OP define a quadrilateral pad area PA, the ground pad GP, the signal input pad DIP and the signal output pad DOP are all disposed in the pad area PA.
  • the pad area PA of the embodiment of the present application 10 pads are arranged in two rows, 2 rows ⁇ 5 columns, wherein the pad area PA The four corners are the four light control pads OP, the signal input pad DIP, the signal output pad DOP in the same row, the other power pad PP, ground pad GP, vacant pad NP, data pad DP
  • the positions can be replaced with each other, and the corresponding wiring design needs to be replaced synchronously when replacing each other.
  • the upper row from left to right is the light control pad OP, the power pad PP, the signal input pad DIP, the ground pad GP and the other One light control pad OP.
  • the bottom row from left to right is: light control pad OP, vacant pad NP, signal output pad DOP, data pad DP and another light control pad OP.
  • the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP are all arranged between the four light control pads OP, so that the connection of the power pad
  • the wiring of pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP can be centrally arranged between adjacent light-emitting units LU, and directly by fan-out
  • the wires drawn from the area FA to the edge of the substrate SB will not intersect with the light-control wires OL or high-potential wires HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wires, with low cost and no Yield issues such as shorting between different metal layers.
  • the present application does not limit the package pins of the driver chip DU, the names of the pins, and the functions of the pins.
  • the shape of each pad such as circle, square, rectangle, etc., is not limited in the present application.
  • a plurality of pads are arranged in two rows, and the control pads on the upper row are sequentially arranged from left to right.
  • the lower row from left to right is: light control pad OP, signal output pad DOP, vacant pad NP, data pad DP and another light control pad OP.
  • Different circuit layers CL' are formed with corresponding multiple light control lines OL, power supply lines PL, ground lines GL, signal input lines DIL, signal output lines DOL and data lines DL.
  • the circuit of the driver chip DU' itself does not need to be redesigned, only the pin position of the package needs to be changed accordingly.
  • the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP of the circuit layer CL' are all arranged between the four light control pads OP , so that the wiring connecting the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP can be centrally arranged between adjacent light-emitting units LU, And the wiring is directly drawn from the fan-out area FA to the edge of the substrate SB, and will not intersect with the light-control wiring OL or the high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wiring, and the cost Low, and there is no yield problem such as short circuit between different metal layers.
  • a plurality of pads are arranged in two rows, and the control pads on the upper row are sequentially arranged from left to right.
  • the bottom row from left to right is: light control pad OP, vacant pad NP, data pad DP, signal output pad DOP and another light control pad OP.
  • the driver chip DU The circuit itself does not need to be redesigned, only the pins of the package need to be changed accordingly.
  • the power pad PP, signal input pad DIP, ground pad GP, vacant pad NP, signal output pad DOP, and data pad DP of the circuit layer CL" are all arranged between the four light control pads OP , so that the wiring connecting the power pad PP, the signal input pad DIP, the ground pad GP, the vacant pad NP, the signal output pad DOP, and the data pad DP can be centrally arranged between adjacent light-emitting units LU, And the wiring is directly drawn from the fan-out area FA to the edge of the substrate SB, and will not intersect with the light-control wiring OL or the high-potential wiring HL required by the light-emitting unit LU, which can meet the requirements of single-layer metal wiring, and the cost Low, and there is no yield problem such as short circuit between different metal layers.
  • the plurality of partitions MD 11 , MD 12 ... are arranged in multiple columns C1, C2 ...
  • the circuit layer CL also includes auxiliary grounding traces AGL, the end of the ground trace GL of the last partition (eg MD 1N ) of each column of the partitions (eg C1 ) is connected to the auxiliary ground trace AGL.
  • the AGL is designed to improve the voltage drop or voltage instability caused by the insufficient width of the ground trace GL.
  • the auxiliary ground line AGL includes a horizontal section and two vertical sections. The vertical section is parallel to the distribution direction of each row of the partitions (for example, C1 ) and is located at the edge of the substrate SB to provide voltage stabilization and shielding effects.
  • the multiple partitions MD 11 , MD 12 ... are arranged in multiple columns C1, C2 ..., wherein the last one of the first column partition C1
  • the signal output wiring DOL of the main partition MD 1N is connected to the signal input wiring DIL of the last partition MD 2N of the second row partition C2.
  • the signal input wiring DIL of a partition MD 2N is connected to the signal output wiring DOL of the last partition MD 1N of the first column partition C1, which is the driver chip DU of the last partition MD 2N of the second column partition C2.
  • the required brightness data comes from the signal output line DOL of the driver chip DU of the last partition MD 1N of the first column partition C1. Therefore, compared with the embodiment of FIG. 8, the second column partition of this embodiment C2 does not need to set the signal input trace DIL in the fan-out area FA, which can reduce the number of traces in the fan-out area FA, save the space of the fan-out area FA, and reduce the design complexity of the fan-out area FA.
  • the power line PL of the last partition MD 1N of the first column partition C1 is connected to the last partition MD 2N of the second column partition C2 The power supply line PL.
  • the operating voltage required by the driver chip DU of the last partition MD 2N of the second column partition C2 is from the driver of the last partition MD 1N of the first column partition C1
  • the power supply wiring PL of the chip DU therefore, compared with the embodiment of FIG.
  • the second column partition C2 of this embodiment does not need to set the power supply wiring PL in the fan-out area FA, which can reduce the wiring in the fan-out area FA number, save the space of the fan-out area FA, and reduce the design complexity of the fan-out area FA.
  • the data line DL of the last partition MD 1N of the first column partition C1 is connected to the last partition MD 2N of the second column partition C2
  • the signal required by the driver chip DU of the last partition MD 2N of the second column partition C2 is from the driver chip of the last partition MD 1N of the first column partition C1
  • the data routing DL of the DU therefore, compared with the embodiment of FIG. 8 , the second column partition C2 of this embodiment does not need to set the data routing DL in the fan-out area FA, which can reduce the number of routings in the fan-out area FA 1. Save the space of the fan-out area FA and reduce the design complexity of the fan-out area FA.
  • the multiple partitions MD 11 , MD 12 . . . are arranged in multiple columns C1, C2 . ), the signal output wire DOL of the previous partition (eg MD 11 ) is connected to the signal input wire DIL of the next partition (eg MD 12 ).
  • the present application provides a display device 1000, wherein, the display device 1000 includes any one of the above-mentioned backlight sources, such as a backlight source 100, and is arranged on the backlight source 100 on the liquid crystal display panel 200.
  • the backlight source 100 is used to provide the backlight required by the liquid crystal display panel 200.
  • the backlight source 100 also includes a backlight control unit B-con connected to the driver chip to provide brightness data required by the driver chip. , address data, PWM data, or scan data, etc.
  • the liquid crystal display panel 200 also includes a liquid crystal control unit T-con connected to the liquid crystal display panel 200 to control the liquid crystal display panel 200 to display, the backlight control unit B-con and the liquid crystal control unit T-con con are connected to the image signal source IS, the liquid crystal control unit T-con is used to display the image data provided by the image signal source IS, and the backlight control unit B-con cooperates with the image data provided by the image signal source IS Perform zone dimming.
  • a liquid crystal control unit T-con connected to the liquid crystal display panel 200 to control the liquid crystal display panel 200 to display
  • the backlight control unit B-con and the liquid crystal control unit T-con con are connected to the image signal source IS
  • the liquid crystal control unit T-con is used to display the image data provided by the image signal source IS
  • the backlight control unit B-con cooperates with the image data provided by the image signal source IS Perform zone dimming.
  • the backlight source and the display device provided in the present application include, through the circuit layer, signal input wiring, signal output wiring, multiple light control wiring, and corresponding signal input pads and signal output. pads and a plurality of light control pads, the plurality of light control pads are respectively located at multiple ends of the drive chip close to the light emitting unit, the signal input wiring and the signal output wiring are located at the The light control pads are used for transmitting signals to the driving chip. Only need to change the design of the pins of the existing driver chips on the market, without redesigning the driver chip itself, it can meet the requirements of single-layer metal wiring, the cost is low, and there is no yield rate such as shorting between different metal layers question.

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Abstract

一种背光源（100）以及显示装置（1000）。背光源（100）包括基板（SB）、电路层（CL）、多个发光单元（LU）以及驱动芯片（DU）。电路层（CL）包括同层设置的讯号输入走线（DIL）、讯号输出走线（DOL）、多条控光走线（OL）以及对应的讯号输入接垫（DIP）、讯号输出接垫（DOP）以及多个控光接垫（OP），多个控光接垫（OP）分别位于驱动芯片（DU）靠近发光单元（LU）的多个端部，讯号输入走线（DIL）、讯号输出走线（DOP）位于控光接垫（OP）之间，用于向驱动芯片（DU）传输信号。仅需对现有市面上的驱动芯片针脚进行变更设计，无需对驱动芯片本身进行重新设计，即可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问颗。

Description

背光源以及显示装置 技术领域
本申请涉及显示面板技术领域，尤其涉及一种背光源以及显示装置。
 背景技术
迷你发光二极管(mini Light Emitting Diode, mini-LED)又名“次毫米发光二极管”，指由晶粒（芯片）尺寸在50微米至200微米的LED。应用方向包括Mini LED显示屏和应用Mini LED背光屏的LCD。由于Mini LED显示屏在能耗、色域、对比度等方面都有出色的表现，工艺难度又没有Micro LED那么大，因此Mini LED有望成为LCD升级的主导产品。
市面上现有的背光产品都是基于两层及两层以上的金属走线方式。两层及两层以上的金属走线方式会存在不同金属层间易短接，以及成本较高等问题。市面上现有驱动IC的信道不兼容单层金属设计。
因此，目前急需能够解决上述背光产品不同金属层间易短接，以及成本较高等问题。
 技术问题
本申请实施例提供一种背光源以及显示装置，以解决现有技术的背光产品不同金属层间易短接，以及成本较高等问题。
 技术解决方案
本申请实施例提供一种背光源，所述背光源包括：
基板；
电路层，设置于所述基板上 ；
多个发光单元，阵列设置于所述电路层上；以及
驱动芯片，设置于所述电路层上，并位于相邻所述发光单元之间，用以驱动所述发光单元发光；其中，所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，所述讯号输入走线与所述讯号输入接垫相连，所述讯号输出走线与所述讯号输出接垫相连，所述控光走线与所述控光接垫相连，所述讯号输入接垫、所述讯号输出接垫以及所述控光接垫分别与所述驱动芯片连接，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。
在本申请的一些实施例的背光源中，所述电路层还包括：数据走线以及连接所述数据走线的数据接垫，其中，所述数据接垫设置于所述多个控光接垫之间，且所述数据走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线均设置于同一层，所述讯号输入走线与所述讯号输出走线位于同一延伸线。
在本申请的一些实施例的背光源中，所述数据走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线彼此之间均无交错。
在本申请的一些实施例的背光源中，所述电路层还包括：电源走线，以及连接所述电源走线的电源接垫，其中，所述电源接垫设置于所述多个控光接垫之间，且所述电源走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线均设置于同一层。
在本申请的一些实施例的背光源中，所述电源走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线彼此之间均无交错。
在本申请的一些实施例的背光源中，所述电路层还包括：接地走线以及连接所述接地走线的接地接垫，所述背光源还包括多个分区，每个所述分区的形状为四边形，包括4个发光单元，且分别分布于所述分区的四个角落，每个所述分区中包括4个控光接垫，所述4个控光接垫定义出四边形的接垫区，所述接地接垫、所述讯号输入接垫及所述讯号输出接垫均设置于所述接垫区中。
在本申请的一些实施例的背光源中，所述多个分区排列成多列，所述电路层还包括辅助接地走线，每一列所述分区的最后一个所述分区的所述接地走线的末端与所述辅助接地走线相连。
在本申请的一些实施例的背光源中，所述多个分区排列成多列，其中，第一列分区的最末一个分区的所述讯号输出走线连接于第二列分区的最末一个分区的所述讯号输入走线。
在本申请的一些实施例的背光源中，所述多个分区排列成多列，每一列所述分区中，前一个分区的讯号输出走线连接下一个分区的讯号输入走线。
在本申请的一些实施例的背光源中，所述电路层包括高电位走线，每条所述高电位走线位于相邻发光单元之间，并同时连接至所述发光单元的另一端。
在本申请的一些实施例的背光源中，所述发光单元包括多个迷你发光二极管(mini Light Emitting Diode, mini-LED)。
在另一方面，本申请提供一种显示装置，包括背光源，以及设置于所述背光源上的液晶显示面板，其中，所述背光源包括：基板；
电路层，设置于所述基板上；
多个发光单元，阵列设置于所述电路层上；以及
驱动芯片，设置于所述电路层上，并位于相邻所述发光单元之间，用以驱动所述发光单元发光；其中，所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，所述讯号输入走线与所述讯号输入接垫相连，所述讯号输出走线与所述讯号输出接垫相连，所述控光走线与所述控光接垫相连，所述讯号输入接垫、所述讯号输出接垫以及所述控光接垫分别与所述驱动芯片连接，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。
在本申请的一些实施例的显示装置中，所述背光源还包括背光控制单元连接所述驱动芯片用以提供所述驱动芯片亮度数据。
在本申请的一些实施例的显示装置中，所述液晶显示面板还包括液晶控制单元连接所述液晶显示面板用以控制所述液晶显示面板进行显示。
本申请的一些实施例的显示装置还包括影像讯号源，其中，所述背光控制单元及所述液晶控制单元均连接至所述影像讯号源，所述液晶控制单元用以控制所述液晶显示面板显示所述影像讯号源提供的影像数据，所述背光控制单元用以配合所述影像讯号源提供的所述影像数据进行区域调光。
 有益效果
本申请的有益效果为：本申请提供的所述背光源以及所述显示装置，通过所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。仅需对现有市面上的驱动芯片脚位进行变更设计，无需对驱动芯片本身进行重新设计，即可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是本申请实施例提供的背光源的结构示意图；
图2是本申请实施例提供的基板以及电路层的结构示意图；
图3是本申请实施例提供的分区的结构示意图；
图4是本申请实施例提供的分区中的电路层结构示意图；
图5是图3的分区沿AA线的剖面结构示意图；
图6是本申请另一实施例提供的分区中的电路层结构示意图；
图7是本申请又一实施例提供的分区中的电路层结构示意图；
图8是本申请另一实施例提供的背光源的结构示意图；
图9是本申请又一实施例提供的背光源的结构示意图；以及
图10是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是支撑连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
请参照图1、图2、图3及图4，其中，图2、图4未绘示驱动芯片DU以使驱动芯片DU下方的走线能在图中清楚呈现。本申请实施例提供一种背光源100，所述背光源100包括基板SB、电路层CL、多个发光单元LU以及驱动芯片DU。电路层CL设置于所述基板SB上；多个发光单元LU阵列设置于所述电路层CL上；驱动芯片DU设置于所述电路层CL上，包括多个针脚PN并位于相邻所述发光单元LU之间，用以驱动所述发光单元LU发光；其中，所述电路层CL包括同层设置的讯号输入走线DIL、讯号输出走线DOL、多条控光走线OL以及对应的讯号输入接垫DIP、讯号输出接垫DOP以及多个控光接垫OP，所述讯号输入走线DIL与所述讯号输入接垫DIP相连，所述讯号输出走线DOL与所述讯号输出接垫DOP相连，所述控光走线OL与所述控光接垫OP相连，所述讯号输入接垫DIP、所述讯号输出接垫DOP以及所述控光接垫OP分别与所述驱动芯片DU连接，多个所述控光接垫OP分别位于所述驱动芯片DU靠近所述发光单元LU的多个端部，所述讯号输入走线DIL、所述讯号输出走线DOL位于所述控光接垫OP之间，用于向所述驱动芯片DU传输信号。
具体的，所述多条控光走线OL、所述接地走线GL、所述讯号输入走线DIL以及所述讯号输出走线DOL均设置于同一层，例如以一层设置于基板SB上的金属铜膜经曝光显影制程形成所述多条控光走线OL、所述接地走线GL、所述讯号输入走线DIL以及所述讯号输出走线DOL的图案。可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
在本申请的一些实施例的背光源中，所述电路层CL包括高电位走线HL，每条所述高电位走线HL位于相邻发光单元LU之间，并同时连接至所述发光单元LU的另一端。
具体的，请参照图1、图2、图3及图4，所述接地接垫GP、所述讯号输入接垫DIP及所述讯号输出接垫DOP均设置于所述多个控光接垫OP之间，使得所述多个控光接垫OP位于接垫区PA的最外侧，因此，设置于所述多个发光单元LU之间的所述驱动芯片DU所需走线，例如所述接地走线GL、所述讯号输入走线DIL以及所述讯号输出走线DOL等，可以走在相邻的两列发光单元LU之间并直接由扇出区FA拉出走线至基板SB边缘，不会与所述发光单元LU所需的控光走线OL或高电位走线HL交错，可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
具体的，所述背光源100中使用半导体组件作为发光单元LU。在本申请的一些实施例的背光源中，发光单元LU为迷你发光二极管(mini Light Emitting Diode, mini-LED)。在其他实施例中，发光单元LU为发光二极管(Light Emitting Diode, LED)、有机发光二极管(Organic Light Emitting Diode, OLED)或微发光二极管(Micro Light Emitting Diode, micro-LED)等，本申请不限于此。发光单元LU中的mini-LED或micro-LED等发光组件的数量至少为一个，也可以为两灯，四灯，六灯，八灯，十灯，十二灯，十四灯，十六灯等中的一种。多个发光组件可串联连接，或是先串联后再并联形成多行的发光组件，本申请不限于此。每个灯之间的距离亦不加以限制。
具体的，所述基板SB的材料包括玻璃、印刷电路板(Printed Circuit Board, PCB)或BT树脂板（Bismaleimide Triazine, BT）。
具体的，请参照图5，电路层CL设置于所述基板SB上。发光单元LU及驱动芯片DU设置于所述电路层CL上。驱动芯片DU为球栅阵列封装(BallGrid Array，BGA)、导线架封装(Lead Frame)、表面贴装组件封装(Surface Mounted Devices package, SMD package)或是其他封装方式。本申请的图式均以球栅阵列封装为例，但本申请不限于此。具体的，所述驱动芯片DU的所述多个针脚PN指的是导线架封装中的引脚(Pin)或是球栅阵列封装中的锡球。具体的，驱动芯片DU的封装尺寸小于1500μm*1500μm。
具体的，所述讯号输入走线DIL用以提供驱动芯片DU关于每个发光单元LU所需的亮度数据以及对应的发光单元LU地址数据。并且以级联的方式，将讯号由讯号输出走线DOL传给下一个分区MD的驱动芯片DU。
请参照图1、图2、图3及图4，在本申请的一些实施例的背光源100中，所述电路层CL还包括：数据走线DL以及连接所述数据走线DL的数据接垫DP。
具体的，所述数据走线DL用以提供驱动芯片DU脉冲宽度调制(Pulse-Width Modulation, PWM)、地址数据或是扫描信号等，视驱动芯片DU的设计而定，本申请不限于此。所述数据接垫DP设置于所述多个控光接垫OP之间，且所述数据走线DL与所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL均设置于同一层，所述驱动芯片DU的所述多个针脚PN其中之一接触所述数据接垫DP。所述讯号输入走线DIL与所述讯号输出走线DOL位于同一延伸线。
具体的，所述讯号输入走线DIL、所述讯号输出走线DOL及所述数据走线DL的另一种数据结构为菊花链结构(Daisy Chain)，地址通过所述讯号输入走线DIL、所述讯号输出走线DOL来传输，亮度数据则通过所述数据走线DL同时传给所有的驱动芯片DU，本申请不限于此。
在本申请的一些实施例的背光源100中，所述数据走线DL与所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL彼此之间均无交错。具体的，所述数据走线DL、所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL彼此用以传输不同的讯号，因此必须彼此绝缘，由于所述数据走线DL、所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL均设置于同一金属层，因此走线彼此之间均无交错。
在本申请的一些实施例的背光源100中，所述电路层CL还包括：电源走线PL，以及连接所述电源走线PL的电源接垫PP。
具体的，所述电源走线PL用以提供驱动芯片DU本身运作所需的电源。所述电源接垫PP设置于所述多个控光接垫OP之间，且所述电源走线PL与所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL均设置于同一层，所述驱动芯片DU的所述多个针脚PN其中之一接触所述电源接垫PP。
在本申请的一些实施例的背光源100中，所述电源走线PL与所述多条控光走线OL、所述讯号输入走线DIL以及所述讯号输出走线DOL彼此之间均无交错。
在本申请的一些实施例的背光源100中，所述电路层CL还包括接地走线GL以及连接所述接地走线GL的接地接垫GP，所述背光源还包括多个分区MD。
具体的，本申请不限制所述分区MD的形状，以及每个分区MD中的所述多个发光单元LU的数目及分布位置。在本申请的一些实施例的背光源100中，每个所述分区MD的形状为四边形，包括4个发光单元LU，且分别分布于所述分区MD的四个角落，每个所述分区MD包括4个控光接垫OP，所述4个控光接垫OP定义出四边形的接垫区PA，所述接地接垫GP、所述讯号输入接垫DIP及所述讯号输出接垫DOP均设置于所述接垫区PA中。
具体的，请参照图3、图4，在本申请的实施例的所述接垫区PA中，10个接垫排列成两行，为2行×5列排列，其中所述接垫区PA的四角分别为所述4个控光接垫OP，讯号输入接垫DIP、讯号输出接垫DOP在同一列，其他电源接垫PP、接地接垫GP、空置接垫NP、数据接垫DP的位置可以相互更换，相互更换时其对应走线设计需同步更换。具体的，在本实施例的所述接垫区PA中，靠上一行从左至右依序为的控光接垫OP、电源接垫PP、讯号输入接垫DIP、接地接垫GP及另一个控光接垫OP。靠下一行从左至右依序为：控光接垫OP、空置接垫NP、讯号输出接垫DOP、数据接垫DP及另一个控光接垫OP。其中，电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP均设置于四个控光接垫OP之间，使得连接电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP的走线可以集中设置在相邻的发光单元LU之间，并直接由扇出区FA拉出走线至基板SB边缘，不会与所述发光单元LU所需的控光走线OL或高电位走线HL交错，可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
具体的，本申请不限制驱动芯片DU的封装脚位、脚位的命名及脚位的功能。具体的，各个接垫的形状，例如圆形、正方形、长方形等，本申请亦不限制。
具体的，请参照图6，在本申请另一实施例的分区MD’的所述接垫区PA’中, 多个接垫排列成两行，靠上一行从左至右依序为的控光接垫OP、讯号输入接垫DIP、电源接垫PP、接地接垫GP及另一个控光接垫OP。靠下一行从左至右依序为：控光接垫OP、讯号输出接垫DOP、空置接垫NP、数据接垫DP及另一个控光接垫OP。配合对应的多条控光走线OL、电源走线PL、接地走线GL、讯号输入走线DIL、讯号输出走线DOL以及数据走线DL，形成不同的电路层CL’。驱动芯片DU’本身的电路不必重新设计，仅需对应变更封装的脚位。其中，电路层CL’的电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP均设置于四个控光接垫OP之间，使得连接电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP的走线可以集中设置在相邻的发光单元LU之间，并直接由扇出区FA拉出走线至基板SB边缘，不会与所述发光单元LU所需的控光走线OL或高电位走线HL交错，可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
具体的，请参照图7，在本申请另一实施例的分区MD”的所述接垫区PA”中, 多个接垫排列成两行，靠上一行从左至右依序为的控光接垫OP、电源接垫PP、接地接垫GP、讯号输入接垫DIP及另一个控光接垫OP。靠下一行从左至右依序为：控光接垫OP、空置接垫NP、数据接垫DP、讯号输出接垫DOP及另一个控光接垫OP。配合对应的多条控光走线OL、电源走线PL、接地走线GL、讯号输入走线DIL、讯号输出走线DOL以及数据走线DL，形成不同的电路层CL”。驱动芯片DU”本身的电路不必重新设计，仅需对应变更封装的脚位。其中，电路层CL”的电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP均设置于四个控光接垫OP之间，使得连接电源接垫PP、讯号输入接垫DIP、接地接垫GP、空置接垫NP、讯号输出接垫DOP、数据接垫DP的走线可以集中设置在相邻的发光单元LU之间，并直接由扇出区FA拉出走线至基板SB边缘，不会与所述发光单元LU所需的控光走线OL或高电位走线HL交错，可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
请参照图8，在本申请的一些实施例的背光源100’中，所述多个分区MD 11、MD 12…排列成多列C1、C2…，所述电路层CL还包括辅助接地走线AGL，每一列所述分区(例如C1)的最后一个所述分区(例如MD 1N)的所述接地走线GL的末端与所述辅助接地走线AGL相连。
具体的，当采取较紧密的发光单元LU排列而导致发光单元LU之间的走线宽度不够时，可以减小接地走线GL的宽度以让位给其他走线，并且另外采用辅助接地走线AGL的设计以改善接地走线GL的宽度不足导致的电压降或电压不稳定。辅助接地走线AGL包括水平段及两段垂直段，垂直段与每一列所述分区(例如C1)的分布方向平行且位于基板SB的最边缘以提供稳压及屏蔽的效果。
请参照图9，在本申请的一些实施例的背光源100”中，所述多个分区MD 11、MD 12…排列成多列C1、C2…，其中，第一列分区C1的最末一个主分区MD 1N的所述讯号输出走线DOL连接于第二列分区C2的最末一个分区MD 2N的所述讯号输入走线DIL。在本实施例中，由于第二列分区C2的最末一个分区MD 2N的讯号输入走线DIL连接第一列分区C1的最末一个分区MD 1N的所述讯号输出走线DOL，即第二列分区C2的最末一个分区MD 2N的驱动芯片DU所需的亮度数据是来自于第一列分区C1的最末一个分区MD 1N的驱动芯片DU的所述讯号输出走线DOL，因此，相对于图8的实施例，本实施例的第二列分区C2不需在扇出区FA设置讯号输入走线DIL，可减少扇出区FA中的走线数目、节省扇出区FA的空间、降低扇出区FA的设计复杂度。
请参照图9，在本申请的一些实施例的背光源100”中，第一列分区C1的最末一个分区MD 1N的电源走线PL连接于第二列分区C2的最末一个分区MD 2N的电源走线PL。在本实施例中，第二列分区C2的最末一个分区MD 2N的驱动芯片DU所需的操作电压是来自于第一列分区C1的最末一个分区MD 1N的驱动芯片DU的电源走线PL，因此，相对于图8的实施例，本实施例的第二列分区C2不需在扇出区FA设置电源走线PL，可减少扇出区FA中的走线数目、节省扇出区FA的空间、降低扇出区FA的设计复杂度。
请参照图9，在本申请的一些实施例的背光源100”中，第一列分区C1的最末一个分区MD 1N的数据走线DL连接于第二列分区C2的最末一个分区MD 2N的数据走线DL。在本实施例中，第二列分区C2的最末一个分区MD 2N的驱动芯片DU所需的讯号是来自于第一列分区C1的最末一个分区MD 1N的驱动芯片DU的数据走线DL，因此，相对于图8的实施例，本实施例的第二列分区C2不需在扇出区FA设置数据走线DL，可减少扇出区FA中的走线数目、节省扇出区FA的空间、降低扇出区FA的设计复杂度。
请参照图8，在本申请的一些实施例的背光源(例如100’)中，所述多个分区MD 11、MD 12…排列成多列C1、C2…，每一列所述分区(例如C1)中，前一个分区(例如MD 11)的讯号输出走线DOL连接下一个分区(例如MD 12)的讯号输入走线DIL。
请参照图10，在另一方面，本申请提供一种显示装置1000，其中，所述显示装置1000包括上述任一所述的背光源，例如为背光源100，以及设置于所述背光源100上的液晶显示面板200。所述背光源100用以提供所述液晶显示面板200所需的背光，具体的，所述背光源100还包括背光控制单元B-con连接所述驱动芯片用以提供驱动芯片所需的亮度数据、地址数据、PWM数据、或扫描数据等。所述液晶显示面板200还包括液晶控制单元T-con连接所述液晶显示面板200，用以控制所述液晶显示面板200进行显示，所述背光控制单元B-con及所述液晶控制单元T-con均连接至影像讯号源IS，所述液晶控制单元T-con用以显示影像讯号源IS所提供的影像数据，而所述背光控制单元B-con则配合影像讯号源IS所提供的影像数据进行区域调光。
本申请提供的所述背光源以及所述显示装置，通过所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。仅需对现有市面上的驱动芯片针脚进行变更设计，无需对驱动芯片本身进行重新设计，即可以满足单层金属走线的要求，成本较低，且无不同金属层间短接等良率问题。
以上对本申请实施例所提供的背光源以及显示装置进行了详细介绍。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种背光源，包括：
    基板；
    电路层，设置于所述基板上；
    多个发光单元，阵列设置于所述电路层上；以及
    驱动芯片，设置于所述电路层上，并位于相邻所述发光单元之间，用以驱动所述发光单元发光；其中，所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，所述讯号输入走线与所述讯号输入接垫相连，所述讯号输出走线与所述讯号输出接垫相连，所述控光走线与所述控光接垫相连，所述讯号输入接垫、所述讯号输出接垫以及所述控光接垫分别与所述驱动芯片连接，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。
  2. 根据权利要求1所述的背光源，其中，所述电路层还包括：数据走线以及连接所述数据走线的数据接垫，其中，所述数据接垫设置于所述多个控光接垫之间，且所述数据走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线均设置于同一层，所述讯号输入走线与所述讯号输出走线位于同一延伸线。
  3. 根据权利要求2所述的背光源，其中，所述数据走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线彼此之间均无交错。
  4. 根据权利要求1所述的背光源，其中，所述电路层还包括：电源走线以及连接所述电源走线的电源接垫，其中，所述电源接垫设置于所述多个控光接垫之间，且所述电源走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线均设置于同一层。
  5. 根据权利要求4所述的背光源，其中，所述电源走线与所述多条控光走线、所述讯号输入走线以及所述讯号输出走线彼此之间均无交错。
  6. 根据权利要求1所述的背光源，其中，所述电路层还包括：接地走线以及连接所述接地走线的接地接垫，所述背光源还包括多个分区，每个所述分区的形状为四边形，包括4个发光单元，且分别分布于所述分区的四个角落，每个所述分区中包括4个控光接垫，所述4个控光接垫定义出四边形的接垫区，所述接地接垫、所述讯号输入接垫及所述讯号输出接垫均设置于所述接垫区中。
  7. 根据权利要求6所述的背光源，其中，所述多个分区排列成多列，所述电路层还包括辅助接地走线，每一列所述分区的最后一个所述分区的所述接地走线的末端与所述辅助接地走线相连。
  8. 根据权利要求6所述的背光源，其中，所述多个分区排列成多列，其中，第一列分区的最末一个分区的所述讯号输出走线连接于第二列分区的最末一个分区的所述讯号输入走线。
  9. 根据权利要求6所述的背光源，其中，所述多个分区排列成多列，每一列所述分区中，前一个分区的讯号输出走线连接下一个分区的讯号输入走线。
  10. 根据权利要求1所述的背光源，其中，所述电路层还包括多条高电位走线，每条所述高电位走线位于相邻发光单元之间，并同时连接至所述发光单元的另一端。
  11. 根据权利要求1所述的背光源，其中，所述发光单元包括多个迷你发光二极管(mini Light Emitting Diode, mini-LED)。
  12. 一种显示装置，包括背光源，以及设置于所述背光源上的液晶显示面板，其中，所述背光源包括：基板；
    电路层，设置于所述基板上；
    多个发光单元，阵列设置于所述电路层上；以及
    驱动芯片，设置于所述电路层上，并位于相邻所述发光单元之间，用以驱动所述发光单元发光；其中，所述电路层包括同层设置的讯号输入走线、讯号输出走线、多条控光走线以及对应的讯号输入接垫、讯号输出接垫以及多个控光接垫，所述讯号输入走线与所述讯号输入接垫相连，所述讯号输出走线与所述讯号输出接垫相连，所述控光走线与所述控光接垫相连，所述讯号输入接垫、所述讯号输出接垫以及所述控光接垫分别与所述驱动芯片连接，多个所述控光接垫分别位于所述驱动芯片靠近所述发光单元的多个端部，所述讯号输入走线、所述讯号输出走线位于所述控光接垫之间，用于向所述驱动芯片传输信号。
  13. 根据权利要求12所述的显示装置，其中，所述背光源还包括背光控制单元连接所述驱动芯片用以提供所述驱动芯片亮度数据。
  14. 根据权利要求13所述的显示装置，其中，所述液晶显示面板还包括液晶控制单元连接所述液晶显示面板用以控制所述液晶显示面板进行显示。
  15. 根据权利要求14所述的显示装置，还包括影像讯号源，其中，所述背光控制单元及所述液晶控制单元均连接至所述影像讯号源，所述液晶控制单元用以控制所述液晶显示面板显示所述影像讯号源提供的影像数据，所述背光控制单元用以配合所述影像讯号源提供的所述影像数据进行区域调光。
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