WO2023098286A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2023098286A1
WO2023098286A1 PCT/CN2022/124197 CN2022124197W WO2023098286A1 WO 2023098286 A1 WO2023098286 A1 WO 2023098286A1 CN 2022124197 W CN2022124197 W CN 2022124197W WO 2023098286 A1 WO2023098286 A1 WO 2023098286A1
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Prior art keywords
bonding
normal
sub
bonding regions
redundant
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PCT/CN2022/124197
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English (en)
French (fr)
Inventor
王岩
黄秀颀
黄飞
王程功
董小彪
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成都辰显光电有限公司
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Publication of WO2023098286A1 publication Critical patent/WO2023098286A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Definitions

  • the present application belongs to the field of display technology, and in particular relates to a display panel and a preparation method thereof.
  • Micro-LED As a new display technology, Micro-LED is receiving more and more attention. However, at present, the yield rate of Micro-LED mass transfer technology is low, and dead pixels need to be repaired in the later stage to meet the display standard. Due to the tight arrangement of Micro-LEDs, how to improve the mass transfer yield and repair yield is an urgent technical problem to be solved.
  • the present application provides a display panel and a preparation method thereof, so as to improve the mass transfer yield and repair yield of Micro-LEDs.
  • a technical solution adopted by the present application is to provide a display panel, including: a driving backplane, the first surface of the driving backplane is provided with a plurality of normal bonding regions and a plurality of redundant bonding regions ; wherein the first spacing between at least partially adjacent two normal bonding regions is greater than the second spacing between at least partially adjacent normal bonding regions and the redundant bonding region, and the The normal bonding area and the adjacent redundant bonding area form a bonding group; the light-emitting layer is located on the first surface and includes a plurality of sub-pixels, and the sub-pixels are connected with the normal bonding area or the redundant bonding area.
  • the co-bonding areas are electrically connected, and the normal bonding areas or the redundant bonding areas in the same bonding group are used for electrical connection with the sub-pixels of the same luminescent color.
  • another technical solution adopted by the present application is to provide a method for manufacturing a display panel, including: providing a driving backplane; wherein, the first surface of the driving backplane is provided with a plurality of normal bonding region and a plurality of redundant bonding regions; at least a first distance between two adjacent normal bonding regions is greater than a second distance between adjacent normal bonding regions and redundant bonding regions, And the normal bonding area and the adjacent redundant bonding area form a bonding group; sub-pixels are set on the normal bonding area of the drive backplane; in response to bonding with the normal bonding area When the sub-pixels connected with each other are determined to be defective sub-pixels, repairing sub-pixels with the same luminescent color are introduced on the redundant bonding regions in the same bonding group.
  • the beneficial effect of the present application is: on the one hand, the drive backplane of the display panel provided by the present application is provided with multiple normal bonding areas and multiple redundant bonding areas, and the normal bonding area and the Adjacent redundant bonding regions can form a bonding group, and a sub-pixel is electrically connected to a normal bonding region or a redundant bonding region in a bonding group.
  • a sub-pixel bonded to a normal bonding area is determined to be a bad pixel
  • a patched sub-pixel having the same luminescent color can be introduced on a redundant bonding area in the same bonding group.
  • the present application introduces a redundant repair method, which increases the repair yield compared with in-situ repair.
  • at least part of the first distance between two adjacent normal bonding regions is greater than the second distance between adjacent normal bonding regions and redundant bonding regions.
  • FIG. 1 is a schematic structural diagram of an embodiment of a display panel of the present application
  • Fig. 2 is a partial top view schematic diagram of the previous embodiment of repairing the defective pixels of the display panel in Fig. 1;
  • FIG. 3 is a schematic top view of an embodiment of a pixel driving circuit and related routings corresponding to FIG. 2;
  • Fig. 4 is a schematic partial top view of another embodiment before the defective pixel of the display panel in Fig. 1 is repaired;
  • FIG. 5 is a schematic partial top view of another embodiment before repairing defective pixels of the display panel in FIG. 1;
  • FIG. 6 is a schematic top view of an embodiment of the pixel driving circuit and related routing corresponding to FIG. 5;
  • FIG. 7 is a schematic partial top view of another embodiment before the defective pixel of the display panel in FIG. 1 is repaired;
  • FIG. 8 is a schematic partial top view of another embodiment before the defective pixel of the display panel in FIG. 1 is repaired;
  • FIG. 9 is a schematic partial top view of another embodiment before the defective pixel of the display panel in FIG. 1 is repaired;
  • FIG. 10 is a schematic partial top view of another embodiment before the defective pixel of the display panel in FIG. 1 is repaired;
  • Fig. 11 is a schematic partial top view of another embodiment before the defective pixel of the display panel in Fig. 1 is repaired;
  • Fig. 12 is a schematic partial top view of another embodiment before the defective pixel of the display panel in Fig. 1 is repaired;
  • FIG. 13 is a schematic partial top view of another embodiment before the defective pixel of the display panel in FIG. 1 is repaired;
  • Fig. 14 is a schematic partial top view of another embodiment before the defective pixel of the display panel in Fig. 1 is repaired;
  • FIG. 15 is a schematic flowchart of an embodiment of a method for manufacturing a display panel of the present application.
  • FIG. 16 is a schematic structural view of an embodiment after the repair of the display panel in FIG. 2;
  • FIG. 17 is a schematic structural diagram of another embodiment after the display panel in FIG. 2 has been repaired.
  • Figure 1 is a schematic structural view of an embodiment of the display panel of the present application
  • Figure 2 is a partial top view of an embodiment of the display panel in Figure 1 before repairing dead pixels
  • the display panel can be a Micro-LED display panel etc.
  • the display panel 1 specifically includes a driving backplane 10 and a light emitting layer 12 located on the first surface 100 of the driving backplane 10 .
  • the first surface 100 of the driving backplane 10 is provided with a plurality of normal bonding regions 1020 and a plurality of redundant bonding regions 1022;
  • the first distance D1 is greater than the second distance D2 between at least part of the adjacent normal bonding regions 1020 and redundant bonding regions 1022 , and the normal bonding regions 1020 and the adjacent redundant bonding regions 1022 form a bonding group 102 .
  • the above-mentioned first distance D1 may be the distance between the edges of two adjacent normal bonding regions 1020
  • the second distance D2 may be the distance between the edges of the adjacent normal bonding regions 1020 and the redundant bonding region 1022. Spacing between edges.
  • first distance D1 may be the distance between the center points of two adjacent normal bonding regions 1020
  • second distance D2 may be the distance between the center points of the adjacent normal bonding regions 1020 and the redundant bonding region 1022. Spacing between center points.
  • a normal bonding area 1020 can form a bonding group 102 with an adjacent redundant bonding area 1022; of course, in other embodiments, a normal bonding area 1020 can also form a bonding group 102 with adjacent redundant bonding areas
  • the Yubonding area 1022 constitutes a bonding group 102 .
  • the light-emitting layer 12 includes a plurality of sub-pixels 120, which can be Micro-LEDs, etc., which can emit red light, green light, or blue light, etc.;
  • the normal bonding region 1020 or the redundant bonding region 1022 in the same bonding group 102 is used to electrically connect with the sub-pixels 120 of the same luminescent color.
  • the appearance structure of the normal bonding area 1020 and the redundant bonding area 1022 can be the same.
  • the sub-pixels 120 in 12 have different priorities when bonding. Generally speaking, during the mass transfer process, the sub-pixel 120 is preferentially bonded to the normal bonding area 1020 in the bonding group 102; when the sub-pixel 120 bonded to the normal bonding area 1020 is determined to be a bad pixel pixel, the bad point sub-pixel is removed, or, when the bad point sub-pixel is an open circuit, the bad point sub-pixel remains;
  • the luminous color of the pixel is the same as the luminous color of the bad pixel sub-pixel when it normally emits light; that is, the bonding time of the sub-pixel 120 electrically connected to the normal bonding area 1020 is earlier than the bonding time of the sub-pixel 120 electrically connected to the redundant bonding area 1022;
  • the normal bonding regions 1020 in the same bonding group 102 are electrically connected to the sub-pixels 120 prior to the redundant bonding regions
  • only one sub-pixel 120 is disposed on the normal bonding area 1020 or the redundant bonding area 1022 in the same bonding group 102 .
  • one sub-pixel 120 is respectively set on the normal bonding area 1020 and the redundant bonding area 1022 in the same bonding group 102, and the sub-pixel 120 on the normal bonding area 1020 is disconnected from the corresponding pixel driving circuit,
  • the sub-pixels 120 located on the redundant bonding regions 1022 are electrically connected to the corresponding pixel driving circuits.
  • FIG. 2 is a partial schematic diagram of the display panel 1 before repairing the dead pixels in FIG. 1, it can be considered that the area covered by the sub-pixel 120 in FIG. 2 is a normal bonding area 1020; and the normal bonding area 1020 and the redundant bonding area 1022
  • the size of the area may be the same as that of the sub-pixel 120 .
  • the number of sub-pixels 120 electrically connected to the normal bonding region 1020 on a display panel 1 is greater than the number of sub-pixels 120 electrically connected to the redundant bonding region 1022;
  • the ratio of the number of sub-pixels 120 electrically connected to the number of sub-pixels 120 electrically connected to the redundant bonding region 1022 may be much greater than 100.
  • all sub-pixels 120 are electrically connected to the normal bonding region 1020 .
  • at least one of the plurality of redundant bonding regions 1022 is not electrically connected to the sub-pixel 120 .
  • this application introduces a redundant repair method, which reduces the repair difficulty and increases the repair yield compared with in-situ repair.
  • the first distance D1 between at least some of the adjacent normal bonding regions 1020 is greater than the second distance D2 between the adjacent normal bonding regions 1020 and the redundant bonding regions 1022 .
  • the above-mentioned design method can increase the distance between adjacent sub-pixels 120, reduce the interference between adjacent sub-pixels 120, and reduce the The probability of rotation and offset occurs to improve the transfer yield; and this design method can make the raised area of the transfer head of the transfer sub-pixel 120 can be appropriately increased to increase the tolerance to the offset of the sub-pixel 120 and improve the transfer rate. yield.
  • a plurality of normal bonding regions 1020 and a plurality of redundant bonding regions 1022 are arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction The directions Y cross each other.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the first distance D1 between two normal bonding regions 1020 that are at least partially adjacent in the first direction X is larger than the normal bonding regions 1020 that are at least partially adjacent in the first direction X or the second direction Y and The second distance D2 between the redundant bonding regions 1022 .
  • the first distance D1 between two normal bonding regions 1020 that are at least partially adjacent in the second direction Y is larger than the normal bonding regions 1020 that are at least partially adjacent in the first direction X or the second direction Y and The second distance D2 between the redundant bonding regions 1022 .
  • two adjacent normal bonding regions 1020 may also be located in an oblique direction, that is, a direction intersecting the first direction X or the second direction Y in FIG.
  • the first distance D1 between two normal bonding regions 1020 that are at least partially adjacent in the oblique direction is still greater than that between the normal bonding regions 1020 and the redundant bonding regions that are at least partially adjacent in the first direction X or the second direction Y
  • the second distance D2 between the regions 1022 is relatively regular, and the process is easy to form.
  • the luminescent colors of the sub-pixels 120 bonded by the above-mentioned two adjacent normal bonding regions 1020 may be the same or different, which is not limited in this application.
  • a redundant bonding region 1022 is provided between at least partially adjacent two normal bonding regions 1020 .
  • This design method can increase the first distance D1 between two adjacent normal bonding regions 1020.
  • the above design method can further reduce the relative The interference between adjacent sub-pixels 120 reduces the probability of sub-pixel 120 rotation and offset, so as to improve the transfer yield; and it can increase the raised area of the transfer head of the transferred sub-pixel to increase the resistance to sub-pixel offset. tolerance.
  • a plurality of adjacent sub-pixels 120 form a pixel unit (not shown), and a plurality of bonding groups 102 electrically connected to the pixel unit form a combination unit 104 .
  • a plurality of normal bonding regions 1020 and a plurality of redundant bonding regions 1022 in the combination unit 104 are arranged in two rows, and a plurality of normal bonding regions 1020 in the combination unit 104 are in two rows Arranged alternately (ie alternately arranged up and down), the multiple redundant bonding regions 1022 in the combination unit 104 are arranged alternately in two rows (ie alternately arranged up and down).
  • This design method can make the distance between adjacent normal bonding regions 1020 larger.
  • the above-mentioned design method can further reduce the distance between adjacent sub-pixels 120.
  • the interference between them reduces the probability of rotation and offset of the sub-pixel 120 to improve the transfer yield; and it can increase the convex area of the transfer head for transferring the sub-pixel to increase the tolerance to the sub-pixel offset.
  • the number of two adjacent sub-pixels 120 arranged in the oblique direction is greater than the number of two adjacent sub-pixels 120 arranged in the same row in the first direction X or the second direction Y;
  • the oblique direction intersects the first direction X and the second direction Y.
  • the first oblique direction is different from the second oblique direction, but both intersect the first direction X and the second direction Y.
  • the above-mentioned design method can make the distance between two adjacent sub-pixels 120 as large as possible.
  • the driving backplane 10 further includes a plurality of pixel driving circuits (not shown), and the normal bonding region 1020 and the redundant bonding region 1022 in the same bonding group 102 are electrically connected to the same pixel driving circuit.
  • This design method can save the wiring space of the pixel driving circuit, and is more suitable for high PPI or closely arranged sub-pixel arrangement scenarios.
  • the structure of the pixel driving circuit may be any one in the prior art, for example, it may be 2T1C, 7T1C, etc., which is not limited in this application.
  • each normal bonding region 1020 or redundant bonding region 1022 includes a first electrode bonding region 1060 for electrical connection with the first electrode, and a second electrode for electrical connection with the second electrode Bonding region 1062;
  • the first electrode corresponding to the first electrode bonding region 1060 marked in FIG. 2 is a P electrode
  • the second electrode corresponding to the second electrode bonding region 1062 marked in FIG. 2 is N electrode.
  • the first electrode corresponding to the first electrode bonding region 1060 may also be an N electrode, and the second electrode corresponding to the second electrode bonding region 1062 may also be a P electrode.
  • the two first electrode bonding regions 1060 in the same bonding group 102 are electrically connected to the output terminals of the same pixel driving circuit; that is, the normal bonding region 1020 and the redundant bonding region 1022 in the same bonding group 102 are connected to the same pixel
  • the driving circuit is electrically connected, and the sub-pixels set in the normal bonding area 1020 and the patched sub-pixels set in the redundant bonding area 1022 can be driven by the same pixel driving circuit.
  • This design method can save the wiring space of the pixel driving circuit, and is more suitable for high PPI or closely arranged sub-pixel arrangement scenarios.
  • the normal bonding area 1020 and the redundant bonding area 1022 in the same bonding group 102 are adjacently arranged along the first direction X, and multiple bonding groups in the same combination unit 104 102 are arranged at intervals along the second direction Y.
  • the redundant bonding region 1022 is designed in the first direction X of the normal bonding region 1020 , the structural design is relatively simple, and the process is easy to implement.
  • a plurality of normal bonding regions 1020 and a plurality of redundant bonding regions 1022 arranged in the same row are alternately arranged at intervals; and
  • the upper and lower rows of normal bonding regions 1020 and redundant bonding regions 1022 are alternately arranged in the opposite manner, and the upper and lower rows are aligned with each other.
  • the two first electrode bonding regions 1060 in the same bonding group 102 are opposite and arranged at intervals, and the two first electrode bonding regions 1060 in the same bonding group 102 are arranged at intervals.
  • An electrode bonding region 1060 is located between two second electrode bonding regions 1062; that is, in the first direction X, in the same bonding group 102, the second electrode bonding region 1062, the first electrode bonding region 1060, The first electrode bonding regions 1060 and the second electrode bonding regions 1062 are sequentially arranged at intervals.
  • the orthographic projection of the output end of the pixel driving circuit on the first surface 100 (as shown by the dotted line box marked 108 in FIG. 2 ) is located between the two first electrode bonding regions 1060 .
  • the design of the above structure is relatively simple, and the process is easy to prepare and form.
  • FIG. 3 is a schematic top view of an implementation manner of the pixel driving circuit and related wirings corresponding to FIG. 2 .
  • the driving backplane 10 includes a thin film transistor layer and an insulating layer above the thin film transistor layer; wherein, the pixel driving circuit 103 is located in the thin film transistor layer, and the surface of the insulating layer facing away from the thin film transistor layer forms the first surface 100 , the first electrode bonding region 1060 and the second electrode bonding region 1062 can be exposed from the first surface 100 of the driving backplane 10 for bonding connection with the sub-pixel 120 .
  • the position of the insulating layer corresponding to the output end of the pixel driving circuit 103 can be provided with a conductive hole (that is, the position indicated by the dotted line box marked as 108 in FIGS.
  • the first electrode bonding region 1060 is electrically connected. It can be seen from FIG. 2 and FIG. 3 that the output terminals of the pixel driving circuit 103 are arranged in a manner of being arranged at intervals along the second direction Y, so that the pixel driving circuit 103 can be repeatedly arranged in the second direction Y, reducing the number of pixels. The layout of the driving circuit 103 is difficult.
  • the pixel unit in FIG. 2 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes the same sub-pixel in the pixel unit. Pixels 120 are electrically connected to the three bonding groups 102 .
  • the three normal bonding regions 1020 in the combination unit 104 are arranged alternately up and down, and the three redundant bonding regions 1022 in the combination unit 104 are arranged alternately up and down.
  • repeating units 106 there are multiple repeating units 106 on the display panel; in the second direction Y, two adjacent combination units 104 form a repeating unit 106, and a plurality of normal bonding regions 1020 in the repeating unit 106 are alternately arranged up and down, repeating The multiple redundant bonding regions 1022 in the unit 106 are alternately arranged up and down.
  • the design of the repeating unit 106 can reduce the complexity of the manufacturing process of the display panel 1 .
  • FIG. 4 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the pixel unit in FIG. 4 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes three sub-pixels 120 electrically connected to the pixel unit. A bonding group 102.
  • the adjacent two combination units 104 are arranged axially symmetrically, and at least part of the adjacent two combination units 104 arranged axially symmetrically correspond to the normal bonding regions 1020 of sub-pixels with the same luminescent color Adjacent setting.
  • This design method can make the two sub-pixels 120 at the positions of the normal bonding regions 1020 in two adjacent bonding groups 102 in the first direction X can be transferred and bonded at the same time, so as to improve the bonding efficiency; and in the bonding During the bonding transfer process, it will not be affected by the sub-pixels 120 on the remaining normal bonding regions 1020, so as to improve the bonding yield. For example, in FIG.
  • two blue sub-pixels that are adjacent in the first direction X and have no redundant bonding area 1022 in the middle can be transferred and bonded at the same time, and due to the existence of the surrounding redundant bonding area 1022, they can be bonded during the bonding process. will not be squeezed or collided by adjacent red sub-pixels and green sub-pixels.
  • the third distance D3 from two adjacent combination units 104 and between two adjacent normal bonding regions 1020 is smaller than that of the same combination unit
  • the fourth distance D4 between two adjacent normal bonding regions 1020 in 104 can increase the arrangement density of pixels to improve the display effect.
  • the third distance D3 and the fourth distance D4 may be the distance between the edges of two adjacent normal bonding regions 1020 .
  • the third distance D3 and the fourth distance D4 may be the distance between the center points of two adjacent normal bonding regions 1020 .
  • FIG. 4 Another option, as shown in FIG. 4 , four combination units 104 adjacent to each other in the first direction X and the second direction Y (four combination units 104 adjacent up, down, left, and right) constitute a repeating unit 106; In the second direction Y, the normal bonding regions 1020 and the redundant bonding regions 1022 in the same row in the repeating unit 106 are alternately arranged.
  • This design method can reduce the difficulty of process preparation.
  • FIG. 5 is a schematic partial top view of another implementation manner before the dead pixels of the display panel in FIG. 1 are repaired.
  • the normal bonding area 1020 and the redundant bonding area 1022 in the same bonding group 102 are arranged at intervals along the second direction Y, and the multiple bonding groups 102 in the same combination unit 104 are arranged in two rows along the first direction X, and the two The rows of bonding groups 102 are arranged to be misaligned; optionally, the amount of misalignment between two rows of bonding groups 102 is a redundant bonding area 1022 or a normal bonding area 1020 .
  • the redundant bonding region 1022 is designed in the second direction Y of the normal bonding region 1020, the structure design is relatively simple, and the process is easy to implement.
  • a plurality of normal bonding regions 1020 and a plurality of redundant bonding regions 1022 arranged in the same row are alternately arranged at intervals; and in the first direction X, up and down
  • the two rows of normal bonding regions 1020 and redundant bonding regions 1022 are arranged alternately in the same manner, and the upper and lower rows are staggered.
  • the two first electrode bonding regions 1060 in the same bonding group 102 are opposite and arranged at intervals, and the two first electrode bonding regions 1060 in the same bonding group 102 are arranged at intervals.
  • the two electrode bonding regions 1062 are opposite and arranged at intervals.
  • This design method can reduce the difficulty of wiring and the difficulty of process preparation.
  • in the second direction Y there is an intermediate region 105 between the two first electrode bonding regions 1060 in the same bonding group 102, and the output terminal of the pixel driving circuit is at the An orthographic projection of a surface 100 (shown as a dotted box marked 108 in FIG. 5 ) is spaced apart from the intermediate region 105 in the first direction X.
  • FIG. 5 in the second direction Y, there is an intermediate region 105 between the two first electrode bonding regions 1060 in the same bonding group 102, and the output terminal of the pixel driving circuit is at the An orthographic projection of a surface 100 (shown as a dotted box marked 108 in FIG. 5 ) is spaced apart from the intermediate region 105 in the first direction X.
  • FIG. 6 is a schematic top view of an embodiment of the pixel driving circuit and related routings corresponding to FIG. 5 .
  • the driving backplane 10 includes a thin film transistor layer and an insulating layer located above the thin film transistor layer; wherein, the pixel driving circuit is located in the thin film transistor layer, and the surface of the insulating layer facing away from the thin film transistor layer forms the first surface 100
  • the first electrode bonding region 1060 and the second electrode bonding region 1062 may be exposed from the first surface 100 of the driving backplane 10 for bonding connection with the sub-pixel 120 .
  • the position of the insulating layer corresponding to the output end of the pixel driving circuit can be provided with a conductive hole (that is, the position indicated by the dotted line box marked as 108 in FIGS. 5 and 6 ), and the conductive hole further passes through the metal wiring and the first electrodes on both sides
  • the bonding area 1060 is electrically connected. It can be seen from FIG. 5 and FIG. 6 that the output ends of the pixel driving circuit 103 are arranged in a manner of being arranged at intervals along the second direction Y, which can make the pixel driving circuit 103 repeatedly arranged in the second direction Y, reducing the pixel driving Difficulty in layout of circuit 103 .
  • the pixel unit in FIG. 5 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes the same sub-pixel in the pixel unit. Pixels 120 are electrically connected to the three bonding groups 102 .
  • the three normal bonding regions 1020 in the combination unit 104 are arranged alternately up and down, and the three redundant bonding regions 1022 in the combination unit 104 are arranged alternately up and down.
  • repeating units 106 there are multiple repeating units 106 on the display panel; in the second direction Y, two adjacent combination units 104 form a repeating unit 106, and a plurality of normal bonding regions 1020 in the repeating unit 106 are alternately arranged up and down, repeating The multiple redundant bonding regions 1022 in the unit 106 are alternately arranged up and down.
  • the design of the repeating unit 106 can reduce the complexity of the manufacturing process of the display panel 1 .
  • FIG. 7 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the pixel unit in FIG. 7 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes three sub-pixels 120 electrically connected to the pixel unit.
  • a bonding group 102 is a bonding group 102.
  • the adjacent two combination units 104 are arranged axially symmetrically, and at least part of the adjacent two combination units 104 arranged axially symmetrically correspond to the normal bonding regions 1020 of sub-pixels with the same luminescent color Adjacent setting.
  • This design method can make the two sub-pixels 120 at the positions of the normal bonding regions 1020 in two adjacent bonding groups 102 in the first direction X can be transferred and bonded at the same time, so as to improve the bonding efficiency; and in the bonding During the bonding transfer process, it will not be affected by the sub-pixels 120 on the remaining normal bonding regions 1020, so as to improve the bonding yield. For example, in FIG.
  • the third distance D3 from two adjacent combination units 104 and between two adjacent normal bonding regions 1020 is smaller than that of the same combination unit
  • the fourth distance D4 between two adjacent normal bonding regions 1020 in 104 can increase the arrangement density of pixels to improve the display effect.
  • the third distance D3 and the fourth distance D4 may be the distance between the edges of two adjacent normal bonding regions 1020 .
  • the third distance D3 and the fourth distance D4 may be the distance between the center points of two adjacent normal bonding regions 1020 .
  • the four combination units 104 adjacent in the first direction X and the second direction Y constitutes a repeating unit 106; in the second direction Y, normal bonding regions 1020 and redundant bonding regions 1022 in the same row in the repeating unit 106 are alternately arranged.
  • This design method can reduce the difficulty of process preparation.
  • the normal bonding area 1020 and the redundant bonding area 1022 in the same combination unit 104 are arranged alternately up and down; in other embodiments, the normal bonding area 1020 in the same combination unit 104 and the redundant bonding area 1022 can be arranged in the same row respectively.
  • FIG. 8 is a schematic partial top view of another implementation before the dead pixels of the display panel in FIG. 1 are repaired.
  • a plurality of adjacent sub-pixels 120 form a pixel unit 122, and a plurality of bonding groups 102 electrically connected to the pixel unit 122 form a combination unit 104;
  • the normal bonding region 1020 and the redundant bonding region 1022 in the same bonding group 102 are along the Arranged in the first direction X
  • a plurality of normal bonding regions 1020 in the combined unit 104 are adjacently arranged in the same row along the second direction Y
  • a plurality of redundant bonding regions 1022 in the combined unit 104 are adjacent along the second direction Y Arranged in the same row; wherein, in the first direction X and the second direction Y, a row of redundant bonding regions 1022 is set between two rows of normal bonding regions 1020 in two adjacent combination units 104 .
  • the structural design is relatively simple, and the process is easy to implement; and in the process of bonding the sub-pixels 120 in the normal bonding area 1020, the transfer head can pick up three sub-pixels 120 bonded to the same combination unit 104 at the same time, so as to improve the bonding efficiency.
  • a plurality of pixel drive circuits are included in the drive backplane, and the normal bonding area 1020 and the redundant bonding area 1022 in the same bonding group 102 can be connected with the same pixel drive circuit
  • the output terminals are electrically connected.
  • the two first electrode bonding regions 1060 in the same bonding group 102 are opposite and arranged at intervals, and the two first electrode bonding regions 1060 in the same bonding group 102 are located at two Between two second electrode bonding regions 1062; that is, in the first direction X, in the same bonding group 102, the second electrode bonding region 1062, the first electrode bonding region 1060, the first electrode bonding region 1060 and The second electrode bonding regions 1062 are sequentially arranged at intervals.
  • the orthographic projection of the output end of the pixel driving circuit on the first surface (as shown by the dotted box marked 108 in FIG. 8 ) is located between the two first electrode bonding regions 1060 .
  • the design of the above structure is relatively simple, and the process is easy to prepare and form.
  • the corresponding pixel driving circuit and related wiring in FIG. 8 may be as shown in FIG. 3 .
  • the pixel unit 122 in FIG. 8 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes the sub-pixel 120 in the pixel unit 122.
  • the three bonding groups 102 are electrically connected.
  • the three normal bonding regions 1020 in the combined unit 104 are located in the same row, and the three redundant bonding regions 1022 in the combined unit 104 are located in the same row.
  • the regions 1020 are alternately arranged up and down.
  • the design of the repeating unit 106 can reduce the complexity of the manufacturing process of the display panel.
  • the number of adjacent two pixel units 122 arranged in the oblique direction is greater than the number of adjacent two pixel units 122 arranged in the same row in the first direction X or the second direction Y;
  • the oblique direction intersects the first direction X and the second direction Y, and all the sub-pixels 120 in each pixel unit 122 in the above-mentioned adjacent two pixel units 122 are aligned along the first direction X or the second direction Y Arranged in the same row; if the sub-pixels 120 in a certain pixel unit 122 are not arranged in the same row, they are not included in the counting range. For example, taking FIG.
  • the pixel unit 122 corresponding to the combination unit 104 in the upper left corner is adjacent to the pixel unit 122 corresponding to the combination unit 104 in the upper right corner in the first oblique direction
  • the pixel unit 122 corresponding to the combination unit 104 in the upper left corner is adjacent to the pixel unit 122 corresponding to the combination unit 104 in the upper left corner.
  • the pixel unit 122 corresponding to the combination unit 104 in the lower right corner is adjacent in the second oblique direction; the first oblique direction is different from the second oblique direction, but both intersect the first direction X and the second direction Y.
  • the above-mentioned design method can make the distance between two adjacent pixel units 122 as large as possible.
  • FIG. 9 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the pixel unit 122 in FIG. 9 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G and blue sub-pixel B), and the combination unit 104 includes three sub-pixels 120 electrically connected to the pixel unit 122.
  • the three normal bonding regions 1020 in the combined unit 104 are located in the same row, and the three redundant bonding regions 1022 in the combined unit 104 are located in the same row.
  • the adjacent two combination units 104 are arranged axially symmetrically, and the normal bonding regions 1020 corresponding to sub-pixels of the same luminescent color in the two adjacent combination units 104 arranged axially symmetrically are arranged opposite to each other. .
  • FIG. 10 is a schematic partial top view of another implementation before the defective pixel of the display panel in FIG. 1 is repaired. The difference between Fig. 10 and the embodiment in Fig.
  • the pixel unit in FIG. 10 includes three adjacent sub-pixels 120 (red sub-pixel R, green sub-pixel G, and blue sub-pixel B), and the corresponding combination unit 104 includes a sub-pixel electrically connected to the pixel unit 120.
  • one combining unit 104 forms one repeating unit 106, and the design of the repeating unit 106 can reduce the complexity of the manufacturing process of the display panel.
  • FIG. 11 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the first direction X at least part of the adjacent two combination units 104 are arranged axially symmetrically, and the normal bonding regions 1020 corresponding to sub-pixels of the same light emitting color in the two axially symmetrically arranged combination units 104 are arranged adjacently;
  • a plurality of repeating units 106 are arranged on the display panel, and two combining units 104 adjacent in the first direction X form one repeating unit 106 .
  • the power supply voltage line 101 is located between two rows of second electrode bonding regions 1062, and the power supply voltage line 101 is electrically connected to two adjacent rows of second electrode bonding regions 1062 .
  • This design method can further save the routing area of the pixel driving circuit, and is especially suitable for high PPI or closely arranged display pixel arrangement scenarios.
  • the power supply voltage line 101 can provide a low power supply voltage of VSS.
  • the power supply voltage line 101 can provide a high power supply voltage of VDD, which is not limited in the present application.
  • the sub-pixel 120 includes a first axis of symmetry L1 , and the extension direction of the axis of symmetry L1 is parallel to the first direction X.
  • the extending direction of the first symmetry axis L1 of the sub-pixel 120 may also be arranged to intersect with the first direction X, and the angle of the intersecting arrangement may be 30° or 45° or 90°.
  • FIG. 12 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the first symmetry axes L1 of all the sub-pixels 120 are arranged across the first direction X, and the first symmetry axes L1 of all the sub-pixels 120 are arranged parallel to each other.
  • the positions of the first electrode bonding region 1060 and the second electrode bonding region 1062 on the redundant bonding region 1022 and the normal bonding region 1020 in FIG. 2 will also adapt to the position of the subpixel 120 and rotate to the position in FIG. 10 .
  • the above-mentioned design method is relatively simple and easy to implement.
  • FIG. 13 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the first symmetry axes L1 of all the sub-pixels 120 are arranged to cross the first direction X; and in the first direction X, the extension directions of the first symmetry axes L1 of two adjacent rows of sub-pixels 120 are arranged to cross each other.
  • the angles between the extension direction of the first symmetry axis L1 of two adjacent rows of sub-pixels 120 and the first direction X are equal.
  • the above-mentioned design method is relatively simple and easy to implement.
  • the orthographic projection of the sub-pixel 120 on the first surface is a rectangle.
  • FIG. 14 is a schematic partial top view of another embodiment of the display panel shown in FIG. 1 before repairing dead pixels.
  • the orthographic projection of the sub-pixel 120 on the first surface is a rounded rectangle.
  • the orthographic projection of the sub-pixel 120 on the first surface may also be circular, elliptical, triangular, trapezoidal, pentagonal, hexagonal, or other special-shaped structures. Not limited.
  • the sub-pixels 120 of the above shape are easy to manufacture and obtain. And as shown in FIG.
  • the distance P1 between the center points of the sub-pixels 120 disposed on two adjacent normal bonding regions 1020 is greater than that of the sub-pixels 120 disposed on adjacent normal bonding regions 1020 and redundant bonding regions 1022 The distance between the center points of P2.
  • FIG. 15 is a schematic flowchart of an embodiment of a method for preparing a display panel of the present application.
  • the above-mentioned preparation method specifically includes:
  • S101 Provide a driving backplane; wherein, the first surface of the driving backplane is provided with a plurality of normal bonding regions and a plurality of redundant bonding regions; at least a first distance between two adjacent normal bonding regions is greater than The second distance between the adjacent normal bonding area and the redundant bonding area, and the normal bonding area and the adjacent redundant bonding area constitute a bonding group.
  • the structure of the driving backplane may refer to any of the foregoing embodiments, and details are not repeated here.
  • S102 Set sub-pixels on the normal bonding area of the driving backplane.
  • a plurality of sub-pixels can be simultaneously transferred to the normal bonding region at the corresponding position by a mass transfer device, and the sub-pixels and the normal bonding region can be bonded and connected by substances such as solder.
  • the diagram corresponding to step S102 may refer to FIG. 2 above.
  • the sub-pixel on the normal bonding area can be tested for lighting up by driving the backplane, if the brightness of the sub-pixel is abnormal (including the brightness is lower than the first threshold or the brightness exceeds the second threshold), the sub-pixel is determined as a bad sub-pixel. Subsequent methods such as laser can be used to remove the bad point sub-pixel from the normal bonding area, and set a repair sub-pixel with the same luminous color on the redundant bonding area in the same bonding group to replace the original normal bonding area. sub-pixel.
  • FIG. 16 is a schematic structural diagram of an embodiment of the repaired display panel in FIG. 2 . Assuming that after the lighting test, it is found that the green sub-pixel G on the upper left in FIG. 120a can emit green light.
  • FIG. 17 is a schematic structural diagram of another embodiment after the display panel in FIG. 2 is repaired.
  • the green sub-pixel G on the upper left in Figure 2 is a bad sub-pixel, and the bad sub-pixel is a broken sub-pixel, which cannot emit green light normally;
  • a patched sub-pixel 120a is introduced into the corresponding redundant bonding area, and the patched sub-pixel 120a can emit green light.

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Abstract

本申请公开了一种显示面板及其制备方法，所述显示面板包括：驱动背板，所述驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区；其中，至少部分相邻的两个所述正常邦定区之间的第一间距大于至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距，且所述正常邦定区与相邻的所述冗余邦定区构成一个邦定组；发光层，位于所述第一表面上，包括多个子像素，所述子像素与所述正常邦定区或所述冗余邦定区电连接，且同一邦定组内的所述正常邦定区或所述冗余邦定区用于与同一发光颜色的子像素电连接。通过上述方式，本申请能够提高Micro-LED巨量转移良率和修补良率。

Description

显示面板及其制备方法
本申请要求于2021年11月30日提交的申请号为202111447380X，发明名称为“显示面板及其制备方法”的中国专利申请的优先权，其通过引用方式全部并入本申请。
技术领域
本申请属于显示技术领域，具体涉及一种显示面板及其制备方法。
背景技术
Micro-LED作为新型显示技术，正受到越来越广泛的关注。但是目前Micro-LED巨量转移技术良率较低，后期需要进行坏点修补以达到显示标准。由于Micro-LED排列较为紧密，如何提高巨量转移良率和修补良率是亟待解决的技术问题。
发明内容
本申请提供一种显示面板及其制备方法，以提高Micro-LED巨量转移良率和修补良率。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种显示面板，包括：驱动背板，所述驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区；其中，至少部分相邻的两个所述正常邦定区之间的第一间距大于至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距，且所述正常邦定区与相邻的所述冗余邦定区构成一个邦定组；发光层，位于所述第一表面上，包括多个子像素，所述子像素与所述正常邦定区或所述冗余邦定区电连接，且同一邦定组内的所述正常邦定区或所述冗余邦定区用于与同一发光颜色的子像素电连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种显示面板的制备方法，包括：提供驱动背板；其中，所述驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区；至少部分相邻的两个所述正常邦定区之间的第一间距大于相邻的所述正常邦定区和所述冗余邦定区之间的第二间距，且所述正常邦定区与相邻的所述冗余邦定区构成一个邦定组；在所述驱动背板的 所述正常邦定区上设置子像素；响应于与所述正常邦定区邦定连接的所述子像素被确定为坏点子像素时，在同一邦定组内的所述冗余邦定区上引入具有相同发光颜色的修补子像素。
区别于现有技术情况，本申请的有益效果是：一方面，本申请所提供的显示面板的驱动背板上设置有多个正常邦定区和多个冗余邦定区，且正常邦定区与相邻的冗余邦定区可以构成一个邦定组，一个子像素与一个邦定组内的正常邦定区或冗余邦定区电连接。在实际应用过程中，当与正常邦定区邦定的子像素被确定为坏点时，可以在同一邦定组内的冗余邦定区上引入具有相同发光颜色的修补子像素。即本申请引入冗余修补的方式，相比原位修补而言，其修补良率增加。另一方面，本申请中至少部分相邻的两个正常邦定区之间的第一间距大于相邻的正常邦定区和冗余邦定区之间的第二间距。在巨量转移过程中，在正常邦定区邦定子像素时，上述设计方式可以增大相邻子像素之间的间距，降低相邻子像素之间的干扰，降低子像素发生旋转、偏移的概率，以提高转移良率；且该设计方式可以使得转移子像素的转移头的凸起面积可以适当增大，以增加对子像素偏移的容忍度，提高转移良率。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，其中：
图1为本申请显示面板一实施方式的结构示意图；
图2为图1中显示面板坏点修补前一实施方式的局部俯视示意图；
图3为图2对应的像素驱动电路和相关走线一实施方式的俯视示意图；
图4为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图5为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图6为图5对应的像素驱动电路和相关走线一实施方式的俯视示意图；
图7为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图8为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图9为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图10为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图11为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图12为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图13为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图14为图1中显示面板坏点修补前另一实施方式的局部俯视示意图；
图15为本申请显示面板的制备方法一实施方式的流程示意图；
图16为图2中显示面板修补后一实施方式的结构示意图；
图17为图2中显示面板修补后另一实施方式的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本申请保护的范围。
请参阅图1和图2，图1为本申请显示面板一实施方式的结构示意图，图2为图1中显示面板坏点修补前一实施方式的局部俯视示意图，该显示面板可以为Micro-LED显示面板等。该显示面板1具体包括驱动背板10和位于驱动背板10的第一表面100上的发光层12。
其中，如图2所示，驱动背板10的第一表面100设置有多个正常邦定区1020和多个冗余邦定区1022；且至少部分相邻的两个正常邦定区1020之间的第一间距D1大于至少部分相邻的正常邦定区1020和冗余邦定区1022之间的第二间距D2，且正常邦定区1020与相邻的冗余邦定区1022构成一个邦定组102。可选地，上述第一间距D1可以为相邻的两个正常邦定区1020的边缘之间的间距，第二间距D2可以为相邻的正常邦定区1020的边缘与冗余邦定区1022的边缘之间的间距。或者，上述第一间距D1可以为相邻的两个正常邦定区1020的中心点之间的间距，第二间距D2可以为相邻的正常邦定区1020的中心点与冗余邦定区1022的中心点之间的间距。可选地，一个正常邦定区1020可以与相邻的一个冗余邦定区1022构成一个邦定组102；当然，在其他实施例中，一个正常邦定区1020也可与相邻的多个冗余邦定区1022构成一个邦定组102。
发光层12包括多个子像素120，该子像素120可以为Micro-LED等，其可以发出红色光线或绿色光线或蓝色光线等；且子像素120与正常邦定区1020或冗余邦定区1022电连接，且同一邦定组102内的正常邦定区1020或冗余邦定 区1022用于与同一发光颜色的子像素120电连接。
在本实施例中，正常邦定区1020和冗余邦定区1022的外观结构可以相同，正常邦定区1020和冗余邦定区1022的区分标准主要在于正常邦定区1020和冗余邦定区1022与发光层12中的子像素120邦定时的优先级不同。一般而言，在巨量转移过程中，子像素120优先与邦定组102内的正常邦定区1020邦定连接；当与正常邦定区1020邦定连接的子像素120被确定为坏点子像素时，该坏点子像素被移除，或者，当该坏点子像素为断路时，该坏点子像素保留；并在同一邦定组102内的冗余邦定区1022上引入修补子像素，该修补子像素的发光颜色与坏点子像素正常发光时的发光颜色相同；即与正常邦定区1020电连接的子像素120的邦定时间先于冗余邦定区1022电连接的子像素120的邦定时间；同一邦定组102内的正常邦定区1020优先于冗余邦定区1022与子像素120电连接。
可选地，在本实施例中，同一邦定组102内仅正常邦定区1020或冗余邦定区1022上设置有一个子像素120。或者，同一邦定组102内正常邦定区1020和冗余邦定区1022上均分别设置有一个子像素120，且位于正常邦定区1020上的子像素120与对应的像素驱动电路之间断路，位于冗余邦定区1022上的子像素120与对应的像素驱动电路之间电连接。由于图2是图1中显示面板1坏点修补前的局部示意图，故可以认为图2中子像素120所覆盖的区域均为正常邦定区1020；且正常邦定区1020和冗余邦定区1022的面积大小可以与子像素120的面积大小相同。
此外，一般而言，一个显示面板1上与正常邦定区1020电连接的子像素120的个数大于与冗余邦定区1022电连接的子像素120的个数；例如，与正常邦定区1020电连接的子像素120的个数与冗余邦定区1022电连接的子像素120的个数的比值可能远大于100。可选地，所有子像素120均与正常邦定区1020电连接。可选地，多个冗余邦定区1022至少有一个不与子像素120电连接。
一方面，本申请引入冗余修补的方式，相比原位修补而言，其修补难度降低，修补良率增加。另一方面，本申请中至少部分相邻的两个正常邦定区1020之间的第一间距D1大于相邻的正常邦定区1020和冗余邦定区1022之间的第二间距D2。在巨量转移过程中，在正常邦定区1020邦定子像素120时，上述设计方式可以增大相邻子像素120之间的间距，降低相邻子像素120之间的干扰，降低子像素120发生旋转、偏移的概率，以提高转移良率；且该设计方式可以 使得转移子像素120的转移头的凸起面积可以适当增大，以增加对子像素120偏移的容忍度，提高转移良率。
在一个实施方式中，如图2中所示，多个正常邦定区1020和多个冗余邦定区1022沿第一方向X和第二方向Y呈阵列排布，且第一方向X和第二方向Y相互交叉。可选地，第一方向X和第二方向Y相互垂直。其中，在第一方向X上至少部分相邻的两个正常邦定区1020之间的第一间距D1大于在第一方向X或第二方向Y上至少部分相邻的正常邦定区1020和冗余邦定区1022之间的第二间距D2。或者，在第二方向Y上至少部分相邻的两个正常邦定区1020之间的第一间距D1大于在第一方向X或第二方向Y上至少部分相邻的正常邦定区1020和冗余邦定区1022之间的第二间距D2。在某些情况下，如图2中所示，相邻的两个正常邦定区1020也可位于斜向方向，即与图2中第一方向X或第二方向Y交叉的方向，此时仍然满足至少部分在斜向方向上相邻的两个正常邦定区1020之间的第一间距D1大于在第一方向X或第二方向Y至少部分相邻的正常邦定区1020和冗余邦定区1022之间的第二间距D2。上述多个正常邦定区1020和多个冗余邦定区1022的排布方式较为规整，工艺易于制备形成。可选地，在本实施例中，上述所提及的相邻的两个正常邦定区1020所邦定的子像素120的发光颜色可以相同或者不同，本申请对此不作限定。
进一步，如图2中所示，在第一方向X或第二方向Y上，至少部分相邻的两个正常邦定区1020之间设置有冗余邦定区1022。该设计方式可以增大相邻的两个正常邦定区1020之间的第一间距D1，在巨量转移过程中，在正常邦定区1020邦定子像素120时，上述设计方式可以进一步降低相邻子像素120之间的干扰，降低子像素120发生旋转、偏移的概率，以提高转移良率；且能够使得转移子像素的转移头凸起面积增大，以增加对子像素偏移的容忍度。
请继续参阅图2，相邻的多个子像素120构成一个像素单元(未标示)，与像素单元电连接的多个邦定组102构成一个组合单元104。其中，在第一方向X上，组合单元104内的多个正常邦定区1020和多个冗余邦定区1022排列为两排，且组合单元104内的多个正常邦定区1020在两排中交替排列(即上下交替排列)，组合单元104内的多个冗余邦定区1022在两排中交替排列(即上下交替排列)。该设计方式可以使得相邻正常邦定区1020之间的距离较大，在巨量转移过程中，在正常邦定区1020邦定子像素120时，上述设计方式可以进一步降低相邻子像素120之间的干扰，降低子像素120发生旋转、偏移的概率，以 提高转移良率；且能够使得转移子像素的转移头凸起面积增大，以增加对子像素偏移的容忍度。
可选地，如图2所示，在斜向方向上设置的相邻两子像素120的数量大于在第一方向X或第二方向Y上同排设置的相邻两子像素120的数量；其中，斜向方向与第一方向X和第二方向Y交叉。例如，以图2中一个组合单元104位置处的三个子像素120为例，其中红色子像素R和绿色子像素G在第一斜向方向上相邻，绿色子像素G和蓝色子像素B在第二斜向方向上相邻，第一斜向方向与第二斜向方向不同，但均与第一方向X和第二方向Y交叉。上述设计方式可以使得相邻两子像素120之间的间距尽可能增大。
在一个实施方式中，驱动背板10还包括多个像素驱动电路(图未示)，同一邦定组102内的正常邦定区1020和冗余邦定区1022与同一像素驱动电路电连接。该设计方式可以节省像素驱动电路的走线空间，更适用于高PPI或紧密排列的子像素排布场景。可选地，在本实施例中，像素驱动电路的结构可以为现有技术中任一一种，例如，可以为2T1C、7T1C等，本申请对此不作限定。
可选地，子像素120可以为水平型发光元件，每个子像素120面向第一表面100一侧设置有第一电极(图未示)和第二电极(图未示)。请继续参阅图2，每个正常邦定区1020或冗余邦定区1022分别包括用于与第一电极电连接的第一电极邦定区1060、以及用于与第二电极电连接的第二电极邦定区1062；例如，图2中所标示的第一电极邦定区1060所对应的第一电极为P电极，图2中所标示的第二电极邦定区1062所对应的第二电极为N电极。当然，在其他实施例中，与第一电极邦定区1060所对应的第一电极也可为N电极，与第二电极邦定区1062所对应的第二电极也可为P电极。进一步，同一邦定组102内的两个第一电极邦定区1060与同一像素驱动电路的输出端电连接；即同一邦定组102内的正常邦定区1020和冗余邦定区1022与同一像素驱动电路电连接，正常邦定区1020所设置的子像素和冗余邦定区1022所设置的修补子像素可由同一像素驱动电路驱动。该设计方式可以节省像素驱动电路的走线空间，更适用于高PPI或紧密排列的子像素排布场景。
在一个应用场景中，如图2所示，同一邦定组102内的正常邦定区1020和冗余邦定区1022沿第一方向X相邻排布，同一组合单元104内的多个邦定组102沿第二方向Y间隔排布。在上述设计方式中，冗余邦定区1022设计在正常邦定区1020的第一方向X上，该结构设计较为简单，且工艺易于实现。
可选地，在本实施例中，如图2中所示，在第二方向Y上，同排设置的多个正常邦定区1020和多个冗余邦定区1022交替间隔排布；且在第一方向X上，上下两排正常邦定区1020和冗余邦定区1022交替设置的方式相反，上下两排相互对齐设置。
在此基础上，如图2中所示，在第一方向X上，同一邦定组102内的两个第一电极邦定区1060相对且间隔设置，同一邦定组102内的两个第一电极邦定区1060位于两个第二电极邦定区1062之间；即在第一方向X上，同一邦定组102内以第二电极邦定区1062、第一电极邦定区1060、第一电极邦定区1060和第二电极邦定区1062的方式依次间隔排布。此时，在第一方向X上，像素驱动电路的输出端在第一表面100的正投影(如图2中标示为108的虚线框所示)位于两个第一电极邦定区1060之间。上述结构设计较为简单，且工艺易于制备形成。
可选地，请参阅图2和图3，图3为图2对应的像素驱动电路和相关走线一实施方式的俯视示意图。在本实施例中，驱动背板10包括薄膜晶体管层以及位于薄膜晶体管层上方的绝缘层；其中，像素驱动电路103位于薄膜晶体管层内，绝缘层背离薄膜晶体管层的一侧表面形成第一表面100，第一电极邦定区1060和第二电极邦定区1062可从驱动背板10的第一表面100外露，以与子像素120邦定连接。此时绝缘层对应像素驱动电路103的输出端的位置可以设置有导电孔(即图2和图3中标示为108的虚线框所示位置)，导电孔进一步通过金属走线与两侧的两个第一电极邦定区1060电连接。从图2和图3中可以看出像素驱动电路103的输出端设置成在沿第二方向Y间隔排布的方式，可以使得像素驱动电路103可以在第二方向Y上重复排布，降低像素驱动电路103的布局难度。
请继续参阅图2，图2中像素单元包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元中的子像素120电连接的三个邦定组102。组合单元104中三个正常邦定区1020上下交替排列，组合单元104中三个冗余邦定区1022上下交替排列。进一步，显示面板上具有多个重复单元106；在第二方向Y上，相邻的两个组合单元104构成一个重复单元106，重复单元106内的多个正常邦定区1020上下交替排列，重复单元106内的多个冗余邦定区1022上下交替排列。该重复单元106的设计方式可以降低制备显示面板1的工艺复杂程度。
当然，在其他实施方式中，图2中组合单元104的排布方式也可为其他。例如，请参阅图4，图4为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图4中像素单元包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元中的子像素120电连接的三个邦定组102。在第一方向X上，至少部分相邻的两个组合单元104呈轴对称设置，且呈轴对称设置的相邻两个组合单元104中至少部分对应相同发光颜色子像素的正常邦定区1020相邻设置。该设计方式可以使得在第一方向X上部分相邻两个邦定组102内的正常邦定区1020位置处的两个子像素120可以同时被转移邦定，以提高邦定效率；且在邦定转移过程中不会受到其余正常邦定区1020上的子像素120的影响，以提高邦定良率。例如，图4中在第一方向X上相邻且中间无冗余邦定区1022间隔的两个蓝色子像素可以被同时转移邦定，且由于周围冗余邦定区1022的存在，其在邦定过程中并不会受到相邻的红色子像素和绿色子像素的挤压、碰撞。
可选地，如图4所示，在第一方向X上，分别来自于相邻两个组合单元104中且相邻的两个正常邦定区1020之间的第三距离D3小于同一组合单元104中的相邻两个正常邦定区1020之间的第四距离D4。该设计方式可以使得像素排布密度增大，以提高显示效果。可选地，第三距离D3和第四距离D4可以为相邻的两个正常邦定区1020的边缘之间的间距。或者，第三距离D3和第四距离D4可以为相邻的两个正常邦定区1020的中心点之间的间距。
另一可选地，如图4所示，在第一方向X和第二方向Y上相邻的四个组合单元104(上下左右相邻的四个组合单元104)构成一个重复单元106；在第二方向Y上，重复单元106内位于同一排的正常邦定区1020和冗余邦定区1022交替排列。该设计方式可以降低工艺制备难度。
在另一应用场景中，如图5所示，图5为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。同一邦定组102内的正常邦定区1020和冗余邦定区1022沿第二方向Y间隔排布，同一组合单元104内的多个邦定组102沿第一方向X排列为两排，且两排邦定组102之间相互错位设置；可选地，两排邦定组102之间的错位量为一个冗余邦定区1022或一个正常邦定区1020。在上述设计方式中，冗余邦定区1022设计在正常邦定区1020的第二方向Y上，该结构设计较为简单，且工艺易于实现。
可选地，如图5中所示，在第二方向Y上，同排设置的多个正常邦定区1020 和多个冗余邦定区1022交替间隔排布；且在第一方向X上，上下两排正常邦定区1020和冗余邦定区1022交替设置的方式相同，上下两排之间错位设置。
在此基础上，如图5中所示，在第二方向Y上，同一邦定组102内的两个第一电极邦定区1060相对且间隔设置，同一邦定组102内的两个第二电极邦定区1062相对且间隔设置。其中，同一组合单元104内的两排邦定组102之间具有间隙(未标示)，像素驱动电路的输出端在第一表面100的正投影(如图5中标示为108的虚线框所示)位于间隙内，且位于同一邦定组102内的两个第一电极邦定区1060之间。该设计方式可以降低布线难度，降低工艺制备难度。可选的，如图5中所示，在第二方向Y上，同一邦定组102内的两个第一电极邦定区1060之间具有一个中间区域105，像素驱动电路的输出端在第一表面100的正投影(如图5中标示为108的虚线框所示)与该中间区域105在第一方向X上间隔设置。
可选地，请一并参阅图5和图6，图6为图5对应的像素驱动电路和相关走线一实施方式的俯视示意图。在本实施例中，驱动背板10包括薄膜晶体管层以及位于薄膜晶体管层上方的绝缘层；其中，像素驱动电路位于薄膜晶体管层内，绝缘层背离薄膜晶体管层的一侧表面形成第一表面100，第一电极邦定区1060和第二电极邦定区1062可从驱动背板10的第一表面100外露，以与子像素120邦定连接。此时绝缘层对应像素驱动电路的输出端的位置可以设置有导电孔(即图5和图6中标示为108的虚线框所示位置)，导电孔进一步通过金属走线与两侧的第一电极邦定区1060电连接。从图5和图6中可以看出像素驱动电路103的输出端设置成在沿第二方向Y间隔排布的方式，可以使得像素驱动电路103在第二方向Y上重复排布，降低像素驱动电路103的布局难度。
请继续参阅图5，图5中像素单元包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元中的子像素120电连接的三个邦定组102。组合单元104中三个正常邦定区1020上下交替排列，组合单元104中三个冗余邦定区1022上下交替排列。进一步，显示面板上具有多个重复单元106；在第二方向Y上，相邻的两个组合单元104构成一个重复单元106，重复单元106内的多个正常邦定区1020上下交替排列，重复单元106内的多个冗余邦定区1022上下交替排列。该重复单元106的设计方式可以降低制备显示面板1的工艺复杂程度。
当然，在其他实施方式中，图5中组合单元104的排布方式也可为其他。 例如，请参阅图7，图7为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图7中像素单元包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元中的子像素120电连接的三个邦定组102。在第一方向X上，至少部分相邻的两个组合单元104呈轴对称设置，且呈轴对称设置的相邻两个组合单元104中至少部分对应相同发光颜色子像素的正常邦定区1020相邻设置。该设计方式可以使得在第一方向X上部分相邻两个邦定组102内的正常邦定区1020位置处的两个子像素120可以同时被转移邦定，以提高邦定效率；且在邦定转移过程中不会受到其余正常邦定区1020上的子像素120的影响，以提高邦定良率。例如，图7中在第一方向X上相邻且中间无冗余邦定区1022间隔的两个蓝色子像素可以被同时转移邦定，且由于周围冗余邦定区1022的存在，其在邦定过程中并不会受到相邻的红色子像素和绿色子像素的挤压、碰撞。
可选地，如图7所示，在第一方向X上，分别来自于相邻两个组合单元104中且相邻的两个正常邦定区1020之间的第三距离D3小于同一组合单元104中的相邻两个正常邦定区1020之间的第四距离D4。该设计方式可以使得像素排布密度增大，以提高显示效果。可选地，第三距离D3和第四距离D4可以为相邻的两个正常邦定区1020的边缘之间的间距。或者，第三距离D3和第四距离D4可以为相邻的两个正常邦定区1020的中心点之间的间距。
另一可选地，如图7所示，显示面板上具有多个重复单元106，在第一方向X和第二方向Y上相邻的四个组合单元104(上下左右相邻的四个组合单元104)构成一个重复单元106；在第二方向Y上，重复单元106内位于同一排的正常邦定区1020和冗余邦定区1022交替排列。该设计方式可以降低工艺制备难度。
在上述几个实施例中，同一组合单元104内的正常邦定区1020和冗余邦定区1022均是上下交替排布的形式；在其他实施例中，同一组合单元104内的正常邦定区1020和冗余邦定区1022均可分别采取同排设置的方式。
在一个应用场景中，请参阅图8，图8为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。相邻的多个子像素120构成一个像素单元122，与像素单元122电连接的多个邦定组102构成一个组合单元104；同一邦定组102内的正常邦定区1020和冗余邦定区1022沿第一方向X排布，且组合单元104内的多个正常邦定区1020沿第二方向Y相邻排列于同一排，组合单元104内的多个冗余邦定区1022沿第二方向Y相邻排列于同一排；其中，在第一方向X和 第二方向Y上，相邻的两个组合单元104中的两排正常邦定区1020之间设置有一排冗余邦定区1022。该结构设计较为简单，且工艺易于实现；且在正常邦定区1020邦定子像素120过程中，转移头可以同时拾取与同一组合单元104邦定的三个子像素120，以提高邦定效率。
在此基础上，如图8中所示，驱动背板内包括多个像素驱动电路(图未示)，同一邦定组102内正常邦定区1020和冗余邦定区1022可以与同一像素驱动电路的输出端电连接。可选地，在第一方向X上，同一邦定组102内的两个第一电极邦定区1060相对且间隔设置，同一邦定组102内的两个第一电极邦定区1060位于两个第二电极邦定区1062之间；即在第一方向X上，同一邦定组102内以第二电极邦定区1062、第一电极邦定区1060、第一电极邦定区1060和第二电极邦定区1062的方式依次间隔排布。此时，在第一方向X上，像素驱动电路的输出端在第一表面的正投影(如图8中标示为108的虚线框所示)位于两个第一电极邦定区1060之间。上述结构设计较为简单，且工艺易于制备形成。此时图8中对应的像素驱动电路和相关走线可如图3中所示。
此外，图8中像素单元122包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元122中的子像素120电连接的三个邦定组102。组合单元104中三个正常邦定区1020位于同一排，组合单元104中三个冗余邦定区1022位于同一排。进一步，显示面板上具有多个重复单元106；在第二方向Y上，相邻的两个组合单元104构成一个重复单元106，重复单元106内的两个组合单元104中的两排正常邦定区1020上下交替排列。该重复单元106的设计方式可以降低制备显示面板的工艺复杂程度。
可选地，请继续参阅图8，在斜向方向上设置的相邻两像素单元122的数量大于在第一方向X或第二方向Y上同排设置的相邻两像素单元122的数量；其中，斜向方向与第一方向X和第二方向Y交叉，且上述所提及的相邻俩像素单元122中每个像素单元122中所有子像素120沿第一方向X或第二方向Y同排设置；若某个像素单元122中子像素120非同排设置则不在数量统计范围内。例如，以图8为例，左上角组合单元104对应的像素单元122与右上角组合单元104对应的像素单元122在第一斜向方向上相邻，左上角组合单元104对应的像素单元122与右下角组合单元104对应的像素单元122在第二斜向方向上相邻；第一斜向方向与第二斜向方向不同，但均与第一方向X和第二方向Y交 叉。上述设计方式可以使得相邻两像素单元122之间的间距尽可能增大。
当然，在其他实施例中，图8中的组合单元104的排布方式也可为其他。例如，请参阅图9，图9为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图9中像素单元122包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，组合单元104包括与该像素单元122中的子像素120电连接的三个邦定组102。组合单元104中三个正常邦定区1020位于同一排，组合单元104中三个冗余邦定区1022位于同一排。在第一方向X上，至少部分相邻的两个组合单元104呈轴对称设置，且呈轴对称设置的相邻两个组合单元104中对应相同发光颜色子像素的正常邦定区1020相对设置。
可选地，如图9中所示，显示面板上具有多个重复单元106，在第一方向X和第二方向Y上相邻的四个组合单元104(上下左右相邻的四个组合单元104)构成一个重复单元106；在第二方向Y上，重复单元106内的相邻两个组合单元104内的冗余邦定区1022和正常邦定区1020的排布方式相反。该设计方式可以降低工艺制备难度。在另一个应用场景中，请参阅图10，图10为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图10中与图8中实施例的差别在于仅在第一方向X上，相邻的两个组合单元104中两排正常邦定区1020之间设置有一排冗余邦定区1022；而在第二方向Y上，相邻的两个组合单元104中两排正常邦定区1020是相邻设置，即位于同一直线上。该结构设计较为简单，且工艺易于实现。
此外，图10中像素单元包括相邻的三个子像素120(红色子像素R、绿色子像素G和蓝色子像素B)，对应的组合单元104包括与该像素单元中的子像素120电连接的三个邦定组102。此时一个组合单元104形成一个重复单元106，该重复单元106的设计方式可以降低制备显示面板的工艺复杂程度。
当然，在其他实施例中，图10中组合单元的排布方式也可为其他。例如，请参阅图11，图11为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。在第一方向X上，至少部分相邻的两个组合单元104呈轴对称设置，且呈轴对称设置的两个组合单元104中对应相同发光颜色子像素的正常邦定区1020相邻设置；进一步，显示面板上设置有多个重复单元106，在第一方向X上相邻的两个组合单元104构成一个重复单元106。
请再次参阅图2或图4或图5或图7或图8，在第二方向Y上，位于同一排的所有正常邦定区1020和冗余邦定区1022的第二电极邦定区1062位于同一 直线上，且位于同一直线上的所有第二电极邦定区1062与同一电源电压线101电连接。该设计方式可以节省像素驱动电路的走线面积，尤其适用于高PPI或紧密排列的显示像素排布场景。
可选地，如图2或图4或图5或图7或图8中所示，在第一方向X上，电源电压线101位于两排第二电极邦定区1062之间，电源电压线101与相邻的两排第二电极邦定区1062电连接。该设计方式可以进一步节省像素驱动电路的走线面积，尤其适用于高PPI或紧密排列的显示像素排布场景。
另一可选地，如图2或或图4或图5或图7或图8中所示，当与电源电压线101电连接的第二电极邦定区1062用于与N电极邦定连接时，该电源电压线101可以提供VSS低电源电压。当然，当与电源电压线101电连接的第二电极邦定区1062用于与P电极邦定连接时，该电源电压线101可以提供VDD高电源电压，本申请对此不作限定。
此外，请继续参阅图2，子像素120包括第一对称轴L1，该第一对称轴L1的延伸方向与第一方向X平行设置。当然，在其他实施例中，子像素120的第一对称轴L1的延伸方向也可与第一方向X交叉设置，交叉设置的角度可以为30°或45°或90°等。
例如，请参阅图12，图12为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图12中所有子像素120的第一对称轴L1均与第一方向X交叉设置，且所有子像素120的第一对称轴L1相互平行设置。此时，图2中冗余邦定区1022和正常邦定区1020上的第一电极邦定区1060和第二电极邦定区1062的位置也会适应子像素120的位置旋转至图10中的位置。上述设计方式较为简单，且易于实现。
又例如，请参阅图13，图13为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。图13中所有子像素120的第一对称轴L1均与第一方向X交叉设置；且在第一方向X上，相邻两排子像素120的第一对称轴L1的延伸方向相互交叉设置。可选地，在第一方向X上，相邻两排子像素120的第一对称轴L1的延伸方向与第一方向X之间的夹角相等。上述设计方式较为简单，且易于实现。
请继续参阅图2，子像素120在第一表面上的正投影为矩形。或者，如图14所示，图14为图1中显示面板坏点修补前另一实施方式的局部俯视示意图。子像素120在第一表面上的正投影为圆角矩形。当然，在其他实施例中，子像 素120在第一表面上的正投影也可为圆形、椭圆形、三角形、梯形、五边形、六边形、或其他异形结构等，本申请对此不作限定。上述形状的子像素120易于工艺制备获得。且如图14所示，对于相邻两个正常邦定区1020上设置的子像素120的中心点之间的距离P1大于相邻正常邦定区1020和冗余邦定区1022上设置的子像素120的中心点之间的距离P2。
请参阅图15，图15为本申请显示面板的制备方法一实施方式的流程示意图，上述制备方法具体包括：
S101：提供驱动背板；其中，驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区；至少部分相邻的两个正常邦定区之间的第一间距大于相邻的正常邦定区和冗余邦定区之间的第二间距，且正常邦定区与相邻的冗余邦定区构成一个邦定组。
具体地，在本实施例中，驱动背板的结构可参见上述任一实施例，在此不再赘述。
S102：在驱动背板的正常邦定区上设置子像素。
具体地，可以通过巨量转移装置将多个子像素同时转移至对应位置处的正常邦定区上，且子像素与正常邦定区之间可以通过焊料等物质邦定连接。可选地，在本实施例中，步骤S102对应的图示可以参见上图2。
S103：响应于与正常邦定区邦定连接的子像素被确定为坏点子像素时，在同一邦定组内的冗余邦定区上引入具有相同发光颜色的修补子像素。
具体地，在本实施例中，在步骤S102之后，可以通过驱动背板对正常邦定区上的子像素进行点亮测试，若该子像素的亮度异常(包括亮度低于第一阈值或亮度超过第二阈值)，则将该子像素确定为坏点子像素。后续可以通过激光等方式将该坏点子像素从正常邦定区去除，并在同一邦定组内的冗余邦定区上设置一个具有相同发光颜色的修补子像素，以代替原正常邦定区上的子像素。例如，请参阅图16，图16为图2中显示面板修补后一实施方式的结构示意图。假设经过点亮测试后发现，图2中左上部的绿色子像素G为坏点子像素，则将该坏点子像素去除后，在对应的冗余邦定区上引入一个修补子像素120a，该修补子像素120a能够发出绿色光线。
或者，若该坏点子像素为断路子像素，则可将该坏点子像素保留，并在同一邦定组内的冗余邦定区上设置一个具有相同发光颜色的修补子像素，以代替原正常邦定区上的子像素。例如，请参阅图17，图17为图2中显示面板修补后 另一实施方式的结构示意图。假设经过点亮测试后发现，图2中左上部的绿色子像素G为坏点子像素，且该坏点子像素为断路子像素，其不能正常发出绿色光线；则将该坏点子像素保留，并在对应的冗余邦定区上引入一个修补子像素120a，该修补子像素120a能够发出绿色光线。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，包括：
    驱动背板，所述驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区；其中，至少部分相邻的两个所述正常邦定区之间的第一间距大于至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距，且所述正常邦定区与相邻的所述冗余邦定区构成一个邦定组；
    发光层，位于所述第一表面上，包括多个子像素，所述子像素与所述正常邦定区或所述冗余邦定区电连接，且同一邦定组内的所述正常邦定区或所述冗余邦定区用于与同一发光颜色的子像素电连接。
  2. 根据权利要求1所述的显示面板，其中，
    所述多个冗余邦定区至少有一个不与所述子像素电连接；和/或，
    同一邦定组内的所述正常邦定区优先于所述冗余邦定区与所述子像素电连接；和/或，
    与所述正常邦定区电连接的所述子像素的个数大于与所述冗余邦定区电连接的所述子像素的个数；和/或，
    所有所述子像素与所述正常邦定区电连接。
  3. 根据权利要求1所述的显示面板，其中，
    多个所述正常邦定区和多个所述冗余邦定区沿第一方向和第二方向呈阵列排布，且所述第一方向和所述第二方向相互交叉；
    其中，在所述第一方向上至少部分相邻的两个所述正常邦定区之间的第一间距大于在所述第一方向或所述第二方向上至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距；和/或，在所述第二方向上至少部分相邻的两个所述正常邦定区之间的第一间距大于在所述第一方向或所述第二方向至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距。
  4. 根据权利要求3所述的显示面板，其中，
    在所述第一方向和/或所述第二方向上，至少部分相邻的两个所述正常邦定区之间设置有所述冗余邦定区。
  5. 根据权利要求1所述的显示面板，其中，
    多个所述正常邦定区和多个所述冗余邦定区沿第一方向和第二方向呈阵列排布，且所述第一方向和所述第二方向相互交叉；相邻的多个所述子像素构成一个像素单元，与所述像素单元电连接的多个所述邦定组构成一个组合单元；
    在所述第一方向上，所述组合单元内的多个所述正常邦定区和多个所述冗余邦定区排列为两排，且所述组合单元内的多个所述正常邦定区在所述两排中交替排列，所述组合单元内的多个所述冗余邦定区在所述两排中交替排列。
  6. 根据权利要求5所述的显示面板，其中，
    在斜向方向上设置的相邻两子像素的数量大于在所述第一方向或所述第二方向上同排设置的相邻两子像素的数量；其中，所述斜向方向与所述第一方向和所述第二方向交叉。
  7. 根据权利要求5所述的显示面板，其中，
    同一所述邦定组内的所述正常邦定区和所述冗余邦定区沿所述第一方向排布，同一所述组合单元内的多个所述邦定组沿所述第二方向间隔排布。
  8. 根据权利要求5所述的显示面板，其中，
    同一所述邦定组内的所述正常邦定区和所述冗余邦定区沿所述第二方向间隔排布，同一所述组合单元内的多个所述邦定组沿所述第一方向排列为两排，且两排所述邦定组之间相互错位设置。
  9. 根据权利要求7或8所述的显示面板，其中，
    所述像素单元包括三个所述子像素，所述组合单元包括三个所述邦定组；在所述第二方向上，相邻的两个所述组合单元构成一个重复单元；所述重复单元内的多个所述正常邦定区上下交替排列，所述重复单元内的多个所述冗余邦定区上下交替排列。
  10. 根据权利要求7或8所述的显示面板，其中，
    所述像素单元包括三个所述子像素，所述组合单元包括三个所述邦定组；在所述第一方向上，至少部分相邻的两个所述组合单元呈轴对称设置，且呈轴对称设置的相邻两个所述组合单元中至少部分对应相同发光颜色子像素的所述正常邦定区相邻设置。
  11. 根据权利要求7或8所述的显示面板，其中，
    在所述第一方向上，分别来自于相邻两个所述组合单元中且相邻的两个所述正常邦定区之间的第三距离小于同一所述组合单元中的相邻两个所述正常邦定区之间的第四距离。
  12. 根据权利要求7或8所述的显示面板，其中，
    在所述第一方向和所述第二方向上相邻的四个所述组合单元构成一个重复单元；且在所述第二方向上所述重复单元内位于同一排的所述正常邦定区和所 述冗余邦定区交替排列。
  13. 根据权利要求1所述的显示面板，其中，
    多个所述正常邦定区和多个所述冗余邦定区沿第一方向和第二方向呈阵列排布，且所述第一方向和所述第二方向相互交叉；
    相邻的多个所述子像素构成一个像素单元，与所述像素单元电连接的多个所述邦定组构成一个组合单元；同一所述邦定组内的所述正常邦定区和所述冗余邦定区沿所述第一方向排布，且所述组合单元内的多个所述正常邦定区沿所述第二方向相邻排布于同一排，所述组合单元内的多个所述冗余邦定区沿所述第二方向相邻排布于同一排；
    其中，在所述第一方向和/或所述第二方向上，相邻的两个所述组合单元中的两排所述正常邦定区之间设置有一排所述冗余邦定区。
  14. 根据权利要求13所述的显示面板，其中，
    在斜向方向上设置的相邻两像素单元的数量大于在所述第一方向或所述第二方向上同排设置的相邻两像素单元的数量；其中，所述斜向方向与所述第一方向和所述第二方向交叉，所述相邻俩像素单元中每个所述像素单元中的所有所述子像素同排设置。
  15. 根据权利要求1所述的显示面板，其中，
    所述驱动背板还包括多个像素驱动电路，同一所述邦定组内的所述正常邦定区和所述冗余邦定区与同一像素驱动电路电连接。
  16. 根据权利要求15所述的显示面板，其中，
    每个所述子像素面向所述第一表面一侧设置有第一电极和第二电极，每个所述正常邦定区或所述冗余邦定区分别包括用于与所述第一电极电连接的第一电极邦定区、以及用于与所述第二电极电连接的第二电极邦定区；其中，同一所述邦定组内的两个所述第一电极邦定区与同一所述像素驱动电路的输出端电连接。
  17. 根据权利要求16所述的显示面板，其中，多个所述正常邦定区和多个所述冗余邦定区沿第一方向和第二方向呈阵列排布，且所述第一方向和所述第二方向相互交叉；在所述第二方向上，位于同一排的所有所述正常邦定区和所述冗余邦定区的所述第二电极邦定区位于同一直线上，且位于同一直线上的所有所述第二电极邦定区与同一电源电压线电连接。
  18. 根据权利要求17所述的显示面板，其中，
    在所述第一方向上，所述电源电压线位于两排所述第二电极邦定区之间，所述电源电压线与相邻的两排所述第二电极邦定区电连接。
  19. 根据权利要求16所述的显示面板，其中，
    在所述第一方向上，同一所述邦定组内的两个所述第一电极邦定区相对且间隔设置，同一所述邦定组内的两个所述第一电极邦定区位于两个所述第二电极邦定区之间；其中，在所述第一方向上，所述像素驱动电路的输出端在所述第一表面的正投影位于两个所述第一电极邦定区之间；
    或者，在所述第二方向上，同一所述邦定组内的两个所述第一电极邦定区相对且间隔设置，同一所述邦定组内的两个所述第二电极邦定区相对且间隔设置；其中，在所述第一方向上，同一所述组合单元内的两排所述邦定组之间具有间隙，所述像素驱动电路的输出端在所述第一表面的正投影位于所述间隙内，且位于同一所述邦定组内的两个所述第一电极邦定区之间。
  20. 一种显示面板的制备方法，其中，包括：
    提供驱动背板；其中，所述驱动背板的第一表面设置有多个正常邦定区和多个冗余邦定区，至少部分相邻的两个所述正常邦定区之间的第一间距大于至少部分相邻的所述正常邦定区和所述冗余邦定区之间的第二间距，且所述正常邦定区与相邻的所述冗余邦定区构成一个邦定组；
    在所述驱动背板的所述正常邦定区上设置子像素；
    响应于与所述正常邦定区邦定连接的所述子像素被确定为坏点子像素时，在同一邦定组内的所述冗余邦定区上引入具有相同发光颜色的修补子像素。
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