WO2023097741A1 - 像素电路及显示装置 - Google Patents

像素电路及显示装置 Download PDF

Info

Publication number
WO2023097741A1
WO2023097741A1 PCT/CN2021/136813 CN2021136813W WO2023097741A1 WO 2023097741 A1 WO2023097741 A1 WO 2023097741A1 CN 2021136813 W CN2021136813 W CN 2021136813W WO 2023097741 A1 WO2023097741 A1 WO 2023097741A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrically connected
transistor
unit
input terminal
signal input
Prior art date
Application number
PCT/CN2021/136813
Other languages
English (en)
French (fr)
Inventor
曾勉
孙亮
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/622,778 priority Critical patent/US20240038160A1/en
Publication of WO2023097741A1 publication Critical patent/WO2023097741A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, in particular to a pixel circuit and a display device.
  • the pixel circuit is an important element for driving the light-emitting unit of the display device to emit light, and the stability and sensitivity of its working performance directly affect the display effect of the display device.
  • the transistors used in the 7T1C (composed of 7 transistors and 1 storage capacitor) pixel circuits are mostly low-temperature polysilicon transistors. This is because the transistors are low in cost, simple in process, and mature in technology, but there is an obvious defect in them. It is a large leakage current, which is mainly manifested in the obvious leakage current problem of the transistor directly connected to the driving transistor in the pixel circuit, which leads to the abnormal operation of the driving transistor, which in turn leads to abnormal display.
  • the current solution is to set the transistor connected to the driving transistor as a double-gate transistor or replace it with a metal oxide transistor, but the double-gate transistor cannot effectively alleviate the leakage current due to the large parasitic capacitance, while the metal oxide transistor exists The problem of high cost and complicated manufacturing process.
  • the pixel circuit has a technical problem of large leakage current.
  • the present application provides a pixel circuit and a display device, which are used to alleviate the technical problem of large leakage current in current pixel circuits.
  • the present application provides a pixel circuit, which includes:
  • the drive unit is electrically connected between the first power input terminal and the light emitting unit;
  • a lighting control unit electrically connected between the first power input terminal and the lighting unit, and electrically connected to the driving unit, and the lighting control unit is electrically connected to the control signal input terminal;
  • the compensation unit is electrically connected between the driving unit and the light emission control unit, and a first capacitor is electrically connected between the compensation unit and the control signal input end.
  • the compensation unit includes a double-gate transistor, the double-gate transistor includes a first channel and a second channel, and the first end of the first capacitor is electrically connected to the first channel and the second channel.
  • the double-gate transistor includes a first sub-transistor and a second sub-transistor
  • the first sub-transistor includes the first channel, and a first source and a first drain disposed at opposite ends of the first channel, and the first source is electrically connected to the driving unit and the lighting control unit;
  • the second sub-transistor includes the second channel, a second source and a second drain disposed at opposite ends of the second channel, and the second drain is electrically connected to the driving unit ;
  • the first drain is electrically connected to the second source, and the first end of the first capacitor is electrically connected to the first drain.
  • the first end of the first capacitor is electrically connected to the second source.
  • the light emission control unit includes a first light emission control unit and a second light emission control unit
  • the control signal input terminal includes a first control signal input electrically connected to the first light emission control unit terminal and a second control signal input terminal electrically connected to the second lighting control unit.
  • the first light emission control unit is electrically connected between the first power input terminal and the driving unit
  • the second light emission control unit is electrically connected between the driving unit and the driving unit. between the light emitting units.
  • the second end of the first capacitor is electrically connected to the first control signal input end.
  • the second end of the first capacitor is electrically connected to the second control signal input end.
  • the pixel circuit further includes:
  • a reset unit electrically connected between the reset signal input terminal and the light emitting unit
  • the storage unit is electrically connected between the first power input terminal and the driving unit.
  • the driving unit includes a first transistor, and a gate of the first transistor is electrically connected to a drain of the double-gate transistor.
  • the first light emission control unit includes a second transistor
  • the second light emission control unit includes a third transistor
  • the gate, source and drain of the first transistor are respectively electrically connected to To the drain of the double-gate transistor, the drain of the second transistor, and the source of the third transistor, the gate, source, and drain of the second transistor are electrically connected to the first a control signal input terminal, the first power input terminal and the source of the first transistor, and the gate, source and drain of the third transistor are respectively electrically connected to the second control signal input terminal, The drain of the first transistor and the light emitting unit.
  • the input unit includes a fourth transistor, the gate, source and drain of the fourth transistor are respectively electrically connected to the first scan signal input terminal, the data signal input terminal and the source of the first transistor.
  • the reset unit includes a fifth transistor, and the gate, source and drain of the fifth transistor are electrically connected to the second scanning signal input terminal, the reset signal input terminal and the second scanning signal input terminal respectively. the drain of the third transistor.
  • the storage unit includes a second capacitor, and opposite ends of the second capacitor are electrically connected to the first power input terminal and the gate of the first transistor, respectively.
  • the gate of the double-gate transistor is electrically connected to the second scan signal input terminal.
  • the double-gate transistor is a low-temperature polysilicon transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all low temperature polysilicon transistors.
  • the present application also provides a display device, which includes a pixel circuit, and the pixel circuit includes:
  • the drive unit is electrically connected between the first power input terminal and the light emitting unit;
  • a lighting control unit electrically connected between the first power input terminal and the lighting unit, and electrically connected to the driving unit, and the lighting control unit is electrically connected to the control signal input terminal;
  • the compensation unit is electrically connected between the driving unit and the light emission control unit, and a first capacitor is electrically connected between the compensation unit and the control signal input terminal.
  • the compensation unit includes a double-gate transistor, the double-gate transistor includes a first channel and a second channel, and the first end of the first capacitor is electrically connected to the first Between the channel and the second channel, the second end of the first capacitor is electrically connected to the control signal input end.
  • the present application also provides a pixel circuit, which includes:
  • the drive unit is electrically connected between the first power input terminal and the light emitting unit;
  • a lighting control unit electrically connected between the first power input terminal and the lighting unit, and electrically connected to the driving unit, and the lighting control unit is electrically connected to the control signal input terminal;
  • a compensation unit electrically connected between the driving unit and the light emission control unit, the compensation unit includes a double-gate transistor, and the double-gate transistor includes a first channel and a second channel;
  • a first capacitor electrically connected between the compensation unit and the control signal input terminal, a first end of the first capacitor electrically connected between the first channel and the second channel , the second end of the first capacitor is electrically connected to the control signal input end.
  • the present application provides a pixel circuit and a display device.
  • the pixel circuit includes a drive unit, a light emission control unit, and a compensation unit. Both the drive unit and the light emission control unit are electrically connected between the first power input terminal and the light emission unit, and both The lighting control unit is electrically connected to the control signal input end, the compensation unit is electrically connected between the driving unit and the lighting control unit, and is electrically connected to the first capacitor with the control signal input end.
  • the first capacitive coupling effect is used to reduce or eliminate the parasitic capacitance in the compensation unit, thereby reducing the parasitic voltage inside the compensation unit, effectively alleviating the compensation unit
  • the leakage problem to the driving unit improves the stability of the pixel circuit and improves the display quality of the display device.
  • FIG. 1 is a structural schematic diagram of a first type of pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a partial timing diagram of the pixel circuit shown in FIG. 1 .
  • FIG. 3 is a structural schematic diagram of a second type of pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a partial timing diagram of the pixel circuit shown in FIG. 3 .
  • An embodiment of the present application provides a pixel circuit and a display device.
  • the pixel circuit includes a drive unit, a light emission control unit, and a compensation unit. Both the drive unit and the light emission control unit are electrically connected to the first power input terminal and the light emission unit.
  • the lighting control unit is electrically connected to the control signal input terminal, and the compensation unit is electrically connected between the driving unit and the lighting control unit and is connected to the control signal input terminal.
  • the first capacitor is electrically connected between them.
  • the first capacitive coupling effect is used to reduce or eliminate the parasitic capacitance in the compensation unit, thereby reducing the parasitic capacitance inside the compensation unit.
  • the voltage can effectively relieve the leakage problem from the compensation unit to the drive unit, improve the stability of the pixel circuit, and improve the display quality of the display device.
  • FIG. 1 is a schematic structural diagram of a first pixel circuit provided in an embodiment of the present application.
  • the pixel circuit includes a drive unit 10, a light emission control unit, a compensation unit 30, an input unit 40, a reset unit 50, and a storage unit 60, wherein the light emission control unit may include a first light emission control unit 21 and a second light emission control unit twenty two.
  • the driving unit 10 and the lighting control unit are used to drive and control the lighting unit L to emit light;
  • the compensation unit 30 is used to compensate the control terminal voltage of the driving unit 10;
  • the input unit 40 is used to input data signals And drive the light emitting unit L to emit light through the driving unit 10;
  • the reset unit 50 is used to reset the control terminal voltage of the driving unit, and reset the input terminal voltage of the light emitting unit L;
  • the storage unit 60 is used to save the control terminal voltage of the driving unit 10 .
  • the driving unit 10 is electrically connected between the first power input terminal VDD and the light emitting unit L, and the first power input terminal VDD is used to input a first power signal to the pixel circuit.
  • the driving unit 10 Driving the first power signal input from the first power input terminal VDD is transmitted to the light emitting unit L, and then drives the light emitting unit L to emit light.
  • the lighting control unit is electrically connected between the first power input terminal VDD and the lighting unit L, and is electrically connected to the driving unit 10, and is also electrically connected to the control signal input terminal. connected, and under the action of the control signal input from the control signal input end, the electrical conduction relationship between the first power input end VDD and the light emitting unit L is controlled.
  • the lighting control unit and the driving unit 10 jointly control whether the first power signal can flow to the lighting unit L, and then control the lighting state of the lighting unit L.
  • the driving unit 10 transmits the first power signal to the lighting unit L to realize the lighting of the lighting unit L;
  • the path between the first power input terminal VDD and the light emitting unit L is cut off, and the light emitting unit L does not emit light.
  • the light-emitting control unit realizes the switch between the on state and the off state.
  • the light emission control unit includes a first light emission control unit 21 and a second light emission control unit 22, the first light emission control unit 21 is electrically connected between the first power input terminal VDD and the drive unit 10 Between, the second lighting control unit 22 is electrically connected between the driving unit 10 and the lighting unit L. Therefore, the path between the first power input terminal VDD and the driving unit 10 is controlled by the first light emitting control unit 21, and the path between the driving unit 10 and the light emitting unit L is controlled by the Controlled by the second light emitting control unit 22 , the first light emitting control unit 21 and the second light emitting control unit 22 jointly control the electrical conduction relationship between the first power input single VDD and the light emitting unit L.
  • the first lighting control unit 21 is electrically connected to the first control signal input terminal EM1, and under the action of the first control signal input from the first control signal input terminal EM1, it is turned on and off;
  • the second lighting control unit The unit 22 is electrically connected to the second control signal input terminal EM2, and is turned on and off under the action of the second control signal input from the second control signal input terminal EM2.
  • the compensation unit 30 is electrically connected between the driving unit 10 and the light emission control unit, specifically, the compensation unit 30 is directly electrically connected to the second light emission control unit 22, and the compensation unit 30 It is also electrically connected with the second scan signal input terminal S2.
  • the second scanning signal input terminal S2 provides the second scanning signal to the compensation unit, and drives the compensation unit 30 to compensate the voltage of the control terminal of the driving unit 10 .
  • a first capacitor C1 is electrically connected between the compensation unit 30 and the input terminal of the control signal, specifically, the first capacitor C1 is electrically connected between the compensation unit 30 and the second control signal input terminal. between the input terminals EM2 and couple the parasitic capacitance generated in the compensation unit 30 to reduce or eliminate the parasitic capacitance.
  • the coupling effect of the first capacitor C1 is used to reduce or eliminate the parasitic capacitance in the compensation unit 30, thereby reducing the parasitic voltage inside the compensation unit 30, effectively alleviating the problem of leakage from the compensation unit 30 to the drive unit 10, which is beneficial
  • the stability of the pixel circuit is improved, and the display quality of the display device is improved.
  • the input unit 40 is electrically connected between the data signal input terminal Da and the driving unit 10 for transmitting data signals to the driving unit 10 to regulate the driving state of the driving unit 10 .
  • the input unit 40 is also electrically connected to the first scan signal input terminal S1, and the first scan signal provided by the first scan signal input terminal S1 controls the opening or closing of the input unit 40 .
  • one end of the input unit 40 is connected between the first lighting control unit 21 and the driving unit 10 .
  • the reset unit 50 is electrically connected between the reset signal input terminal V and the light emitting unit L for providing a reset signal to the light emitting unit L, and the reset unit 50 is also connected to the second scan signal input terminal S2 is electrically connected, and the second scan signal provided by the second scan signal input terminal S2 controls the reset unit 50 to be turned on or off.
  • one end of the reset unit 50 is connected between the light emitting unit L and the second light emitting control unit 22 , and the reset unit 50 passes through the second light emitting control unit 22 and the compensation unit 30 It is electrically connected to the control terminal of the driving unit 10 so as to reset the voltage of the control terminal of the driving unit 10 .
  • the storage unit 60 is electrically connected between the first power input terminal VDD and the driving unit 10 for storing the voltage of the control terminal of the driving unit 10 .
  • the other end of the light emitting unit L is electrically connected to the second power input terminal VSS, and the second power input terminal VSS provides the light emitting unit L with a second power signal.
  • both the first power signal and the second power signal are voltage signals, and the voltage of the first power signal is greater than the voltage of the second power signal.
  • the compensation unit 30 includes a double-gate transistor, the double-gate transistor includes a first channel D1 and a second channel D2, and the first end of the first capacitor C1 is electrically connected to the first channel. Between the channel D1 and the second channel D2, the second terminal of the first capacitor C1 is electrically connected to the second control signal input terminal EM2, and the coupling effect of the first capacitor C1 is used to eliminate or reduce the small parasitic capacitances within the double-gate transistor.
  • the gate of the double-gate transistor is electrically connected to the second scan signal input terminal S2.
  • the double-gate transistor includes a first sub-transistor T61 and a second sub-transistor T62, the first sub-transistor T61 includes the first channel D1, and two transistors arranged at opposite ends of the first channel D1 A first source and a first drain, the second sub-transistor T62 includes the second channel D2, and a second source and a second drain disposed at opposite ends of the second channel D2, so The first drain is electrically connected to the second source, and the first end of the first capacitor C1 is electrically connected to the first drain or is electrically connected to the second source.
  • the first source is electrically connected to the driving unit 10
  • the second drain is electrically connected to the control terminal of the driving unit 10 .
  • Both the gate of the first sub-transistor T61 and the gate of the second sub-transistor T62 are electrically connected to the second scan signal input terminal S2.
  • the drive unit 10 includes a first transistor T1
  • the first light emission control unit 21 includes a second transistor T2
  • the second light emission control unit 22 includes a third transistor T3, and the gate of the first transistor T1
  • the pole, the source and the drain are respectively electrically connected to the drain of the double-gate transistor, the drain of the second transistor T2, and the source of the third transistor T3, and the gate of the second transistor T2
  • the electrode and the source are electrically connected to the first control signal input terminal EM1 and the first power input terminal VDD respectively
  • the gate and drain of the third transistor T3 are electrically connected to the second control signal input terminal terminal EM2 and the light emitting unit L.
  • the input unit 40 includes a fourth transistor T4, the gate, source and drain of the fourth transistor T4 are electrically connected to the first scan signal input terminal S1, the data signal input terminal Da and the first scan signal input terminal Da and the fourth transistor T4, respectively.
  • the reset unit 50 includes a fifth transistor T5, the gate, source and drain of the fifth transistor T5 are respectively electrically connected to the second scan signal input terminal S2, the reset signal input terminal V and the first Drain of transistor T3.
  • the storage unit 60 includes a second capacitor C2, and opposite ends of the second capacitor C2 are electrically connected to the first power input terminal VDD and the gate of the first transistor T1, respectively.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the double-gate transistor are low temperature polysilicon transistors. It can be understood that the pixel circuits provided in this embodiment all use low-temperature polysilicon transistors. Since the material cost of low-temperature polysilicon transistors is low, and the manufacturing process is simple and mature, this embodiment can reduce product costs and improve product yield and quality.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the double-gate transistor mentioned in this embodiment are all symmetrical transistors, that is, each transistor
  • the source and drain of the transistor can be interchanged regardless of the relationship between the current flow and the source and drain of the transistor.
  • the working principle of the pixel circuit provided by this embodiment will be described below with reference to FIG. 2 , and the pixel circuit has at least the following working stages.
  • both the second control signal input terminal EM2 and the second scanning signal input terminal S2 input a low-level signal, the fifth transistor T5, the third transistor T3 and the double-gate transistor are turned on, and the reset signal input terminal V is connected to the first transistor.
  • the gate voltage of T1 is initialized.
  • the driving unit is charged.
  • both the first scanning signal input terminal S1 and the second scanning signal input terminal S2 input low-level signals
  • the first control signal input terminal EM1 and the second control signal input terminal EM2 both input high-level signals
  • the fourth The transistor T4, the fifth transistor T5 and the double-gate transistor are turned on
  • the second transistor T2 and the third transistor T3 are turned off
  • the data signal input from the data signal input terminal Da charges the gate of the first transistor T1 and stores it in the second capacitor C2, at the same time, the reset signal input terminal V resets the input terminal of the light emitting unit L.
  • the internal potential of the double-gate transistor is coupled to a higher value; at the last moment of the time period t3, the input signal of the second control signal input terminal EM2 changes from a high level to a low level, at Under the coupling effect of the first capacitor C1, the internal potential of the double-gate transistor is coupled to a lower value, which is lower than the gate potential of the first transistor T1, thereby weakening or eliminating the leakage from the double-gate transistor to the first transistor T1 current.
  • both the first control signal input terminal EM1 and the second control signal input terminal EM2 input a low-level signal, the second transistor T2 and the third transistor T3 are turned on, and under the action of the data signal stored in the second capacitor C2, The first transistor T1 drives the light emitting unit L to emit light.
  • FIG. 3 is a schematic structural diagram of a second pixel circuit provided in an embodiment of the present application. It can be understood that the pixel circuit shown in FIG. 3 has the same or similar features as the pixel circuit shown in FIG. 1. The features of the pixel circuit shown in FIG. Example records.
  • the pixel circuit includes a drive unit 10, a light emission control unit, a compensation unit 30, an input unit 40, a reset unit 50, and a storage unit 60, wherein the light emission control unit may include a first light emission control unit 21 and a second light emission control unit twenty two.
  • the driving unit 10 is electrically connected between the first power input terminal VDD and the light emitting unit L, the first power input terminal VDD is used to input a first power signal to the pixel circuit, and the driving unit 10 drives the pixel circuit.
  • the first power signal input from the first power input terminal VDD is transmitted to the light emitting unit L, and then the light emitting unit L is driven to emit light.
  • the lighting control unit is electrically connected between the first power input terminal VDD and the lighting unit L, and is electrically connected to the driving unit 10, and is also electrically connected to the control signal input terminal. connected, and under the action of the control signal input from the control signal input end, the electrical conduction relationship between the first power input end VDD and the light emitting unit L is controlled.
  • the light emission control unit includes a first light emission control unit 21 and a second light emission control unit 22, the first light emission control unit 21 is electrically connected between the first power input terminal VDD and the drive unit 10, so The second lighting control unit 22 is electrically connected between the driving unit 10 and the lighting unit L. As shown in FIG.
  • the first lighting control unit 21 is electrically connected to the first control signal input terminal EM1, and under the action of the first control signal input from the first control signal input terminal EM1, it is turned on and off;
  • the second lighting control unit The unit 22 is electrically connected to the second control signal input terminal EM2, and is turned on and off under the action of the second control signal input from the second control signal input terminal EM2.
  • the compensation unit 30 is electrically connected between the driving unit 10 and the light emission control unit, specifically, the compensation unit 30 is directly electrically connected to the second light emission control unit 22, and the compensation unit 30 It is also electrically connected with the second scan signal input terminal S2.
  • the second scanning signal input terminal S2 provides the second scanning signal to the compensation unit, and drives the compensation unit 30 to compensate the voltage of the control terminal of the driving unit 10 .
  • a first capacitor C1 is electrically connected between the compensation unit 30 and the control signal input terminal, specifically, the first capacitor C1 is electrically connected between the compensation unit 30 and the first control signal input terminal EM1 used to couple the parasitic capacitance generated in the compensation unit 30 to achieve the effect of reducing or eliminating the parasitic capacitance, thereby effectively alleviating the leakage problem of the compensation unit 30 to the driving unit 10, which is beneficial to improve the pixel circuit stability, and improve the display quality of the display device.
  • the input unit 40 is electrically connected between the data signal input terminal Da and the driving unit 10 for transmitting data signals to the driving unit 10 to regulate the driving state of the driving unit 10 .
  • the input unit 40 is also electrically connected to the first scan signal input terminal S1, and the first scan signal provided by the first scan signal input terminal S1 controls the opening or closing of the input unit 40 .
  • one end of the input unit 40 is connected between the first lighting control unit 21 and the driving unit 10 .
  • the reset unit 50 is electrically connected between the reset signal input terminal V and the light emitting unit L for providing a reset signal to the light emitting unit L, and the reset unit 50 is also connected to the second scan signal input terminal S2 is electrically connected, and the second scan signal provided by the second scan signal input terminal S2 controls the reset unit 50 to be turned on or off.
  • one end of the reset unit 50 is connected between the light emitting unit L and the second light emitting control unit 22 , and the reset unit 50 passes through the second light emitting control unit 22 and the compensation unit 30 It is electrically connected to the control terminal of the driving unit 10 so as to reset the voltage of the control terminal of the driving unit 10 .
  • the storage unit 60 is electrically connected between the first power input terminal VDD and the driving unit 10 for storing the voltage of the control terminal of the driving unit 10 .
  • the other end of the light emitting unit L is electrically connected to the second power input terminal VSS, and the second power input terminal VSS provides the light emitting unit L with a second power signal.
  • both the first power signal and the second power signal are voltage signals, and the voltage of the first power signal is greater than the voltage of the second power signal.
  • the compensation unit 30 includes a double-gate transistor, the double-gate transistor includes a first channel D1 and a second channel D2, and the first end of the first capacitor C1 is electrically connected to the first channel. Between the channel D1 and the second channel D2, the second terminal of the first capacitor C1 is electrically connected to the first control signal input terminal EM1, and the coupling effect of the first capacitor C1 is used to eliminate or reduce the small parasitic capacitances within the double-gate transistor.
  • the gate of the double-gate transistor is electrically connected to the second scan signal input terminal S2.
  • the double-gate transistor includes a first sub-transistor T61 and a second sub-transistor T62, the first sub-transistor T61 includes the first channel D1, and two transistors arranged at opposite ends of the first channel D1 A first source and a first drain, the second sub-transistor T62 includes the second channel D2, and a second source and a second drain disposed at opposite ends of the second channel D2, so The first drain is electrically connected to the second source, and the first end of the first capacitor C1 is electrically connected to the first drain or is electrically connected to the second source.
  • the first source is electrically connected to the driving unit 10
  • the second drain is electrically connected to the control terminal of the driving unit 10 .
  • Both the gate of the first sub-transistor T61 and the gate of the second sub-transistor T62 are electrically connected to the second scan signal input terminal S2.
  • the drive unit 10 includes a first transistor T1
  • the first light emission control unit 21 includes a second transistor T2
  • the second light emission control unit 22 includes a third transistor T3, and the gate of the first transistor T1
  • the pole, the source and the drain are respectively electrically connected to the drain of the double-gate transistor, the drain of the second transistor T2, and the source of the third transistor T3, and the gate of the second transistor T2
  • the electrode and the source are electrically connected to the first control signal input terminal EM1 and the first power input terminal VDD respectively
  • the gate and drain of the third transistor T3 are electrically connected to the second control signal input terminal terminal EM2 and the light emitting unit L.
  • the input unit 40 includes a fourth transistor T4, the gate, source and drain of the fourth transistor T4 are electrically connected to the first scan signal input terminal S1, the data signal input terminal Da and the first scan signal input terminal Da and the fourth transistor T4, respectively.
  • the reset unit 50 includes a fifth transistor T5, the gate, source and drain of the fifth transistor T5 are respectively electrically connected to the second scan signal input terminal S2, the reset signal input terminal V and the first Drain of transistor T3.
  • the storage unit 60 includes a second capacitor C2, and opposite ends of the second capacitor C2 are electrically connected to the first power input terminal VDD and the gate of the first transistor T1, respectively.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the double-gate transistor are low temperature polysilicon transistors. It can be understood that the pixel circuits provided in this embodiment all use low-temperature polysilicon transistors. Since the material cost of low-temperature polysilicon transistors is low, and the manufacturing process is simple and mature, this embodiment can reduce product costs and improve product yield and quality.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the double-gate transistor mentioned in this embodiment are all symmetrical transistors, that is, each transistor
  • the source and drain of the transistor can be interchanged regardless of the relationship between the current flow and the source and drain of the transistor.
  • both the second control signal input terminal EM2 and the second scanning signal input terminal S2 input a low-level signal, the fifth transistor T5, the third transistor T3 and the double-gate transistor are turned on, and the reset signal input terminal V is connected to the first transistor.
  • the gate voltage of T1 is initialized.
  • the driving unit is charged.
  • both the first scanning signal input terminal S1 and the second scanning signal input terminal S2 input low-level signals
  • the first control signal input terminal EM1 and the second control signal input terminal EM2 both input high-level signals
  • the fourth The transistor T4, the fifth transistor T5 and the double-gate transistor are turned on
  • the second transistor T2 and the third transistor T3 are turned off
  • the data signal input from the data signal input terminal Da charges the gate of the first transistor T1 and stores it in the second capacitor C2, at the same time, the reset signal input terminal V resets the input terminal of the light emitting unit L.
  • the first scanning signal input terminal S1 and the second scanning signal input terminal S2 change to input a high-level signal
  • the double-gate transistor is turned off, and the first control signal input terminal EM1 inputs a high-level signal.
  • the internal potential of the double-gate transistor is coupled to a higher value; at the last moment of the time period t3, the input signal of the first control signal input terminal EM1 changes from a high level to a low level, at Under the coupling effect of the first capacitor C1, the internal potential of the double-gate transistor is coupled to a lower value, which is lower than the gate potential of the first transistor T1, thereby weakening or eliminating the leakage from the double-gate transistor to the first transistor T1 current.
  • both the first control signal input terminal EM1 and the second control signal input terminal EM2 input a low-level signal, the second transistor T2 and the third transistor T3 are turned on, and under the action of the data signal stored in the second capacitor C2, The first transistor T1 drives the light emitting unit L to emit light.
  • the pixel circuit provided by the embodiment of the present application includes a driving unit, a light emitting control unit and a compensation unit, and the driving unit and the light emitting control unit are both electrically connected between the first power input terminal and the light emitting unit.
  • the two are electrically connected, the lighting control unit is electrically connected to the control signal input end, and the compensation unit is electrically connected between the driving unit and the lighting control unit and is electrically connected to the control signal input end.
  • An embodiment of the present application further provides a display device, the display device including the pixel circuit described in any one of the foregoing embodiments. It can be understood that the display device exhibits better display quality due to the inclusion of the above-mentioned pixel circuit, and compared with the prior art, the leakage current of the internal circuit of the display device and the display problems caused by the leakage current are significantly reduced. improve.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路及显示装置，其中，像素电路包括驱动单元（10）、发光控制单元和补偿单元（30），驱动单元（10）和发光控制单元均电性连接于第一电源输入端（VDD）与发光单元（L）之间且二者电性连接，发光控制单元电性连接控制信号输入端，补偿单元（30）电性连接于驱动单元（10）与发光控制单元之间且与控制信号输入端之间电性连接第一电容（C1）。

Description

像素电路及显示装置
本申请要求于2021年12月03日提交中国专利局、申请号为202111464063.9、发明名称为“像素电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及显示装置。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求也越来越高，尤其是智能手机领域，超高频驱动显示、低功耗驱动显示以及低频驱动显示都是现阶段和未来的重要发展方向。
像素电路作为驱动显示装置的发光单元进行发光的重要元件，其工作性能的稳定性及灵敏性直接影响显示装置的显示效果。目前7T1C（由7个晶体管和1个存储电容组成）像素电路中使用的晶体管多为低温多晶硅晶体管，这是因为这种晶体管的成本低、工艺简单、且技术成熟，但其存在的一个明显缺陷是漏电流较大，主要表现为与像素电路中的驱动晶体管直接连接的晶体管存在明显的漏电流问题，导致驱动晶体管的工作异常，进而导致显示异常。目前的解决方案是将与驱动晶体管连接的晶体管设置为双栅晶体管或采用金属氧化物晶体管替代，但是双栅晶体管由于存在较大的寄生电容而无法有效缓解漏电流，而金属氧化物晶体管则存在成本高、制作工艺复杂的问题。
 技术问题
目前像素电路存在漏电流大的技术问题。
 技术解决方案
本申请提供一种像素电路及显示装置，用于缓解目前像素电路存在的漏电流大的技术问题。
本申请提供一种像素电路，其包括：
驱动单元，电性连接于第一电源输入端与发光单元之间；
发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，且所述补偿单元与所述控制信号输入端之间电性连接第一电容。
在本申请的像素电路中，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间。
在本申请的像素电路中，所述双栅晶体管包括第一子晶体管和第二子晶体管；
所述第一子晶体管包括所述第一沟道、以及设置于所述第一沟道相对两端的第一源极和第一漏极，所述第一源极电性连接于所述驱动单元与所述发光控制单元之间；
所述第二子晶体管包括所述第二沟道、以及设置于所述第二沟道相对两端的第二源极和第二漏极，所述第二漏极与所述驱动单元电性连接；
所述第一漏极与所述第二源极电性连接，所述第一电容的第一端与所述第一漏极电性连接。
在本申请的像素电路中，所述第一电容的第一端与所述第二源极电性连接。
在本申请的像素电路中，所述发光控制单元包括第一发光控制单元和第二发光控制单元，所述控制信号输入端包括与所述第一发光控制单元电性连接的第一控制信号输入端和与所述第二发光控制单元电性连接的第二控制信号输入端。
在本申请的像素电路中，所述第一发光控制单元电性连接于所述第一电源输入端与所述驱动单元之间，所述第二发光控制单元电性连接于所述驱动单元与所述发光单元之间。
在本申请的像素电路中，所述第一电容的第二端与所述第一控制信号输入端电性连接。
在本申请的像素电路中，所述第一电容的第二端与所述第二控制信号输入端电性连接。
在本申请的像素电路中，所述像素电路还包括：
复位单元，电性连接于复位信号输入端与所述发光单元之间；
输入单元，电性连接于数据信号输入端与所述驱动单元之间；
存储单元，电性连接于所述第一电源输入端与所述驱动单元之间。
在本申请的像素电路中，所述驱动单元包括第一晶体管，所述第一晶体管的栅极电性连接所述双栅晶体管的漏极。
在本申请的像素电路中，所述第一发光控制单元包括第二晶体管，所述第二发光控制单元包括第三晶体管，所述第一晶体管的栅极、源极和漏极分别电性连接至所述双栅晶体管的漏极、所述第二晶体管的漏极、以及所述第三晶体管的源极，所述第二晶体管的栅极、源极和漏极分别电性连接所述第一控制信号输入端、所述第一电源输入端和所述第一晶体管的源极，所述第三晶体管的栅极、源极和漏极分别电性连接所述第二控制信号输入端、所述第一晶体管的漏极和所述发光单元。
在本申请的像素电路中，所述输入单元包括第四晶体管，所述第四晶体管的栅极、源极和漏极分别电性连接至第一扫描信号输入端、所述数据信号输入端和所述第一晶体管的源极。
在本申请的像素电路中，所述复位单元包括第五晶体管，所述第五晶体管的栅极、源极和漏极分别电性连接至第二扫描信号输入端、所述复位信号输入端和所述第三晶体管的漏极。
在本申请的像素电路中，所述存储单元包括第二电容，所述第二电容的相对两端分别电性连接至所述第一电源输入端和所述第一晶体管的栅极。
在本申请的像素电路中，所述双栅晶体管的栅极电性连接至所述第二扫描信号输入端。
在本申请的像素电路中，所述双栅晶体管为低温多晶硅晶体管。
在本申请的像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为低温多晶硅晶体管。
本申请还提供一种显示装置，其包括像素电路，所述像素电路包括：
驱动单元，电性连接于第一电源输入端与发光单元之间；
发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，且所述补偿单元与所述控制信号输入端之间电性连接第一电容。
在本申请的显示装置中，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间，所述第一电容的第二端电性连接所述控制信号输入端。
本申请还提供一种像素电路，其包括：
驱动单元，电性连接于第一电源输入端与发光单元之间；
发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道；以及
第一电容，电性连接于所述补偿单元与所述控制信号输入端之间，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间，所述第一电容的第二端电性连接所述控制信号输入端。
 有益效果
本申请提供一种像素电路及显示装置，该像素电路包括驱动单元、发光控制单元和补偿单元，驱动单元和发光控制单元均电性连接于第一电源输入端与发光单元之间且二者电性连接，发光控制单元电性连接控制信号输入端，补偿单元电性连接于驱动单元与发光控制单元之间且与控制信号输入端之间电性连接第一电容。本申请通过在补偿单元与控制信号输入端之间电性连接第一电容，利用第一电容耦合作用减小或消除补偿单元内的寄生电容，进而降低补偿单元内部的寄生电压，有效缓解补偿单元向驱动单元的漏电问题，提高了该像素电路的稳定性，改善了显示装置的显示品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的第一种像素电路的结构原理图。
图2是图1所示的像素电路的部分时序图。
图3是本申请实施例提供的第二种像素电路的结构原理图。
图4是图3所示的像素电路的部分时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种像素电路及显示装置，该像素电路包括驱动单元、发光控制单元和补偿单元，所述驱动单元和所述发光控制单元均电性连接于第一电源输入端与发光单元之间且二者电性连接，所述发光控制单元电性连接控制信号输入端，所述补偿单元电性连接于所述驱动单元与所述发光控制单元之间且与所述控制信号输入端之间电性连接第一电容。本申请实施例提供的像素电路通过在补偿单元与控制信号输入端之间电性连接第一电容，利用第一电容耦合作用减小或消除补偿单元内的寄生电容，进而降低补偿单元内部的寄生电压，有效缓解补偿单元向驱动单元的漏电问题，提高了该像素电路的稳定性，改善了显示装置的显示品质。
下面结合具体实施例对本申请提供的像素电路的结构和功能进行阐述。
在一种实施例中，请参阅图1，图1是本申请实施例提供的第一种像素电路的结构原理图。该像素电路包括驱动单元10、发光控制单元、补偿单元30、输入单元40、复位单元50、以及存储单元60，其中，所述发光控制单元可以包括第一发光控制单元21和第二发光控制单元22。所述驱动单元10和所述发光控制单元用于驱动并控制发光单元L进行发光；所述补偿单元30用于补偿所述驱动单元10的控制端电压；所述输入单元40用于输入数据信号并通过所述驱动单元10驱动所述发光单元L进行发光；所述复位单元50用于对所述驱动单元的控制端电压进行复位，并对所述发光单元L的输入端电压进行复位；所述存储单元60用于对所述驱动单元10的控制端电压进行保存。
具体地，所述驱动单元10电性连接于第一电源输入端VDD与发光单元L之间，所述第一电源输入端VDD用于向该像素电路输入第一电源信号，所述驱动单元10驱动所述第一电源输入端VDD输入的第一电源信号传输至所述发光单元L，进而驱动所述发光单元L进行发光。
所述发光控制单元电性连接于所述第一电源输入端VDD与所述发光单元L之间，且与所述驱动单元10电性连接，所述发光控制单元还与控制信号输入端电性连接，且在所述控制信号输入端输入的控制信号作用下，控制所述第一电源输入端VDD与所述发光单元L之间的电性导通关系。所述发光控制单元与所述驱动单元10共同控制所述第一电源信号能否流向所述发光单元L，进而控制所述发光单元L的发光状态。例如，在所述发光控制单元和所述驱动单元10均开启时，所述驱动单元10将所述第一电源信号传输至所述发光单元L，实现发光单元L的发光；在所述发光控制单元关闭时，所述第一电源输入端VDD与所述发光单元L之间的通路被截断，发光单元L不发光。所述发光控制单元在所述控制信号输入端输出的信号作用下，实现其在开启和关闭两种状态之间转换。
进一步地，所述发光控制单元包括第一发光控制单元21和第二发光控制单元22，所述第一发光控制单元21电性连接于所述第一电源输入端VDD与所述驱动单元10之间，所述第二发光控制单元22电性连接于所述驱动单元10与所述发光单元L之间。因此，所述第一电源输入端VDD与所述驱动单元10之间的通路被所述第一发光控制单元21所控制，所述驱动单元10与所述发光单元L之间的通路被所述第二发光控制单元22所控制，从而实现第一发光控制单元21与第二发光控制单元22共同控制第一电源输入单VDD与发光单元L之间的电性导通关系。其中，第一发光控制单元21电性连接第一控制信号输入端EM1，且在所述第一控制信号输入端EM1输入的第一控制信号的作用下，实现其开启和关闭；第二发光控制单元22电性连接第二控制信号输入端EM2，且在所述第二控制信号输入端EM2输入的第二控制信号的作用下，实现其开启和关闭。
所述补偿单元30电性连接于所述驱动单元10与所述发光控制单元之间，具体地，所述补偿单元30与所述第二发光控制单元22直接电性连接，所述补偿单元30还与第二扫描信号输入端S2电性连接。所述第二扫描信号输入端S2向所述补偿单元提供第二扫描信号，并驱动所述补偿单元30对所述驱动单元10的控制端电压进行补偿。
进一步地，所述补偿单元30与所述控制信号输入端之间电性连接第一电容C1，具体地，所述第一电容C1电性连接于所述补偿单元30与所述第二控制信号输入端EM2之间，且对所述补偿单元30内产生的寄生电容进行耦合，以达到减小或消除寄生电容的作用。本实施例利用第一电容C1的耦合作用减小或消除了补偿单元30内的寄生电容，进而降低补偿单元30内部的寄生电压，有效缓解了补偿单元30向驱动单元10的漏电问题，有利于提高该像素电路的稳定性，并改善显示装置的显示品质。
所述输入单元40电性连接于数据信号输入端Da与所述驱动单元10之间，用于将数据信号传输至所述驱动单元10，以调控所述驱动单元10的驱动状态。所述输入单元40还与第一扫描信号输入端S1电性连接，第一扫描信号输入端S1提供的第一扫描信号控制所述输入单元40的开启或关闭。具体地，所述输入单元40的一端连接于所述第一发光控制单元21与所述驱动单元10之间。
所述复位单元50电性连接于复位信号输入端V与所述发光单元L之间，用于向所述发光单元L提供复位信号，所述复位单元50还与所述第二扫描信号输入端S2电性连接，所述第二扫描信号输入端S2提供的第二扫描信号控制所述复位单元50的开启或关闭。具体地，所述复位单元50的一端连接于所述发光单元L与所述第二发光控制单元22之间，且所述复位单元50通过所述第二发光控制单元22及所述补偿单元30电性连接至所述驱动单元10的控制端，以实现对所述驱动单元10的控制端的电压进行复位。
所述存储单元60电性连接于所述第一电源输入端VDD与所述驱动单元10之间，用于对所述驱动单元10的控制端电压进行存储。所述发光单元L的另一端与第二电源输入端VSS电性连接，所述第二电源输入端VSS向所述发光单元L提供第二电源信号。通常第一电源信号和第二电源信号均为电压信号，且第一电源信号的电压大于第二电源信号的电压。
进一步地，所述补偿单元30包括双栅晶体管，所述双栅晶体管包括第一沟道D1和第二沟道D2，所述第一电容C1的第一端电性连接至所述第一沟道D1与所述第二沟道D2之间，所述第一电容C1的第二端电性连接至所述第二控制信号输入端EM2，利用所述第一电容C1的耦合作用消除或减小所述双栅晶体管内的寄生电容。所述双栅晶体管的栅极电性连接至所述第二扫描信号输入端S2。
进一步地，所述双栅晶体管包括第一子晶体管T61和第二子晶体管T62，所述第一子晶体管T61包括所述第一沟道D1、以及设置于所述第一沟道D1相对两端的第一源极和第一漏极，所述第二子晶体管T62包括所述第二沟道D2、以及设置于所述第二沟道D2相对两端的第二源极和第二漏极，所述第一漏极与所述第二源极电性连接，所述第一电容C1的第一端与所述第一漏极电性连接或与所述第二源极电性连接。所述第一源极与所述驱动单元10电性连接，所述第二漏极与所述驱动单元10的控制端电性连接。所述第一子晶体管T61的栅极和所述第二子晶体管T62的栅极均电性连接所述第二扫描信号输入端S2。
进一步地，所述驱动单元10包括第一晶体管T1，所述第一发光控制单元21包括第二晶体管T2，所述第二发光控制单元22包括第三晶体管T3，所述第一晶体管T1的栅极、源极和漏极分别电性连接至所述双栅晶体管的漏极、所述第二晶体管T2的漏极、以及所述第三晶体管T3的源极，所述第二晶体管T2的栅极和源极分别电性连接所述第一控制信号输入端EM1和所述第一电源输入端VDD，所述第三晶体管T3的栅极和漏极分别电性连接所述第二控制信号输入端EM2和所述发光单元L。
所述输入单元40包括第四晶体管T4，所述第四晶体管T4的栅极、源极和漏极分别电性连接至第一扫描信号输入端S1、所述数据信号输入端Da和所述第一晶体管T1的源极。所述复位单元50包括第五晶体管T5，所述第五晶体管T5的栅极、源极和漏极分别电性连接至第二扫描信号输入端S2、所述复位信号输入端V和所述第三晶体管T3的漏极。所述存储单元60包括第二电容C2，所述第二电容C2的相对两端分别电性连接至所述第一电源输入端VDD和所述第一晶体管T1的栅极。
在本实施例中，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、以及所述双栅晶体管均为低温多晶硅晶体管。可以理解，本实施例提供的像素电路均采用低温多晶硅晶体管，由于低温多晶硅晶体管的材料成本低、制作工艺简单且成熟，因此本实施例可以降低产品成本，并提高产品良率和品质。
需要说明的是，本实施例中提及的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、以及双栅晶体管均为对称型晶体管，即各个晶体管的源极与漏极均可互换，而无需考虑电流流向与晶体管的源极和漏极之间的关系。
下面结合图2对本实施例提供的像素电路的工作原理进行阐述，该像素电路至少存在以下工作阶段。
在t1时间段，为初始化阶段。在该阶段，第二控制信号输入端EM2和第二扫描信号输入端S2均输入低电平信号，第五晶体管T5、第三晶体管T3和双栅晶体管开启，复位信号输入端V对第一晶体管T1的栅极电压进行初始化。
在t2时间段，为驱动单元充电阶段。在该阶段，第一扫描信号输入端S1和第二扫描信号输入端S2均输入低电平信号，第一控制信号输入端EM1和第二控制信号输入端EM2均输入高电平信号，第四晶体管T4、第五晶体管T5和双栅晶体管开启，第二晶体管T2和第三晶体管T3关闭，数据信号输入端Da输入的数据信号对第一晶体管T1的栅极进行充电，并存储至第二电容C2，同时复位信号输入端V对发光单元L的输入端进行复位。
在t3时间段，为第一电容C1耦合阶段。在该阶段的初始时刻，第一扫描信号输入端S1和第二扫描信号输入端S2转变为输入高电平信号，双栅晶体管关闭，第二控制信号输入端EM2输入高电平信号，在第一电容C1的耦合作用下，双栅晶体管的内部电位被耦合至较高值；在t3时间段的最后时刻，第二控制信号输入端EM2的输入信号由高电平转变为低电平，在第一电容C1的耦合作用下，双栅晶体管的内部电位被耦合至较低值，并小于第一晶体管T1的栅极电位，从而减弱或消除由所述双栅晶体管向第一晶体管T1的漏电流。
在t4时间段，为发光阶段。在该阶段，第一控制信号输入端EM1和第二控制信号输入端EM2均输入低电平信号，第二晶体管T2和第三晶体管T3开启，在第二电容C2存储的数据信号的作用下，第一晶体管T1驱动发光单元L进行发光。
在另一种实施例中，请参阅图3，图3是本申请实施例提供的第二种像素电路的结构原理图。可以理解，图3所示的像素电路与图1所示的像素电路具有相同或相似的特征，下面对图3所示的像素电路的特征进行阐述，其中未详述之处请参阅上述实施例的记载。
该像素电路包括驱动单元10、发光控制单元、补偿单元30、输入单元40、复位单元50、以及存储单元60，其中，所述发光控制单元可以包括第一发光控制单元21和第二发光控制单元22。
所述驱动单元10电性连接于第一电源输入端VDD与发光单元L之间，所述第一电源输入端VDD用于向该像素电路输入第一电源信号，所述驱动单元10驱动所述第一电源输入端VDD输入的第一电源信号传输至所述发光单元L，进而驱动所述发光单元L进行发光。
所述发光控制单元电性连接于所述第一电源输入端VDD与所述发光单元L之间，且与所述驱动单元10电性连接，所述发光控制单元还与控制信号输入端电性连接，且在所述控制信号输入端输入的控制信号作用下，控制所述第一电源输入端VDD与所述发光单元L之间的电性导通关系。所述发光控制单元包括第一发光控制单元21和第二发光控制单元22，所述第一发光控制单元21电性连接于所述第一电源输入端VDD与所述驱动单元10之间，所述第二发光控制单元22电性连接于所述驱动单元10与所述发光单元L之间。其中，第一发光控制单元21电性连接第一控制信号输入端EM1，且在所述第一控制信号输入端EM1输入的第一控制信号的作用下，实现其开启和关闭；第二发光控制单元22电性连接第二控制信号输入端EM2，且在所述第二控制信号输入端EM2输入的第二控制信号的作用下，实现其开启和关闭。
所述补偿单元30电性连接于所述驱动单元10与所述发光控制单元之间，具体地，所述补偿单元30与所述第二发光控制单元22直接电性连接，所述补偿单元30还与第二扫描信号输入端S2电性连接。所述第二扫描信号输入端S2向所述补偿单元提供第二扫描信号，并驱动所述补偿单元30对所述驱动单元10的控制端电压进行补偿。
所述补偿单元30与所述控制信号输入端之间电性连接第一电容C1，具体地，所述第一电容C1电性连接于所述补偿单元30与所述第一控制信号输入端EM1之间，用于对所述补偿单元30内产生的寄生电容进行耦合，以达到减小或消除寄生电容的作用，进而有效缓解补偿单元30向驱动单元10的漏电问题，有利于提高该像素电路的稳定性，并改善显示装置的显示品质。
所述输入单元40电性连接于数据信号输入端Da与所述驱动单元10之间，用于将数据信号传输至所述驱动单元10，以调控所述驱动单元10的驱动状态。所述输入单元40还与第一扫描信号输入端S1电性连接，第一扫描信号输入端S1提供的第一扫描信号控制所述输入单元40的开启或关闭。具体地，所述输入单元40的一端连接于所述第一发光控制单元21与所述驱动单元10之间。
所述复位单元50电性连接于复位信号输入端V与所述发光单元L之间，用于向所述发光单元L提供复位信号，所述复位单元50还与所述第二扫描信号输入端S2电性连接，所述第二扫描信号输入端S2提供的第二扫描信号控制所述复位单元50的开启或关闭。具体地，所述复位单元50的一端连接于所述发光单元L与所述第二发光控制单元22之间，且所述复位单元50通过所述第二发光控制单元22及所述补偿单元30电性连接至所述驱动单元10的控制端，以实现对所述驱动单元10的控制端的电压进行复位。
所述存储单元60电性连接于所述第一电源输入端VDD与所述驱动单元10之间，用于对所述驱动单元10的控制端电压进行存储。所述发光单元L的另一端与第二电源输入端VSS电性连接，所述第二电源输入端VSS向所述发光单元L提供第二电源信号。通常第一电源信号和第二电源信号均为电压信号，且第一电源信号的电压大于第二电源信号的电压。
进一步地，所述补偿单元30包括双栅晶体管，所述双栅晶体管包括第一沟道D1和第二沟道D2，所述第一电容C1的第一端电性连接至所述第一沟道D1与所述第二沟道D2之间，所述第一电容C1的第二端电性连接至所述第一控制信号输入端EM1，利用所述第一电容C1的耦合作用消除或减小所述双栅晶体管内的寄生电容。所述双栅晶体管的栅极电性连接至所述第二扫描信号输入端S2。
进一步地，所述双栅晶体管包括第一子晶体管T61和第二子晶体管T62，所述第一子晶体管T61包括所述第一沟道D1、以及设置于所述第一沟道D1相对两端的第一源极和第一漏极，所述第二子晶体管T62包括所述第二沟道D2、以及设置于所述第二沟道D2相对两端的第二源极和第二漏极，所述第一漏极与所述第二源极电性连接，所述第一电容C1的第一端与所述第一漏极电性连接或与所述第二源极电性连接。所述第一源极与所述驱动单元10电性连接，所述第二漏极与所述驱动单元10的控制端电性连接。所述第一子晶体管T61的栅极和所述第二子晶体管T62的栅极均电性连接所述第二扫描信号输入端S2。
进一步地，所述驱动单元10包括第一晶体管T1，所述第一发光控制单元21包括第二晶体管T2，所述第二发光控制单元22包括第三晶体管T3，所述第一晶体管T1的栅极、源极和漏极分别电性连接至所述双栅晶体管的漏极、所述第二晶体管T2的漏极、以及所述第三晶体管T3的源极，所述第二晶体管T2的栅极和源极分别电性连接所述第一控制信号输入端EM1和所述第一电源输入端VDD，所述第三晶体管T3的栅极和漏极分别电性连接所述第二控制信号输入端EM2和所述发光单元L。
所述输入单元40包括第四晶体管T4，所述第四晶体管T4的栅极、源极和漏极分别电性连接至第一扫描信号输入端S1、所述数据信号输入端Da和所述第一晶体管T1的源极。所述复位单元50包括第五晶体管T5，所述第五晶体管T5的栅极、源极和漏极分别电性连接至第二扫描信号输入端S2、所述复位信号输入端V和所述第三晶体管T3的漏极。所述存储单元60包括第二电容C2，所述第二电容C2的相对两端分别电性连接至所述第一电源输入端VDD和所述第一晶体管T1的栅极。
在本实施例中，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、以及所述双栅晶体管均为低温多晶硅晶体管。可以理解，本实施例提供的像素电路均采用低温多晶硅晶体管，由于低温多晶硅晶体管的材料成本低、制作工艺简单且成熟，因此本实施例可以降低产品成本，并提高产品良率和品质。
需要说明的是，本实施例中提及的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、以及双栅晶体管均为对称型晶体管，即各个晶体管的源极与漏极均可互换，而无需考虑电流流向与晶体管的源极和漏极之间的关系。
下面结合图4对本实施例提供的像素电路的工作原理进行阐述，该像素电路至少存在以下工作阶段。
在t1时间段，为初始化阶段。在该阶段，第二控制信号输入端EM2和第二扫描信号输入端S2均输入低电平信号，第五晶体管T5、第三晶体管T3和双栅晶体管开启，复位信号输入端V对第一晶体管T1的栅极电压进行初始化。
在t2时间段，为驱动单元充电阶段。在该阶段，第一扫描信号输入端S1和第二扫描信号输入端S2均输入低电平信号，第一控制信号输入端EM1和第二控制信号输入端EM2均输入高电平信号，第四晶体管T4、第五晶体管T5和双栅晶体管开启，第二晶体管T2和第三晶体管T3关闭，数据信号输入端Da输入的数据信号对第一晶体管T1的栅极进行充电，并存储至第二电容C2，同时复位信号输入端V对发光单元L的输入端进行复位。
在t3时间段，为第一电容C1耦合阶段。在该阶段的初始时刻，第一扫描信号输入端S1和第二扫描信号输入端S2转变为输入高电平信号，双栅晶体管关闭，第一控制信号输入端EM1输入高电平信号，在第一电容C1的耦合作用下，双栅晶体管的内部电位被耦合至较高值；在t3时间段的最后时刻，第一控制信号输入端EM1的输入信号由高电平转变为低电平，在第一电容C1的耦合作用下，双栅晶体管的内部电位被耦合至较低值，并小于第一晶体管T1的栅极电位，从而减弱或消除由所述双栅晶体管向第一晶体管T1的漏电流。
在t4时间段，为发光阶段。在该阶段，第一控制信号输入端EM1和第二控制信号输入端EM2均输入低电平信号，第二晶体管T2和第三晶体管T3开启，在第二电容C2存储的数据信号的作用下，第一晶体管T1驱动发光单元L进行发光。
综上所述，本申请实施例提供的像素电路包括驱动单元、发光控制单元和补偿单元，所述驱动单元和所述发光控制单元均电性连接于第一电源输入端与发光单元之间且二者电性连接，所述发光控制单元电性连接控制信号输入端，所述补偿单元电性连接于所述驱动单元与所述发光控制单元之间且与所述控制信号输入端之间电性连接第一电容，通过在补偿单元与控制信号输入端之间电性连接第一电容，利用第一电容耦合作用减小或消除补偿单元内的寄生电容，进而降低补偿单元内部的寄生电压，有效缓解补偿单元向驱动单元的漏电问题，提高了该像素电路的稳定性。
本申请实施例还提供一种显示装置，所述显示装置包括上述任一实施例所述像素电路。可以理解，所述显示装置因包含上述像素电路而表现出较好的显示品质，并且相较于现有技术，所述显示装置的内部电路的漏电流和因漏电流而导致的显示问题得到显著改善。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素电路，其包括：
    驱动单元，电性连接于第一电源输入端与发光单元之间；
    发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
    补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，且所述补偿单元与所述控制信号输入端之间电性连接第一电容。
  2. 根据权利要求1所述的像素电路，其中，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间。
  3. 根据权利要求2所述的像素电路，其中，所述双栅晶体管包括第一子晶体管和第二子晶体管；
    所述第一子晶体管包括所述第一沟道、以及设置于所述第一沟道相对两端的第一源极和第一漏极，所述第一源极电性连接于所述驱动单元与所述发光控制单元之间；
    所述第二子晶体管包括所述第二沟道、以及设置于所述第二沟道相对两端的第二源极和第二漏极，所述第二漏极与所述驱动单元电性连接；
    所述第一漏极与所述第二源极电性连接，所述第一电容的第一端与所述第一漏极电性连接。
  4. 根据权利要求3所述的像素电路，其中，所述第一电容的第一端与所述第二源极电性连接。
  5. 根据权利要求4所述的像素电路，其中，所述发光控制单元包括第一发光控制单元和第二发光控制单元，所述控制信号输入端包括与所述第一发光控制单元电性连接的第一控制信号输入端和与所述第二发光控制单元电性连接的第二控制信号输入端。
  6. 根据权利要求5所述的像素电路，其中，所述第一发光控制单元电性连接于所述第一电源输入端与所述驱动单元之间，所述第二发光控制单元电性连接于所述驱动单元与所述发光单元之间。
  7. 根据权利要求6所述的像素电路，其中，所述第一电容的第二端与所述第一控制信号输入端电性连接。
  8. 根据权利要求6所述的像素电路，其中，所述第一电容的第二端与所述第二控制信号输入端电性连接。
  9. 根据权利要求6所述的像素电路，其中，所述像素电路还包括：
    复位单元，电性连接于复位信号输入端与所述发光单元之间；
    输入单元，电性连接于数据信号输入端与所述驱动单元之间；
    存储单元，电性连接于所述第一电源输入端与所述驱动单元之间。
  10. 根据权利要求9所述的像素电路，其中，
    所述驱动单元包括第一晶体管，所述第一晶体管的栅极电性连接所述双栅晶体管的漏极。
  11. 根据权利要求10所述的像素电路，其中，所述第一发光控制单元包括第二晶体管，所述第二发光控制单元包括第三晶体管，所述第一晶体管的栅极、源极和漏极分别电性连接至所述双栅晶体管的漏极、所述第二晶体管的漏极、以及所述第三晶体管的源极，所述第二晶体管的栅极、源极和漏极分别电性连接所述第一控制信号输入端、所述第一电源输入端和所述第一晶体管的源极，所述第三晶体管的栅极、源极和漏极分别电性连接所述第二控制信号输入端、所述第一晶体管的漏极和所述发光单元。
  12. 根据权利要求11所述的像素电路，其中，所述输入单元包括第四晶体管，所述第四晶体管的栅极、源极和漏极分别电性连接至第一扫描信号输入端、所述数据信号输入端和所述第一晶体管的源极。
  13. 根据权利要求12所述的像素电路，其中，所述复位单元包括第五晶体管，所述第五晶体管的栅极、源极和漏极分别电性连接至第二扫描信号输入端、所述复位信号输入端和所述第三晶体管的漏极。
  14. 根据权利要求13所述的像素电路，其中，所述存储单元包括第二电容，所述第二电容的相对两端分别电性连接至所述第一电源输入端和所述第一晶体管的栅极。
  15. 根据权利要求14所述的像素电路，其中，所述双栅晶体管的栅极电性连接至所述第二扫描信号输入端。
  16. 根据权利要求15所述的像素电路，其中，所述双栅晶体管为低温多晶硅晶体管。
  17. 根据权利要求16所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为低温多晶硅晶体管。
  18. 一种显示装置，其包括像素电路，所述像素电路包括：
    驱动单元，电性连接于第一电源输入端与发光单元之间；
    发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
    补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，且所述补偿单元与所述控制信号输入端之间电性连接第一电容。
  19. 根据权利要求18所述的显示装置，其中，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间，所述第一电容的第二端电性连接所述控制信号输入端。
  20. 一种像素电路，其包括：
    驱动单元，电性连接于第一电源输入端与发光单元之间；
    发光控制单元，电性连接于所述第一电源输入端与所述发光单元之间，且与所述驱动单元电性连接，所述发光控制单元与控制信号输入端电性连接；
    补偿单元，电性连接于所述驱动单元与所述发光控制单元之间，所述补偿单元包括双栅晶体管，所述双栅晶体管包括第一沟道和第二沟道；以及
    第一电容，电性连接于所述补偿单元与所述控制信号输入端之间，所述第一电容的第一端电性连接至所述第一沟道与所述第二沟道之间，所述第一电容的第二端电性连接所述控制信号输入端。
PCT/CN2021/136813 2021-12-03 2021-12-09 像素电路及显示装置 WO2023097741A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/622,778 US20240038160A1 (en) 2021-12-03 2021-12-09 Pixel circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111464063.9 2021-12-03
CN202111464063.9A CN114067720A (zh) 2021-12-03 2021-12-03 像素电路及显示装置

Publications (1)

Publication Number Publication Date
WO2023097741A1 true WO2023097741A1 (zh) 2023-06-08

Family

ID=80229095

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/136813 WO2023097741A1 (zh) 2021-12-03 2021-12-09 像素电路及显示装置

Country Status (3)

Country Link
US (1) US20240038160A1 (zh)
CN (1) CN114067720A (zh)
WO (1) WO2023097741A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114822400B (zh) 2022-06-28 2022-10-25 惠科股份有限公司 像素驱动电路、显示面板及显示装置
CN115148143B (zh) * 2022-07-20 2023-09-05 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120074422A (ko) * 2010-12-28 2012-07-06 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN106531075A (zh) * 2017-01-10 2017-03-22 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN111508435A (zh) * 2020-04-29 2020-08-07 昆山国显光电有限公司 像素驱动电路、显示面板及终端设备
CN112489600A (zh) * 2020-12-15 2021-03-12 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN113314073A (zh) * 2021-05-17 2021-08-27 上海天马微电子有限公司 显示面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102930824B (zh) * 2012-11-13 2015-04-15 京东方科技集团股份有限公司 像素电路及驱动方法、显示装置
CN107945743A (zh) * 2018-01-04 2018-04-20 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置
CN110176213B (zh) * 2018-06-08 2023-09-26 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN110264946A (zh) * 2019-05-21 2019-09-20 合肥维信诺科技有限公司 一种像素电路和显示装置
CN111179820A (zh) * 2020-03-12 2020-05-19 武汉华星光电半导体显示技术有限公司 一种像素电路及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120074422A (ko) * 2010-12-28 2012-07-06 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN106531075A (zh) * 2017-01-10 2017-03-22 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN111508435A (zh) * 2020-04-29 2020-08-07 昆山国显光电有限公司 像素驱动电路、显示面板及终端设备
CN112489600A (zh) * 2020-12-15 2021-03-12 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN113314073A (zh) * 2021-05-17 2021-08-27 上海天马微电子有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN114067720A (zh) 2022-02-18
US20240038160A1 (en) 2024-02-01

Similar Documents

Publication Publication Date Title
US11436978B2 (en) Pixel circuit and display device
US11232734B2 (en) Shift register unit, driving method, gate driving circuit and display device
WO2023097741A1 (zh) 像素电路及显示装置
WO2022011777A1 (zh) 像素电路及显示装置
CN104318883A (zh) 移位寄存器及其单元、显示器和阈值电压补偿电路
CN107564474A (zh) 一种触控面板及触摸屏
US10192474B2 (en) Controllable voltage source, shift register and unit thereof, and display
WO2021046999A1 (zh) 一种oled像素补偿电路及像素补偿方法
WO2023108734A1 (zh) 显示面板
WO2023236289A1 (zh) 像素电路及显示面板
WO2024000789A1 (zh) 扫描驱动电路和显示面板
WO2021012430A1 (zh) 像素驱动电路及显示面板
WO2023103038A1 (zh) 像素电路及显示面板
CN109616041A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN111243543A (zh) Goa电路、tft基板、显示装置及电子设备
WO2024109060A1 (zh) 像素电路及显示面板
WO2020177258A1 (zh) 像素驱动电路及显示面板
CN111210766B (zh) 反相器及其驱动方法、栅极驱动电路、显示装置
WO2023216823A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2024045484A1 (zh) 像素电路及其驱动方法和显示面板
WO2020252913A1 (zh) 像素驱动电路及显示面板
CN114005396B (zh) 像素电路和显示面板
CN214012479U (zh) 一种提升显示品质的栅极电路
CN213958558U (zh) 一种gip电路
WO2019015236A1 (zh) 静电放电电路和显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17622778

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21966166

Country of ref document: EP

Kind code of ref document: A1