WO2023095893A1 - 光検出装置及び電子機器 - Google Patents

光検出装置及び電子機器 Download PDF

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WO2023095893A1
WO2023095893A1 PCT/JP2022/043620 JP2022043620W WO2023095893A1 WO 2023095893 A1 WO2023095893 A1 WO 2023095893A1 JP 2022043620 W JP2022043620 W JP 2022043620W WO 2023095893 A1 WO2023095893 A1 WO 2023095893A1
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Prior art keywords
region
semiconductor layer
photoelectric conversion
light
light shielding
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English (en)
French (fr)
Japanese (ja)
Inventor
恭平 水田
芳樹 蛯子
康史 三好
建治 竹尾
時久 金口
保久登 三木
佳紀 白数
正真 塩山
利彦 林
尚之 佐藤
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to US18/711,240 priority Critical patent/US20250006764A1/en
Priority to JP2023563765A priority patent/JPWO2023095893A1/ja
Priority to CN202280069098.9A priority patent/CN118103983A/zh
Priority to DE112022005653.3T priority patent/DE112022005653T5/de
Priority to KR1020247015183A priority patent/KR20240108393A/ko
Publication of WO2023095893A1 publication Critical patent/WO2023095893A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8033—Photosensitive area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H10F39/8057—Optical shielding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/806—Optical elements or arrangements associated with the image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/806—Optical elements or arrangements associated with the image sensors
    • H10F39/8067—Reflectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present technology (technology according to the present disclosure) relates to a photodetector and an electronic device, and more particularly, a photodetector having a photoelectric conversion region partitioned by a separation region extending in the thickness direction of a semiconductor layer and an electronic device including the photodetector. It relates to technology that is effective when applied to equipment.
  • Photodetection devices such as solid-state imaging devices and distance measuring devices divide the semiconductor layer into separate regions.
  • Japanese Unexamined Patent Application Publication No. 2002-100002 discloses a buried isolation region in which a recessed portion of a semiconductor layer is charged with conductive polysilicon through an insulating film as an isolation region that partitions a photoelectric conversion region of a semiconductor layer.
  • the width of the isolation region tends to be miniaturized as the photoelectric conversion region is miniaturized.
  • the width of the separation region is too narrow (too small)
  • the light incident on the photoelectric conversion region is not totally reflected by the separation region and is transmitted to the adjacent photoelectric conversion region, resulting in a decrease (deterioration) in quantum efficiency (QE) as a pixel characteristic.
  • QE quantum efficiency
  • the isolation region filled with polysilicon having a high light absorption rate the light is absorbed by the polysilicon, and the quantum efficiency QE is lowered.
  • silicon (Si) in the semiconductor layer has a low optical absorption coefficient for near-infrared light, its quantum efficiency is low. Therefore, when dealing with near-infrared light, in order to improve the quantum efficiency QE, the thickness of the semiconductor layer is increased, or a diffraction/scattering portion is provided on the light incident surface side of the semiconductor layer. Consideration is being given to extending the optical path length within. However, when the semiconductor layer is thickened, there is a problem in transferring signal charges from the photoelectric conversion portion to the charge holding portion in the photoelectric conversion cell. This signal charge transfer affects pixel characteristics.
  • the purpose of this technology is to provide a technology capable of improving pixel characteristics.
  • a photodetector comprising a semiconductor layer and first and second isolation regions provided in the semiconductor layer, the first isolation region includes an insulating material filled in the first recess extending in the thickness direction of the semiconductor layer and having a lower refractive index than the semiconductor layer;
  • the second isolation region includes a conductive material filled in a second dug portion extending in the thickness direction of the semiconductor layer.
  • a photodetector according to another aspect of the present technology, a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second isolation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region; a charge holding portion provided on the first surface side of the semiconductor layer in the second region; a light shield provided on the second surface side of the semiconductor layer and overlapping the second region in plan view; It has (3) A photodetector according to another aspect of the present technology, a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region
  • a photodetector a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; A second recess extending in a thickness direction of the semiconductor layer includes a conductive material provided through an insulator having a lower refractive index than that of the semiconductor layer, and the photoelectric conversion region extends in one direction as a first region.
  • the thickness of the insulator on the first region side of the conductive material is thicker than the thickness of the insulator on the second region side of the conductive material.
  • a photodetector according to another aspect of the present technology, a semiconductor layer having first and second surfaces opposite to each other; a photoelectric conversion region provided in the semiconductor layer so as to be partitioned by a first separation region; a second separation region for separating each photoelectric conversion region of the photoelectric conversion region into a first region and a second region arranged in one direction; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding portion provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion portion; with the first isolation region is provided in a first recess extending in the thickness direction of the semiconductor layer and includes an insulating material having a lower refractive index than the semiconductor layer; the second isolation region includes a conductive material provided in a second recess extending in the thickness direction of the semiconductor layer via an isolation insulating film having a lower refractive index than the semiconductor layer; Of the incident light incident on the first region from the second surface side of the semiconductor layer
  • a photodetector according to another aspect of the present technology, a semiconductor layer having first and second surfaces opposite to each other; a plurality of photoelectric conversion regions provided in the semiconductor layer so as to be partitioned by first isolation regions; a second separation region for separating each photoelectric conversion region of the plurality of photoelectric conversion regions into a first region and a second region arranged in one direction; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding portion provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion portion; with the first isolation region is provided in a first recess extending in the thickness direction of the semiconductor layer and includes an insulating material having a lower refractive index than the semiconductor layer; the second isolation region includes a conductive
  • a photodetector a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second isolation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region and configured to photoelectrically convert light incident from the second surface side of the semiconductor layer into signal charges; a charge holding portion provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion portion; a dielectric in which an insulating film is provided via a fixed charge film in a third dug portion extending in the depth direction of the semiconductor layer; A photodetector, comprising a dielectric in which an insul
  • a photodetector according to another aspect of the present technology, a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second isolation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding portion provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion portion; a multilayer body provided on the first surface side of the semiconductor layer; with The multilayer body includes a light absorber provided so as to overlap with the first region and having a higher light absorption rate than the semiconductor layer
  • An electronic device includes the photodetector, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and output from the photodetector. and a signal processing circuit for performing signal processing on the received signal.
  • FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology
  • FIG. 1 is an equivalent circuit diagram showing one configuration example of a pixel of a solid-state imaging device according to a first embodiment of the present technology
  • FIG. 3 is a plan view schematically showing a planar pattern of separation regions in a pixel array section of the solid-state imaging device according to the first embodiment of the present technology
  • FIG. 5 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure taken along line a4-a4 of FIG. 4;
  • FIG. 6 is a longitudinal sectional view enlarging a part of FIG. 5 ; It is an equivalent circuit diagram showing a configuration example of a pixel included in a pixel array unit of a solid-state imaging device according to a second embodiment of the present technology. It is an equivalent circuit diagram showing a configuration example of a pixel included in a pixel array unit of a solid-state imaging device according to a second embodiment of the present technology.
  • FIG. 7 is a plan view showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to a second embodiment of the present technology;
  • FIG. 9 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a8-a8 of FIG. 8; FIG.
  • FIG. 10 is a plan view showing a planar pattern of separation regions in a pixel array section of a solid-state imaging device according to a third embodiment of the present technology
  • FIG. 10 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a10-a10 of FIG. 9
  • FIG. 11 is a plan view showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to a fourth embodiment of the present technology
  • FIG. 13 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a12-a12 of FIG. 12
  • It is an equivalent circuit diagram showing a configuration example of a pixel of a solid-state imaging device according to a fifth embodiment of the present technology.
  • FIG. 10 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a10-a10 of FIG. 9
  • FIG. 11 is a plan view showing a plane pattern of separation regions in a
  • FIG. 11 is an equivalent circuit diagram showing one configuration example of a pixel of a solid-state imaging device according to a sixth embodiment of the present technology
  • FIG. 20 is an equivalent circuit diagram showing one configuration example of a pixel of a solid-state imaging device according to a seventh embodiment of the present technology
  • FIG. 21 is a plan view schematically showing a planar pattern of a light shielding body in a pixel array section of a solid-state imaging device according to an eighth embodiment of the present technology
  • FIG. 18 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a17-a17 of FIG. 17
  • 19 is an enlarged plan view of a part of FIG. 18;
  • FIG. 20 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a19-a19 of FIG. 19; It is a figure which shows the dimension of the 2nd light-shielding part of a light-shielding body. It is a figure which shows typically the light reflection state in the 2nd light-shielding part of a light-shielding body.
  • FIG. 21 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to an eighth embodiment of the present technology;
  • FIG. 22B is a longitudinal sectional view schematically showing a step subsequent to FIG. 22A;
  • FIG. 22B is a longitudinal sectional view schematically showing a step subsequent to FIG. 22B;
  • FIG. 22C is a longitudinal sectional view schematically showing a step subsequent to FIG. 22C
  • FIG. 22D is a longitudinal sectional view schematically showing a step subsequent to FIG. 22D
  • FIG. 22E is a longitudinal sectional view schematically showing a step subsequent to FIG. 22E
  • FIG. 22F is a longitudinal sectional view schematically showing a step subsequent to FIG. 22F
  • FIG. 22G is a longitudinal sectional view schematically showing a step subsequent to FIG. 22G
  • FIG. 22H is a longitudinal sectional view schematically showing a step subsequent to FIG. 22H
  • FIG. 20 is a plan view schematically showing a modified example 8-1 of the eighth embodiment
  • FIG. 21 is a plan view schematically showing a modified example 8-2 of the eighth embodiment
  • FIG. 20 is a plan view schematically showing a modified example 8-1 of the eighth embodiment
  • FIG. 21 is a plan view schematically showing a modified example 8-2 of the eighth embodiment
  • FIG. 21 is a plan view schematically showing a modified example 8-3 of the eighth embodiment
  • FIG. 21 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of Modification 8-4 of the eighth embodiment
  • FIG. 20 is a plan view schematically showing a plane pattern of a light shield in a pixel array section of a solid-state imaging device according to a ninth embodiment of the present technology
  • FIG. 28 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a27-a27 of FIG. 27;
  • FIG. 4 is a diagram showing dimensions of a second light shielding portion of a light shielding body and an intra-pixel isolation region; It is a figure which shows typically the light reflection state in the 2nd light-shielding part of a light-shielding body.
  • FIG. 20 is a vertical cross-sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a ninth embodiment of the present technology;
  • FIG. 30B is a longitudinal sectional view schematically showing a step subsequent to FIG. 30A;
  • FIG. 30B is a longitudinal sectional view schematically showing a step subsequent to FIG. 30B;
  • FIG. 30C is a longitudinal sectional view schematically showing a step subsequent to FIG. 30C;
  • FIG. 30D is a longitudinal sectional view schematically showing a step subsequent to FIG. 30D
  • FIG. 30E is a longitudinal sectional view schematically showing a step subsequent to FIG. 30E
  • FIG. 30F is a longitudinal sectional view schematically showing a step subsequent to FIG. 30F
  • FIG. 30G is a longitudinal sectional view schematically showing a step subsequent to FIG. 30G
  • FIG. 21 is a plan view schematically showing a planar pattern of a light shielding body in a pixel array section of a solid-state imaging device according to a tenth embodiment of the present technology
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a31-a31 of FIG.
  • FIG. 20 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a tenth embodiment of the present technology
  • FIG. 34B is a longitudinal sectional view schematically showing a step subsequent to FIG. 34A
  • FIG. 34B is a vertical cross-sectional view schematically showing a step subsequent to FIG. 34B
  • FIG. 34C is a longitudinal sectional view schematically showing a step subsequent to FIG. 34C
  • FIG. 34D is a longitudinal sectional view schematically showing a step subsequent to FIG. 34D
  • FIG. 20 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a tenth embodiment of the present technology
  • FIG. 34B is a longitudinal sectional view schematically showing a step subsequent to FIG. 34A
  • FIG. 34B is a vertical cross-sectional view schematically showing a step subsequent to FIG. 34B
  • FIG. 34C is a longitudinal sectional view schematically showing a step subsequent
  • FIG. 21 is a plan view schematically showing a plane pattern of a light shielding body in a pixel array section of a solid-state imaging device according to an eleventh embodiment of the present technology
  • FIG. 36 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a35-a35 of FIG. 35
  • FIG. 4 is a diagram showing dimensions of a light reflector and an intra-pixel isolation region
  • FIG. 4 is a diagram schematically showing a light reflection state on a light reflector
  • FIG. 4 is a diagram showing the correlation between the length of a light reflector in the Z direction and the transmittance;
  • FIG. 21 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to an eleventh embodiment of the present technology
  • FIG. 38B is a longitudinal sectional view schematically showing a step subsequent to FIG. 38A
  • FIG. 38B is a longitudinal sectional view schematically showing a step subsequent to FIG. 38B
  • FIG. 38C is a longitudinal sectional view schematically showing a step subsequent to FIG. 38C
  • FIG. 38D is a longitudinal sectional view schematically showing a step subsequent to FIG. 38D
  • FIG. 38E is a longitudinal sectional view schematically showing a step subsequent to FIG. 38E
  • FIG. 20 is a longitudinal sectional view schematically showing a modified example 11-1 of the eleventh embodiment
  • FIG. 22 is a plan view schematically showing a modified example 11-2 of the eleventh embodiment
  • FIG. 41 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a40-a40 of FIG. 40
  • FIG. 22 is a longitudinal sectional view schematically showing a modified example 11-3 of the eleventh embodiment
  • FIG. 22 is a longitudinal sectional view schematically showing a modified example 11-4 of the eleventh embodiment
  • FIG. 20 is a plan view schematically showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to a twelfth embodiment of the present technology
  • FIG. 45 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a44-a44 of FIG.
  • FIG. 44 19 is an enlarged plan view of a part of FIG. 18;
  • FIG. 19 is an enlarged plan view of a part of FIG. 18;
  • FIG. FIG. 22A is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a twelfth embodiment of the present technology;
  • FIG. 47B is a longitudinal sectional view schematically showing a step subsequent to FIG. 47A;
  • FIG. 47B is a longitudinal sectional view schematically showing a step subsequent to FIG. 47B;
  • FIG. 47C is a longitudinal sectional view schematically showing a step subsequent to FIG. 47C;
  • FIG. 47D is a longitudinal sectional view schematically showing a step subsequent to FIG. 47D;
  • FIG. 47E is a longitudinal sectional view schematically showing a step subsequent to FIG. 47E;
  • FIG. 47F is a longitudinal sectional view schematically showing a step subsequent to FIG. 47F;
  • FIG. 47G is a longitudinal sectional view schematically showing a step subsequent to FIG. 47G;
  • FIG. 12 is a vertical cross-sectional view schematically showing an incident optical path of oblique light in Comparative Example 12-1.
  • FIG. 20 is a longitudinal sectional view schematically showing an incident optical path of oblique light in the twelfth embodiment;
  • FIG. 12 is a vertical cross-sectional view showing a case where a first dug portion and a third dug portion are formed in the same step in Comparative Example 12-2;
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of Modification 12-1 of the twelfth embodiment;
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of Modification 12-2 of the twelfth embodiment;
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of Modification 12-3 of the twelfth embodiment;
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of Modification 12-4 of the twelfth embodiment;
  • FIG. 20 is a plan view schematically showing a planar pattern of separation regions in a pixel array section of a solid-state imaging device according to a thirteenth embodiment of the present technology
  • FIG. 56 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a55-a55 of FIG. 55
  • FIG. 57 is a longitudinal sectional view enlarging a part of FIG. 56
  • It is a figure which shows the correlation between the film thickness of an insulator, and an average reflectance.
  • FIG. 22 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a thirteenth embodiment of the present technology
  • FIG. 59B is a longitudinal sectional view schematically showing a step subsequent to FIG.
  • FIG. 59A is a longitudinal sectional view schematically showing a step subsequent to FIG. 59B
  • FIG. 59C is a longitudinal sectional view schematically showing a step subsequent to FIG. 59C
  • FIG. 59D is a vertical cross-sectional view schematically showing a step subsequent to FIG. 59D
  • FIG. 59E is a longitudinal sectional view schematically showing a step subsequent to FIG. 59E
  • FIG. 59F is a longitudinal sectional view schematically showing a step subsequent to FIG. 59F
  • FIG. 59G is a longitudinal sectional view schematically showing a step subsequent to FIG. 59G
  • FIG. 59H is a longitudinal sectional view schematically showing a step subsequent to FIG. 59H
  • FIG. 59H is a longitudinal sectional view schematically showing a step subsequent to FIG. 59H
  • FIG. 59H is a longitudinal sectional view schematically showing a step subsequent to FIG. 59H
  • FIG. 59H is a longitudinal
  • FIG. 59I is a longitudinal sectional view schematically showing a step subsequent to FIG. 59I.
  • FIG. 32 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a modification of the thirteenth embodiment
  • FIG. 20 is a plan view schematically showing a planar pattern of separation regions in a pixel array section of a solid-state imaging device according to a fourteenth embodiment of the present technology
  • FIG. 62 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a61-a61 of FIG. 61
  • FIG. 63 is a longitudinal cross-sectional view in which a part of FIG. 62 is enlarged and turned upside down;
  • FIG. 5 is a diagram schematically showing interference between reflected light reflected by an intra-pixel isolation region and return light reflected by an inter-pixel isolation region
  • FIG. 10 is a diagram showing the correlation between the width of the second region of the photoelectric conversion region and the light reflectance on the sidewall of the intra-pixel isolation region
  • FIG. 20 is a plan view schematically showing a planar pattern of separation regions in a pixel array section of a solid-state imaging device according to a fifteenth embodiment of the present technology
  • FIG. 67 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a66-a66 of FIG. 66;
  • FIG. 67 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line b66-b66 of FIG. 66;
  • FIG. 3 is a plan view schematically showing a plane pattern of a light shielding film;
  • FIG. 10 is a diagram showing the correlation between the width of the second region of the photoelectric conversion region and the light reflectance on the sidewall of the intra-pixel isolation region;
  • FIG. 20 is a plan view schematically showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to a sixteenth embodiment of the present technology;
  • FIG. 72 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a71-a71 of FIG. 71;
  • FIG. 72 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line b71-b71 of FIG. 71;
  • FIG. 20A is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a sixteenth embodiment of the present technology;
  • FIG. 74B is a longitudinal sectional view schematically showing a step subsequent to FIG. 74A;
  • FIG. 74B is a longitudinal sectional view schematically showing a step subsequent to FIG. 74B;
  • FIG. 74C is a longitudinal sectional view schematically showing a step subsequent to FIG. 74C;
  • FIG. 74D is a longitudinal sectional view schematically showing a step subsequent to FIG. 74D;
  • FIG. 74E is a longitudinal sectional view schematically showing a step subsequent to FIG. 74E;
  • FIG. 74F is a longitudinal sectional view schematically showing a step subsequent to FIG. 74F;
  • FIG. 32 is a plan view schematically showing a modification of the sixteenth embodiment;
  • FIG. 20 is a plan view schematically showing a planar pattern of separation regions in a pixel array section of a solid-state imaging device according to a seventeenth embodiment of the present technology;
  • FIG. 77 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a76-a76 of FIG. 76;
  • FIG. 77 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line b76-b76 of FIG.
  • FIG. 20 is a plan view schematically showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to an eighteenth embodiment of the present technology
  • FIG. 80 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a79-a79 of FIG. 79
  • FIG. 20 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a nineteenth embodiment of the present technology
  • FIG. 20 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twentieth embodiment of the present technology
  • FIG. 83 is a plan view schematically showing a planar pattern of the light reflector of FIG. 82;
  • FIG. 4 is a longitudinal sectional view schematically showing light reflection by a light reflector;
  • FIG. 20 is a longitudinal sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a twentieth embodiment of the present technology;
  • FIG. 84B is a longitudinal sectional view schematically showing a step subsequent to FIG. 84A;
  • FIG. 84B is a vertical cross-sectional view schematically showing a step subsequent to FIG. 84B;
  • FIG. 84C is a vertical cross-sectional view schematically showing a step subsequent to FIG. 84C;
  • FIG. 84D is a vertical cross-sectional view schematically showing a step subsequent to FIG.
  • FIG. 84D is a longitudinal sectional view schematically showing a step subsequent to FIG. 84E;
  • FIG. 84F is a longitudinal sectional view schematically showing a step subsequent to FIG. 84F;
  • FIG. 84G is a longitudinal sectional view schematically showing a step subsequent to FIG. 84G;
  • FIG. 84H is a longitudinal sectional view schematically showing a step subsequent to FIG. 84H;
  • FIG. 84I is a vertical cross-sectional view schematically showing a step subsequent to FIG. 84I.
  • FIG. 21 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twenty-first embodiment of the present technology;
  • FIG. 21 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twenty-first embodiment of the present technology;
  • FIG. 21 is a vertical cross-sectional view schematically showing a vertical cross-
  • FIG. 86 is a plan view schematically showing a planar pattern of the light absorber of FIG. 85;
  • FIG. 21 is a vertical cross-sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a twenty-first embodiment of the present technology;
  • FIG. 87B is a longitudinal sectional view schematically showing a step subsequent to FIG. 87A;
  • FIG. 87B is a longitudinal sectional view schematically showing a step subsequent to FIG. 87B;
  • FIG. 87C is a longitudinal sectional view schematically showing a step subsequent to FIG. 87C;
  • FIG. 87D is a longitudinal sectional view schematically showing a step subsequent to FIG. 87D;
  • FIG. 87E is a longitudinal sectional view schematically showing a step subsequent to FIG. 87E
  • FIG. 87F is a longitudinal sectional view schematically showing a step subsequent to FIG. 87F
  • FIG. 87G is a longitudinal sectional view schematically showing a step subsequent to FIG. 87G
  • FIG. 87H is a longitudinal sectional view schematically showing a step subsequent to FIG. 87H
  • FIG. 20 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twenty-second embodiment of the present technology
  • FIG. 89 is a plan view schematically showing a planar pattern of the light reflector of FIG. 88;
  • FIG. 89 is a plan view schematically showing a planar pattern of the light reflector of FIG. 88;
  • FIG. 22 is a vertical cross-sectional view schematically showing steps of a method for manufacturing a solid-state imaging device according to a twenty-second embodiment of the present technology
  • FIG. 90B is a longitudinal sectional view schematically showing a step subsequent to FIG. 90A
  • FIG. 90B is a longitudinal sectional view schematically showing a step subsequent to FIG. 90B
  • FIG. 90C is a longitudinal sectional view schematically showing a step subsequent to FIG. 90C
  • FIG. 90D is a longitudinal sectional view schematically showing a step subsequent to FIG. 90D
  • FIG. 90E is a longitudinal sectional view schematically showing a step subsequent to FIG. 90E
  • FIG. 90F is a longitudinal sectional view schematically showing a step subsequent to FIG. 90F
  • FIG. 90G is a longitudinal sectional view schematically showing a step subsequent to FIG. 90G.
  • FIG. 23 is a diagram illustrating a configuration example of an electronic device according to a twenty-third embodiment of the present technology
  • the first conductivity type is the p-type and the second conductivity type is the n-type as the conductivity type of the semiconductor
  • the first conductivity type may be n-type
  • the second conductivity type may be p-type.
  • the first direction and the second direction which are orthogonal to each other in the same plane, are the X direction and the Y direction, respectively.
  • a third direction orthogonal to each of the second directions is the Z direction.
  • the thickness direction of the semiconductor layer 20, which will be described later will be described as the Z direction.
  • CMOS complementary metal oxide semiconductor
  • isolation regions for partitioning the semiconductor layer an inter-pixel isolation region corresponding to a specific example of the “first isolation region” of the present technology and a “second isolation region” of the present technology.
  • An example including an intra-pixel isolation region corresponding to one specific example will be described.
  • a solid-state imaging device 1A mainly includes a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed from above. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A.
  • this solid-state imaging device 1A (301) takes in image light (incident light 306) from an object through an optical lens 302, and measures the light quantity of the incident light 306 formed on the imaging surface. Each pixel is converted into an electric signal and output as a pixel signal.
  • a semiconductor chip 2 on which a solid-state imaging device 1A is mounted has a square-shaped pixel array section 2A provided in the center in a two-dimensional plane including X and Y directions orthogonal to each other, A peripheral portion 2B is provided outside the pixel array portion 2A so as to surround the pixel array portion 2A.
  • the semiconductor chip 2 is formed by dividing a plurality of chip forming regions formed on a semiconductor wafer into small pieces for each chip forming region. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same even in a wafer state before the semiconductor wafer is cut into small pieces.
  • the pixel array section 2A is a light receiving surface that receives light condensed by an optical lens (optical system) 302 shown in FIG. 91, for example.
  • a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction.
  • the pixels 3 are repeatedly arranged in the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.
  • a plurality of bonding pads 14 are arranged in the peripheral portion 2B.
  • Each of the plurality of bonding pads 14 is arranged, for example, along each of four sides in the two-dimensional plane of the semiconductor chip 2 .
  • Each of the plurality of bonding pads 14 functions as an input/output terminal that electrically connects the semiconductor chip 2 and an external device.
  • the semiconductor chip 2 has a logic circuit 13 shown in FIG.
  • the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like, as shown in FIG.
  • the logic circuit 13 is composed of a CMOS (Complementary MOS) circuit having, for example, an n-channel conductivity type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-channel conductivity type MOSFET as field effect transistors.
  • CMOS Complementary MOS
  • the vertical driving circuit 4 is composed of, for example, a shift register.
  • the vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses for driving the pixels 3 to the selected pixel drive lines 10, and drives the pixels 3 in row units. That is, the vertical drive circuit 4 sequentially selectively scans the pixels 3 of the pixel array section 2A in the vertical direction row by row, and the photoelectric conversion section (photoelectric conversion element) of each pixel 3 generates signal charges according to the amount of received light. is supplied to the column signal processing circuit 5 through the vertical signal line 11 .
  • the column signal processing circuit 5 is arranged, for example, for each column of the pixels 3, and performs signal processing such as noise removal on the signals output from the pixels 3 of one row for each pixel column.
  • the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion for removing pixel-specific fixed pattern noise.
  • the horizontal driving circuit 6 is composed of, for example, a shift register.
  • the horizontal driving circuit 6 sequentially outputs a horizontal scanning pulse to the column signal processing circuit 5 to select each of the column signal processing circuits 5 in order, and the pixels subjected to the signal processing from each of the column signal processing circuits 5 are selected.
  • a signal is output to the horizontal signal line 12 .
  • the output circuit 7 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12 and outputs the processed signal.
  • signal processing for example, buffering, black level adjustment, column variation correction, and various digital signal processing can be used.
  • the control circuit 8 generates a clock signal and a control signal that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Generate. The control circuit 8 then outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.
  • each pixel 3 of the plurality of pixels 3 has a photoelectric conversion area 21 and a readout circuit 15 .
  • the photoelectric conversion region 21 includes a photoelectric conversion portion 24, a transfer transistor TRG as a pixel transistor, and a floating diffusion region FD.
  • the readout circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 21 .
  • one readout circuit 15 is assigned to one pixel 3 as an example, but the circuit configuration is not limited to this. It is good also as a circuit configuration which carries out.
  • the floating diffusion region FD corresponds to a specific example of the "charge holding portion" of the present technology.
  • the photoelectric conversion unit 24 shown in FIG. 3 is composed of, for example, a pn junction photodiode (PD), and generates signal charges according to the amount of received light.
  • the photoelectric conversion unit 24 has a cathode side electrically connected to the source region of the transfer transistor TRG, and an anode side electrically connected to a reference potential line (for example, ground).
  • the transfer transistor TRG shown in FIG. 3 transfers signal charges photoelectrically converted by the photoelectric conversion unit 24 to the floating diffusion region FD.
  • a source region of the transfer transistor RTL is electrically connected to the cathode side of the photoelectric conversion unit 24, and a drain region of the transfer transistor TRG is electrically connected to the floating diffusion region FD.
  • a gate electrode of the transfer transistor TRG is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).
  • the floating diffusion region FD shown in FIG. 3 temporarily holds (accumulates) signal charges transferred from the photoelectric conversion unit 24 via the transfer transistor TRG.
  • the photoelectric conversion region 21 including the photoelectric conversion section 24, the transfer transistor TRG, and the floating diffusion region FD is mounted on the semiconductor layer 20 (see FIG. 5), which will be described later.
  • the readout circuit 15 shown in FIG. 3 reads the signal charge held in the floating diffusion region FD and outputs a pixel signal based on this signal charge.
  • the readout circuit 15 includes, but is not limited to, pixel transistors such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.
  • pixel transistors such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.
  • Each of these transistors (AMP, SEL, RST) and the above-described transfer transistor TRG has, as a field effect transistor, a gate insulating film made of, for example, a silicon oxide (SiO 2 ) film, a gate electrode, a source region and a drain. and a pair of main electrode regions functioning as regions.
  • these transistors may be MISFETs (Metal Insulator Semiconductor FET) whose gate insulating film is a silicon nitride (Si 3 N 4 ) film or a laminated film of silicon nitride film and silicon oxide film.
  • MISFETs Metal Insulator Semiconductor FET
  • the amplification transistor AMP has a source region electrically connected to the drain region of the selection transistor SEL, and a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST.
  • a gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.
  • the selection transistor SEL has a source electrically connected to the vertical signal line 11 (VSL) and a drain region electrically connected to the source region of the amplification transistor AMP.
  • a gate electrode of the select transistor SEL is electrically connected to a select transistor drive line among the pixel drive lines 10 (see FIG. 2).
  • the reset transistor RST has a source region electrically connected to the floating diffusion region FD and the gate electrode of the amplification transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP.
  • a gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).
  • the transfer transistor TRG transfers signal charges generated by the photoelectric conversion unit 24 to the floating diffusion region FD when the transfer transistor TRG is turned on.
  • the reset transistor RST resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd when the reset transistor RST is turned on.
  • the selection transistor SEL controls the output timing of the pixel signal from the readout circuit 15 .
  • the amplification transistor AMP generates, as a pixel signal, a voltage signal corresponding to the level of the signal charge held in the floating diffusion region FD.
  • the amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion section 24 .
  • the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL). do.
  • the selection transistor SEL may be omitted as necessary.
  • the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).
  • FIG. 4 is a plan view schematically showing a plane pattern of the inter-pixel separation region 31 in the pixel array section 2A of the solid-state imaging device 1A.
  • FIG. 5 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a4-a4 of FIG.
  • FIG. 6 is a longitudinal sectional view enlarging a part of FIG. 4 is a plan view of the semiconductor layer 20 shown in FIG. 5 as viewed from the first surface S1 side. 5 and 6 are upside down with respect to FIG. 1 in order to make the drawings easier to see. 5 and 6 omit illustration of layers above a second wiring layer 45 of a multilayer wiring layer 40, which will be described later.
  • the semiconductor chip 2 includes a semiconductor layer 20 having a first surface S1 and a second surface S2 located opposite to each other in the thickness direction (Z direction), and a semiconductor layer 20 having a first surface S1 and a second surface S2. 20, an inter-pixel isolation region 31 and an intra-pixel isolation region 32 are provided.
  • the inter-pixel isolation region 31 corresponds to a specific example of the “first isolation region” of the present technology.
  • the intra-pixel isolation region 32 corresponds to a specific example of the “second isolation region” of the present technology.
  • the inter-pixel isolation region 31 partitions the photoelectric conversion region 21 of the semiconductor layer 20
  • the intra-pixel isolation region 32 partitions the inside of the photoelectric conversion region 21 .
  • the semiconductor chip 2 includes a multilayer wiring layer (wiring layer laminate) 40 provided on the first surface S1 side of the semiconductor layer 20, and a second surface S2 side of the semiconductor layer 20 on the second surface S2 side.
  • a fixed charge film 52, an insulating film 53, a light shielding film (light shielding body) 54, a color filter 55, and a microlens (on-chip lens) 56 are sequentially provided from the S2 side.
  • the semiconductor layer 20 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 20 and a plurality of photodiodes partitioned by the inter-pixel isolation region 31 .
  • a conversion area 21 is provided.
  • Each photoelectric conversion region 21 of the plurality of photoelectric conversion regions 21 is provided for each pixel 3 and is adjacent to each other via the inter-pixel separation region 31 in a plan view. That is, in the solid-state imaging device 1A of the first embodiment, a plurality of pixels are provided in the semiconductor layer 20 so as to be adjacent to each other with the inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 20 interposed therebetween.
  • a photoelectric conversion region 21 is provided.
  • an element isolation region (field isolation region) 25 and an island-like element forming region 20a partitioned by the element isolation region 25 are provided on the side of the first surface S1 of the semiconductor layer 20, an element isolation region (field isolation region) 25 and an island-like element forming region 20a partitioned by the element isolation region 25 are provided. , is provided.
  • the element formation region 20a is provided for each pixel 3 (photoelectric conversion region 21).
  • a Si substrate, a SiGe substrate, an InGaAs substrate, or the like can be used as the semiconductor layer 20 .
  • a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 20 .
  • the first surface S1 of the semiconductor layer 20 is sometimes called an element forming surface or main surface, and the second surface S2 side is sometimes called a light incident surface or back surface.
  • the solid-state imaging device 1A of the first embodiment photoelectrically converts light incident from the second surface (light incident surface, back surface) S2 of the semiconductor layer 20 in the photoelectric conversion region 21 provided in the semiconductor layer 20. .
  • a planar view refers to a case viewed from a direction along the thickness direction (Z direction) of the semiconductor layer 20 .
  • a cross-sectional view refers to a case where a cross section along the thickness direction (Z direction) of the semiconductor layer 20 is viewed from a direction (X direction or Y direction) orthogonal to the thickness direction (Z direction) of the semiconductor layer 20.
  • the photoelectric conversion region 21 can also be called a photoelectric conversion cell.
  • the element isolation region 25 is formed in an insulating film (field trench) 26 recessed from the first surface S1 to the second surface S2 of the semiconductor layer 20, although not limited thereto.
  • Field insulating film) 27 is selectively embedded in the STI (Shallow Trench Isolation) structure.
  • a silicon oxide film can be used as the insulating film 27, for example.
  • a p-type well region 22 which will be described later, is provided in the element formation region 20a partitioned by the element isolation region 25.
  • the pixel transistors (AMP, SEL, RST, TRG) described above are provided in the element forming region 20a.
  • illustration of the pixel transistor is omitted in FIG.
  • the transfer transistor TRG is illustrated, and illustration of other pixel transistors (AMP, SEL, RST) is omitted.
  • illustration of the element isolation region 25 and the element formation region 20a shown in FIG. 5 is also omitted.
  • each photoelectric conversion region 21 of a plurality of photoelectric conversion regions (photoelectric conversion cells) 21 includes a p-type well region 22 provided in the semiconductor layer 20 and a and the floating diffusion region FD and the photoelectric conversion portion 24 described above.
  • Each photoelectric conversion region 21 further includes an element formation region 20a, an intra-pixel isolation region 32, and a diffraction/scattering portion 51. As shown in FIG.
  • the p-type well region 22 is provided widely over the first surface S1 side and the second surface S2 side of the semiconductor layer 20 .
  • the p-type well region 22 is composed of a p-type semiconductor region.
  • the n-type semiconductor region 23 is separated from the first surface S 1 and the second surface S 2 of the semiconductor layer 20 and the inter-pixel isolation region 31 . provided over the first surface S1 side and the second surface S2 side.
  • the n-type semiconductor region 23 has an upper surface portion on the first surface S1 side of the semiconductor layer 20, a lower surface portion on the second surface S2 side of the semiconductor layer 20, and a side surface portion on the inter-pixel isolation region 31 side. Each is surrounded by a p-type well region 22 .
  • p-type well regions 22 are provided so as to overlap the n-type semiconductor regions 23 respectively.
  • a p-type well region 22 extending along the thickness direction (Z direction) of the semiconductor layer 20 is provided between the inter-pixel isolation region 31 and the n-type semiconductor region 23 .
  • the floating diffusion region FD is provided in the surface layer portion of the p-type well region 22 on the first surface S1 side of the semiconductor layer 20 .
  • the floating diffusion region FD is composed of an n-type semiconductor region (floating diffusion region) having an impurity concentration higher than that of the n-type semiconductor region 23, for example.
  • the photoelectric conversion section 24 is mainly composed of an n-type semiconductor region 23 and is configured as a pn junction photodiode (PD) composed of a p-type well region 22 and an n-type semiconductor region 23 .
  • the transfer transistor TRG included in the photoelectric conversion region 21 is not illustrated in detail, but will be described with reference to FIGS.
  • the transfer transistor TRG further includes a photoelectric conversion portion 24 (n-type semiconductor region 23) functioning as a source region, and a floating diffusion region FD functioning as a drain region.
  • the transfer transistor TRG controls a channel formed in the channel forming region by a gate voltage applied to the gate electrode 37 .
  • the transfer transistor TRG transfers signal charges photoelectrically converted (generated) by the photoelectric conversion unit 24 from the photoelectric conversion unit 24 to the floating diffusion region FD via a channel formed in the channel formation region.
  • each of the pixel transistors (AMP, SEL, RST) included in the readout circuit 15 is described with reference to FIG.
  • a gate insulating film provided on the p-type well region 22 a gate electrode provided on the p-type well region 22 via the gate insulating film, and a p-type electrode directly below the gate electrode. and a channel formation region in which a channel (conducting path) is formed in the well region 22 of .
  • Each of the pixel transistors (AMP, SEL, RST) included in the readout circuit 15 is provided in the p-type well region 22 while being separated from each other in the channel length direction (gate length direction) with the channel forming region interposed therebetween. and a pair of main electrode regions functioning as source and drain regions. These pixel transistors control a channel formed in a channel forming region by a gate voltage applied to a gate electrode.
  • the semiconductor layer 20 includes an inter-pixel isolation region 31 as a first isolation region and an intra-pixel isolation region 32 as a second isolation region. That is, the solid-state imaging device 1A according to the first embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32 as first and second isolation regions that partition the semiconductor layer 20 .
  • the pixel isolation region 31 includes a first portion 31x extending in the X direction and a second portion 31y extending in the Y direction in plan view.
  • the first portion 31x and the second portion 31y are orthogonal to each other.
  • the first portions 31x are repeatedly arranged in the Y direction at predetermined intervals. Also, the second portions 31y are repeatedly arranged in the X direction at predetermined intervals. That is, the inter-pixel separation region 31 has a grid-like planar pattern in plan view.
  • Each photoelectric conversion region 21 of the plurality of photoelectric conversion regions 21 is partitioned by two second portions 31y of the separation regions 31 adjacent to each other on both ends in the X direction, and separated by the separation regions 31 on both ends in the Y direction. It is partitioned by two matching first portions 31x.
  • the inter-pixel isolation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 20 and electrically and optically separates the photoelectric conversion regions 21 adjacent to each other in plan view. separated into One end side of the inter-pixel isolation region 31 is connected to the element isolation region 25 , and the other end side reaches the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the inter-pixel isolation region 31 is a fixed charge film 52 provided along the inner wall (side wall and bottom wall) of the dug portion 33a extending in the depth direction (Z direction) of the semiconductor layer 20. and an insulating film 53 as an insulating material that fills the dug portion 33 a with a fixed charge film 52 interposed therebetween and has a refractive index lower than that of the semiconductor layer 20 . That is, the inter-pixel isolation region 31 of the first embodiment includes the insulating film 53 as an insulating material having a lower refractive index than the semiconductor layer 20 . Air can also be used as the insulating material having a lower refractive index than the semiconductor layer 20 . In this case, the inter-pixel isolation region 31 includes a cavity filled with air.
  • the dug portion 33a of the first embodiment corresponds to a specific example of the "first dug portion" of the present technology.
  • the fixed charge film 52 is provided over the second surface S ⁇ b>2 of the semiconductor layer 20 and the recessed portion 33 a of the semiconductor layer 20 .
  • the fixed charge film 52 includes, for example, a dielectric film that generates negative fixed charges.
  • hafnium oxide (HfO 2 ) having a high dielectric constant can be used as the dielectric film.
  • the fixed charge film 52 induces holes (h + ) at the interface between the semiconductor layer 20 and the inter-pixel isolation region 31, and pinning can be ensured at this interface, thereby preventing the generation of dark current. can be suppressed.
  • zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), or the like can be used as the dielectric film.
  • the insulating film 53 is provided over the second surface S ⁇ b>2 of the semiconductor layer 20 and the second dug portion 33 b of the semiconductor layer 20 .
  • a silicon oxide film can be used as the insulating film 53.
  • a silicon oxide film has a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs.
  • the insulating film 53 covers the entire second surface S2 side of the semiconductor layer 20 in the pixel array section 2A so that the second surface S2 (light incident surface) side of the semiconductor layer 20 is a flat surface without unevenness. ing.
  • silicon has a refractive index of about 3.62
  • silicon oxide has a refractive index of about 1.45
  • air has a refractive index of about 1.45. It has a refractive index of about 00.
  • silicon has a refractive index of about 4.08
  • silicon oxide has a refractive index of about 1.46
  • air has a refractive index of about 1.46. It has a refractive index of about 00.
  • the intra-pixel isolation region 32 extends, for example, in the X direction in plan view, and is provided apart from the inter-pixel isolation region 31 (the first portion 31x and the second portion 31y). Further, the intra-pixel separation region 32 is arranged so as to be closer to the inter-pixel separation region 31 side than the central portion of the photoelectric conversion region 21 in plan view, and the width of the photoelectric conversion region 21 in the Y direction in plan view is relatively large. It is selectively separated (partitioned) into two different regions (first region 21a and second region 21b).
  • the photoelectric conversion unit 24 is provided in the region (first region 21a) that is wider in the Y direction.
  • a floating diffusion region FD is provided in a region (second region 21b) having a smaller width in the Y direction. That is, the photoelectric conversion region 21 includes the photoelectric conversion portion 24 and the floating diffusion region FD that are separated from each other by the intra-pixel separation region 32 .
  • the intra-pixel isolation region 32 extends in the thickness direction (Z direction) of the semiconductor layer 20 , is connected to the element isolation region 25 at one end, and is connected to the second region of the semiconductor layer 20 at the other end. has reached the surface S2.
  • the intra-pixel isolation region 32 is composed of an isolation insulating film 34 provided along the side wall of a dug portion 33b extending in the depth direction (Z direction) of the semiconductor layer 20, and the isolation insulating film 34 in the dug portion 33b. and a conductive material 35 filled through.
  • a silicon oxide film for example, can be used as the isolation insulating film 34 .
  • As the conductive material 35 for example, a semiconductor film into which an impurity that reduces resistance is introduced can be used.
  • the conductive material 35 of the first embodiment is composed of, but not limited to, a p-type doped polysilicon film into which boron (B) is introduced as an impurity, for example.
  • the dug portion 33b of the first embodiment corresponds to a specific example of the "second dug portion" of the present technology.
  • the transfer transistor TRG is provided so as to cross between the end portion of the intra-pixel isolation region 32 in the X direction and the inter-pixel isolation region 31 in plan view.
  • a p-type well region 22 is provided in each of two regions separated by the intra-pixel separation region 32 of the photoelectric conversion region 21 .
  • a first reference potential of 0 V, for example, is applied as a power supply potential to the p-type well region 22, and the potential is fixed at this first reference potential.
  • the multilayer wiring layer (wiring layer laminate) 40 is provided on the first surface S1 side opposite to the light incident surface side (second surface S2 side) of the semiconductor layer 20.
  • the multilayer wiring layer 40 includes, but is not limited to, an interlayer insulating film 41, a first wiring layer 43, an interlayer insulating film 44, and an interlayer insulating film 41, which are sequentially laminated from the first surface S1 side of the semiconductor layer 20. It has a laminated structure including the wiring layer 45 of the second layer.
  • the interlayer insulating film 41 is provided on the first surface S1 side of the semiconductor layer 20 so as to cover the gate electrodes of the pixel transistors (AMP, SEL, RST, TRG). Pixel transistors are not shown in FIG.
  • a first wiring layer 43 is provided above the interlayer insulating film 41 , and the first wiring layer 43 is covered with an upper interlayer insulating film 44 .
  • a second wiring layer 45 is provided above the interlayer insulating film 44 . Although not shown, the second wiring layer 45 is covered with an upper interlayer insulating film.
  • FIG. 5 the wirings 43a, 43b 1 , 43f formed in the wiring layer 41 of the first layer and the wiring 45a formed in the wiring layer 45 of the second layer are illustrated.
  • the wiring 43f is electrically connected to the floating diffusion region FD via a contact electrode (conductive plug) 42f embedded in the interlayer insulating film 41.
  • This wiring 43f is electrically connected to the input side of the readout circuit 15 (the gate electrode of the amplification transistor AMP and the source region of the reset transistor RST) shown in FIG.
  • the wiring 43 b 1 is electrically connected to the conductive material 35 of the intra-pixel isolation region 32 via the contact electrode 42 b 1 buried over the interlayer insulating film 41 and the element isolation region 25 .
  • a second reference potential which is a positive potential higher than the first reference potential applied to the p-type well region 22, is applied to the wiring 43b1 as a power supply potential. That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 43b via the contact electrode 42b1 , and is fixed at this second reference potential. For example, 2.7 V is applied as the second reference potential.
  • Each of the wiring layers 43 and 45 is made of, for example, a metal film such as copper (Cu) or an alloy mainly composed of Cu.
  • Each of the interlayer insulating films 41 and 44 is, for example, one single layer film of a silicon oxide film, a silicon nitride (Si 3 N 4 ) film, or a silicon carbonitride (SiCN) film, or two or more of these. It is composed of a laminated film in which
  • Each of the contact electrodes 42b1 and 42f is composed of, for example, a refractory metal film such as a tungsten (W) film or a titanium (Ti) film.
  • the diffraction/scattering portion 51 has a structure in which periodic unevenness is provided on the interface of the semiconductor layer 20 on the light incident surface side (second surface S2 side).
  • the diffraction/scattering portion 51 is provided so as to overlap the photoelectric conversion portion 24 for each photoelectric conversion region 21 in plan view.
  • the unevenness of the diffraction/scattering portion 51 serves as a diffraction grating, and high-order components are diffracted in an oblique direction, so that the optical path length in the photoelectric conversion portion 24 can be lengthened.
  • the diffraction/scattering portion 51 for example, a quadrangular pyramid formed by wet etching the Si (111) surface using alkaline ionized water (AKW) can be applied. .
  • the diffraction/scattering portion 51 may be formed by dry etching. Furthermore, by adopting a shape in which the cross-sectional area changes in the depth direction, reflection is suppressed and the sensitivity is slightly improved.
  • the light shielding film 54 is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the light-shielding film 54 has a planar pattern that opens on the light receiving surface side of each of the plurality of photoelectric conversion regions 21 so that light incident on a predetermined photoelectric conversion region 21 does not leak into the adjacent photoelectric conversion region 21 . It has a grid plane pattern.
  • the light-shielding film 54 has the same grid plane pattern as the grid plane pattern of the pixel isolation region 31 , and is arranged at a position overlapping the pixel isolation region 31 in plan view.
  • the light shielding film 54 covers the region between the inter-pixel isolation region 31 and the intra-pixel isolation region 32 in plan view, specifically, the p-type well region 22 and the floating diffusion region FD.
  • the width is selectively thickened as shown in FIG. That is, the floating diffusion region FD is arranged at a position overlapping the light shielding film 54 in plan view.
  • the light shielding film 54 for example, a tungsten (W) film having a light shielding property is used.
  • the color filter 55 is provided for each photoelectric conversion region 21 (pixel 3) on the opposite side (light incident surface side) of the light shielding film 54 from the semiconductor layer 20 side.
  • the color filter 55 color-separates the incident light incident from the light incident surface side of the semiconductor chip 2 .
  • the color filters 55 include a red (R) first color filter, a green (G) second color filter, and a blue (B) third color filter. In this first embodiment, for example, three color filters 55 of R, G, and B are provided.
  • a microlens 56 is provided for each photoelectric conversion region 21 (pixel 3) on the opposite side (light incident surface side) of the color filter 55 from the light shielding film 54 side.
  • the microlenses 56 condense the irradiation light and allow the condensed light to enter the photoelectric conversion region 21 efficiently.
  • the photoelectric conversion unit 24 shown in FIGS. 5 and 6 converts light with a wavelength in the visible region (hereinafter referred to as visible light) or light with a wavelength in the near-infrared region (hereinafter referred to as near-infrared light (NIR)). photoelectric conversion.
  • the photoelectric conversion unit 24 photoelectrically converts near-infrared light (handles near-infrared light) by making the thickness of the semiconductor layer 20 thicker than when photoelectrically converting visible light (handling visible light). be able to. Therefore, by selecting the thickness of the semiconductor layer 20 so that the photoelectric conversion unit 24 can photoelectrically convert near-infrared light, the light (visible light or near-infrared light) can be selected.
  • the thickness of the semiconductor layer is set to a thickness that enables photoelectric conversion of near-infrared light.
  • the wavelength range of near-infrared light is about 700 nm to 2500 nm
  • the wavelength range of visible light is about lower limit 360-400 nm to upper limit 760-830 nm.
  • the thickness of the semiconductor layer 20 in the photoelectric conversion region 21 that handles visible light is usually 2.5 ⁇ m or more, and the thickness of the semiconductor layer 20 in the photoelectric conversion region 21 that handles near-infrared light is 6 ⁇ m or more. It may become
  • the solid-state imaging device 1A includes an inter-pixel separation region 31 corresponding to a specific example of the "first separation region” of the present technology and a specific example of the "second separation region” of the present technology. and corresponding intra-pixel isolation regions 32 .
  • the inter-pixel isolation region 31 has a structure in which an insulating film 53 as an insulating material having a refractive index lower than that of the semiconductor layer 20 is filled in the dug portion 33 a extending in the thickness direction (Z direction) of the semiconductor layer 20 . It has become.
  • the intra-pixel isolation region 32 has a configuration in which a dug portion 33 b extending in the thickness direction of the semiconductor layer 20 is filled with a conductive material 35 .
  • the potential of the semiconductor layer 20 on the side wall of the intra-pixel isolation region 32 changes, and the signal charge photoelectrically converted by the photoelectric conversion portion 24 is transferred.
  • the floating diffusion region FD it can function as an assist electrode that assists the transfer of the signal charge to the floating diffusion region FD, thereby improving transfer characteristics as pixel characteristics.
  • This improvement in transfer characteristics is particularly effective when the thickness of the semiconductor layer 20 is increased to photoelectrically convert near-infrared light. Therefore, according to the solid-state imaging device 1A of the first embodiment, it is possible to improve pixel characteristics.
  • the thickness of the semiconductor layer 20 is increased so that near-infrared light can be photoelectrically converted by the photoelectric conversion section 24, or when the diffraction scattering section 51 is provided in the photoelectric conversion region 21,
  • high MTF characteristics can be achieved while ensuring high quantum efficiency QE.
  • the width of the inter-pixel isolation region 31 and the miniaturization of the photoelectric conversion region 21 can be achieved.
  • the solid-state imaging device 1A of the first embodiment is arranged between the inter-pixel isolation region 31 and the intra-pixel isolation region 32 on the light incident surface side (second surface S2 side) of the semiconductor layer 20.
  • a light shielding film 54 is provided which is selectively widened so as to cover the floating diffusion region FD. Therefore, it is possible to suppress light irradiation to the floating diffusion region FD, and improve parasitic light sensitivity characteristics (PLS (Parasitic Light Sensitivity) characteristics).
  • the thickness of the semiconductor layer 20 is set thick so that the photoelectric conversion portion 24 can photoelectrically convert near-infrared light has been described.
  • the present technology can also be applied when the thickness of the semiconductor layer 20 is set thin so that the photoelectric conversion unit 24 can selectively photoelectrically convert visible light.
  • each of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 reaches the second surface S2 of the semiconductor layer 20 has been described.
  • the present technology can be applied even when each of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 is separated from the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the case where the silicon film into which the impurity for reducing the resistance value is introduced is used as the conductive material 35 of the intra-pixel isolation region 32 has been described.
  • a silicon film absorbs light
  • a conductive refractory metal film such as tungsten or titanium
  • a conductive metal film such as aluminum (Al), or an alloy film
  • the intra-pixel isolation region 32 can also be used as a transfer transistor having an assist function of assisting the transfer of signal charges to the floating diffusion region FD.
  • a solid-state imaging device 1B according to the second embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, and the following configurations are different. That is, the solid-state imaging device 1B according to the second embodiment includes pixels 3a shown in FIG. 7A and pixels 3b shown in FIG. 7B instead of the pixels 3 shown in FIG. 3 of the first embodiment. there is Further, in the solid-state imaging device 1B according to the second embodiment, instead of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 shown in FIGS. 4 and 5 of the above-described first embodiment, a first inter-pixel isolation region 31a and a second pixel isolation region 31b. Other configurations are basically the same as those of the above-described first embodiment.
  • the pixel 3a has a first photoelectric conversion region 21A and a readout circuit 15a.
  • the first photoelectric conversion region 21A includes a photoelectric conversion portion 24a, a transfer transistor TRG1 as a pixel transistor, and a floating diffusion region FD1 as a charge holding portion.
  • the readout circuit 15a is electrically connected to the floating diffusion region FD1 of the first photoelectric conversion region 21A.
  • the pixel 3b has a second photoelectric conversion region 21B and a readout circuit 15b.
  • the second photoelectric conversion region 21B includes a photoelectric conversion portion 24b, a transfer transistor TRG2 as a pixel transistor, and a floating diffusion region FD2 as a charge holding portion.
  • the readout circuit 15b is electrically connected to the floating diffusion region FD2 of the second photoelectric conversion region 21B.
  • one pixel 3a, 3b has a circuit configuration in which one readout circuit 15a, 15b is assigned to one pixel 3a, 3b.
  • a circuit configuration may be adopted in which one readout circuit 15a is shared by a plurality of pixels 3a and one readout circuit 15b is shared by a plurality of pixels 3b.
  • the photoelectric conversion unit 24a shown in FIG. 7A is composed of, for example, a pn junction photodiode (PD).
  • the photoelectric conversion unit 24a generates (photoelectrically converts) signal charges corresponding to the amount of received light (near-infrared light) with a wavelength in the near-infrared region, and holds the signal charges.
  • the photoelectric conversion unit 24a has a cathode side electrically connected to the source region of the transfer transistor TRG1, and an anode side electrically connected to a reference potential line (for example, ground).
  • the transfer transistor TRG1 shown in FIG. 7A transfers signal charges photoelectrically converted by the photoelectric conversion unit 24a to the floating diffusion region FD1.
  • a source region of the transfer transistor RTG1 is electrically connected to the cathode side of the photoelectric conversion unit 24a, and a drain region of the transfer transistor TRG is electrically connected to the floating diffusion region FD1.
  • a gate electrode of the transfer transistor TRG1 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).
  • the floating diffusion region FD1 shown in FIG. 7A temporarily holds (accumulates) signal charges transferred from the photoelectric conversion unit 24a via the transfer transistor TRG1.
  • a first photoelectric conversion region 21A including the photoelectric conversion portion 24a, the transfer transistor TRG1, and the floating diffusion region FD1 is mounted on the semiconductor layer 20 shown in FIG.
  • the readout circuit 15a shown in FIG. 7A reads out the signal charge held in the floating diffusion region FD1 and outputs a pixel signal based on this signal charge.
  • the readout circuit 15a has the same configuration as the readout circuit 15 of the above-described first embodiment, although not limited thereto. , is equipped with
  • the photoelectric conversion unit 24b shown in FIG. 7B is composed of, for example, a pn junction photodiode (PD).
  • the photoelectric conversion unit 24b generates (photoelectrically converts) signal charges corresponding to the amount of received light (visible light) from light having a wavelength in the visible region, and holds the signal charges.
  • the photoelectric conversion unit 24b has a cathode side electrically connected to the source region of the transfer transistor TRG2, and an anode side electrically connected to a reference potential line (for example, ground).
  • the transfer transistor TRG2 shown in FIG. 7B transfers the signal charge photoelectrically converted by the photoelectric conversion unit 24b to the floating diffusion region FD2.
  • a source region of the transfer transistor RTG2 is electrically connected to the cathode side of the photoelectric conversion unit 24b, and a drain region of the transfer transistor TRG2 is electrically connected to the floating diffusion region FD2.
  • a gate electrode of the transfer transistor TRG2 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).
  • the floating diffusion region FD2 shown in FIG. 7B temporarily holds (accumulates) signal charges transferred from the photoelectric conversion unit 24b via the transfer transistor TRG2.
  • a second photoelectric conversion region 21B including the photoelectric conversion portion 24b, the transfer transistor TRG2, and the floating diffusion region FD2 is mounted on the semiconductor layer 20 shown in FIG.
  • the readout circuit 15b shown in FIG. 7B reads out the signal charge held in the floating diffusion region FD2 and outputs a pixel signal based on this signal charge.
  • the readout circuit 15b has the same configuration as the readout circuit 15 of the above-described first embodiment, although not limited thereto. , is equipped with
  • the semiconductor layer 20 includes first and second pixel separation regions 31a and 31b extending in the thickness direction (Z direction) of the semiconductor layer 20, and the first pixel separation regions 31a and 31b.
  • a first photoelectric conversion region 21A partitioned by the region 31a and a second photoelectric conversion region 21B partitioned by the second inter-pixel separation region 31b are provided.
  • the first photoelectric conversion region 21A and the second photoelectric conversion region 21B are alternately arranged in the X direction and the Y direction, which are orthogonal to each other in a two-dimensional plane, in the pixel array section 2A. placed repeatedly.
  • the pixels 3a including the first photoelectric conversion regions 21A and the pixels 3b including the second photoelectric conversion regions 21B are alternately arranged in the X direction and the Y direction. are repeatedly placed in the FIG. 8 shows five first photoelectric conversion regions 21A (pixels 3a: NIR) and four second photoelectric conversion regions 21B (pixels 3b: RGB).
  • the first photoelectric conversion region 21A basically has the same configuration as the photoelectric conversion region 21 of the first embodiment described above. That is, the first photoelectric conversion region 21A includes a p-type well region 22, an n-type semiconductor region 23, a floating diffusion region FD1, and a photoelectric conversion portion, similarly to the photoelectric conversion region 21 of the first embodiment described above. 24a, a transfer transistor TRG1 (see FIG. 8), an element forming region 20a, and a diffraction scattering portion 51.
  • FIG. The first photoelectric conversion region 21A does not include the intra-pixel separation region 32 shown in FIGS. 4 and 5 of the above-described first embodiment.
  • the second photoelectric conversion region 21B has basically the same configuration as the photoelectric conversion region 21 of the first embodiment described above. That is, the second photoelectric conversion region 21B includes a p-type well region 22, an n-type semiconductor region 23, a floating diffusion region FD2, and a photoelectric conversion portion, similarly to the photoelectric conversion region 21 of the first embodiment. 24b, a transfer transistor TRG2 (see FIG. 8), an element forming region 20a, and a diffraction scattering portion 51.
  • each of the floating diffusion regions FD1 and FD2 is located on the side of the first surface S1 of the semiconductor layer 20 in the p-type well region 22, similarly to the floating diffusion region FD of the first embodiment. It is provided on the surface layer.
  • Each of the floating diffusion regions FD1 and FD2 is composed of an n-type semiconductor region (floating diffusion region) having an impurity concentration higher than that of the n-type semiconductor region 23 .
  • Each of the photoelectric conversion units 24a and 24b is mainly composed of an n-type semiconductor region 23, and includes a p-type well region 22 and an n-type semiconductor region 23, similarly to the photoelectric conversion unit 24 of the first embodiment. is configured as a pn junction type photodiode (PD).
  • the first inter-pixel separation region 31a includes a first portion 31x extending in the X direction in a plan view, similar to the inter-pixel separation region 31 shown in FIG. 4 of the above-described first embodiment, and and a second portion 31y extending in the Y direction.
  • the first portion 31x and the second portion 31y are orthogonal to each other.
  • the first portions 31x are repeatedly arranged in the Y direction at predetermined intervals. Also, the second portions 31y are repeatedly arranged in the X direction at predetermined intervals. That is, the first inter-pixel separation region 31a has a grid-like planar pattern in plan view.
  • the first photoelectric conversion region 21A is partitioned by two adjacent second portions 31y of the separation region 31a on both end sides in the X direction, and two first portions 31x of the separation region 31 adjacent to each other on both end sides in the Y direction. are separated by
  • the second pixel isolation region 31b is arranged adjacent to the first pixel isolation region 31a within the region partitioned by the first pixel isolation region 31a.
  • the second inter-pixel isolation region 31b has an annular planar pattern in plan view, and is in contact with the first portion 31x and the second portion 31y of the first inter-pixel isolation region 31a. That is, the second photoelectric conversion region 21B is partitioned by the second inter-pixel separation regions 31b on both end sides in the X direction in a plan view, and by the second inter-pixel separation regions 31b on both end sides in the Y direction.
  • first photoelectric conversion region 21A and the second photoelectric conversion region 21B are adjacent to each other via the first and second inter-pixel isolation regions 31a and 31b that are adjacent to each other.
  • the first photoelectric conversion region 21A and the second photoelectric conversion region 21B adjacent to each other are electrically and optically separated by the first and second inter-pixel separation regions 31a and 31b.
  • the first inter-pixel separation region 31a extends in the thickness direction (Z direction) of the semiconductor layer 20, and the first photoelectric conversion region 21A and the second photoelectric conversion region 21B are adjacent to each other in plan view. are electrically and optically separated from each other.
  • One end of the first inter-pixel isolation region 31 a is connected to the element isolation region 25 , and the other end of the first inter-pixel isolation region 31 a reaches the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the first inter-pixel isolation region 31a includes a fixed charge film 52 provided along the inner wall (side wall and bottom wall) of the dug portion 33a1 extending in the depth direction (Z direction) of the semiconductor layer 20, and an insulating film 53 as an insulating material that fills the recessed portion 33 a 1 via a fixed charge film 52 and has a lower refractive index than the semiconductor layer 20 .
  • Air can also be used as the insulating material having a lower refractive index than the semiconductor layer 20 .
  • the first inter-pixel isolation region 31a includes a cavity filled with air.
  • the dug portion 33a1 of the second embodiment corresponds to a specific example of the "first dug portion" of the present technology.
  • the second inter-pixel separation region 31b extends in the thickness direction (Z direction) of the semiconductor layer 20, and the first photoelectric conversion region 21A and the second photoelectric conversion region 21B are adjacent to each other in plan view. are electrically and optically separated from each other.
  • One end of the second inter-pixel isolation region 31 b is connected to the element isolation region 25 , and the other end reaches the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the second inter-pixel isolation region 31b includes an isolation insulating film 34 provided along the inner wall (side wall and bottom wall) of the second dug portion 33a2 extending in the depth direction (Z direction) of the semiconductor layer 20; A conductive material 35 with a lower refractive index than the semiconductor layer 20 is filled in the dug portion 33 a 2 with an isolation insulating film 34 interposed therebetween.
  • a silicon oxide film for example, can be used as the isolation insulating film 34 .
  • As the conductive material 35 for example, a semiconductor film into which an impurity that reduces resistance is introduced can be used.
  • the conductive material 35 of the second embodiment is composed of, but not limited to, a p-type doped polysilicon film into which boron (B) is introduced as an impurity, for example.
  • the dug portion 33b2 of the second embodiment corresponds to a specific example of the "second dug portion" of the present technology.
  • the conductive material 35 of the second inter-pixel isolation region 31b is connected to the wiring layer of the first layer via the contact electrode 42b2 embedded over the interlayer insulating film 41 and the element isolation region 25. It is electrically connected to the wiring 43b2 formed in 43.
  • the wiring 43b2 is applied with a third reference potential which is a negative potential lower than the first reference potential applied to the p-type well region 22 as a power supply potential. be. That is, the conductive material 35 of the second inter-pixel isolation region 31b is supplied with the second reference potential applied to the wiring 43b2 through the contact electrode 42b2 , and is fixed at this third reference potential.
  • ⁇ 1.2 V is applied as the third reference potential.
  • the potential of the semiconductor layer 20 on the side wall of the second pixel isolation region 31b is changed to increase the saturated charge amount Qs. It is possible to improve the pixel characteristics.
  • the floating diffusion region FD1 of the first photoelectric conversion region 21A is connected to the wiring 43f formed in the wiring layer 43 of the first layer via the contact electrode 42f1 embedded in the interlayer insulating film 41. 1 is electrically connected.
  • This wiring 43f1 is electrically connected to the input side (the gate electrode of the amplification transistor AMP and the source region of the reset transistor RST) of the readout circuit 15a shown in FIG. 7A.
  • the floating diffusion region FD2 of the second photoelectric conversion region 21B is connected to the wiring 43f2 formed in the first wiring layer via the contact electrode 42f2 embedded in the interlayer insulating film 41. is electrically connected to This wiring 43f2 is electrically connected to the input side (the gate electrode of the amplification transistor AMP and the source region of the reset transistor RST) of the readout circuit 15b shown in FIG. 7B.
  • near-infrared light and visible light can be separated by the color filter 55, for example.
  • the color filter 55a that transmits near-infrared light so as to overlap the first photoelectric conversion region 21A in plan view
  • the first photoelectric conversion region 21A (the first photoelectric conversion unit 24a) can Infrared light can be incident.
  • the color filter 55b through which visible light passes so as to overlap the second photoelectric conversion region 21B in plan view
  • visible light can be made incident on the second photoelectric conversion region 21B (second photoelectric conversion unit 24b). can be done.
  • the color filter 55 (55a) is arranged so as to overlap the first photoelectric conversion region 21A in plan view, but the first photoelectric conversion unit 24a for photoelectrically converting near-infrared light is provided.
  • the color filter 55 does not necessarily have to be arranged in the first photoelectric conversion region 21A.
  • the solid-state imaging device 1B includes a first inter-pixel isolation region 31a as a “first isolation region” of the present technology, and a first photoelectric conversion region partitioned by the first inter-pixel isolation region 31a. 21A, a second inter-pixel separation region 31b as a “second separation region” of the present technology, and a second photoelectric conversion region 21B partitioned by the second pixel separation region 31b. Then, the first inter-pixel isolation region 31a is formed in a recessed portion 33a1 extending in the thickness direction (Z direction) of the semiconductor layer 20 in the same manner as the inter-pixel isolation region 31 of the first embodiment described above.
  • the first inter-pixel isolation region 31a a first photoelectric conversion region 21A including a first photoelectric conversion unit 24a that can suppress absorption of light, in other words, increase light reflection in the first inter-pixel separation region 31a, and that photoelectrically converts near-infrared light; Even when the second photoelectric conversion region 21B including the second photoelectric conversion portion 24b that photoelectrically converts visible light is mounted together, it is possible to improve the quantum efficiency QE and highly suppress color mixing (high MTF characteristics).
  • a recessed portion 33a2 extending in the thickness direction of the semiconductor layer 20 is filled with the conductive material 35 in the same manner as the intra-pixel isolation region 32 of the first embodiment described above. It is configured. Therefore, by applying a negative potential to the conductive material 35 of the second pixel isolation region 31b, the potential of the semiconductor layer 20 on the side wall of the second pixel isolation region 31b changes, and the second pixel photoelectric conversion potential of visible light is changed.
  • the saturated charge amount Qs in the second photoelectric conversion region 21B provided with the photoelectric conversion portion 24b can be increased, and the pixel characteristics can be improved. Therefore, in the solid-state imaging device 1B according to the second embodiment as well, it is possible to improve the pixel characteristics.
  • the width of the first pixel isolation region 31a can be reduced in the solid-state imaging device 1B according to the second embodiment as well.
  • miniaturization of each of the first photoelectric conversion region 21A and the second photoelectric conversion region 21B can be achieved.
  • the floating diffusion regions FD1 and FD2 and the light shielding film 54 do not overlap in plan view, but as shown in FIG. 6 of the first embodiment described above, the floating diffusion regions FD1 and FD2
  • the width of the light shielding film 54 may be selectively increased so as to cover the .
  • This third embodiment includes the inter-pixel isolation region 31 and the intra-pixel isolation region 32 shown in FIGS. It is a combination of the photoelectric conversion region 21A and the second photoelectric conversion region 21B.
  • a first photoelectric conversion region 21A and a first photoelectric conversion region 21A and a first photoelectric conversion region 21A and a first photoelectric conversion region 21A and a first photoelectric conversion region 21A are respectively partitioned adjacent to each other by an inter-pixel separation region 31.
  • FIGS. It has two photoelectric conversion regions 21B. At least one of the first photoelectric conversion region 21A and the second photoelectric conversion region 21B, for example, the in-pixel separation region 32 is provided in the first photoelectric conversion region 21A.
  • the first photoelectric conversion region 21A is provided with the intra-pixel isolation region 32, and the second photoelectric conversion region 21B is not provided with the intra-pixel isolation region 32.
  • the inter-pixel isolation region 31 corresponds to a specific example of the "first isolation region" of the present technology
  • the intra-pixel isolation region 32 is a specific example of the "second isolation region” of the present technology. corresponds to the example.
  • Other configurations are basically the same as those of the above-described first embodiment.
  • pixels 3a including first photoelectric conversion regions 21A and pixels 3b including second photoelectric conversion regions 21B are arranged in the pixel array section 2A of the third embodiment.
  • the pixels 3b are repeatedly arranged in the X direction and the Y direction, which are orthogonal to each other in the two-dimensional plane.
  • Pixels 3a are interspersed in a pixel group in which a plurality of pixels 3b are arranged, and form a pixel row together with the pixels 3b.
  • FIG. 10 shows, as an example, an arrangement pattern in which eight pixels 3b are arranged around one pixel 3a.
  • the pixels 3a may be arranged periodically or randomly.
  • the conductive material 35 of the intra-pixel isolation region 32 is connected to the wiring layer 43 of the first layer via the contact electrode 42b1 embedded over the interlayer insulating film 41 and the element isolation region 25. It is electrically connected to the wiring 43b1 .
  • a positive second reference potential higher than the first reference potential applied to the p-type well region 22 is applied to the wiring 43b1 as the power supply potential in the same manner as in the first embodiment. be. That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 43b1 through the contact electrode 42b1 , and is fixed at this second reference potential.
  • the floating diffusion region FD1 of the first photoelectric conversion region 21A is connected to the wiring 43f formed in the wiring layer 43 of the first layer via the contact electrode 42f1 embedded in the interlayer insulating film 41. 1 is electrically connected.
  • This wiring 43f1 is electrically connected to the input side (the gate electrode of the amplification transistor AMP and the source region of the reset transistor RST) of the readout circuit 15a shown in FIG. 7A of the second embodiment.
  • the floating diffusion region FD2 of the second photoelectric conversion region 21B is connected to the wiring 43f2 formed in the first wiring layer via the contact electrode 42f2 embedded in the interlayer insulating film 41. is electrically connected to This wiring 43f2 is electrically connected to the input side (the gate electrode of the amplification transistor AMP and the source region of the reset transistor RST) of the readout circuit 15b shown in FIG. 7B of the second embodiment.
  • a solid-state imaging device 1 ⁇ /b>C according to the third embodiment includes an inter-pixel isolation region 31 corresponding to one specific “first isolation region” of the present technology, and a first photoelectric conversion region partitioned by the inter-pixel isolation region 31 . 21A and a second photoelectric conversion region 21B. Then, the inter-pixel isolation region 31 of the third embodiment is formed into a recessed portion 33a extending in the thickness direction (Z direction) of the semiconductor layer 20, similarly to the inter-pixel isolation region 31 of the first embodiment. , and is filled with an insulating film 53 as an insulating material having a refractive index lower than that of the semiconductor layer 20 .
  • the first inter-pixel isolation region 31 is Light absorption can be suppressed, in other words, light reflection in the first inter-pixel separation region 31a can be increased, and the first photoelectric conversion region 21A including the first photoelectric conversion unit 24a that photoelectrically converts near-infrared light and visible Even when the second photoelectric conversion region 21B including the second photoelectric conversion portion 24b that photoelectrically converts light is mounted together, it is possible to improve the quantum efficiency QE and highly suppress color mixing (high MTF characteristics).
  • the in-pixel isolation region 32 of the third embodiment has a structure in which the recessed portion 33b extending in the thickness direction of the semiconductor layer 20 is filled with the conductive material 35, as in the first embodiment. ing.
  • the potential of the semiconductor layer 20 on the sidewall of the intra-pixel isolation region 32 is changed, resulting in photoelectric conversion.
  • the signal charges photoelectrically converted in the portion 24a are transferred to the floating diffusion region FD1, it can function as an assist electrode that assists the transfer of the signal charges to the floating diffusion region FD1, thereby improving transfer characteristics as pixel characteristics. can be planned. Therefore, in the solid-state imaging device 1C of the first embodiment as well, it is possible to improve the pixel characteristics.
  • the width of the inter-pixel isolation region 31 can be made finer in the solid-state imaging device 1C of the first embodiment as well.
  • Each of the photoelectric conversion regions 21A (pixels 3a) and the second photoelectric conversion regions 21B (pixels 3b) can be miniaturized.
  • the inter-pixel isolation region 31 and the intra-pixel A light-shielding film 54 having a selectively large width is provided so as to cover the floating diffusion regions FD1 and FD2 arranged between the separation region 32 and the isolation region 32 . Therefore, also in the solid-state imaging device 1C according to the third embodiment, PLS characteristics (parasitic light sensitivity characteristics) can be improved as in the solid-state imaging device 1A according to the above-described first embodiment.
  • the intra-pixel separation region 32 functioning as an assist electrode is provided in the first photoelectric conversion region 21A
  • the in-pixel separation region 32 functioning as an assist electrode may be provided in the second photoelectric conversion region 21B, or may be provided in both the first photoelectric conversion region 21A and the second photoelectric conversion region 21B.
  • the in-pixel separation region 32 functioning as an assist electrode is preferably provided in the first photoelectric conversion region 21A including the photoelectric conversion portion 24a that photoelectrically converts near-infrared light, as in the third embodiment.
  • This fourth embodiment incorporates the intra-pixel isolation regions 32 shown in FIGS. 4 and 5 of the above-described first embodiment into the above-described second embodiment.
  • a solid-state imaging device 1D includes a first inter-pixel isolation region 31a, a second inter-pixel isolation region 31b, an intra-pixel isolation region 32 and has.
  • the first inter-pixel isolation region 31a corresponds to a specific example of the "first isolation region" of the present technology
  • the second inter-pixel isolation region 31b is the "second isolation region” of the present technology.
  • the intra-pixel isolation region 32 corresponds to the third isolation region of the present technology.
  • the solid-state imaging device 1D includes the first photoelectric conversion regions 21A partitioned by the first inter-pixel isolation regions 31a and the second photoelectric conversion regions partitioned by the second inter-pixel isolation regions 31b. and a conversion area 21B.
  • the intra-pixel separation region 32 is provided in each of the first photoelectric conversion region 21A and the second photoelectric conversion region 21B.
  • the first photoelectric conversion region 21A basically has the same configuration as the first photoelectric conversion region 21A of the above-described second embodiment. That is, the first photoelectric conversion region 21A includes a p-type well region 22, an n-type semiconductor region 23, a floating diffusion region FD1, and a photoelectric conversion portion, similarly to the photoelectric conversion region 21 of the second embodiment described above. 24a, a transfer transistor TRG1 (see FIG. 8), an element forming region 20a, and a diffraction scattering portion 51.
  • FIG. The first photoelectric conversion region 21A of the fourth embodiment includes an intra-pixel isolation region 32. As shown in FIG. The intra-pixel isolation region 32 is provided apart from the first inter-pixel isolation region 31a.
  • the second photoelectric conversion region 21B basically has the same configuration as the photoelectric conversion region 21B of the second embodiment described above. That is, the second photoelectric conversion region 21B includes a p-type well region 22, an n-type semiconductor region 23, a floating diffusion region FD1, and a photoelectric conversion portion, similarly to the photoelectric conversion region 21 of the second embodiment described above. 24a, a transfer transistor TRG1 (see FIG. 8), an element forming region 20a, and a diffraction scattering portion 51.
  • the second photoelectric conversion region 21B of the fourth embodiment includes an intra-pixel separation region 32. As shown in FIG. The intra-pixel isolation region 32 is provided apart from the second inter-pixel isolation region 31b.
  • the conductive material 35 of the intra-pixel isolation region 32 included in the first photoelectric conversion region 21A is formed through the contact electrode 42b1 embedded over the interlayer insulating film 41 and the element isolation region 25. It is electrically connected to the wiring 43b1 of the wiring layer 43 of the first layer.
  • the conductive material 35 of the intra-pixel isolation region 32 included in the second photoelectric conversion region 21B is applied to the first layer via the contact electrode 42b1 embedded over the interlayer insulating film 41 and the element isolation region 25. is electrically connected to the wiring 43b1 of the wiring layer 43 of .
  • a positive second reference potential higher than the first reference potential applied to the p-type well region 22 is applied to these wirings 43b1 as the power supply potential in the same manner as in the first embodiment. be done. That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 43b1 through the contact electrode 42b1 , and is fixed at this second reference potential.
  • the conductive material 35 of the second inter-pixel isolation region 31b is connected to the wiring layer of the first layer via the contact electrode 42b2 embedded over the interlayer insulating film 41 and the element isolation region 25. It is electrically connected to the wiring 43b2 formed in 43.
  • a third reference potential which is a negative potential lower than the first reference potential applied to the p-type well region 22, is applied to the wiring 43b2 as a power supply potential in the same manner as in the above-described second embodiment. be. That is, the conductive material 35 of the second pixel isolation region 31b is supplied with the third reference potential applied to the wiring 43b2 through the contact electrode 42b2 , and is fixed at this second reference potential.
  • the solid-state imaging device 1D according to the fourth embodiment includes a first inter-pixel isolation region 31a corresponding to a specific example of the "first isolation region" of the present technology, and a A first photoelectric conversion region 21A, a second inter-pixel separation region 31b corresponding to a specific example of the “second separation region” of the present technology, and a second photoelectric conversion region 21B partitioned by the second pixel separation region 31b and has. Then, the first inter-pixel isolation region 31a is formed in a recessed portion 33a1 extending in the thickness direction (Z direction) of the semiconductor layer 20 in the same manner as the inter-pixel isolation region 31 of the second embodiment described above.
  • An insulating film 53 as an insulating material having a refractive index lower than 20 is filled. Therefore, as in the second embodiment described above, a first photoelectric conversion region 21A including a first photoelectric conversion unit 24a that photoelectrically converts near-infrared light and a second photoelectric conversion unit 24b that photoelectrically converts visible light are provided. Even when the second photoelectric conversion region 21B including the second photoelectric conversion region 21B is mixed, it is possible to improve the quantum efficiency QE and highly suppress color mixing (high MTF characteristics).
  • a recessed portion 33a2 extending in the thickness direction of the semiconductor layer 20 is filled with the conductive material 35 in the same manner as the intra-pixel isolation region 32 of the first embodiment described above. It is configured.
  • a second photoelectric conversion unit 24b is provided that photoelectrically converts visible light by applying a negative potential to the conductive material 35 of the second inter-pixel separation region 31b.
  • the saturated charge amount Qs in the two photoelectric conversion regions 21B can be increased, and the pixel characteristics can be improved.
  • the conductive material 35 is filled in the dug portion 33a2 extending in the thickness direction of the semiconductor layer 20 in the same manner as the second intra-pixel isolation region 32 of the above-described second embodiment. It is configured as Therefore, by applying a negative potential to the conductive material 35 of the second pixel isolation region 31b, the potential of the semiconductor layer 20 on the side wall of the second pixel isolation region 31b changes, and the second pixel photoelectric conversion potential of visible light is changed.
  • the saturated charge amount Qs in the second photoelectric conversion region 21B provided with the photoelectric conversion portion 24b can be increased, and the pixel characteristics can be improved. Therefore, in the solid-state imaging device 1D according to the fourth embodiment as well, it is possible to improve the pixel characteristics.
  • the width of the first pixel isolation region 31a can be made finer in the solid-state imaging device 1D according to the fourth embodiment as well.
  • miniaturization of each of the first photoelectric conversion region 21A and the second photoelectric conversion region 21B can be achieved.
  • the first inter-pixel isolation region 31a and the A light shielding film 54 is provided which is selectively widened so as to cover the floating diffusion regions FD1 and FD2 arranged between the in-pixel isolation regions 32 . Therefore, in the solid-state imaging device 1D according to the fourth embodiment as well, PLS characteristics (parasitic light sensitivity characteristics) can be improved as in the solid-state imaging device 1A according to the first embodiment.
  • the intra-pixel isolation regions 32 functioning as assist electrodes are provided in both the first and second photoelectric conversion regions 21A and 21B.
  • the in-pixel isolation region 32 functioning as an assist electrode may be provided in either one of the first and second photoelectric conversion regions 21A and 21B.
  • the intra-pixel separation region 32 functioning as an assist electrode is preferably provided in the first photoelectric conversion region 21A including the photoelectric conversion portion 24a that photoelectrically converts near-infrared light.
  • FIG. 14 is an equivalent circuit diagram showing one configuration example of a pixel of the solid-state imaging device according to the fifth embodiment of the present technology.
  • a solid-state imaging device 1E according to the fifth embodiment of the present technology includes pixels 60 illustrated in FIG. 14 . Although one pixel 60 is illustrated in FIG. 14, the pixel 60 is repeatedly arranged in each of the X direction and the Y direction in the same manner as the pixel 3 shown in FIG. 1 of the first embodiment, It constitutes a pixel array section.
  • the pixel 60 includes a photoelectric conversion portion (photoelectric conversion element PD) 61, a first transfer transistor (TRG) 62, a second transfer transistor (TRG) 63, a memory portion 64, a floating diffusion (FD ) region 65 , an amplifier transistor (AMP) 66 , a select transistor (SEL) 67 and a reset transistor (RST) 68 .
  • the memory unit 64 is a specific example of the “charge holding unit” of the present technology.
  • the photoelectric conversion unit 61 receives light irradiated to the pixels 60, generates and accumulates electric charges according to the light amount of the light.
  • the first transfer transistor 62 is driven according to the transfer signal supplied from the vertical drive section, and when the first transfer transistor 62 is turned on, the charge accumulated in the photoelectric conversion section 61 is transferred to the memory section 64. .
  • the second transfer transistor 63 is driven according to the transfer signal supplied from the vertical drive section, and when the second transfer transistor 63 is turned on, the signal charge accumulated in the memory section 64 is transferred to the floating diffusion region 65. be.
  • the memory unit 64 accumulates signal charges transferred from the photoelectric conversion unit 61 via the first transfer transistor 62 .
  • the floating diffusion region 65 is a floating diffusion region having a predetermined capacitance formed at the connection point between the second transfer transistor 63 and the gate electrode of the amplification transistor 66 . accumulates the signal charge transferred from The amplification transistor 66 is connected to the power supply line Vdd and outputs a pixel signal whose level corresponds to the signal charges accumulated in the floating diffusion region 65 .
  • the selection transistor 67 is driven in accordance with a selection signal supplied from the vertical driving section, and when the selection transistor 67 is turned on, the pixel signal output from the amplification transistor 66 can be read out to the vertical signal line 11 via the selection transistor 67. state.
  • the reset transistor 68 is driven according to a reset signal supplied from the vertical driving section. When the reset transistor 58 is turned on, the charges accumulated in the FD 55 are discharged to the power supply Vdd through the reset transistor 58, and the floating diffusion region is generated. 65 is reset.
  • the solid-state imaging device 1E having the pixels 60 configured in this way, a global shutter method is adopted, and signal charges can be transferred simultaneously from the photoelectric conversion units 61 to the memory units 64 for all the pixels 60.
  • the exposure timing of all pixels 60 can be made the same. This makes it possible to avoid distortion in the image.
  • a photoelectric conversion unit (photoelectric conversion element PD) 61, a first transfer transistor (TRG) 62, 2, a transfer transistor (TRG) 63, a memory section 64, a floating diffusion (FD) region 65, an amplification transistor (AMP) 66, a selection transistor (SEL) 67, and a reset transistor (RST) 68 are arranged in the pixel isolation region 31. It is mounted on the partitioned photoelectric conversion area 21 .
  • the photoelectric conversion region 21 is selectively separated into two regions having relatively different widths in the Y direction in plan view by an intra-pixel separation region 32 provided apart from the inter-pixel separation region 31 . ing. Of the two regions separated by the intra-pixel separation region 32, the photoelectric conversion unit 61 is provided in the region with the wider width in the Y direction, and the memory unit 54 is provided in the region with the narrower width in the Y direction. It is
  • the solid-state imaging device 1E according to the fifth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment.
  • FIG. 15 is an equivalent circuit diagram showing one configuration example of a pixel of a solid-state imaging device according to the sixth embodiment of the present technology.
  • a solid-state imaging device 1F according to the sixth embodiment of the present technology includes pixels 70 illustrated in FIG. 15 . Although one pixel 70 is illustrated in FIG. 15, the pixel 70 is repeatedly arranged in each of the X direction and the Y direction in the same manner as the pixel 3 shown in FIG. 1 of the first embodiment, It constitutes a pixel array section.
  • the solid-state imaging device 1F having this pixel 70 employs a charge domain type global shutter system.
  • the pixel 70 includes, for example, a photoelectric conversion portion (photoelectric conversion element PD) 71, a transfer transistor (TRG) 72, a floating diffusion (FD) region 73 as a charge holding portion and a charge-voltage conversion portion, a reset It includes a transistor (RST) 74, a feedback enable transistor (FBEN) 75, an ejection transistor (OFG) 76, an amplification transistor (AMP) 77, a select transistor (SEL) 78, and the like.
  • the floating diffusion region 73 corresponds to a specific example of the “charge holding portion” of the present technology.
  • the transfer transistor 72, the FD 73, the reset transistor 74, the feedback enable transistor 75, the discharge transistor 76, the amplification transistor P77, and the selection transistor 78 as pixel transistors are all n-channel conductivity type MOS transistors.
  • a drive signal is supplied to each gate electrode of these pixel transistors (72, 74, 75, 76, 77, 78).
  • Each drive signal is a pulse signal whose high level state is an active state, that is, an ON state, and whose low level state is an inactive state, that is, an OFF state. Note that hereinafter, setting the drive signal to the active state is also referred to as turning the drive signal on, and setting the drive signal to the inactive state is also referred to as turning the drive signal off.
  • the photoelectric conversion unit 71 is a photoelectric conversion element made up of, for example, a pn-junction photodiode, and receives light from a subject, and generates and accumulates charges according to the amount of light received by photoelectric conversion.
  • the transfer transistor 72 is connected between the photoelectric conversion portion 71 and the floating diffusion region 73, and transfers the signal charges accumulated in the photoelectric conversion portion 71 according to the drive signal applied to the gate electrode of the transfer transistor 72. is transferred to the floating diffusion region 73 .
  • the floating diffusion region 73 is a region that temporarily holds signal charges accumulated in the floating diffusion region 73 in order to realize a global shutter function.
  • the floating diffusion region 73 is also a floating diffusion region that converts the signal charge transferred from the photoelectric conversion unit 71 via the transfer transistor 72 into an electric signal (for example, a voltage signal) and outputs the electric signal.
  • a reset transistor 74 is connected to the floating diffusion region 73 , and the vertical signal line 11 is connected via an amplification transistor 77 and a selection transistor 78 .
  • the reset transistor 74 has a drain region connected to the feedback enable transistor 75 and a source region connected to the floating diffusion region FD73.
  • the reset transistor 74 initializes, ie resets, the floating diffusion region 73 according to the drive signal applied to its gate electrode.
  • the feedback enable transistor 75 controls the reset voltage applied to the reset transistor 74 .
  • the drain transistor 76 has a drain region connected to the power supply Vdd and a source region connected to the photoelectric conversion section 71 .
  • a cathode of the photoelectric conversion unit 71 is commonly connected to the source region of the discharge transistor 76 and the source region of the transfer transistor 72 .
  • the transfer transistor 76 initializes, ie resets, the photoelectric conversion section 71 according to the drive signal applied to its gate electrode. “Resetting the photoelectric conversion unit 71” means depleting the photoelectric conversion unit 71. As shown in FIG.
  • the amplification transistor 77 has a gate electrode connected to the floating diffusion region 73 and a drain region connected to the power supply Vdd, and is a source follower circuit for reading signal charges obtained by photoelectric conversion in the photoelectric conversion section 71. becomes the input part of That is, the amplification transistor 77 forms a source follower circuit together with a constant current source connected to one end of the vertical signal line 11 by connecting the source region to the VSL 117 via the selection transistor 78 .
  • the selection transistor 78 is connected between the source region of the amplification transistor 77 and the vertical signal line 11, and the gate electrode of the selection transistor 78 is supplied with a selection signal.
  • the selection transistor 78 becomes conductive when its selection signal is turned on, and the pixel 70 provided with the selection transistor 78 is selected.
  • the pixel signal output from the amplifying transistor 77 is read out by the column signal processing circuit 5 (see FIG. 2) through the vertical signal line 11 .
  • a plurality of pixel driving lines 10 are wired, for example, for each pixel row.
  • Each drive signal is supplied to the selected pixel 70 from the vertical drive circuit section 4 through the plurality of pixel drive lines 10 .
  • the solid-state imaging device 1F having the pixels 70 configured in this manner a global shutter method is adopted, and signal charges are simultaneously transferred from the photoelectric conversion units 71 to the floating diffusion (FD) regions 73 for all the pixels 70. , and the exposure timing of all the pixels 70 can be made the same. This makes it possible to avoid distortion in the image.
  • FD floating diffusion
  • region 73 region 73 , reset transistor (RST) 74 , feedback enable transistor (FBEN) 75 , discharge transistor (OFG) 76 , amplification transistor (AMP) 77 , and selection transistor (SEL) 78 are partitioned by pixel separation region 31 . It is mounted on the photoelectric conversion region 21 .
  • the photoelectric conversion region 21 is selectively separated into two regions having relatively different widths in the Y direction in plan view by an intra-pixel separation region 32 provided apart from the inter-pixel separation region 31 . ing.
  • the photoelectric conversion unit 71 is provided in the region with the wider width in the Y direction, and the floating diffusion (FD) is provided in the region with the narrower width in the Y direction.
  • a region 73 is provided.
  • the solid-state imaging device 1F according to the sixth embodiment can also obtain the same effects as the solid-state imaging device 1A according to the first embodiment.
  • FIG. 16 is an equivalent circuit diagram showing one configuration example of a pixel of the solid-state imaging device according to the seventh embodiment of the present technology.
  • a solid-state imaging device 1G according to the seventh embodiment of the present technology includes pixels 90 illustrated in FIG. 16 . Although one pixel 90 is illustrated in FIG. 16, the pixel 90 is repeatedly arranged in each of the X direction and the Y direction in the same manner as the pixel 3 shown in FIG. 1 of the first embodiment, It constitutes a pixel array section.
  • the solid-state imaging device 1G having this pixel 90 employs a voltage domain global shutter method.
  • the pixel 90 includes a front-stage circuit 110 , capacitive elements 121 and 122 , a selection circuit 130 , a rear-stage reset transistor 141 , and a rear-stage circuit 150 .
  • the front-stage circuit 110 includes a photoelectric conversion unit (PD) 111, a transfer transistor (TRG) 112, a reset transistor (RST) 113a, a switching transistor (FDG) 113b, a floating diffusion region (FD) 114, a front-stage amplification transistor (AMP) 115a, A pre-stage selection transistor 115 b and a current source transistor 116 are provided.
  • the floating diffusion region (FD) 114 corresponds to a specific example of the "charge holding section" of the present technology.
  • the photoelectric conversion unit 111 generates charges by photoelectric conversion.
  • the transfer transistor 112 transfers charges from the photoelectric conversion section 111 to the floating diffusion region 114 according to the transfer signal trg from the vertical drive circuit 4 (see FIG. 2).
  • the reset transistor 113 extracts signal charges from the floating diffusion region 114 in accordance with the FD reset signal rst from the vertical drive circuit 4 for initialization.
  • the floating diffusion region 114 accumulates charges and generates a voltage corresponding to the amount of charges.
  • the front-stage amplification transistor 115 a amplifies the voltage level of the floating diffusion region 114 and outputs it to the front-stage node 120 .
  • the source regions of the reset transistor 113 and the pre-amplification transistor 115 are connected to the power supply voltage Vdd.
  • the current source transistor 116 is connected to the drain region of the pre-amplification transistor 115a. This current source transistor 116 supplies the current id1 under the control of the vertical drive circuit 4 .
  • each of the capacitive elements 121 and 122 is commonly connected to the preceding node 120 and the other end of each is connected to the selection circuit 130 .
  • the selection circuit 130 includes selection transistors 131 and 132 .
  • the selection transistor 131 opens and closes the path between the capacitive element 121 and the subsequent node 140 according to the selection signal ⁇ r from the vertical drive circuit 4 .
  • the selection transistor 132 opens and closes the path between the capacitive element 122 and the subsequent node 140 according to the selection signal ⁇ s from the vertical drive circuit 4 .
  • the post-stage reset transistor 141 initializes the level of the post-stage node 140 to a predetermined potential Vreg according to the post-stage reset signal rstb from the vertical drive circuit 4 .
  • the potential Vreg is set to a potential different from the power supply potential Vdd (for example, a potential lower than Vdd).
  • the post-stage circuit 150 includes a post-stage amplification transistor 151 and a post-stage selection transistor 152 .
  • the post-amplification transistor 151 amplifies the level of the post-stage node 140 .
  • the rear-stage selection transistor 152 outputs a signal having a level amplified by the rear-stage amplification transistor 151 as a pixel signal to the vertical signal line 11 (see FIG. 2) according to the rear-stage selection signal selb from the vertical drive circuit 4 .
  • the vertical drive circuit 4 of this embodiment supplies high-level FD reset signal rst and transfer signal trg to all pixels at the start of exposure. Thereby, the photoelectric conversion unit 111 is initialized.
  • this control will be referred to as "PD reset”.
  • the vertical drive circuit 4 supplies the high-level FD reset signal rst over the pulse period while setting the post-stage reset signal rstb and the selection signal ⁇ r to high level for all pixels.
  • the floating diffusion region 114 is initialized, and the capacitive element 121 holds a level corresponding to the level of the floating diffusion region 114 at that time.
  • This control is hereinafter referred to as "FD reset".
  • the level of the floating diffusion region 114 at the time of FD reset and the level corresponding to that level (holding level of the capacitive element 121 and level of the vertical signal line 11) are collectively referred to as “P phase” or “reset level”. ”.
  • the vertical drive circuit 4 supplies a high-level transfer signal trg over the pulse period while setting the post-stage reset signal rstb and the selection signal ⁇ s to a high level for all pixels.
  • signal charges corresponding to the amount of exposure are transferred to the floating diffusion region 114 , and a level corresponding to the level of the floating diffusion region 114 at that time is held in the capacitive element 122 .
  • phase D The level of the floating diffusion region 114 during signal charge transfer and the level corresponding to that level (the holding level of the capacitive element 122 and the level of the vertical signal line 11) are collectively referred to as "phase D” or “phase D” below. signal level”.
  • Exposure control that simultaneously starts and ends exposure for all pixels in this way is called a global shutter method.
  • the pre-stage circuits 110 of all pixels sequentially generate a reset level and a signal level.
  • the reset level is held in the capacitor 121 and the signal level is held in the capacitor 122 .
  • the vertical drive circuit 4 sequentially selects rows and sequentially outputs the reset level and signal level of the rows.
  • the vertical drive circuit 4 supplies the high-level selection signal ⁇ r for a predetermined period while setting the FD reset signal rst and the post-selection signal selb of the selected row to high level.
  • the capacitive element 121 is connected to the post-stage node 140, and the reset level is read.
  • the vertical drive circuit 4 After reading the reset level, the vertical drive circuit 4 supplies the high-level post-stage reset signal rstb over the pulse period while keeping the FD reset signal rst and the post-stage selection signal selb of the selected row at high level. As a result, the level of the subsequent node 140 is initialized. At this time, both the selection transistor 331 and the selection transistor 132 are open, and the capacitive elements 121 and 122 are disconnected from the subsequent node 140 .
  • the vertical drive circuit 4 After the initialization of the rear-stage node 140, the vertical drive circuit 4 supplies the high-level selection signal ⁇ s for a predetermined period while keeping the FD reset signal rst and the rear-stage selection signal selb of the selected row at high level. Thereby, the capacitive element 122 is connected to the post-stage node 140, and the signal level is read.
  • the selection circuit 130 of the selected row performs control to connect the capacitive element 121 to the subsequent node 140, to disconnect the capacitive elements 121 and 122 from the subsequent node 140, and to connect the capacitive element 122 to the subsequent node 140. and control to connect to .
  • post-stage reset transistor 141 in the selected row initializes the level of post-stage node 140 .
  • the post-stage circuit 150 in the selected row sequentially reads the reset level and the signal level from the capacitive elements 121 and 122 via the post-stage node 140 and outputs them to the vertical signal line 11 .
  • region 114 is mounted on the photoelectric conversion region 21 partitioned by the inter-pixel separation region 31 .
  • the photoelectric conversion region 21 is selectively separated into two regions having relatively different widths in the Y direction in plan view by an intra-pixel separation region 32 provided apart from the inter-pixel separation region 31 . ing. Then, of the two regions separated by the intra-pixel separation region 32, the photoelectric conversion unit 111 is provided in the region with the wider width in the Y direction, and the floating diffusion (FD) is provided in the region with the narrower width in the Y direction.
  • FD floating diffusion
  • the solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1A according to the above-described first embodiment.
  • FIG. 17 is a plan view schematically showing the plane pattern of the light blocking member in the pixel array section of the solid-state imaging device according to the eighth embodiment.
  • 18 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a17-a17 of FIG. 17.
  • FIG. 19 is a partially enlarged plan view of FIG. 18.
  • FIG. FIG. 20 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a19-a19 of FIG. 17 and 19 are plan views viewed from the second surface S2 side (light incident surface side) of the semiconductor layer 20 shown in FIGS. 18 and 20.
  • FIG. 18 and 20 are upside down with respect to FIGS. 5 and 6 of the above-described first embodiment.
  • a solid-state imaging device 1H according to the eighth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, and differs in the following configurations.
  • the solid-state imaging device 1H according to the eighth embodiment of the present technology includes a light shielding body 80H instead of the light shielding film 54 shown in FIGS. 4 and 5 of the first embodiment. It has Other configurations are generally similar to those of the first embodiment, and similar configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the light shielding body 80H of the eighth embodiment is provided on the second surface S2 side of the semiconductor layer 20, and in plan view, the second region 21b of the photoelectric conversion region 21 and the It overlaps with each of the floating diffusion regions FD in the second region 21b.
  • the light shield 80H is provided inside and outside the second region 21b in the thickness direction (Z direction) of the semiconductor layer 20. As shown in FIG.
  • the light shielding body 80H includes first linear portions 81x that extend in the X direction and are repeatedly arranged in the Y direction at a predetermined arrangement pitch. and second linear portions 81y extending in the X direction and repeatedly arranged at a predetermined arrangement pitch.
  • the first linear portion 81x overlaps the first portion 31x of the pixel separation region 31 in plan view
  • the second linear portion 81y overlaps the second portion 31y of the pixel separation region 31 in plan view. That is, the light shielding body 80H of the eighth embodiment also prevents light incident on a predetermined photoelectric conversion region 21 from leaking into the adjacent photoelectric conversion region 21, similarly to the light shielding film 54 of the first embodiment.
  • the planar pattern is a grid-like planar pattern in which the light-receiving surface side (second surface S2 side) of each of the plurality of photoelectric conversion regions 21 is opened.
  • the width Xwy of the first linear portion 81x in the Y direction is wider than the width Ywx of the second linear portion 81y in the X direction.
  • the light shielding body 80H is provided outside the second surface S2 of the semiconductor layer 20 and overlaps the second region 21b of the photoelectric conversion region 21 in plan view.
  • a light shielding portion 82a and a second light shielding portion 82b projecting from the first light shielding portion 82a into the second region 21b of the photoelectric conversion region 21 are provided.
  • the first light shielding portion 82a and the second light shielding portion 82b are formed in the first linear portion 81x.
  • the first linear portion 81x includes the first light shielding portion 82a and the second light shielding portion 82b.
  • the intra-pixel isolation region 32 extends, for example, in the X direction in plan view and is separated from the inter-pixel isolation region 31 (the first portion 31x and the second portion 31y). are provided.
  • the intra-pixel separation region 32 is arranged so as to be closer to the inter-pixel separation region 31 side than the central portion of the photoelectric conversion region 21 in plan view, and the photoelectric conversion region 21 has a width in the Y direction in plan view. is selectively separated (partitioned) into two relatively different regions (first region 21a and second region 21b).
  • the first region 21a having the wider width in the Y direction is provided with the photoelectric conversion unit 24.
  • a floating diffusion region FD is provided in the second region 21b having a narrower width in the direction. That is, the intra-pixel separation region 32 separates the photoelectric conversion region 21 into a first region 21a and a second region 21b in one direction (Y direction).
  • the second light shielding portion 82b crosses the second surface S2 of the semiconductor layer 20 in the thickness direction (Z direction) of the semiconductor layer 20. As shown in FIG. The second light shielding portion 82b is separated from each of the inter-pixel isolation regions 31 and the intra-pixel isolation regions 32 in the arrangement direction (Y direction) of the first regions 21a and the second regions 21b.
  • the second light shielding portion 82b is provided inside the dug portion 33h provided over the insulating film 53 and the semiconductor layer 20 via the insulating film 33h1 .
  • the insulating film 33h1 is provided mainly for the purpose of electrically isolating the second light shielding portion 82b and the semiconductor layer 20 from each other. Although the insulating film 33h1 is provided from the insulating film 53 to the semiconductor layer 20 in FIG. 20, the insulating film 33h1 may be provided only on the semiconductor layer 20 side.
  • the first light shielding portion 82a is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the second light shielding portion 82b penetrates the insulating film 53 and reaches the inside of the second region 21b (inside the semiconductor layer 20).
  • the light shielding body 80H extends over two photoelectric conversion regions 21 adjacent to each other in the X direction within a two-dimensional plane, although not limited to this.
  • the first light shielding portion 82a also extends continuously across two photoelectric conversion regions 21 adjacent to each other in the X direction.
  • the second light shielding portion 82b is provided separately for each photoelectric conversion region 21 arranged in the X direction. That is, unlike the first light shielding portion 82a, the second light shielding portion 82b does not extend continuously across two photoelectric conversion regions 21 adjacent to each other in the Y direction.
  • the second light shielding portion 82b extends in the X direction along with the intra-pixel isolation region 32 in plan view.
  • the X-direction length of the second light shielding portion 82b is preferably equal to or longer than the X-direction length of the intra-pixel isolation region 32 .
  • the X-direction length of the second light shielding portion 82b is longer than the X-direction length of the intra-pixel isolation region 32. As shown in FIG.
  • the first light shielding portion 82a mainly blocks light outside the second surface S2 of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21, and is provided on the first surface S1 side of the semiconductor layer 20. Restricts light from reaching the floating diffusion region FD.
  • the second light shielding portion 82b blocks light inside the second surface S2 side of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21, and is provided on the first surface S1 side of the semiconductor layer 20. Restricts light from reaching the floating diffusion region FD.
  • the light blocking member 80H blocks light entering (incident) into the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20, Reaching of light to the floating diffusion region FD provided on the first surface S1 side of the layer 20 is suppressed.
  • a metal film such as titanium (Ti), tungsten (W), aluminum (Al), or an alloy thereof is used as a material having excellent light shielding properties and light reflectance higher than that of a silicon oxide film or a silicon film. It is preferred to use membranes.
  • a tungsten (W) film for example, is used as the light shield 80H.
  • the inter-pixel isolation region 31, the intra-pixel isolation region 32, and the floating diffusion region FD are the “first isolation region”, the “second isolation region”, and the “charge holding portion” of the present technology. correspond respectively to
  • the photoelectric conversion region 21, the element isolation region 25, the dug portion 33a, the in-pixel isolation region 32, and the like are formed in the semiconductor layer 20, and the semiconductor layer 20 is formed on the first surface S1 side.
  • a multilayer wiring layer 40 is formed.
  • the intra-pixel isolation region 32 is composed of an isolation insulating film 34 provided along the inner side wall of a dug portion 33b extending in the depth direction (Z direction) of the semiconductor layer 20, and an isolation insulating film on the dug portion 33b. and a conductive material 35 filled through 34 .
  • the dug portion 33a is the base of the inter-pixel isolation region 31 shown in FIG. 22F.
  • the dug portion 33a extends in the depth direction (Z direction) of the semiconductor layer 20, similarly to the dug portion 33b of the intra-pixel isolation region 32, and has a conductive material 35 inside it via the isolation insulating film 34. is filled.
  • the dug portion 33 a partitions the photoelectric conversion regions 21 into individual photoelectric conversion regions 21 .
  • the dug portions 33a and 33b are formed, for example, in the same process.
  • the photoelectric conversion region 21 is formed in an element formation region 20a, a p-type well region 22, an n-type semiconductor region 23, a photoelectric conversion portion 24 (PD), an element isolation region (field isolation region) 25, and an element formation region 20a. and pixel transistors (AMP, SEL, RST, TR).
  • the photoelectric conversion region 21 includes a floating diffusion region FD, an intra-pixel separation region 32, and a first region 21a and a second region 21b separated by the intra-pixel separation region 32.
  • FIG. A p-type well region 22 is formed in the first region 21 a and the second region 21 b of the photoelectric conversion region 21 .
  • the element forming region 20a, the n-type semiconductor region 23, and the photoelectric conversion portion 24 are formed in the first region 21a of the photoelectric conversion region 21.
  • the floating diffusion region FD is formed on the first surface S1 side of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 .
  • the semiconductor layer 20 although not limited to this, for example, a p-type semiconductor substrate made of single crystal silicon is used.
  • the thickness of the semiconductor layer 20 is reduced by cutting the side of the second surface S2 of the semiconductor layer 20 by, for example, CMP. 22B, the intra-pixel isolation region 32 is exposed from the second surface S2 of the semiconductor layer 20, and the isolation insulating film 34 and the conductive material 35 in the dug portion 33a are exposed.
  • a diffraction scattering portion 51 is formed on the second surface S2 of the semiconductor layer 20 in the first region 21a.
  • the isolation insulating film 34 and the conductive material 35 in the dug portion 33a are selectively removed.
  • the isolation insulating film 34 and the conductive material 35 in the dug portion 33a can be selectively removed by using well-known photolithography technology and anisotropic dry etching technology.
  • a fixed charge film 52 is formed to cover the second surface S2.
  • the fixed charge film 52 is formed over the first region 21a and the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20. Covered with membrane 52 .
  • an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the inside of the dug portion 33a.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by a CVD method and then planarizing the surface side of the silicon oxide film by cutting it by a CMP method.
  • the inter-pixel isolation region 31 in which the insulating film 53 is embedded through the fixed charge film 52 is formed inside the dug portion 33a, and the inter-pixel isolation region 31 partitions the periphery and the interior. is separated into a first region 21a and a second region 21b by the intra-pixel separation region 32 to form the photoelectric conversion region 21.
  • An insulating film 33h1 is formed to cover the inner wall (side wall and bottom wall) of 33a.
  • the dug portion 33h can be formed by using well-known photolithography technology and anisotropic dry etching technology.
  • a silicon oxide film for example, can be used as the insulating film 33h1 , and this silicon oxide film can be formed by a deposition method or a thermal oxidation method.
  • a light shielding film 82 is formed on the entire surface of the insulating film 53 including the inside of the dug portion 33h.
  • the light-shielding film 82 is, for example, a metal film or an alloy film such as titanium (Ti), tungsten (W), aluminum (Al), etc., which has excellent light-shielding properties and has a higher light reflectance than a silicon oxide film or a silicon film. can be formed by forming a film by a well-known film forming technique.
  • the light shielding film 82 is formed over the plurality of photoelectric conversion regions 21, covers the first regions 21a and the second regions 21b of the plurality of photoelectric conversion regions 21 in a plan view, and covers the second regions 21b of the respective second regions 21b.
  • the dug portion 33h1 is formed so as to be embedded.
  • the light shielding film 82 in the embedded portion 33h is formed through the insulating film 33h.
  • the light shielding film 82 is patterned to cover the second region 21b of the photoelectric conversion region 21 and the floating diffusion region FD as shown in FIG. 22I, and in the thickness direction (Z direction) of the semiconductor layer 20, A light blocking body 80H is formed extending over the inside and outside of the second region 21b. Patterning of the light shielding film 82 can be performed using well-known photolithography technology and anisotropic dry etching technology.
  • the light shielding member 80H is formed on the insulating film 53 outside the second region 21b of the photoelectric conversion region 21 (outside the first surface S1 of the semiconductor layer 20) in the thickness direction (Z direction) of the semiconductor layer 20. and a first light shielding portion 82a that overlaps the second region 21b and the floating diffusion region FD in a plan view; and a second light shielding portion 82b projecting inside the region 21b.
  • the light shielding body 80H includes first linear portions 81x extending in the X direction and repeatedly arranged at a predetermined arrangement pitch in the Y direction, and the first linear portions 81x.
  • the light shield 80 ⁇ /b>H is formed in a lattice planar pattern that overlaps the lattice planar pattern of the inter-pixel isolation region 31 in plan view.
  • the first light shielding portion 82a and the second light shielding portion 82b are formed in the first linear portion 81x.
  • the color filter 55 and the microlens 56 are formed in this order on the side of the light shielding body 80H opposite to the semiconductor layer 20 side. Become.
  • the solid-state imaging device 1H is in the state of the semiconductor chip 2 shown in FIG. 1 by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 into each chip formation region.
  • FIG. 21B As shown in FIG. 21B, in one photoelectric conversion region 21 (one pixel 3), irradiation light 57H with which the microlens 56 is irradiated becomes oblique light 57H1 , and the microlens 56, the color filter 55, and the insulating film 53, penetrates (enters) the first region 21a (photoelectric conversion portion 24 (PD)) of the photoelectric conversion region 21 from the second surface S2 of the semiconductor layer 20 through the fixed charge film 52, the diffraction scattering portion 51, and the like. .
  • the oblique light 57H1 that has entered the first region 21a hits (irradiates) the intra-pixel isolation region 32 from the first region 21a side.
  • the oblique light 57H1 impinging on the intra-pixel isolation region 32 includes oblique light that is reflected by the intra-pixel isolation region 32 and returns to the first region 21a of the photoelectric conversion region 21, and transmitted through the intra-pixel isolation region 32 for photoelectric conversion. There is also oblique light that enters the second region 21b of the region 21 .
  • the intra-pixel isolation region 32 including a silicon film as the conductive material 35 the silicon film has poor light-shielding properties, so there is concern that the oblique light 57H1 may enter the second region 21b.
  • the second light shielding portion shown in FIG. 21B of the eighth embodiment is similar to the light shielding film 54 shown in FIG. 82b, the oblique light 57H1 entering the second region 21b of the photoelectric conversion region 21 reaches the floating diffusion region FD provided on the first surface S1 side of the semiconductor layer 20 in the second region 21b. do. Since the arrival of the oblique light 57H1 to the floating diffusion region FD affects the parasitic light sensitivity characteristic, it is important to suppress the oblique light from entering the second region 21b as much as possible.
  • the light shielding member 80H of the eighth embodiment has a second light shielding portion 82b projecting from the first light shielding portion 82a into the second region 21b. Therefore, the oblique light 75a transmitted through the intra-pixel isolation region 32 from the first region 21a side of the photoelectric conversion region 21 is reflected by the second light shielding portion 82b and returns to the first region 21a. That is, the light blocking member 80H of the eighth embodiment blocks the oblique light 75H1 transmitted through the intra-pixel separation region 32 from the first region 21a side of the photoelectric conversion region 21 by the second light blocking portion 82b, thereby blocking the floating diffusion region FD. It is possible to suppress the oblique light 75H1 from reaching the .
  • the quantum efficiency QE can also be improved.
  • the first region 21a of one photoelectric conversion region 21X 1 The oblique light 57H2 transmitted through the inter-pixel separation region 31 from the side is reflected by the second light shielding portion 82b of the light shielding body 80H in the second region 21b of the other photoelectric conversion region 21X2 , and Return to the first region 21a (photoelectric conversion unit 24 (FD)). Therefore, it is possible to further improve the quantum efficiency.
  • the light shield 80H of the eighth embodiment is provided outside the second surface S2 of the semiconductor layer 20 and overlaps the second region 21b of the photoelectric conversion region 21 in plan view. Since the first light shielding portion 82a is also provided, like the light shielding film 54 of the above-described first embodiment, the light from the second surface S2 of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 to the second region 21b is also provided. The first light shielding portion 82a blocks the light entering the floating diffusion region FD, thereby suppressing the arrival of the light to the floating diffusion region FD.
  • the solid-state imaging device 1H according to the eighth embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32, like the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1H according to the eighth embodiment, similarly to the solid-state imaging device 1A according to the first embodiment, improvement of the quantum efficiency QE as a pixel characteristic and high color mixture suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixture suppression
  • the light shielding body 80H of the eighth embodiment has a first light shielding portion 82a provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have.
  • first light shielding portion 82a provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have.
  • the first light shielding device similarly to the solid-state imaging device 1A of the first embodiment described above, light entering the second region 21b from the second surface S2 of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 is blocked by the first light shielding device.
  • Light is blocked by the portion 82a, light reaching the floating diffusion region FD can be suppressed, and the parasitic light sensitivity characteristic (PLS) can be improved.
  • PLS parasitic light sensitivity characteristic
  • the light shielding member 80H of the eighth embodiment includes a second light shielding portion 82b projecting inside the second region 21b of the photoelectric conversion region 21 from the first light shielding portion 82a. Therefore, the oblique light 75H1 transmitted through the intra-pixel isolation region 32 from the first region 21a side of the photoelectric conversion region 21 is blocked by the second light shielding portion 82b, thereby suppressing the arrival of the oblique light 75H1 to the floating diffusion region FD. It is possible to further improve the parasitic light sensitivity characteristic (PLS) together with the effect of improving the parasitic light sensitivity characteristic by the first light shielding portion 82a.
  • PLS parasitic light sensitivity characteristic
  • the oblique light 75H1 transmitted through the intra-pixel isolation region 32 from the first region 21a side is reflected by the second light shielding portion 82b and returns to the first region 21a, it is possible to improve the quantum efficiency QE.
  • the pixel separation region 31 is The oblique light 57H2 transmitted through the other photoelectric conversion region 21X2 is reflected by the second light shielding portion 82b of the light shielding member 80H in the second region 21b of the other photoelectric conversion region 21X2 , and is reflected by the first region 21a (photoelectric conversion Return to section 24 (FD)). Therefore, according to the solid-state imaging device 1H according to the eighth embodiment, it is possible to further improve the quantum efficiency QE together with the effect of the quantum efficiency QE due to the light reflection of the inter-pixel separation region 31 .
  • the oblique light 57H2 transmitted through the inter-pixel isolation region 31 from the first region 21a side of one photoelectric conversion region 21X1 is transferred to one photoelectric conversion region 21X. Since it can be returned to the first region 21a of 1 , it is possible to further suppress color mixing together with the effect of suppressing color mixing due to the light reflection of the inter-pixel separation region 31 .
  • the effect of suppressing oblique light (57H 1 , 57H 2 ) from reaching the floating diffusion region FD is that the second light shielding portion 82b moves from the first light shielding portion 82a to the second region 21b ( Of the total length L1 up to the tip protruding into the semiconductor layer 20), it is mainly dependent (proportional) to the embedding length L2 of the second light shielding portion 82b embedded inside the second region 21b.
  • the overall length L1 and width W1 in the Y direction of the second light shielding portion 82b affect the manufacturing yield.
  • the overall length L 1 in the Z direction or the embedded length L 2 of the second light shielding portion 82b is determined in consideration of the effect of suppressing oblique light (57H 1 , 57H 2 ) from reaching the floating diffusion region FD and the manufacturing yield. It is preferable that the semiconductor layer 20 is separated from the floating diffusion region FD by a half or more of the thickness of the semiconductor layer 20 .
  • the second light shielding portion 82b is separated from each of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 in the Y direction. and at least one of the intra-pixel isolation region 32 .
  • the first light shielding portion 82a having a constant width in the Y direction and extending in the X direction was described as the configuration of the light shielding body 80H.
  • the present technology is not limited to the eighth embodiment described above.
  • the Y-direction width Xwy of the first light shielding portion 82a may be partially narrowed. In this case, it is preferable to narrow the width Xwy in the Y direction in the portion where the first light shielding portion 82a does not overlap the floating diffusion region FD in plan view.
  • the light shielding body 80H including the first straight portion 81x and the second straight portion 81y, and the first light shielding portion 82a and the second light shielding portion 82b has been described.
  • the present technology is not limited to the eighth embodiment described above.
  • the first straight portion 81x and the second straight portion 81y may be omitted, and the first light shielding portion 82a and the second light shielding portion 82b alone may be included. .
  • FIG. 27 is a plan view schematically showing the plane pattern of the light blocking member in the pixel array section of the solid-state imaging device according to the ninth embodiment.
  • 28 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a27-a27 of FIG. 27.
  • FIG. 27 is a plan view of the semiconductor layer 20 shown in FIG. 28 as viewed from the second surface S2 side (light incident surface side). 28 is upside down with respect to FIGS. 5 and 6 of the above-described first embodiment.
  • a solid-state imaging device 1I according to the ninth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, but differs in the following configurations.
  • the solid-state imaging device 1I according to the ninth embodiment of the present technology includes a light shielding body 80I instead of the light shielding film 54 shown in FIGS. 5 and 6 of the first embodiment. It has In relation to this light shield 80I, the length L 5 (see FIG. 29B) of the intra-pixel isolation region 32 in the Z direction is shorter than the length of the inter-pixel isolation region 31 in the Z direction. In other words, in the in-pixel isolation region 32 of the ninth embodiment, the length L5 extending from the first surface S1 side of the semiconductor layer 20 to the second surface S2 side is the same as that of the first embodiment described above. It is shorter than the intra-pixel isolation region 32 shown in FIGS. Other configurations are generally the same as those of the first embodiment, and similar configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the light shielding member 80I of the ninth embodiment is provided on the second surface S2 side of the semiconductor layer 20, and has the second region 21b of the photoelectric conversion region 21 and the floating region in plan view. It overlaps with the diffusion area FD.
  • the light shielding member 80I overlaps the in-pixel isolation region 32 in a plan view, and is provided on the inside and outside of the semiconductor layer 20 on the second surface S2 side of the semiconductor layer 20 .
  • the light shielding member 80I is arranged in the X direction. and a first linear portion 81x repeatedly arranged at a predetermined arrangement pitch in the Y direction; and a second linear portion 81y arranged.
  • the first linear portion 81x overlaps the first portion 31x of the pixel separation region 31 in plan view
  • the second linear portion 81y overlaps the second portion 31y of the pixel separation region 31 in plan view.
  • the light shielding member 80I of the ninth embodiment also prevents the light incident on a predetermined photoelectric conversion region 21 from leaking into the adjacent photoelectric conversion region 21, similarly to the light shielding member 80H of the eighth embodiment.
  • the planar pattern is a grid-like planar pattern in which the light-receiving surface side (second surface S2 side) of each of the plurality of photoelectric conversion regions 21 is opened.
  • the width Xwy of the first linear portion 81x in the Y direction is wider than the width Ywx of the second linear portion 81y in the X direction.
  • the light shielding body 80I is provided outside the second surface S2 of the semiconductor layer 20, and the second region 21b of the photoelectric conversion region 21 and the floating diffusion region FD in plan view. and a second light shielding portion 82c that overlaps the in-pixel isolation region 32 in plan view and protrudes into the semiconductor layer 20 from the first light shielding portion 82a.
  • the first light shielding portion 82a and the second light shielding portion 82c are formed in the first linear portion 81x.
  • the first linear portion 81x of the ninth embodiment includes the first light shielding portion 82a and the second light shielding portion 82c.
  • the second light shielding portion 82c is fixed in a recessed portion 33i as a third recessed portion extending from the second surface S2 side of the semiconductor layer 20 toward the intra-pixel isolation region 32. It is provided through the charge film 52 .
  • the length L5 in the Z direction along the thickness direction of the semiconductor layer 20 is longer than the length of the inter-pixel isolation region 31 in the Z direction. It's getting shorter.
  • the Z-direction length L5 of the intra-pixel isolation region 32 of the ninth embodiment is shorter than the Z-direction length of the intra-pixel isolation region 32 of the first embodiment.
  • the in-pixel isolation region 32 of the ninth embodiment extends from the element isolation region 25 on the first surface S1 side of the semiconductor layer 20 toward the second surface S2 side, and extends from the second surface S2 side of the semiconductor layer 20 . is separated from the surface S2 of .
  • the dug portion 33i crosses the second surface S2 of the semiconductor layer 20 from the upper surface of the insulating film 53 opposite to the semiconductor layer 20 to reach the tip of the in-pixel isolation region 32. are doing.
  • the second light shielding portion 82c extends from the first light shielding portion 82a toward the tip of the intra-pixel isolation region 32 and is provided inside the dug portion 33i with the fixed charge film 52 interposed therebetween.
  • the fixed charge film 52 in the dug portion 33i is provided along the sidewall and bottom wall of the dug portion 33i.
  • the fixed charge film 52 on the side wall of the dug portion 33i electrically insulates and isolates the semiconductor layer 20 from the second light blocking portion 82c of the light blocking body 80I.
  • the fixed charge film 52 on the bottom wall of the dug portion 33i electrically insulates and separates the second light shielding portion 82c of the light shielding body 80I and the conductive material 35 of the intra-pixel isolation region 32 from each other.
  • the intra-pixel isolation region 32 of the ninth embodiment extends from the element isolation region 25 to the dug portion 33i.
  • the length L5 of the intra-pixel isolation region 32 is the distance from the bottom surface of the element isolation region 25 to the dug portion 33i.
  • the cut portion 33i extends from the first surface S1 of the semiconductor layer 20 to the dug portion 33i. is the length L5 of the intra-pixel isolation region 32 .
  • the surface of the semiconductor layer 20 in contact with the bottom surface of the element isolation region (field isolation region) 25 can also be regarded as the first surface S1.
  • the intra-pixel separation region 32 and the dug portion 33i have widths (W 2 , W 3 ) are different.
  • the width W2 of the recessed portion 33i is wider than the width W3 of the intra-pixel isolation region 32, but the width W3 of the intra-pixel isolation region 32 is recessed. It may be wider than the width W2 of the portion 33i. That is, from the viewpoint of patterning accuracy and characteristics, it is preferable to satisfy "W 2 >W 3 " or "W 2 ⁇ W 3 ".
  • the light shielding body 80I extends over two photoelectric conversion regions 21 adjacent to each other in the X direction within a two-dimensional plane, although not limited to this.
  • the first light shielding portion 82a also extends continuously across two photoelectric conversion regions 21 adjacent to each other in the X direction.
  • the second light shielding portion 82c is provided separately for each photoelectric conversion region 21 arranged in the X direction. That is, unlike the first light shielding portion 82a, the second light shielding portion 82c does not extend continuously over two photoelectric conversion regions 21 adjacent to each other in the Y direction.
  • the second light shielding portion 82c extends in the X direction along with the intra-pixel isolation region 32 in plan view.
  • the X-direction length of the second light shielding portion 82c is preferably equal to or longer than the X-direction length of the intra-pixel isolation region 32 .
  • the length in the X direction of the second light shielding portion 82c is longer than the length in the X direction of the intra-pixel isolation region 32 .
  • the first light shielding portion 82a mainly blocks light outside the second surface S2 of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21, and is provided on the first surface S1 side of the semiconductor layer 20. Restricts light from reaching the floating diffusion region FD.
  • the second light shielding portion 82c blocks light mainly inside the second surface S2 side of the semiconductor layer 20 in the photoelectric conversion region 21, and is a floating diffusion region provided on the first surface S1 side of the semiconductor layer 20. It suppresses the arrival of light to the FD.
  • the light shielding member 80I shields light entering (incident) into the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20, Reaching of light to the floating diffusion region FD provided on the first surface S1 side of the layer 20 is suppressed.
  • a metal film such as titanium (Ti), tungsten (W), aluminum (Al), or an alloy thereof is used as a material having excellent light shielding properties and light reflectance higher than that of a silicon oxide film or a silicon film. It is preferred to use membranes.
  • a tungsten (W) film for example, is used as the light shield 80I.
  • the inter-pixel isolation region 31 corresponds to the "first isolation region” of the present technology
  • the intra-pixel isolation region 32 corresponds to the "second isolation region” of the present technology
  • the dug portion 33a, the dug portion 33b, and the dug portion 33i correspond to the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology.
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to "one direction" of the present technology.
  • the photoelectric conversion region 21, the element isolation region 25, the dug portion 33a, the in-pixel isolation region 32, and the like are formed in the semiconductor layer 20, and the semiconductor layer 20 is formed on the first surface S1 side.
  • a multilayer wiring layer 40 is formed.
  • the intra-pixel isolation region 32 is composed of an isolation insulating film 34 provided along the side wall of a dug portion 33b extending in the depth direction (Z direction) of the semiconductor layer 20, and the isolation insulating film 34 in the dug portion 33b. and a silicon film as a conductive material 35 filled through.
  • the in-pixel separation region 32 has a length L 4 (see FIG.
  • the dug portion 33a is the base of the inter-pixel isolation region 31 shown in FIG. 30F.
  • the dug portion 33a extends in the depth direction (Z direction) of the semiconductor layer 20, similarly to the dug portion 33b of the intra-pixel isolation region 32, and has a conductive material 35 inside it via the isolation insulating film 34. is filled.
  • the dug portion 33 a partitions the photoelectric conversion regions 21 into individual photoelectric conversion regions 21 .
  • the dug portions 33a and 33b of the ninth embodiment have different lengths in the Z direction, and therefore are formed in separate steps unlike the eighth embodiment described above.
  • the photoelectric conversion region 21 is formed in an element formation region 20a, a p-type well region 22, an n-type semiconductor region 23, a photoelectric conversion portion 24 (PD), an element isolation region (field isolation region) 25, and an element formation region 20a. and pixel transistors (AMP, SEL, RST, TR).
  • the photoelectric conversion region 21 includes a floating diffusion region FD, an intra-pixel separation region 32, and a first region 21a and a second region 21b separated by the intra-pixel separation region 32.
  • the p-type well region 22 is formed in the first region 21 a and the second region 21 b of the photoelectric conversion region 21 .
  • the element forming region 20a, the n-type semiconductor region 23, and the photoelectric conversion portion 24 are formed in the first region 21a of the photoelectric conversion region 21.
  • the floating diffusion region FD is formed on the first surface S1 side of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 .
  • the semiconductor layer 20 although not limited to this, for example, a p-type semiconductor substrate made of single crystal silicon is used.
  • the thickness of the semiconductor layer 20 is reduced by cutting the side of the second surface S2 of the semiconductor layer 20 by, for example, CMP. 30B, the isolation insulating film 34 and the conductive material 35 in the dug portion 33a are exposed.
  • a dug portion 33i is formed that reaches the tip of the in-pixel isolation region 32 from the second surface S2 side of the semiconductor layer 20 and overlaps with the in-pixel isolation region 32 in plan view. do.
  • the shape and dimensions of the dug portion 33i define the shape and dimensions of the second light shielding portion 82c of the light shielding body 80I shown in FIG. 30H.
  • the width W2 of the dug portion 33i is formed wider than the width W3 of the intra-pixel isolation region 32 .
  • the dug portion 33i is formed using a well-known photolithographic technique and an anisotropic dry etching technique. Although the dug portion 33i and the diffraction/scattering portion 51 are formed in separate processes, either the dug portion 33i or the diffraction/scattering portion 51 may be formed first.
  • the isolation insulating film 34 and the conductive material 35 in the dug portion 33a are selectively removed.
  • the isolation insulating film 34 and conductive material film 35 in the dug portion 33a can be selectively removed by using well-known photolithography technology and anisotropic dry etching technology.
  • the fixed charge film 52 covering the second surface S2 of the semiconductor layer 20 is formed.
  • the fixed charge film 52 is formed over the first region 21a and the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20. Covered with membrane 52 .
  • an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the insides of the dug portions 33a and 33i. .
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by a CVD method and then planarizing the surface side of the silicon oxide film by cutting it by a CMP method.
  • the inter-pixel isolation region 31 in which the insulating film 53 is embedded through the fixed charge film 52 is formed inside the dug portion 33a, and the inter-pixel isolation region 31 partitions the periphery and the interior. is separated into a first region 21a and a second region 21b by the intra-pixel separation region 32 to form the photoelectric conversion region 21.
  • FIG. 30F an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the insides of the dug portions 33a and 33i.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by a CVD method
  • the insulating film 53 on the dug portion 33i and the insulating film 53 inside the dug portion 33i are selectively removed.
  • This selective removal of the insulating film 53 is performed using well-known photolithography technology and anisotropic dry etching technology.
  • a light shielding film 82 is formed on the entire surface of the insulating film 53 including the inside of the dug portion 33i.
  • the light shielding film 82 is, for example, a metal film such as titanium (Ti) or tungsten (W) having a higher light reflectance than a silicon oxide film or a silicon film, or an alloy film formed by a well-known film forming technique. can be formed by
  • the light shielding film 82 is formed over the plurality of photoelectric conversion regions 21, covers the first region 21a and the second region 21b of each of the plurality of photoelectric conversion regions 21 in plan view, and covers the second region 21b of each of the plurality of photoelectric conversion regions 21.
  • the dug portion 33i is formed so as to be embedded.
  • the light shielding film 82 in the embedded portion 33i is formed through the fixed charge film 52. As shown in FIG.
  • the light shielding film 82 is patterned to cover the second region 21b of the photoelectric conversion region 21 and extend over the inside and outside of the second surface S2 of the semiconductor layer 20 as shown in FIG. 30H.
  • Form 80I. Patterning of the light shielding film 82 can be performed using well-known photolithography technology and anisotropic dry etching technology.
  • the light shielding body 80I is provided outside the second region 21b of the photoelectric conversion region 21 (outside the first surface S1 of the semiconductor layer 20) with the insulating film 53 interposed therebetween, and is located on the second region in plan view. 21b and the floating diffusion region FD, and a second light shielding portion 82c protruding into the semiconductor layer 20 through the insulating film 53 from the first light shielding portion 82a.
  • the light blocking member 80I includes first linear portions 81x extending in the X direction and repeatedly arranged at a predetermined arrangement pitch in the Y direction, and the first linear portions 81x.
  • the light shielding member 80I is formed in a lattice planar pattern that overlaps the lattice planar pattern of the inter-pixel separation region 31 in plan view.
  • the first light shielding portion 82a and the second light shielding portion 82c are formed in the first linear portion 81x.
  • the color filter 55 and the microlens 56 are formed in this order on the opposite side of the light shielding member 80I from the semiconductor layer 20 side. Become.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • FIG. 29B in one photoelectric conversion region 21 (one pixel 3), irradiation light 57I irradiated to the microlens 56 becomes oblique light 57I1 , and the microlens 56, the color filter 55, and the insulating film 53, penetrates (passes) the fixed charge film 52, the diffraction/scattering portion 51, etc., and enters the first region 21a (photoelectric conversion portion 24 (PD)) of the photoelectric conversion region 21 from the second surface S2 side of the semiconductor layer 20. (incident).
  • the oblique light 57I1 entering the first region 21a hits (irradiates) the second light blocking portion 82c of the light blocking body 80I from the first region 21a side.
  • the second light shielding portion shown in FIG. 29B of the ninth embodiment is similar to the light shielding film 54 shown in FIG. Without the 82c, the oblique light 57I1 entering the second region 21b of the photoelectric conversion region 21 hits (irradiates) the intra-pixel isolation region 32 from the first region 21a side.
  • the oblique light 57I1 striking the intra-pixel isolation region 32 includes oblique light reflected by the intra-pixel isolation region 32 and returning to the first region 21a of the photoelectric conversion region 21, and passing through the intra-pixel isolation region 32 for photoelectric conversion. There is also oblique light that enters the second region 21b of the region 21 .
  • the intra-pixel isolation region 32 including a silicon film as the conductive material 35 there is concern that the oblique light 57I1 may enter the second region 21b because the silicon film has poor light blocking properties.
  • the oblique light 57I1 When the oblique light 57I1 enters the second region 21b of the photoelectric conversion region 21, the oblique light 57I1 reaches the floating diffusion region FD provided on the first surface S1 side of the semiconductor layer 20 in the second region 21b. do. Since the arrival of the oblique light 57H1 to the floating diffusion region FD affects the parasitic light sensitivity characteristic, it is important to suppress the oblique light from entering the second region 21b as much as possible.
  • the light shielding member 80I of the ninth embodiment overlaps the intra-pixel isolation region 32 in a plan view and is the first light shielding member outside the second surface S2 of the semiconductor layer 20.
  • a second light shielding portion 82c protruding into the semiconductor layer 20 from the portion 82a is provided. Therefore, the oblique light 57H1 that has entered the first region 21a of the photoelectric conversion region 21 hits (irradiates) the second light shielding portion 82c of the light shielding member 80I from the first region 21a side, and is reflected by the second light shielding portion 82c. to return to the second area 21b.
  • the light shielding body 80I of the ninth embodiment shields the oblique light 57I1 entering the second region 21b from the first region 21a side of the photoelectric conversion region 21 with the second light shielding portion 82c, and passes the oblique light 57I1 to the floating diffusion region FD. can be suppressed from reaching the oblique light 57I1 .
  • the oblique light 57I1 impinging (irradiated) on the second light shielding portion 82c of the light shielding body 80I from the first region 21a side is reflected by the second light shielding portion 82c and reaches the first region 21a of the photoelectric conversion region 21. Therefore, it is possible to improve the quantum efficiency QE.
  • the oblique light 57 I 2 that hits (irradiates) the inter-pixel separation region 31 from the first region 21 a side of the photoelectric conversion region 21 is mainly reflected by the inter-pixel separation region 31 . to return to the first region 21a (photoelectric conversion unit 24 (PD)).
  • the light shielding member 80I of the ninth embodiment is provided outside the second surface S2 of the semiconductor layer 20 and overlaps the second region 21b of the photoelectric conversion region 21 in plan view. Since the first light shielding portion 82a is also provided, like the light shielding film 54 of the above-described first embodiment, the light from the second surface S2 of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 to the second region 21b is also provided. The first light shielding portion 82a blocks the light entering the floating diffusion region FD, thereby suppressing the arrival of the light to the floating diffusion region FD.
  • the solid-state imaging device 1I according to the ninth embodiment includes an inter-pixel isolation region 31 and an intra-pixel isolation region 32, like the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1I according to the ninth embodiment, similarly to the solid-state imaging device 1A according to the first embodiment described above, the quantum efficiency QE as a pixel characteristic is improved and high color mixing suppression (MTF) is achieved. In addition, transfer characteristics as pixel characteristics can be improved.
  • the light shielding member 80I of the ninth embodiment has a first light shielding portion 82a provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have.
  • the first light shielding portion 82a provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have.
  • PLS parasitic light sensitivity characteristic
  • the light shielding member 80I of the ninth embodiment includes a second light shielding portion 82c that overlaps the intra-pixel isolation region 32 in plan view and protrudes into the semiconductor layer 20 from the first light shielding portion 82a. Therefore, the oblique light 57I- 1 entering the second region 21b from the first region 21a side of the photoelectric conversion region 21 is blocked by the second light shielding portion 82c, thereby suppressing the arrival of the oblique light 57I- 1 to the floating diffusion region FD.
  • the parasitic light sensitivity characteristic (PLS) can be further improved in combination with the effect of improving the parasitic light sensitivity characteristic by the first light shielding portion 82a.
  • the quantum efficiency QE is also improved. be able to.
  • the effect of suppressing the oblique light 57I1 from reaching the floating diffusion region FD is that the second light shielding portion 82c extends from the first light shielding portion 82a to the tip of the semiconductor layer 20.
  • the total length L3 it is mainly dependent (proportional) to the embedding length L4 of the second light shielding portion 82c embedded inside the semiconductor layer 20.
  • the function of the intra-pixel isolation region 32 acting as an assist electrode to assist the transfer of signal charges to the floating diffusion region FD is mainly proportional to the length L5 of the intra-pixel isolation region 32 in the Z direction.
  • the embedding length L4 of the second light shielding portion 82c is made longer than the length L5 of the intra-pixel isolation region 32 ( L4 > L5 ), and the transfer is important, it is preferable that the length L5 of the in-pixel isolation region 32 is longer than the embedding length L4 of the second light shielding portion 82c ( L5 > L4 ).
  • FIG. 31 is a plan view schematically showing the plane pattern of the light blocking member in the pixel array section of the solid-state imaging device according to the tenth embodiment.
  • 32 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a31-a31 of FIG. 31.
  • FIG. 31 is a plan view of the semiconductor layer 20 shown in FIG. 32 as viewed from the second surface S2 side (light incident surface side). 32 is upside down with respect to FIGS. 5 and 6 of the above-described first embodiment.
  • a solid-state imaging device 1J according to the tenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, but differs in the following configurations.
  • the solid-state imaging device 1J includes a light shielding body 80J instead of the light shielding film 54 shown in FIGS. 5 and 6 of the first embodiment. It has Further, an insulating film 53J provided between the insulating film 53 and the color filter 55 is further provided in relation to the light blocking member 80J.
  • Other configurations are generally similar to those of the first embodiment, and similar configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the light shielding member 80J of the ninth embodiment is provided on the second surface S2 side of the semiconductor layer 20, and has the second region 21b of the photoelectric conversion region 21 and the floating region in plan view. It overlaps with the diffusion area FD.
  • the light shielding member 80J is provided over the inside and outside of the insulating film 53 in the thickness direction (Z direction) of the insulating film 53 .
  • the light shielding member 80J is arranged in the X direction. and a first linear portion 81x repeatedly arranged at a predetermined arrangement pitch in the Y direction; and a second linear portion 81y arranged.
  • the first linear portion 81x overlaps the first portion 31x of the pixel separation region 31 in plan view
  • the second linear portion 81y overlaps the second portion 31y of the pixel separation region 31 in plan view.
  • the light shielding member 80J of the tenth embodiment is also designed to prevent the light incident on a predetermined photoelectric conversion region 21 from leaking into the adjacent photoelectric conversion region 21, similarly to the light shielding member 80H of the eighth embodiment.
  • the planar pattern is a grid-like planar pattern in which the light-receiving surface side (second surface S2 side) of each of the plurality of photoelectric conversion regions 21 is opened.
  • the width Xwy of the first linear portion 81x in the Y direction is wider than the width Ywx of the second linear portion 81y in the X direction.
  • the light shielding body 80J is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side, and the second region 21b of the photoelectric conversion region 21 and the floating diffusion region in plan view.
  • a third light shielding portion 82d2 that overlaps with the inter-separation region 31 and protrudes into the insulating film 53 from the first light shielding portion 82a.
  • the first light shielding portion 82a, the second light shielding portion 82d1 and the third light shielding portion 82d2 are formed in the first linear portion 81x.
  • the first linear portion 81x of the tenth embodiment includes first to third light shielding portions 82a, 82d 1 and 82d 2 .
  • the first light blocking portion 82a of the light blocking body 80J is covered with an insulating film 53J provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side. That is, the light shield 80J is included in the insulating layers including the insulating films 53 and 53J.
  • the insulating film 53J is composed of, for example, a silicon oxide film.
  • the second light shielding portion 82d1 of the light shielding body 80J is provided in the dug portion 53d1 of the insulating film 53.
  • the third light shielding portion 82d2 of the light shielding body 80J is provided in the dug portion 53d2 of the insulating film 53.
  • the second light shielding portion 82d1 and the recessed portion 53d1 , and the third light shielding portion 82d2 and the recessed portion 53d2 are arranged in the direction in which the first regions 21a and the second regions 21b of the photoelectric conversion region 21 are arranged (Y direction). are spaced apart from each other.
  • each of the first light shielding portion 82a, the second light shielding portion 82d1 , and the third light shielding portion 82d2 of the light shielding body 80J corresponds to the arrangement of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21. In the direction (Y direction), it is positioned closer to the second region 21b than the first region 21a. Specifically, each of the first light shielding portion 82a and the second light shielding portion 82d1 is located closer to the second region 21b than the interface If1 between the first region 21a and the intra-pixel isolation region 32 in plan view.
  • the first light-shielding portion 82a and the third light-shielding portion 82d2 are the inter-pixel separation region 31 between the two photoelectric conversion regions 21 adjacent to each other in the Y direction, and the first region adjacent to the inter-pixel separation region 31. It is positioned closer to the second region 21b than the interface If2 with 21a. That is, the light shielding member 80J overlaps with each of the intra-pixel separation region (second separation region) 32 and the inter-pixel separation region (first separation region) 31 in a plan view, and also overlaps the first region 21a and the inter-pixel separation region 31 of the photoelectric conversion region 21. It is positioned closer to the second region 21b than the first region 21a of the photoelectric conversion region 21 in the arrangement direction (Y direction) of the second region 21b.
  • each of the second and third light shielding portions 82d 1 and 82d 2 also has a planar surface similar to the second light shielding portions 82b and 82c of the eighth and ninth embodiments described above. It extends in the X direction side by side with the intra-pixel isolation region 32 when viewed.
  • the X-direction length of each of the second and third light shielding portions 82d 1 and 82d 2 is equal to or longer than the X-direction length of the intra-pixel isolation region 32. is preferred.
  • the X-direction length of each of 82d 1 and 82d 2 is longer than the X-direction length of the intra-pixel isolation region 32 .
  • the first light shielding portion 82a mainly shields the outside of the insulating film 53 on the side opposite to the semiconductor layer 20 side in the second region 21b of the photoelectric conversion region 21, It suppresses light from reaching the provided floating diffusion region FD.
  • the second and third light shielding portions 82d 2 and 82d 3 block light inside the insulating film 53 and suppress light from reaching the floating diffusion region FD provided on the first surface S1 side of the semiconductor layer 20. do.
  • the light blocking member 80J blocks light entering (incident) into the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20, Reaching of light to the floating diffusion region FD provided on the first surface S1 side of the layer 20 is suppressed.
  • a metal film such as titanium (Ti), tungsten (W), aluminum (Al), or the like, which has excellent light shielding properties and has a higher light reflectance than a silicon oxide film or a silicon film, or an alloy film is used. is preferred.
  • a tungsten (W) film for example, is used as the light blocking member 80J.
  • the inter-pixel isolation region 31 corresponds to the "first isolation region” of the present technology
  • the intra-pixel isolation region 32 corresponds to the "second isolation region” of the present technology
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to "one direction" of the present technology.
  • the light blocking member 80J extends over two photoelectric conversion regions 21 adjacent to each other in the X direction within a two-dimensional plane, although not limited thereto.
  • the first light shielding portion 82a also extends continuously across two photoelectric conversion regions 21 adjacent to each other in the X direction.
  • steps similar to those of the eighth embodiment are performed to form an insulating film 53 as shown in FIG. 34A.
  • each of the dug portions 53d1 and 53d2 is formed by selectively etching the insulating film 53 using well-known photolithography technology and anisotropic dry etching technology.
  • Each of the dug portions 53d 1 and 53d 2 is formed so as to be positioned closer to the second region 21b than the first region 21a of the photoelectric conversion region 21 .
  • a light shielding film 82 is formed on the entire surface of the insulating film 53 including the inside of each of the dug portions 53d1 and 53d2 .
  • the light shielding film 82 is formed of a metal film such as titanium (Ti), tungsten (W), aluminum (Al) or the like, or an alloy film having a reflectance higher than that of a silicon oxide film or a silicon film, or an alloy film. It can be formed by forming a film by a technique.
  • the light shielding film 82 is formed over the plurality of photoelectric conversion regions 21 and is formed so as to bury the dug portions 53d 1 and 53d 2 of each photoelectric conversion region 21 .
  • the light shielding film 82 is patterned to cover the second region 21b of the photoelectric conversion region 21 and the second surface S2 side of the semiconductor layer 20 as shown in FIG. 34D.
  • a light shielding member 80J extending over the inside and outside of the insulating film 53 is formed. Patterning of the light shielding film 82 can be performed using well-known photolithography technology and anisotropic dry etching technology.
  • the light shielding member 80J is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side and overlaps the second region 21b of the photoelectric conversion region 21 in plan view, and and a second light shielding portion 82d1 that overlaps the intra-pixel isolation region 32 and protrudes into the insulating film 53 from the first light shielding portion 82a, and a first light shielding portion 82d1 that overlaps the inter-pixel isolation region 31 in plan view and and a third light shielding portion 82d2 protruding into the insulating film 53 from 82a. Further, referring to FIG.
  • the light blocking member 80J includes first linear portions 81x extending in the X direction and repeatedly arranged at a predetermined arrangement pitch in the Y direction, and the first linear portions 81x. and second linear portions 81y that intersect and extend in the Y direction and are repeatedly arranged in the X direction at a predetermined arrangement pitch. Further, the light shielding member 80J is formed in a lattice planar pattern that overlaps the lattice planar pattern of the inter-pixel separation region 31 in plan view. The first light shielding portion 82a, the second light shielding portion 82d1 and the third light shielding portion 82d2 are formed in the first linear portion 81x.
  • an insulating film 53J covering the light shielding member 80J is formed on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the color filter 55, the microlens 56, and the like are formed in this order on the side of the insulating film 53J opposite to the semiconductor layer 20 side, resulting in the state shown in FIGS.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • FIG. 33 As shown in FIG. 33, in one photoelectric conversion region 21 (one pixel 3), oblique light 57J1 radially emitted from the microlens 56 is transmitted through the color filter 55 , the insulating film 53J, and the insulating film 53 to be shielded. It hits (irradiates) the second light shielding portion 82d1 of the body 80J.
  • the oblique light 57J1 striking the second light shielding portion 82d1 is reflected by the second light shielding portion 82d1 , and is transmitted from the second surface S2 side of the semiconductor layer 20 to the first region 21a (photoelectric conversion region) of the photoelectric conversion region 21. 24 (PD)). That is, in the light shielding member 80J of the tenth embodiment, the oblique light 57J1 entering the second region 21b of the photoelectric conversion region 21 from the periphery of the first light shielding portion 82a of the light shielding member 80J is shielded by the second light shielding portion 82d1 . Thus, it is possible to suppress the oblique light 57J1 from reaching the floating diffusion region FD.
  • the oblique light entering the second region 21b of the photoelectric conversion region 21 from the periphery of the light shielding film 54 can be shielded by adopting the first protrusion structure that protrudes toward the first region 21a.
  • the light-shielding film 54 has the above-described first protruding structure, the amount of light entering the first region 21a of the photoelectric conversion region 21 is reduced, and the quantum efficiency QE is lowered.
  • the second light shielding portion 82d1 projecting into the insulating film 53 from the first light shielding portion 82a prevents the photoelectric conversion region 21 from surrounding the first light shielding portion 82a. Since the oblique light 57J1 entering the second region 21b can be blocked, there is no need to provide the first protruding structure unlike the light blocking film 54 shown in FIG. Therefore, the light shielding member 80J of the tenth embodiment secures the amount of light that enters the first region 21a (photoelectric conversion section 24 (PD)) of the photoelectric conversion region 21, and the surroundings of the first light shielding portion 82d2. oblique light 57J1 entering the second region 21b of the photoelectric conversion region 21 from the second region 21b can be blocked.
  • PD photoelectric conversion section 24
  • the quantum efficiency QE can be improved. can.
  • oblique light 57J 2 radially emitted from the microlens 56 of one pixel 3X 1 passes through the color filter 55 , passes through the insulating film 53J and the insulating film 53, and hits (is irradiated with) the third light shielding portion 82d2 of the light shielding body 80J in the other pixel 3X2 .
  • the oblique light 57J2 striking the third light shielding portion 82d2 of the light shielding body 80J in the other pixel 3X2 is reflected by the second light shielding portion 82d2 and emitted from the second surface S2 of the semiconductor layer 20 to one side.
  • the first region 21a (photoelectric conversion unit 24 (PD)) of the photoelectric conversion region 21 in the pixel 3X1 is shielded by the third light shielding portion 82d2.
  • the light shielding film 54 of the other pixel 3X2 extends from the second region 21b side of the photoelectric conversion region 21 of the other pixel 3X2 to the first region 21a side of the photoelectric conversion region 21 of the one pixel 3X1.
  • the second protruding structure it is possible to block oblique light entering the second region 21b of the photoelectric conversion region 21 of the pixel 3X1 from one pixel 3X1 to the other pixel 3X2.
  • the light-shielding film 54 in the other pixel 3X2 has the above-described second protrusion structure
  • the light-shielding film 54 in the one pixel 3X1 is formed in the same manner as in the case of the above-described first protrusion structure.
  • the amount of light entering the first region 21a (photoelectric conversion part 24 (PD)) of the conversion region 21 is reduced, and the quantum efficiency QE is lowered.
  • the third light shielding portion 82d2 protruding into the insulating film 53 from the first light shielding portion 82a allows the two pixels 3 ( 3X1) adjacent to each other in the Y direction. , 3X 2 ), the oblique light 57J 2 that enters the second region 21b of the photoelectric conversion region 21 in the pixel 3X 1 from one pixel 3X 1 to the other pixel 3X 2 can be blocked. It is not necessary to have a second protruding structure.
  • the light shielding member 80J of the tenth embodiment secures the amount of light entering the first region 21a (photoelectric conversion portion 24 (PD)) of the photoelectric conversion region 21 in one pixel 3X1 , It is possible to suppress the oblique light 57J2 entering from the pixel 3X1 to the second region 21b of the photoelectric conversion region 21 in the other pixel 3X2 .
  • the oblique light 75J2 that hits the third light shielding portion 82d2 of the light shielding body 80J from one pixel 3X1 to the other pixel 3X2 is reflected by the third light shielding portion 82d2 , Since it penetrates into the first region 21a of the photoelectric conversion region 21, it is possible to improve the quantum efficiency QE in one pixel 3X1 .
  • each of the first light shielding portion 82a, the second light shielding portion 82d1 , and the third light shielding portion 82d2 of the light shielding body 80J is arranged in the direction ( Y direction), it overlaps with the second region 21b of the photoelectric conversion region 21 in a plan view, and is preferably located closer to the second region 21b than the first region 21a of the photoelectric conversion region 21 .
  • the oblique lights 57J1 and 57J2 are more likely to enter the second region 21b of the photoelectric conversion region 21 in proportion to the thickness of the insulating film 53. Therefore, in the case of the light shielding film 54 shown in FIG. It is necessary to widen the width in the Y direction of the portion of the photoelectric conversion region 21 that overlaps the first region 21a in plan view according to the film thickness of 53 . On the other hand, in the case of the light shielding member 80J of the first embodiment, the length (height) in the Z direction of each of the second light shielding portion 82d1 and the third light shielding portion 82d2 depends on the film thickness of the insulating film 53.
  • depth allows oblique light to enter the second region 21a of the photoelectric conversion region 21 without preventing light from entering the first region 21a (photoelectric conversion portion 24 (PD)) of the photoelectric conversion region 21. Intrusion of 57J 1 and 57J 2 can be suppressed.
  • the solid-state imaging device 1J according to the tenth embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32, like the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1J according to the tenth embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, an improvement in the quantum efficiency QE as a pixel characteristic and a high color mixing suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixing suppression
  • the light shielding member 80J of the tenth embodiment includes a first light shielding portion 82a provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side and overlapping the intra-pixel isolation region 32 in plan view. .
  • a first light shielding portion 82a provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side and overlapping the intra-pixel isolation region 32 in plan view.
  • the light shielding member 80J of the tenth embodiment includes a second light shielding portion 82d1 that overlaps the intra-pixel isolation region 32 in plan view and protrudes into the insulating film 53 from the first light shielding portion 82a . . Therefore, the oblique light 57J1 entering the second region 21b of the photoelectric conversion region 21 from the periphery of the first light shielding portion 82a of the light shielding body 80J is blocked by the second light shielding portion 82d1 . It is possible to suppress the oblique light 57J1 from reaching the floating diffusion region FD, and further improve the parasitic light sensitivity characteristic (PLS) together with the effect of improving the parasitic light sensitivity characteristic by the first light shielding portion 82a.
  • PLS parasitic light sensitivity characteristic
  • the oblique light 75a striking the second light shielding portion 82d1 of the light shielding body 80J is reflected by the second light shielding portion 82d1 and enters the first region 21a (photoelectric conversion portion 24 (PD)). It is also possible to improve the efficiency QE.
  • the light shielding member 80J of the tenth embodiment includes a third light shielding portion 82d2 that overlaps the pixel isolation region 31 in plan view and protrudes into the insulating film 53 from the first light shielding portion 82a. . Therefore, in two pixels 3 (3X 1 and 3X 2 ) adjacent to each other in the Y direction, oblique light 57J 2 enters the second region 21b of the photoelectric conversion region 21 of one pixel 3X 1 to the other pixel 3X 2 . can be blocked by the third light shielding portion 82d2 to suppress oblique light 57J1 from reaching the floating diffusion region FD provided in the second region 21b of the photoelectric conversion region 21 in the other pixel 3X2. Combined with the effect of suppressing color mixture due to the light reflection of the separation region 31, it is possible to further suppress color mixture.
  • the oblique light 57J2 that hits the third light shielding portion 82d2 of the light shielding body 80J from one pixel 3X1 to the other pixel 3X2 is reflected by the third light shielding portion 82d2 , Since it penetrates into the first region 21a (photoelectric conversion part 24 (PD)) of the photoelectric conversion region 21, it is possible to further improve the quantum efficiency QE.
  • FIG. 35 is a plan view schematically showing the planar patterns of the light blocking bodies and the light reflectors in the pixel array section of the solid-state imaging device according to the eleventh embodiment.
  • FIG. 36 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a35-a35 of FIG. 35 is a plan view of the semiconductor layer 20 shown in FIG. 36 as viewed from the second surface S2 side (light incident surface side). 36 is upside down with respect to FIGS. 5 and 6 of the first embodiment.
  • a solid-state imaging device 1K according to the eleventh embodiment of the present technology basically has the same configuration as that of the solid-state imaging device 1A according to the above-described first embodiment, except for the following configurations.
  • the in-pixel isolation region 32 overlaps with the in-pixel isolation region 32 in a plan view on the second surface S2 side of the semiconductor layer 20.
  • a light reflector 85K provided and having a lower refractive index than the semiconductor layer 20 is further provided.
  • the length L 5 (see FIG. 37A) of the intra-pixel isolation region 32 in the Z direction is shorter than the length of the inter-pixel isolation region 31 in the Z direction. .
  • the length L5 extending from the first surface S1 side of the semiconductor layer 20 to the second surface S2 side is equal to that of the first embodiment described above. It is shorter than the intra-pixel isolation region 32 shown in FIGS.
  • Other configurations are generally similar to those of the first embodiment, and similar configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the light reflector 85K has a fixed charge in a recessed portion 33K as a third recessed portion extending from the second surface S2 side of the semiconductor layer 20 toward the intra-pixel isolation region 32.
  • It includes an insulating film 53 provided through a film 52 .
  • a silicon oxide film can be used as the insulating film 53.
  • a silicon oxide film has a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs.
  • the fixed charge film 52 is provided over the dug portion 33a, the second surface S2 of the semiconductor layer 20, and the dug portion 33K.
  • the fixed charge film 52 in the dug portion 33K is provided along the inner wall (side wall and bottom wall) of the dug portion 33K.
  • the film thickness of the fixed charge film 52 is extremely thin compared to the film thickness of the insulating film 53 in the dug portion 33K.
  • the film thickness of the fixed charge film is drawn thicker than the actual ratio in order to make the configuration of the fixed charge film 52 easier to understand. Therefore, the insulating film 53 and the fixed charge film 52 can be regarded as the light reflector 85K.
  • the fixed charge film 52 includes a film of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), or the like, as a dielectric film that generates negative fixed charges. These dielectric films have a lower refractive index than semiconductor materials such as Si, SiGe and InGaAs. Therefore, from this point as well, the insulating film 53 and the fixed charge film 52 can be regarded as the light reflector 85K.
  • silicon has a refractive index of about 3.62
  • silicon oxide has a refractive index of about 1.45
  • air has a refractive index of about 1.45. It has a refractive index of about 00.
  • silicon has a refractive index of about 4.08
  • silicon oxide has a refractive index of about 1.46
  • air has a refractive index of about 1.46.
  • it has a refractive index of about 1.00.
  • the length L5 in the Z direction along the thickness direction of the semiconductor layer 20 is longer than the length in the Z direction of the inter-pixel isolation region 31 . It's getting shorter.
  • the Z-direction length L5 of the intra-pixel isolation region 32 of the eleventh embodiment is shorter than the Z-direction length of the intra-pixel isolation region 32 of the above-described first embodiment.
  • the in-pixel isolation region 32 of the eleventh embodiment extends from the element isolation region 25 on the first surface S1 side of the semiconductor layer 20 toward the second surface S2 side, and extends from the second surface S2 side of the semiconductor layer 20 . is separated from the surface S2 of .
  • the dug portion 33K and the light reflector 85K extend from the second surface S2 of the semiconductor layer 20 toward the tip of the in-pixel isolation region 32 and reach the tip of the in-pixel isolation region 32. are doing.
  • the light reflector 85K and the in-pixel isolation region 32 are terminated with each other inside the semiconductor layer 20 where their tips abut.
  • the in-pixel isolation region 32 of the eleventh embodiment extends from the element isolation region 25 to the dug portion 33K.
  • the length L5 of the intra-pixel isolation region 32 is the distance from the bottom surface of the element isolation region 25 to the dug portion 33K.
  • the cut portion 33i extends from the first surface S1 of the semiconductor layer 20 to the dug portion 33i. is the length L5 of the intra-pixel isolation region 32 .
  • the surface of the semiconductor layer 20 in contact with the bottom surface of the element isolation region (field isolation region) 25 can also be regarded as the first surface S1.
  • the intra-pixel separation region 32 and the dug portion 33K are arranged in the direction (Y direction) along the arrangement direction (one direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21, respectively. have different widths (W 3 , W 4 ).
  • the width W4 of the dug portion 33K is wider than the width W3 of the intra-pixel isolation region 32, but the width W3 of the intra-pixel isolation region 32 is dug. It may be wider than the width W4 of the portion 33K. That is, from the viewpoint of patterning accuracy and characteristics, it is preferable to satisfy "W 4 >W 3 " or "W 4 ⁇ W 3 ".
  • the light-shielding film 54 is arranged in the X direction. and a first linear portion 81x repeatedly arranged at a predetermined arrangement pitch in the Y direction; and a second linear portion 81y arranged.
  • the first linear portion 81x overlaps the first portion 31x of the pixel separation region 31 in plan view
  • the second linear portion 81y overlaps the second portion 31y of the pixel separation region 31 in plan view.
  • the light-shielding film 54 of the eleventh embodiment prevents the light incident on a predetermined photoelectric conversion region 21 from leaking into the adjacent photoelectric conversion region 21.
  • the planar pattern is a grid-like planar pattern in which the light-receiving surface side (second surface S2 side) of each of the plurality of photoelectric conversion regions 21 is opened.
  • the width Xwy of the first linear portion 81x in the Y direction is wider than the width Ywx of the second linear portion 81y in the X direction.
  • the light shielding film 54 is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side, and overlaps the intra-pixel isolation region 32 in plan view.
  • the light shielding film 54 includes a second region 21b between the inter-pixel isolation region 31 and the intra-pixel isolation region 32 in plan view, specifically, the p-type well region 22 and the floating diffusion region. It is provided so as to cover the FD. That is, the floating diffusion region FD is arranged at a position overlapping the light shielding film 54 in plan view.
  • a tungsten (W) film having a light shielding property is used as the light shielding film 54.
  • the inter-pixel isolation region 31 corresponds to one specific example of the “first isolation region” of the present technology
  • the intra-pixel isolation region 32 is one example of the “second isolation region” of the present technology. It corresponds to a specific example.
  • the dug portion 33a, the dug portion 33b, and the dug portion 33K correspond to the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology.
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to a specific example of "one direction" of the present technology
  • the light shielding film 54 corresponds to the "one direction” of the present technology. It corresponds to a specific example of "light shielding body”.
  • a step similar to that of the eighth embodiment described above is performed to form the diffraction scattering portion 51 on the second surface S2 of the semiconductor layer 20 in the first region 21a of the photoelectric conversion region 21. to be carried out.
  • the isolation insulating film 34 and the conductive material 35 in the dug portion 33a are selectively removed.
  • the isolation insulating film 34 and the conductive material 35 in the dug portion 33a can be selectively removed by using well-known photolithography technology and anisotropic dry etching technology.
  • the isolation insulating film 34 and the conductive material 35 is formed on the S2 side using, for example, a photolithographic technique.
  • the second surface S2 side of the semiconductor layer 20 is covered with the mask M1, and the inside of the dug portion 33a is partially filled with the mask M1.
  • the conductive material 35 and the isolation insulating film 34 exposed from the opening M1a of the mask M1 are selectively etched to form a dug portion 33K as shown in FIG. 3D. do.
  • the dug portion 33K overlaps the in-pixel isolation region 32 in a plan view and extends from the second surface S2 side of the semiconductor layer 20 toward the first surface S1 side to form the in-pixel isolation region 32. formed in contact with the tip of the The dug portion 33K is formed with a predetermined depth, but the length of the intra-pixel isolation region 32 is shortened in inverse proportion to the depth of the dug portion 33K.
  • the inner walls (side walls and bottom walls) of the dug portions 33a and 33K are covered, and the second surface S2 of the semiconductor layer 20 is covered.
  • a fixed charge film 52 covering is formed.
  • the fixed charge film 52 is formed over the first region 21a and the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20. Covered with membrane 52 .
  • an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the insides of the dug portions 33a and 33K.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by the CVD method and then cutting the surface side of the silicon oxide film by the CMP method to planarize it.
  • the inter-pixel isolation region 31 in which the insulating film 53 is embedded through the fixed charge film 52 is formed inside the dug portion 33a, and the inter-pixel isolation region 31 partitions the periphery and the interior.
  • the light reflector 85K including the fixed charge film 52 and the insulating film 53 is formed inside the dug portion 33K.
  • a light-shielding film 54, a color filter 55, a microlens 56, and the like are formed in this order on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the state shown in FIG. 32 is obtained.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • FIG. 37B in one photoelectric conversion region 21 (one pixel 3), the oblique light 57K1 radially emitted from the microlens 56 is reflected by the color filter 55, the insulating film 53, the fixed charge film 52, and the diffraction scattering portion. 51 and the like, and enters (enters) the first region 21a (photoelectric conversion part 24 (PD)) of the photoelectric conversion region 21 from the second surface S2 side of the semiconductor layer 20 .
  • PD photoelectric conversion part 24
  • the oblique light 57K1 that has entered the first region 21a hits (irradiates) the light reflector 85K from the first region 21a side.
  • the oblique light 57K1 striking the light reflector 85K is reflected by the light reflector 85K and returns to the first region 21a of the photoelectric conversion region 21.
  • FIG. That is, the light reflector 85K of the eleventh embodiment reflects the oblique light 57K1 that enters the second region 21b from the first region 21a side of the photoelectric conversion region 21 with the light reflector 85K. It is possible to suppress the oblique light 57K1 from reaching the floating diffusion region FD provided in the second region 21b.
  • the oblique light 57K1 that hits (is irradiated to) the light reflector 85K from the first region 21a side of the photoelectric conversion region 21 is reflected by the light reflector 85K and reaches the first region 21a of the photoelectric conversion region 21. Therefore, it is possible to improve the quantum efficiency QE.
  • the oblique light 57K2 radially emitted from the microlens 56 passes through the color filter 55, the insulating film 53, the fixed charge film 52, the diffraction scattering portion 51, and the like, and passes through the second surface S2 side of the semiconductor layer 20. , enters (enters) the first region 21 a (photoelectric conversion portion 24 (PD)) of the photoelectric conversion region 21 .
  • the oblique light 57K2 entering the first region 21a is reflected by the inter-pixel separation region 31 and returns to the first region 21b (photoelectric conversion unit 24 (PD)).
  • FIG. 37C is a diagram showing the correlation between the transmittance in the intra-pixel isolation region 32 and the length L 6 of the light reflector 85K (see FIG. 37A) (a diagram showing the dependence of the transmittance on the insulating film length). be.
  • the intra-pixel isolation region 32 includes a silicon film having poor light blocking properties as the conductive material 35 , and the light reflector 85K includes an insulating film 53 having a lower refractive index than the semiconductor layer 20 .
  • the first region 21a of the photoelectric conversion region 21 to the second The transmittance of light (632 nm wavelength) entering the region 21b can be reduced by 50% or more. Therefore, the length L6 of the light reflector extending from the second surface S2 of the semiconductor layer 20 toward the first surface S1 is preferably 1.5 ⁇ m or more.
  • the solid-state imaging device 1K according to the eleventh embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32, similarly to the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1K according to the eleventh embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, an improvement in the quantum efficiency QE as a pixel characteristic and a high color mixture suppression (MTF) are intended. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixture suppression
  • the solid-state imaging device 1K includes the light shielding film 54 provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have it.
  • the solid-state imaging device 1A of the first embodiment described above in the second region 21b of the photoelectric conversion region 21, from the second surface S2 side (light incident surface side) of the semiconductor layer 20 to the second region 21b. Intruding light can be shielded by the first light shielding portion 82a, light reaching the floating diffusion region FD can be suppressed, and the parasitic light sensitivity characteristic (PLS) can be improved.
  • PLS parasitic light sensitivity characteristic
  • the solid-state imaging device 1K according to the eleventh embodiment is provided on the second surface S2 side (light incident surface side) of the semiconductor layer 20 so as to overlap the in-pixel isolation region 32 in a plan view, and the semiconductor layer A light reflector 85K having a lower refractive index than 20 is provided. Therefore, the oblique light 57K1 striking the light reflector 85K from the first region 21a side of the photoelectric conversion region 21 is reflected by the light reflector 85K and returns to the first region 21a. It is possible to suppress the oblique light 57I1 from reaching the floating diffusion region FD provided in the region 21b. can be improved.
  • the oblique light 75K1 is reflected by the light reflector 85K and returns to the first region 21a, it is possible to improve the quantum efficiency QE.
  • the present technology is not limited to the light reflector 85K of the above-described eleventh embodiment.
  • a light reflector 85K- 1 including a cavity 53k- 1 filled with air having a lower refractive index than the semiconductor layer 20 and a fixed charge film 52 can be used.
  • the inter-pixel separation region 31K including the cavity 53k2 filled with air having a lower refractive index than the semiconductor layer 20 and the fixed charge film 52 may be used as the first separation region.
  • the X-direction length of the light reflector 85K may be the length that the gate electrode 37 of the transfer transistor TRG and the light reflector 85K overlap in plan view.
  • each of the two pixel separation regions 31 separated from each other in the X direction and the light It may be integrated with the reflector 85K.
  • the light reflector 85K is biased (offset) toward the first region 21a of the photoelectric conversion region 21 relative to the intra-pixel separation region 32 in the Y direction (one direction). and the second region 21b. That is, the light reflector 85K is provided closer to the first region 21a than the intra-pixel separation region 32 in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21,
  • a configuration in which a silicon film 35 as the conductive material 35 of the intra-pixel isolation region 32 is provided between the body 85K and the second region 21b may be employed.
  • the conductive material 35 of the intra-pixel isolation region 32 is configured (extended) closer to the second surface S2 side of the semiconductor layer 20 than in the eleventh embodiment.
  • the charge transfer characteristics can be improved.
  • FIG. 44 is a plan view schematically showing a plane pattern of separation regions in the pixel array section of the solid-state imaging device according to the twelfth embodiment.
  • FIG. 45 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line a44-a44 of FIG.
  • FIG. 46 is a longitudinal sectional view enlarging a part of FIG.
  • the inter-pixel separation region 31 corresponds to a specific example of the "first separation region” of the present technology
  • the intra-pixel separation region 32 corresponds to a specific example of the "second separation region” of the present technology.
  • the insulating film 53 and the conductive material 35 correspond to specific examples of the "insulating material” and the "conductive material” of the present technology.
  • the dug portion 33a, the dug portion 33b, and the dug portion 33L correspond to the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology.
  • the photoelectric conversion region 21L 1 and the photoelectric conversion region 21L 2 correspond to specific examples of the “first photoelectric conversion region” and the “second photoelectric conversion region” of the present technology.
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21L- 1 and 21L- 2 corresponds to a specific example of "one direction" of the present technology.
  • a solid-state imaging device 1L according to the twelfth embodiment of the present technology basically has the same configuration as that of the solid-state imaging device 1A according to the above-described first embodiment, except for the following configurations.
  • the solid-state imaging device 1L according to the twelfth embodiment includes a photoelectric conversion region 21L- 1 and a photoelectric conversion region 21L- 2 partitioned by the inter-pixel separation region 31 in the Y direction.
  • the solid-state imaging device 1L according to the twelfth embodiment also includes an in-cell inter-pixel separation region 31L that separates the photoelectric conversion region 21L -1 and the photoelectric conversion region 21L- 2 .
  • Other configurations are generally similar to those of the above-described first embodiment.
  • the photoelectric conversion cell 16 includes two photoelectric conversion regions 21L 1 and 21L 2 arranged in a 1 ⁇ 2 array, one in the X direction and two in the Y direction.
  • the photoelectric conversion cells 16 are repeatedly arranged in each of the X direction and the Y direction to construct a pixel array section similar to the pixel array section 2A shown in FIG.
  • Each of the photoelectric conversion regions 21L 1 and 21L 2 included in the photoelectric conversion cell 16 is provided individually corresponding to the pixel 3 .
  • each of the photoelectric conversion regions 21L- 1 and 21L- 2 included in the photoelectric conversion cell 16 has the same configuration as the photoelectric conversion region 21 of the above-described first embodiment. That is, each of the first and second photoelectric conversion regions 21L 1 and 21L 2 includes the intra-pixel isolation region 32, the p-type well region 22 provided in the semiconductor layer 20, and the p-type well region 22 provided in the p-type well region 22. and an n-type semiconductor region 23, a photoelectric conversion portion 24 (PD), and a floating diffusion region FD.
  • Each of the first and photoelectric conversion regions 21L 1 and 21L 2 includes an element formation region 20a, an intra-pixel separation region 32, and a diffraction/scattering portion 51. As shown in FIG.
  • first portions 31x extending in the X direction are repeatedly arranged in the Y direction for each photoelectric conversion cell 16 (for each two photoelectric conversion regions 21L1 and 21L2 ).
  • a second portion 31y extending in the Y direction is repeatedly arranged in the X direction for each photoelectric conversion cell 16 (for each photoelectric conversion region 21L1 or 21L2 ). That is, the inter-pixel separation region 31 has a grid-like planar pattern in plan view, as in the first embodiment described above.
  • the two photoelectric conversion regions 21L1 and 21L2 aligned in the Y direction are partitioned by two adjacent first portions 31x of the inter-pixel separation region 31 at both ends in the Y direction.
  • the two photoelectric conversion regions 21L- 1 and 21L -2 aligned in the direction are partitioned by two adjacent second portions 31y of the inter-pixel separation region 31 on both end sides in the X direction.
  • the photoelectric conversion region 21L- 1 and the photoelectric conversion region 21L- 2 are separated (partitioned) by an in-cell pixel separation region 31L extending in the X direction.
  • the intra-pixel isolation region 32 is formed by dividing each of the photoelectric conversion regions 21L -1 and 21L- 2 into the first region in the Y direction, similarly to the intra-pixel isolation region 32 of the first embodiment described above. 21a and the second region 21b.
  • a p-type well region 22, an n-type semiconductor region 23, a photoelectric conversion portion 24 (PD), an element forming region 20a, a diffraction scattering portion 51, and the like are provided in the first region 21a.
  • a p-type well region 22, a floating diffusion region FD, and the like are provided in the second region 21b.
  • Pixel transistors AMP, SEL, RST, TRG
  • AMP AMP, SEL, RST, TRG
  • FIG. 44 shows only the transfer transistor TRG among the pixel transistors, and illustration of the pixel transistors is omitted in FIG. 45, as in FIGS. are doing.
  • the order in which the first regions 21a and the second regions 21b are arranged in the Y direction (one direction) is different between the photoelectric conversion regions 21L -1 and 21L- 2 .
  • the first region 21a and the second region 21b are arranged in this order in the photoelectric conversion region 21L -1
  • the second region 21b is arranged in the photoelectric conversion region 21L -2 .
  • the second area and the first area are arranged in this order. That is, in the photoelectric conversion cell 16, the second regions 21b of the photoelectric conversion regions 21L- 1 and 21L- 2 are adjacent to each other in a plan view via the intra-cell pixel isolation region 31L.
  • the photoelectric conversion cell 16 has first and photoelectric conversion regions 21L 1 and 21L in which each second region 21b is arranged adjacent to each other in the Y direction via the in-cell pixel separation region 31L in plan view. 2 .
  • the in-cell pixel isolation region 31L extends in the thickness direction (Z direction) of the semiconductor layer 20 .
  • One end of the in-cell pixel isolation region 31 ⁇ /b>L is connected to the element isolation region 25 , and the other end is separated from the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the in-cell pixel isolation region 31L is provided in a recessed portion 33L extending in the thickness direction (Z direction) of the semiconductor layer 20 and includes an insulating film 27 as an insulating material having a lower refractive index than the semiconductor layer 20. .
  • the dug portion 33 ⁇ /b>L has one end connected to the element isolation region 25 and the other end separated from the second surface S ⁇ b>2 of the semiconductor layer 20 .
  • the insulating film 27 in the intra-cell pixel isolation region 31L is formed in the same process as the insulating film 27 in the element isolation region 25 .
  • a silicon oxide film can be used as the insulating film 27, for example.
  • a silicon oxide film has a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs.
  • the in-cell pixel separation region 31L and the pixel separation region 31 are arranged in each direction along the arrangement direction (one direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21.
  • the widths ( W7 , W8 ) are different. Specifically, the width W7 of the in-cell pixel separation region 31L is narrower than the width W7 of the pixel separation region 31 ( W7 ⁇ W8 ). Further, the width W7 of the intra-cell isolation region 31L and the intra-pixel isolation region 32 are narrower than the width W3 of the intra-pixel isolation region 32 ( W7 ⁇ W3 ).
  • the width of the dug portion 33L is narrower than the width of each of the dug portions 33a and 33b.
  • the intra-cell inter-pixel isolation region 31L, the inter-pixel isolation region 31 and the intra-pixel isolation region 32 have lengths (L 7 , L 8 , L 5 ) are different. Specifically, the length L7 of the intra-cell isolation region 31L between pixels is shorter than the length L8 of the inter-pixel isolation region 31 and the length L5 of the intra-pixel isolation region 32 .
  • the depth in the Z direction of the dug portion 33L is shallower than the depth in the Z direction of each of the dug portions 33a and 33b.
  • the in-cell pixel isolation region 31L extends from the element isolation region 25 toward the second surface S2 of the semiconductor layer 20 and is separated from the second surface S2 of the semiconductor layer 20 .
  • the length L7 of the in-cell pixel isolation region 31L is the distance from the bottom surface to the tip of the element isolation region 25.
  • FIG. although not shown, in the case where the in-cell pixel separation region 31L extends from the first surface S1 of the semiconductor layer 20 toward the second surface S2, it extends from the first surface S1 of the semiconductor layer 20 to the tip. is the length L7 of the in-cell pixel isolation region 31L.
  • the surface of the semiconductor layer 20 in contact with the bottom surface of the element isolation region (field isolation region) 25 can also be regarded as the first surface S1.
  • the dug portion 33a of the inter-pixel isolation region 31 and the dug portion 33b of the intra-pixel isolation region 32 have the same length and width as design values.
  • the dug portion 33L of the in-cell pixel isolation region 31L and the dug portions 33a and 33b are different in length and width. That is, the dug portion 33L of the intra-cell isolation region 31L is formed in a separate process from the dug portion 33a of the inter-pixel isolation region 31 and the trench portion 33b of the intra-pixel isolation region 32.
  • the light shielding film 54 is provided on the second surface S2 side of the semiconductor layer 20 .
  • the light shielding film 54 overlaps the second region 21b of each of the two photoelectric conversion regions 21L1 and 21L2 and is provided continuously over the second region 21b.
  • the semiconductor layer 20 is formed with the recessed portions 33a and 33b extending from the first surface S1 of the semiconductor layer 20 toward the second surface S2.
  • the dug portion 33a partitions the photoelectric conversion cell 16 including two photoelectric conversion regions 21L1 and 21L2 that are arranged adjacent to each other in the Y direction. That is, the dug portion 33a partitions the periphery of the two photoelectric conversion regions 21L- 1 and 21L- 2 that are arranged adjacent to each other in the Y direction.
  • the dug portion 33b partitions each of the two photoelectric conversion regions 21L- 1 and 21L- 2 into a first region 21a and a second region 21b.
  • Each of the dug portions 33a and 33b can be formed by well-known photolithography technology and anisotropic dry etching technology.
  • the second region 21b of each of the photoelectric conversion regions 21L- 1 and 21L- 2 is Y-shaped through the dug portion forming region 33L1 in which the dug portion 33L (see FIG. 47C) is formed in the subsequent step. lined up next to each other in the direction. That is, the two photoelectric conversion regions 21L -1 and 21L- 2 are not yet partitioned, and each of the two photoelectric conversion regions 21L -1 and 21L -2 is connected to each other through the dug portion forming region 33L- 1 . ing.
  • the p-type well region 22, the n-type semiconductor region 23, the photoelectric conversion part 24 (PD), etc. are already formed in the first region 21a of each of the photoelectric conversion regions 21L - 1 and 21L -2 .
  • a p-type well region 22 is already formed in the second region 21b of each of the photoelectric conversion regions 21L- 1 and 21L -2 .
  • a thinning step for thinning the thickness of the semiconductor layer 20 is performed. Therefore, the depth of each of the dug portions 33a and 33b in the Z direction (thickness direction of the semiconductor layer 20) is formed deeper than the thinning line S3 indicating the thickness of the semiconductor layer 20 performed in the thinning step. do.
  • a cleaning step is performed.
  • the second region 21b of one photoelectric conversion region 21L- 1 and the second region 21b of the other photoelectric conversion region 21L- 2 of the two photoelectric conversion regions 21L- 1 and 21L- 2 that are adjacent to each other in the Y direction. are not partitioned yet and are connected to each other.
  • the isolation insulating film 34 and the conductive material 35 are selectively formed inside each of the dug portions 33a and 33b.
  • the isolation insulating film 34 is formed along the inner walls (side walls and bottom walls) of each of the dug portions 33a and 33b.
  • the conductive material 35 is formed inside each of the dug portions 33a and 33b with the isolation insulating film 34 interposed therebetween.
  • the isolation insulating film 34 and the conductive material 35 inside each of the dug portions 33a and 33b are, for example, the first surface S1 of the semiconductor layer 20 including the inner walls (side walls and bottom walls) of each of the dug portions 33a and 33b.
  • An isolation insulating film 34 and a conductive material 35 are formed in this order on the entire upper surface, and then the conductive material 35 and the isolation insulating film 34 on the first surface S1 of the semiconductor layer 20 are selectively removed in this order by a CMP method or the like. can be formed by removing the As the isolation insulating film 34, for example, a silicon oxide film can be used.
  • Conductive material 35 may be, for example, a doped polysilicon film into which impurities that reduce resistance are introduced during or after deposition.
  • the intra-pixel isolation region 32 including the isolation insulating film 34 and the conductive material 35 is formed inside the dug portion 33b. Then, the first region 21a and the second region 21b of each of the photoelectric conversion regions 21L -1 and 21L- 2 are partitioned and separated by the intra-pixel separation region 32 .
  • the dug portion 33L extending from the first surface S1 toward the second surface S2 of the semiconductor layer 20 is formed.
  • the dug portion 33 ⁇ /b>L is formed shallower than the depth of the dug portions 33 a and 33 b and shallower than the thinning line S ⁇ b>3 of the semiconductor layer 20 . That is, the dug portion 33 ⁇ /b>L is formed with a depth away from the thinning line S ⁇ b>3 of the semiconductor layer 20 .
  • the dug portion 33L can be formed by well-known photolithography technology and anisotropic dry etching technology.
  • the second region 21b of the photoelectric conversion region 21L- 1 and the second region 21b of the photoelectric conversion region 21L- 2 are partitioned and separated by the dug portion 33L, and are adjacent to each other via the dug portion 33L.
  • the dug portion 33L is formed in a separate step from the dug portions 33a and 33b, so that the width and depth in the transverse direction are formed with dimensions different from those of the dug portions 33a and 33b. be able to.
  • the width and depth of the dug portion 33L in the transverse direction are smaller than those of the dug portions 33a and 33b.
  • the isolation insulating film 34 and the conductive material 35 are already provided in each of the dug portions 33a and 33b.
  • an element formation region 20a and an element isolation region 25 are formed on the first surface S1 side of the semiconductor layer 20, and a An intra-cell inter-pixel isolation region 31L in which the insulating film 27 is embedded is formed.
  • the element formation region 20a is partitioned by the element isolation region 25, and by forming the element isolation region 25, the first region 21a of each of the photoelectric conversion regions 21L -1 and 21L- 2 is formed.
  • Each of the element isolation region 25 and the in-cell inter-pixel isolation region 31L is formed by, for example, forming a shallow trench (field trench) 26 recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 20.
  • An insulating film 27 made of, for example, a silicon oxide film is formed on the entire surface of the first surface S1 of the semiconductor layer 20 including the inside of the shallow groove portion 26 and the inside of the dug portion 33L. It can be formed by removing the insulating film 27 on the first surface S1 of the semiconductor layer 20 by the CMP method so as to selectively remain inside each of the dug portions 33L.
  • the insulating film 27 for example, a silicon oxide film having a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs is used.
  • the insulating film 27 is provided inside the dug portion 33L, and the length L7 in the Z direction is the depth of the dug portion 33a in the Z direction and the length L of the intra-pixel isolation region 32 in the Z direction.
  • An intra-cell inter-pixel isolation region 31L shorter than 5 is formed.
  • the second region 2b of the photoelectric conversion region 21L- 1 and the second region 21b of the photoelectric conversion region 21L- 2 are partitioned and separated by the in-cell pixel separation region 31L.
  • pixel transistors (AMP, SEL, RST, TRG) are formed in the element formation regions 20a of the photoelectric conversion regions 21L -1 and 21L- 2 , respectively, and photoelectric conversion is performed as shown in FIG. 47D.
  • a floating diffusion region FD is formed in the second region 21b of each of the regions 21L- 1 and 21L- 2 .
  • the floating diffusion region FD is formed on the first surface S1 side of the semiconductor layer 20 in the second region 21b of each of the photoelectric conversion regions 21L- 1 and 21L -2 .
  • a multilayer wiring layer 40 is formed on the first surface S1 side of the semiconductor layer 20.
  • a thinning step is performed to reduce the thickness of the semiconductor layer 20 by cutting the second surface S2 side of the semiconductor layer 20 by, for example, the CMP method.
  • the isolation insulating film 34 and the conductive material 35 are exposed, and the isolation insulating film 34 and the conductive material 35 of the intra-pixel isolation region 32 are exposed.
  • the thinning of the semiconductor layer 20 is performed up to the thinning line S3 shown in FIG. 47E.
  • the bottom surface of the element isolation region 25 on the first surface S1 side of the semiconductor layer 20 extends toward the second surface S2 side of the semiconductor layer 20, and the tip ends on the second surface S2 of the semiconductor layer 20.
  • 31 L of intra-cell pixel separation regions separated from are formed.
  • the element isolation region 25 extends from the bottom surface of the element isolation region 25 on the first surface S1 side of the semiconductor layer 20 toward the second surface S2 side of the semiconductor layer 20, and the tip thereof extends to the second surface S2 of the semiconductor layer 20.
  • An intra-pixel isolation region 32 reaching the surface S2 is formed.
  • the diffraction scattering portion 51 is formed on the second surface S2 side of the semiconductor layer 20, and the dug portion
  • the isolation insulating film 34 and conductive material 35 inside 33a are selectively removed.
  • the step of forming the diffraction scattering portion 51 is performed separately from the removing step of selectively removing the isolation insulating film 34 and the conductive material 35, but either step may be performed first.
  • the isolation insulating film 34 and the conductive material 35 inside the dug portion 33a can be selectively removed by using well-known photolithography technology and anisotropic dry etching technology.
  • a fixed charge film 52 is formed.
  • the fixed charge film 52 is formed over the first region 21a and the second region 21b of each of the photoelectric conversion regions 21L1 and 21L2 on the second surface S2 side of the semiconductor layer 20, and is formed inside the dug portion 33a. are formed along the sidewalls and bottom walls of and the unevenness of the diffraction scattering portion 51 .
  • the insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the inside of the dug portion 33a.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by the CVD method and then cutting the surface side of the silicon oxide film by the CMP method to planarize it.
  • the inter-pixel isolation region 31 in which the insulating film 53 is buried through the fixed charge film 52 is formed inside the dug portion 33a, and the photoelectric conversion region 31 is partitioned around the periphery by the inter-pixel isolation region 31.
  • a cell 16 is formed.
  • Each photoelectric conversion cell 16 is internally separated into a first region 21a and a second region 21b in the Y direction by an intra-pixel isolation region 32, and each second region 21b is an intra-cell inter-pixel isolation region 31L. It includes two photoelectric conversion regions 21L- 1 and 21L- 2 that are arranged in the Y direction adjacent to each other via the .
  • a light shielding film 54 is formed on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the light shielding film 54 overlaps the second regions 21b of the two photoelectric conversion regions 21L1 and 21L2 , and is formed continuously over the respective second regions 21b.
  • a color filter 55 and a microlens 56 are formed in this order on the opposite side of the light shielding film 54 from the semiconductor layer 20 side, resulting in the states shown in FIGS. 44 to 46B.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • FIG. 48 is a vertical cross-sectional view schematically showing an incident optical path of oblique light in Comparative Example 12-1.
  • FIG. 49 is a vertical cross-sectional view schematically showing an incident optical path of oblique light in the twelfth embodiment.
  • the oblique light is mainly emitted from the edge side of the light shielding film 54 in the width direction (Y direction).
  • the light enters the second region 21b immediately below the light shielding film 54 as the entering optical path 57L. Since the light shielding film 54 has two ends in the width direction (Y direction), there are also two entrance optical paths 57L for one light shielding film 54 in the Y direction.
  • Comparative Example 12-1 in each of the two photoelectric conversion regions 21 arranged adjacent to each other in the Y direction, the first region 21a and the second region 21b are arranged in the same order in the Y direction. . Therefore, there is one light shielding film 54 for each second region 21b, and there are also two entrance optical paths 57L for each second region 21b.
  • the photoelectric conversion cell 16 in the photoelectric conversion cell 16 according to the twelfth embodiment, two photoelectric conversion regions 21L 1 and 21L 2 are arranged adjacent to each other in the Y direction. and the second region 21b of the other photoelectric conversion region 21L2 are arranged adjacent to each other in the Y direction via the intra-cell pixel separation region 31L. Therefore, the light shielding film 54 can be continuously provided over the second regions 21b of the two photoelectric conversion regions 21L1 and 21L2 , and the two second regions 21b share one light shielding film 54. can do.
  • the in-cell pixel isolation region 31L has insulation resistance and light shielding resistance. Therefore, compared to the inter-pixel isolation region 31, which requires both insulation resistance and light-shielding resistance to be emphasized, the lateral direction (the direction orthogonal to the extending direction) is reduced.
  • the width W7 can be narrow.
  • the width W7 of the intra-cell pixel separation region 31L can be narrowed, the pixel pitch in the Y direction can be narrowed, and the area of the pixel array portion can be reduced in the Y direction, or within the same area. , the number of pixels in the Y direction can be increased. This makes it possible to provide a compact image sensor with high resolution.
  • the area of the pixel array section can be reduced in each of the X direction and the Y direction.
  • the in-cell pixel separation region 31L can be replaced by the light shielding film 54 of the semiconductor layer 20. It can also be configured to be spaced apart from the second surface S2 on the side.
  • the recessed portion 33L that defines the Z-direction length L7 of the intra-cell isolation region 31L and the recessed portion 33a that defines the Z-direction length L8 of the inter-pixel isolation region 31 are formed in separate processes. , it is possible to form the dug portion 33L whose depth in the Z direction is shallower than the depth in the Z direction of the dug portion 33a. A spaced in-cell pixel isolation region 31L can be formed.
  • FIG. 50 shows, in Comparative Example 12-2, a recessed portion (third recessed portion) 33L that defines the length L7 of the intra-cell inter-pixel isolation region 31L in the Z direction, and the inter-pixel isolation region 31 in the Z direction.
  • 2 is a vertical cross-sectional view showing a case in which a dug portion (first dug portion) 33a defining a length L8 of is formed in the same step.
  • the dug portion 33b that defines the Z-direction length L5 of the intra-pixel isolation region 32 is normally formed in the same process as the dug portion 33a that defines the Z-direction length L8 of the inter-pixel isolation region 31. Therefore, the description here is omitted, and the description will focus on the dug portions 33L and 33a.
  • dug portions 33L and 33a are separately described, but when the dug portions 33L and 33a are formed in the same process, the dug portion 33L can be replaced with the dug portion 33a.
  • a dug portion 33L partitions between the two photoelectric conversion regions 21L -1 and 21L -2 that are adjacent to each other in the Y direction, and a dug portion surrounds each of the two photoelectric conversion regions 21L -1 and 21L- 2 . It is partitioned by the portion 33a.
  • a cleaning step is performed, although not shown.
  • the second region 21b of one of the two photoelectric conversion regions 21L 1 and 21L 2 arranged adjacent to each other in the Y direction and the second region 21b of the other photoelectric conversion region 21L 1 A dug portion 33L separates the region 21L -2 from the second region 21b, and a dug portion 33a separates the periphery of each of the two photoelectric conversion regions 21L -1 and 21L -2 . Therefore, in the cleaning step after forming the recessed portion 33a in the semiconductor layer 20, the two photoelectric conversion regions 21L 1 , 21L 1 and 21L 21L2 is located on the side of the dug portion 33a (in the direction of arrow R1 shown in FIG.
  • the formation of the dug portion 33L and the formation of the dug portion 33a are performed in separate processes.
  • the dug portion 33L when forming the dug portion 33a, the dug portion 33L is not formed.
  • a cleaning process is performed in the same manner as in the comparative example.
  • a recessed portion 33L is not formed between the region 21b and the second region 21b of the other photoelectric conversion region 21L2. Therefore, in the cleaning process after forming the recessed portion 33a in the semiconductor layer 20, the photoelectric conversion regions 21L- 1 and 21L- 2 are prevented from bending (falling down) due to the capillary force (surface tension) caused by the evaporation of the cleaning liquid. can be done.
  • the manufacturing yield can be improved as compared with the comparative example 12-2.
  • the depth of the dug portion 33L can be made shallower than the depth of the dug portion 33a, and the inter-pixel isolation region 31 can be formed. It is possible to form the intra-cell inter-pixel isolation region 31L having a Z-direction length L 7 shorter than the Z-direction length L 8 (see FIG. 46). Further, the width of the dug portion 33L in the width direction can be narrower than the width of the dug portion 33a in the width direction, and is shorter than the width W8 of the inter-pixel isolation region 31 in the width direction. It is possible to form the intra-cell inter-pixel isolation region 31L having a narrow width W7 in the hand direction.
  • the solid-state imaging device 1L according to the twelfth embodiment like the solid-state imaging device 1A according to the above-described first embodiment, has an inter-pixel isolation region 31, an intra-cell inter-pixel isolation region 31L, and an intra-pixel isolation region 32. , is equipped with Therefore, in the solid-state imaging device 1L according to the twelfth embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, improvement of the quantum efficiency QE as a pixel characteristic and high color mixture suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixture suppression
  • the solid-state imaging device 1L according to the twelfth embodiment includes a light shielding film 54, like the solid-state imaging device 1A according to the above-described first embodiment. Therefore, in the solid-state imaging device 1L according to the twelfth embodiment as well, similarly to the solid-state imaging device 1A according to the above-described first embodiment, it is possible to suppress the arrival (irradiation) of light to the floating diffusion region FD. , the parasitic photosensitivity (PLS) can be improved.
  • PLS parasitic photosensitivity
  • the photoelectric conversion cell 16 in the photoelectric conversion cell 16 according to the twelfth embodiment, two photoelectric conversion regions 21L- 1 and 21L- 2 are arranged adjacent to each other in the Y direction, and the second region 21b of one photoelectric conversion region 21L- 1 and the other photoelectric conversion region 21L-1
  • the second region 21b of the conversion region 21L2 is provided adjacent to each other in the Y direction via the in-cell pixel isolation region 31L. Therefore, the light shielding film 54 can be continuously provided over the second regions 21b of the two photoelectric conversion regions 21L1 and 21L2 , and the two second regions 21b share one light shielding film 54. be able to.
  • the in-cell pixel isolation region 31L has insulation resistance and light shielding resistance. Therefore, compared to the inter-pixel isolation region 31, which requires both insulation resistance and light-shielding resistance to be emphasized, the lateral direction (the direction orthogonal to the extending direction) is reduced.
  • the width W7 can be narrow.
  • the width W7 of the intra-cell pixel separation region 31L can be narrowed, the pixel pitch in the Y direction can be narrowed, and the area of the pixel array portion can be reduced in the Y direction, or within the same area. , the number of pixels in the Y direction can be increased. This makes it possible to provide a compact image sensor with high resolution.
  • the area of the pixel array section can be reduced in each of the X direction and the Y direction.
  • the in-cell pixel separation region 31L can be replaced by the light shielding film 54 of the semiconductor layer 20. It can also be configured to be spaced apart from the second surface S2 on the side.
  • the recessed portion 33L that defines the Z-direction length L7 of the intra-cell isolation region 31L and the recessed portion 33a that defines the Z-direction length L8 of the inter-pixel isolation region 31 are formed in separate processes.
  • the photoelectric conversion regions 21L 1 and 21L 2 can be prevented from bending (falling down) due to capillary force (surface tension) caused by evaporation of the cleaning liquid in the cleaning process. Therefore, according to the manufacturing method of the solid-state imaging device 1L according to the twelfth embodiment, it is possible to improve the manufacturing yield.
  • the intra-cell pixel isolation region 31L including the insulating film 27 is used as the intra-cell pixel isolation region. It is not limited to the area 31L.
  • an in-cell pixel isolation region 31L1 including an n-type semiconductor region 58 having a conductivity type opposite to that of the p-type well region may be used.
  • a light shielding body 80H shown in FIG. 20 of the eighth embodiment can be used instead of the light shielding film 54.
  • the light shielding body 80H is provided outside the second surface S2 of the semiconductor layer 20, and is a first light shielding layer overlapping the second regions 21b of the two photoelectric conversion regions 21L1 and 21L2 in plan view.
  • the configuration includes a portion 82a and a second light shielding portion 82b projecting from the first light shielding portion 82a into the second region 21b of each of the two photoelectric conversion regions 21L1 and 21L2 .
  • a light shielding body 80I shown in FIG. 28 of the ninth embodiment can be used in place of the light shielding film 54.
  • the light shielding body 80I is provided outside the second surface S2 of the semiconductor layer 20, and is a first light shielding layer overlapping the second regions 21b of the two photoelectric conversion regions 21L1 and 21L2 in plan view.
  • the portion 82a overlaps the in-pixel separation region 32 of one of the two photoelectric conversion regions 21L1 and 21L2 in a plan view, and the light shielding portion 82a extends into the semiconductor layer 20 from the first light shielding portion 82a.
  • the projecting second light shielding portion 82c- 1 overlaps the intra-pixel isolation region 32 of the other photoelectric conversion region 21L- 2 of the two photoelectric conversion regions 21L -1 and 21L -2 in plan view, and is separated from the first light shielding portion 82a. and a second light shielding portion 82 c 2 protruding into the semiconductor layer 20 .
  • the light shielding body 80J shown in FIG. 32 of the tenth embodiment can be used instead of the light shielding film 54.
  • the light shielding member 80J is provided on the side of the insulating film 53 opposite to the semiconductor layer 20 side, and is the first region 21b that overlaps the second region 21b of each of the two photoelectric conversion regions 21L1 and 21L2 in plan view.
  • the light-shielding portion 82a overlaps the intra-pixel isolation region 32 of one of the two photoelectric conversion regions 21L -1 and 21L - 2 in a plan view, and the inside of the insulating film 53 extends from the first light-shielding portion 82a.
  • the second light-shielding portion 82d1 projecting toward the outside overlaps with the intra-pixel separation region 32 of the other of the two photoelectric conversion regions 21L -1 and 21L - 2 in plan view, and overlaps the pixel separation region 32 in plan view.
  • the light shielding film 54 can be combined with the light reflector 85K shown in FIG. 37B of the eleventh embodiment described above.
  • FIG. 55 is a plan view schematically showing a plane pattern of isolation regions (inter-pixel isolation regions and intra-pixel isolation regions) in the pixel array section of the solid-state imaging device according to the thirteenth embodiment.
  • 56 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a55-a55 of FIG. 55.
  • FIG. FIG. 57 is a longitudinal sectional view enlarging a part of FIG.
  • the inter-pixel separation region 31 corresponds to a specific example of the "first separation region” of the present technology
  • the intra-pixel separation region 32M is a specific example of the "second separation region” of the present technology.
  • the first insulator 58M1 and the second insulator 58M2 correspond to a specific example of the "insulator” of the present technology.
  • the dug portion 33a and the dug portion 33M correspond to specific examples of the "first dug portion” and the "second dug portion” of the present technology.
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to a specific example of "one direction" of the present technology.
  • a solid-state imaging device 1M according to the thirteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above. configuration is different. That is, as shown in FIGS. 55 to 57, the solid-state imaging device 1M according to the thirteenth embodiment has intra-pixel separation regions instead of the intra-pixel separation regions 32 shown in FIGS. 4 to 6 of the first embodiment. It has a region 32M. Other configurations are generally similar to those of the above-described first embodiment.
  • the intra-pixel isolation region 32M extends, for example, in the X direction in a plan view, and the inter-pixel isolation region 31 ( It is provided apart from the first portion 31x and the second portion 31y).
  • the intra-pixel separation region 32M is arranged so as to be closer to the inter-pixel separation region 31 side than the central portion of the photoelectric conversion region 21 in plan view, and the photoelectric conversion region 21 has a width in the Y direction in plan view. is selectively separated (partitioned) into two relatively different regions (first region 21a and second region 21b).
  • the first region 21a having the wider width in the Y direction is provided with the photoelectric conversion unit 24.
  • a floating diffusion region FD is provided in the second region 21b having a narrower width in the direction. That is, the intra-pixel separation region 32 separates the photoelectric conversion region 21 into a first region 21a and a second region 21b in one direction (Y direction).
  • the floating diffusion region FD is provided on the first surface S1 side of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 .
  • the in-pixel isolation region 32M extends in the thickness direction (Z direction) of the semiconductor layer 20, is connected to the element isolation region 25 at one end, and reaches the second surface S2 of the semiconductor layer 20 at the other end.
  • the in-pixel isolation region 32M of the thirteenth embodiment has a vertical sectional configuration different from that of the in-pixel isolation region 32 of the first embodiment.
  • the in-pixel isolation region 32M is provided along the inner side wall of the dug portion 33M extending in the thickness direction (Z direction) of the semiconductor layer 20, and has a refractive index higher than that of the semiconductor layer 20.
  • a conductive material 35 filled in the dug portion 33M via the insulator 58M is provided on the first region 21a side and the second region 21b side of the conductive material 35 in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21, respectively.
  • the insulator 58M on the first region 21a side of the conductive material 35 may be called a first insulator 58M1
  • the insulator 58M on the second region 21b side of the conductive material 35 may be called a second insulator 58M2 . be.
  • Each of the dug portion 33M, the conductive material 35, and the insulator 58 extends from the element isolation region 25 provided on the first surface side of the semiconductor layer 20 toward the second surface S2 of the semiconductor layer 20.
  • the conductive material 35 is electrically separated from the first region 21a in the Y direction via a first insulator 58M1 provided on the first region 21a side of the conductive material 35.
  • the conductive material 35 is electrically separated from the second region 21b in the Y direction via a second insulator 58M2 provided on the second region 21a side of the conductive material 35 .
  • the conductive material 35 of the intra-pixel isolation region 32M has the same configuration as the conductive material 35 of the above-described first embodiment. That is, one end side of the conductive material 35 of the intra-pixel isolation region 32M is also electrically connected to the wiring 43b1 through the contact electrode 42b1 .
  • the conductive material 35 of the intra-pixel isolation region 32M is also supplied with the second reference potential applied to the wiring 43b1 through the contact electrode 42b1 , and is fixed at this second reference potential.
  • the film thickness t1 of the first insulator 58M1 on the side of the first region 21a of the conductive material 35 is the second thickness on the side of the second region 21b of the conductive material 35. It is thicker than the film thickness t2 of the insulator 58M2 (t1>t2).
  • the film thickness t1 of the first insulator 58M1 between the conductive material 35 and the first region 21a in plan view is equal to the thickness t1 between the conductive material 35 and the second region 21b.
  • the thickness t1 of the first insulator 58M1 is set to about 50 nm
  • the thickness t2 of the second insulator 58M2 is set to about 10 nm.
  • the first insulator 58M1 includes, but is not limited to, a fixed charge film 52 and an insulating film 53 arranged in the Y direction from the first region 21a side to the second region 21b side, for example. , the fixed charge film 52 and the insulating film 36.
  • the second insulator 58M2 has, for example, a single layer structure including one isolation insulating film 34 in the Y direction.
  • Each of the insulating film 53, the isolation insulating film 34, and the insulating film 36 is composed of, for example, a silicon oxide film.
  • This silicon oxide film has a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs.
  • the fixed charge film 52 includes a film of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), or the like, as a dielectric film that generates negative fixed charges. These dielectric films have a lower refractive index than semiconductor materials such as Si, SiGe and InGaAs. Also, the film thickness of the fixed charge film 52 is much thinner than the film thickness of the insulating film 53 . In FIG. 57, the film thickness of the fixed charge film 52 is drawn thicker than the actual ratio in order to make the configuration of the fixed charge film 52 easier to understand. Therefore, the first insulator 58M1 including the fixed charge film 52 together with the insulating films 53 and 36 can be regarded as a layer having a lower refractive index than the semiconductor layer 20.
  • FIG. 1 hafnium oxide
  • ZrO 2 zirconium oxide
  • Ta 2 O 5 tantalum oxide
  • silicon has a refractive index of about 3.62
  • silicon oxide has a refractive index of about 1.45
  • air has a refractive index of about 1.45. It has a refractive index of about 00.
  • silicon has a refractive index of about 4.08
  • silicon oxide has a refractive index of about 1.46
  • air has a refractive index of about 1.46.
  • it has a refractive index of about 1.00.
  • the intra-pixel isolation region 32M and the inter-pixel isolation region 31 have different widths in the lateral direction. Specifically, the width W 9 of the intra-pixel isolation region 32M is wider than the width W 8 of the inter-pixel isolation region 31 (W 9 >W 8 ).
  • dug portions 33a and 33M extending from the first surface S1 of the semiconductor layer 20 toward the second surface S2 are formed in the semiconductor layer 20.
  • the dug portion 33a partitions the photoelectric conversion region 21L.
  • the dug portion 33M divides the photoelectric conversion region 21 into a first region 21a and a second region 21b arranged in the Y direction.
  • Each of the dug portions 33a and 33M can be formed by well-known photolithography technology and anisotropic dry etching technology.
  • the width in the lateral direction (Y direction) of the dug portion 33M is formed wider than the width in the lateral direction of the dug portion 33a.
  • the p-type well region 22 in the first region 21a of the photoelectric conversion region 21, the p-type well region 22, the n-type semiconductor region 23, the photoelectric conversion part 24 (PD), etc. are already formed.
  • a p-type well region 22 is already formed in the second region 21b of the photoelectric conversion region 21L.
  • a thinning step for thinning the thickness of the semiconductor layer 20 is performed. Therefore, the depth of each of the dug portions 33a and 33M in the Z direction (thickness direction of the semiconductor layer 20) is formed deeper than the thinning line S3 indicating the thickness of the semiconductor layer 20 performed in the thinning step. do.
  • the isolation insulating film 34 and the conductive material 35 are formed inside the dug portions 33a and 33M in this order.
  • the isolation insulating film 34 is formed with a film thickness extending along the sidewalls and bottom walls inside each of the dug portions 33a and 33M.
  • the isolation insulating film 34 is formed by depositing, for example, a silicon oxide film by the CVD method.
  • the conductive material 35 is formed in such a thickness that it fills the interior of the dug portion 33a and extends along the inner sidewall and bottom wall of the dug portion 33M.
  • the conductive material 35 is formed by depositing, for example, a doped polysilicon film into which impurities for reducing the resistance value are introduced by the CVD method.
  • the isolation insulating film 34 and the conductive material 35 are also formed on the first surface S ⁇ b>1 of the semiconductor layer 20 . In this step, the isolation insulating film 34, the conductive material 35, the space (clearance), and the conductive material 35 are formed inside the dug portion 33M from the first region 21a side of the photoelectric conversion region 21 toward the second region 21b side. and an isolation insulating film 34 are arranged side by side in a multi-layered manner.
  • the insulating film 36 is formed inside the dug portion 33M with the isolation insulating film 34 and the conductive material 35 interposed therebetween.
  • the insulating film 36 is formed by depositing a silicon oxide film by, for example, a CVD method so as to fill the inside of the dug portion 33M.
  • the insulating film 36 is also formed on the first surface S ⁇ b>1 of the semiconductor layer 20 .
  • the isolation insulating film 34, the conductive material 35, the insulating film 36, the conductive material 35, and the isolation insulating film are formed inside the dug portion 33M from the first region 21a side of the photoelectric conversion region 21 toward the second region 21b side.
  • the membranes 34 are arranged side by side in multiple layers.
  • the conductive material 35 on the first region 21a side is used as an assist electrode.
  • the isolation insulating film 34 on the side of the first region 21a is used as the second insulator 58M2 .
  • the first insulating film 34 and the conductive material 35 of the semiconductor layer 20 are left in each of the dug portions 33a and 33M.
  • Each of the insulating film 36, the conductive material 35 and the isolation insulating film 34 on the surface S1 is selectively removed.
  • the insulating film 36, the conductive material 35, and the isolation insulating film 34 can be selectively removed by the CMP method or the etchback method.
  • the element formation region 20 a is partitioned by the element isolation region 25 and formed in the first region 21 a of the photoelectric conversion region 21 .
  • a shallow trench (field trench) 26 recessed from the first surface S1 of the semiconductor layer 20 toward the second surface S2 is formed, and then the semiconductor layer 20 including the inside of the shallow trench 26 is formed.
  • An insulating film 27 made of, for example, a silicon oxide film is formed on the entire surface of the first surface S1 of the semiconductor layer 20, and then the first surface S1 of the semiconductor layer 20 is subjected to the CMP method so that the insulating film 27 remains inside the shallow groove portion 26. It can be formed by selectively removing the upper insulating film 27 .
  • the insulating film 27 for example, a silicon oxide film having a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs can be used.
  • the element isolation region 25 is formed so as to overlap each of the dug portion 33a and the dug portion 33M in plan view.
  • pixel transistors (AMP, SEL, RST, TRG) are formed in the element formation region 20a, and as shown in FIG. , the floating diffusion region FD is formed in the second region 21 b of the photoelectric conversion region 21 .
  • the floating diffusion region FD is formed on the first surface S1 side of the semiconductor layer 20 in the second region 21b of the photoelectric conversion region 21 .
  • the multilayer wiring layer 40 is formed on the first surface S1 side of the semiconductor layer 20.
  • the semiconductor layer 20 is turned upside down, and the second surface S2 side of the semiconductor layer 20 is cut by, for example, the CMP method to reduce the thickness of the semiconductor layer 20, thereby performing a thinning step.
  • the isolation insulating film 34 and the conductive material 35 inside the dug portion 33a are exposed, and the isolation insulating film 34 and the conductive material 35 inside the dug portion 33M are exposed.
  • the thinning of the semiconductor layer 20 is performed up to the thinning line S3 shown in FIG. 59F.
  • the diffraction scattering portion 51 is formed on the second surface S2 side of the semiconductor layer 20, and the separation and insulation inside the dug portion 33a is performed.
  • the film 34, the conductive material 35, and the isolation insulating film 34 and the conductive material 35 on the side of the first region 21a inside the dug portion 33M are selectively removed.
  • the step of forming the diffraction scattering portion 51 is performed separately from the removing step of selectively removing the isolation insulating film 34 and the conductive material 35, but both steps may be performed first.
  • the isolation insulating film 34 and the conductive material 35 can be selectively removed by using well-known photolithography technology and anisotropic dry etching technology. In this process, the second region 21b side of the insulating film 36 inside the dug portion 33M is etched, and the film thickness is slightly reduced.
  • a fixed charge film 52 is formed.
  • the fixed charge film 52 is formed on the side of the second surface S2 of the semiconductor layer 20 over the first region 21a and the second region 21b of the photoelectric conversion region 21, and is formed on the sidewalls inside each of the dug portions 33a and 33M. and along the unevenness of the bottom wall and the diffraction/scattering portion 51 .
  • an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the insides of the dug portions 33a and 33M.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by the CVD method and then cutting the surface side of the silicon oxide film by the CMP method to planarize it.
  • the inter-pixel isolation region 31 including the fixed charge film 52 and the insulating film 53 is formed inside the dug portion 33a.
  • the conductive material 35 side is multi-layered from the conductive material 35 side toward the second region 21a side.
  • a first insulator 58M1 is formed which includes the insulating film 36, the fixed charge film 52, the insulating film 53 and the fixed charge film 52 which are arranged in sequence and which has a thickness t1 greater than the thickness t2 of the second insulator 58M2.
  • an intra-pixel isolation region 32M including a first insulator 58M 1 , a conductive material 35 and a second insulator 58M 2 sequentially arranged in multiple layers from the first region 21a side to the second region 21b side is formed. Further, in this process, the intra-pixel isolation region 32M is formed so that the width W9 in the lateral direction is wider than the width W8 of the inter-pixel isolation region 31 in the lateral direction.
  • a light shielding film 54 is formed on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the light shielding film 54 is formed so as to overlap the second region 21b of the photoelectric conversion region 21L.
  • a color filter 55 and a microlens 56 are formed in this order on the opposite side of the light shielding film 54 from the semiconductor layer 20 side, resulting in the states shown in FIGS. 44 to 46B.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • FIG. FIG. 58 shows the light reflectance at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the intra-pixel isolation region 32M, and the optical reflectivity of the first insulator 58M1 on the side of the first region 21a of the intra-pixel isolation region 32M. It is a figure which shows correlation with the film thickness t1.
  • the reflectance on the vertical axis is the reflectance when the interface If1 between the first region 21a of the photoelectric conversion region 21 and the intra-pixel separation region 32M is irradiated with incident light at 45° to 85°.
  • B is data of light in the blue wavelength band
  • G is data of light in the green wavelength band
  • R is data of light in the red wavelength band
  • NIR is the near-infrared wavelength band.
  • the photoelectric conversion region 21 is made of a semiconductor material (for example, silicon) that absorbs light, and generally has a large (high) refractive index. Thus, in the case of light reflection with a large incident angle in a high refractive index medium, the total reflection condition is satisfied.
  • the evanescent component is transmitted and enters the second region 21b side, but the conductive material 35 As the film thickness t1 of the first insulator 58M1 on the side of the first region 21a of is thicker, the evanescent component becomes smaller.
  • the intra-pixel isolation region 32M applies a positive potential to the conductive material 35 of the intra-pixel isolation region 32M when transferring the signal charge photoelectrically converted by the photoelectric conversion unit 24 to the floating diffusion region FD, thereby isolating the pixel.
  • the potential of the semiconductor layer 20 on the side wall of the region 32M it functions as an assist electrode (transfer performance in the second region 21b) that assists the transfer of the signal charge to the floating diffusion region FD.
  • the thickness t1 of the first insulator 58M1 located on the first region 21a side of the conductive material 35 is greater than the thickness t2 of the second insulator 58M2 located on the second region 21b side of the conductive material 35.
  • the light reflectance at the interface If1 is improved depending on the film thickness t1 of the first insulator 58M1.
  • the improvement in light reflectance is saturated when the film thickness t1 of the first insulator 58M1 is around 50 nm.
  • the thicker the film thickness t1 of the first insulator 58M1 the better. Since it becomes smaller, it affects the decrease in sensitivity. Therefore, the film thickness t1 of the first insulator 58M1 is preferably about 50 nm.
  • the difference between the film thickness t1 of the first insulator 58M1 and the film thickness t2 of the second insulator 58M2 is different from the dimensional error due to processing variations during the manufacturing process.
  • the first insulator 58M1 includes the fixed charge film 52.
  • a silicon nitride ( Si3N4 ) film, an air layer, or the like is used. Even when a dielectric is included, the same effect of improving the light reflectance can be obtained.
  • the solid-state imaging device 1M according to the thirteenth embodiment includes an inter-pixel isolation region 31 and an intra-pixel isolation region 32M, similarly to the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1M according to the thirteenth embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, improvement of the quantum efficiency QE as a pixel characteristic and high color mixing suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixing suppression
  • the solid-state imaging device 1L according to the thirteenth embodiment includes a light shielding film 54, like the solid-state imaging device 1A according to the above-described first embodiment. Therefore, in the solid-state imaging device 1M according to the twelfth embodiment as well, similarly to the solid-state imaging device 1A according to the above-described first embodiment, it is possible to suppress the arrival (irradiation) of light to the floating diffusion region FD. , the parasitic photosensitivity (PLS) can be improved.
  • PLS parasitic photosensitivity
  • the film thickness t1 of the first insulator 58M1 on the first region 21a side of the conductive material 35 is the second thickness on the second region 21b side of the conductive material 35. It is thicker than the film thickness t2 of the insulator 58M2 .
  • the light reflectance at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the intra-pixel isolation region 32M is improved, so that the light is absorbed by the photoelectric conversion portion 24 (PD) of the first region 21a.
  • the amount of light can be increased, the quantum efficiency QE (sensitivity) can be improved, the intrusion of light into the second region 21b can be suppressed, and the arrival (irradiation) of light to the floating diffusion region FD can be suppressed. be able to. Therefore, according to the solid-state imaging device 1M according to the thirteenth embodiment, it is possible to further improve the parasitic light sensitivity characteristic (PLS) in addition to the improvement effect of the parasitic light sensitivity characteristic due to the light shielding of the light shielding film 54. In addition, the quantum efficiency QE (sensitivity) can be improved.
  • PLS parasitic light sensitivity characteristic
  • solid-state imaging device 1M including the fixed charge film 52 has been described in the above-described thirteenth embodiment, the present technology can also be applied to a solid-state imaging device 1M that does not include the fixed charge film.
  • FIG. 61 is a plan view schematically showing a planar pattern of isolation regions (inter-pixel isolation regions 31 and intra-pixel isolation regions 32) in the pixel array section 2A of the solid-state imaging device 1N according to the fourteenth embodiment of the present technology.
  • . 62 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a61-a61 of FIG. 61.
  • FIG. FIG. 63 is a longitudinal cross-sectional view in which a part of FIG. 62 is enlarged and turned upside down.
  • FIG. 64 is a diagram schematically showing the interference between the reflected light 57N1 reflected by the intra-pixel isolation region 32 and the return light 57N2 reflected by the inter-pixel isolation region 31.
  • a solid-state imaging device 1N according to the fourteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment.
  • the configuration of the conversion area 21 is different. That is, the photoelectric conversion region 21 shown in FIGS. 61 and 62 of the fourteenth embodiment has a second The width Wb of the region 21b in the Y direction is set, and the width Wb of the second region 21b is the width at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32. Designed to increase light reflectance.
  • the width Wb of the second region 21b in the Y direction is the width along the arrangement direction of the first region 21a and the second region 21a of the photoelectric conversion region 21 .
  • incident light 57N that has entered (entered) the first region 21a of the photoelectric conversion region 21 from the second surface S2 of the semiconductor layer 20 is separated from the first region 21a in the pixel. It corresponds to the interface portion If 1 with the region 32 (side wall of the intra-pixel isolation region 32 on the side of the first region 21a).
  • the incident light 57N that hits the interface If1 includes reflected light 57N1 that is reflected by the interface If1 and light that passes through the intra-pixel isolation region 32 and is further reflected by the inter-pixel isolation region 31. and return light 57N2 returning to the first region 21a.
  • the photoelectric conversion units 24 photoelectrically convert near-infrared light (NIR) with a wavelength of 800 nm into signal charges. As shown in FIGS.
  • the solid-state imaging device 1N according to the fourteenth embodiment does not include the color filters 55 shown in FIGS. 5 and 6 of the first embodiment.
  • the solid-state imaging device 1N according to the fourteenth embodiment includes a flattening film 59 provided between the insulating film 53 and the microlens 56 so as to cover the light shielding film 54 .
  • FIG. 65 shows the width Wb of the second region 21b of the photoelectric conversion region 21 and the side wall of the intra-pixel separation region 32 on the side of the first region 21a (the first region 21a of the photoelectric conversion region 21 and the intra-pixel width Wb).
  • FIG. 10 is a diagram showing the correlation between the light reflectance at the interface If 1 ) with the side wall of the isolation region 32; The relationship between the width Wb of the second region 21b of the photoelectric conversion region 21 and the light reflectance at the interface If1 is as shown in FIG .
  • the width Wb of 21b is maximum at 350 nm.
  • the width Wb of the second region 21b of the photoelectric conversion region 21 so that the phase difference between the reflected light 57N- 1 and the return light 57N -2 is an integral multiple ( ⁇ /4n) of the incident light 57N, , the light reflectance of the incident light 57N at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32 can be increased.
  • the light reflectance at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32 can be increased, the The light component absorbed by the photoelectric conversion unit 24 (PD) increases, and the sensitivity of the solid-state imaging device 1N can be improved.
  • the light reflectance at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32 can be increased, the light to the floating diffusion region FD provided in the second region can be increased.
  • the arrival (irradiation) of the incident light 57N can be suppressed, and together with the effect of improving the parasitic light sensitivity characteristic due to the light blocking by the light shielding film 54, the parasitic light sensitivity characteristic (PLS) can be further improved.
  • the intra-pixel isolation region 32 has a configuration in which isolation insulating films 34 are provided on the first region 21a side and the second region 21b side of the conductive material 35, respectively.
  • This isolation insulating film 34 can be regarded as a single insulator, as in the thirteenth embodiment described above. Therefore, the intra-pixel isolation region 32 has a structure in which the conductive material 35 is provided via an insulator including the isolation insulating film 34 on each of the first region side and the second region side inside the dug portion 33b. ing.
  • the solid-state imaging device 1N that photoelectrically converts near-infrared light has been mainly described.
  • An example in which the present technology is applied to a solid-state imaging device that photoelectrically converts infrared light will be described.
  • FIG. 66 is a plan view schematically showing a planar pattern of isolation regions (inter-pixel isolation regions 31 and intra-pixel isolation regions 32) in the pixel array section 2A of the solid-state imaging device 1P according to the fifteenth embodiment of the present technology.
  • . 67 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a66-a66 of FIG. 66.
  • FIG. 68 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line b66-b66 of FIG. 66.
  • FIG. FIG. 69 is a plan view schematically showing the planar pattern of the light shield.
  • a solid-state imaging device 1P according to the fifteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, and pixels The configuration of the array section 2A is different.
  • the pixel array section 2A of the fifteenth embodiment includes a plurality of photoelectric conversion regions 21 arranged corresponding to a plurality of pixels 3 arranged in a matrix.
  • the plurality of photoelectric conversion regions 21 includes two or more types of photoelectric conversion regions 21 having different widths in the Y direction of the second regions 21b.
  • the fifteenth embodiment includes four types of photoelectric conversion regions 21 (21P 1 , 21P 2 , 21P 3 , 21P 4 ) having different widths in the Y direction of the second regions 21b.
  • the photoelectric conversion region 21P1 shown in FIGS. 66 and 67 photoelectrically converts light of red (R) wavelength by the photoelectric conversion portion 24 (PD) of the first region 21a.
  • the Y direction of the second region 21b is increased so as to increase the light reflectance of red wavelength light reflected at the interface If1 between the first region 21a and the side wall of the intra-pixel isolation region 32.
  • width Wb 1 is set.
  • the photoelectric conversion region 21P2 shown in FIGS. 66 and 67 photoelectrically converts green (G) wavelength light by the photoelectric conversion unit 24 (PD) of the first region 21a.
  • the Y direction of the second region 21b is increased so as to increase the light reflectance of green wavelength light reflected at the interface If1 between the first region 21a and the side wall of the intra-pixel isolation region 32.
  • width Wb2 is set. The width Wb2 of the second region 21b of the photoelectric conversion region 21P2 is smaller than the width Wb1 of the second region 21b of the photoelectric conversion region 21P1 ( Wb2 ⁇ Wb1 ).
  • the photoelectric conversion region 21P3 shown in FIGS. 66 and 68 photoelectrically converts blue (B) wavelength light by the photoelectric conversion unit 24 (PD) of the first region 21a.
  • the Y direction of the second region 21b is increased so as to increase the light reflectance of blue wavelength light reflected at the interface If1 between the first region 21a and the side wall of the intra-pixel separation region 32.
  • width Wb 3 is set.
  • the width Wb3 of the second region 21b of the photoelectric conversion region 21P3 is smaller than the width Wb2 of the second region 21b of the photoelectric conversion region 21P2 ( Wb3 ⁇ Wb2 ).
  • the photoelectric conversion region 21P4 shown in FIGS. 66 and 68 photoelectrically converts near-infrared light (NIR) with the photoelectric conversion portion 24 (PD) of the first region 21a.
  • NIR near-infrared light
  • the Y direction of the second region 21b is increased so as to increase the light reflectance of near-infrared light reflected at the interface If1 between the first region 21a and the side wall of the intra-pixel isolation region 32.
  • width Wb 4 is set.
  • the width Wb4 of the second region 21b of the photoelectric conversion region 21P4 is smaller than the width Wb3 of the second region 21b of the photoelectric conversion region 21P2 ( Wb4 ⁇ Wb3 ).
  • each of the photoelectric conversion regions 21P 1 to 21P 4 has a width (Wb 1 , Wb 2 , Wb 3 , Wb 4 ) of the second region 21b so that the light reflectance at the interface If 1 is high. is set.
  • Each of the photoelectric conversion regions 21P 1 to 21P 4 has a different width of the second region 21b (Wb 1 >Wb 2 >Wb 3 >Wb 4 ).
  • the light reflectance at the interface If 1 of each of the photoelectric conversion regions 21P 1 to 21P 4 will be described with reference to FIG. 64 of the fourteenth embodiment described above.
  • the widths (Wb 1 , Wb 2 , Wb 3 , Wb 3 , Wb 1 , Wb 2 , Wb 3 , Wb 4 ) increases the light reflectance at the interface If 1 between the first region 21 a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32 .
  • FIG. 70 shows the width (Wb 1 , Wb2, Wb 3 , Wb 4 ) and the side wall of the intra-pixel isolation region 32 on the side of the first region 21 a (interface portion If 1 between the first region 21 a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 21 b)
  • FIG. 10 is a diagram showing the correlation with light reflectance at .
  • the photoelectric conversion regions 21P 1 to 21P 4 the relationship between the widths (Wb 1 , Wb 2 , Wb 3 , Wb 4 ) of the second regions 21b and the light reflectance at the interface If 1 is as shown in FIG.
  • the light reflectance of the interface If1 in the photoelectric conversion region 21P1 is maximum when the width Wb1 of the second region 21b is 400 nm.
  • the light reflectance of the interface If1 in the photoelectric conversion region 21P2 is maximum when the width Wb2 of the second region 21b is 390 nm.
  • the light reflectance of the interface If1 in the photoelectric conversion region 21P3 is maximum when the width Wb3 of the second region 21b is 360 nm.
  • the light reflectance of the interface If1 in the photoelectric conversion region 21P4 is maximum when the width Wb4 of the second region 21b is 400 nm. It has become.
  • the phase difference between the reflected light 57N1 and the return light 57N2 is an integral multiple ( ⁇ /4n) of the incident light 57N.
  • the widths (Wb 1 , Wb 2 , Wb 3 , Wb 4 ) of the two regions 21b the incidence at the interface If 1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32
  • the light reflectance of the light 57N can be increased.
  • the Y-direction widths (Wb 1 , Wb 2 , Wb 3 , Wb 4 ) of the second regions 21b are different.
  • the light reflectance at the interface If1 between the first region 21a and the sidewall of the intra-pixel isolation region 32 can be increased.
  • the light component absorbed by the photoelectric conversion unit 24 (PD) provided in 21a increases, and the sensitivity of the solid-state imaging device 1P can be improved.
  • the light reflectance at the interface If1 between the first region 21a of the photoelectric conversion region 21 and the side wall of the intra-pixel isolation region 32 can be increased, the light to the floating diffusion region FD provided in the second region can be increased.
  • the arrival (irradiation) of the incident light 57N can be suppressed, and together with the effect of improving the parasitic light sensitivity characteristic due to the light blocking by the light shielding film 54, the parasitic light sensitivity characteristic (PLS) can be further improved.
  • the Y-direction width of the light-shielding film 54 is also the Y-direction width ( Wb 1 , Wb 2 , Wb 3 , Wb 4 ) is preferably varied differently.
  • the width of the second region 21b of each of the photoelectric conversion regions 21P1 to 21P4 satisfies Wb1 > Wb2 > Wb3 > Wb4 .
  • the width of the film 54 is Ws1
  • the width of the light shielding film 54 in the photoelectric conversion region 21P2 is Ws2
  • the width of the light shielding film 54 in the photoelectric conversion region 21P3 is Ws3
  • the width of the light shielding film 54 in the photoelectric conversion region 21P4 is Ws3 .
  • the widths of the light shielding films 54 of the photoelectric conversion regions 21p1 to 21p4 are Wb1 > Wb2 > Wb3 > Wb4 .
  • the intra-pixel isolation region 32 has the isolation insulating film 34 on the first region 21a side and the second region 21b side of the conductive material 35, respectively. It has a set configuration.
  • This isolation insulating film 34 can be regarded as a single insulator, as in the thirteenth embodiment described above. Therefore, the intra-pixel isolation region 32 has a configuration in which the conductive material 35 is provided via an insulator including the isolation insulating film 34 on each of the first region side and the second region side inside the dug portion 33b.
  • the solid-state imaging device 1P including the intra-pixel isolation region 32 as the second isolation region has been described. It can also be applied to a solid-state imaging device including
  • FIG. 71 is a plan view schematically showing a plane pattern of separation regions in a pixel array section of a solid-state imaging device according to a sixteenth embodiment of the present technology; 72 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a71-a71 of FIG. 71.
  • FIG. FIG. 73 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure along line b71-b71 of FIG.
  • the inter-pixel separation region 31 corresponds to a specific example of the "first separation region” of the present technology
  • the intra-pixel separation region 32 corresponds to a specific example of the "second separation region” of the present technology.
  • the dug portion 33a, the dug portion 33b, and the dug portion 33Q correspond to the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology. It corresponds to a specific example of "part".
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to a specific example of "one direction" of the present technology
  • the protrusion 31Q corresponds to the "one direction” of the present technology. It corresponds to a specific example of "dielectric”.
  • a solid-state imaging device 1Q according to the sixteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above. configuration is different. That is, as shown in FIGS. 71 to 73 , the solid-state imaging device 1Q according to the sixteenth embodiment of the present technology has a dielectric as a dielectric projecting from the intra-pixel isolation region 32 toward the second region 21b of the photoelectric conversion region 21. A protrusion 31Q is further provided. Other configurations are generally similar to those of the above-described first embodiment.
  • the protrusions 31Q are repeatedly provided at a predetermined arrangement pitch in the longitudinal direction (X direction) in which the intra-pixel isolation regions 32 extend on a two-dimensional plane. That is, protrusions 31Q projecting from the in-pixel isolation region 32 are scattered along the longitudinal direction of the in-pixel isolation region 32 on the side of the in-pixel isolation region 32 of the second region 21b. In other words, the second region 21b side of the intra-pixel isolation region 32 has an uneven shape with recesses between the protrusions 31Q.
  • the projecting portion 31Q is formed inside the dug portion 33Q extending in the thickness direction (Z direction) of the semiconductor layer 20 along the inner wall (side wall and bottom wall) of the dug portion 33Q. It includes a fixed charge film 52 provided and an insulating film 53 provided inside the dug portion 33Q with the fixed charge film 52 interposed therebetween.
  • the protrusion 31Q extends in the thickness direction (Z direction) of the semiconductor layer 20, is connected to the element isolation region 25 at one end, and reaches the second surface S2 of the semiconductor layer 20 at the other end.
  • the protrusion 31Q has the same structure as the inter-pixel isolation region 31 in vertical section.
  • the dug portion 33Q is connected to and integrated with the dug portion 33b of the intra-pixel isolation region 32. As shown in FIG.
  • the fixed charge film 52 is provided over the inter-pixel separation region 31, the diffraction diffusion portion 51 and the projection portion 31Q.
  • the fixed charge film 52 of the protrusion 31Q is located on the in-pixel isolation region 32 side and the second region 21b side of the insulating film 53 in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21. is provided.
  • the fixed charge films 52 of the projecting portion 31Q are provided on both sides of the insulating film 53 in the longitudinal direction (X direction) of the intra-pixel isolation region 32 in plan view.
  • the fixed charge films 52 of the projecting portion 31Q are provided on both sides in the X direction and both sides in the Y direction of the insulating film 53 in plan view, and surround the insulating film 53 .
  • the fixed charge film 52 of the projecting portion 31Q is located on three sides of the insulating film 53 in the X direction and the Y direction in a plan view, excluding the first region 21a side (in-pixel isolation region 32 side). next to each other.
  • Reference numeral 57Q in FIG. 71 denotes a charge transfer path through which the transfer transistor TRG transfers signal charges from the first region 21a to the second region 21b.
  • the width in the Y direction of the second region of the photoelectric conversion region 21 is narrower where there is no projection 31Q than where it is.
  • the steps similar to those of the eighth embodiment are performed to form the diffraction/scattering portion 51 on the second surface S2 of the semiconductor layer 20 in the first region 21a of the photoelectric conversion region 21. do.
  • the diffraction/scattering portion 51 As shown in FIG. It is formed on the second surface S2 side using, for example, a photolithographic technique.
  • the photoelectric conversion region 21 is covered with a mask M3 on the second surface S2 side of the semiconductor layer 20 except for a part of the second region 21b.
  • the second region 21b exposed from the opening M3a of the mask M3 is selectively etched to form a dug portion as shown in FIG. 74C.
  • 33Q is formed.
  • the dug portion 33Q protrudes from the in-pixel isolation region 32 toward the second region 21b of the photoelectric conversion region 21 and reaches the element isolation region 25 on the first surface S1 side from the second surface S2 side of the semiconductor layer 20. formed at a depth that
  • a plurality of dug portions 33Q are formed so as to be scattered in the longitudinal direction (X direction) of the intra-pixel isolation region 32.
  • the dug portion 33Q is formed integrally with the dug portion 33b of the intra-pixel isolation region 32 so that the isolation insulating film 34 of the intra-pixel isolation region 32 is exposed from the inside of the dug portion 33Q. do.
  • a mask M4 having an opening portion M4a exposing the isolation insulating film 34 and the conductive material 35 inside the dug portion 33a is applied to the second semiconductor layer 20. Then, as shown in FIG. It is formed on the surface S2 side using, for example, a photolithographic technique. In each of the first region 21a and the second region 21b of the photoelectric conversion region 21, the second surface S2 side of the semiconductor layer 20 is covered with the mask M4, and the inside of the dug portion 33Q is partially filled with the mask M4. .
  • the isolation insulating film 34 and the conductive material 35 inside the dug portion 33a are selectively removed.
  • the isolation insulating film 34 and the conductive material 35 inside the dug portion 33a can be selectively removed by well-known photolithography technology and anisotropic dry etching technology.
  • a fixed charge film 52 covering S2 is formed.
  • the fixed charge film 52 is formed over the first region 21a and the second region 21b of the photoelectric conversion region 21 on the second surface S2 side of the semiconductor layer 20. Covered with membrane 52 .
  • an insulating film 53 is formed on the entire surface of the semiconductor layer 20 on the second surface S2 side including the insides of the dug portions 33a and 33Q.
  • the insulating film 53 can be formed, for example, by forming a silicon oxide film by a CVD method and then planarizing the surface side of the silicon oxide film by cutting it by a CMP method.
  • the inter-pixel isolation region 31 in which the insulating film 53 is embedded through the fixed charge film 52 is formed inside the dug portion 33a, and the inter-pixel isolation region 31 partitions the periphery and the interior.
  • the insulating film 53 protrudes from the in-pixel isolation region 32 toward the second region 21b of the photoelectric conversion region 21 in a plan view, and is embedded in the trench 33Q with the fixed charge film 52 interposed therebetween. A protrusion 31Q is formed.
  • a light-shielding film 54, a color filter 55, a microlens 56, and the like are formed in this order on the side of the insulating film 53 opposite to the semiconductor layer 20 side.
  • the state shown in FIG. 32 is obtained.
  • the state of the semiconductor chip 2 shown in FIG. 1 is obtained by dividing the semiconductor wafer including the semiconductor layer 20 and the multilayer wiring layer 40 for each chip formation region.
  • the solid-state imaging device 1Q according to the sixteenth embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32, like the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1Q according to the sixteenth embodiment, similarly to the solid-state imaging device 1A according to the above-described first embodiment, improvement of the quantum efficiency QE as a pixel characteristic and high color mixing suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixing suppression
  • the solid-state imaging device 1Q includes a light shielding film 54 provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have. Therefore, as in the solid-state imaging device 1A of the first embodiment described above, the second region 21b of the photoelectric conversion region 21 enters the second region 21b from the second surface S2 side (light incident surface side) of the semiconductor layer 20.
  • the light shielding film 54 shields the light from reaching the floating diffusion region FD, and the parasitic light sensitivity characteristic (PLS) can be improved.
  • the solid-state imaging device 1Q includes projections 31Q projecting from the intra-pixel isolation region 32 toward the second region 21b side of the photoelectric conversion region 21 in plan view.
  • the projecting portion 31Q has an insulating film 53 provided in a recessed portion 33Q extending in the thickness direction of the semiconductor layer 20 with a fixed charge film 52 interposed therebetween. Therefore, in the second region 21b of the photoelectric conversion region 21, the area of the fixed charge film 52 adjacent to (facing) the semiconductor layer 20 can be increased, and the signal charge can be temporarily transferred in the second region 21b of the photoelectric conversion region 21. It is possible to increase the charge storage capacity that is effectively held.
  • the present technology is also effective in realizing a high-resolution image sensor.
  • the projection 31Q is located on the opposite side of one of the ends in the longitudinal direction (X direction) of the intra-pixel isolation region 32 in a plan view, where the transfer transistor TRG is provided. may be provided at the other end of the
  • FIG. 76 is a plan view schematically showing a plane pattern of separation regions in the pixel array section of the solid-state imaging device according to the seventeenth embodiment of the present technology; 77 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a76-a76 of FIG. 76.
  • FIG. 78 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line b76-b76 of FIG. 76.
  • the inter-pixel separation region 31 corresponds to a specific example of the "first separation region” of the present technology
  • the intra-pixel separation region 32 corresponds to a specific example of the "second separation region” of the present technology.
  • the dug portion 33a, the dug portion 33b, and the dug portion 33R correspond to the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology. It corresponds to a specific example of "part".
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to a specific example of "one direction" of the present technology
  • the protrusion 31R corresponds to the "one direction” of the present technology. It corresponds to a specific example of "dielectric”.
  • a solid-state imaging device 1R according to the seventeenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1Q according to the sixteenth embodiment described above. configuration is different. That is, as shown in FIGS. 76 to 78, in the solid-state imaging device 1R according to the seventeenth embodiment of the present technology, in the photoelectric conversion region 21, the pixel A protrusion 31R that protrudes from the separation region 31 toward the second region 21b is further provided. Other configurations are generally similar to those of the sixteenth embodiment described above.
  • the protrusions 31R are repeatedly provided at a predetermined arrangement pitch in the longitudinal direction (X direction) in which the inter-pixel separation regions 31 extend on a two-dimensional plane. That is, in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21, on the inter-pixel separation region 31 side of the second region 21b, the second region 21b side from the inter-pixel separation region 31 Projections 31 ⁇ /b>R that protrude outward are scattered along the longitudinal direction (X direction) of the inter-pixel separation region 31 . In other words, the second region 21b side of the inter-pixel separation region 31 has an uneven shape with recesses between the protrusions 31R.
  • the projecting portion 31R is a fixed charge film 52 provided along the inner wall (side wall and bottom wall) inside the dug portion 33R extending in the thickness direction (Z direction) of the semiconductor layer 20. and an insulating film 53 provided inside the dug portion 33R with a fixed charge film 52 interposed therebetween.
  • the fixed charge film 52 of the protrusion 31R is integrated with the fixed charge film 52 of the inter-pixel separation region 31 and formed continuously.
  • the insulating film 53 of the protrusion 31R is also integrated with the insulating film 53 of the inter-pixel isolation region 31 and formed continuously.
  • the protrusion 31 ⁇ /b>R extends in the thickness direction (Z direction) of the semiconductor layer 20 , is connected to the element isolation region 25 at one end, and reaches the second surface S ⁇ b>2 of the semiconductor layer 20 at the other end.
  • the dug portion 33R is connected to and integrated with the dug portion 33a of the inter-pixel isolation region 31. As shown in FIG.
  • the fixed charge film 52 is provided over the inter-pixel separation region 31, the diffraction diffusion portion 51, and the protrusions 31Q and 31R.
  • the fixed charge film 52 of the protrusion 31R is provided on the second region 21b side of the insulating film 53 in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21 .
  • the fixed charge films 52 of the projecting portion 31R are provided on both sides of the insulating film 53 in the longitudinal direction (X direction) of the inter-pixel separation region 31 in plan view. That is, the fixed charge film 52 of the projecting portion 31R is adjacent to the semiconductor layer 20 in three of the four directions in the X and Y directions of the insulating film 53 in plan view, excluding the inter-pixel isolation region 31 side. ing).
  • the second region 21b of the photoelectric conversion region 21 is can further increase the charge storage capacity at .
  • the protrusion 31R is provided in the inter-pixel separation region 31 on the side opposite to the intra-pixel separation region 32 side of the second region 21b of the photoelectric conversion region 21 .
  • the protrusion 31 ⁇ /b>R may be the second region 21 b of the photoelectric conversion region 21 .
  • the protrusion 31R is the other end of the longitudinal direction (X direction) of the in-pixel isolation region 32 in plan view, which is opposite to the one end provided with the transfer transistor TRG in plan view. It may be provided in the inter-pixel isolation region 31 adjacent to the part.
  • FIG. 79 is a plan view schematically showing a plane pattern of separation regions in the pixel array section of the solid-state imaging device according to the eighteenth embodiment of the present technology; 80 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a79-a79 of FIG. 79.
  • FIG. 79 is a plan view schematically showing a plane pattern of separation regions in the pixel array section of the solid-state imaging device according to the eighteenth embodiment of the present technology
  • 80 is a longitudinal sectional view schematically showing the longitudinal sectional structure along line a79-a79 of FIG. 79.
  • the inter-pixel isolation region 31 corresponds to a specific example of the "first isolation region” of the present technology
  • the intra-pixel isolation region 32 corresponds to a specific example of the "second isolation region” of the present technology.
  • the dug portion 33a, the dug portion 33b, and the dug portion 33S are the “first dug portion”, the “second dug portion”, and the “third dug portion” of the present technology. It corresponds to a specific example of "part".
  • the arrangement direction of the first regions 21a and the second regions 21b of the photoelectric conversion regions 21 corresponds to a specific example of "one direction" of the present technology
  • the island portion 31S corresponds to the "one direction” of the present technology. It corresponds to a specific example of "dielectric".
  • the solid-state imaging device 1S according to the eighteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1R according to the seventeenth embodiment described above. configuration is different. That is, as shown in FIGS. 79 and 80, in the solid-state imaging device 1S according to the eighteenth embodiment of the present technology, in the photoelectric conversion region 21, islands separated from each of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 A portion 31S is further provided. Other configurations are generally similar to those of the seventeenth embodiment described above.
  • the island portion 31S is one of the two ends in the longitudinal direction (X direction) of the in-pixel isolation region 32 in plan view, where the transfer transistor TRG is provided. and the inter-pixel isolation region 31 adjacent to the other end.
  • the island portion 31S is formed by the fixed charge film 52 provided along the inner wall (side wall and bottom wall) inside the dug portion 33S extending in the thickness direction (Z direction) of the semiconductor layer 20. and an insulating film 53 provided inside the dug portion 33S with a fixed charge film 52 interposed therebetween.
  • the fixed charge film 52 of the island portion 31S is integrated with the fixed charge film 52 of each of the inter-pixel isolation region 31 and the intra-pixel isolation region 32 and formed continuously.
  • the island portion 31S is separated from the recessed portions 33a and 33b of the inter-pixel isolation region 31 and the intra-pixel isolation region 32, respectively.
  • the island portion 31S extends in the thickness direction (Z direction) of the semiconductor layer 20, is connected to the element isolation region 25 at one end, and reaches the second surface S2 of the semiconductor layer 20 at the other end.
  • the fixed charge film 52 is provided over the inter-pixel separation region 31, the diffraction diffusion portion 51, the protrusions 31Q and 31R, and the island portion 31S.
  • the fixed charge film 52 of the island portion 31S is provided on the second region 21b side of the insulating film 53 in the arrangement direction (Y direction) of the first region 21a and the second region 21b of the photoelectric conversion region 21 .
  • the fixed charge films 52 of the island portion 31S are provided on both sides of the insulating film 53 in the longitudinal direction (X direction) of the inter-pixel isolation region 31 in plan view. That is, the fixed charge film 52 of the island portion 31S is adjacent to (faces with) the semiconductor layer 20 in the X direction and the Y direction of the insulating film 53 in plan view.
  • the second region 21b of the photoelectric conversion region 21 is formed.
  • the area of the fixed charge film 52 adjacent to (facing) the semiconductor layer 20 can be increased. Therefore, according to the solid-state imaging device 1S according to the eighteenth embodiment, the second The charge storage capacity in region 21b can be further increased.
  • the island portion 31S and both the protrusions 31Q and 31R are provided. May be combined. Alternatively, only the island portion 31S may be used. Also, the island portion 31S may be provided in the second region 21b of the photoelectric conversion region 21 in plan view.
  • FIG. 81 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device 1T according to the nineteenth embodiment of the present technology.
  • the semiconductor layer 20 corresponds to a specific example of the "first semiconductor layer” of the present technology
  • the semiconductor layer 92 corresponds to a specific example of the "second semiconductor layer” of the present technology.
  • a solid-state imaging device 1T according to the nineteenth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, and has the following configuration. different.
  • the solid-state imaging device 1A includes a multilayer wiring layer 40 on the first surface S1 side of the semiconductor layer 20.
  • Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 of FIG. 3 are provided in the photoelectric conversion region 21 of the semiconductor layer 20 .
  • the semiconductor layer 20 as the first semiconductor layer is provided on the first surface S1 side with the insulating layer 91 interposed therebetween.
  • a semiconductor layer 92 is provided as a second semiconductor layer.
  • Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 of FIG. 3 are provided in the semiconductor layer 92 .
  • FIG. 81 shows the amplification transistor AMP and the selection transistor SEL among the pixel transistors included in the readout circuit 15 .
  • an interlayer insulating film 94 is provided on the side of the semiconductor layer 92 opposite to the insulating layer 91 side.
  • the semiconductor layer 92 is covered with an interlayer insulating film 94 .
  • Each of the pixel transistors (AMP, SEL, RST) included in the readout circuit 15 is provided on the element forming surface of the semiconductor layer 92 opposite to the insulating layer 91 side. covered with
  • a wiring layer 96 is provided on the side of the interlayer insulating film 94 opposite to the semiconductor layer 92 side. Various wirings are formed in the wiring layer 96 . In FIG. 81, wirings 96b 1 , 96f and 96s are illustrated.
  • the wiring 96b1 is a contact electrode (penetrating plug) penetrating the interlayer insulating film 94, the semiconductor layer 92, the insulating layer 91, and the element isolation region 25 to reach the conductive material 35 of the intra-pixel isolation region 32.
  • 95b- 1 and further electrically connected to the conductive material 35 of the intra-pixel isolation region 32 via the contact electrode 95b -1 .
  • a second reference potential which is a positive potential higher than the first reference potential applied to the p-type well region 22, is applied to the wiring 96b1 as a power supply potential.
  • the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 96b1 through the contact electrode 95b1 , and is fixed at this second reference potential.
  • the second reference potential For example, 2.7 V is applied as the second reference potential.
  • the contact electrode 95b1 passes through a through hole in the semiconductor layer 92 and is electrically insulated and separated from the semiconductor layer 92 via an interlayer insulating film 94 in the through hole.
  • the wiring 96f is a contact electrode (through plug) penetrating the interlayer insulating film 94, the semiconductor layer 92, and the insulating layer 91 to reach the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21. 95f, and further electrically connected to the floating diffusion region FD via this contact electrode 95f.
  • the wiring 96f is electrically connected to the gate electrode 93a of the amplification transistor AMP through the contact electrode 95a embedded in the interlayer insulating film 94. As shown in FIG.
  • the floating diffusion region FD is electrically connected to the input stage side of the readout circuit 15 (the gate electrode 93a of the amplification transistor AMP and the source region of the reset transistor RST).
  • the contact electrode 95f passes through a through hole in the semiconductor layer 92 and is electrically insulated and separated from the semiconductor layer 92 via an interlayer insulating film 94 in the through hole.
  • the wiring 96s is electrically connected to the source region of the selection transistor SEL via a contact electrode 95s embedded in the interlayer insulating film 94.
  • the wiring 96s is electrically connected to the vertical signal line 11 (VSL) shown in FIG.
  • the solid-state imaging device 1T having a two-stage structure according to the nineteenth embodiment can also obtain the same effect as the solid-state imaging device 1A according to the above-described first embodiment.
  • the present technology is applied to a solid-state imaging device having a two-stage structure in which two semiconductor layers are stacked
  • the present technology is a multi-stage structure in which three or more semiconductor layers are stacked.
  • the present technology according to the second to eighteenth embodiments can also be applied to solid-state imaging devices in which two or more semiconductor layers are stacked.
  • FIG. 82 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to a twentieth embodiment of the present technology
  • FIG. 83A is a plan view schematically showing a planar pattern of the light reflector of FIG. 82.
  • FIG. 83B is a longitudinal sectional view schematically showing light reflection by a light reflector.
  • the hatching representing the cross section is partially omitted in order to make the drawings easier to see.
  • the gate electrode 37 of the transfer transistor TRG is illustrated in FIGS. 82 and 83B, the position of the gate electrode 37 is intentionally changed with respect to FIG. 83A in order to make the configuration easier to understand.
  • FIG. 82 illustration of the diffraction diffusion portion 51, the fixed charge film 52, the color filter 55, the microlens 56, and the like shown in FIGS. 5 and 6 is omitted.
  • FIG. 83B is upside down with respect to FIG.
  • the semiconductor layer 20 corresponds to a specific example of the "first semiconductor layer" of the present technology
  • the island-shaped semiconductor portions 204a and 204b are a specific example of the "second semiconductor layer" of the present technology. corresponds to
  • a solid-state imaging device 1U according to the twentieth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, and has the following configuration. different.
  • the solid-state imaging device 1A includes a multilayer wiring layer 40 on the first surface S1 side of the semiconductor layer 20.
  • Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 of FIG. 3 are provided in the photoelectric conversion region 21 of the semiconductor layer 20 .
  • the semiconductor layer 20 as the first semiconductor layer is provided on the first surface S1 side via the interlayer insulating film 41.
  • a multi-layer body (laminate) 200 is provided. Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 shown in FIG.
  • the multilayer body 200 includes a light reflector 213 provided so as to overlap the first region 21a of the photoelectric conversion region 21 in a plan view, and the light reflector 213 opposite to the semiconductor layer 20 side. and island-shaped semiconductor portions 204a and 204b as second semiconductor layers provided on the sides thereof.
  • the solid-state imaging device 1U has a two-stage structure in which the semiconductor layer 20, which is the first semiconductor layer, and the island-shaped semiconductor portions 204a and 204b, which are the second semiconductor layers, are laminated.
  • the multilayer body 200 includes a stopper film 202 provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side, and an insulating film 203 provided on the side of the stopper film 202 opposite to the interlayer insulating film 41 side. and further comprising: The island-shaped semiconductor portions 204a and 204b are provided on the opposite side of the insulating film 203 from the stopper film 202 side.
  • the multilayer body 200 also includes an insulating film 206 provided on the opposite side of the insulating film 203 from the stopper film 202 side so as to cover the island-shaped semiconductor portions 204a and 204b, and the insulating film 206 on the insulating film 203 side. and an insulating film 208 provided on the substrate.
  • the multilayer body 200 also includes a wiring layer 209 provided on the insulating film 208 and a cap film 210 provided on the side of the insulating film 208 opposite to the insulating film 206 so as to cover the wiring layer 209 . ing.
  • the multilayer body 200 is provided on the opposite side of the insulating film 208 side of the cap film 210 and extends from the insulating film 210 toward the semiconductor layer 20.
  • the inner walls (sidewalls and bottom) of the opening (drilled portion) 211 extend from the insulating film 210 toward the semiconductor layer 20 .
  • a protective film 212 provided along the wall
  • an insulating film 215 provided on the opposite side of the isolation insulating film 217 from the cap film 210 side and provided so as to fill the inside of the opening 211; is further provided.
  • the interlayer insulating film 41 shown in FIG. 82 is provided on the first surface S1 side of the semiconductor layer 20 so as to cover the gate electrode 37 of the transfer transistor TRG.
  • Each of the island-shaped semiconductor portions 204a and 204b shown in FIG. 82 is formed of the same layer. That is, the semiconductor portions 204a and 204b are formed by patterning one semiconductor layer. Semiconductors such as Si substrates, SiGe substrates, and InGaAs substrates can be used as the semiconductor layers (semiconductor portions 204a and 204b). In the twentieth embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used.
  • an amplification transistor AMP is provided as a pixel transistor included in the readout circuit 15 in the island-shaped semiconductor portion 204a.
  • a reset transistor RST for example, is provided as a pixel transistor included in the readout circuit 15 in the island-shaped semiconductor portion 204b.
  • a selection transistor as a pixel transistor included in the readout circuit 15 may be connected in series with the amplification transistor AMP and provided in the island-shaped semiconductor portion 204a, or may be provided in another island-shaped semiconductor portion. good too.
  • FIG. 82 shows wirings 209b 1 , 209f, 209r and 209t.
  • the wiring 209b1 is a contact electrode (through plug) 207b1 that penetrates the insulating films 206 and 203, the stopper film 202 and the interlayer insulating film 41 to reach the conductive material 35 of the intra-pixel isolation region 32. , and is further electrically connected to the conductive material 35 of the intra-pixel isolation region 32 via the contact electrode 207b1 .
  • a positive second reference potential higher than the first reference potential applied to the p-type well region 22 is applied to the wiring 209b1 as a power supply potential. That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 96b1 through the contact electrode 95b1 , and is fixed at this second reference potential. For example, 2.7 V is applied as the second reference potential.
  • the wiring 209f penetrates the insulating films 206 and 203, the stopper film 202 and the interlayer insulating film 41 to reach the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21. plug) 207f, and further electrically connected to the floating diffusion region FD via this contact electrode 207f.
  • the wiring 209f is electrically connected to the gate electrode 205a of the amplification transistor AMP via a contact electrode (embedded plug) 207a embedded in the insulating film 206.
  • the wiring 209r is electrically connected to the gate electrode 205r of the reset transistor RST through a contact electrode 207r embedded in the insulating film 206. As shown in FIG.
  • the wiring 209t is electrically connected to a contact electrode (through plug) 207t that penetrates the insulating films 206 and 203, the stopper film 202 and the interlayer insulating film 41 to reach the gate electrode 37 of the transfer transistor TRG. It is electrically connected to the gate electrode 37 of the transfer transistor TRG via the electrode 207t.
  • the light reflector 213 is provided in the opening 211 so as to overlap the first region 21a of the photoelectric conversion region 21 in plan view.
  • the light reflector 213 is positioned closer to the semiconductor layer 20 than the island-shaped semiconductor portions 204a and 204b in the thickness direction (Z direction) of the semiconductor layer 20, and is closer to the semiconductor layer 20 than the semiconductor layer 20. It is located on the side of portions 204a and 204b.
  • the light reflector 213 is provided in a layer between the semiconductor layer 20 and the island-shaped semiconductor portions 204a and 204b layerwise.
  • the light reflector 213 has a plate shape extending two-dimensionally.
  • the light reflector 213 preferably contains a metal material having a higher light reflectance than the insulating material contained in the inter-pixel isolation region 31 . Moreover, the light reflector 213 preferably contains a metal material having a higher light reflectance and a lower light absorption than those of the island-shaped semiconductor portions 204a and 204b, which are the second semiconductor layers. Examples of such metal materials include copper (Cu) and aluminum (Al). Cu and Al have higher light reflectance and lower light absorption than silicon oxide and silicon. In the twentieth embodiment, a light reflector 213 containing Cu, for example, is used.
  • the light reflector 213 reflects the light 57T incident from the second surface S2 (light incident surface) of the semiconductor layer 20 and transmitted through the first region 21a of the photoelectric conversion region 21 to the first region 21a. Reflect to That is, the light 57U that is incident from the second surface S2 of the semiconductor layer 20 and has transmitted (passed through) the first region 21a of the photoelectric conversion region 21 is reflected by the light reflector 213 and Return to 21a.
  • a photoelectric conversion part 24 (PD) is provided in the first region 21a of the photoelectric conversion region.
  • FIGS. 84A to 84J a method for manufacturing the solid-state imaging device 1U according to the twentieth embodiment of the present technology will be described with reference to FIGS. 84A to 84J.
  • the hatching representing the cross section is partially omitted in order to make the drawings easier to see.
  • 84 to 84J also show the gate electrode 37 of the transfer transistor TRG, the position of the gate electrode 37 is intentionally changed from that of FIG. 83A in order to make the configuration easier to understand.
  • the description will be focused on manufacturing the light reflector 213 included in the manufacturing method of the solid-state imaging device 1U.
  • the semiconductor layer 20 includes a photoelectric conversion region 21, an inter-pixel isolation region 31, an intra-pixel isolation region 32, a floating diffusion region FD, and a transfer transistor TRG (not shown).
  • an interlayer insulating film 41 and a stopper film 202 are formed in this order on the first surface S1 side of the semiconductor layer 20 .
  • a silicon oxide film for example, is used as the interlayer insulating film 41 .
  • the stopper film 202 for example, a silicon nitride (SiN) film or a silicon oxynitride (SiON) film, which is transparent and has selectivity with respect to a silicon oxide film when etching the silicon oxide film, is used.
  • SiN silicon nitride
  • SiON silicon oxynitride
  • a silicon oxide film, a silicon nitride film, and a silicon oxynitride film can be formed by, for example, a CVD method.
  • an insulating film 203, island-shaped semiconductor portions 204a and 204b, and an insulating film 206 are formed in this order on the opposite side of the stopper film 202 from the semiconductor layer 20 side.
  • the insulating film 203 is formed of, for example, a silicon oxide film.
  • the island-shaped semiconductor portions 204a and 204b are formed by first preparing a semiconductor substrate having an insulating film 203 provided on the side opposite to the element forming surface of the semiconductor layer made of, for example, a p-type single crystal silicon substrate, and then forming the semiconductor substrate.
  • the insulating film 203 side of the substrate is joined to the stopper film 202, then the thickness of the semiconductor layer of the semiconductor substrate is reduced by, for example, CMP, and then this semiconductor layer is subjected to well-known photolithography and anisotropic dry etching techniques. can be formed by patterning using
  • the insulating film 206 is formed on the side of the insulating film 203 opposite to the semiconductor layer 20 so as to cover the island-shaped semiconductor portions 204a and 204b. Before forming the insulating film 206, pixel transistors (AMP, SEL, RST) are formed in the island-shaped semiconductor portion.
  • FIG. 84B shows a state in which an amplifier transistor AMP having a gate electrode 205a is formed in an island-shaped semiconductor portion 204a, and a reset transistor RST having a gate electrode 205r is formed in an island-shaped semiconductor portion 204b.
  • a contact electrode 207b1 reaching the conductive material 35 of the intra-pixel isolation region 32 from the upper surface of the insulating film 206 and a contact electrode 207f reaching the floating diffusion region FD from the upper surface of the insulating film 206 are formed.
  • the contact electrode 207t reaching the gate electrode 37 of the transfer transistor from the upper surface of the insulating film 206
  • the reset from the upper surface of the insulating film 206.
  • the contact electrodes 207b 1 , 207f, 207t, 207a and 207r are formed by forming respective contact holes in insulating layers including the insulating films 206 and 203, the stopper film 202 and the interlayer insulating film 41, and then forming the inner walls of the respective contact holes.
  • a titanium (Ti) film for connection and a titanium nitride (TiN) film as a barrier film are sequentially formed on the surface of the contact hole.
  • a tungsten film, a titanium nitride film and a titanium film are formed on the upper surface of the insulating layer (on the upper surface of the insulating film 206) so that the tungsten film, the titanium nitride film and the titanium film in each contact hole remain selectively.
  • the film can be formed by selectively removing it, for example, by CMP.
  • an insulating film 208, a wiring layer 209 including wirings 209b 1 , 209f, 209t, 209a and 209r, and a cap film 210 are formed.
  • the insulating film 208 is formed on the side of the insulating film 206 opposite to the semiconductor layer 20 side.
  • a silicon oxide film is used as the insulating film 208.
  • a wiring layer 209 including wirings 209b 1 , 209f, 209t, 209a and 209r is formed on the insulating film 208 by, for example, a single damascene method.
  • Cu is used as the material of the wiring layer 209 .
  • the cap film 210 is formed on the side of the insulating film 208 opposite to the insulating film 206 side so as to cover the wiring layer 209 .
  • the cap film 210 can be formed by depositing a film of SiN, SiCN, SiC, or the like, for example, by the CVD method.
  • the conductive material 35 of the intra-pixel isolation region 32 is electrically connected to the wiring 209b1 through the contact electrode 207b1 .
  • the floating diffusion region FD provided in the second region 21b of the photoelectric conversion region 21 is electrically connected to the wiring 209f through the contact electrode 207f.
  • the gate electrode 37 of the transfer transistor TRG provided in the first region 21a of the photoelectric conversion region 21 is electrically connected to the wiring 209t through the contact electrode 207t.
  • the gate electrode 37 of the amplification transistor AMP provided in the island-shaped semiconductor portion 204a is electrically connected to the wiring 209a through the contact electrode 207a.
  • the gate electrode 205r of the reset transistor RST provided in the island-shaped semiconductor portion 204b is electrically connected to the wiring 209r through the contact electrode 207r.
  • an opening 211 extending from the upper surface of the cap film 210 toward the semiconductor layer 20 and overlapping the first region 21a of the photoelectric conversion region 21 in plan view is formed.
  • the opening 211 is formed with a depth reaching the stopper film 202 from the upper surface of the cap film 210 .
  • the opening 211 is for installing a light reflector 213 to be described later, and the planar size of the light reflector 213 is determined by the opening size of the opening 211 .
  • the opening 211 can be formed using well-known photolithography technology and anisotropic dry etching technology.
  • the depth of the opening 211 can be controlled by the stopper film 202 .
  • a protective film 212 for protecting the cap film 210 from chemicals during etching and a Cu film 213A as a conductive material are formed.
  • the protective film 212 is formed by depositing a transparent silicon oxide film by ALD or CVD.
  • the protective film 212 is formed to have a film thickness along the upper surface of the cap film 210 and the inner wall (side wall and bottom wall) of the opening 211 .
  • the Cu film 213A is formed by sputtering, for example, so that the film thickness on the bottom wall inside the opening 211 is about 50 nm.
  • the film thickness of the Cu film 213A is required to be 5 nm or more to produce light reflectance, and is preferably 50 nm or more to prevent light transmission.
  • the Cu film 213A inside the opening 211 is formed in an overhang shape.
  • titanium (Ti), tantalum (Ta), each nitride film, and a laminated film of the nitride film may be thinly provided as a barrier metal layer for adhesion between the Cu film and the insulating film and for preventing Cu diffusion.
  • a highly fluid resin film 214 is formed on the entire surface of the Cu film 213A so as to fill the opening 211 by spin coating.
  • the resin film 214 for example, a novolax resin-based material can be used. This resin film 214 is suitable for embedding the opening 211 having a large aspect ratio. The resin film 214 is for selectively removing the excess Cu film 213A in subsequent steps.
  • anisotropic dry etching such as IRE (Reactive Ion Etching) is used to remove the resin film 214 on the flat portion on the protective film 212.
  • the flat portion on the protective film 212 is etched with a chemical solution such as nitric acid.
  • the Cu film 213A is removed.
  • the Cu film 213A selectively remains on the bottom wall inside the opening 211 while being protected by the resin film 214.
  • the inside of the opening 211 is filled with an insulating film 215 .
  • the insulating film 215 for example, a silicon oxide film formed by a CVD method or a bias CVD method in which a high frequency is applied to the substrate can be used.
  • the multilayer body 200 including the light reflector 213 overlapping the first region 21a of the photoelectric conversion region 21 in plan view, and the island-shaped semiconductor portions 204a and 204b as the second semiconductor layer is formed from the semiconductor layer 20. It is formed on the first surface S1 side.
  • the wiring layer is further formed in the wafer process.
  • the solid-state imaging device 1U according to the twentieth embodiment includes inter-pixel isolation regions 31 and intra-pixel isolation regions 32, like the solid-state imaging device 1A according to the first embodiment. Therefore, in the solid-state imaging device 1U according to the twentieth embodiment, similarly to the solid-state imaging device 1A according to the first embodiment, improvement of the quantum efficiency QE as a pixel characteristic and high color mixing suppression (MTF) are attempted. In addition, transfer characteristics as pixel characteristics can be improved.
  • MTF color mixing suppression
  • the solid-state imaging device 1U includes the light shielding film 54 provided outside the second surface S2 of the semiconductor layer 20 and overlapping the second region 21b of the photoelectric conversion region 21 in plan view. I have. Therefore, as in the solid-state imaging device 1A of the first embodiment described above, the second region 21b of the photoelectric conversion region 21 enters the second region 21b from the second surface S2 side (light incident surface side) of the semiconductor layer 20.
  • the first light shielding portion 82a shields the light, which suppresses the arrival of the light to the floating diffusion region FD, thereby improving the parasitic light sensitivity characteristic (PLS).
  • the solid-state imaging device 1U according to the twentieth embodiment includes a multilayer body 200 provided on the first surface S1 side of the semiconductor layer 20. As shown in FIG.
  • the multilayer body 200 includes a light reflector 213 that overlaps the first region 21 a of the photoelectric conversion region 21 . Therefore, the light 57U that is incident from the second surface S2 of the semiconductor layer 20 and has transmitted (passed through) the first region 21a of the photoelectric conversion region 21 is reflected by the light reflector 213 and is reflected by the first region of the photoelectric conversion region. Return to 21a. Therefore, according to the solid-state imaging device 1U according to the twentieth embodiment, it is possible to improve the light utilization efficiency.
  • the manufacturing process using the Cu film 213A as the conductive material of the light reflector 213 has been described. can be applied.
  • FIG. 85 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twenty-first embodiment of the present technology
  • 86 is a plan view schematically showing a planar pattern of the light absorber of FIG. 85.
  • FIG. 85 the hatching representing the cross section is partially omitted to make the drawing easier to see.
  • the semiconductor layer 20 corresponds to a specific example of the "first semiconductor layer” of the present technology
  • the island-shaped semiconductor portions 204a and 204b are a specific example of the "second semiconductor layer” of the present technology. corresponds to
  • a solid-state imaging device 1V according to the twenty-first embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the above-described first embodiment, and has the following configuration. different. That is, as shown in FIG. 5, the solid-state imaging device 1A according to the first embodiment described above includes a multilayer wiring layer 40 on the first surface side of the semiconductor layer 20. As shown in FIG. Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 of FIG. 3 are provided in the photoelectric conversion region 21 of the semiconductor layer 20 . On the other hand, as shown in FIG.
  • the semiconductor layer 20 as the first semiconductor layer is provided on the first surface S1 side with the interlayer insulating film 41 interposed therebetween.
  • a multi-layer body (laminate) 220 is provided.
  • the multilayer body 220 includes a light absorber 228 provided so as to overlap the first region 21a of the photoelectric conversion region 21 in a plan view, and the light absorber 228 opposite to the semiconductor layer 20 side. and island-shaped semiconductor portions 204a and 204b as second semiconductor layers provided on the sides thereof. That is, the solid-state imaging device 1V according to the twenty-first embodiment has a two-stage structure in which the semiconductor layer 20 as the first semiconductor layer and the island-shaped semiconductor layers 204a and 204b as the second semiconductor layers are laminated. there is
  • the multilayer body 220 includes an insulating film 222 provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side, and an insulating film 223 provided on the side of the insulating film 222 opposite to the interlayer insulating film 41 . , and a wiring layer 229 provided on the opposite side of the insulating film 223 to the insulating film 222 side.
  • the interlayer insulating film 41 covers the gate electrode 37 (see FIG. 4) of the transfer transistor TRG provided in the photoelectric conversion region 21 as in the twentieth embodiment. It is provided on the first surface S1 side of the layer 20 .
  • the island-shaped semiconductor portions 204 a and 204 b are provided on the side opposite to the interlayer insulating film 41 side of the insulating film 222 and covered with the insulating film 223 .
  • Each of the island-shaped semiconductor portions 204a and 204b is formed of the same semiconductor layer as in the twentieth embodiment described above.
  • a Si substrate, a SiGe substrate, an InGaAs substrate, or the like can be used as the semiconductor layer.
  • An island-shaped semiconductor portion 204a is provided with, for example, an amplification transistor AMP as a pixel transistor included in the readout circuit 15, as in the above-described twentieth embodiment.
  • a reset transistor RST for example, is provided as a pixel transistor included in the readout circuit 15 in the island-shaped semiconductor portion 204b.
  • a selection transistor as a pixel transistor included in the readout circuit 15 may be connected in series with the amplification transistor AMP and provided in the island-shaped semiconductor portion 204a, or may be provided in another island-shaped semiconductor portion. good too.
  • FIG. 85 wirings 229b 1 , 229f and 229r are illustrated.
  • a wiring 229b1 is connected to a contact electrode (through plug) 227b1 that penetrates the insulating film 223, the insulating film 222, and the interlayer insulating film 41 to reach the conductive material 35 of the intra-pixel isolation region 32, and an electrical conductor. , and is electrically connected to the conductive material 35 of the intra-pixel isolation region 32 through the contact electrode 227b1 .
  • a positive second reference potential higher than the first reference potential applied to the p-type well region 22 is applied to the wiring 229b1 as the power supply potential in the same manner as in the twentieth embodiment. be. That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the wiring 96b1 through the contact electrode 95b1 , and is fixed at this second reference potential.
  • the wiring 229f is a contact electrode (through plug) penetrating the insulating film 223, the insulating film 222 and the interlayer insulating film 41 to reach the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21. 227f, and further electrically connected to the floating diffusion region FD via this contact electrode 227f.
  • the wiring 229f is electrically connected to the gate electrode 205a of the amplification transistor AMP via a contact electrode (embedded plug) 227a embedded in the insulating film 223 . That is, the floating diffusion region FD is electrically connected to the input stage side of the readout circuit 15 (the gate electrode 205a of the amplification transistor AMP and the source region of the reset transistor RST).
  • the wiring 229r is electrically connected to the gate electrode 205r of the reset transistor RST via a contact electrode 227r embedded in the insulating film 203.
  • the light absorber 228 overlaps the first region 21a of the photoelectric conversion region 21 in a plan view, is provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side, and It is covered with a membrane 222 .
  • the light absorber 228 is positioned closer to the semiconductor layer 20 than the island-shaped semiconductor portions 204a and 204b in the thickness direction (Z direction) of the semiconductor layer 20, and is closer to the semiconductor layer 20 than the semiconductor layer 20. It is located on the side of portions 204a and 204b.
  • the light absorber 228 is provided between the semiconductor layer 20, which is the first semiconductor layer, and the island-shaped semiconductor portions 204a and 204b, which are the second semiconductor layer.
  • the light absorber 228 is provided in a layer between the semiconductor layer 20 and the island-like semiconductor portions 204a and 204b layerwise. As shown in FIG. 86, the light reflector 213 has a plate shape extending two-dimensionally. In the twenty-first embodiment, the light absorber 228 also overlaps the inter-pixel isolation region and the intra-pixel isolation region in plan view.
  • the light absorber 228 preferably contains a metal material having a higher light absorption rate than the semiconductor layer 20 and the island-shaped semiconductor portions 204a and 204b as the second semiconductor layer. Specifically, the light absorber 228 preferably contains a metal material having a higher light absorption rate than semiconductor materials such as Si, SiGe, and InGaAs. Tungsten (W), for example, is effective as such a metal material. In this twenty-first embodiment, a light absorber 228 containing, for example, tungsten is used.
  • the light absorber 228 enters from the second surface S2 (light incident surface) of the semiconductor layer 20, passes through the first region 21a of the photoelectric conversion region 21, and becomes its own light absorber 228. absorbs the light 57V that hits the That is, the light 57V incident from the second surface S2 (light incident surface) of the semiconductor layer 20, transmitted through the first region 21a of the photoelectric conversion region 21, and impinging on the light absorber 228 is absorbed by the light absorber 228. be done.
  • FIGS. 87A to 87J a method for manufacturing the solid-state imaging device 1V according to the twenty-first embodiment of the present technology will be described with reference to FIGS. 87A to 87J.
  • FIGS. 87A to 87I the hatching representing the cross section is partially omitted in order to make the drawings easier to see.
  • the explanation will be focused on the production of the light absorber 228 included in the production method of the solid-state imaging device 1V.
  • a photoelectric conversion region 21, an inter-pixel isolation region 31, an intra-pixel isolation region 32, a floating diffusion region FD, a transfer transistor TRG (not shown), and the like are formed in a semiconductor layer 20. do.
  • an interlayer insulating film 41 and a sacrificial film 221 are formed in this order on the first surface S1 side of the semiconductor layer 20 .
  • a silicon oxide film for example, is used as the interlayer insulating film 41 .
  • the sacrificial film 221 for example, a silicon nitride film having selectivity with respect to a silicon oxide film is used.
  • the interlayer insulating film 41 is formed so as to cover the gate electrode 37 of the transfer transistor TRG formed in the photoelectric conversion region 21, as explained with reference to FIG.
  • the sacrificial film 221 is for forming a cavity by selectively removing the sacrificial film 221 .
  • the sacrificial film 221 is patterned to form a first pattern portion 221a that overlaps the first region 21a of the photoelectric conversion region 21 in plan view and a first pattern portion 221a that overlaps the first region 21a of the photoelectric conversion region 21 in plan view.
  • a second pattern portion 221f that overlaps with the second region 21b is formed.
  • the patterning of this sacrificial film 221 is performed using well-known photolithography technology and anisotropic dry etching technology.
  • the space between the first pattern portion 221a and the second pattern portion 221f is buried, and the first pattern portion 221a and the second pattern portion 221f are buried.
  • An insulating film 222 is formed to cover the second pattern portion 221f.
  • a silicon oxide film formed by a CVD method, a bias CVD method in which a high frequency is applied to the substrate, or the like can be used.
  • island-shaped semiconductor portions 204a and 204b are formed as second semiconductor layers on the side of the insulating film 222 opposite to the semiconductor layer 20 side, and then the island-shaped semiconductor portion 204a is formed.
  • An amplification transistor AMP is formed in the region 204b, and a reset transistor RST is formed in the island-shaped semiconductor portion 204b.
  • the island-shaped semiconductor portions 204a and 204b are formed by the same method as in the twentieth embodiment.
  • the amplification transistor AMP and the reset transistor RST will be described. It is formed in one or another island-like semiconductor portion.
  • an insulating film 223 is formed on the side of the insulating film 222 opposite to the semiconductor layer 20 so as to cover the island-shaped semiconductor portions 204a and 204b.
  • the insulating film 223 for example, a silicon oxide film formed by a CVD method is used.
  • a contact hole 224b1 that reaches the first pattern portion 221a from the upper surface of the insulating film 223 and overlaps the intra-pixel isolation region 32 in a plan view, and a first contact hole 224b1 that extends from the upper surface of the insulating film 223.
  • These contact holes 224b 1 , 224f, 224a and 224r can be formed using well-known photolithography technology and anisotropic dry etching technology.
  • the first pattern portion 221a and the interlayer insulating film 41 are sequentially etched through the contact hole 224b1 so that the contact hole 224b1 reaches the conductive material 35 of the intra-pixel isolation region 32, and the contact is formed.
  • the second pattern portion 221f and the interlayer insulating film 41 are sequentially etched through the hole 224f so that the contact hole 224f reaches the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21.
  • the first pattern portion 221a is selectively removed to form the first cavity portion 225a
  • the second pattern portion 221f is selectively removed to form the second cavity portion 225f.
  • Each of the first and second pattern portions 221a and 221f is selectively removed by supplying a chemical solution of phosphoric acid to each of the first and second pattern portions 221a and 221f through the contact holes 224b1 and 224f. can be done.
  • the inner walls of the contact holes 224b 1 , 224f, 224a and 224r and the inner walls of the first and second cavities 225a and 225f are formed.
  • a titanium (Ti) film for connection and a titanium nitride (TiN) film as a barrier film are sequentially formed.
  • the Ti film and TiN film can be formed by a sputtering method or a CVD method.
  • a tungsten (W) film 226 as a conductive material is buried in each of the first and second cavities 225a and 225f and the contact holes 224b 1 , 224f, 224a and 224r. to form The W film 226 can be formed by sputtering or CVD.
  • the W film 226, TiN film and Ti film on the upper surface of the insulating film 223 are selectively removed by, eg, CMP.
  • CMP chemical vapor deposition
  • the Ti film, the TiN film, and the W film 226 are included in the first hollow portion 225a, and are electrically connected to the conductive material 35 of the intra-pixel isolation region 32, and the second layer of the photoelectric conversion region 21 in plan view.
  • a light absorber 228 can be formed that overlaps with the first region 21a and is positioned between the first region 21a of the photoelectric conversion region 21 and the island-shaped semiconductor portions 204a and 204b.
  • a contact electrode 227b including the Ti film, the TiN film and the W film 226 and electrically connected to the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21 1 can be formed.
  • a contact electrode 227a including the Ti film, the TiN film and the W film 226 and electrically connected to the gate electrode 205a of the amplification transistor AMP can be formed.
  • a contact electrode 227r including the Ti film, the TiN film and the W film 226 and electrically connected to the gate electrode 205r of the reset transistor RST can be formed.
  • a wiring layer 229 including a wiring 229b 1 , a wiring 229f, a wiring 229a and a wiring 229r is formed on the side of the insulating film 223 opposite to the semiconductor layer 20 side.
  • the wiring layer is further formed in the wafer process.
  • the solid-state imaging device 1V according to the twenty-first embodiment includes an inter-pixel isolation region 31, an intra-pixel isolation region 32, and a light shielding film 54, similarly to the solid-state imaging device 1A according to the first embodiment. there is Therefore, in the solid-state imaging device 1V according to the twenty-first embodiment as well, the same effects as those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.
  • the solid-state imaging device 1V includes a multilayer body 220 provided on the first surface S1 side of the semiconductor layer 20 .
  • the multilayer body 220 includes a light absorber 228 that overlaps the first region 21 a of the photoelectric conversion region 21 and has a higher light absorption rate than the semiconductor layer 20 . Therefore, the light 57V incident from the second surface S2 (light incident surface) of the semiconductor layer 20 and transmitted through the first region 21a of the photoelectric conversion region 21 can be absorbed by the light absorber 228, resulting in an island-like shape. It is possible to suppress the incidence of light on the second semiconductor layer including the semiconductor portions 204a and 204b. Thereby, scattering and stray light can be suppressed.
  • the light absorber 228 can be formed between the first region 21a of the photoelectric conversion region 21 and the island-shaped semiconductor portions 204a and 204b.
  • the installation area of the semiconductor portions 204a and 204b can be widened.
  • FIG. 88 is a vertical cross-sectional view schematically showing a vertical cross-sectional structure of a solid-state imaging device according to a twenty-second embodiment of the present technology
  • 89 is a plan view schematically showing a plane pattern of the light reflector of FIG. 88.
  • FIG. 88 the hatching representing the cross section is partially omitted in order to make the drawing easier to see.
  • FIG. 88 the hatching representing the cross section is partially omitted in order to make the drawing easier to see.
  • the semiconductor layer 20 corresponds to a specific example of the "first semiconductor layer” of the present technology
  • the island-shaped semiconductor portions 204a and 204b are a specific example of the "second semiconductor layer” of the present technology. corresponds to
  • a solid-state imaging device 1W according to the twenty-second embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, and has the following configuration. different. That is, as shown in FIG. 5, the solid-state imaging device 1A according to the first embodiment described above includes a multilayer wiring layer 40 on the first surface side of the semiconductor layer 20. As shown in FIG. Pixel transistors (AMP, SEL, RST) included in the readout circuit 15 of FIG. 3 are provided in the photoelectric conversion region 21 of the semiconductor layer 20 . On the other hand, as shown in FIG.
  • the semiconductor layer 20 as the first semiconductor layer is provided on the first surface S1 side with the interlayer insulating film 41 interposed therebetween.
  • a multi-layer body (laminate) 230 is provided.
  • the multilayer body 220 includes a light reflector 239 provided so as to overlap the first region 21a of the photoelectric conversion region 21 in plan view, and the light reflector 239 opposite to the semiconductor layer 20 side. and island-shaped semiconductor portions 204a and 204b as second semiconductor layers provided on the sides thereof. That is, the solid-state imaging device 1W according to the twenty-second embodiment has a two-stage structure in which the semiconductor layer 20, which is the first semiconductor layer, and the island-shaped semiconductor layers 204a and 204b, which are the second semiconductor layers, are laminated. there is
  • the multilayer body 230 includes an insulating film 232 provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side, and an insulating film 234 provided on the side of the insulating film 232 opposite to the interlayer insulating film 41 . , and an insulating film 236 provided on the opposite side of the insulating film 234 from the insulating film 232 side.
  • the interlayer insulating film 41 covers the gate electrode 37 (see FIG. 4) of the transfer transistor TRG provided in the photoelectric conversion region 21 as in the twentieth embodiment. It is provided on the first surface S1 side of the layer 20 .
  • the island-shaped semiconductor portions 204 a and 204 b are provided on the side of the insulating film 232 opposite to the interlayer insulating film 41 side and covered with the insulating film 234 .
  • Each of the island-shaped semiconductor portions 204a and 204b is formed of the same layer as in the twentieth embodiment.
  • a Si substrate, a SiGe substrate, an InGaAs substrate, or the like can be used as the semiconductor layer 20 .
  • a p-type semiconductor substrate made of, for example, single-crystal silicon is used as in the above-described twentieth embodiment.
  • An island-shaped semiconductor portion 204a is provided with, for example, an amplification transistor AMP as a pixel transistor included in the readout circuit 15, as in the above-described twentieth embodiment.
  • a reset transistor RST for example, is provided as a pixel transistor included in the readout circuit 15 in the island-shaped semiconductor portion 204b.
  • a selection transistor as a pixel transistor included in the readout circuit 15 may be connected in series with the amplification transistor AMP and provided in the island-shaped semiconductor portion 204a, or may be provided in another island-shaped semiconductor portion. good too.
  • a contact electrode 235b1 reaching the conductive material 35 from the upper surface of the insulating film 234 is electrically connected to the conductive material 35 of the intra-pixel isolation region 32 of the photoelectric conversion region 21.
  • a positive second reference potential higher than the first reference potential applied to the p-type well region 22 is applied to the contact electrode 235b1 as the power supply potential in the same manner as in the above-described first embodiment. . That is, the conductive material 35 of the intra-pixel isolation region 32 is supplied with the second reference potential applied to the contact electrode 235b1 and fixed at this second reference potential.
  • a contact electrode 235f reaching the floating diffusion region FD from the upper surface of the insulating film 234 is electrically connected to the floating diffusion region FD of the second region 21b of the photoelectric conversion region 21 .
  • this contact electrode 235f is electrically connected to the gate electrode 205a of the amplification transistor AMP. That is, the floating diffusion region FD is electrically connected to the input stage side of the readout circuit 15 (the gate electrode 205a of the amplification transistor AMP and the source region of the reset transistor RST).
  • a contact electrode 235a reaching the gate electrode 205a from the upper surface of the insulating film 234 is electrically connected to the gate electrode 205a of the amplification transistor AMP.
  • a contact electrode 235r reaching the floating diffusion region FD from the upper surface of the insulator 234 is electrically connected to the gate electrode of the reset transistor RST.
  • the light reflector 239 overlaps the first region 21a of the photoelectric conversion region 21 in plan view, is provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side, and is provided on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side. It is covered with a membrane 232 .
  • the light reflector 239 is positioned closer to the semiconductor layer 20 than the island-shaped semiconductor portions 204a and 204b in the thickness direction (Z direction) of the semiconductor layer 20, and is closer to the semiconductor layer 20 than the semiconductor layer 20. It is located on the side of portions 204a and 204b.
  • the light reflector 239 is provided between the semiconductor layer 20, which is the first semiconductor layer, and the island-shaped semiconductor portions 204a and 204b, which are the second semiconductor layer. In other words, the light reflector 239 is provided in a layer between the semiconductor layer 20 and the island-shaped semiconductor portions 204a and 204b layerwise. As shown in FIG. 89, the light reflector 239 has a plate shape extending two-dimensionally. As shown in FIG. 88, the light reflector 239 is formed integrally with a runner metal body 239a extending from the upper surface of the insulating film 236 toward the semiconductor layer 20. As shown in FIG.
  • the light reflector 239 preferably contains a metal material having a higher light reflectance than the insulating material contained in the inter-pixel isolation region 31 .
  • the light reflector 213 preferably contains a metal material having a higher light reflectance and a lower light absorption than those of the island-shaped semiconductor portions 204a and 204b, which are the second semiconductor layers.
  • metal materials include copper (Cu) and aluminum (Al).
  • Cu and Al have higher light reflectance and lower light absorption than silicon oxide and silicon.
  • a light reflector 239 containing Al for example, is used.
  • the light reflector 239 reflects the light 57W incident from the second surface S2 (light incident surface) of the semiconductor layer 20 and transmitted through the first region 21a of the photoelectric conversion region 21 to the first region 21a. Reflect to That is, the light 57W incident from the second surface S2 of the semiconductor layer 20 and transmitted (passed) through the first region 21a of the photoelectric conversion region 21 is reflected by the light reflector 239 and is reflected by the first region of the photoelectric conversion region 21. Return to 21a.
  • a photoelectric conversion part 24 (PD) is provided in the first region 21a of the photoelectric conversion region.
  • FIGS. 90A to 90H a method for manufacturing the solid-state imaging device 1W according to the twenty-second embodiment of the present technology will be described with reference to FIGS. 90A to 90H.
  • the hatching representing the cross section is partially omitted in order to make the drawings easier to see.
  • the description will be focused on the manufacture of the light reflector 239 included in the manufacturing method of the solid-state imaging device 1W.
  • a photoelectric conversion region 21, an inter-pixel isolation region 31, an intra-pixel isolation region 32, a floating diffusion region FD, a transfer transistor TRG (not shown), and the like are formed in a semiconductor layer 20. do.
  • an interlayer insulating film 41 and a sacrificial film 231 are formed in this order on the first surface S1 side of the semiconductor layer 20 .
  • a silicon oxide film for example, is used as the interlayer insulating film 41 .
  • the sacrificial film 231 for example, a silicon nitride film having selectivity with respect to a silicon oxide film is used.
  • the interlayer insulating film 41 is formed to cover the gate electrode 37 of the transfer transistor TRG formed in the photoelectric conversion region 21, as explained with reference to FIG.
  • the sacrificial film 231 is for forming a cavity by selectively removing the sacrificial film 221 .
  • the sacrificial film 231 is patterned to form an opening 231a overlapping the second region 21a of the photoelectric conversion region 21 in plan view.
  • the patterning of this sacrificial film 221 is performed using well-known photolithography technology and anisotropic dry etching technology.
  • an insulating film 232 that fills the opening 231a and covers the sacrificial film 231 is formed on the side of the interlayer insulating film 41 opposite to the semiconductor layer 20 side.
  • a silicon oxide film formed by a CVD method, a bias CVD method in which a high frequency is applied to the substrate, or the like can be used.
  • island-shaped semiconductor portions 204a and 204b are formed as second semiconductor layers on the side of the insulating film 232 opposite to the semiconductor layer 20 side, and then the island-shaped semiconductor portion 204a is formed.
  • An amplification transistor AMP is formed in the region 204b, and a reset transistor RST is formed in the island-shaped semiconductor portion 204b.
  • the island-shaped semiconductor portions 204a and 204b are formed by the same method as in the twentieth embodiment.
  • the amplification transistor AMP and the reset transistor RST will be described. It is formed in one or another island-like semiconductor portion.
  • an insulating film 234 is formed on the side of the insulating film 222 opposite to the semiconductor layer 20 so as to cover the island-shaped semiconductor portions 204a and 204b.
  • the insulating film 234 for example, a silicon oxide film formed by a CVD method is used.
  • a contact electrode 235b1 reaching the conductive material 35 of the intra-pixel isolation region 32 from the upper surface of the insulating film 234 and a contact electrode 235f reaching the floating diffusion region FD from the upper surface of the insulating film 234 are formed.
  • a contact electrode 235a reaching the gate electrode 205a of the amplifier transistor AMP from the upper surface of the insulating film 206 and a contact electrode 235r reaching the gate electrode 205r of the reset transistor RST from the upper surface of the insulating film 206 are formed.
  • the contact electrodes 235b 1 , 235f, 235a and 2335s are formed by the same method as in the twentieth embodiment described above.
  • an insulating film 236 covering each of the contact electrodes 235b 1 , 235f, 235a and 235r is formed on the side of the insulating film 234 opposite to the semiconductor layer 20 side. Form.
  • an opening 237 reaching the sacrificial film 231 from the upper surface of the insulating film 236 is formed.
  • the opening 237 can be formed using well-known photolithography technology and anisotropic dry etching technology.
  • the sacrificial film 231 is selectively removed to form a cavity 238 that connects with the opening 237 .
  • the sacrificial film 231 can be selectively removed by supplying a phosphoric acid-based chemical to the sacrificial film 231 through the opening 237 .
  • an aluminum (Al) film is formed as a conductive material so as to fill each of the cavity 238 and the opening 237.
  • the aluminum film on the insulating film 236 is etched. It is selectively removed by a back method or a CMP method.
  • the aluminum film can be formed by a sputtering method or a CVD method. In the case of the CVD method, a Ti film or a TiN film may be formed first for stable growth.
  • the island-shaped semiconductor portions 204a and 204b which include the Al film and overlap the first region 21a of the photoelectric conversion region 21 in a plan view, form the first region 21a of the photoelectric conversion region 21 and the island-shaped semiconductor portions 204b.
  • a light reflector 239 can be formed between the .
  • a runner metal body 239a including an Al film and connected to the light reflector 239 is also formed.
  • the wiring layer is further formed in the wafer process.
  • the solid-state imaging device 1W according to the twenty-second embodiment includes an inter-pixel isolation region 31, an intra-pixel isolation region 32, and a light shielding film 54, similarly to the solid-state imaging device 1A according to the first embodiment. there is Therefore, in the solid-state imaging device 1W according to the twenty-first embodiment as well, the same effects as those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.
  • the solid-state imaging device 1W according to the twenty-second embodiment includes a multilayer body 230 provided on the first surface S1 side of the semiconductor layer 20. As shown in FIG.
  • the multilayer body 230 includes a light reflector 239 provided so as to overlap the first region 21 a of the photoelectric conversion region 21 . Therefore, the light 57W that is incident from the second surface S2 of the semiconductor layer 20 and is transmitted (passed) through the first region 21a of the photoelectric conversion region 21 is reflected by the light reflector 213 and is reflected by the first region of the photoelectric conversion region. Return to 21a. Therefore, according to the solid-state imaging device 1W according to the twenty-second embodiment, it is possible to improve the light utilization efficiency.
  • the light reflector 239 can be formed between the first region 21b of the photoelectric conversion region 21 and the island-shaped semiconductor portions 204a and 204b.
  • the installation area of the shaped semiconductor portions 204a and 204b can be increased.
  • the Al film has lower light absorption and higher reflectance than the W film, it is possible to improve the light utilization efficiency.
  • FIG. 91 is a diagram showing a schematic configuration of an electronic device (for example, camera) according to the eighth embodiment of the present technology.
  • the electronic device 300 includes a solid-state imaging device 301, an optical lens 302, a shutter device 303, a driving circuit 304, and a signal processing circuit 305.
  • This electronic device 300 shows an embodiment in which the solid-state imaging device according to the first to fourth embodiments of the present technology is used as an electronic device (for example, a camera) as a solid-state imaging device 301 .
  • the optical lens 302 forms an image of image light (incident light 306 ) from the subject on the imaging surface of the solid-state imaging device 301 .
  • image light incident light 306
  • a shutter device 303 controls a light irradiation period and a light shielding period for the solid-state imaging device 301 .
  • a drive circuit 304 supplies drive signals for controlling the transfer operation of the solid-state imaging device 301 and the shutter operation of the shutter device 303 .
  • Signal transfer of the solid-state imaging device 301 is performed by a driving signal (timing signal) supplied from the driving circuit 304 .
  • a signal processing circuit 305 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 301 .
  • the video signal that has undergone signal processing is stored in a storage medium such as a memory, or output to a monitor.
  • the pixel characteristics are improved in the solid-state imaging device 301, so that the image quality can be improved.
  • the electronic device 300 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to cameras, and can be applied to other electronic devices.
  • the present invention may be applied to imaging devices such as camera modules for mobile devices such as mobile phones and tablet terminals.
  • the present technology can also be applied to light detection devices in general, including range sensors that measure distance, which is called a ToF (Time of Flight) sensor.
  • range sensors that measure distance
  • a distance measuring sensor emits irradiation light toward an object, detects the reflected light that is reflected by the surface of the object, and detects the time from when the irradiation light is emitted to when the reflected light is received.
  • the structure of the element isolation region of this distance measuring sensor the structure of the element isolation region described above can be adopted.
  • the present technology may be configured as follows. (1) a semiconductor layer; first and second isolation regions provided in the semiconductor layer; with the first isolation region includes an insulating material filled in a first recess extending in the thickness direction of the semiconductor layer and having a lower refractive index than the semiconductor layer; The photodetector, wherein the second isolation region includes a conductive material filled in a second dug portion extending in a thickness direction of the semiconductor layer. (2) The photodetector according to (1) above, wherein the conductive material is electrically connected to a wiring to which a potential is applied.
  • the photoelectric conversion region is the second isolation region spaced apart from the first isolation region; a charge holding portion and a photoelectric conversion portion separated by the second separation region; a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit;
  • Each of the first and second photoelectric conversion regions includes a charge holding portion, a photoelectric conversion portion, a transfer transistor for transferring signal charges photoelectrically converted in the photoelectric conversion portion to the charge holding portion,
  • the photodetector according to (5) above comprising: (7) The photoelectric conversion part in the first photoelectric conversion region photoelectrically converts light with a wavelength in the infrared region, The photodetector according to (6), wherein the photoelectric conversion portion in the second photoelectric conversion region photoelectrically converts light with a wavelength in the visible region.
  • first and second photoelectric conversion regions partitioned adjacent to each other by the first isolation region;
  • the photodetector according to (1) or (2) above wherein the second separation region is provided in at least one of the first and second photoelectric conversion regions and is spaced apart from the first separation region. .
  • one of the photoelectric conversion regions including the second separation region photoelectrically converts light with a wavelength in the infrared region, and the other photoelectric conversion region does not include the second separation region.
  • the region photoelectrically converts light with a wavelength in the visible region.
  • each of the first and second isolation regions has one end connected to the element isolation region and the other end reaching the light incident surface of the semiconductor layer.
  • (11) a first photoelectric conversion region partitioned by the first separation region; a second photoelectric conversion region partitioned by the second isolation region; a third isolation region containing a conductive material filled in a third dug portion extending in the thickness direction of the semiconductor layer; The third isolation region is provided in the first photoelectric conversion region spaced apart from the first isolation region, and is provided in the second photoelectric conversion region spaced apart from the second isolation region.
  • Each of the first and second photoelectric conversion regions is a charge holding portion and a photoelectric conversion portion separated by the third isolation region; a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit;
  • each of the first, second and third isolation regions has one end connected to the element isolation region and the other end reaching the light incident surface of the semiconductor layer.
  • a photoelectric conversion region including a first region and a second region partitioned by the first separation region and separated by the second separation region; a photoelectric conversion unit provided in the first region; a charge holding portion provided on the second region side of the semiconductor layer in the second region; a light shield provided on the first surface side of the semiconductor layer so as to overlap with the charge holding portion;
  • the photodetector according to (1) above further comprising: (17) using the semiconductor layer as a first semiconductor layer; a second semiconductor layer provided on the first surface side of the first semiconductor layer; a readout circuit electrically connected to the charge holding unit,
  • a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second separation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region; a charge holding portion provided on the first surface side of the semiconductor layer in the second region; a light shield provided on the second surface side of the semiconductor layer and overlapping the second region in plan view;
  • a photodetector comprising: (19) The photodetector according to (18) above, wherein the light shield is provided over the inside and outside of the second region.
  • the light shielding body is a first light shielding portion provided outside the second surface of the semiconductor layer and overlapping the second region in a plan view; a second light shielding portion protruding from the first light shielding portion to the inside of the second region;
  • the first light shielding portion is provided on the side opposite to the semiconductor layer side of the insulating film, The second light shielding portion penetrates the insulating film,
  • the photodetector according to any one of (20) to (22) above.
  • the light shielding body is a first light shielding portion provided outside the second surface of the semiconductor layer and overlapping the second region in a plan view; a second light shielding portion that overlaps with the second isolation region in plan view and protrudes into the semiconductor layer from the first light shielding portion;
  • the photodetector according to (24) above comprising: (26) The photodetector according to (25) above, wherein the second light shielding portion is provided in a third dug portion extending from the second surface side of the semiconductor layer toward the second dug portion. .
  • the photodetector according to (25) or (26) above, wherein the second light shielding portion and the second isolation region have different widths in the one direction.
  • the photodetector according to (18) above wherein the light shield is provided to cover the inside and outside of the insulating film in the thickness direction of the insulating film.
  • the light shielding body is a first light shielding portion provided on the side opposite to the semiconductor layer side of the insulating film and overlapping the second region in plan view; a second light shielding portion that overlaps with the first isolation region in a plan view and protrudes into the insulating film from the first light shielding portion; a third light shielding portion overlapping the second isolation region in plan view and projecting from the first light shielding portion into the insulating film;
  • the photodetector according to (28) above comprising: (30) 3.
  • the light shielding body overlaps with each of the first and second separation regions in a plan view, and is located closer to the second region than the first region of the photoelectric conversion region in the one direction.
  • the photodetector according to (28) or (29) above. (31) The light shielding body according to any one of (18) to (30) above, wherein the light shield extends over the two photoelectric conversion regions that are adjacent to each other in the other direction orthogonal to the one direction in a two-dimensional plane.
  • Photodetector. (32)
  • the photoelectric conversion unit photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges,
  • the charge holding unit holds signal charges photoelectrically converted by the photoelectric conversion unit.
  • a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second separation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region; a charge holding portion provided on the first surface side of the semiconductor layer in the second region; a light shield provided on the second surface side of the semiconductor layer and overlapping the second region in plan view; a light reflector provided on the second surface side of the semiconductor layer so as to overlap with the second isolation region in plan view and having a lower refractive index than the semiconductor layer;
  • a photodetector comprising: (34) The light reflector is provided in a
  • the light reflector is provided closer to the first region than the second separation region in the one direction, and the conductive material of the second separation region is provided between the light reflector and the second region. provided, the photodetector according to (33) or (34) above.
  • the photoelectric conversion unit photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges,
  • the charge holding unit holds signal charges photoelectrically converted by the photoelectric conversion unit.
  • the photodetector according to any one of (33) to (37) above. (39) a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; first and second photoelectric conversion regions arranged in one direction and partitioned by the first separation region; including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer, wherein each of the first and second photoelectric conversion regions is divided into the first region and the second region in the one direction; a second separation region that separates; a photoelectric conversion part provided in each of the first and second photoelectric conversion regions; a charge holding portion provided in the second region of each of the first and second photoelectric conversion regions; with The photodetector, wherein the second regions of the first and second photoelectric conversion regions are arranged adjacent to each other in the one direction with the third separation region interposed there
  • the photoelectric conversion unit photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges, The charge holding unit holds signal charges photoelectrically converted by the photoelectric conversion unit.
  • a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a first region including a conductive material provided through an insulator having a lower refractive index than that of the semiconductor layer in a second recess extending in a thickness direction of the semiconductor layer, and extending the photoelectric conversion region in one direction; and a second separation region that separates into a second region; a photoelectric conversion unit provided in the first region; a charge holding portion provided in the second region; with In the second isolation region, the photodetector is such that the thickness of the insulator on the first region side of the conductive material is thicker than the thickness of the insulator on the second region side of the conductive material.
  • the photodetector according to (46) above wherein the conductive material is biased closer to the second region than to the first region in plan view.
  • the photodetector according to (46) or (47) above wherein the width of the second isolation region in the one direction is wider than the width of the first isolation region in the one direction.
  • the photoelectric conversion unit photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges, the charge holding unit holds a signal charge photoelectrically converted by the photoelectric conversion unit; further comprising a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion unit to the charge holding unit;
  • a semiconductor layer having first and second surfaces opposite to each other; a photoelectric conversion region provided in the semiconductor layer so as to be partitioned by a first isolation region; a second separation region for separating each photoelectric conversion region of the photoelectric conversion region into a first region and a second region arranged in one direction; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding unit provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion unit; with the first isolation region is provided in a first recess extending in the thickness direction of the semiconductor layer and includes an insulating material having a lower refractive index than the semiconductor layer;
  • the second isolation region includes a conductive material provided in a second recess extending in the thickness direction of the semiconductor layer via an isolation insulating film having a lower refractive index than the semiconductor layer, Of the incident light incident on the first region from the second surface side of the semiconductor layer, the reflected light reflected by the side surface portion of the
  • a photodetector with a set width (1) The photodetector according to (50) above, further comprising a light shielding film provided on the second surface side of the semiconductor layer so as to overlap with the charge holding portion in plan view. (52) The photodetector according to (50) or (51), wherein the charge holding portion is provided on the second surface side of the semiconductor layer. (53) The photodetector according to any one of (50) to (52) above, further comprising a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit.
  • a semiconductor layer having first and second surfaces opposite to each other; a plurality of photoelectric conversion regions provided in the semiconductor layer so as to be partitioned by first isolation regions; a second separation region for separating each photoelectric conversion region of the plurality of photoelectric conversion regions into a first region and a second region arranged in one direction; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding unit provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion unit; with the first isolation region is provided in a first recess extending in the thickness direction of the semiconductor layer and includes an insulating material having a lower refractive index than the semiconductor layer; The second isolation region includes a conductive material provided in a second recess extending in the thickness direction of the semiconductor layer via an isolation insulating film having a lower refractive index than the semiconductor layer, The photodetector, wherein the plurality of photoelectric conversion regions includes two or more types of photoelectric conversion regions having different
  • the photodetector according to (54) above further comprising a light shielding film provided on the second surface side of the semiconductor layer so as to overlap with the second region in plan view.
  • the photodetector according to (54) or (55) above wherein the width of the light shielding film along the one direction is different depending on the width of the photoelectric conversion region.
  • a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second separation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer into signal charges; a charge holding unit provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion unit; a dielectric in which an insulating film is provided via a fixed charge film in a third dug portion extending in the depth direction of the semiconductor layer;
  • a photodetector comprising: (60) The photodetector according to (59
  • the photodetector according to any one of (59) to (64) above, further comprising a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit.
  • a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second separation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding unit provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion unit; a multilayer body provided on the first surface side of the semiconductor layer
  • (70) further comprising a readout circuit electrically connected to the charge holding unit;
  • the photodetector according to any one of (67) to (69) above, wherein the pixel transistor included in the readout circuit is provided in the second semiconductor layer.
  • (71) a semiconductor layer having a first surface and a second surface located opposite to each other in a thickness direction; a first isolation region provided in a first recess extending in the thickness direction of the semiconductor layer and containing an insulating material having a lower refractive index than the semiconductor layer; a photoelectric conversion region partitioned by the first separation region; a second separation region including a conductive material provided in a second dug portion extending in the thickness direction of the semiconductor layer and separating the photoelectric conversion region in one direction into a first region and a second region; a photoelectric conversion unit provided in the first region and photoelectrically converting light incident from the second surface side of the semiconductor layer; a charge holding unit provided in the second region and holding signal charges photoelectrically converted by the photoelectric conversion unit
  • the photodetector according to any one of (1) to (71) above, an optical lens that forms an image of image light from a subject on an imaging surface of the photodetector, and output from the photodetector and a signal processing circuit that performs signal processing on a signal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
PCT/JP2022/043620 2021-11-26 2022-11-25 光検出装置及び電子機器 Ceased WO2023095893A1 (ja)

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US18/711,240 US20250006764A1 (en) 2021-11-26 2022-11-25 Light detecting device and electronic device
JP2023563765A JPWO2023095893A1 (https=) 2021-11-26 2022-11-25
CN202280069098.9A CN118103983A (zh) 2021-11-26 2022-11-25 光检测装置和电子设备
DE112022005653.3T DE112022005653T5 (de) 2021-11-26 2022-11-25 Fotodetektionsvorrichtung und elektronische vorrichtung
KR1020247015183A KR20240108393A (ko) 2021-11-26 2022-11-25 광 검출 장치 및 전자 기기

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025142948A1 (ja) * 2023-12-25 2025-07-03 ソニーセミコンダクタソリューションズ株式会社 光検出装置及び電子機器

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102950629B1 (ko) * 2020-11-10 2026-04-13 삼성전자주식회사 이미지 센서

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012204562A (ja) * 2011-03-25 2012-10-22 Sony Corp 固体撮像装置、および、その製造方法、電子機器
JP2015082510A (ja) * 2013-10-21 2015-04-27 ソニー株式会社 固体撮像素子および製造方法、並びに電子機器
JP2020027884A (ja) * 2018-08-13 2020-02-20 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器
WO2020170936A1 (ja) * 2019-02-20 2020-08-27 ソニーセミコンダクタソリューションズ株式会社 撮像装置
WO2020175195A1 (ja) * 2019-02-25 2020-09-03 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置および電子機器
JP2021027276A (ja) * 2019-08-08 2021-02-22 キヤノン株式会社 光電変換装置および機器
WO2021085172A1 (ja) * 2019-10-30 2021-05-06 ソニーセミコンダクタソリューションズ株式会社 受光素子、測距モジュール、および、電子機器
JP2021114538A (ja) * 2020-01-20 2021-08-05 ソニーセミコンダクタソリューションズ株式会社 撮像素子および撮像装置
JP2021153161A (ja) * 2020-03-25 2021-09-30 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、及び、固体撮像装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7090480B2 (ja) 2018-06-13 2022-06-24 前田建設工業株式会社 シールドセグメントの接続構造及び接続方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012204562A (ja) * 2011-03-25 2012-10-22 Sony Corp 固体撮像装置、および、その製造方法、電子機器
JP2015082510A (ja) * 2013-10-21 2015-04-27 ソニー株式会社 固体撮像素子および製造方法、並びに電子機器
JP2020027884A (ja) * 2018-08-13 2020-02-20 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器
WO2020170936A1 (ja) * 2019-02-20 2020-08-27 ソニーセミコンダクタソリューションズ株式会社 撮像装置
WO2020175195A1 (ja) * 2019-02-25 2020-09-03 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置および電子機器
JP2021027276A (ja) * 2019-08-08 2021-02-22 キヤノン株式会社 光電変換装置および機器
WO2021085172A1 (ja) * 2019-10-30 2021-05-06 ソニーセミコンダクタソリューションズ株式会社 受光素子、測距モジュール、および、電子機器
JP2021114538A (ja) * 2020-01-20 2021-08-05 ソニーセミコンダクタソリューションズ株式会社 撮像素子および撮像装置
JP2021153161A (ja) * 2020-03-25 2021-09-30 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、及び、固体撮像装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025142948A1 (ja) * 2023-12-25 2025-07-03 ソニーセミコンダクタソリューションズ株式会社 光検出装置及び電子機器

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KR20240108393A (ko) 2024-07-09
DE112022005653T5 (de) 2024-09-19

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