WO2023093193A1 - 一种存储芯片的电阻补偿装置、方法及存储芯片 - Google Patents

一种存储芯片的电阻补偿装置、方法及存储芯片 Download PDF

Info

Publication number
WO2023093193A1
WO2023093193A1 PCT/CN2022/116776 CN2022116776W WO2023093193A1 WO 2023093193 A1 WO2023093193 A1 WO 2023093193A1 CN 2022116776 W CN2022116776 W CN 2022116776W WO 2023093193 A1 WO2023093193 A1 WO 2023093193A1
Authority
WO
WIPO (PCT)
Prior art keywords
compensation
bit
resistance
decoder
array
Prior art date
Application number
PCT/CN2022/116776
Other languages
English (en)
French (fr)
Inventor
方伟
Original Assignee
浙江驰拓科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浙江驰拓科技有限公司 filed Critical 浙江驰拓科技有限公司
Publication of WO2023093193A1 publication Critical patent/WO2023093193A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present application relates to the field of storage technology, in particular to a resistance compensation device and method for a storage chip and a storage chip.
  • a low dropout regulator (Low Dropout Regulator, hereinafter referred to as "LDO”) is usually used to uniformly supply power to the bits in a bit array. Due to the different wiring lengths from the voltage output terminal of the LDO to each bit, affected by the wiring resistance, the voltage of the bit farther away from the LDO (hereinafter referred to as “far end bit”) will be higher than that of the bit closer to the LDO. (hereinafter referred to as “near end bit”) low. In order to ensure that the remote bit has enough voltage to ensure the success rate of reading and writing, it is necessary to increase the voltage output of the LDO.
  • LDO Low Dropout Regulator
  • FIG. 1 is a graph showing the relationship between the bit failure rate and the bit data LDO trace length of the memory chip under the same write times. As shown in FIG. 1 , tests have shown that in current memory chips, the lifespan of LDO near-end bits is obviously lower than the lifespan of LDO far-end bits.
  • the technicians proposed a method of compensating each bit through a compensation resistor, specifically by setting the sampling circuit to collect the circuit parameters (voltage or current) in the bit array, and calculating the compensation value according to the circuit parameters of the bit array , adjust the resistance value of the compensation resistor to balance the voltages of each bit.
  • this method requires an additional sampling circuit and a compensation resistor circuit, and the circuit structure is complex, which is not conducive to the miniaturization of the equipment, and the delay in compensation control is large, and it is difficult to obtain high compensation accuracy.
  • the purpose of this application is to provide a memory chip resistance compensation device, method and memory chip, which can perform resistance compensation on each element on the memory chip faster and with higher precision, and balance the voltage of each element, and compared with the existing The compensation scheme saves more chip space, thereby reducing chip cost.
  • the present application provides a resistance compensation device for a memory chip, which has a compensation resistance array structure composed of a plurality of compensation resistances and a plurality of compensation circuit switches;
  • the compensation resistor array structure is arranged between the bit power supply output end of the memory chip and the preset power supply end of the bit array of the memory chip;
  • the compensation circuit switch is set corresponding to the bits in the bit array
  • the compensation circuit switch and the corresponding bit are synchronously turned on and off, so as to synchronously change the total resistance value of the compensation resistor array structure to perform corresponding resistance compensation for the gated bit.
  • the compensation circuit switch and the corresponding bit are synchronously gated and synchronously turned off, so as to synchronously change the total resistance value of the compensation resistor array structure to perform corresponding switching on the gated bit.
  • Resistance compensation specifically:
  • the compensation circuit switch and the corresponding bit are synchronously strobed and turned off, so that when each bit is selected, the total output from the bit power supply output to the selected bit The trace resistance is the same.
  • each of the compensation resistor wirings is serially connected in series as two or more metal wires; each of the metal wires is connected through the compensation circuit switch.
  • the number of the metal wires is specifically two.
  • the compensation circuit switches are in one-to-one correspondence with the gate signal lines of the bit array.
  • the bit array is specifically a two-dimensional array
  • the gate signal lines specifically include x+1 bit lines in the abscissa direction and y+1 word lines in the ordinate direction;
  • the compensation circuit switches corresponding to each bit line are sequentially connected to the two between metal wires;
  • the compensation circuit switches corresponding to each word line are sequentially connected to the two between metal wires;
  • x and y are both positive integers, and in the same coordinate direction, the sum of the resistance values of the two sections of the compensation resistance traces between any two compensation switches is equal to the corresponding two gate signals Trace resistance between lines.
  • each of the compensation circuit switches is connected to the corresponding control terminal of the strobe signal line.
  • a first decoder, a second decoder, a third decoder and a fourth decoder are also included;
  • the input end of the first decoder is connected to the same group of bit line control pins as the input end of the second decoder, and the output end of the first decoder is connected to the bit line selection pins of each of the bit lines. switch, the output end of the second decoder is connected to the compensation circuit switch corresponding to each of the bit lines, and the decoding sequence of the control signal output by the second decoder is the same as that of the first decoder. on the contrary;
  • the input end of the third decoder is connected to the same group of word line control pins as the input end of the fourth decoder, and the output end of the third decoder is connected to the word line selection pins of each of the word lines. switch, the output end of the fourth decoder is connected to the compensation circuit switch corresponding to each of the word lines, and the decoding order of the control signal output by the fourth decoder is the same as that of the third decoder. on the contrary.
  • the compensation circuit switch is specifically a MOS transistor.
  • the output end of the bit power supply is specifically an output end of a linear voltage regulator or an output end of an operational amplifier
  • the voltage provided by the output terminal of the bit power supply is specifically a read operation voltage for the bit array or a write operation voltage for the bit array.
  • the present application further provides a memory chip, including the resistance compensation device for the memory chip described in any one of the above.
  • the present application also provides a resistance compensation method for a memory chip, which is applied to a compensation resistance array structure composed of a plurality of compensation resistances and a plurality of compensation circuit switches, and the compensation resistance array structure is set on the memory chip Between the bit power supply output end of the memory chip and the preset power supply end of the bit array of the memory chip, the compensation circuit switch is set corresponding to the bit in the bit array, and the resistance compensation method includes:
  • the resistance compensation device of the memory chip provided by the application has a compensation resistance array structure composed of a plurality of compensation resistances and a plurality of compensation circuit switches. Between the preset power supply terminals of the bit array, the compensation circuit switch and the bit in the bit array are set correspondingly, and the compensation circuit switch and the corresponding bit are synchronously strobed and synchronously turned off to change the compensation resistance synchronously
  • the total resistance value of the array structure performs corresponding resistance compensation for the selected bit, so that when each bit is selected, the total wiring resistance from the output end of the bit power supply to the bit tends to be consistent.
  • the compensation resistor is gated by setting the switch of the strobe compensation circuit synchronously with the receiving of the bit, and the corresponding resistance compensation is performed on the gated bit by using the total resistance value of the pre-designed compensation resistor array structure, compared with the sampling circuit After sampling, the compensation scheme is determined. No sampling circuit is required and the effect of synchronous compensation can be achieved. There is more space to design a more refined compensation resistance step size, so as to achieve faster and higher precision resistance compensation and balance the voltage of each element. It avoids the contradiction of reading and writing failure caused by insufficient far-end bit voltage and the short-lived life caused by too high near-end bit voltage. Compared with the existing compensation scheme, it saves chip space and reduces chip cost.
  • the present application also provides a resistance compensation method for a memory chip and the memory chip, which have the above-mentioned beneficial effects, and will not be repeated here.
  • Figure 1 is a graph showing the relationship between the bit failure rate of the memory chip and the bit data LDO trace length under the same write times
  • FIG. 2 is a schematic structural diagram of a first memory chip resistance compensation device provided in an embodiment of the present application
  • Fig. 3 is the schematic structural diagram of the resistance compensating device of the second storage chip provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a third resistance compensation device for a memory chip provided by an embodiment of the present application.
  • the core of this application is to provide a resistance compensation device and method for a memory chip and a memory chip, which can perform resistance compensation on each element on the memory chip faster and with higher precision, and balance the voltage of each element, and compared with the existing The compensation scheme saves more chip space, thereby reducing chip cost.
  • FIG. 2 is a schematic structural diagram of a first resistance compensation device for a memory chip provided by an embodiment of the present application.
  • the bit lines include BL0, BL1, ... BLx-1, BLx, and the corresponding bit lines
  • the strobe signals are BP0, BP1, ... BPx-1, BPx, and the bit line strobe signals are respectively input to the gate of the bit line strobe switch on the corresponding bit line;
  • the word lines include VWL0, VWL1, ... VWLy-1 , VWLy, the corresponding word line strobe signals are VWL0, VWL1, ...
  • each word line strobe signal is respectively input to the gate of the word line strobe switch on the corresponding word line; a bit line and When one word line is selected at the same time, only one bit is selected, so as to realize the selection of bits BitCell_00 to BitCell_xy in the two-dimensional bit array.
  • the gate signal line in the ordinate direction is added.
  • an embodiment of the present application provides a resistance compensation device for a memory chip, which has a compensation resistance array structure composed of a plurality of compensation resistances and a plurality of compensation circuit switches;
  • the compensation resistor array structure is arranged between the bit power supply output end of the memory chip and the preset power supply end of the bit array of the memory chip;
  • the compensation circuit switch is set correspondingly to the bits in the bit array
  • the compensation circuit switch and the corresponding bit are synchronously gated and synchronously turned off, so as to synchronously change the total resistance value of the compensation resistor array structure to perform corresponding resistance compensation for the gated bit.
  • the resistance compensation device for the memory chip provided in the embodiment of the present application is not limited to the structure shown in FIG. 2 .
  • the compensation circuit switch and the corresponding bit are synchronously strobed and synchronously turned off, so as to synchronously change the total resistance value of the compensation resistor array structure to perform corresponding resistance compensation for the gated bit, specifically: the compensation circuit
  • the switch and the corresponding bit are synchronously turned on and turned off, so that when each bit is selected, the total wiring resistance from the output end of the bit power supply to the selected bit is consistent.
  • bit for example BitCell_xy in FIG. 2
  • bit is connected to the voltage input terminal of the bit array (for example, Shown in Fig. 2 by the drain electrode of the bit line strobe switch corresponding to the bit line strobe signal BP0) the wiring resistance is the largest; BitCell_00) is strobed, the wiring resistance between the bit and the voltage input terminal of the bit array (such as the drain of the bit line gating switch corresponding to the bit line gating signal BP0 shown in Figure 2) Minimum, from which the maximum and minimum trace resistance in the bit array can be determined.
  • BitCell_xy in FIG. 2 the bit is connected to the voltage input terminal of the bit array (for example, Shown in Fig. 2 by the drain electrode of the bit line strobe switch corresponding to the bit line strobe signal BP0) the wiring resistance is the largest; BitCell_00) is strobed, the wiring resistance between the bit and the voltage input terminal of the bit array (such as the drain of the bit line gating switch
  • the resistance compensation device of the memory chip provided by the embodiment of the present application is to change the resistance value synchronously with each bit through the compensation resistance array structure arranged between the output end of the bit power supply and the voltage input end of the bit array, Therefore, the resistance value to be compensated for each bit is compensated correspondingly.
  • each bit When each bit is strobed, its corresponding compensation circuit switch is also synchronously gated, so that the total resistance value of the compensation resistor array structure is exactly the resistance value that the bit needs to compensate, so that when each bit is gated , The purpose of consistent total wiring resistance from the output end of the bit power supply to the selected bit.
  • the corresponding relationship between the compensation circuit switch and the bit can be one-to-one, one-to-many or many-to-one, which can be determined according to the physical space, cost and resistance compensation accuracy of the memory chip.
  • each bit corresponds to a gating mode of a compensation resistor array structure; if the resistance compensation accuracy is not high, then multiple adjacent bits can correspond to the selection mode of the same compensation resistor array structure. pass mode.
  • the compensation resistor can be in the form of a metal wire, a chip resistor, or a combination of different types of compensation resistors, and can be adaptively designed according to the physical space, cost, and resistance compensation accuracy of the memory chip.
  • the switch of the compensation circuit is implemented by an electronically controlled switching tube, such as a MOS tube, or other switching elements such as a relay and an IGBT.
  • the output terminal of the bit power supply in this application may specifically be the output terminal of a linear voltage regulator or the output terminal of an operational amplifier.
  • the voltage provided by the output terminal of the bit power supply may specifically be a read operation voltage for the bit array or a write operation voltage for the bit array.
  • the linear voltage regulator may be a low dropout linear voltage regulator.
  • the application of the memory chip resistance compensation device provided by this application compared with the control scheme in the prior art that uses a sampling circuit to sample and then adjust the compensation resistance, does not require a sampling circuit and can achieve the effect of synchronous compensation, that is, in the strobe bit
  • the wiring resistance of the bit is compensated, which not only saves chip space, thereby reducing the cost of the chip, but also has more space to design a more refined compensation resistance step, thereby achieving faster and higher precision.
  • the resistance compensation of each bit balances the voltage of each bit, and eliminates the contradiction that the reading and writing failure caused by the insufficient voltage of the far-end bit and the life-span reduction caused by the high voltage of the near-end bit.
  • the compensation resistors specifically adopt the compensation resistor traces used to connect the compensation circuit switches, and each compensation resistor traces are connected in series to form two or more metal wires; They are connected through a compensation circuit switch, so that after the compensation circuit switch is selected, different compensation resistance wirings are short-circuited.
  • the scheme of the compensation resistor traces included in the above series into two metal wires in series is not a complete two metal wires, but the compensation resistor traces are divided into two wires for connection as shown in Figure 2.
  • the two sets of connecting wires at both ends of the compensation circuit switch form a ladder-shaped compensation resistor array structure by the compensation resistor wiring and the compensation circuit switch.
  • more than two metal wires can be connected in series by each compensation resistor wiring, and then a checkerboard-shaped compensation resistor array structure can be formed by the compensation resistor wiring in the vertical direction and a plurality of compensation circuit switches in the horizontal direction. Then, the sum of the resistance values of the adjacent compensation resistor traces in the horizontal direction should be equal to the resistance value of the single-segment strobe signal line of the bit corresponding to each compensation circuit switch in the horizontal direction. For example, as shown in FIG. 2 , the sum of the resistance values of the two compensation resistor wires in the compensation resistor array structure is equal to the resistance value of a single-segment gate signal line in the bit array.
  • the laterally adjacent compensation circuit switches may not be connected to the same connection point.
  • the compensation resistor array structure is not limited to a planar structure, and may also be a three-dimensional structure.
  • the compensation resistor array structure can be a two-dimensional structure as shown in FIG. 2 or a three-dimensional structure, so as to adapt to application scenarios corresponding to different bit array structures and different resistance compensation precisions.
  • the compensation circuit switch can be set in one-to-one correspondence with the gate signal lines of the bit array. That is, if the bit array is a two-dimensional array, the number of switches in the compensation circuit is equal to the sum of the number of bit lines and the number of word lines; if the bit array is a three-dimensional array, the number of switches in the compensation circuit is equal to the number of bit lines and the number of word lines On the basis of the sum, add the number of gate signal lines in the vertical coordinate direction.
  • adjacent bits can be set to correspond to the same compensation circuit switch, and the compensation circuit switch and the gate signal line of the bit array can also be a pair many relationships.
  • the embodiments of the present application take the one-to-one correspondence between the compensation circuit switches and the gate signal lines of the bit array as an example for further description.
  • the specific corresponding relationship between the switch of the compensation circuit and the gate signal line of the bit array is related to the setting of the synchronous control signal of the switch of the compensation circuit.
  • the bit array is specifically a two-dimensional array
  • the gate signal lines specifically include x+1 bit lines in the abscissa direction and y+1 word lines in the ordinate direction;
  • the compensation circuit switches corresponding to the bit lines are sequentially connected between the two metal wires according to the reverse order of arrangement of the bit lines from the output end of the bit power supply;
  • the compensation circuit switches corresponding to each word line are sequentially connected between the two metal lines according to the reverse order of arrangement of the word lines from the output end of the bit power supply;
  • x and y are both positive integers, and in the same coordinate direction, the sum of the resistance values of the two sections of compensation resistance wiring between any two compensation switches is equal to the wiring between the corresponding two gating signal lines resistance.
  • the corresponding relationship between the gate signal line (gate switch) and the compensation circuit switch is represented by the same gate signal.
  • the compensation circuit switches corresponding to the bit lines that is, corresponding to the bit line strobe signals BPx, BPx-1, ... BP1,
  • the compensation circuit switch corresponding to BP0 is sequentially connected between the two metal wires;
  • the compensation circuit switch corresponding to each word line (that is, the compensation circuit switch corresponding to the word line strobe signal VWLy, VWLy-1, ... VW1, VWL0 ) are sequentially connected between two metal wires;
  • the preset voltage input terminal of the bit array is the drain of the bit line gate switch corresponding to the first bit line (that is, the gate signal switch corresponding to BP0); the smaller the word line number is, the closer the corresponding word line is to Voltage input for bit array.
  • sequence number arrangement shown in FIG. 2 may also be arranged in a reverse manner.
  • the address decoding direction of the compensation resistance array structure and the direction of the gate signal line is reversed.
  • the ath bit in the abscissa direction of the bit array is selected, that is, when the bit line BPa is selected
  • the x-a compensation circuit switch in the compensation resistance (Rcompx) in the abscissa direction in the resistance compensation array structure is selected
  • the control method of the compensation resistance (Rcompy) in the ordinate direction in the resistance compensation array structure is the same.
  • the sum of the resistance values of the two circled compensation resistance lines in the compensation resistance array structure in FIG. 2 is equal to the resistance value of the circled single-segment gate signal line in the bit array,
  • the structure has a similar structure to the bit array and realizes high-precision resistance compensation.
  • FIG. 3 is a schematic structural diagram of a second resistance compensation device for a memory chip provided by an embodiment of the present application.
  • each compensation circuit switch is connected to the control terminal of the corresponding gate signal line.
  • the compensation circuit switch can be directly connected to the control terminal of the gate signal line of the corresponding serial number (that is, the drain of the bit line gate switch on the bit line, the drain electrode of the word line gate switch on the word line) Gate) connection, so that the control terminal of the compensation circuit switch and the control terminal of the strobe signal line corresponding to the serial number are directly connected to the same control pin of the controller, so that the address decoding direction and the selection of the compensation resistor array structure can be achieved.
  • the address decoding direction of the communication signal line is opposite to the control effect, and the required resistance compensation purpose is realized.
  • FIG. 4 is a schematic structural diagram of a third resistance compensation device for a memory chip provided by an embodiment of the present application.
  • the resistance compensation device of the memory chip provided by the embodiment of the present application further includes a first decoder, a second decoder, a third decoder and a fourth decoder device;
  • the input end of the first decoder is connected to the same group of bit line control pins as the input end of the second decoder, the output end of the first decoder is connected to the bit line gating switch of each bit line, and the second decoder The output end of the decoder is connected to the compensation circuit switch corresponding to each bit line, and the decoding sequence of the control signal output by the second decoder is opposite to that of the first decoder;
  • the input end of the third decoder is connected to the same group of word line control pins as the input end of the fourth decoder, the output end of the third decoder is connected to the word line gating switch of each word line, and the fourth decoder The output end of the decoder is connected to the compensation circuit switch corresponding to each word line, and the decoding sequence of the control signal output by the fourth decoder is opposite to that of the third decoder.
  • the address decoding direction of the compensation resistor array structure is opposite to the address decoding direction of the gate signal line by setting a decoder with the opposite decoding direction.
  • the same group of bit line control pins A0, A1, ... An on the controller are also connected to the input end of the first decoder Y1 and the input end of the second decoder Y2, The difference is that the input pins of the first decoder Y1 are connected in reverse order to the bit line control pins A0, A1, ...
  • the input pins of the second decoder Y2 are connected to the bit line control pins A0, A1,...An are positive sequence connections; and the output pins of the first decoder Y1 correspond to the bit line strobe signals BPx, BPx-1,...BP1, BP0 in the bit array in turn, the second decoder
  • the output pins of Y2 correspond to the control signals BPx, BPx-1, .
  • the various embodiments corresponding to the resistance compensation device of the memory chip are described in detail above. On this basis, the application also discloses a memory chip corresponding to the resistance compensation method of the memory chip and a resistance compensation method of the memory chip.
  • the memory chip provided in the embodiments of the present application may include the resistance compensation device for the memory chip provided in any one of the foregoing embodiments.
  • the embodiment of the memory chip part corresponds to the embodiment of the resistance compensating device part of the memory chip, please refer to the description of the embodiment of the resistance compensating device part of the memory chip for the embodiment of the memory chip part, and details will not be repeated here.
  • the resistance compensation method of the memory chip provided by the embodiment of the present application is applied to a compensation resistance array structure composed of a plurality of compensation resistances and a plurality of compensation circuit switches. Between the preset power supply terminals of the bit array of the chip, the compensation circuit switch is set corresponding to the bits in the bit array.
  • the resistance compensation method includes:
  • the first control signal and the second control signal are issued synchronously, so as to perform corresponding resistance compensation on the gated bit by using the total resistance value of the compensation resistor array structure controlled by the second control signal.
  • the embodiment of the resistance compensation method part of the memory chip corresponds to the embodiment of the resistance compensation device part of the memory chip, please refer to the description of the embodiment of the resistance compensation device part of the memory chip for the embodiment of the resistance compensation method part of the memory chip , which will not be described here.
  • a memory chip resistance compensation device, method and memory chip provided by the present application have been introduced in detail above.
  • Each embodiment in the description is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.
  • the description is relatively simple.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种存储芯片的电阻补偿装置、方法及存储芯片，通过设置与位元接收同步选通补偿电路开关来选通补偿电阻，利用预先设计好的补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿，相较于采用采样电路采样后再确定补偿方案，无需采样电路且可以达到同步补偿的效果，具有更多空间设计更精细化的补偿电阻步长，从而实现更快、更高精度的电阻补偿，平衡各位元的电压，避免远端位元电压不足导致读写失败而近端位元电压过高导致寿命降低的矛盾，提高位元电阻一致性也能提高阵列读良率，且相较于现有补偿方案更节约芯片空间、进而降低了芯片成本。

Description

一种存储芯片的电阻补偿装置、方法及存储芯片
本申请要求于2021年11月24日提交中国专利局、申请号为202111407324.3、发明名称为“一种存储芯片的电阻补偿装置、方法及存储芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，特别是涉及一种存储芯片的电阻补偿装置、方法及存储芯片。
背景技术
存储芯片中通常通过低压差线性稳压器(Low Dropout Regulator，下文检简称“LDO”)为一个位元阵列中的位元统一供电。由于LDO的电压输出端到各位元的走线长度不同，受走线电阻的影响，距离LDO较远的位元(下文称“远端位元”)的电压将比距离LDO较近的位元(下文称“近端位元”)低。为了保证远端位元有足够的电压来保证读写成功率，就需要提高LDO的电压输出。
但是，芯片的读写寿命对电压敏感，过高的电压又会降低芯片的读写寿命。图1为存储芯片在相同写次数下位元的故障率与位元据LDO走线长度的对应关系图。如图1所示，经测验表明，在当前的存储芯片中，LDO近端位元的寿命明显低于LDO远端位元的寿命。
对此，技术人员提出了通过补偿电阻对各位元进行补偿的方法，具体为通过设置采样电路采集位元阵列中的电路参数(电压或电流)，根据位元阵列的电路参数计算得到补偿值后，调整补偿电阻的阻值，以平衡各位元的电压。然而，这种方式需要额外设置采样电路和补偿电阻电路，电路结构复杂，不利于设备小型化，且在补偿控制上延迟较大、难以获得较高的补偿精度。
发明内容
本申请的目的是提供一种存储芯片的电阻补偿装置、方法及存储芯片， 能够更快、更高精度的对存储芯片上各位元进行电阻补偿，平衡各位元的电压，且相较于现有补偿方案更节约芯片空间、进而降低了芯片成本。
为解决上述技术问题，本申请提供一种存储芯片的电阻补偿装置，具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构；
所述补偿电阻阵列结构设于存储芯片的位元电源输出端与所述存储芯片的位元阵列的预设供电端之间；
其中，所述补偿电路开关与所述位元阵列中的位元对应设置；
所述补偿电路开关与对应的所述位元被同步选通、同步关断，以同步改变所述补偿电阻阵列结构的总阻值对被选通的所述位元进行对应的电阻补偿。
可选的，所述补偿电路开关与对应的所述位元被同步选通、同步关断，以同步改变所述补偿电阻阵列结构的总阻值对被选通的所述位元进行对应的电阻补偿，具体为：
所述补偿电路开关与对应的所述位元被同步选通、同步关断，以使各所述位元被选中时、自所述位元电源输出端至被选中的所述位元的总走线电阻一致。
可选的，各所述补偿电阻走线顺次串联为两条或以上金属线；各所述金属线之间通过所述补偿电路开关连接。
可选的，所述金属线的数量具体为两条。
可选的，所述补偿电路开关与所述位元阵列的选通信号线一一对应。
可选的，所述位元阵列具体为二维阵列，所述选通信号线具体包括横坐标方向的x+1条位线和纵坐标方向的y+1条字线；
自所述位元电源输出端起，按与所述位线自所述位元电源输出端起相反的排布顺序，各所述位线对应的所述补偿电路开关依次连接于两条所述金属线之间；
自所述位元电源输出端起，按与所述字线自所述位元电源输出端起相反的排布顺序，各所述字线对应的所述补偿电路开关依次连接于两条所述金属线之间；
其中，x、y均为正整数，且在同一坐标方向上，任意两个所述补偿开 关之间的两段所述补偿电阻走线的阻值之和等于对应的两条所述选通信号线之间的走线电阻。
可选的，各所述补偿电路开关均与对应的所述选通信号线的控制端连接。
可选的，还包括第一译码器、第二译码器、第三译码器和第四译码器；
所述第一译码器的输入端与第二译码器的输入端连接同样的一组位线控制引脚，所述第一译码器的输出端连接各所述位线的位线选通开关，所述第二译码器的输出端连接与各所述位线对应的所述补偿电路开关，所述第二译码器输出的控制信号译码顺序与所述第一译码器相反；
所述第三译码器的输入端与第四译码器的输入端连接同样的一组字线控制引脚，所述第三译码器的输出端连接各所述字线的字线选通开关，所述第四译码器的输出端连接与各所述字线对应的所述补偿电路开关，所述第四译码器输出的控制信号译码顺序与所述第三译码器相反。
可选的，所述补偿电路开关具体为MOS管。
可选的，所述位元电源输出端具体为线性稳压器的输出端或运算放大器的输出端；
所述位元电源输出端提供的电压具体为对所述位元阵列的读操作电压或对所述位元阵列的写操作电压。
为解决上述技术问题，本申请还提供一种存储芯片，包括上述任意一项所述的存储芯片的电阻补偿装置。
为解决上述技术问题，本申请还提供一种存储芯片的电阻补偿方法，应用于具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构，所述补偿电阻阵列结构设于存储芯片的位元电源输出端与所述存储芯片的位元阵列的预设供电端之间，所述补偿电路开关与所述位元阵列中的位元对应设置，所述电阻补偿方法包括：
在生成对所述位元的第一控制信号时，生成对与所述位元对应的所述补偿电路开关的第二控制信号；
同步下发所述第一控制信号和所述第二控制信号，以利用经过所述第二控制信号控制后的所述补偿电阻阵列结构的总阻值对被选通的所述位元 进行对应的电阻补偿。
本申请所提供的存储芯片的电阻补偿装置，具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构，该补偿电阻阵列结构设于存储芯片的位元电源输出端与存储芯片的位元阵列的预设供电端之间，其中的补偿电路开关与位元阵列中的位元对应设置，且补偿电路开关与对应的位元被同步选通、同步关断，以同步改变补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿，以使各位元被选通时、自位元电源输出端至位元的总走线电阻趋于一致。通过设置与位元接收同步选通补偿电路开关来选通补偿电阻，利用预先设计好的补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿，相较于采用采样电路采样后再确定补偿方案，无需采样电路且可以达到同步补偿的效果，具有更多空间设计更精细化的补偿电阻步长，从而实现更快、更高精度的电阻补偿，平衡各位元的电压，避免远端位元电压不足导致读写失败而近端位元电压过高导致寿命降低的矛盾，且相较于现有补偿方案更节约芯片空间、进而降低了芯片成本。
本申请还提供一种存储芯片的电阻补偿方法及存储芯片，具有上述有益效果，在此不再赘述。
附图说明
为了更清楚的说明本申请实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为存储芯片在相同写次数下位元的故障率与位元据LDO走线长度的对应关系图；
图2为本申请实施例提供的第一种存储芯片的电阻补偿装置的结构示意图；
图3为本申请实施例提供的第二种存储芯片的电阻补偿装置的结构示 意图；
图4为本申请实施例提供的第三种存储芯片的电阻补偿装置的结构示意图。
具体实施方式
本申请的核心是提供一种存储芯片的电阻补偿装置、方法及存储芯片，能够更快、更高精度的对存储芯片上各位元进行电阻补偿，平衡各位元的电压，且相较于现有补偿方案更节约芯片空间、进而降低了芯片成本。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例一
图2为本申请实施例提供的第一种存储芯片的电阻补偿装置的结构示意图。
如图2所示，以具有x+1条位线、y+1条字线的二维位元阵列为例，其位线包括BL0、BL1、……BLx-1、BLx，对应的位线选通信号为BP0、BP1、……BPx-1、BPx，各位线选通信号分别输入对应的位线上的位线选通开关的栅极；字线包括VWL0、VWL1、……VWLy-1、VWLy，对应的字线选通信号为VWL0、VWL1、……VWLy-1、VWLy，各字线选通信号分别输入对应的字线上的字线选通开关的栅极；一条位线和一条字线同时选通时唯一选通一个位元，从而实现对二维位元阵列中位元BitCell_00至BitCell_xy的选通。此外，还有三维位元阵列，在横坐标方向的位线和纵坐标的字线的基础上增加纵坐标方向的选通信号线。
针对位元阵列，本申请实施例提供一种存储芯片的电阻补偿装置，具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构；
补偿电阻阵列结构设于存储芯片的位元电源输出端与存储芯片的位元阵列的预设供电端之间；
其中，补偿电路开关与位元阵列中的位元对应设置；
补偿电路开关与对应的位元被同步选通、同步关断，以同步改变补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿。
需要说明的是，本申请实施例提供的存储芯片的电阻补偿装置不限于图2中所示的结构。
优选的是，补偿电路开关与对应的位元被同步选通、同步关断，以同步改变补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿，具体为：补偿电路开关与对应的位元被同步选通、同步关断，以使各位元被选中时、自位元电源输出端至被选中的位元的总走线电阻一致。
可以理解的是，距位元电源输出端(如图2所示的VWR)最远的位元(例如图2中的BitCell_xy)被选通时，该位元到位元阵列的电压输入端(例如图2中所示的由位线选通信号BP0对应的位线选通开关的漏极)之间的走线电阻最大；同理，距位元电源输出端最近的位元(例如图2中的BitCell_00)被选通时，该位元到位元阵列的电压输入端(例如图2中所示的由位线选通信号BP0对应的位线选通开关的漏极)之间的走线电阻最小，由此可以确定位元阵列中的最大走线电阻和最小走线电阻。通过依次仿真测量的方式，或通过根据最大走线电阻、最小走线电阻和位元排布方式进行估算的方式，可以得到各位元对应的走线电阻与最大走线电阻之间的差值，即各位元需要进行补偿的阻值。本申请实施例提供的存储芯片的电阻补偿装置，即是要通过设于位元电源输出端与位元阵列的电压输入端之间的补偿电阻阵列结构，能够与各位元同步的改变阻值，从而对应地补偿各位元需要进行补偿的阻值。达到每个位元被选通时，其对应的补偿电路开关也被同步选通，使得补偿电阻阵列结构的总阻值正好为该位元需要补偿的阻值，从而使得各位元被选通时、自位元电源输出端至被选中的位元的总走线电阻一致的目的。
在具体实施中，补偿电路开关与位元的对应关系可以为一对一、一对多或多对一，具体可以根据存储芯片的物理空间、成本以及电阻补偿精度 制定。电阻补偿精度最大的情况下，各位元均唯一对应一种补偿电阻阵列结构的选通模式；若电阻补偿精度要求不高，则相邻的多个位元可以对应同一种补偿电阻阵列结构的选通模式。
补偿电阻可以采用金属线、贴片电阻等形式或不同类型的补偿电阻组合，具体可以根据存储芯片的物理空间、成本以及电阻补偿精度进行适应性设计。
补偿电路开关采用电控开关管实现，如可以采用MOS管，也可以采用如继电器、IGBT等其他开关元件。
本申请中的位元电源输出端，具体可以为线性稳压器的输出端或运算放大器的输出端。
位元电源输出端提供的电压具体可以为对位元阵列的读操作电压或对位元阵列的写操作电压。
线性稳压器具体可以为低压差线性稳压器。
应用本申请所提供的存储芯片的电阻补偿装置，相较于现有技术中采用采样电路采样后再调节补偿电阻的控制方案，无需采样电路且可以达到同步补偿的效果，即在选通位元的同时就对位元的走线电阻进行了补偿，从而不仅节约芯片空间、进而降低了芯片成本，且具有更多的空间设计更精细化的补偿电阻步长，从而实现更快、更高精度的电阻补偿，平衡各位元的电压，消除远端位元电压不足导致读写失败而近端位元电压过高导致寿命降低的矛盾。
实施例二
在上述实施例的基础上，如图2所示，补偿电阻具体采用用于连接补偿电路开关的补偿电阻走线，各补偿电阻走线顺次串联为两条及以上金属线；各金属线之间通过补偿电路开关连接，以使补偿电路开关被选通后对不同的补偿电阻走线进行短接。
需要说明的是，上述包含的各补偿电阻走线顺次串联为两条金属线的方案，并非完整的两条金属线，而是如图2所示的将补偿电阻走线分为用于连接补偿电路开关两端的两组连接线，由补偿电阻走线和补偿电路开关 构成梯子形状的补偿电阻阵列结构。
此外，可以由各补偿电阻走线顺次串联为两条以上金属线，则可以由纵向上的补偿电阻走线和横向上的多个补偿电路开关构成棋盘格形状的补偿电阻阵列结构。则在横向上相邻的各补偿电阻走线的阻值之和，应等于与该横向上各补偿电路开关对应的位元的单段选通信号线的阻值。例如如图2所示，补偿电阻阵列结构中两条补偿电阻走线的阻值之和等于位元阵列中的单段选通信号线的阻值。
在此基础上，横向上相邻的补偿电路开关可以不连接于同一连接点上。
此外，补偿电阻阵列结构不限于平面结构，还可以为三维立体结构。当位元阵列为三维结构时，补偿电阻阵列结构可以为图2所示的二维结构，也可以为三维结构，以适应不同的位元阵列结构、不同的电阻补偿精度对应的应用场景。
实施例三
在上述实施例的基础上，如图2中的补偿电阻阵列结构的电路所示，若金属线的数量具体为两条，即由补偿电阻走线和补偿电路开关构成梯子形状的补偿电阻阵列结构，则可以设置补偿电路开关与位元阵列的选通信号线一一对应。即若位元阵列为二维阵列，则补偿电路开关的数量等于位线数量与字线数量之和；若位元阵列为三维阵列，则补偿电路开关的数量为在位线数量与字线数量之和的基础上再加上竖坐标方向的选通信号线的数量。
当然，若存储芯片空间、成本有限而对电阻补偿精度要求不高，则可以设置相邻的位元对应同样的补偿电路开关，补偿电路开关与位元阵列的选通信号线也可以为一对多的关系。
实施例四
在上述实施例的基础上，本申请实施例以补偿电路开关与位元阵列的选通信号线一一对应为例进行进一步说明。此时，补偿电路开关与位元阵列的选通信号线的具体对应关系与对补偿电路开关的同步控制信号的设置 相关。
如图2所示，位元阵列具体为二维阵列，选通信号线具体包括横坐标方向的x+1条位线和纵坐标方向的y+1条字线；
自位元电源输出端起，按与位线自位元电源输出端起相反的排布顺序，各位线对应的补偿电路开关依次连接于两条金属线之间；
自位元电源输出端起，按与字线自位元电源输出端起相反的排布顺序，各字线对应的补偿电路开关依次连接于两条金属线之间；
其中，x、y均为正整数，且在同一坐标方向上，任意两个补偿开关之间的两段补偿电阻走线的阻值之和等于对应的两条选通信号线之间的走线电阻。
在图2中，以相同的选通信号表示选通信号线(选通开关)与补偿电路开关的对应关系。具体可以如图2所示的，自位元电源输出端起，按位线序号递减的顺序，各位线对应的补偿电路开关(即与位线选通信号BPx、BPx-1、……BP1、BP0对应的补偿电路开关)依次连接于两条金属线之间；
自位元阵列的电压输入端起，按字线序号递减的顺序，各字线对应的补偿电路开关(即与字线选通信号VWLy、VWLy-1、……VW1、VWL0对应的补偿电路开关)依次连接于两条金属线之间；
其中，位元阵列的预设电压输入端为第1条位线对应的位线选通开关(即BP0对应的选通信号开关)的漏极；字线序号越小，对应的字线越靠近位元阵列的电压输入端。
在实际应用中，也可以按照与图2所示的序号排布方式相反的排布。
基于如图2所述的电阻补偿装置的结构，则按对应关系排序后(如均从序号0开始由小到大排列)，对补偿电阻阵列结构的地址译码方向与对选通信号线的地址译码方向相反。例如，当位元阵列横坐标方向上第a个位元被选通、即位线BPa被选通时，电阻补偿阵列结构中横坐标方向的补偿电阻(Rcompx)中第x-a个补偿电路开关被选通；电阻补偿阵列结构中纵坐标方向的补偿电阻(Rcompy)的控制方式同理。
在上述实施例中提到，图2中补偿电阻阵列结构中被圈出的两条补偿电阻走线的阻值之和等于位元阵列中被圈出的单段选通信号线的阻值，则 优选的，可以采用与位元阵列中材质相同的金属导线作为补偿电阻走线，根据电阻公式R＝ρL/S(R为电阻，ρ为电阻率，L为长度，S为横截面积)，设置补偿电阻走线的长度与对应的单段选通信号线的长度一致、补偿电阻走线的横截面积为单段选通信号线的横截面积的2倍等方式，使补偿电阻阵列结构与位元阵列有着相似的结构且实现高精度的电阻补偿。
实施例五
图3为本申请实施例提供的第二种存储芯片的电阻补偿装置的结构示意图。
在上述实施例的基础上，在本申请实施例提供的存储芯片的电阻补偿装置中，如图3所示，各补偿电路开关均与对应的选通信号线的控制端连接。
在上述实施例四的基础上，可以将补偿电路开关直接与对应序号的选通信号线的控制端(即位线上的位线选通开关的漏极、字线上的字线选通开关的栅极)连接，从而补偿电路开关的控制端与对应序号的选通信号线的控制端直接连接到控制器的同一控制引脚，即可达到对补偿电阻阵列结构的地址译码方向与对选通信号线的地址译码方向相反的控制效果，实现所需电阻补偿目的。
实施例六
图4为本申请实施例提供的第三种存储芯片的电阻补偿装置的结构示意图。
在上述实施例的基础上，如图4所示，本申请实施例提供的存储芯片的电阻补偿装置还包括第一译码器、第二译码器、第三译码器和第四译码器；
第一译码器的输入端与第二译码器的输入端连接同样的一组位线控制引脚，第一译码器的输出端连接各位线的位线选通开关，第二译码器的输出端连接与各位线对应的补偿电路开关，第二译码器输出的控制信号译码顺序与第一译码器相反；
第三译码器的输入端与第四译码器的输入端连接同样的一组字线控制引脚，第三译码器的输出端连接各字线的字线选通开关，第四译码器的输出端连接与各字线对应的补偿电路开关，第四译码器输出的控制信号译码顺序与第三译码器相反。
在上述实施例四的基础上，还可以通过设置译码方向相反的译码器的方式来实现对补偿电阻阵列结构的地址译码方向与对选通信号线的地址译码方向相反的控制效果。例如可以如图4所示的，控制器上同样一组位线控制引脚A0、A1、……An同样连接到第一译码器Y1的输入端和第二译码器Y2的输入端，区别在于在第一译码器Y1的输入端引脚对位线控制引脚A0、A1、……An是倒序连接，第二译码器Y2的输入端引脚对位线控制引脚A0、A1、……An是正序连接；而第一译码器Y1的输出端引脚依次对应位元阵列中的位线选通信号BPx、BPx-1、……BP1、BP0，第二译码器Y2的输出端引脚依次对应电阻补偿阵列结构中横坐标方向的电阻偏置补偿(Rcompx)中的补偿电路开关的控制信号BPx、BPx-1、……BP1、BP0。
第三译码器和第四译码器的连接规则参考上述描述即可，在此不再赘述。
上文详述了存储芯片的电阻补偿装置对应的各个实施例，在此基础上，本申请还公开了与存储芯片的电阻补偿方法对应的存储芯片及存储芯片的电阻补偿方法。
实施例七
本申请实施例提供的存储芯片，可以包括上述任意一项实施例提供的存储芯片的电阻补偿装置。
由于存储芯片部分的实施例与存储芯片的电阻补偿装置部分的实施例相互对应，因此存储芯片部分的实施例请参见存储芯片的电阻补偿装置部分的实施例的描述，这里暂不赘述。
实施例八
本申请实施例提供的存储芯片的电阻补偿方法，应用于具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构，补偿电阻阵列结构设于存储芯片的位元电源输出端与存储芯片的位元阵列的预设供电端之间，补偿电路开关与位元阵列中的位元对应设置，该电阻补偿方法包括：
在生成对位元的第一控制信号时，生成对与位元对应的补偿电路开关的第二控制信号；
同步下发第一控制信号和第二控制信号，以利用经过第二控制信号控制后的补偿电阻阵列结构的总阻值对被选通的位元进行对应的电阻补偿。
由于存储芯片的电阻补偿方法部分的实施例与存储芯片的电阻补偿装置部分的实施例相互对应，因此存储芯片的电阻补偿方法部分的实施例请参见存储芯片的电阻补偿装置部分的实施例的描述，这里暂不赘述。
以上对本申请所提供的一种存储芯片的电阻补偿装置、方法及存储芯片进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的存储芯片的电阻补偿方法及存储芯片而言，由于其与实施例公开的存储芯片的电阻补偿装置相对应，所以描述的比较简单，相关之处参见存储芯片的电阻补偿装置部分说明即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一 个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (12)

  1. 一种存储芯片的电阻补偿装置，其特征在于，具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构；
    所述补偿电阻阵列结构设于存储芯片的位元电源输出端与所述存储芯片的位元阵列的预设供电端之间；
    其中，所述补偿电路开关与所述位元阵列中的位元对应设置；
    所述补偿电路开关与对应的所述位元被同步选通、同步关断，以同步改变所述补偿电阻阵列结构的总阻值对被选通的所述位元进行对应的电阻补偿。
  2. 根据权利要求1所述的电阻补偿装置，其特征在于，所述补偿电路开关与对应的所述位元被同步选通、同步关断，以同步改变所述补偿电阻阵列结构的总阻值对被选通的所述位元进行对应的电阻补偿，具体为：
    所述补偿电路开关与对应的所述位元被同步选通、同步关断，以使各所述位元被选中时、自所述位元电源输出端至被选中的所述位元的总走线电阻一致。
  3. 根据权利要求1所述的电阻补偿装置，其特征在于，各所述补偿电阻走线顺次串联为两条或以上金属线；各所述金属线之间通过所述补偿电路开关连接。
  4. 根据权利要求3所述的电阻补偿装置，其特征在于，所述金属线的数量具体为两条。
  5. 根据权利要求4所述的电阻补偿装置，其特征在于，所述补偿电路开关与所述位元阵列的选通信号线一一对应。
  6. 根据权利要求5所述的电阻补偿装置，其特征在于，所述位元阵列具体为二维阵列，所述选通信号线具体包括横坐标方向的x+1条位线和纵坐标方向的y+1条字线；
    自所述位元电源输出端起，按与所述位线自所述位元电源输出端起相反的排布顺序，各所述位线对应的所述补偿电路开关依次连接于两条所述金属线之间；
    自所述位元电源输出端起，按与所述字线自所述位元电源输出端起相 反的排布顺序，各所述字线对应的所述补偿电路开关依次连接于两条所述金属线之间；
    其中，x、y均为正整数，且在同一坐标方向上，任意两个所述补偿开关之间的两段所述补偿电阻走线的阻值之和等于对应的两条所述选通信号线之间的走线电阻。
  7. 根据权利要求6所述的电阻补偿装置，其特征在于，各所述补偿电路开关均与对应的所述选通信号线的控制端连接。
  8. 根据权利要求6所述的电阻补偿装置，其特征在于，还包括第一译码器、第二译码器、第三译码器和第四译码器；
    所述第一译码器的输入端与第二译码器的输入端连接同样的一组位线控制引脚，所述第一译码器的输出端连接各所述位线的位线选通开关，所述第二译码器的输出端连接与各所述位线对应的所述补偿电路开关，所述第二译码器输出的控制信号译码顺序与所述第一译码器相反；
    所述第三译码器的输入端与第四译码器的输入端连接同样的一组字线控制引脚，所述第三译码器的输出端连接各所述字线的字线选通开关，所述第四译码器的输出端连接与各所述字线对应的所述补偿电路开关，所述第四译码器输出的控制信号译码顺序与所述第三译码器相反。
  9. 根据权利要求1所述的电阻补偿装置，其特征在于，所述补偿电路开关具体为MOS管。
  10. 根据权利要求1所述的电阻补偿装置，其特征在于，所述位元电源输出端具体为线性稳压器的输出端或运算放大器的输出端；
    所述位元电源输出端提供的电压具体为对所述位元阵列的读操作电压或对所述位元阵列的写操作电压。
  11. 一种存储芯片，其特征在于，包括权利要求1至10任意一项所述的存储芯片的电阻补偿装置。
  12. 一种存储芯片的电阻补偿方法，其特征在于，应用于具有由多个补偿电阻和多个补偿电路开关构成的补偿电阻阵列结构，所述补偿电阻阵列结构设于存储芯片的位元电源输出端与所述存储芯片的位元阵列的预设供电端之间，所述补偿电路开关与所述位元阵列中的位元对应设置，所述 电阻补偿方法包括：
    在生成对所述位元的第一控制信号时，生成对与所述位元对应的所述补偿电路开关的第二控制信号；
    同步下发所述第一控制信号和所述第二控制信号，以利用经过所述第二控制信号控制后的所述补偿电阻阵列结构的总阻值对被选通的所述位元进行对应的电阻补偿。
PCT/CN2022/116776 2021-11-24 2022-09-02 一种存储芯片的电阻补偿装置、方法及存储芯片 WO2023093193A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111407324.3 2021-11-24
CN202111407324.3A CN116168744A (zh) 2021-11-24 2021-11-24 一种存储芯片的电阻补偿装置、方法及存储芯片

Publications (1)

Publication Number Publication Date
WO2023093193A1 true WO2023093193A1 (zh) 2023-06-01

Family

ID=86420567

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/116776 WO2023093193A1 (zh) 2021-11-24 2022-09-02 一种存储芯片的电阻补偿装置、方法及存储芯片

Country Status (2)

Country Link
CN (1) CN116168744A (zh)
WO (1) WO2023093193A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116913341B (zh) * 2023-09-12 2024-04-30 温州核芯智存科技有限公司 一种存储器及补偿方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157203A (zh) * 2010-02-12 2011-08-17 台湾积体电路制造股份有限公司 存储器电路及其操作方法
CN103222004A (zh) * 2011-09-09 2013-07-24 松下电器产业株式会社 交叉点型电阻变化非易失性存储装置及其写入方法
CN107705813A (zh) * 2016-08-08 2018-02-16 爱思开海力士有限公司 非易失性存储装置及其电阻补偿电路
US20190385678A1 (en) * 2018-06-15 2019-12-19 Samsung Electronics Co., Ltd. Resistive memory device including compensation circuit
CN110660434A (zh) * 2018-06-29 2020-01-07 三星电子株式会社 存储器装置及其操作方法
CN110729012A (zh) * 2018-07-16 2020-01-24 台湾积体电路制造股份有限公司 存储器件、电阻式存储单元阵列的电压补偿控制器和方法
CN111755037A (zh) * 2019-03-27 2020-10-09 中芯国际集成电路制造(上海)有限公司 读出放大电路以及mram电路
CN112309472A (zh) * 2019-07-30 2021-02-02 三星电子株式会社 非易失性存储器件及其操作方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102157203A (zh) * 2010-02-12 2011-08-17 台湾积体电路制造股份有限公司 存储器电路及其操作方法
CN103222004A (zh) * 2011-09-09 2013-07-24 松下电器产业株式会社 交叉点型电阻变化非易失性存储装置及其写入方法
CN107705813A (zh) * 2016-08-08 2018-02-16 爱思开海力士有限公司 非易失性存储装置及其电阻补偿电路
US20190385678A1 (en) * 2018-06-15 2019-12-19 Samsung Electronics Co., Ltd. Resistive memory device including compensation circuit
CN110660434A (zh) * 2018-06-29 2020-01-07 三星电子株式会社 存储器装置及其操作方法
CN110729012A (zh) * 2018-07-16 2020-01-24 台湾积体电路制造股份有限公司 存储器件、电阻式存储单元阵列的电压补偿控制器和方法
CN111755037A (zh) * 2019-03-27 2020-10-09 中芯国际集成电路制造(上海)有限公司 读出放大电路以及mram电路
CN112309472A (zh) * 2019-07-30 2021-02-02 三星电子株式会社 非易失性存储器件及其操作方法

Also Published As

Publication number Publication date
CN116168744A (zh) 2023-05-26

Similar Documents

Publication Publication Date Title
TW201901674A (zh) 記憶體系統及感測裝置
WO2023093193A1 (zh) 一种存储芯片的电阻补偿装置、方法及存储芯片
US9105357B2 (en) Semiconductor memory device and defective judging method thereof
WO2010088443A1 (en) In-situ resistance measurement for magnetic random access memory (mram)
CN1123431A (zh) 提供电耦合到控制卡的远程定位外侧卡的方法和装置
KR20060009370A (ko) 저항성 메모리의 집적형 전하 센싱 구조
CN112767993A (zh) 测试方法以及测试系统
CN107369471A (zh) 存储器及其参考电路的校准方法
US10613128B2 (en) Testing device and testing method
US20240096434A1 (en) Error remapping
CN104991214A (zh) 数字集成电路直流参数标准复现方法及标准装置
WO2023093192A1 (zh) 一种存储芯片的电压调节装置、方法及存储芯片
JP2014187162A (ja) 半導体装置とそのトリミング方法
CN216351077U (zh) 功耗测试装置
TWI737519B (zh) 產生增強位元線電壓的操作方法及非揮發性記憶體裝置
US11055023B2 (en) Electronic device, related controller circuit and method
CN113791334A (zh) 可寻址测试芯片用开关电路及高密度可寻址测试芯片
CN112582017A (zh) 半导体存储装置及其测试方法
CN216718594U (zh) 可寻址测试芯片用开关电路及高密度可寻址测试芯片
CN220357193U (zh) 一种测试主板及测试装置
CN210075199U (zh) 一种dac和adc实验测试板及测试装置
US11935602B2 (en) Power management
US20050270865A1 (en) Test apparatus with memory data converter for redundant bit and word lines
CN217980578U (zh) 一种铂热电阻模拟板卡及模拟测试装置
US11551744B2 (en) Merged buffer and memory device including the merged buffer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22897285

Country of ref document: EP

Kind code of ref document: A1