Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
  • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
  • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/10—Arrangements for heating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/25—Arrangements for cooling characterised by their materials
  • H10W40/254—Diamond
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/25—Arrangements for cooling characterised by their materials
  • H10W40/258—Metallic materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
  • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

• the field relates to dissipating heat in microelectronics, and particularly in microelectronics formed of directly bonded elements.
• FIG. 1 schematically illustrates a cross-sectional view of an example microelectronic system according to some embodiments of the disclosed technology.
• FIG. 2 schematically illustrate a plan view of the example microelectronic system shown in FIG. 1.
• FIG. 3 schematically illustrates a cross-sectional view of another example microelectronic system according to some embodiments of the disclosed technology.
• Microelectronic elements e.g., dies/chips
• stacked and bonded to one another can be stacked and bonded to one another to form a device. It is difficult to dissipate heat in a device with chip stacking, especially as chips get thinner.
• chip joining methods such as adhesive bonding can make heat dissipation in the device less effective, as the adhesives may reduce or insulate heat transfer.
• a microelectronic device 100 may include thermal blocks/heat blocks 137 which can redirect the heat flow in the device, thus reducing the heat flow through a certain chip (e.g., 101 and 102) or particular region(s) of a chip in the device.
• a microelectronic device 100 may include one thermal block.
• a microelectronic device 100 may include multiple thermal blocks spaced apart from one another.
• the thermal block 137 may include a conductive thermal pathway to transfer heat from a bottom semiconductor element 1000 to a heat sink 131 disposed on top of the thermal block 137.
• a thermal block 137 (or thermal bypass) may occupy only a small footprint in a device 100.
• the thermal block 137 can be devoid of active circuitry (e.g., devoid of transistors). In other embodiments, it can also be devoid of passive circuits.
• a thermal block 137 is directly bonded to another element (e.g., a lower die 1000) in the device 100, thus avoiding the use of adhesives which may reduce heat transfer.
• the coefficient of thermal expansion (CTE) of the thermal block 137 may be chosen to substantially match with the CTE of that element, to avoid fractures or cracks in the bonded structure when the temperature rises during operation of the device 100.
• the element to which the thermal block 137 is directly bonded to e.g., the lower die 1000
• the thermal block material may have a CTE similar to that of silicon.
• the thermal block 137 is formed of a high thermal conductivity material (e.g., a material having a higher thermal conductivity than that of silicon or copper, at least at around the device operating temperature, e.g., about 0-40 °C).
• the thermal conductivity of the thermal block 137 may be higher than that of a neighboring chip (e.g., 101 and 102), thus redirecting the heat flow in the device 100 and reducing the heat flow through that neighboring chip (e.g., 101 and 102).
• the thermal block 137 may comprise a single crystal diamond block, a nano-fiber block, or a nano-porous metal (e.g., tungsten (W)) filled block.
• a stacked system 100 may include a thermal path unit 137 attached directly (e.g., directly bonded without an adhesive) to a bottom element 1000 (which may have a high temperature during operation) by way of direct bonding (e.g., nonconductive direct bonding or hybrid bonding in which nonconductive regions are directly bonded to one another and conductive features are directly bonded to one another).
• the thermal path unit 137 may be adjacent to at least one chip, e.g, first die 101.
• the thermal path unit 137 may be connected to a top thermal sink 131.
• the thermal path unit 137 may have a CTE under 10 pm/m°C (or close to that of Si) and a thermal conductivity higher than that of copper (e.g., many times of copper).
• heat flux in the stacked system 100 can be redirected, so that the heat flux through the thermal block 137 is larger than the heat flux through the first die 101. Therefore, a non-limiting advantage of the disclosed technology is that most of the heat bypasses the operational die(s), e.g., the first die 101 and/or the second die 102, so as to not negatively affect their operation.
• FIG. 1 and FIG. 2 schematically illustrate a cross-sectional view and a plan view of an example microelectronic system 100 having stacked semiconductor elements (e.g., dies/chips) and a thermal block 137 (or thermal bypass) which connects to a heat sink 131 (e.g., a metal heat sink or a heat pipe with fluid coolant) at the top of the stack.
• a heat sink 131 e.g., a metal heat sink or a heat pipe with fluid coolant
• the heat generated by the semiconductor elements during operation may be transferred to the heat sink and dissipated away from the system as illustrated by the arrows.
• the thermal block 137 may include a conductive thermal pathway to transfer heat from a bottom semiconductor element/base element 1000 to a heat sink 131 disposed on top of the thermal block 137.
• the thermal block 137 and one or a plurality of chips may be mounted on a base element 1000, which can be a die, wafer, etc.
• the thermal block 137 may be adjacent to at least one chip (e.g., at least “first die” 101) and thus reducing heat flow through the at least one chip.
• the thermal block 137 may also be adjacent to additional chips disposed on the base element 1000.
• the thermal block 137 may also be adjacent to the second die 102 and/or the third die 103.
• a method of operating the microelectronic system 100 may include directing a heat flux through the thermal block 137 that is disposed on the base element 1000 and a heat flux through the first die 101 (or the second die 102), such that the heat flux through the thermal block 137 is larger than the heat flux through the first die 101 (or the second die 102).
• the thermal block 137 has a CTE very close to that of the base element 1000.
• the thermal block 137 may have a CTE close to that of silicon (Si).
• the thermal block 137 may have a CTE lower than that of copper at least at around the device operating temperature, or no more than (e.g., less than) 10 pm/m°C, no more than 9 pm/m°C, no more than 8 pm/m°C, or more preferably no more than 7 pm/m°C.
• the thermal block 137 has a thermal conductivity greater than that of an adjacent chip (e.g., “first die”), thus reducing heat flow through the adjacent chip.
• the adjacent chip e.g., “first die”
• the thermal block 137 may have a thermal conductivity greater than that of silicon.
• the thermal block 137 has a thermal conductivity similar to that of copper or higher (e.g., about 3 times that of copper, or about 5 times that of copper).
• the thermal block 137 has a thermal conductivity of about 1000 to 2000 Wm' room temperature.
• the thermal block 137 may include diamond blocks (e.g., single crystal diamond) or alike, nano-fiber blocks, nano-porous metal (e.g., W) filled blocks, graphite, or GeSe.
• the thermal block 137 may be formed of an electrically non-conducting or semiconducting material, for example non-metal.
• the thermal block 137 is formed of materials that have both a low CTE (e.g., lower than 10 pm/m°C, e.g., lower than 8 pm/m°C or lower than 7 pm/m°C) and a thermal conductivity higher than that of Si at least at around the device operating temperature (for example, the thermal block may have a thermal conductivity higher than 100 Wm -1 K _1 , e.g., higher than 150 Wm ⁇ K 1 , at room tempetarue).
• a low CTE e.g., lower than 10 pm/m°C, e.g., lower than 8 pm/m°C or lower than 7 pm/m°C
• the thermal block may have a thermal conductivity higher than 100 Wm -1 K _1 , e.g., higher than 150 Wm ⁇ K 1 , at room tempetarue.
• the thermal block 137 may be mounted to base element 1000 by way of direct bonding without an intervening adhesive, such as nonconductive direct bonding techniques or hybrid direct bonding techniques.
• the thermal block 137 can be mounted using the ZIBOND® and/or DBI® processes configured for room temperature, atmospheric pressure direct bonding or the DBI® Ultra process configured for low-temperature hybrid bonding, which are commercially available from Adeia of San Jose, CA.
• the thermal block 137 may be mounted to the bottom chip by way of solder bonding or adhesive bonding.
• the thermal block may be mounted to the bottom chip via a thermal interface material (TIM).
• TIM thermal interface material
• the stacked semiconductor elements can be directly bonded to each other without an intervening adhesive.
• first die 101, “second die” 102 and/or “third die” 103 may be directly bonded (e.g., direct hybrid bonded) to the base element 1000.
• the top heat sink may be directly bonded to the semiconductor elements (e.g., “first die” 101, “second die” 102 and/or “third die” 103) and/or the thermal block 137, or may be mounted to the semiconductor elements and/or the thermal block via a TIM.
• the direct bonding process may include the ZIBOND® and DBI® processes configured for room temperature, atmospheric pressure direct bonding or the DBI® Ultra process configured for low-temperature hybrid bonding, which are commercially available from Adeia of San Jose, CA.
• the direct bonds can be between dielectric materials of the bonded elements and, in some embodiments, can also include conductive materials at or near the bond interface for direct hybrid bonding.
• the conductive materials at the bonding interface may be bonding pads formed in or over a redistribution layer (RDL) over a die, and/or passive electronic components.
• RDL redistribution layer
• a microelectronic device may include a first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; and a thermal block disposed on the first semiconductor element and adjacent to the at least one second semiconductor element, the thermal block comprising a conductive thermal pathway to transfer heat from the first semiconductor element to a heat sink disposed on the thermal block, wherein a coefficient of thermal expansion (CTE) of the thermal block is less than 10 pm/m°C, and wherein a thermal conductivity of the thermal block is higher than 150 Wnf'K’ 1 at room temperature.
• the thermal block is configured to reduce a heat flow through the at least one second semiconductor element.
• the at least one second semiconductor element may comprise silicon, and a thermal conductivity of the thermal block at around the device operating temperature is higher than that of silicon, such that a heat flux through the thermal block is larger than that through the at least one second semiconductor element during operation of the microelectronic device.
• a coefficient of thermal expansion (CTE) of the thermal block is substantially similar to a CTE of the first semiconductor element.
• the first semiconductor element comprises silicon, and wherein a coefficient of thermal expansion (CTE) of the thermal block is substantially similar to the CTE of silicon.
• a coefficient of thermal expansion (CTE) of the thermal block is lower than that of copper.
• a coefficient of thermal expansion (CTE) of the thermal block is lower than 7 pm/m°C.
• a thermal conductivity of the thermal block is higher than that of the at least one second semiconductor element.
• a thermal conductivity of the thermal block is higher than that of silicon.
• a thermal conductivity of the thermal block is higher than 200 Wm -1 K _1 at room temperature. In one embodiment, a thermal conductivity of the thermal block is within 10% of that of copper. In one embodiment, a thermal conductivity of the thermal block is at least three times that of copper. In one embodiment, the thermal block comprises diamond, nano-fiber, a nano-porous metal, graphite, or GeSe. In one embodiment, the thermal block is formed of an electrically non-conducting or semiconducting material.
• the thermal block is directly bonded to the first semiconductor element without an intervening adhesive.
• the interface between the thermal block and the first semiconductor element comprises dielectric-to- dielectric direct bonds.
• the thermal block is bonded to the first semiconductor element by way of solder bonding.
• the thermal block is bonded to the first semiconductor element by way of adhesive bonding.
• the thermal block is bonded to the first semiconductor element by a thermal interface material (TIM).
• the at least one second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive.
• the interface between the at least one second semiconductor element and the first semiconductor element comprises conductor- to-conductor and dielectric-to-dielectric direct bonds.
• the heat sink is in contact with the at least one second semiconductor element. In one embodiment, the heat sink is directly bonded to the at least one second semiconductor element without an intervening adhesive. In one embodiment, the heat sink is directly bonded to the thermal block without an intervening adhesive. In one embodiment, the first semiconductor element comprises an integrated device die. In one embodiment, the least one second semiconductor element comprises an integrated device die. In one embodiment, the thermal block is devoid of active circuitry. In one embodiment, the thermal block is further devoid of passive circuits.
• FIG. 3 schematically illustrates a cross-sectional view of another example microelectronic system 300 having stacked semiconductor elements 301 (e.g., dies/chips), several thermal blocks 337, and a heat sink 331 (e.g., a metal heat sink or a heat pipe with fluid coolant) at the top of the stack.
• the thermal blocks 337 can be arranged in a variety of ways. In some embodiments, a thermal block 337 can extend from the bottom element 3000 to an upper die that is connected to the heat sink 331. In other embodiments, a thermal block 337 can extend from the bottom element 3000 directly to the heat sink 331.
• a thermal block 337 can extend from a lower die (which is mounted on the bottom element 3000) to the heat sink 331.
• the thermal blocks 337 can redirect heat flow in the system as indicated by the arrows, thus reducing heat flow through their adjacent/neighboring chips.
• a microelectronic device may include a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block directly bonded to the first integrated device die without an adhesive; and a heat sink disposed over at least the heat block.
• the heat block comprises a conductive thermal pathway to transfer heat from the first integrated device die to the heat sink.
• the heat block is configured to reduce a heat flow through the second integrated device die.
• the second integrated device die comprises silicon, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C.
• a heat flux through the heat block is larger than that through the second integrated device die during operation of the microelectronic device.
• the second integrated device die is directly bonded to the first integrated device die without an adhesive.
• a microelectronic device may include a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block disposed on the first integrated device die; and a heat sink disposed over at least the heat block, wherein a heat flux through the heat block is larger than that through the second integrated device die during operation of the microelectronic device.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• the second integrated device die is directly bonded to the first integrated device die without an adhesive.
• the heat block is directly bonded to the first integrated device die without an adhesive.
• a method of forming a microelectronic device disclosed herein may include: providing a first semiconductor element; bonding a second semiconductor element and a thermal block to the first semiconductor element; and providing a heat sink over the thermal block, the thermal block providing a thermal pathway between the first semiconductor element and the heat sink, wherein a coefficient of thermal expansion (CTE) of the thermal block is less than 10 pm/m°C, and wherein a thermal conductivity of the thermal block is higher than 150 Wm -1 K _1 at room temperature.
• the second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive.
• the thermal block is directly bonded to the first semiconductor element without an intervening adhesive.
• a method of operating a microelectronic device comprising a first integrated device die and a second integrated device die disposed on the first integrated device die may include: directing a first heat flux through a heat block disposed on the first integrated device die and a second heat flux through the second integrated device die, wherein the first heat flux through the heat block is larger than the second heat flux through the second integrated device die.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• a heat sink is disposed over at least the heat block.
• a die can refer to any suitable type of integrated device die.
• the integrated device dies can comprise an electronic component such as an integrated circuit (such as a processor die, a controller die, or a memory die), a microelectromechanical systems (MEMS) die, an optical device, or any other suitable type of device die.
• the electronic component can comprise a passive device such as a capacitor, inductor, or other surface-mounted device.
• Circuitry (such as active components like transistors) can be patterned at or near active surface(s) of the die in various embodiments. The active surface may be on a side of the die which is opposite the backside of the die. The backside may or may not include any active circuitry or passive devices.
• An integrated device die can comprise a bonding surface and a back surface opposite the bonding surface.
• the bonding surface can have a plurality of conductive bond pads including a conductive bond pad, and a non-conductive material proximate to the conductive bond pad.
• the conductive bond pads of the integrated device die can be directly bonded to the corresponding conductive pads of the substrate or wafer without an intervening adhesive
• the non-conductive material of the integrated device die can be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Directly bonding without an adhesive is described throughout U.S. Patent Nos.
• Various embodiments disclosed herein relate to directly bonded structures in which two elements can be directly bonded to one another without an intervening adhesive.
• Two or more electronic elements which can be semiconductor elements (such as integrated device dies, wafers, etc.), may be stacked on or bonded to one another to form a bonded structure.
• Conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure.
• the contact pads may comprise metallic pads formed in a nonconductive bonding region, and may be connected to underlying metallization, such as a redistribution layer (RDL).
• RDL redistribution layer
• the elements are directly bonded to one another without an adhesive.
• a non-conductive or dielectric material of a first element can be directly bonded to a corresponding non-conductive or dielectric field region of a second element without an adhesive.
• the non-conductive material can be referred to as a nonconductive bonding region or bonding layer of the first element.
• the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques.
• dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Patent Nos.
• Suitable dielectric materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, silicon carbonitride or diamond-like carbon. In some embodiments, the dielectric materials do not comprise polymer materials, such as epoxy, resin or molding materials.
• hybrid direct bonds can be formed without an intervening adhesive.
• dielectric bonding surfaces can be polished to a high degree of smoothness.
• the bonding surfaces can be cleaned and exposed to a plasma and/or etchants to activate the surfaces.
• the surfaces can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes).
• the activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding.
• the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces.
• the bonding surface can be terminated in a separate treatment to provide the additional species for direct bonding.
• the terminating species can comprise nitrogen.
• the bonding surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding interfaces. Thus, in the directly bonded structures, the bonding interface between two dielectric materials can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination treatments may be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
• conductive contact pads of the first element can also be directly bonded to corresponding conductive contact pads of the second element.
• a hybrid direct bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to- dielectric surfaces, prepared as described above.
• the conductor-to- conductor (e.g., contact pad to contact pad) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
• dielectric bonding surfaces can be prepared and directly bonded to one another without an intervening adhesive as explained above.
• Conductive contact pads (which may be surrounded by nonconductive dielectric field regions) may also directly bond to one another without an intervening adhesive.
• the respective contact pads can be recessed below exterior (e.g., upper) surfaces of the dielectric field or nonconductive bonding regions, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm.
• the nonconductive bonding regions can be directly bonded to one another without an adhesive at room temperature in some embodiments in the bonding tool described herein and, subsequently, the bonded structure can be annealed. Annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact one another to form a metal-to-metal direct bond.
• hybrid bonding techniques such as Direct Bond Interconnect, or DBI®, available commercially from Xperi of San Jose, CA, can enable high density of pads connected across the direct bond interface (e.g., small or fine pitches for regular arrays).
• the pitch of the bonding pads, or conductive traces embedded in the bonding surface of one of the bonded elements may be less 40 microns or less than 10 microns or even less than 2 microns.
• the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2.
• the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range
• the contact pads and/or traces can comprise copper, although other metals may be suitable.
• a first element can be directly bonded to a second element without an intervening adhesive.
• the first element can comprise a singulated element, such as a singulated integrated device die.
• the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies.
• the first element can be considered a host substrate and is mounted on a support in the bonding tool to receive the second element from a pick-and-place or robotic end effector.
• the second element of the illustrated embodiments comprises a die.
• the second element can comprise a carrier or a flat panel.or substrate (e.g., a wafer).
• the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process.
• a width of the first element in the bonded structure can be similar to a width of the second element.
• a width of the first element in the bonded structure can be different from a width of the second element.
• the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element.
• the first and second elements can accordingly comprise non-deposited elements.
• directly bonded structures unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present.
• the nanovoids may be formed due to activation of the bonding surfaces (e.g., exposure to a plasma).
• the bond interface can include concentration of materials from the activation and/or last chemical treatment processes.
• a nitrogen peak can be formed at the bond interface.
• an oxygen peak can be formed at the bond interface.
• the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.
• the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds.
• the bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.
• the bonding layers may have a surface roughness of less than 2 nm root mean square (RMS) per micron, or less than 1 nm RMS per micron.
• RMS root mean square
• metal-to-metal bonds between the contact pads in direct hybrid bonded structures can be joined such that conductive features grains, for example copper grains on the conductive features grow into each other across the bond interface.
• the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface.
• the bond interface can extend substantially entirely to at least a portion of the bonded contact pads, such that there is substantially no gap between the nonconductive bonding regions at or near the bonded contact pads.
• a barrier layer may be provided under the contact pads (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the contact pads, for example, as described in US 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.
• the disclosed technology relates to a microelectronic device comprising: a first semiconductor element; at least one second semiconductor element disposed on the first semiconductor element; and a thermal block disposed on the first semiconductor element and adjacent to the at least one second semiconductor element, the thermal block comprising a conductive thermal pathway to transfer heat from the first semiconductor element to a heat sink disposed on the thermal block, wherein a coefficient of thermal expansion (CTE) of the thermal block is less than 10 pm/m°C, and wherein a thermal conductivity of the thermal block is higher than 150 Wm ⁇ K 1 at room temperature.
• CTE coefficient of thermal expansion
• the thermal block is configured to reduce a heat flow through the at least one second semiconductor element.
• the at least one second semiconductor element comprises silicon, and wherein a thermal conductivity of the thermal block at around the device operating temperature is higher than that of silicon.
• a heat flux through the thermal block is larger than that through the at least one second semiconductor element during operation of the microelectronic device.
• a coefficient of thermal expansion (CTE) of the thermal block is substantially similar to a CTE of the first semiconductor element.
• the first semiconductor element comprises silicon, and wherein a coefficient of thermal expansion (CTE) of the thermal block is substantially similar to the CTE of silicon.
• a coefficient of thermal expansion (CTE) of the thermal block is lower than that of copper.
• a coefficient of thermal expansion (CTE) of the thermal block is lower than 7 pm/m°C.
• a thermal conductivity of the thermal block is higher than that of the at least one second semiconductor element.
• a thermal conductivity of the thermal block is higher than that of silicon.
• a thermal conductivity of the thermal block is higher than 200 Wm -1 K _1 at room temperature.
• a thermal conductivity of the thermal block is within 10% of that of copper.
• a thermal conductivity of the thermal block is at least three times that of copper.
• the thermal block comprises diamond, nano-fiber, a nano-porous metal, graphite, or GeSe.
• the thermal block is formed of an electrically nonconducting or semiconducting material.
• the thermal block is directly bonded to the first semiconductor element without an intervening adhesive.
• the interface between the thermal block and the first semiconductor element comprises dielectric-to-dielectric direct bonds.
• the thermal block is bonded to the first semiconductor element by way of solder bonding.
• the thermal block is bonded to the first semiconductor element by way of adhesive bonding.
• the thermal block is bonded to the first semiconductor element by a thermal interface material (TIM).
• TIM thermal interface material
• the at least one second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive.
• the interface between the at least one second semiconductor element and the first semiconductor element comprises conductor-to-conductor and dielectric-to-dielectric direct bonds.
• the heat sink is in contact with the at least one second semiconductor element.
• the heat sink is directly bonded to the at least one second semiconductor element without an intervening adhesive.
• the heat sink is directly bonded to the thermal block without an intervening adhesive.
• the first semiconductor element comprises an integrated device die.
• the least one second semiconductor element comprises an integrated device die.
• the thermal block is devoid of active circuitry.
• the thermal block is further devoid of passive circuits.
• the disclosed technology relates to a method of forming a microelectronic device, the method comprising: providing a first semiconductor element; bonding a second semiconductor element and a thermal block to the first semiconductor element; and providing a heat sink over the thermal block, the thermal block providing a thermal pathway between the first semiconductor element and the heat sink, wherein a coefficient of thermal expansion (CTE) of the thermal block is less than 10 pm/m°C, and wherein a thermal conductivity of the thermal block is higher than 150 Wm ⁇ K 1 at room temperature.
• CTE coefficient of thermal expansion
• the second semiconductor element is directly bonded to the first semiconductor element without an intervening adhesive.
• the thermal block is directly bonded to the first semiconductor element without an intervening adhesive.
• the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block directly bonded to the first integrated device die without an adhesive; and a heat sink disposed over at least the heat block.
• the heat block comprises a conductive thermal pathway to transfer heat from the first integrated device die to the heat sink.
• the heat block is configured to reduce a heat flow through the second integrated device die.
• the second integrated device die comprises silicon, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C.
• a heat flux through the heat block is larger than that through the second integrated device die during operation of the microelectronic device.
• the second integrated device die is directly bonded to the first integrated device die without an adhesive.
• the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a second integrated device die disposed on the first integrated device die; a heat block disposed on the first integrated device die; and a heat sink disposed over at least the heat block, wherein a heat flux through the heat block is larger than that through the second integrated device die during operation of the microelectronic device.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• the second integrated device die is directly bonded to the first integrated device die without an adhesive.
• the heat block is directly bonded to the first integrated device die without an adhesive.
• the disclosed technology relates to method of operating a microelectronic device comprising a first integrated device die and a second integrated device die disposed on the first integrated device die, the method comprising: directing a first heat flux through a heat block disposed on the first integrated device die and a second heat flux through the second integrated device die, wherein the first heat flux through the heat block is larger than the second heat flux through the second integrated device die.
• a coefficient of thermal expansion (CTE) of the heat block is lower than 10 pm/m°C, and wherein a thermal conductivity of the heat block is higher than that of silicon.
• a heat sink is disposed over at least the heat block.
• the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.”
• the word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
• the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
• the words “herein,” “above,” “below,” and words of similar import when used in this application, shall refer to this application as a whole and not to any particular portions of this application.
• first element when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements.
• words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively.
• the word “or” in reference to a list of two or more items that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
• conditional language used herein such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments. [0085] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure.

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• 2022
  • 2022-11-15 US US18/055,798 patent/US20230154816A1/en active Pending
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