WO2023088115A1 - Structure d'encapsulation, module de puce, architecture au niveau de la carte et dispositif de communication - Google Patents

Structure d'encapsulation, module de puce, architecture au niveau de la carte et dispositif de communication Download PDF

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Publication number
WO2023088115A1
WO2023088115A1 PCT/CN2022/130259 CN2022130259W WO2023088115A1 WO 2023088115 A1 WO2023088115 A1 WO 2023088115A1 CN 2022130259 W CN2022130259 W CN 2022130259W WO 2023088115 A1 WO2023088115 A1 WO 2023088115A1
Authority
WO
WIPO (PCT)
Prior art keywords
pin
dielectric layer
pin array
circuit board
chip module
Prior art date
Application number
PCT/CN2022/130259
Other languages
English (en)
Chinese (zh)
Inventor
郭小亚
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023088115A1 publication Critical patent/WO2023088115A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the embodiment of the present application provides a chip module, including: at least one cored packaging structure and at least one coreless packaging structure, the cored packaging structure and the coreless packaging structure are stacked, and the cored packaging structure is the The packaging structure provided by the first aspect of the embodiment;
  • the coreless packaging structure is located between two cored packaging structures; and the first pin array in the coreless packaging structure is connected to an adjacent cored
  • the first lead array of the package structure is opposite to and in contact with; the second lead array of the coreless package structure is opposite to and in contact with the second lead array of another adjacent core package structure.
  • FIG. 7 is a schematic structural diagram of the first type of chip module provided in the embodiment of the present application at a second viewing angle
  • FIG. 22 is a schematic structural diagram of the tenth chip module provided by the embodiment of the present application.
  • the embodiment of the present application also provides a chip module 30, the chip module 30 includes at least one packaging structure 31, for example, in Figure 5, the chip module 30 includes a packaging structure 31, in some examples, the chip module 30 It may include two packaging structures 31 (such as shown in FIG. 25 below), or the chip module 30 may also include three packaging structures 31 (see FIG. 26 below).
  • the packaging method adopted by the packaging structure 31 is different from that of the QFN packaging, so as to avoid that the signal can only be fanned out from the side close to the substrate 32 on the chip module 30 .
  • the second pin array 3111 may also include a plurality of second signal pins 3111a, for example, a plurality of second signal pins 3111a form the second pin array 3111 .
  • a plurality of second signal pins 3111 a are arranged at intervals around the outer edge of the second surface 3102 of the dielectric layer 310 .
  • One side of each second signal pin 3111a is exposed on the second side of the dielectric layer 310 (see FIG. 6 ).
  • the second pin array 3111 may also include a second signal pin 3111a.
  • the number of chips 33 is not limited, that is, the packaging structure 31 may have one chip 33 or multiple chips 33 .
  • each first signal pin 3110 a of the first pin array 3110 is electrically connected to the chip 33 .
  • the multiple first signal pins 3110a may be electrically connected to the multiple chips 33 respectively. It should also be noted that, when there are multiple chips 33 , the multiple chips 33 can also be electrically connected together through the connecting wire 330 .
  • the first ground pin 34, the second ground pin 35, the second metal connection structure 3113, and the third metal connection structure 3114 are all integrated with the substrate 32, for example, the substrate 32, the first The ground pin 34 , the second ground pin 35 , the second metal connection structure 3113 , and the third metal connection structure 3114 form an integral structure by stamping or integral molding.
  • the relative positional relationship between the first ground pin 34 and the second ground pin 35 includes but not limited to the following possibilities:
  • each first ground pin 34 may be completely opposite to the corresponding second ground pin 35 .
  • the vertical projection of the first ground pin 34 on the first surface 3101 of the dielectric layer 310 completely coincides with the vertical projection of the second ground pin 35 on the first surface 3101 of the dielectric layer 310 .
  • the bottom surface and the top surface of the chip module 30 composed of the two packaging structures 31 have the first signal pins 3110a fanning out, and the chip 33 sends out Signals can be fanned out from opposite sides of the chip module 30 .
  • the process of installing the chip module 30 between the first circuit board 10 and the second circuit board 20 can be roughly as follows: make the substrate 32 of one of the packaging structures 31 contact the ground point of the first circuit board 10, and the other packaging structure The first pin array 3110 of 31 is electrically connected with the second circuit board 20 .
  • the insulating layer 37 can isolate the first pin array of the first package structure 31a 3110 and solder, which is beneficial to ensure that the first pin array 3110 of the first package structure 31a cannot be connected together with the first ground pin 34 of the first package structure 31a through solder, so as to ensure the first pin array 3110 of the first package structure 31a
  • the pin array 3110 is not grounded to be able to transmit signals, so that the entire chip module 30 can work normally.
  • the packaging structure 31 exposed by the first pin array 3110 is the second The package structure 31b
  • the package structure 31 not exposed by the first pin array 3110 is the first package structure 31a. That is, the first pin array 3110 of the first package structure 31 a is completely enclosed in its own dielectric layer 310 .
  • the coreless package structure 312 may also have the first ground pin 34 and the second ground pin 310 arranged in the dielectric layer 310.
  • Two grounding pins 35, and the first grounding pin 34 of the coreless packaging structure 312 is electrically connected to the second grounding pin 35, and the first grounding pin 34 of the coreless packaging structure 312 is electrically connected to the substrate 32, so that When the substrate 32 of the coreless package structure 312 is grounded, the substrate 32 of the coreless package structure 312 can transmit the ground signal to the second ground pin 35 through the first ground pin 34 .
  • This embodiment provides a board-level architecture 100, which may include a first circuit board 10, a second circuit board 20, and the chip module 30 described in any one of the second and third embodiments above.
  • the chip module 30 is located between the first circuit board 10 and the second circuit board 20 .
  • the bottom surface of the chip module 30 faces the first circuit board 10
  • the top surface of the chip module 30 faces the second circuit board 20 .
  • the substrate 32 in the package structure 31 closest to the first circuit board 10 in the chip module 30 (for example, the first package structure 31a in FIG.
  • the second pin array 3111 in the packaging structure 31 of the second circuit board 20 (for example, the second packaging structure 31 b in FIG. 25 ) is electrically connected to the second circuit board 20 .
  • the board-level architecture 100 of the communication device does not need to set the adapter frame 11a to transfer signals, which solves the problem of large signal loss caused by the installation of the adapter frame 11a, the high manufacturing cost of the board-level architecture 100, and the unfavorable level architecture 100 miniaturization problem.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

La présente demande concerne, selon des modes de réalisation, une structure d'encapsulation, un module de puce, une architecture au niveau de la carte et un dispositif de communication, destinés à résoudre les problèmes de l'art antérieur, à savoir un long trajet de transmission du signal et une perte de signal importante causés par la nécessité de prévoir un cadre d'adaptation pour transmettre un signal lorsqu'une puce est encapsulée à l'aide d'un QFN. Dans une structure d'encapsulation décrite dans le présent mode de réalisation, un substrat, un premier réseau de broches, un second réseau de broches connecté électriquement au premier réseau de broches et au moins une puce sont disposés dans une couche diélectrique, les broches du premier réseau de broches étant connectées électriquement à une ou plusieurs des puces, et au moins une partie de la surface de chaque broche du second réseau de broches étant visible à partir d'une seconde surface de la couche diélectrique ; lorsque la structure d'encapsulation est placée entre deux cartes de circuit imprimé externes, le second réseau de broches est en contact et connecté électriquement à une carte de circuit imprimé externe, un signal est transmis à la carte de circuit imprimé externe par le biais de la puce, du premier réseau de broches et du second réseau de broches, le signal étant transmis sans cadre d'adaptation, et un trajet de transmission du signal est raccourci, de sorte que la perte dans un processus de transmission de signal est réduite.
PCT/CN2022/130259 2021-11-16 2022-11-07 Structure d'encapsulation, module de puce, architecture au niveau de la carte et dispositif de communication WO2023088115A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111355510.7 2021-11-16
CN202111355510.7A CN114267658A (zh) 2021-11-16 2021-11-16 封装结构、芯片模组、板级架构及通信设备

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WO2023088115A1 true WO2023088115A1 (fr) 2023-05-25

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WO (1) WO2023088115A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114267658A (zh) * 2021-11-16 2022-04-01 华为技术有限公司 封装结构、芯片模组、板级架构及通信设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030197290A1 (en) * 1999-12-16 2003-10-23 Crowley Sean Timothy Stackable semiconductor package and method for manufacturing same
CN1808711A (zh) * 2005-12-09 2006-07-26 威盛电子股份有限公司 封装体及封装体模块
US20060261453A1 (en) * 2005-03-16 2006-11-23 Yonggill Lee Semiconductor package and stack arrangement thereof
US20070114641A1 (en) * 2005-11-21 2007-05-24 Stmicroelectronics Asia Pacific Pte Ltd Ultra-thin quad flat no-lead (QFN) package
CN111867249A (zh) * 2019-04-29 2020-10-30 三星电机株式会社 印刷电路板组件
CN114267658A (zh) * 2021-11-16 2022-04-01 华为技术有限公司 封装结构、芯片模组、板级架构及通信设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030197290A1 (en) * 1999-12-16 2003-10-23 Crowley Sean Timothy Stackable semiconductor package and method for manufacturing same
US20060261453A1 (en) * 2005-03-16 2006-11-23 Yonggill Lee Semiconductor package and stack arrangement thereof
US20070114641A1 (en) * 2005-11-21 2007-05-24 Stmicroelectronics Asia Pacific Pte Ltd Ultra-thin quad flat no-lead (QFN) package
CN1808711A (zh) * 2005-12-09 2006-07-26 威盛电子股份有限公司 封装体及封装体模块
CN111867249A (zh) * 2019-04-29 2020-10-30 三星电机株式会社 印刷电路板组件
CN114267658A (zh) * 2021-11-16 2022-04-01 华为技术有限公司 封装结构、芯片模组、板级架构及通信设备

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