WO2023083095A1 - 一种电路板封装结构、电路板组件以及电子设备 - Google Patents

一种电路板封装结构、电路板组件以及电子设备 Download PDF

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Publication number
WO2023083095A1
WO2023083095A1 PCT/CN2022/129632 CN2022129632W WO2023083095A1 WO 2023083095 A1 WO2023083095 A1 WO 2023083095A1 CN 2022129632 W CN2022129632 W CN 2022129632W WO 2023083095 A1 WO2023083095 A1 WO 2023083095A1
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WIPO (PCT)
Prior art keywords
circuit board
ground
signal
packaging structure
board packaging
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Application number
PCT/CN2022/129632
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English (en)
French (fr)
Inventor
田耀华
叶涛
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华为技术有限公司
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Publication of WO2023083095A1 publication Critical patent/WO2023083095A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0227—Split or nearly split shielding or ground planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane

Definitions

  • the present application relates to the technical field of circuit boards, in particular to a circuit board packaging structure, circuit board components and electronic equipment.
  • the signal transmission between electronic components is realized through a circuit board, and the circuit board is usually a printed circuit board (Printed Circuit Board, PCB).
  • PCB printed Circuit Board
  • the signal transmission rate is increased to 112Gbps or even higher 224Gbps, most signals are modulated with multi-level levels. Since the modulation of the signal is divided into more level stages, the loss of signal swing increases, resulting in less crosstalk noise allowed by the signal swing under the same loss, and the performance requirements for crosstalk noise are also more stringent. Harsh. However, as the signal transmission rate increases, the crosstalk noise will accumulate higher in a wider frequency band, which will directly cause the signal-to-noise ratio of signal transmission to fail to meet the transmission requirements, and cannot achieve a higher signal transmission bandwidth.
  • Embodiments of the present application provide a circuit board packaging structure, a circuit board assembly, and an electronic device, which are used to solve or at least partially solve the technical problem of high crosstalk noise during high-speed signal transmission.
  • the embodiment of the first aspect of the present application provides a circuit board packaging structure, which includes a circuit board, at least one signal via hole group, and a shielding structure.
  • the circuit board includes a substrate body and signal traces and a ground layer arranged in the substrate body.
  • the signal via hole group includes at least one signal via hole, and the signal via hole penetrates at least a part of the substrate body, and the signal via hole is electrically connected to the signal wiring.
  • the shielding structure penetrates at least a part of the substrate body, and the shielding structure is arranged around the periphery of the signal via hole group and is electrically connected to the ground layer.
  • a shielding structure is provided on the circuit board, and the grounded shielding structure has the function of shielding and isolating the crosstalk noise generated by the signal via hole.
  • the shielding structure can block and isolate the crosstalk noise in one signal via group from being transmitted to the adjacent signal via group.
  • the shielding structure is arranged around the periphery of the signal via group, which can surround the crosstalk noise, so as to prevent the crosstalk noise from being transmitted outward, and is beneficial to reduce the crosstalk noise during high-speed signal transmission.
  • the circuit board packaging structure is electrically connected to the electronic component, and the electronic component has a ground pin.
  • the shielding structure includes at least two first ground via groups and at least two second ground via groups.
  • the first ground via groups and the second ground via groups are arranged alternately and arranged around the periphery of the signal via groups.
  • each first ground via group includes at least one first ground via, and the first ground via is electrically connected to the ground pin of the electronic component and electrically connected to the ground layer.
  • Each second ground via group includes at least one second ground via, and the second ground via is electrically connected to the ground layer.
  • the shielding structure is designed as the structural form of the first ground via group and the second ground via group, so that the ground pins of the electronic components can be inserted into the first ground via holes, which facilitates the assembly of the electronic components and the circuit board.
  • both the second ground via hole and the first ground via hole can block and isolate crosstalk noise to the signal via hole, enhance the anti-interference performance of the circuit board packaging structure, and facilitate high-speed signal transmission.
  • each first ground via group includes at least two first ground vias.
  • the first ground via group further includes a third ground via, the third ground via is located between two adjacent first ground vias, and the third ground via is electrically connected to the ground layer.
  • Adding a third ground via between the two first ground vias can improve the blocking and isolation density of the shielding structure against crosstalk noise, which is beneficial to reduce the probability of the electromagnetic wave of the signal crosstalking to the adjacent signal via, thereby improving the reliability of the circuit board. Anti-interference performance of package structure.
  • the circuit board further includes leads, one end of which is electrically connected to the signal via hole, and the other end is electrically connected to the signal trace.
  • Each group of second ground vias includes at least two second ground vias, and the lead wire passes through the gap between two adjacent second ground vias. Providing a gap between two adjacent second ground via holes can avoid the influence of the setting of the shielding structure on the arrangement of the leads.
  • the gap between two adjacent second ground vias on both sides of the lead is 0.6-2 mm.
  • first ground vias between adjacent first ground vias, between adjacent second ground vias, between first ground vias and second ground vias, between first ground vias and third ground vias
  • the spacing between the holes is 0.2-0.6mm. Setting the distance between the first ground via hole, the second ground via hole and the third ground via hole to 0.2-0.6 mm can ensure a high-density arrangement of the shielding structure, thereby improving the shielding effect of the shielding structure on crosstalk noise.
  • the circuit board packaging structure includes at least two signal via groups.
  • the first ground via group between two adjacent signal via groups is shared.
  • the second ground via group between two adjacent signal via groups is shared. Sharing the first ground via group or the second ground via group between two adjacent signal via groups is beneficial to reducing the structural size of the circuit board and making the structure of the holes on the circuit board more compact.
  • the circuit board packaging structure is electrically connected to the electronic component, and the electronic component has a ground pin.
  • the substrate body is provided with a shielding groove, the shielding groove penetrates at least a part of the substrate body, and the shielding groove is arranged around the periphery of the signal via hole group.
  • the shielding structure consists of insulating barriers and metal cladding.
  • the insulating retaining wall is filled in the shielding groove and arranged around the outer periphery of the signal via hole group.
  • the metal covering layer is located between the insulating retaining wall and the slot wall of the shielding slot, and is connected with the insulating retaining wall and the shielding slot. The metal covering layer is electrically connected to the ground layer and the ground pin of the electronic component.
  • the shielding structure can also be designed in the form of a connected shielding groove.
  • a metal covering layer is set in the shielding groove and an insulating retaining wall is filled, so that the grounding pins of the electronic components can be fixed in the insulating retaining wall, which is also convenient for the electronic components to be connected to the insulating retaining wall.
  • both the shielding groove and the insulation retaining wall can block and isolate crosstalk noise from signal via holes, enhance the anti-interference performance of the circuit board packaging structure, and facilitate high-speed signal transmission.
  • the insulating retaining wall is provided with connection holes.
  • the connection hole runs through at least a part of the insulating retaining wall, and a side wall of the connection hole exposes a part of the metal covering layer.
  • the ground pin of the electronic component is arranged in the connection hole, and is electrically connected with the metal covering layer through the side wall of the connection hole.
  • Connecting holes are provided on the insulating retaining wall so that the grounding pins of the electronic components can also be inserted into the connecting holes, thereby realizing packaging and fixing of the electronic components and the circuit board.
  • the ground pin can be in contact with the metal covering layer, so as to realize the electrical connection of the electronic components.
  • the circuit board further includes leads, one end of which is electrically connected to the signal via hole, and the other end is electrically connected to the signal trace.
  • the horizontal section of the shielding groove is C-shaped, and the lead wire passes through the opening of the C-shaped shielding groove. Wherein, the horizontal section is parallel to the surface of the circuit board. Likewise, setting the opening on the shielding groove can avoid the influence of the setting of the shielding structure on the arrangement of the lead wires.
  • the opening size of the C-shaped shielding groove is 0.6-2 mm.
  • setting the opening size of the C-shaped shielding groove to 0.6-2mm can not only meet the wiring requirements of the leads, but also minimize the probability of crosstalk noise being transmitted from the opening of the shielding groove, thereby improving the shielding structure’s resistance to crosstalk. The effect of noise shielding.
  • the circuit board packaging structure includes at least two signal via groups.
  • the shielding slots between two adjacent signal via hole groups are connected, and the shielding structures between the two adjacent signal via hole groups are shared.
  • two adjacent signal via groups share a connected shielding groove, which is beneficial to reducing the structural size of the circuit board and making the structure of the holes and slots on the circuit board more compact.
  • At least one signal via group includes a pair of differential pair vias. Designing the signal via group as a structural form of a differential pair of vias can make the transmitted signal form a differential signal, which is conducive to enhancing the anti-interference ability of the signal to noise.
  • the embodiment of the second aspect of the present application provides a circuit board assembly, including electronic components and any one of the above-mentioned circuit board packaging structures.
  • the electronic component has a signal pin and a ground pin, the signal pin is electrically connected to the signal via hole of the circuit board packaging structure, and the ground pin is electrically connected to the shielding structure of the circuit board packaging structure.
  • the above-mentioned circuit board assembly has the same technical effect as that of the circuit board packaging structure provided by the foregoing embodiments, which will not be repeated here.
  • the electronic component is a connector
  • the connector includes a male end and a female end.
  • the public end has a first signal pin and a first ground pin.
  • the female terminal has a second signal pin and a second ground pin.
  • the circuit board packaging structure includes a first circuit board packaging structure and a second circuit board packaging structure. Wherein, the first signal pin is plugged into the signal via hole of the first circuit board packaging structure, and the first ground pin is plugged into the shielding structure of the first circuit board packaging structure.
  • the second signal pin is plugged into the signal via hole of the packaging structure of the second circuit board, and the second ground pin is plugged into the shielding structure of the packaging structure of the second circuit board.
  • the electronic component is a chip, and the chip has signal solder balls and ground solder balls.
  • the signal solder balls are electrically connected to the signal via holes of the circuit board package structure, and the ground solder balls are electrically connected to the shielding structure of the circuit board package structure.
  • the embodiment of the third aspect of the present application provides an electronic device, including a casing and any circuit board assembly as described above, and the circuit board assembly is disposed in the casing.
  • the above-mentioned electronic device has the same technical effect as that of the circuit board assembly provided by the foregoing embodiments, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of an embodiment of the circuit board assembly in Fig. 2;
  • FIG. 4 is a schematic structural view of another embodiment of the circuit board assembly in FIG. 2;
  • FIG. 5 is a schematic diagram of an exploded structure of the connector and circuit board packaging structure in FIG. 2;
  • Fig. 6 is a structural schematic diagram of the connection between the chip and the circuit board packaging structure in Fig. 1;
  • FIG. 7 is a schematic top view of a circuit board packaging structure provided by an embodiment of the present application.
  • Fig. 8 is a schematic cross-sectional structure diagram of A-A in Fig. 7;
  • FIG. 9A is a schematic structural diagram of an embodiment of the shielding structure in FIG. 7;
  • FIG. 9B is a schematic diagram of a circuit board packaging structure and an exploded structure of electronic components provided by the embodiment of the present application.
  • FIG. 10 is a schematic top view of another circuit board packaging structure provided by the embodiment of the present application.
  • FIG. 11 is a schematic diagram of far-end crosstalk results of the circuit board package structure in FIG. 10;
  • FIG. 12 is a schematic diagram of near-end crosstalk results of the circuit board package structure in FIG. 10;
  • FIG. 13A is a schematic top view of another circuit board packaging structure provided by the embodiment of the present application.
  • Fig. 13B is a schematic cross-sectional structure diagram of B-B in Fig. 13A;
  • Fig. 14 is a schematic structural diagram of an embodiment of the shielding groove in Fig. 13A;
  • Fig. 15 is a schematic structural diagram of an embodiment of the shielding structure in Fig. 13A;
  • FIG. 16 is a schematic top view of another circuit board packaging structure provided by the embodiment of the present application.
  • first”, second, etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • orientation terms such as “upper”, “lower”, “left”, “right”, “horizontal” and “vertical” are defined relative to the schematic placement orientations of components in the drawings, It should be understood that these directional terms are relative concepts, which are used for description and clarification relative to each other, and which may change accordingly according to changes in the orientation in which components are placed in the drawings.
  • connection should be understood in a broad sense, for example, “connection” can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.
  • the present application provides an electronic device, and the electronic device may include electronic devices such as a router, a switch, a server, or a base station.
  • the embodiments of the present application do not place special limitations on the specific forms of the foregoing electronic devices.
  • the foregoing electronic device 01 is used as an example for description.
  • the electronic device 01 may include a casing 100 and a circuit board assembly 200 , and the circuit board assembly 200 may be installed in the casing 100 .
  • the circuit board assembly 200 may include a circuit board packaging structure 210 and an electronic component 220 .
  • the circuit board packaging structure 210 can be installed in the casing 100 through structures such as screws or screws, and the electronic component 220 can be arranged on the circuit board packaging structure 210 and electrically connected with the circuit board packaging structure 210 .
  • the electronic component 220 may include components such as a chip, a connector, or a filter, and the embodiment of the present application does not specifically limit the specific structure of the electronic component 220 .
  • the electronic component 220 is used as an example for illustration.
  • the circuit board packaging structure 210 may include a first circuit board packaging structure 210a and a second circuit board packaging structure 210b, and the electronic component 220 may include a male terminal 220a and a female terminal 220b.
  • the male terminal 220a may be electrically connected to the first circuit board packaging structure 210a
  • the female terminal 220b may be electrically connected to the second circuit board packaging structure 210b.
  • the electrically connected male terminal 220a and the first circuit board packaging structure 210a may be called a daughter card
  • the electrically connected female terminal 220b and the second circuit board packaging structure 210b may be called a backplane.
  • Central processing unit, memory, multiple control chips and other devices can be integrated on the backplane.
  • the daughter card can be mounted on the backplane through the insertion of the male end 220a and the female end 220b.
  • the daughter card can integrate more interfaces to increase the number of interfaces of the electronic device 01 .
  • a plurality of female terminals 220b may be provided on one backplane for electrical connection with the male terminals 220a of each daughter card.
  • the embodiment of the present application does not place a special limit on the number of backplanes and daughter cards in the casing 100 of the electronic device 01 .
  • first circuit board encapsulation structure 210a and the second circuit board encapsulation structure 210b in the above embodiment are vertically connected.
  • the first circuit board packaging structure 210a and the second circuit board packaging structure 210b can also be arranged in parallel as shown in FIG. connect.
  • the first circuit board packaging structure 210a and the second circuit board packaging structure 210b may also be connected horizontally as shown in FIG. 4 .
  • the embodiment of the present application does not place special limitations on the connection manner between the first circuit board packaging structure 210a and the second circuit board packaging structure 210b.
  • a plurality of via holes 20 are respectively provided on the first circuit board packaging structure 210a and the second circuit board packaging structure 210b, and a part of the via holes 20 are signal via holes. , and the other part is the ground via.
  • the public terminal 220 a has a plurality of pins distributed in an array, and some of the plurality of pins may be first signal pins 221 a for electrical connection with the signal vias in the vias 20 . The rest of the pins may be the first ground pins 222 a for electrical connection with the ground vias in the via holes 20 .
  • the female end 220 b also has a plurality of pins distributed in an array, and some of the pins may be the second signal pins 221 b for electrical connection with the signal vias in the vias 20 .
  • the rest of the pins can be the second ground pins 222 b for electrical connection with the ground vias in the via holes 20 .
  • the first signal pin 221a, the first ground pin 222a, the second signal pin 221b and the second ground pin 222b can all be designed as fisheye pins.
  • the male terminal 220a can be electrically connected to the first circuit board packaging structure 210a by plugging
  • the female terminal 220b can be electrically connected to the second circuit board packaging structure 210b by plugging.
  • the electronic component 220 can also use surface mount technology SMT or through-hole reflow soldering to realize the electrical connection with the circuit board packaging structure 210 .
  • the electronic component 220 may also be a chip 220c as shown in FIG. 6 .
  • the chip 220c has a plurality of solder balls distributed in an array, and some of the plurality of solder balls may be signal solder balls 221 for electrical connection with the signal vias in the via holes 20 .
  • the rest of the solder balls may be ground solder balls 222 for electrical connection with the ground vias in the via holes 20 .
  • the signal solder ball 221 and the ground solder ball 222 of the chip 220c can be assembled by SMT or through-hole reflow soldering. on the circuit board packaging structure 210 .
  • the frequency of signal transmission will correspondingly increase to 40GHz or even higher than 80GHz.
  • the crosstalk noise will accumulate higher in a wider frequency band, which requires the signal to be more stringent in the performance of the crosstalk noise.
  • the packaging structure design of the circuit board is one of the main factors that lead to the increase of crosstalk noise when the signal is transmitted at high speed. The encapsulation structure of the circuit board will be described in detail below.
  • Multiple sets of signal vias 212 and shielding structures 213 are provided on the circuit board 211 , and the following will take one set of signal vias 212 and shielding structures 213 as an example for illustration.
  • the circuit board 211 may include a substrate body 2110 as shown in FIG. 8 , and a signal trace 2111 and a ground layer 2112 disposed in the substrate body 2110 , and a dielectric layer 2113 may be disposed between the signal trace 2111 and the ground layer 2112 .
  • the substrate body 2110 can be a double-sided copper clad laminate.
  • the double-sided copper clad board includes a core board layer and copper foil layers covering both sides of the core board layer.
  • One of the copper foil layers in the double-sided copper clad board can be used as the signal trace 2111, and the other copper foil layer can be used as the ground layer 2112.
  • the core layer in the double-sided copper clad laminate can be used as the dielectric layer 2113 .
  • the copper foil layers on both sides of the double-sided copper-clad laminate can also be used as the signal wiring 2111 or the ground layer 2112 .
  • the circuit board 211 requires multiple layers of signal traces 2111 and ground layers 2112, multiple double-sided copper-clad boards can also be selected for lamination, and adhesive layers 2114 such as prepregs can be used to press and form adjacent double-sided copper-clad boards.
  • the signal via group 212 may include two signal vias 2121 as shown in FIG. 8 .
  • the two signal via holes 2121 are disposed through the substrate body 2110 and may be blind holes, buried holes or through holes.
  • the wall of each signal via hole 2121 is plated with a conductive metal material, and the signal trace 2111 is electrically connected to the signal via hole 2121 .
  • the circuit board 211 may also include a lead wire 214 as shown in FIG. 7 , one end of the lead wire 214 is electrically connected to the signal via hole 2121 , and the other end of the lead wire 214 is electrically connected to the signal trace 2111 .
  • the two signal vias 2121 may form a pair of differential pair vias.
  • the two lead wires 214 and the two signal traces 2111 electrically connected to the two signal via holes 2121 are arranged with equal length, equal width, and equal spacing, so that the transmitted signal can form a differential signal, so that the signal is equal in amplitude and phase.
  • the opposite differential transmission is beneficial to enhance the anti-interference ability of the signal to noise.
  • the signal via group 212 may also include a signal via 2121 .
  • the present application does not place any special limitation on the specific number of signal vias 2121 in the signal via group 212 .
  • multiple pairs of differential pair via holes may be provided on the circuit board 211 , and the multiple pairs of differential pair via holes may be in a rectangular array or in a circular array.
  • the embodiment of the present application does not place special restrictions on the specific distribution form of the differential pair vias.
  • the first signal pin 221a of the connector male end 220a can be plugged into the signal via hole 2121 of the first circuit board package structure 210a, and the second signal pin 221b of the connector female end 220b It can be inserted into the signal via hole 2121 of the second circuit board package structure 210b.
  • the signal solder balls 221 of the chip can be electrically connected to the signal via holes 2121 of the package structure 210 of the circuit board.
  • the shielding structure 213 can be designed as a via hole.
  • the via hole can be a blind hole, a buried hole or a through hole, and the via hole penetrates at least a part of the substrate body 2110 .
  • the depth of the via hole penetrating through the substrate body 2110 is greater than or equal to the depth of the signal via hole 2121 , and the shielding structure 213 surrounds the periphery of the signal via hole 2121 to achieve the function of blocking and isolating crosstalk noise.
  • the via hole can be electrically connected to the ground layer 2112, and the ground layer 2112 can have an anti-pad at the position where the signal via hole 2121 penetrates, and the signal trace 2111 can bypass the position where the shielding structure 213 penetrates to avoid short circuit.
  • the signal traces 2111 and the ground layer 2112 are arranged horizontally on the substrate body 2110 , the signal via holes 2121 and the shielding structure 213 are arranged vertically on the substrate body 2110 .
  • the signal traces 2111, the signal via holes 2121, the ground layer 2112 and the shielding structure 213 form at least one loop on the substrate body 2110.
  • the current flows along the signal traces 2111 and the signal vias 2121 in the loop, while carrying high and low level signals for transmission in the loop. After the signal is transmitted, it returns along with the circuit along the ground layer 2112 and the shielding structure 213 .
  • the signal when the signal is transmitted, the signal can be transmitted horizontally in the signal trace 2111 and vertically transmitted in the signal via hole 2121 .
  • the signal When the signal returns, the signal may return horizontally within the ground layer 2112 and return vertically at the shielding structure 213 . Since the depth of the via hole penetrating the substrate body 2110 is not less than the depth of the signal via hole 2121, the transmission path of the signal is wrapped in the return path of the signal, so that the crosstalk noise generated in the signal via hole 2121 can be blocked by the shielding structure 213 ,isolation.
  • the shielding structure 213 may include two first ground via hole groups 2131 and two second ground via hole groups 2132.
  • the first ground via hole group 2131 and the second ground via hole group 2132 are respectively It is electrically connected to the ground plane 2112 (shown in FIG. 8 ).
  • the first ground via group 2131 and the second ground via group 2132 may surround the outer periphery of the signal via group 212 (rectangular box with dotted lines shown in FIG. 7 ).
  • two first ground via hole groups 2131 are arranged side by side along the X direction
  • two second ground via hole groups 2132 are arranged side by side along the Y direction. Wherein, the X direction and the Y direction are set vertically.
  • the arrangement of the first ground via hole group 2131 and the second ground via hole group 2132 can also be arranged in a ring around the outer circumference of the signal via hole group 212 .
  • the following is an example in which the first ground via hole group 2131 and the second ground via hole group 2132 can be arranged in a rectangular shape around the periphery of the signal via hole group 212 .
  • each group of first ground vias 2131 may include two first ground vias 2131a arranged along the Y direction, and the first ground vias 2131a are electrically connected to the ground layer 2112 (shown in FIG. 8 ).
  • the wall of the first ground via hole 2131a is plated with a conductive metal material.
  • each first ground via group 2131 may further include a third ground via 2131b, and the third ground via 2131b is located between two adjacent first ground vias 2131a.
  • both ends of the third ground via hole 2131 b may be electrically connected to the ground layer 2112 .
  • the difference from the first ground via hole 2131 a is that the third ground via hole 2131 b is not electrically connected to the pin of the electronic component 220 .
  • the wall of the third ground via hole 2131b is plated with a conductive metal material.
  • the third ground via hole 2131b can be filled with materials such as insulating plastic or conductive metal material, and the third ground via hole 2131b can also be set as a hollow structure. The specific structure makes special restrictions.
  • each group of second ground vias 2132 may include a plurality of second ground vias 2132a arranged along the X direction, and both ends of the second ground vias 2132a may also be connected to the ground layer 2112 (Fig. 9B) electrical connection.
  • the difference from the first ground via hole 2131 a is that the second ground via hole 2132 a is also not electrically connected to the pin of the electronic component 220 .
  • Two groups of first ground via groups 2131 and two groups of second ground via groups 2132 may enclose a rectangular frame, and the signal via group 212 may be disposed within the rectangular frame.
  • the wall of the second ground via hole 2132a is plated with a conductive metal material.
  • the second ground via hole 2132a can be filled with materials such as insulating plastic or conductive metal material, and the second ground via hole 2132a can also be set as a hollow structure. The specific structure makes special restrictions.
  • the lead wire 214 (shown in FIG. 7 ) can pass through the gap between two adjacent second ground via holes 2132a.
  • the opening 2130 of the shielding structure 213 is formed between the walls of the two second ground via holes 2132 a on both sides of the lead wire 214 . If the distance S1 of the opening 2130 is less than 0.6 mm, the narrow opening 2130 is not conducive to the arrangement of the leads 214 . If the distance S1 of the opening 2130 is greater than 2 mm, it will be unfavorable to shield the crosstalk noise. Optionally, the distance S1 of the opening 2130 may be set to 0.6-2 mm.
  • the spacing S2 between adjacent second ground vias 2132a, between the first ground via 2131a and the second ground via 2132a, and between the first ground via 2131a and the third ground via 2131b can be set as 0.2-0.6mm.
  • the distance S2 between the two first ground via holes 2131a can also be set to 0.2-0.6mm.
  • the embodiment of the present application does not The specific number and size of the via holes 2131b are subject to special restrictions.
  • four groups of signal via groups 212 are taken as an example for illustration.
  • the opening distance S1 between the walls of the two second ground via holes 2132a in each group of signal via holes 212 is 0.6 mm.
  • the distance S2 between the holes 2132a and between the first ground via hole 2131a and the third ground via hole 2131b is 0.2mm.
  • the four groups of signal vias 212 are arranged in a rectangular array along the X direction and the Y direction, and the adjacent first ground vias 2131a and the third ground vias 2131b are shared along the X direction.
  • the abscissa represents the frequency of signal transmission (unit GHz), and the ordinate represents crosstalk noise (unit dB).
  • the curve relationship between the crosstalk noise between the four signal via groups 212 and the signal transmission frequency can be seen from the figure, the circuit board package structure 210 can realize the frequency of signal transmission up to 80GHz, and at the same time, the far-end crosstalk of the signal can meet -40dB requirements.
  • the circuit board package structure 210 can realize the frequency of signal transmission up to 80 GHz, and at the same time, the near-end crosstalk of the signal can meet the requirement of -40 dB.
  • each group of signal vias 212 is surrounded by a first grounding via group 2131 and a second group of vias.
  • Ground via group 2132 Each group of the first ground via hole group 2131 and the second ground via hole group 2132 are alternately arranged, and the second ground via hole group 2132 may also be shared between two adjacent signal via hole groups 212 .
  • the opening distance S1 between the walls of two second ground via holes 2132a in each group of signal via holes 212 is 2mm, between the adjacent second ground via holes 2132a, the first ground via hole 2131a and the second ground via hole 2131a
  • the distance S2 between the ground vias 2132 a and between the first ground vias 2131 a and the third ground vias 2131 b is 0.6 mm.
  • the shielding structure 213 can be designed in the form of a shielding groove 215 .
  • a shielding slot 215 may be provided on the circuit board 211 .
  • the depth of the shielding groove 215 penetrating the circuit board 211 is greater than or equal to the depth of the signal via hole group 212 , and the shielding groove 215 surrounds the periphery of the signal via hole group 212 .
  • the shielding groove 215 can be electrically connected to the ground layer 2112, and the ground layer 2112 can have an anti-pad at the position where the signal via hole 2121 penetrates, and the signal trace 2111 can bypass the position where the shielding groove 215 penetrates to avoid short circuit.
  • the horizontal section of the shielding groove 215 can be designed as a C shape with an opening 2130 , and the horizontal section is parallel to the surface of the circuit board 211 .
  • the lead wire 214 can pass through the opening 2130 of the C-shaped shielding groove 215 .
  • the size S1 of the opening 2130 of the shielding groove 215 on both sides of the lead wire 214 can be set to 0.6-2mm.
  • the shielding groove 215 can also be designed as a U-shape or a circular shape, and the embodiment of the present application does not place special limitations on the specific structural form of the shielding groove 215 .
  • the shielding structure 213 may include an insulating barrier 2133 and a metal covering layer 2134 .
  • the insulation retaining wall 2133 can be made of resin or glass fiber and filled in the shielding groove 215 and arranged around the periphery of the signal via hole group 212 .
  • the metal covering layer 2134 is located between the insulation retaining wall 2133 and the groove wall of the shielding groove 215, and the metal covering layer 2134 can be processed by copper plating, etc., and the metal covering layer 2134 is connected with the insulating retaining wall 2133 and the shielding groove 215.
  • the metal capping layer 2134 is also electrically connected to the ground layer 2112 (shown in FIG. 13B ) and pins of the electronic component 220 .
  • a connecting hole 2135 may be opened on the insulating barrier 2133 for connecting the electronic component 220 (shown in FIG. 1 ).
  • the connection hole 2135 may pass through at least a part of the insulating barrier 2133 , and a side wall of the connection hole 2135 exposes a part of the metal covering layer 2134 for electrical connection with the electronic component 220 .
  • the connection holes 2135 may be arranged at intervals.
  • the first ground pin 222a of the connector male end 220a can be plugged into the connection hole 2135 of the first circuit board packaging structure 210a, and is electrically connected to the metal covering layer 2134; the connector female end The second ground pin 222b of the circuit board 220b can be plugged into the connection hole 2135 of the second circuit board package structure 210b and electrically connected to the metal covering layer 2134 .
  • connection hole 2135 When the electronic component 220 is a chip, there is no need to open the connection hole 2135 at this time. It is only necessary to set pads on the top of the insulating barrier 2133 to electrically connect the pads to the metal covering layer 2134 .
  • the ground solder balls 222 of the chip can be electrically connected to the pads of the circuit board package structure 210 .
  • the embodiments of the present application do not impose special restrictions on the width of the shielding groove 215 and the shielding structure 213 .
  • each group of signal via holes 212 is surrounded by a shielding slot 215 and a shielding structure 213 .
  • Four groups of signal via groups 212 are also arranged in a rectangular array along the X direction and Y direction, and the shielding slots 215 between two adjacent signal via groups 212 along the X direction are connected, and the adjacent two signal via groups 212 The shielding structure 213 between them is shared.
  • the circuit board package structure 210 can also achieve a signal transmission frequency of 80 GHz, and at the same time, the far-end crosstalk and near-end crosstalk of the signal can both meet -40dB requirements.
  • the circuit board packaging structure 210 can also achieve a signal transmission frequency of 50 GHz, and at the same time, the far-end crosstalk and near-end crosstalk of the signal can meet the -40dB requirement Require.
  • the circuit board packaging structure 210 provided in the embodiment of the present application is not limited to the arrangement of the via-type shielding structure 213 or the shielding groove 215-type shielding structure 213 on the periphery of the signal via hole group 212 .
  • the through-hole shielding structure 213 and the shielding groove 215 shielding structure 213 can also be combined and arranged on the circuit board 211 .

Abstract

一种电路板封装结构（210）、电路板组件（200）以及电子设备（01），涉及电路板技术领域，用于解决或者至少部分解决信号高速传输时串扰噪声大的技术问题。电路板封装结构（210）包括电路板（211）、至少一个信号过孔组（212）以及屏蔽结构（213）。电路板（211）包括基板本体（2110）以及设置于基板本体（2110）内的信号走线（2111）和接地层（2112）。信号过孔组（212）包括至少一个信号过孔（2121），信号过孔（2121）贯穿基板本体（2110）的至少一部分，信号过孔（2121）与信号走线（2111）电连接。屏蔽结构（213）贯穿基板本体（2110）的至少一部分，屏蔽结构（213）围绕信号过孔组（212）的外周设置，且与接地层（2112）电连接。电路板封装结构（210）用于连接电子元件（220）。

Description

一种电路板封装结构、电路板组件以及电子设备
本申请要求于2021年11月10日提交国家知识产权局、申请号为202111327300.7、申请名称为“一种电路板封装结构、电路板组件以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路板技术领域，尤其涉及一种电路板封装结构、电路板组件以及电子设备。
背景技术
电子元件之间的信号传输通过电路板实现，电路板通常选用印制电路板(Printed Circuit Board，PCB)。当信号传输的速率提高至112Gbps甚至更高的224Gbps时，信号大多采用多阶电平进行调制。由于信号的调制被划分为更多的电平阶段，使得信号摆幅的损失增大，导致信号摆幅在同样的损耗下所允许的串扰噪声也须更少，对串扰噪声的性能要求也更加严苛。而随着信号传输速率的提高，串扰噪声却会在更宽的频带内累积的更高，从而直接导致信号传输的信噪比不能满足传输要求，无法实现更高的信号传输带宽。
发明内容
本申请实施例提供一种电路板封装结构、电路板组件以及电子设备，用于解决或者至少部分解决信号高速传输时串扰噪声大的技术问题。
为达到上述目的，本申请采用如下技术方案：
本申请的第一方面实施例提供一种电路板封装结构，该电路板封装结构包括电路板、至少一个信号过孔组以及屏蔽结构。电路板包括基板本体以及设置于基板本体内的信号走线和接地层。信号过孔组包括至少一个信号过孔，且信号过孔贯穿基板本体的至少一部分，信号过孔与信号走线电连接。屏蔽结构贯穿基板本体的至少一部分，且屏蔽结构围绕信号过孔组的外周设置，并与接地层电连接。
本申请实施例在电路板上设置有屏蔽结构，接地的屏蔽结构对信号过孔产生的串扰噪声具有屏蔽、隔离的作用。这样一来，当信号在高速传输时，屏蔽结构能够阻挡、隔离一组信号过孔组内的串扰噪声传输至相邻的信号过孔组。同时，屏蔽结构围绕信号过孔组的外周设置，能够包绕串扰噪声，从而避免串扰噪声向外传输，有利于减少信号高速传输时的串扰噪声。
在一些实施方式中，电路板封装结构与电子元件电连接，电子元件具有接地管脚。屏蔽结构包括至少两个第一接地过孔组和至少两个第二接地过孔组，第一接地过孔组与第二接地过孔组交替排列，且围绕信号过孔组的外周设置。其中，每组第一接地过孔组包括至少一个第一接地过孔，第一接地过孔与电子元件的接地管脚电连接，且与接地层电连接。每组第二接地过孔组包括至少一个第二接地过孔，第二接地过孔与接地层电连接。
将屏蔽结构设计为第一接地过孔组和第二接地过孔组的结构形式，使电子元件的 接地管脚能够插入第一接地过孔中，方便电子元件与电路板的装配。同时，第二接地过孔与第一接地过孔均能够对信号过孔起到阻挡、隔离串扰噪声的作用，增强了电路板封装结构的抗干扰性能，有利于信号的高速传输。
在一些实施方式中，每组第一接地过孔组包括至少两个第一接地过孔。第一接地过孔组还包括第三接地过孔，第三接地过孔位于相邻两个第一接地过孔之间，第三接地过孔与接地层电连接。在两个第一接地过孔之间增设第三接地过孔，能够提高屏蔽结构对串扰噪声的阻挡、隔离密度，有利于降低信号的电磁波向相邻信号过孔串扰的几率，从而提高电路板封装结构的抗干扰性能。
在一些实施方式中，电路板还包括引线，引线的一端与信号过孔电连接，另一端与信号走线电连接。每组第二接地过孔组包括至少两个第二接地过孔，引线穿过相邻两个第二接地过孔之间的间隙。在相邻两个第二接地过孔之间设置间隙，能够避免屏蔽结构的设置对引线布置造成的影响。
在一些实施方式中，引线两侧相邻两个第二接地过孔之间的间隙为0.6-2mm。将引线两侧相邻两个第二接地过孔之间的间隙设置为0.6-2mm，既能够满足引线的布线要求，又能够尽量降低串扰噪声从引线两侧相邻两个第二接地过孔之间的间隙向外传输的几率，从而提高了屏蔽结构对串扰噪声屏蔽的效果。
在一些实施方式中，相邻第一接地过孔之间、相邻第二接地过孔之间、第一接地过孔与第二接地过孔之间、第一接地过孔与第三接地过孔之间的间距为0.2-0.6mm。将第一接地过孔、第二接地过孔以及第三接地过孔之间的间距设置为0.2-0.6mm，能够保证屏蔽结构的高密布置，从而提高了屏蔽结构对串扰噪声屏蔽的效果。
在一些实施方式中，电路板封装结构包括至少两个信号过孔组。相邻两个信号过孔组之间的第一接地过孔组共用。或者，相邻两个信号过孔组之间的第二接地过孔组共用。相邻两个信号过孔组之间共用第一接地过孔组或者第二接地过孔组，有利于减小电路板的结构尺寸，使得电路板上开孔的结构更紧凑。
在一些实施方式中，电路板封装结构与电子元件电连接，电子元件具有接地管脚。基板本体开设有屏蔽槽，屏蔽槽贯穿基板本体的至少一部分，且屏蔽槽围绕信号过孔组的外周设置。屏蔽结构包括绝缘挡墙和金属覆盖层。绝缘挡墙填充于屏蔽槽内，且围绕信号过孔组的外周设置。金属覆盖层位于绝缘挡墙和屏蔽槽的槽壁之间，且与绝缘挡墙和屏蔽槽相连接。金属覆盖层与接地层和电子元件的接地管脚电连接。
屏蔽结构还可以设计为连通的屏蔽槽的结构形式，在屏蔽槽内设置金属覆盖层，并填充绝缘挡墙，能够使电子元件的接地管脚能够固定在绝缘挡墙中，同样方便电子元件与电路板的装配。同时，屏蔽槽与绝缘挡墙均能够对信号过孔起到阻挡、隔离串扰噪声的作用，增强了电路板封装结构的抗干扰性能，有利于信号的高速传输。
在一些实施方式中，绝缘挡墙开设有连接孔。连接孔贯穿绝缘挡墙的至少一部分，且连接孔的侧壁露出金属覆盖层的一部分。电子元件的接地管脚设置于连接孔内，且通过连接孔的侧壁与金属覆盖层电连接。在绝缘挡墙上设置连接孔，使电子元件的接地管脚同样能够插入连接孔内，从而实现电子元件与电路板的封装固定。接地管脚可以与金属覆盖层接触，从而实现电子元件的电连接。
在一些实施方式中，电路板还包括引线，引线的一端与信号过孔电连接，另一端 与信号走线电连接。屏蔽槽的水平截面为C形，引线穿过C形的屏蔽槽的开口。其中，水平截面与电路板的板面平行。同样，在屏蔽槽上设置开口，能够避免屏蔽结构的设置对引线布置造成的影响。
在一些实施方式中，C形的屏蔽槽的开口尺寸为0.6-2mm。同理，将C形的屏蔽槽的开口尺寸设置为0.6-2mm，既能够满足引线的布线要求，又能够尽量降低串扰噪声从屏蔽槽的开口向外传输的几率，从而提高了屏蔽结构对串扰噪声屏蔽的效果。
在一些实施方式中，电路板封装结构包括至少两个信号过孔组。相邻两个信号过孔组之间的屏蔽槽连通，且相邻两个信号过孔组之间的屏蔽结构共用。同理，相邻两个信号过孔组之间共用连通的屏蔽槽，有利于减小电路板的结构尺寸，使得电路板上开孔和开槽的结构更紧凑。
在一些实施方式中，至少一个信号过孔组包括一对差分对过孔。将信号过孔组设计为差分对过孔的结构形式，能够使传输的信号形成差分信号，从而有利于增强信号对噪声的抗干扰能力。
本申请的第二方面实施例提供一种电路板组件，包括电子元件以及如上所述的任意一种电路板封装结构。电子元件具有信号管脚与接地管脚，信号管脚与电路板封装结构的信号过孔电连接，接地管脚与电路板封装结构的屏蔽结构电连接。上述电路板组件具有与前述实施例提供的电路板封装结构相同的技术效果，此处不再赘述。
在一些实施方式中，电子元件为连接器，连接器包括公端和母端。公端具有第一信号管脚与第一接地管脚。母端具有第二信号管脚与第二接地管脚。电路板封装结构包括第一电路板封装结构和第二电路板封装结构。其中，第一信号管脚与第一电路板封装结构的信号过孔插接，第一接地管脚与第一电路板封装结构的屏蔽结构插接。第二信号管脚与第二电路板封装结构的信号过孔插接，第二接地管脚与第二电路板封装结构的屏蔽结构插接。当电子元件为连接器时，本申请实施例提供的电路板组件的串扰噪声更小，能够实现连接器高速传输信号的功能。
在一些实施方式中，电子元件为芯片，芯片具有信号焊球与接地焊球。信号焊球与电路板封装结构的信号过孔电连接，接地焊球与电路板封装结构的屏蔽结构电连接。当电子元件为芯片时，本申请实施例提供的电路板组件的串扰噪声更小，能够实现芯片高速传输信号的功能。
本申请的第三方面实施例提供一种电子设备，包括壳体以及如上所述的任意一种电路板组件，电路板组件设置于壳体内。上述电子设备具有与前述实施例提供的电路板组件相同的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的另一电子设备的结构示意图；
图3为图2中电路板组件的一种实施方式结构示意图；
图4为图2中电路板组件的另一实施方式结构示意图；
图5为图2中连接器与电路板封装结构的分解结构示意图；
图6为图1中芯片与电路板封装结构连接的结构示意图；
图7为本申请实施例提供的一种电路板封装结构的俯视结构示意图；
图8为图7中A-A的剖视结构示意图；
图9A为图7中屏蔽结构的一种实施方式结构示意图；
图9B为本申请实施例提供的电路板封装结构与电子元件的分解结构示意图；
图10为本申请实施例提供的另一电路板封装结构的俯视结构示意图；
图11为图10中电路板封装结构的远端串扰结果示意图；
图12为图10中电路板封装结构的近端串扰结果示意图；
图13A为本申请实施例提供的又一电路板封装结构的俯视结构示意图；
图13B为图13A中B-B的剖视结构示意图；
图14为图13A中屏蔽槽的一种实施方式结构示意图；
图15为图13A中屏蔽结构的一种实施方式结构示意图；
图16为本申请实施例提供的再一电路板封装结构的俯视结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
此外，本申请中，“上”、“下”、“左”、“右”、“水平”以及“竖直”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。
本申请提供一种电子设备，该电子设备可以包括路由器、交换机、服务器或者基站等电子设备。本申请实施例并不对上述电子设备的具体形式做特殊的限制。以下为了方便说明，如图1所示，以上述电子设备01为路由器进行举例说明。该电子设备01可以包括壳体100和电路板组件200，电路板组件200可以安装在壳体100内。
其中，电路板组件200可以包括电路板封装结构210和电子元件220。电路板封装结构210可以通过螺钉或者螺杆等结构安装在壳体100内，电子元件220可以设置在电路板封装结构210上，且与电路板封装结构210电连接。电子元件220可以包括芯片、连接器或者滤波器等器件，本申请实施例并不对电子元件220的具体结构做特殊的限制。
在一些实施方式中，如图2所示，以电子元件220为连接器进行举例说明。电路板封装结构210可以包括第一电路板封装结构210a和第二电路板封装结构210b，电子元件220可以包括公端220a和母端220b。其中，公端220a可以与第一电路板封装结构210a电连接，母端220b可以与第二电路板封装结构210b电连接。
其中，电连接后的公端220a与第一电路板封装结构210a可以称为子卡，电连接后的母端220b与第二电路板封装结构210b可以称为背板。背板上可以集成中央处理 器、内存、多个控制芯片等器件。子卡作为背板功能的扩展，可以通过公端220a与母端220b的插接搭载在背板上。例如，子卡可以集成更多的接口，以增加电子设备01的接口数量。此时，一个背板上可以设置多个母端220b，用于与各个子卡的公端220a电连接。本申请实施例并不对电子设备01壳体100内的背板和子卡数量做特殊的限制。
当然，上述实施例中的第一电路板封装结构210a和第二电路板封装结构210b之间为垂直连接。根据公端220a和母端220b结构的不同，以及电子设备01所需功能的不同，还可以使第一电路板封装结构210a和第二电路板封装结构210b之间采用如图3所示的平行连接。或者，还可以使第一电路板封装结构210a和第二电路板封装结构210b之间采用如图4所示的水平对接。本申请实施例并不对第一电路板封装结构210a和第二电路板封装结构210b之间的连接方式做特殊的限制。
在此基础上，具体的，如图5所示，在第一电路板封装结构210a和第二电路板封装结构210b上分别设置有多个过孔20，过孔20中的一部分为信号过孔，另一部分为接地过孔。公端220a具有多个阵列分布的管脚(pin)，多个管脚中的一部分可以为第一信号管脚221a，用于与过孔20中的信号过孔电连接。其余部分管脚可以为第一接地管脚222a，用于与过孔20中的接地过孔电连接。母端220b也具有多个阵列分布的管脚(pin)，多个管脚中的一部分可以为第二信号管脚221b，用于与过孔20中的信号过孔电连接。其余部分管脚可以为第二接地管脚222b，用于与过孔20中的接地过孔电连接。
其中，第一信号管脚221a、第一接地管脚222a、第二信号管脚221b以及第二接地管脚222b均可以设计为鱼眼针脚。在此情况下，可以使公端220a通过插接的方式与第一电路板封装结构210a电连接，可以使母端220b通过插接的方式与第二电路板封装结构210b电连接。当然，电子元件220也可以选用表面贴装技术SMT或者通孔回流焊等方式，实现与电路板封装结构210之间的电连接。
上述实施例是以电子元件220为连接器进行的举例说明。在另一些实施方式中，电子元件220还可以为如图6所示的芯片220c。芯片220c具有多个阵列分布的焊球，多个焊球中的一部分可以为信号焊球221，用于与过孔20中的信号过孔电连接。其余部分焊球可以为接地焊球222，用于与过孔20中的接地过孔电连接。在此情况下，为了实现芯片220c与电路板封装结构210之间的电连接，可以将芯片220c的信号焊球221与接地焊球222通过表面贴装技术SMT或者通孔回流焊等方式，装配在电路板封装结构210上。
当信号传输的速率提高至112Gbps甚至更高的224Gbps时，信号传输的频率也会相应的提高至40GHz甚至更高的80GHz。而随着信号传输速率的提高、频率的增大，串扰噪声却会在更宽的频带内累积的更高，这就要求信号对串扰噪声的性能也更加严苛。其中，电路板的封装结构设计，是导致信号在高速传输时串扰噪声增加的主要因素之一。以下将对电路板的封装结构进行详细说明。
为了有效减少信号高速传输时的串扰噪声影响，满足信号高速传输的要求，如图7所示，本申请提供的电路板封装结构210可以包括电路板211、信号过孔组212以及屏蔽结构213。多组信号过孔组212与屏蔽结构213均开设在电路板211上，以下将以其中一组信号过孔组212与屏蔽结构213为例进行说明。
电路板211可以包括如图8所示的基板本体2110，以及设置于基板本体2110内的信号走线2111和接地层2112，在信号走线2111与接地层2112之间可以设置介质层2113。具体的，基板本体2110可以选用双面覆铜板。双面覆铜板包括芯板层以及覆盖在芯板层两侧的铜箔层，双面覆铜板中的其中一面铜箔层可以作为信号走线2111，另一面铜箔层可以作为接地层2112，双面覆铜板中的芯板层则可以作为介质层2113。
当然，根据电路板211的不同结构设计，双面覆铜板中的两面铜箔层也可以均作为信号走线2111或者接地层2112。当电路板211需要多层信号走线2111和接地层2112时，还可以选用多个双面覆铜板进行层压，相邻双面覆铜板之间可以采用半固化片等粘接层2114压制成型。
信号过孔组212可以包括如图8所示的两个信号过孔2121。两个信号过孔2121贯穿基板本体2110设置，可以是盲孔、埋孔或者通孔。每个信号过孔2121的孔壁内镀覆有可以导电的金属材料，信号走线2111与信号过孔2121电连接。当然，电路板211还可以包括如图7所示的引线214，将引线214的一端与信号过孔2121电连接，引线214的另一端与信号走线2111电连接。
需要说明的是，当信号过孔组212为两个信号过孔2121时，两个信号过孔2121可以组成一对差分对过孔。与两个信号过孔2121分别电连接的两根引线214和两根信号走线2111，等长、等宽、等间距设置，能够使传输的信号形成差分信号，从而使信号进行振幅相等、相位相反的差分传输，有利于增强信号对噪声的抗干扰能力。
当然，信号过孔组212也可以包括一个信号过孔2121。本申请并不对信号过孔组212内信号过孔2121的具体数量做特殊的限制。此外，电路板211上可以开设多对差分对过孔，多对差分对过孔可以呈矩形阵列，也可以呈圆形阵列。本申请实施例并不对差分对过孔的具体分布形式做特殊的限制。
当电子元件220为连接器时，连接器公端220a的第一信号管脚221a可以与第一电路板封装结构210a的信号过孔2121插接，连接器母端220b的第二信号管脚221b可以与第二电路板封装结构210b的信号过孔2121插接。当电子元件220为芯片时，芯片的信号焊球221可以与电路板封装结构210的信号过孔2121电连接。
以上是对电路板211以及电路板211上的信号过孔组212进行的介绍。由于信号在电路板211的各信号走线2111之间通过信号过孔2121进行垂直传输，因此，为了实现对信号过孔组212的串扰噪声屏蔽，降低相邻信号过孔组212之间的串扰噪声，以下将对屏蔽结构213进行详细的介绍。
示例一：
在一些实施方式中，如图8所示，屏蔽结构213可以设计为过孔的结构形式，过孔可以是盲孔、埋孔或者通孔，且过孔贯穿基板本体2110的至少一部分。过孔贯穿基板本体2110的深度大于或等于信号过孔2121的深度，且屏蔽结构213围绕在信号过孔2121的外周，以实现对串扰噪声阻挡、隔离的作用。过孔可以与接地层2112电连接，接地层2112可以在信号过孔2121贯穿的位置开设反焊盘，信号走线2111可以绕开屏蔽结构213贯穿的位置，以避免造成短路。
这样一来，由于信号走线2111和接地层2112在基板本体2110上呈水平布置，信号过孔2121与屏蔽结构213在基板本体2110上呈竖直布置。信号走线2111、信号过 孔2121、接地层2112以及屏蔽结构213，在基板本体2110上构成至少一个回路。电流在回路内沿信号走线2111和信号过孔2121流动，同时携带高低电平信号在回路内传输。当信号完成传输后，又随电路沿接地层2112和屏蔽结构213返回。
由此可知，当信号传输时，信号可以在信号走线2111内进行水平传输，并且在信号过孔2121进行垂直传输。当信号返回时，信号可以在接地层2112内进行水平返回，并且在屏蔽结构213垂直返回。由于过孔贯穿基板本体2110的深度不小于信号过孔2121的深度，使得信号的传输路径被包绕在信号的返回路径内，从而使得信号过孔2121内产生的串扰噪声能够被屏蔽结构213阻挡、隔离。
具体的，如图9A所示，屏蔽结构213可以包括两个第一接地过孔组2131和两个第二接地过孔组2132，第一接地过孔组2131和第二接地过孔组2132分别与接地层2112(图8所示)电连接。第一接地过孔组2131与第二接地过孔组2132可以围绕在信号过孔组212(图7所示点画线矩形框)的外周。具体的，图9A中，两个第一接地过孔组2131沿X方向并排设置，两个第二接地过孔组2132沿Y方向并排设置。其中，X方向和Y方向垂直设置。当然，第一接地过孔组2131与第二接地过孔组2132的排列也可以呈圆环形围绕在信号过孔组212的外周。以下为了方便说明是以第一接地过孔组2131与第二接地过孔组2132可以排列呈矩形围绕在信号过孔组212的外周为例进行的举例说明。
其中，如图9A所示，每组第一接地过孔组2131可以包括两个沿Y方向排列的第一接地过孔2131a，第一接地过孔2131a与接地层2112(图8所示)电连接，第一接地过孔2131a的孔壁内镀覆有可以导电的金属材料。当电子元件220为连接器时，连接器公端220a的第一接地管脚222a可以与第一电路板封装结构210a的第一接地过孔2131a插接，连接器母端220b的第二接地管脚222b可以与第二电路板封装结构210b的第一接地过孔2131a插接。当电子元件220为芯片时，芯片的接地焊球222可以与电路板封装结构210的第一接地过孔2131a电连接。
在此基础上，如图9A所示，每组第一接地过孔组2131还可以包括第三接地过孔2131b，第三接地过孔2131b位于相邻两个第一接地过孔2131a之间。如图9B所示，第三接地过孔2131b的两端可以均与接地层2112电连接。与第一接地过孔2131a的不同之处在于，第三接地过孔2131b并不与电子元件220的管脚(pin)电连接。
其中，第三接地过孔2131b内的孔壁内镀覆有可以导电的金属材料。在第三接地过孔2131b内既可以填充绝缘塑胶等材料，也可以填充导电金属材料，还可以将第三接地过孔2131b设置为空心结构，本申请实施例并不对第三接地过孔2131b的具体结构做特殊的限制。
此外，如图9A所示，每组第二接地过孔组2132可以包括多个沿X方向排列第二接地过孔2132a，第二接地过孔2132a的两端也可以均与接地层2112(图9B所示)电连接。同理，与第一接地过孔2131a的不同之处在于，第二接地过孔2132a也不与电子元件220的管脚(pin)电连接。两组第一接地过孔组2131和两组第二接地过孔组2132可以围成矩形框，信号过孔组212可以设置在矩形框内。
其中，第二接地过孔2132a内的孔壁内镀覆有可以导电的金属材料。在第二接地过孔2132a内既可以填充绝缘塑胶等材料，也可以填充导电金属材料，还可以将第二 接地过孔2132a设置为空心结构，本申请实施例并不对第二接地过孔2132a的具体结构做特殊的限制。
在此基础上，如图9A所示，引线214(图7所示)可以穿过相邻两个第二接地过孔2132a之间的间隙。此时，引线214两侧的两个第二接地过孔2132a的孔壁之间形成屏蔽结构213的开口2130。若开口2130的距离S1小于0.6mm，开口2130过窄将不利于引线214的布置。若开口2130的距离S1大于2mm，将不利于串扰噪声的屏蔽。可选的，开口2130的距离S1可以设置为0.6-2mm。
同理，若相邻第二接地过孔2132a之间、第一接地过孔2131a与第二接地过孔2132a之间、第一接地过孔2131a与第三接地过孔2131b之间的间距S2小于0.2mm，则不利于各过孔的布置。若间距S2大于0.6mm，将不利于串扰噪声的屏蔽。因此，相邻第二接地过孔2132a之间、第一接地过孔2131a与第二接地过孔2132a之间、第一接地过孔2131a与第三接地过孔2131b之间的间距S2可以设置为0.2-0.6mm。当第一接地过孔组2131内仅设置有两个第一接地过孔2131a时，两个第一接地过孔2131a之间的间距S2也可以设置为0.2-0.6mm。
根据电路板211的阻抗设计、电子元件220管脚的布置、电路板211上排布的过孔尺寸，本申请实施例并不对第一接地过孔2131a、第二接地过孔2132a以及第三接地过孔2131b的具体数量和尺寸做特殊的限制。
示例的，如图10所示，以四组信号过孔组212为例进行说明。每组信号过孔组212中两个第二接地过孔2132a孔壁之间的开口距离S1为0.6mm，相邻第二接地过孔2132a之间、第一接地过孔2131a与第二接地过孔2132a之间、第一接地过孔2131a与第三接地过孔2131b之间的间距S2为0.2mm。四组信号过孔组212沿X方向和Y方向呈矩形阵列布置，且沿X方向相邻第一接地过孔2131a与第三接地过孔2131b共用。
如图11所示，以横坐标表示信号传输的频率(单位GHz)，以纵坐标表示串扰噪声(单位dB)。则四组信号过孔组212之间的串扰噪声随信号传输频率变化的曲线关系由图可知，电路板封装结构210能够实现信号传输的频率达到80GHz，同时，信号的远端串扰能够满足-40dB的要求。如图12所示，电路板封装结构210能够实现信号传输的频率达到80GHz，同时，信号的近端串扰能够满足-40dB的要求。
需要说明的是，本申请实施例并不对电路板211上信号过孔组212的组数做特殊的限制，每组信号过孔组212的外周均围绕有第一接地过孔组2131与第二接地过孔组2132。每组第一接地过孔组2131与第二接地过孔组2132交替排列，相邻两个信号过孔组212之间也可以是第二接地过孔组2132共用。
此外，若每组信号过孔组212中两个第二接地过孔2132a孔壁之间的开口距离S1为2mm，相邻第二接地过孔2132a之间、第一接地过孔2131a与第二接地过孔2132a之间、第一接地过孔2131a与第三接地过孔2131b之间的间距S2为0.6mm。则电路板封装结构210能够实现信号传输的频率达到50GHz，同时，信号的远端串扰和近端串扰均能够满足-40dB的要求。
示例二：
与示例一的不同之处在于，如图13A所示，屏蔽结构213可以设计为屏蔽槽215 的结构形式。具体的，可以在电路板211上开设屏蔽槽215。同样，如图13B所示，屏蔽槽215贯穿电路板211的深度大于或等于信号过孔组212的深度，且屏蔽槽215围绕在信号过孔组212的外周。屏蔽槽215可以与接地层2112电连接，接地层2112可以在信号过孔2121贯穿的位置开设反焊盘，信号走线2111可以绕开屏蔽槽215贯穿的位置，以避免造成短路。
在此基础上，如图13A所示，屏蔽槽215的水平截面可以设计为具有开口2130的C形，水平截面与电路板211的板面平行。引线214可以穿过C形的屏蔽槽215的开口2130。其中，如图14所示，引线214两侧的屏蔽槽215的开口2130尺寸S1可以设置为0.6-2mm。当然，屏蔽槽215也可以设计为U形或者圆环形的形状，本申请实施例并不对屏蔽槽215的具体结构形式做特殊的限制。
具体的，如图15所示，屏蔽结构213可以包括绝缘挡墙2133和金属覆盖层2134。绝缘挡墙2133可以选用树脂或者玻璃纤维等材质制成，并填充于屏蔽槽215内，且围绕信号过孔组212的外周设置。金属覆盖层2134位于绝缘挡墙2133和屏蔽槽215的槽壁之间，金属覆盖层2134可以选用镀铜等方式进行加工制造，且金属覆盖层2134与绝缘挡墙2133和屏蔽槽215相连接。金属覆盖层2134还与接地层2112(图13B所示)和电子元件220的管脚(pin)电连接。
在一些实施方式中，如图15所示，绝缘挡墙2133上可以开设连接孔2135，用于连接电子元件220(图1所示)。具体的，连接孔2135可以贯穿绝缘挡墙2133的至少一部分，且连接孔2135的侧壁露出金属覆盖层2134的一部分，用于与电子元件220电连接。沿绝缘挡墙2133的长度方向，连接孔2135可以间隔设置。
当电子元件220为连接器时，连接器公端220a的第一接地管脚222a可以与第一电路板封装结构210a的连接孔2135插接，且与金属覆盖层2134电连接；连接器母端220b的第二接地管脚222b可以与第二电路板封装结构210b的连接孔2135插接，且与金属覆盖层2134电连接。
当电子元件220为芯片时，此时可以无需开设连接孔2135。仅需在绝缘挡墙2133的顶部设置焊盘，使焊盘与金属覆盖层2134电连接即可。芯片的接地焊球222可以与电路板封装结构210的焊盘电连接。
根据电路板211的阻抗设计以及电子元件220管脚的布置，本申请实施例并不对屏蔽槽215和屏蔽结构213的设置宽度做特殊的限制。
示例的，如图16所示，同样以四组信号过孔组212为例进行说明。每组信号过孔组212的外周均围绕有屏蔽槽215和屏蔽结构213。四组信号过孔组212同样沿X方向和Y方向呈矩形阵列布置，且沿X方向相邻两个信号过孔组212之间的屏蔽槽215连通，且相邻两个信号过孔组212之间的屏蔽结构213共用。
当引线214两侧的屏蔽槽215的开口尺寸S1设置为0.6mm时，电路板封装结构210同样能够实现信号传输的频率达到80GHz，同时，信号的远端串扰和近端串扰均能够满足-40dB的要求。当引线214两侧的屏蔽槽215的开口尺寸S1设置为2mm时，电路板封装结构210同样能够实现信号传输的频率达到50GHz，同时，信号的远端串扰和近端串扰均能够满足-40dB的要求。
需要说明的是，本申请实施例提供的电路板封装结构210，并不局限于在信号过 孔组212的外周布置过孔式的屏蔽结构213或者屏蔽槽215式的屏蔽结构213。根据电路板的封装结构设计以及电子元件220管脚的布置，过孔式的屏蔽结构213与屏蔽槽215式的屏蔽结构213也可以相互结合布置在电路板211上。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种电路板封装结构，其特征在于，包括：
    电路板，包括基板本体以及设置于所述基板本体内的信号走线和接地层；
    至少一个信号过孔组，所述信号过孔组包括至少一个信号过孔，所述信号过孔贯穿所述基板本体的至少一部分；所述信号过孔与所述信号走线电连接；以及，
    屏蔽结构，贯穿所述基板本体的至少一部分，所述屏蔽结构围绕所述信号过孔组的外周设置，且与所述接地层电连接。
  2. 根据权利要求1所述的电路板封装结构，其特征在于，所述电路板封装结构与电子元件电连接，所述电子元件具有接地管脚；
    所述屏蔽结构包括：
    至少两个第一接地过孔组和至少两个第二接地过孔组，所述第一接地过孔组与所述第二接地过孔组交替排列，且围绕所述信号过孔组的外周设置；
    其中，每组所述第一接地过孔组包括至少一个第一接地过孔，所述第一接地过孔与所述电子元件的接地管脚电连接，且与所述接地层电连接；
    每组所述第二接地过孔组包括至少一个第二接地过孔，所述第二接地过孔与所述接地层电连接。
  3. 根据权利要求2所述的电路板封装结构，其特征在于，每组所述第一接地过孔组包括至少两个所述第一接地过孔；
    所述第一接地过孔组还包括第三接地过孔，所述第三接地过孔位于相邻两个所述第一接地过孔之间，所述第三接地过孔与所述接地层电连接。
  4. 根据权利要求2或3所述的电路板封装结构，其特征在于，所述电路板还包括引线，所述引线的一端与所述信号过孔电连接，另一端与所述信号走线电连接；
    每组所述第二接地过孔组包括至少两个所述第二接地过孔，所述引线穿过相邻两个所述第二接地过孔之间的间隙。
  5. 根据权利要求4所述的电路板封装结构，其特征在于，所述引线两侧相邻两个所述第二接地过孔之间的间隙为0.6-2mm。
  6. 根据权利要求4所述的电路板封装结构，其特征在于，相邻所述第一接地过孔之间、相邻所述第二接地过孔之间、所述第一接地过孔与所述第二接地过孔之间、所述第一接地过孔与所述第三接地过孔之间的间距为0.2-0.6mm。
  7. 根据权利要求2所述的电路板封装结构，其特征在于，所述电路板封装结构包括至少两个所述信号过孔组；
    相邻两个所述信号过孔组之间的所述第一接地过孔组共用；或者，
    相邻两个所述信号过孔组之间的所述第二接地过孔组共用。
  8. 根据权利要求1所述的电路板封装结构，其特征在于，所述电路板封装结构与电子元件电连接，所述电子元件具有接地管脚；
    所述基板本体开设有屏蔽槽，所述屏蔽槽贯穿所述基板本体的至少一部分，且所述屏蔽槽围绕所述信号过孔组的外周设置；
    所述屏蔽结构包括：
    绝缘挡墙，填充于所述屏蔽槽内，且围绕所述信号过孔组的外周设置；以及，
    金属覆盖层，位于所述绝缘挡墙和所述屏蔽槽的槽壁之间，且与所述绝缘挡墙和所述屏蔽槽相连接；所述金属覆盖层与所述接地层和所述电子元件的接地管脚电连接。
  9. 根据权利要求8所述的电路板封装结构，其特征在于，所述绝缘挡墙开设有连接孔；
    所述连接孔贯穿所述绝缘挡墙的至少一部分，且所述连接孔的侧壁露出所述金属覆盖层的一部分；
    所述电子元件的接地管脚设置于所述连接孔内，且通过所述连接孔的侧壁与所述金属覆盖层电连接。
  10. 根据权利要求8所述的电路板封装结构，其特征在于，所述电路板还包括引线，所述引线的一端与所述信号过孔电连接，另一端与所述信号走线电连接；
    所述屏蔽槽的水平截面为C形，所述引线穿过所述C形的所述屏蔽槽的开口；其中，所述水平截面与所述电路板的板面平行。
  11. 根据权利要求10所述的电路板封装结构，其特征在于，所述C形的所述屏蔽槽的开口尺寸为0.6-2mm。
  12. 根据权利要求8所述的电路板封装结构，其特征在于，所述电路板封装结构包括至少两个所述信号过孔组；
    相邻两个所述信号过孔组之间的所述屏蔽槽连通，且相邻两个所述信号过孔组之间的所述屏蔽结构共用。
  13. 根据权利要求1-12中任一项所述的电路板封装结构，其特征在于，所述至少一个信号过孔组包括一对差分对过孔。
  14. 一种电路板组件，其特征在于，包括：
    电子元件，具有信号管脚与接地管脚；以及，
    如权利要求1-13中任一项所述的电路板封装结构，所述信号管脚与所述电路板封装结构的所述信号过孔电连接，所述接地管脚与所述电路板封装结构的所述屏蔽结构电连接。
  15. 根据权利要求14所述的电路板组件，其特征在于，所述电子元件为连接器，所述连接器包括：
    公端，具有第一信号管脚与第一接地管脚；以及，
    母端，具有第二信号管脚与第二接地管脚；
    所述电路板封装结构包括第一电路板封装结构和第二电路板封装结构：
    其中，所述第一信号管脚与所述第一电路板封装结构的所述信号过孔插接，所述第一接地管脚与所述第一电路板封装结构的所述屏蔽结构插接；所述第二信号管脚与所述第二电路板封装结构的所述信号过孔插接，所述第二接地管脚与所述第二电路板封装结构的所述屏蔽结构插接。
  16. 根据权利要求14所述的电路板组件，其特征在于，所述电子元件为芯片，所述芯片具有信号焊球与接地焊球；
    所述信号焊球与所述电路板封装结构的所述信号过孔电连接，所述接地焊球与所述电路板封装结构的所述屏蔽结构电连接。
  17. 一种电子设备，其特征在于，包括：
    壳体；以及，
    如权利要求14-16中任一项所述的电路板组件，设置于所述壳体内。
PCT/CN2022/129632 2021-11-10 2022-11-03 一种电路板封装结构、电路板组件以及电子设备 WO2023083095A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307273A (ja) * 1996-05-14 1997-11-28 Matsushita Electric Ind Co Ltd シールド構造を備えた高周波回路
WO2016115742A1 (zh) * 2015-01-24 2016-07-28 深圳市鑫龙上通讯科技有限公司 Pcb线路板及移动通信设备
CN107041062A (zh) * 2015-12-30 2017-08-11 泰科电子公司 配置用于四元信号传输的印刷电路和电路板组件
CN113573463A (zh) * 2021-06-08 2021-10-29 华为技术有限公司 电路板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869898A (en) * 1997-04-25 1999-02-09 Nec Corporation Lead-frame having interdigitated signal and ground leads with high frequency leads positioned adjacent a corner and shielded by ground leads on either side thereof
JP2003249559A (ja) * 2002-02-22 2003-09-05 Handotai Rikougaku Kenkyu Center:Kk 多層配線装置および配線方法並びに配線特性解析・予測方法
US9087846B2 (en) * 2013-03-13 2015-07-21 Apple Inc. Systems and methods for high-speed, low-profile memory packages and pinout designs
US20160020177A1 (en) * 2014-06-13 2016-01-21 Ubotic Company Limited Radio frequency shielding cavity package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307273A (ja) * 1996-05-14 1997-11-28 Matsushita Electric Ind Co Ltd シールド構造を備えた高周波回路
WO2016115742A1 (zh) * 2015-01-24 2016-07-28 深圳市鑫龙上通讯科技有限公司 Pcb线路板及移动通信设备
CN107041062A (zh) * 2015-12-30 2017-08-11 泰科电子公司 配置用于四元信号传输的印刷电路和电路板组件
CN113573463A (zh) * 2021-06-08 2021-10-29 华为技术有限公司 电路板

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