WO2023065431A1 - 一种半导体器件的制造方法 - Google Patents

一种半导体器件的制造方法 Download PDF

Info

Publication number
WO2023065431A1
WO2023065431A1 PCT/CN2021/130253 CN2021130253W WO2023065431A1 WO 2023065431 A1 WO2023065431 A1 WO 2023065431A1 CN 2021130253 W CN2021130253 W CN 2021130253W WO 2023065431 A1 WO2023065431 A1 WO 2023065431A1
Authority
WO
WIPO (PCT)
Prior art keywords
film layer
extracted
mask
photoresist
layer
Prior art date
Application number
PCT/CN2021/130253
Other languages
English (en)
French (fr)
Inventor
张利斌
韦亚一
宋桢
粟雅娟
何建芳
马乐
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US17/630,674 priority Critical patent/US20240055254A1/en
Publication of WO2023065431A1 publication Critical patent/WO2023065431A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Definitions

  • the present application relates to the field of semiconductor devices, in particular to a method for manufacturing a semiconductor device.
  • the self-alignment process is an important technical means to achieve alignment between different layers. At present, the self-alignment process is often used to achieve the alignment between the metal layer and the interconnection layer.
  • the error of the self-alignment process is relatively large, resulting in a low yield of the manufactured semiconductor device.
  • the purpose of the present application is to provide a method for manufacturing a semiconductor device, so as to improve the alignment accuracy between different layers and reduce alignment errors.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a substrate and a structure to be extracted on one side of the substrate, and the method includes:
  • a photoresist coating is formed on the structure to be extracted, and the photoresist coating includes a first film layer, a photoresist film layer and a second film layer stacked in sequence, the first film layer and the second film layer
  • the refractive index of the layer is less than 1;
  • the photoresist coating is exposed to the light of the target wavelength and the mask, so that the image of the structure to be extracted and the pattern of the mask are jointly imaged to the target area of the photoresist film layer; the target area Corresponding to the structure to be extracted.
  • the thickness of the photoresist coating is based on the light intensity in the photoresist film layer when the structure to be extracted is imaged to the photoresist film layer by the light of the target wavelength and the photoresist film layer when the pattern of the mask is imaged to the photoresist film layer.
  • the light intensities in the layers are jointly determined.
  • the method before forming a photoresist coating on the structure to be extracted, the method further includes:
  • the method further includes:
  • the dielectric layer corresponding to the target area is etched by using the photoresist film layer to obtain a contact hole penetrating through the dielectric layer, and the contact hole exposes the structure to be led out.
  • the method before using the photoresist film layer to etch the dielectric layer corresponding to the target region, the method further includes:
  • the method further includes:
  • Metal is filled in the contact hole to form a metal contact, and the metal contact is connected with the structure to be led out.
  • the material of the photoresist film layer is photoresist
  • the materials of the first film layer and the second film layer are metal materials.
  • the light of the target wavelength is red light or ultraviolet light.
  • the structure to be extracted is at least one of a gate structure, a source structure and a drain structure.
  • the feature size of the pattern of the mask varies from 100% to 160%.
  • the offset range of the center position of the pattern of the mask is -20%-20%.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device.
  • the semiconductor device includes a substrate and a structure to be extracted located on one side of the substrate.
  • a photolithographic coating is formed on the structure to be extracted.
  • the photolithographic coating includes sequentially stacked first A layer, a photoresist layer, and a second layer, wherein both the first layer and the second layer have a refractive index less than 1, so that the photoresist coating forms an optical structure with a high reflectance, and then utilizes the target wavelength
  • the photoresist coating is exposed to light and a mask. At this time, the structure to be extracted is reflected by the photoresist coating.
  • the structure to be extracted is used as a mask to image the photoresist film layer, and the pattern of the mask is also imaged to the photoresist layer.
  • the etched film layer, that is, the pattern of the structure to be extracted and the mask are all imaged to the target area of the photoresist film layer, and the target area corresponds to the structure to be extracted.
  • the position of the structure to be extracted is imaged on the photoresist layer, and the pattern of the mask is also imaged on the photoresist layer at the same time, the area where both the structure to be extracted and the pattern of the mask are imaged
  • the structure to be drawn that is, the self-alignment of the layer of the structure to be drawn and the layer where the contact hole is located is realized. Therefore, only in the overlapping area where the structure to be drawn and the pattern of the mask are imaged in the photoresist film layer at the same time during the exposure process It will correspond to the structure to be extracted, which can improve the alignment accuracy between different layers and reduce the alignment error.
  • FIG. 1 shows a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • FIG. 2 shows a top view structural view of a semiconductor device provided by an embodiment of the present application
  • FIG. 3 shows a cross-sectional view of the semiconductor device provided in FIG. 2 along the direction AA;
  • Figure 6 shows a schematic diagram of light intensity changes in the photoresist film layer provided by the embodiment of the present application.
  • Figure 7 shows a schematic diagram of light intensity distribution in the photoresist film layer provided by the embodiment of the present application.
  • FIG. 8 shows a schematic top view of a semiconductor device and a mask provided by an embodiment of the present application
  • FIG. 9 shows the correspondence relationship between the feature size and the imaging size of a pattern of a mask provided by an embodiment of the present application.
  • FIG. 10 shows a correspondence diagram between the center position offset and the imaging size of a pattern of a mask provided by an embodiment of the present application
  • 11-13 show schematic structural views of a semiconductor device manufactured by the method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • the self-alignment process is an important technical means to achieve the alignment between different layers, and the self-alignment process is often used to achieve the alignment between the metal layer and the interconnection layer.
  • an embodiment of the present application provides a method for manufacturing a semiconductor device.
  • the semiconductor device includes a substrate and a structure to be extracted located on one side of the substrate.
  • a photolithographic coating is formed on the structure to be extracted.
  • the photolithographic coating It includes a first film layer, a photoresist film layer and a second film layer stacked in sequence, wherein the refractive indices of the first film layer and the second film layer are both less than 1, so that the photoresist coating forms an optical structure with a higher reflectance , and then use the target wavelength of light and a mask to expose the photoresist coating.
  • the structure to be extracted is reflected by the photoresist coating, and the structure to be extracted is used as a mask to image the photoresist film layer.
  • the pattern is also imaged on the photoresist layer, that is, both the structure to be extracted and the pattern of the mask are imaged to the target area of the photoresist layer, and the target area corresponds to the structure to be extracted.
  • the position of the structure to be extracted is imaged on the photoresist layer, and the pattern of the mask is also imaged on the photoresist layer at the same time, the area where both the structure to be extracted and the pattern of the mask are imaged
  • the structure to be drawn that is, the self-alignment of the layer of the structure to be drawn and the layer where the contact hole is located is realized. Therefore, only in the overlapping area where the structure to be drawn and the pattern of the mask are imaged in the photoresist film layer at the same time during the exposure process It will correspond to the structure to be extracted, which can improve the alignment accuracy between different layers and reduce the alignment error.
  • FIG. 1 it is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • the semiconductor device provided in the embodiment of the present application includes a substrate 110 and a structure to be extracted 120 located on one side of the substrate 110.
  • FIG. 2 is a top structural view of the semiconductor device 100 provided by the embodiment of the present application
  • FIG. 3 is a cross-sectional view of the semiconductor device provided in FIG. 2 along the direction AA.
  • the structure to be extracted 120 may be at least one of a gate structure, a source structure and a drain structure.
  • the material of the structure to be extracted 120 may be a metal material with better conductivity.
  • the structure to be extracted may be the structure of the layer to be aligned.
  • the substrate 110 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator). Insulator) and so on.
  • the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as quartz, GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc.
  • the substrate 110 is a silicon substrate.
  • film layers may be formed between the substrate 110 and the structure 120 to be extracted, so as to form various semiconductor devices.
  • the semiconductor device may be a three-dimensional memory device.
  • a doped layer or other dielectric film layer is formed between the substrate 110 and the structure 120 to be extracted, and the semiconductor device at this time may be a logic device, such as a transistor.
  • the method includes the following steps:
  • a photoresist coating 130 is formed on the structure to be extracted 120, and the photoresist coating 130 is patterned to form a metal contact with the patterned photoresist coating 130, and the structure to be extracted 130 for electrical extraction.
  • a dielectric layer 140 is firstly formed on the structure to be extracted 130, that is, the dielectric layer 140 is located between the structure to be extracted 120 and the photoresist coating 130, Refer to Figure 4.
  • the material of the dielectric layer 140 may be a material with better insulation, such as silicon oxide.
  • the dielectric material can be deposited by a deposition process to form the dielectric layer 140.
  • the dielectric layer 140 will conform to the structure 120 to be extracted, so that the shape of the dielectric layer 140 is consistent with that of the structure 120 to be extracted. If the morphology is similar, the dielectric layer 140 can be polished by chemical mechanical polishing equipment to obtain a relatively flat dielectric layer 140 , which is conducive to the subsequent formation of the photolithographic coating 130 on the relatively flat dielectric layer 140 .
  • the photoresist coating 130 includes a first film layer 131, a photoresist film layer 132 and a second film layer 133 stacked in sequence, wherein the refraction of the first film layer 131 and the second film layer 132 rate is less than 1.
  • the photoresist coating 130 is composed of the first film layer 131, the photoresist film layer 132 and the second film layer 133 to form an optical structure similar to a sandwich, and both sides are film layers with a refractive index less than 1.
  • a reflection oscillation is formed in the coating 130 , that is, the intensity of the incident light can be enhanced by using the reflection oscillation.
  • the material of the photoresist film layer 132 is photoresist
  • the materials of the first film layer 131 and the second film layer 133 may be metal materials or metamaterials.
  • Metal materials such as gold, silver or copper have a refractive index less than 1 under the irradiation of deep ultraviolet light, visible light or infrared light.
  • Metamaterials can be a combination of certain compound materials and certain materials. Metamaterials can be artificially synthesized materials. In order to be able to form the effect that the refractive index is less than 1 when irradiated by light at certain wavelengths.
  • the sequentially stacked first film layer 131 , photoresist film layer 132 and second film layer 133 may be formed by using a spin coating process, a deposition process or an ion sputtering process. Then the first film layer 131, the photoresist film layer 132 and the second film layer 133 can be polished by chemical mechanical polishing equipment to further control the flatness of the first film layer 131, the photoresist film layer 132 and the second film layer 133 degree and thickness.
  • the photoresist coating 130 may be exposed by a photolithography process.
  • the target area 132 -1 corresponds to the structure 120 to be exported.
  • the photoresist coating 130 is exposed to the light of the target wavelength.
  • the photoresist coating 130 has a high reflectivity to the light of the target wavelength, and the structure 120 to be extracted under the photoresist coating 130 can be
  • the structure is imaged to the target area 132 - 1 of the photoresist film layer 132 , as shown in FIG. 5 . That is to say, when the photoresist coating 130 is exposed to the light of the target wavelength, the structure to be extracted 120 is equivalent to a mask, and the light of the target wavelength undergoes a photochemical reaction in the target region 132-1 to image the structure to be extracted 120 to Photoresist film layer 132 .
  • the light of the target wavelength can also image the pattern of the mask 150 to the target area 132-1 of the photoresist film layer 132, only the target area 132-1, that is, the structure 120 to be extracted in the photoresist film layer 132 and the mask 150
  • the photochemical reaction will only occur in the overlapping area of the graphic imaging, which can be developed in the subsequent development process.
  • the photoresist film layer 132 can have an optical response to the light of the target wavelength.
  • the photoresist film layer 132 undergoes a photochemical reaction, and at the same time, the position of the structure 120 to be extracted is determined. And determine the position where the contact hole is formed, the target area 132 - 1 is the area where the photochemical reaction occurs, and is the extraction area, and the extraction area corresponds to the structure 120 to be extracted.
  • simulation software can be used to simulate the thicknesses of the first film layer 131, the photoresist film layer 132 and the second film layer 133 in the photoresist coating 130, usually the thickness of the photoresist film layer 132 greater than the thickness of the first film layer 131 and the second film layer 133 .
  • the thickness of the photoresist coating 130 can be based on the light intensity in the photoresist film layer 132 when the structure 120 to be extracted is imaged to the photoresist film layer 132 and the photoresist pattern of the mask 150 is imaged to the photoresist film layer 120 according to the target wavelength.
  • the light intensity in the film layers 120 is jointly determined.
  • the light intensity of the light of the target wavelength that needs to pass through the light-transmitting region of the mask 150 has a larger light intensity in the photoresist film layer 132, and the pattern of the mask 150 can be imaged to the photoresist film layer 132, followed by
  • the light intensity in the imaged region with the structure to be extracted 120 is stronger.
  • the light intensity when the pattern of the mask 150 is imaged to the photoresist film layer 132 is equal to or close to the light intensity when the structure to be extracted 120 is imaged to the photoresist film layer 132, so that the two work together, Determine the target area to be exported.
  • the variation of the thickness of the photoresist coating 130 can affect the variation of the light intensity in the photoresist film layer 132 when the light of the target wavelength is exposed.
  • the thickness of the photoresist coating 130 is fixed, whether there is the structure 120 to be extracted can also affect the change of the light intensity in the photoresist film layer 132 . That is to say, the thickness of the photoresist coating 130 and whether there is the structure 120 to be extracted are factors affecting the light intensity of the photoresist film layer 132 .
  • the control variable method can be used, for example, the first film layer 131 and the first film layer 131 can be fixed.
  • the thickness of the second film layer 133 only changes the thickness of the photoresist film layer 132, obtains the light intensity in the photoresist film layer 132 with the change relation of the photoresist film layer 132 thickness, also can adopt simultaneously to change the first film layer 131, the photoresist film layer 132.
  • the thickness of the photoresisted film layer 132 and the second film layer 133 can be used to obtain the variation relationship of the light intensity in the photoresisted film layer 132 with the thicknesses of the three.
  • FIG. 6 it is a schematic diagram of light intensity changes in the photoresist film layer.
  • the area 100 in the figure represents the area where the structure 120 to be extracted has the maximum light intensity when it is imaged to the photoresist film layer 132, and the area 200 in the figure represents that there is no structure 120.
  • the light intensity of the area where the structure 120 is to be extracted is the largest when it is imaged on the photoresist film layer 132 .
  • the light intensity of the area where the structure to be extracted 120 exists is relatively high when it is imaged on the photoresist film layer 132, so as to improve the exposure and imaging efficiency. efficiency.
  • the thickness range of the photoresist coating layer 130 corresponding to the region 100 in FIG. 6 can be selected.
  • the thickness of the photoresist coating 130 uses the thickness to simulate the light intensity in the photoresist film layer 132, as shown in FIG. 7, the light intensity distribution in the photoresist film layer provided by the embodiment of the present application Schematic diagram, as can be seen from the figure, the area where the structure to be extracted 120 is imaged to the photoresist film layer 132 has a higher light intensity, and the area where the structure to be extracted 120 does not exist has a lower light intensity when imaged to the photoresist film layer 132 , coincides with the effect of determining the thickness of the photoresist coating 130 in FIG. 6 .
  • the light of the target wavelength can not only image the structure to be extracted 120 to the photoresist film layer 132 , but also image the pattern of the mask 150 to the photoresist film layer 132 .
  • the target wavelength of light can be visible light or ultraviolet light, and the visible light can be red light, for example, the target wavelength can be 633 nm, 532 nm, 436 nm, 365 nm, 248 nm or 193 nm.
  • FIG. 8 is a schematic top view of the semiconductor device and the mask provided by the embodiment of the present application.
  • FIG. 7 is a cross-sectional view of FIG. 8 along the BB direction, and the pattern of the mask 150 is The position of exposure is located in the target area 132-1 of the photoresist film layer 132, and the characteristic size of the pattern of the mask 150 can be larger than the characteristic size of the structure to be extracted 120, so that even if the pattern of the mask 150 is consistent with the central point of the structure 120 to be extracted , that is, the center position of the mask 150 is shifted, and it can also ensure that the pattern of the mask 150 and the structure 120 to be extracted have the largest overlapping area, thereby realizing self-alignment.
  • the pattern of the mask can be a hole type, so that the contact hole can be formed later, the mask can be a binary mask or an attenuation-dependent mask, and the mask substrate can be made of quartz or other light-transmitting materials.
  • the material of the opaque area can be a metal material, such as metal chrome.
  • the feature size of the pattern of the mask 150 can be changed, and within a certain range of variation, there is no difference to the final image size of the pattern in the photoresist film layer 132. greater impact.
  • FIG. 9 is a map of the correspondence relationship between the feature size and the imaging size of the pattern of a mask provided by the embodiment of the present application.
  • the variation range of the feature size of the pattern of the mask is 100%. -160%.
  • the imaging size is almost constant, that is, the feature size of the pattern of the mask 150 can be increased by 50%, which shows that even when the mask 150 is manufactured, the mask 150
  • the size error of the graphic will not affect the final imaging size.
  • the influence of alignment errors between different layers can also be reduced by increasing the feature size of the pattern of the mask 150 .
  • the center position of the pattern of the mask 150 when exposing to light of the target wavelength, the center position of the pattern of the mask 150 can be shifted. Size has no major effect.
  • FIG. 10 is a diagram of the correspondence relationship between the center position offset and the imaging size of a mask pattern provided by the embodiment of the present application, it can be seen from the figure that the center position offset range of the mask pattern -20%-20%.
  • the variation of the imaging size is within the range of 5%, which is less than the requirement of 10% variation in the field of integrated circuits.
  • the maximum value of the center position shift of the mask 150 is half of the change of the feature size of the mask 150 .
  • the second film layer 133 can be removed, so that the photoresist film layer 132 can be developed to form a patterned photoresist film layer 160, referring to FIG. As shown in FIG. 11 , after the development process is performed, the photoresist film layer 132 corresponding to the target area 132 - 1 is removed.
  • the dielectric layer 140 corresponding to the target region 132-1 can be etched using the patterned photoresist film layer 160 to obtain a contact hole 170 penetrating through the dielectric layer 140, and the contact hole 170 exposes the structure 120 to be led out.
  • the first film layer 131 is also etched, and after the contact hole 170 penetrating the dielectric layer 140 is obtained, the remaining photoresist film layer 160 and the first film layer can be removed. 131, only the dielectric layer 140 including the contact hole 170 remains.
  • the metal material can be filled in the contact hole 170 to form a metal contact 180, and the metal contact 180 is connected to the structure 120 to be drawn out, that is, the electrical extraction of the structure 120 to be drawn out is formed. , as shown in Figure 13.
  • the photolithography process for forming the metal contact may be an extreme ultraviolet lithography process, a deep ultraviolet lithography process, a nanoimprint process, a super-diffraction lithography process or other processes applying optical imaging.
  • a lens can be used to form parallel light to irradiate the semiconductor device. If the metal surface plasmon superdiffraction lithography is used as the photolithography process, the lens does not need to be used.
  • the region with the structure to be extracted and the region without the structure to be extracted can be imaged to There are different light intensities in the photolithography of the film layer. Using the difference in light intensity, the self-alignment of the two layers is realized. Compared with the two photolithography and etching processes required for self-alignment using the double damascene process, this paper
  • the one-time photolithography process of the application embodiment is more convenient and saves process time.
  • the change of the feature size and center position of the pattern of the mask has little influence on the final imaging size, which can reduce the difficulty of the self-alignment process and improve the precision of forming metal contacts and aligning structures to be extracted.
  • the embodiment of the present application provides a method for manufacturing a semiconductor device.
  • the semiconductor device includes a substrate and a structure to be extracted on one side of the substrate.
  • a photoresist coating is formed on the structure to be extracted.
  • the photoresist coating includes The first film layer, the photoresist film layer and the second film layer stacked in sequence, wherein the refractive index of the first film layer and the second film layer is less than 1, so that the photoresist coating forms an optical structure with a higher reflectance, Then use the light of the target wavelength and the mask to expose the photoresist coating.
  • the structure to be extracted is reflected by the photoresist coating, and the structure to be extracted is used as a mask to image the photoresist film layer, and the pattern of the mask
  • the photoresist layer is also imaged, that is, the structure to be extracted and the pattern of the mask are both imaged to the target area of the photoresist layer, and the target area corresponds to the structure to be extracted.
  • the position of the structure to be extracted is imaged on the photoresist layer, and the pattern of the mask is also imaged on the photoresist layer at the same time, the area where both the structure to be extracted and the pattern of the mask are imaged
  • the structure to be drawn that is, the self-alignment of the layer of the structure to be drawn and the layer where the contact hole is located is realized. Therefore, only in the overlapping area where the structure to be drawn and the pattern of the mask are imaged in the photoresist film layer at the same time during the exposure process It will correspond to the structure to be extracted, which can improve the alignment accuracy between different layers and reduce the alignment error.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

本申请实施例提供了一种半导体器件的制造方法，在待引出结构上形成光刻涂层，光刻涂层包括第一膜层、光刻膜层和第二膜层，第一膜层和第二膜层的折射率都小于1，以便光刻涂层形成一个反射系数较高的光学结构，利用目标波长的光和掩模对光刻涂层进行曝光，待引出结构被光刻涂层进行反射，将待引出结构作为掩模成像至光刻膜层，同时将掩模的图形也成像至光刻膜层，即待引出结构和掩模的图形都成像至光刻膜层的目标区域，目标区域对应待引出结构，实现了待引出结构的图层与接触孔所在图层的自对准，只有在一次曝光过程中待引出结构和掩模的图形同时在光刻膜层成像的重叠区域才会对应待引出结构，能够提高不同的图层之间的对准精度，降低对准误差。

Description

一种半导体器件的制造方法
本申请要求于2021年10月21日提交中国国家知识产权局、申请号为CN202111228709.3、发明名称为“一种半导体器件的制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件领域，特别涉及一种半导体器件的制造方法。
背景技术
在半导体的工艺制造过程中，保证不同的图层之间的对准尤为重要。不同图层之间若是存在较大的对准误差，则可能会导致不同图层之间无法电连接，最终导致制造得到的半导体器件性能下降。自对准工艺是实现不同图层之间对准的重要技术手段，目前经常利用自对准工艺实现金属层和互连层之间的对准。
但是受自对准工艺的限制，在制造半导体器件时，例如形成接触孔的工艺过程中，自对准工艺的误差较大，导致制造得到的半导体器件良率低。
因此，现在急需一种半导体器件的制造方法，能够提高不同的图层之间的对准精度，降低对准误差。
发明内容
有鉴于此，本申请的目的在于提供一种半导体器件的制造方法，以提高不同的图层之间的对准精度，降低对准误差。
为实现上述目的，本申请有如下技术方案：
本申请实施例提供了一种半导体器件的制造方法，其特征在于，所述半导体器件包括衬底以及位于衬底一侧的待引出结构，所述方法包括：
在所述待引出结构上形成光刻涂层，所述光刻涂层包括依次层叠的第一膜层、光刻膜层和第二膜层，所述第一膜层和所述第二膜层的折射率小于1；
利用目标波长的光以及掩模对所述光刻涂层进行曝光，以将所述待引出结构成像和所述掩模的图形共同成像至所述光刻膜层的目标区域；所述目标区域对应所述待引出结构。
可选地，所述光刻涂层的厚度根据目标波长的光将待引出结构成像至光刻膜层时光刻膜层中的光强和将掩模的图形成像至光刻膜层时光刻膜层中的光强共同确定。
可选地，在所述待引出结构上形成光刻涂层之前，所述方法还包括：
在所述待引出结构上形成介质层，所述介质层位于所述待引出结构和所述光刻涂层之间；
在利用目标波长的光以及掩模对所述光刻涂层进行曝光之后，所述方法还包括：
利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀，得到贯穿所述介质层的接触孔，所述接触孔暴露所述待引出结构。
可选地，在利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀之前，所述方法还包括：
去除所述第二膜层。
可选地，在利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀，得到贯穿所述介质层的接触孔之后，所述方法还包括：
在所述接触孔内填充金属，形成金属接触，所述金属接触与所述待引出结构连接。
可选地，所述光刻膜层的材料为光刻胶，所述第一膜层和所述第二膜层的材料为金属材料。
可选地，所述目标波长的光为红光或紫外光。
可选地，所述待引出结构为栅极结构、源极结构和漏极结构中的至少一种。
可选地，所述掩模的图形的特征尺寸变化范围为100％-160％。
可选地，所述掩模的图形的中心位置的偏移范围为-20％-20％。
本申请实施例提供了一种半导体器件的制造方法，半导体器件包括衬底以及位于衬底一侧的待引出结构，在待引出结构上形成光刻涂层，光刻涂层包括依次层叠的第一膜层、光刻膜层和第二膜层，其中第一膜层和第二膜层的折射率都小于1，以便光刻涂层形成一个反射系数较高的光学结构，之后利用目标波长的光和掩模对光刻涂层进行曝光，此时待引出结构被光刻涂层进行反射，将待引出结构作为掩模成像至光刻膜层，同时将掩模的图形也成像至光刻膜层，即待引出结构和掩模的图形都成像至光刻膜层的目标区域，目标区域对应待引出结构。也就是说，经过目标波长的光曝光之后，待引出结构的位置被成像至光刻膜层，掩模的图形也同时成像至光刻膜层，待引出结构和掩模的图形都成像的区域对应待引出结构，即实现了待引出结构的图层与接触孔所在图层的自对准，因此只有在曝光过程中待引出结构和掩模的图形同时在光刻膜层成像的重叠区域才会对应待引出结构，能够提高不同的图层之间的对准精度，降低对准误差。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1示出了本申请实施例提供的一种半导体器件的制造方法的流程图；
图2示出了本申请实施例提供的半导体器件的俯视结构图；
图3示出了图2提供的半导体器件沿AA方向的截面图；
图4-图5示出了本申请实施例提供的半导体器件的制造方法制造的半导体器件的结构示意图；
图6示出了本申请实施例提供的光刻膜层中光强变化示意图；
图7示出了本申请实施例提供的光刻膜层中的光强分布示意图；
图8示出了本申请实施例提供的半导体器件和掩模的俯视示意图；
图9示出了本申请实施例提供的一种掩模的图形的特征尺寸和成像尺寸之间的对应关系图；
图10示出了本申请实施例提供的一种掩模的图形的中心位置偏移和成像尺寸之间的对应关系图；
图11-13示出了本申请实施例提供的半导体器件的制造方法制造的半导体器件的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
其次，本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
目前，自对准工艺是实现不同图层之间对准的重要技术手段，目前经常利用自对准工艺实现金属层和互连层之间的对准。
但是针对半导体器件在形成源极、漏极或栅极之后，为了对源极、漏极或栅极进行引出的接触孔工艺，缺少有效的自对准工艺，能够实现接触孔与源极、漏极或栅极的精准对准。
基于以上技术问题，本申请实施例提供了一种半导体器件的制造方法，半导体器件包括衬底以及位于衬底一侧的待引出结构，在待引出结构上形成光刻涂层，光刻涂层包括依次层叠的第一膜层、光刻膜层和第二膜层，其中第一膜层和第二膜层的折射率都小于1，以便光刻涂层形成一个反射系数较高的光学结构，之后利用目标波长的光和掩模对光刻涂层进行曝光，此时待引出结构被光刻涂层进行反射，将待引出结构作为掩模成像至光刻膜层，同时将掩模的图形也成像至光刻膜层，即待引出结构和掩模的图形都成像至光刻膜层的目标区域，目标区域对应待引出结构。也就是说，经过目标波长的光曝光之后，待引出结构的位置被成像至光刻膜层，掩模的图形也同时成像至光刻膜层，待引出结构和掩模的图形都成像的区域对应待引出结构，即实现了待引出结构的图层与接触孔所在图层的自对准，因此只有在曝光过程中待引出结构和掩模的图形同时在光刻膜层成像的重叠区域才会对应待引出结构，能够提高不同的图层之间的对准精度，降低对准误差。
为了更好地理解本申请的技术方案和技术效果，以下将结合附图对具体的实施例进行详细的描述。
参考图1所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，本申请实施例提供的半导体器件包括衬底110以及位于衬底110一侧的待引出结构120，参考图2 和图3所示，图2为本申请实施例提供的半导体器件100的俯视结构图，图3为图2提供的半导体器件沿AA方向的截面图。在本申请实施例中，待引出结构120可以为栅极结构、源极结构和漏极结构中的至少一种。待引出结构120的材料可以为导电性较好的金属材料。在其他实施例中，待引出结构可以是待对准的图层的结构。
在本申请的实施例中，衬底110为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium On Insulator)等。在其他实施例中，半导体衬底还可以为包括其他元素半导体或化合物半导体的衬底，例如石英、GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以是其他外延结构，例如SGOI(绝缘体上锗硅)等。本实施例中，衬底110为硅衬底。
在实际应用中，衬底110和待引出结构120之间还可以形成有其他膜层，以形成多种半导体器件。
作为一种示例，衬底110和待引出结构120之间形成有堆叠层以及贯穿堆叠层的沟道结构，此时半导体器件可以为三维存储器件。
作为另一种示例，衬底110和待引出结构120之间形成有掺杂层或其他介质膜层，此时半导体器件可以为逻辑器件，例如晶体管。
该方法包括以下步骤：
S101，在所述待引出结构120上形成光刻涂层130，参考图4所示。
在本申请的实施例中，在待引出结构120上形成光刻涂层130，对光刻涂层130进行图案化，以利用图案化后的光刻涂层130形成金属接触，将待引出结构130进行电引出。
在实际应用中，在待引出结构120上形成光刻涂层130之前，还首先在待引出结构130上形成介质层140，即介质层140位于待引出结构120和光刻涂层130之间，参考图4所示。介质层140的材料可以为绝缘性较好的材料，例如氧化硅。可以利用沉积工艺沉积介质材料形成介质层140，在待引出结构120上沉积介质材料时，形成的介质层140会与待引出结构120共形，使得介质层140的形貌与待引出结构120的形貌相近，此时可以采用化学机械研磨设备对介质层140进行研磨，最终得到平坦度较高的介质层140，有利于后续在较为平坦的介质层上140形成光刻涂层130。
在本申请的实施例中，光刻涂层130包括依次层叠的第一膜层131、光刻膜层132和第二膜层133，其中，第一膜层131和第二膜层132的折射率小于1。光刻涂层130由第一膜层131、光刻膜层132和第二膜层133构成类似三明治的光学结构，两侧皆为折射率小于1的膜层，光线入射之后，能够在光刻涂层130中形成反射震荡，即可以利用该反射震荡，增强入射光线的光强。
其中，光刻膜层132的材料为光刻胶，第一膜层131和第二膜层133的材料可以为金属材料或超材料。金属材料例如金、银或铜在深紫外光、可见光或红外光的照射下折射率小于1，超材料可以是某些化合物材料和某些材料的组合，超材料可以是人工合成的一些材料，以便能够形成在某些波长下的光照射时折射率小于1的效果。
在实际应用中，可以利用旋涂工艺、沉积工艺或离子溅射工艺形成依次层叠的第一膜层131、光刻膜层132和第二膜层133。而后可以利用化学机械研磨设备对第一膜层131、 光刻膜层132和第二膜层133进行研磨，以进一步控制第一膜层131、光刻膜层132和第二膜层133的平坦度和厚度。
S102，利用目标波长的光以及掩模150对所述光刻涂层130进行曝光，参考图5所示。
在本申请的实施例中，在待引出结构120上形成光刻涂层130后，可以利用光刻工艺对光刻涂层130进行曝光。
利用目标波长的光以及掩模150对光刻涂层130进行一次曝光，同时将待引出结构120成像和掩模150的图形共同成像至光刻膜层132的目标区域132-1，目标区域132-1对应待引出结构120。
利用目标波长的光对光刻涂层130进行曝光，在具体进行曝光时，光刻涂层130对目标波长的光的反射率较高，能够将光刻涂层130下的待引出结构120的结构成像至光刻膜层132的目标区域132-1，参考图5所示。也就是说，利用目标波长的光对光刻涂层130进行曝光时，待引出结构120相当于掩模，目标波长的光在目标区域132-1发生光化学反应，以将待引出结构120成像至光刻膜层132。
同时目标波长的光还可以将掩模150的图形成像至光刻膜层132的目标区域132-1，只有目标区域132-1，即光刻膜层132中待引出结构120和掩模150的图形成像的重叠区域，才会发生光化学反应，能够在后续的显影工艺中进行显影。
在本申请的实施例中，光刻膜层132能够对目标波长的光具有光学响应，目标波长的光进行曝光时，光刻膜层132发生光化学反应，同时确定待引出结构120所处的位置和确定接触孔形成的位置，目标区域132-1为发生光化学反应的区域，为引出区域，该引出区域对应待引出结构120。
也就是说，只有曝光在光刻膜层成像的重叠区域才会对应待引出结构，只有引出区域的光刻膜层才会在后续的显影工艺中被显影，其他没有被成像的区域不会被显影。这样就实现了待引出结构的图层与接触孔所在图层的自对准，因此能够提高不同的图层之间的对准精度，降低对准误差。
在本申请的实施例中，可以利用仿真软件对光刻涂层130中的第一膜层131、光刻膜层132和第二膜层133的厚度进行仿真，通常光刻膜层132的厚度大于第一膜层131和第二膜层133的厚度。光刻涂层130的厚度可以根据目标波长的光将待引出结构120成像至光刻膜层132时光刻膜层132中的光强和将掩模150的图形成像至光刻膜层120时光刻膜层120中的光强共同确定。
首先是需要穿过掩模150的透光区域的目标波长的光的光强在光刻膜层132中的光强较大，能够将掩模150的图形成像至光刻膜层132，其次是目标波长的光照射待引出结构120时的反射光线成像至光刻膜层132时，在具有待引出结构120的成像的区域的光强更强。
在本申请的实施例中，掩模150的图形成像至光刻膜层132时的光强和待引出结构120成像至光刻膜层132时的光强相等或接近，以便两者共同作用，确定待引出的目标区域。
在本申请的实施例中，光刻涂层130厚度的变化能够影响目标波长的光进行曝光时，在光刻膜层132中的光强变化。在光刻涂层130厚度固定时，是否存在待引出结构120， 也能够影响光刻膜层132中的光强变化。也就是说，光刻涂层130的厚度以及是否存在待引出结构120都为影响光刻膜层132的光强的影响因素。
在利用仿真软件对光刻涂层130中的第一膜层131、光刻膜层132和第二膜层133的厚度进行仿真时，可以采用控制变量法，例如可以固定第一膜层131和第二膜层133的厚度，只改变光刻膜层132的厚度，得到光刻膜层132中光强随光刻膜层132厚度的变化关系，也可以采用同时改变第一膜层131、光刻膜层132和第二膜层133的厚度的方式，得到光刻膜层132中光强随三者厚度的变化关系。
在进行仿真时，还可以加入是否存在待引出结构120这一影响因素，可以计算存在待引出结构120的区域和不存在待引出结构120的区域在成像至光刻膜层132时的光强，并计算得到光强差，利用该光强差优化光刻涂层130的厚度。
参考图6所示，为光刻膜层中光强变化示意图，图中区域100代表存在待引出结构120的区域在成像至光刻膜层132时的光强最大，图中区域200代表不存在待引出结构120的区域在成像至光刻膜层132时的光强最大。在本申请的实施例中，由于后续需要在待引出结构120的上方形成接触孔，因此存在待引出结构120的区域在成像至光刻膜层132时的光强较大，以便提高曝光成像的效率。也就是说，为了保证存在待引出结构120的区域在成像至光刻膜层132时的光强较大，可以选择图6中区域100对应的光刻涂层130的厚度范围。
在确定了光刻涂层130的厚度之后，利用该厚度对光刻膜层132中的光强进行仿真，参考图7所示，为本申请实施例提供的光刻膜层中的光强分布示意图，由图可知，存在待引出结构120的区域在成像至光刻膜层132时的光强较大，不存在待引出结构120的区域在成像至光刻膜层132时的光强较小，与图6中确定光刻涂层130的厚度的效果相吻合。
在本申请的实施例中，目标波长的光不仅能够将待引出结构120成像至光刻膜层132，还能够将掩模150的图形成像至光刻膜层132即可。例如目标波长的光可以为可见光或紫外光，可见光例如可以为红光，例如目标波长可以为633纳米、532纳米、436纳米、365纳米、248纳米或193纳米。
在本申请的实施例中，参考8所示，图8为本申请实施例提供的半导体器件和掩模的俯视示意图，图7为图8沿着BB方向的截面图，掩模150的图形被曝光的位置位于光刻膜层132的目标区域132-1，并且掩模150的图形的特征尺寸可以大于待引出结构120的特征尺寸，这样即使掩模150的图形与待引出结构120的中心点，即掩模150的中心位置出现偏移，也能够保证掩模150的图形与待引出结构120具有最大的重叠面积，实现自对准。
如图8所示，掩模的图形可以为孔型，以便后续形成接触孔，掩模可以为二元掩模或衰减相依掩模，掩模基底可以采用石英或其他透光材料，掩模中的不透光区域的材料可以是金属材料，例如金属铬。
在本申请的实施例中，在进行目标波长的光的曝光时，掩模150的图形的特征尺寸可以进行变化，在一定变化范围内，对最终成像至光刻膜层132中的图形尺寸没有较大影响。
参考图9所示，为本申请实施例提供的一种掩模的图形的特征尺寸和成像尺寸之间的对应关系图，由图可以看出，掩模的图形的特征尺寸变化范围为100％-160％。当掩模150 的图形的特征尺寸增大50％时，成像尺寸几乎不变，也就是说，掩模150的图形的特征尺寸可以增加50％，说明即使在制造掩模150时，掩模150的图形出现大小误差，也不会影响最终的成像尺寸。在实际应用过程中，也可以通过增大掩模150的图形的特征尺寸来降低不同的图层之间的对准误差的影响。
在本申请的实施例中，在进行目标波长的光的曝光时，掩模150的图形的中心位置可以进行偏移，在一定偏移范围内，对最终成像至光刻膜层132中的图形尺寸没有较大影响。
参考图10所示，为本申请实施例提供的一种掩模的图形的中心位置偏移和成像尺寸之间的对应关系图，由图可以看出，掩模的图形的中心位置偏移范围为-20％-20％。当掩模150的图形的中心位置在水平方向上变化20％的距离时，成像尺寸的变化在5％的范围内，小于集成电路领域对尺寸变化10％的要求。
当掩模150的图形的特征尺寸和中心位置都变化时，掩模150的中心位置偏移的最大值为掩模150的特征尺寸变化的一半。
在本申请的实施例中，在对光刻涂层130进行曝光之后，可以去除第二膜层133，以便将光刻膜层132进行显影工艺，形成图案化的光刻膜层160，参考图11所示，进行显影工艺后，目标区域132-1对应的光刻膜层132被去除。
之后可以利用图案化的光刻膜层160，对目标区域132-1对应的介质层140进行刻蚀，得到贯穿介质层140的接触孔170，接触孔170暴露待引出结构120，参考图12所示。在利用图案化的光刻膜层160进行刻蚀时，也刻蚀第一膜层131，在得到贯穿介质层140的接触孔170之后，可以去除剩余的光刻膜层160和第一膜层131，只保留包括接触孔170的介质层140即可。
在对应待引出结构120的位置上形成接触孔170之后，就可以在接触孔170内填充金属材料，形成金属接触180，金属接触180与待引出结构120连接，即形成待引出结构120的电引出，参考图13所示。
在本申请的实施例中，形成金属接触的光刻工艺可以是极紫外光刻工艺、深紫外光刻工艺、纳米压印工艺、超衍射光刻工艺或其他应用光学成像的工艺。在利用光刻工艺进行曝光时，可以采用透镜形成平行光照射半导体器件，若采用金属表面等离子体超衍射光刻作为光刻工艺，可以不采用透镜。
由此可见，本申请实施例中提供的半导体器件的制造方法，利用一次曝光工艺，通过调整光刻涂层的厚度就能使得存在待引出结构的区域和不存在待引出结构的区域在成像至光刻膜层时具有不同的光强，利用该光强差，实现两个图层的自对准，相较于利用双大马士革工艺进行自对准需要的两次光刻和刻蚀工艺，本申请实施例的一次光刻工艺更为方便和节省工艺时间。并且本申请实施例中掩模的图形的特征尺寸和中心位置的变化对最终的成像尺寸影响较小，能够降低自对准的工艺难度，提高形成金属接触和待引出结构对准的精度。
由此可见，本申请实施例提供了一种半导体器件的制造方法，半导体器件包括衬底以及位于衬底一侧的待引出结构，在待引出结构上形成光刻涂层，光刻涂层包括依次层叠的第一膜层、光刻膜层和第二膜层，其中第一膜层和第二膜层的折射率都小于1，以便光刻 涂层形成一个反射系数较高的光学结构，之后利用目标波长的光和掩模对光刻涂层进行曝光，此时待引出结构被光刻涂层进行反射，将待引出结构作为掩模成像至光刻膜层，同时将掩模的图形也成像至光刻膜层，即待引出结构和掩模的图形都成像至光刻膜层的目标区域，目标区域对应待引出结构。也就是说，经过目标波长的光曝光之后，待引出结构的位置被成像至光刻膜层，掩模的图形也同时成像至光刻膜层，待引出结构和掩模的图形都成像的区域对应待引出结构，即实现了待引出结构的图层与接触孔所在图层的自对准，因此只有在曝光过程中待引出结构和掩模的图形同时在光刻膜层成像的重叠区域才会对应待引出结构，能够提高不同的图层之间的对准精度，降低对准误差。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于装置实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅是本申请的优选实施方式，虽然本申请已以较佳实施例披露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。

Claims (10)

  1. 一种半导体器件的制造方法，其特征在于，所述半导体器件包括衬底以及位于衬底一侧的待引出结构，所述方法包括：
    在所述待引出结构上形成光刻涂层，所述光刻涂层包括依次层叠的第一膜层、光刻膜层和第二膜层，所述第一膜层和所述第二膜层的折射率小于1；
    利用目标波长的光以及掩模对所述光刻涂层进行曝光，以将所述待引出结构成像和所述掩模的图形共同成像至所述光刻膜层的目标区域；所述目标区域对应所述待引出结构。
  2. 根据权利要求1所述的制造方法，其特征在于，所述光刻涂层的厚度根据目标波长的光将待引出结构成像至光刻膜层时光刻膜层中的光强和将掩模的图形成像至光刻膜层时光刻膜层中的光强共同确定。
  3. 根据权利要求1所述的制造方法，其特征在于，在所述待引出结构上形成光刻涂层之前，所述方法还包括：
    在所述待引出结构上形成介质层，所述介质层位于所述待引出结构和所述光刻涂层之间；
    在利用目标波长的光以及掩模对所述光刻涂层进行曝光之后，所述方法还包括：
    利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀，得到贯穿所述介质层的接触孔，所述接触孔暴露所述待引出结构。
  4. 根据权利要求3所述的制造方法，其特征在于，在利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀之前，所述方法还包括：
    去除所述第二膜层。
  5. 根据权利要求3所述的制造方法，其特征在于，在利用所述光刻膜层，对所述目标区域对应的介质层进行刻蚀，得到贯穿所述介质层的接触孔之后，所述方法还包括：
    在所述接触孔内填充金属，形成金属接触，所述金属接触与所述待引出结构连接。
  6. 根据权利要求1-5任意一项所述的制造方法，其特征在于，所述光刻膜层的材料为光刻胶，所述第一膜层和所述第二膜层的材料为金属材料。
  7. 根据权利要求1-5任意一项所述的制造方法，其特征在于，所述目标波长的光为红光或紫外光。
  8. 根据权利要求1-5任意一项所述的制造方法，其特征在于，所述待引出结构为栅极结构、源极结构和漏极结构中的至少一种。
  9. 根据权利要求1-5任意一项所述的制造方法，其特征在于，所述掩模的图形的特征尺寸变化范围为100％-160％。
  10. 根据权利要求1-5任意一项所述的制造方法，其特征在于，所述掩模的图形的中心位置的偏移范围为-20％-20％。
PCT/CN2021/130253 2021-10-21 2021-11-12 一种半导体器件的制造方法 WO2023065431A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/630,674 US20240055254A1 (en) 2021-10-21 2021-11-12 Method for manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111228709.3A CN113990743A (zh) 2021-10-21 2021-10-21 一种半导体器件的制造方法
CN202111228709.3 2021-10-21

Publications (1)

Publication Number Publication Date
WO2023065431A1 true WO2023065431A1 (zh) 2023-04-27

Family

ID=79740060

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/130253 WO2023065431A1 (zh) 2021-10-21 2021-11-12 一种半导体器件的制造方法

Country Status (3)

Country Link
US (1) US20240055254A1 (zh)
CN (1) CN113990743A (zh)
WO (1) WO2023065431A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990742A (zh) * 2021-10-21 2022-01-28 中国科学院微电子研究所 一种半导体器件的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080654A (en) * 1999-08-20 2000-06-27 Advanced Micro Devices, Inc. Simplified method of forming self-aligned vias in a semiconductor device
US20070092810A1 (en) * 2005-10-24 2007-04-26 Shoaib Zaidi Mask-less method of forming aligned semiconductor wafer features
US20080311527A1 (en) * 2007-06-18 2008-12-18 Samsung Electronics Co., Ltd. Method of forming protection layer on photoresist pattern and method of forming fine pattern using the same
CN102636967A (zh) * 2012-04-19 2012-08-15 苏州大学 表面等离子体纳米光刻结构及方法
CN112309963A (zh) * 2019-07-31 2021-02-02 台湾积体电路制造股份有限公司 用于形成自对准互连结构的方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990742A (zh) * 2021-10-21 2022-01-28 中国科学院微电子研究所 一种半导体器件的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080654A (en) * 1999-08-20 2000-06-27 Advanced Micro Devices, Inc. Simplified method of forming self-aligned vias in a semiconductor device
US20070092810A1 (en) * 2005-10-24 2007-04-26 Shoaib Zaidi Mask-less method of forming aligned semiconductor wafer features
US20080311527A1 (en) * 2007-06-18 2008-12-18 Samsung Electronics Co., Ltd. Method of forming protection layer on photoresist pattern and method of forming fine pattern using the same
CN102636967A (zh) * 2012-04-19 2012-08-15 苏州大学 表面等离子体纳米光刻结构及方法
CN112309963A (zh) * 2019-07-31 2021-02-02 台湾积体电路制造股份有限公司 用于形成自对准互连结构的方法

Also Published As

Publication number Publication date
US20240055254A1 (en) 2024-02-15
CN113990743A (zh) 2022-01-28

Similar Documents

Publication Publication Date Title
US5532089A (en) Simplified fabrication methods for rim phase-shift masks
US7560199B2 (en) Polarizing photolithography system
WO2023065431A1 (zh) 一种半导体器件的制造方法
KR100355228B1 (ko) 하프톤 위상반전 마스크 및 그 제조방법
WO2023065432A1 (zh) 一种半导体器件的制造方法
CN116954014A (zh) 光刻胶斜齿图形的制作方法及斜齿光栅的制作方法
JPH02211450A (ja) 位相シフトマスクおよびその製造方法
CN111463171B (zh) 图形结构的制造方法
KR100855851B1 (ko) 반도체 소자 및 그 제조 방법
KR100508093B1 (ko) 위상 반전 마스크 및 그 제조방법
KR20020046040A (ko) 반도체소자의 미세패턴 제조방법
JP4225544B2 (ja) 感光性材料の積層構造および微細パターン形成方法
JP3417470B2 (ja) 薄膜作製方法
KR100669559B1 (ko) 콘택홀용 위상반전마스크
KR100516746B1 (ko) 노광마스크의 제조방법
KR20000045334A (ko) 반도체소자의 제조방법
JPH07159971A (ja) 光学マスクブランクと光学マスクおよびそれらの製造方法
JPH0950114A (ja) ホトマスク及び半導体装置
KR20060045265A (ko) 반도체소자의 미세 패턴 형성방법
KR0172235B1 (ko) 반도체 소자의 미세패턴 제조방법
TWI532120B (zh) 半導體結構與其製法
KR20000003569A (ko) 반도체소자의 제조방법
KR20030050952A (ko) 반도체 제조용 노광 마스크의 제조방법
KR20040080574A (ko) 반도체소자의 제조방법
KR20020057765A (ko) 듀얼다마신 공정용 포토마스크, 그 제조방법 및 그포토마스크를 이용한 듀얼다마신 배선 형성방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17630674

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21961171

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE