WO2023060732A1 - 一种接触插塞的测试结构及其形成方法、测试方法 - Google Patents

一种接触插塞的测试结构及其形成方法、测试方法 Download PDF

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Publication number
WO2023060732A1
WO2023060732A1 PCT/CN2021/136327 CN2021136327W WO2023060732A1 WO 2023060732 A1 WO2023060732 A1 WO 2023060732A1 CN 2021136327 W CN2021136327 W CN 2021136327W WO 2023060732 A1 WO2023060732 A1 WO 2023060732A1
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Prior art keywords
contact plug
substrate
test
gate
contact
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PCT/CN2021/136327
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English (en)
French (fr)
Inventor
龙强
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长鑫存储技术有限公司
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Publication of WO2023060732A1 publication Critical patent/WO2023060732A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
    • G01R31/69—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board of terminals at the end of a cable or a wire harness; of plugs; of sockets, e.g. wall sockets or power sockets in appliances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a test structure of a contact plug, a forming method and a test method thereof.
  • the embodiments of the present disclosure provide a method for measuring a contact plug to solve at least one problem existing in the background art.
  • a test structure of a contact plug including:
  • a substrate a plurality of active regions disposed on the substrate; a plurality of contact plugs disposed on the substrate, at least two contact plugs are formed on the same active region, and the contact The bottom of the plug is electrically connected to the active area; a plurality of connectors, each of which is electrically connected to the contact plug on a different active area, so that the active area, the contact
  • the plug and the connecting member form a series structure; a plurality of dummy gates on the substrate, the dummy gates are at least on one side of the contact plug.
  • a plurality of the dummy gates are arranged in parallel with each other, and at least one of the dummy gates is located between two contact plugs on the same active region, and the dummy gate partially covers the The active region, and the width of the dummy gate is smaller than the width of the active region.
  • a plurality of dummy gates are arranged in parallel with each other, and the dummy gates are located between adjacent active regions, and the width of the dummy gates is smaller than that of the adjacent active regions. width.
  • At least one side wall of the contact plug has a recess, and the side wall of the contact plug is recessed inwardly along the lateral direction at the recess, and the recess is located at the contact plug.
  • One side of the plug facing the adjacent dummy gate.
  • the active region, the contact plug and the connecting member are arranged in a meandering manner to form a serpentine structure.
  • the material of the contact plug is the same as that of the connecting piece.
  • An embodiment of the present disclosure also provides a test structure of a contact plug, including:
  • a substrate a plurality of active regions disposed on the substrate, the active region including two source-drain doped regions and a channel doped region between the two source-drain doped regions;
  • a gate disposed on the doped channel region, the gate, the doped channel region at the bottom of the gate, and doped source and drain regions on both sides of the gate constitute a transistor;
  • a plurality of contact plugs on the substrate, the bottom of the contact plugs are electrically connected to the source-drain doped regions of the transistor; a plurality of connectors, each of which is electrically connected to two adjacent contact plugs on the transistors, so that the active region, the contact plugs, and the connectors form a series structure.
  • At least one side wall of the contact plug has a recess, and the side wall of the contact plug is recessed inwardly along the lateral direction at the recess, and the recess is located at the contact plug. side of the plug facing the adjacent gate.
  • the active region, the contact plug and the connecting member are arranged in a meandering manner to form a serpentine structure.
  • An embodiment of the present disclosure also provides a method for forming a test structure of a contact plug, including:
  • a dielectric layer is formed on it, and the dielectric layer covers the dummy gate; the dielectric layer is etched to form a contact hole, and at least two contact holes are formed on the same active region, and the contact holes are at least located on the dummy gate.
  • One side of the gate deposit conductive material, the conductive material fills the contact hole to form a contact plug, the bottom of the contact plug is electrically connected to the active region, and continues to deposit conductive material to form a covering of the dielectric layer A conductive material covering layer on the surface; patterning the conductive material covering layer to form a plurality of connectors, each of which is electrically connected to the contact plugs respectively located on different active regions, so that the active region , the contact plug and the connector form a series structure.
  • forming a plurality of active regions on the substrate; forming a dummy gate stack on the substrate includes: forming a mask layer on the substrate, etching the mask layer to form an active area opening; doping the substrate exposed from the active area opening to form an active area; after forming the active area, depositing a dummy gate stack.
  • the active region includes a source-drain doped region, and the doping type of the source-drain doped region is either N-type or P-type.
  • An embodiment of the present disclosure also provides a method for forming a test structure of a contact plug, including:
  • the gate constitutes a transistor; a dielectric layer is formed on the substrate, and the dielectric layer covers the gate; the dielectric layer is etched to form a contact hole; a conductive material is deposited, and the conductive material fills the contact hole to form A contact plug, the bottom of the contact plug is electrically connected to the source-drain doped region, and the conductive material is continuously deposited to form a conductive material covering layer covering the surface of the dielectric layer; the conductive material covering layer is patterned to form A plurality of connecting pieces, each of which is electrically connected to the contact plugs on two adjacent transistors,
  • forming a plurality of source-drain doped regions in the substrates on both sides of the gate includes: forming a sidewall structure covering the sidewall of the gate; using the gate and the sidewall structure As a mask, self-aligned ions are implanted into source and drain doping ions to form source and drain doping regions.
  • the channel doped region is doped with the first ion type by ion implantation
  • the source and drain doped region is doped with the second ion type by ion implantation
  • the first and second ion types are N-type Or one of the P type, and the type of the first ion is opposite to that of the second ion.
  • An embodiment of the present disclosure also provides a test method for a contact plug, the test structure in the above solution, the test method includes:
  • two different contact plugs are selected as the input end and the output end respectively; an operating voltage is added to the gate of the transistor connected in series between the two contact plugs, so that the transistor is turned on; at the input end Connect the first test terminal, connect the second test terminal to the output terminal, respectively connect the first test terminal and the second test terminal to a constant current source to form a first loop to obtain the test current; connect the third test terminal to the input terminal, and connect the The output terminal is connected to the fourth test terminal, and the third test terminal and the fourth test terminal are respectively connected to the voltmeter to form a second loop to obtain the test voltage; the test voltage is divided by the test current to obtain the test resistance; the test resistance and The preset ideal resistance range is compared, and if the test resistance is within the ideal resistance range, it is determined that the performance of the contact plug is qualified.
  • An embodiment of the present disclosure provides a contact plug test structure, including: a substrate; a plurality of active regions disposed on the substrate; a plurality of contact plugs disposed on the substrate, the same At least two contact plugs are formed on the active area, and the bottoms of the contact plugs are electrically connected to the active area; a plurality of connectors, each of which is electrically connected to a different active area
  • the contact plugs so that the active region, the contact plugs and the connecting pieces form a series structure; a plurality of dummy gates located on the substrate, the dummy gates are located at least on the side of the contact plug.
  • Figure 1a is a schematic plan view of a contact plug test structure of the related art
  • Figure 1b is a schematic cross-sectional view of a contact plug test structure in the related art
  • Fig. 2a is a schematic plan view of a contact plug test structure provided by an embodiment of the present disclosure
  • Fig. 2b is a schematic cross-sectional view of a contact plug test structure provided by an embodiment of the present disclosure
  • FIG. 3 is a partially enlarged schematic diagram of a contact plug test structure provided by an embodiment of the present disclosure
  • Fig. 4a is a schematic plan view of a contact plug test structure provided by another embodiment of the present disclosure.
  • Fig. 4b is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 5a is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 5b is a schematic cross-sectional view of a contact plug test structure provided by another embodiment of the present disclosure.
  • Fig. 6a is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 6b is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 6c is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 7a is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 7b is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 7c is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 7d is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 8a is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 8b is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 8c is a schematic plan view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • Fig. 8d is a schematic cross-sectional view of a contact plug testing structure provided by another embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method for forming a contact plug test structure provided by an embodiment of the present disclosure.
  • 10a to 10h are schematic diagrams of the device structure during the preparation process of the contact plug test structure provided by the embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a method for forming a contact plug test structure provided by another embodiment of the present disclosure.
  • 12a to 12i are schematic diagrams of the device structure during the preparation process of the contact plug test structure provided by another embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a circuit structure of a contact plug testing structure provided by an embodiment of the present disclosure.
  • the test structure includes: a substrate 101; a connector 103; area 105 ; contact plug 107 .
  • the bottom of the contact plug 107 is coupled to the active region 105, and the top of the contact plug 107 is coupled to the connector 103;
  • the substrate 101 also includes a dielectric layer 109 covering the substrate 101 , the contact plug 107 is formed in the dielectric layer 109 .
  • Adjacent contact plugs are electrically connected through active regions or connectors to form a series structure, and this test structure is generally called a chain contact structure.
  • the head-to-tail connectors of the chain contact structure can respectively couple the test pads for input and output of test signals.
  • the resistance of the entire test structure is obtained from the contact plug resistance, the active area resistance and the connector resistance in series. By applying a test voltage, a test current is obtained. Since the resistance of the upper connection and the active area is much smaller than that of the contact plug, it can be omitted.
  • the total resistance value of the test circuit is obtained from the test voltage and the test current, and the resistance value of a single contact plug can be obtained by dividing the resistance value by the number of contact plugs. Because the surrounding environment of the contact plug in the above-mentioned test structure is quite different from that of the contact plug in the actual integrated circuit application, this will cause the resistance value of the contact plug measured by the above-mentioned test structure to be different from that of the contact plug in the actual application. The resistance value of the plug varies greatly and cannot reflect the real resistance value of the contact plug.
  • an embodiment of the present disclosure provides a test structure of a contact plug
  • accompanying drawing 2a is a schematic plan view of the contact plug test structure provided by an embodiment of the present disclosure
  • accompanying drawing 2b is a section along the dotted line in the accompanying drawing 2a
  • the structure includes: a substrate 101; a plurality of active regions 105 disposed on the substrate; a plurality of contact plugs 107 disposed on the substrate, the same At least two contact plugs are formed on the active area, and the bottom of the contact plug 107 is electrically connected to the active area 105; a plurality of connectors 103, and each of the connectors 103 is electrically connected to a different location.
  • the contact plug 107 on the active region 105 so that the active region 105, the contact plug 107 and the connector 103 form a series structure; a plurality of dummy gates 211 on the substrate , the dummy gate 211 is located at least on one side of the contact plug 107 .
  • the substrate 101 further includes a dielectric layer 109 covering the substrate 101 , and the contact plug 107 is formed in the dielectric layer 109 .
  • test structure is closer to the structure of the actual integrated circuit application, such a test structure can better reflect the process conditions of the contact plug, and the resistance value of the contact plug can be tested more accurately.
  • the substrate may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • the active region can form an N-type doped region by doping n-type dopants such as phosphorus, arsenic, other n-type dopants or combinations thereof; and can form an N-type doped region by doping such as boron, indium, other p-type dopant or a combination of p-type dopants to form a p-type doped region, and in actual operation, the active region 105 includes a source-drain doped region.
  • the material of the connector 103 can be, for example, a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • the bottom of the contact plug 107 is electrically connected to the active region 105 to realize ohmic contact through a metal silicide layer, so as to reduce the series resistance.
  • the metal silicide layer includes silicides of iron, cobalt, nickel, platinum or alloys thereof, such as low-resistivity nickel silicide, platinum silicide, cobalt silicide or alloys thereof.
  • a plurality of dummy gates 211 are arranged in parallel with each other, and at least one of the dummy gates 211 is located on the two dummy gates 211 on the same active region 105. Between the contact plugs 107 , the dummy gate 211 partially covers the active region 105 , and the width W2 of the dummy gate 211 is smaller than the width W1 of the active region 105 .
  • the material of the contact plug 107 and the material of the connecting member 103 may be the same.
  • the contact plug 107 is formed by depositing a conductive material, and then the conductive material is deposited to form a conductive material covering layer covering the surface of the dielectric layer 109, and the conductive material covering layer is patterned. layer, forming a plurality of connectors 103 .
  • the process flow can be simplified, and the contact resistance between the connector and the contact plug can be reduced.
  • At least one side wall of the contact plug 107 has a recess 110, and the side wall of the contact plug 107 is recessed inwardly along the lateral direction at the recess. , and the recessed portion is located on a side of the contact plug facing the adjacent dummy gate. Since the contact plugs in practical applications are in the real integrated circuit environment, some process steps in the integrated circuit manufacturing process will affect the morphology of the contact plugs, such as forming depressions on the side walls of the contact plugs, etc. This affects the resistance value of the contact plug. In the test structure of the contact plug provided by the embodiment of the present disclosure, the dummy gate is usually formed before the contact plug.
  • FIG. 3 is an enlarged schematic view of the structure inside the dotted circle in FIG. 2b. As shown in FIG. The upper surface of the portion between the contact plug 107 and the dummy gate 211 , that is, the height H in FIG. 3 is greater than h. Since the contact plugs in practical applications are in the real integrated circuit environment, some process links in the integrated circuit manufacturing process will affect the surface height of the substrate.
  • the preparation of the gate line will lead to the substrate on both sides of the gate line Problems such as subsidence of the surface occur, which causes the joint surface formed between the bottom end of the contact plug and the substrate in the real environment to be lower than the joint surface between the bottom end of the contact plug and the substrate under ideal conditions, that is, The height of the contact plug in the actual application environment is higher than the ideal situation, which results in a difference between the actual contact plug resistance value and the ideal situation.
  • the preparation process of forming the dummy gate by etching will produce a certain etching effect on the surfaces of the substrates on both sides of the dummy gate, which makes the substrates on both sides of the dummy gate If the top surface of the contact plug is lowered, then the junction surface between the bottom end of the subsequently formed contact plug and the active region is lowered, that is, the height of the contact plug is increased. This makes the contact plugs provided by the embodiments of the present disclosure closer to the contact plugs actually used in integrated circuits, thereby further improving the accuracy of the resistance value measurement of the contact plugs.
  • accompanying drawing 4a is a schematic plan view of a contact plug test structure provided by an embodiment of the present disclosure
  • accompanying drawing 4b is a schematic cross-sectional view along the dotted line in accompanying drawing 4a
  • a plurality of the dummy gates 211 are arranged parallel to each other, and the dummy gates 211 are located in the area between two adjacent columns of the active regions 105 in the array of active regions 105, and the width of the dummy gates is W2 is less than or equal to the distance W3 between two adjacent columns of the active regions.
  • the dummy gate 211 is between two adjacent contact plugs 107 connected in series
  • the connecting member 103 straddles the dummy gate 211 to connect the two contact plugs 107 on both sides of the dummy gate 211 .
  • accompanying drawing 5a is a schematic plan view of a contact plug test structure provided by an embodiment of the present disclosure
  • accompanying drawing 5b is a schematic cross-sectional view along the dotted line in accompanying drawing 5a
  • a plurality of the dummy gates 211 are arranged parallel to each other, and the dummy gates 211 are located in the area between two adjacent rows of the active regions 105 in the active region 105 array, and the dummy gates 211
  • the width W2 is less than or equal to the distance W4 between two adjacent rows of the active regions 105 .
  • the dummy gate is formed in the region between adjacent active regions.
  • the dummy gate pattern can be formed on the substrate first, and then ion implantation is performed on both sides of the dummy gate to form the active region.
  • region on the one hand, the process flow is simplified compared with the scheme of forming dummy gates on the active area, and on the other hand, the process is closer to the process of contact plugs in actual integrated circuit applications.
  • accompanying drawing 6a is a schematic plan view of a contact plug test structure provided by an embodiment of the present disclosure
  • accompanying drawing 6b is a schematic cross-sectional view along the dotted line in accompanying drawing 6a
  • a plurality of dummy gates 211 are arranged in parallel, and the extension direction of the dummy gates 211 is parallel to the arrangement direction of the active regions of each column in the active region array, and both sides of each contact plug 107 are A dummy gate 211 is provided.
  • both sides of the contact plug are adjacent to the dummy gate, which makes the test structure in the embodiment of the present disclosure closer to the real integrated circuit environment, and further improves the accuracy of the resistance value measurement of the contact plug.
  • the active area arrays are arranged vertically in rows and columns.
  • the above arrangement is only an example of one embodiment. It should be understood that various arrangements can be used to implement the present disclosure. , and should not be limited by the specific embodiments described here.
  • Figure 6c is a schematic plan view of a contact plug test structure provided by an embodiment of the present disclosure
  • the row extension direction of the active region 105 array is not perpendicular to the column extension direction
  • the direction in which the dummy gates 211 extend is perpendicular to the row extension direction of the active area array, and forms a certain angle with the column extension direction of the active area array, and the connection between two adjacent dummy gates 211
  • the extending direction of the element 103 can be parallel to the extending direction of the dummy gate, which can further improve the integration degree of the device.
  • the active region 105 , the contact plug 107 and the connecting member 103 are arranged in a meandering manner to form a serpentine structure.
  • the active regions 105 are arranged in an array structure, and two adjacent contact plugs are connected in an L-shaped, U-shaped, M-shaped, S-shaped or W-shaped linear manner through active regions or connectors.
  • this embodiment also provides a test method for a contact plug, the test method includes: selecting two different contact plugs in a series structure as input terminals and output terminals respectively.
  • the input terminal is connected to the first test terminal, the output terminal is connected to the second test terminal, and the first test terminal and the second test terminal are respectively connected to a constant current source to form a first loop to obtain a test current, for example denoted as I.
  • the input terminal is connected to the third test terminal, the output terminal is connected to the fourth test terminal, and the third test terminal and the fourth test terminal are respectively connected to a voltmeter to form a second loop to obtain a test voltage, for example denoted as U.
  • the test resistance is obtained by dividing the test voltage U by the test current I.
  • test resistance is compared with a preset ideal resistance range, and if the test resistance is within the ideal resistance range, it is determined that the performance of the contact plug is qualified. On the contrary, there is an abnormality in the performance of at least one contact plug in the series structure.
  • FIG. 7a is a schematic plan view of the contact plug test structure provided by an embodiment of the present disclosure
  • Figure 7b is a section along the dotted line in Figure 7a
  • the schematic diagram, referring to accompanying drawings 7a-7b, includes: a substrate 101; a plurality of active regions 705 disposed on the substrate, and the active regions 705 include two source-drain doped regions 705-1 and two A channel doped region 705-2 between the source and drain doped regions 705-1; a gate 711 disposed on the channel doped region 705-2, the active region 705 and the gate 711 constitute The transistor 713, that is, the channel doped region 705-2 located at the bottom of the gate 711 and the source-drain doped region 705-1 located on both sides of the gate and the gate 711 form a transistor 713; A plurality of contact plugs 107 on the substrate 101, the bottom of the contact plug 107 is electrically connected to the source-drain doped region 705-1
  • test structure is closest to the structure used in the actual integrated circuit, such a test structure can better reflect the actual process conditions of the contact plug, and the resistance value of the contact plug can be tested more accurately.
  • the substrate 101 may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • the source-drain doped region 705-1 or the channel doped region 705-2 can be doped with n-type dopants such as phosphorus, arsenic, other n-type dopants or a combination thereof to form N-type doped impurity region; and the p-type doped region may be formed by doping p-type dopants such as boron, indium, other p-type dopants or combinations thereof.
  • the doping ion type of the channel doping region 705-2 is opposite to the doping ion type of the source and drain doping region 705-1.
  • the material of the connecting member 103 can be, for example, a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • the electrical connection between the bottom of the contact plug 107 and the source-drain doped region 705-1 can also realize ohmic contact through a metal silicide layer, so as to reduce the series resistance.
  • the metal silicide layer includes silicides of iron, cobalt, nickel, platinum or alloys thereof, such as nickel silicide, platinum silicide, cobalt silicide or alloys thereof with low resistivity.
  • the material of the contact plug 107 is the same as that of the connecting member 103 .
  • the contact plug 107 is formed by depositing a conductive material, and then the conductive material is deposited to form a conductive material covering layer covering the surface of the dielectric layer 109, and the conductive material covering layer is patterned. layer, forming a plurality of connectors 103 .
  • the process flow can be simplified, and the contact resistance between the connector and the contact plug can be reduced.
  • At least one side wall of the contact plug 107 has a recessed portion, and the side wall of the contact plug 107 is recessed inwardly along the lateral direction at the recessed portion, and the recessed portion Located on the side of the contact plug facing the adjacent gate (not shown in FIG. 7b, refer to the recessed structure in FIG. 2b). Since the contact plugs in practical applications are in the real integrated circuit environment, some process steps in the integrated circuit manufacturing process will affect the morphology of the contact plugs, such as forming depressions on the side walls of the contact plugs, etc. This affects the resistance value of the contact plug. In the test structure of the contact plug provided by the embodiment of the present disclosure, the gate is usually formed before the contact plug.
  • the upper surface of at least one portion of the substrate below the gate is higher than the upper surface of a portion between the contact plug and the gate (not shown in FIG. 7 b ). Shown, refer to Figure 3). Since the contact plugs in practical applications are in the real integrated circuit environment, some process links in the integrated circuit manufacturing process will affect the surface height of the substrate, for example, the preparation of the gate line will cause the surface of the substrate to sink, etc.
  • the preparation process of forming the gate by etching will produce a certain etching effect on the substrate surface on both sides of the gate where the source-drain doped region is to be formed.
  • the upper surface of the source-drain doped region on both sides of the gate will be lowered, and the upper surface of the source-drain doped region on both sides of the gate will be lower than the upper surface of the substrate below the gate. Then, the subsequently formed The joint surface between the bottom end of the contact plug and the source-drain doped region is lowered, that is, the height of the contact plug is increased. This makes the contact plug provided by the embodiment of the present disclosure closer to the contact plug actually used in the integrated circuit, thereby improving the accuracy of the resistance value measurement of the contact plug.
  • the active regions 705 are arranged vertically in rows and columns, however, the above-mentioned arrangement is only an example of one embodiment, and it should be understood that various arrangements can be used to implement the present disclosure. , and should not be limited by the specific embodiments described here.
  • the row extending direction of the active region 705 array is not perpendicular to the column extending direction
  • the extending direction of the gate 711 is not perpendicular to the row extending direction of the active region 705 array.
  • the extension direction is vertical and forms a certain angle with the column extension direction of the active region 705 array
  • the extension direction of the connecting member 103 between two adjacent gates 711 is parallel to the extension direction of the gates 711, which can improve device integration.
  • FIG. 8a is a schematic plan view of a contact plug test structure provided by another embodiment of the present disclosure
  • FIG. 8b is a schematic cross-sectional view at the dotted line in FIG. 8a; as shown in FIGS. 8a-8b, the The source region 705 , the contact plug 107 and the connection piece 103 are arranged in a meandering manner to form a serpentine structure.
  • the active region 705 is arranged in an array structure, and two adjacent contact plugs are connected by transistors or connectors in an L-shaped, U-shaped, M-shaped, S-shaped or W-shaped linear arrangement or in a circuitous manner.
  • Form a serpentine series structure In this way, through the serpentine series design, it is possible to improve the arrangement integrity of the test structure and realize the miniaturization of the test structure.
  • FIG. 8c is a schematic plan view of a contact plug test structure provided by another embodiment of the present disclosure
  • FIG. 8d is a schematic cross-sectional view at the dotted line along the row extending direction in FIG. 8c; as shown in FIGS. 8c-8d It includes a plurality of active regions 705, a plurality of contact plugs 107 located on the active regions 705, and a connector 103 electrically connecting the contact plugs; wherein, a plurality of the active regions 705, the contact plugs 107 and the connecting piece 103 are arranged in a meandering manner to form a serpentine structure.
  • a plurality of gates 711 are arranged parallel to each other and extend along the column extension direction, wherein, for two adjacent gates 711, one is located on the active region 705, and the other is located on the substrate between two adjacent active regions 705 superior.
  • the active region 705 includes two doped source and drain regions 705-1 and a channel located between the two doped source and drain regions 705-1 and below the gate 711.
  • the doped region 705 - 2 , the active region 705 and the gate 711 thereon form a transistor 713 .
  • Two contact plugs 107 are disposed on the same source-drain doped region 705 - 1 , and the two contact plugs 107 are located on the same side of the gate 711 .
  • the transistor 713 When measuring the contact plug resistance, no additional voltage is applied to the gate 711, the transistor 713 does not need to be turned on, and the current does not pass through the channel doped region 705-2, but is connected to the same source and drain doped region
  • the two contact plugs on 705-1 are arranged in a serpentine structure in a meandering manner via the source-drain doped regions connected in common with the connecting member to achieve conduction. In this way, the real process manufacturing environment of the transistor is fully characterized, and the actual device environment of the contact plug is restored. At the same time, when measuring the resistance of the contact plug, the transistor does not need to be turned on, thereby avoiding adding and changing the measurement conditions, thereby ingeniously And accurately measure the resistance value of the contact plug.
  • the source-drain doped region 705-1 may further include an LDD region and a Halo region (not shown in the figure).
  • the substrate located on both sides of the gate or the dummy gate can be firstly implanted with large-angle ions, and then the LDD region and the Halo region can be formed by using a small-angle ion implantation process.
  • This embodiment also provides a method for forming a test structure of a contact plug, please refer to accompanying drawing 9 for details, as shown in the figure, the method includes the following steps:
  • Step 901 providing a substrate
  • Step 902 forming a plurality of active regions on the substrate
  • Step 903 forming a dummy gate stack on the substrate
  • Step 904 etching the dummy gate stack to form a plurality of dummy gates
  • Step 905 forming a dielectric layer on the substrate, the dielectric layer covering the dummy gate;
  • Step 906 Etching the dielectric layer to form contact holes, forming at least two contact holes on the same active region, the contact holes being located at least on one side of the dummy gate;
  • Step 907 Deposit conductive material, the conductive material fills the contact hole to form a contact plug, the bottom of the contact plug is electrically connected to the active region, and continues to deposit conductive material to form a conductive layer covering the surface of the dielectric layer. material covering;
  • Step 908 pattern the conductive material cover layer to form a plurality of connecting pieces, each of the connecting pieces is electrically connected to the contact plugs respectively located on different active regions, so that the active region, the contact The plug and the connector form a series structure.
  • 10a to 10h are schematic diagrams of the device structure during the preparation process of the test structure provided by the embodiments of the present disclosure.
  • step 901 is performed, referring to FIG. 10 a , to provide a substrate 101 .
  • the substrate may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • step 902 is performed to form a plurality of active regions 105 on the substrate.
  • a mask layer can be grown on the upper surface of the substrate 101 first, and then the mask layer can be patterned to display the pattern to be ion-implanted on the mask layer to form an opening in the active region. .
  • the mask layer can be patterned by a photolithography process. For example, the mask layer is patterned through steps such as exposure, development, and stripping.
  • the substrate exposed from the active region opening is then doped to form an active region 105 .
  • the active region may be formed by using an ion implantation process.
  • the active region 105 includes a source-drain doped region, and the doping type of the source-drain doped region is either N-type or P-type.
  • the active region can form an N-type doped region by doping an n-type dopant such as phosphorus, arsenic, other n-type dopants or a combination thereof; and can form an N-type doped region by doping such as boron, indium, other p-type dopants or a combination of p-type dopants to form a p-type doped region.
  • an n-type dopant such as phosphorus, arsenic, other n-type dopants or a combination thereof
  • an N-type doped region by doping such as boron, indium, other p-type dopants or a combination of p-type dopants to form a p-type doped region.
  • step 903 is executed, referring to FIG. 10 c , forming a dummy gate stack 1011 on the substrate, and the dummy gate stack 1011 includes a dummy gate electrode layer and a dummy gate dielectric layer.
  • step 904 is executed, referring to FIG. 10 d , etching the dummy gate stack 1011 to form a plurality of dummy gates 211 .
  • a mask layer can be grown on the upper surface of the dummy gate stack, and then the mask layer can be patterned to display the pattern to be etched on the mask layer, which can be processed by a photolithography process.
  • the mask layer is patterned.
  • the mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; and other steps to pattern the mask layer.
  • An etching process is then performed to transfer the pattern from the hard mask layer to the dummy gate stack.
  • the dummy gate may further include a sidewall structure (not shown in the figure) outside the sidewall of the dummy gate, and the sidewall structure covers the sidewall of the dummy gate.
  • a plurality of the dummy gates 211 are arranged parallel to each other, the dummy gates 211 partially cover the active region 105, and the width of the dummy gates 211 is smaller than that of the active region 105. width.
  • the upper surface of the part of at least one active region located below the dummy gate is higher than the part located between the contact plug and the dummy gate This is caused by overetching the substrates on both sides of the dummy gate 211 when etching to form the dummy gate 211, which makes the test structure prepared by the formation method provided in this embodiment more realistic. The structure applied in the integrated circuit, so as to obtain more accurate measurement results.
  • dummy gates can be formed on all active regions to improve accuracy.
  • step 905 is performed to form a dielectric layer 109 on the substrate, and the dielectric layer 109 covers the dummy gate 211 .
  • step 906 is performed to etch the dielectric layer 109 to form a contact hole 1007, at least two contact holes are formed on the same active region, and the contact holes are at least located on one of the dummy gates. side.
  • step 907 is performed to deposit a conductive material, the conductive material fills the contact hole 1007 to form a contact plug 107, the bottom of the contact plug is electrically connected to the active region, and the conductive material is continuously deposited A conductive material covering layer 1003 covering the surface of the dielectric layer is formed.
  • the existence of the dummy gate will often cause a recess to be formed on the side of the contact plug facing the dummy gate.
  • the recessed part is recessed inward along the lateral direction, and the recessed part is located on a side of the contact plug facing the adjacent dummy gate. This enables the structure provided by this embodiment to provide contact plugs that are closer to those used in actual integrated circuits, thereby obtaining more accurate measurement results.
  • step 908 is executed, referring to FIG. 10h, patterning the conductive material covering layer 1003 to form a plurality of connectors 103, each of which is electrically connected to the contact plugs respectively located on different active regions, so that The active region 105 , the contact plug 107 and the connector 103 form a series structure.
  • step 902 may be performed after steps 903 and 904.
  • step 903 may be performed first to form a dummy gate stack on the substrate, and the dummy gate stack includes a dummy gate electrode layer and a dummy gate electrode layer. gate dielectric layer.
  • step 904 is executed to etch the dummy gate stack to form a plurality of dummy gates.
  • step 902 is performed to form a plurality of active regions on the substrate. Specifically, a self-alignment process is adopted, using the formed dummy gate as a mask, and then diffusion or ion implantation is performed on the dummy gate A plurality of active regions are formed in the substrates on both sides of the substrate.
  • a plurality of dummy gates are arranged parallel to each other, and the dummy gates are located between adjacent active regions, and the width of the dummy gates is less than or equal to that of the adjacent dummy gates. The width of the active area.
  • This embodiment also provides a method for forming a test structure of a contact plug, please refer to Figure 11 for details, as shown in the figure, the method includes the following steps:
  • Step 1101 providing a substrate
  • Step 1102 forming a channel doped region on the substrate
  • Step 1103 forming a gate stack on the substrate
  • Step 1104 etching the gate stack to form multiple gates
  • Step 1105 Form a plurality of source-drain doped regions in the substrate on both sides of the gate, consisting of the source-drain doped regions on both sides of the gate and the channel doped region at the bottom of the gate. a source region, the active region and the gate forming a transistor;
  • Step 1106 forming a dielectric layer on the substrate, the dielectric layer covering the gate;
  • Step 1107 Etching the dielectric layer to form a contact hole
  • Step 1108 Deposit a conductive material, the conductive material fills the contact hole to form a contact plug, the bottom of the contact plug is electrically connected to the source-drain doped region, and continues to deposit a conductive material to form a dielectric layer covering the Surface covering of conductive material;
  • Step 1109 pattern the conductive material covering layer to form a plurality of connecting pieces, each of which is electrically connected to the contact plugs on two adjacent transistors, so that the active region, the contact plugs The plug and the connector form a series structure.
  • 12a to 12i are schematic diagrams of the device structure during the preparation process of the test structure provided by the embodiments of the present disclosure.
  • step 1101 is performed, referring to FIG. 12 a , to provide a substrate 101 .
  • the substrate may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • step 1102 is performed, referring to FIG. 12 b , step 1102 is performed to form a channel doped region 705 - 2 on the substrate 101 .
  • a mask layer is formed on the substrate, and the mask layer is patterned to form an opening of the channel doping region, and then the substrate exposed to the opening of the channel doping region is doped by a diffusion or ion implantation process.
  • a channel doped region is formed.
  • the position of the channel doping region in the substrate can be adjusted according to actual needs.
  • step 1103 is performed to form a gate stack 1111 on the substrate, and the gate stack 1111 includes a gate electrode layer and a gate dielectric layer.
  • step 1104 is executed, referring to FIG. 12d , etching the gate stack to form a plurality of gates 711 .
  • a mask layer can be grown on the upper surface of the gate stack first, and then the mask layer can be patterned to display the pattern to be etched on the mask layer, which can be processed by a photolithography process.
  • the mask layer is patterned.
  • the mask layer may be a photoresist mask or a hard mask patterned based on a photolithographic mask; and other steps to pattern the mask layer.
  • An etching process is then performed to transfer the pattern from the hard mask layer to the gate stack.
  • the gate may further include a sidewall structure (not shown in the figure) outside the sidewall of the gate, and the sidewall structure covers the sidewall of the gate.
  • a plurality of gates can be directly formed by using a mask window for forming channel doping regions. Specifically, firstly, a mask layer is formed on the substrate, and the mask layer is patterned to form channel doping regions. region opening, and then doping the substrate exposed to the channel doping region opening by diffusion or ion implantation process to form a channel doping region. Next, the gate stack material is directly deposited using the same mask window used to form the channel doping region 705-2 to form a plurality of gates 711, and finally the mask layer is removed.
  • the mask window used to form the channel doping region 705-2 to form a plurality of gates 711
  • step 1105 is performed to form a plurality of source-drain doped regions 705-1 in the substrate on both sides of the gate 711, and the source-drain doped regions 705-1 located on both sides of the gate 1 and the channel doped region 705-2 at the bottom of the gate constitute the active region 705, and the active region 705 and the gate 711 constitute a transistor 713, that is, the source and drain doped regions 705-2 on both sides of the gate 1.
  • the channel doped region 705 - 2 located at the bottom of the gate and the gate 711 form a transistor 713 .
  • multiple source-drain doped regions are formed in the substrate on both sides of the gate, including:
  • the channel doped region is doped with a first ion type by ion implantation
  • the source-drain doped region is doped with a second ion type by ion implantation
  • the first and second ion types are One of N type or P type, and the type of the first ion is opposite to that of the second ion.
  • the transistor 713 may be a metal oxide semiconductor transistor (MOS), such as a P-type metal oxide semiconductor transistor (PMOS) or an N-type metal oxide semiconductor transistor (NMOS).
  • MOS metal oxide semiconductor transistor
  • PMOS P-type metal oxide semiconductor transistor
  • NMOS N-type metal oxide semiconductor transistor
  • step 1106 is performed to form a dielectric layer 109 on the substrate, and the dielectric layer 109 covers the gate 711 .
  • step 1107 is performed to etch the dielectric layer 109 to form a contact hole 1007 .
  • step 1108 is performed to deposit conductive materials to form contact plugs 107.
  • the bottom of the contact plugs is electrically connected to the source-drain doped region, and the conductive material is continuously deposited to form a layer covering the surface of the dielectric layer.
  • the existence of the gate will often cause a recess to be formed on the side of the contact plug facing the gate, and the side wall of the contact plug is formed in the recess.
  • the portion is recessed inward along the lateral direction, and the recess is located on a side of the contact plug facing the adjacent gate.
  • step 1109 is executed, referring to FIG. 12i , patterning the conductive material covering layer 1003 to form a plurality of connectors 103, each of which is electrically connected to the contact plugs on two adjacent transistors,
  • the transistor 713 , the contact plug 107 and the connection member 103 form a series structure.
  • the transistors and contact plugs in the test structure can be formed in the same formation process as the actual applied transistors and contact plugs in the core region.
  • the steps 1101-1109 in the above method for forming the test structure may be the same steps as the steps for forming the transistor and the contact plug in the core region.
  • this embodiment also provides a test method for a contact plug, which is suitable for the test structure corresponding to Figure 7a, 7c and Figure 8a, see Figure 13, the test method includes:
  • two different contact plugs are selected as the input terminal 1305 and the output terminal 1306 respectively.
  • An operating voltage is applied to the gate of the transistor connected in series between the two contact plugs, so that the transistor is turned on.
  • the input terminal is connected to the first test terminal 1301, the output terminal is connected to the second test terminal 1302, and the first test terminal 1301 and the second test terminal 1302 are respectively connected to the constant current source 1307 to form a first loop to obtain the test current, for example record for I.
  • the input terminal is connected to the third test terminal 1303, the output terminal is connected to the fourth test terminal 1304, and the third test terminal and the fourth test terminal are respectively connected to a voltmeter 1308 to form a second loop to obtain a test voltage, for example denoted as U.
  • the test resistance is obtained by dividing the test voltage U by the test current I.
  • the test resistance is compared with a preset ideal resistance range, and if the test resistance is within the ideal resistance range, it is determined that the performance of the contact plug is qualified. On the contrary, there is an abnormality in the performance of at least one contact plug in the series structure.
  • the conductive path is a series structure formed by the active region, the contact plug, and the connector.
  • the conduction path is realized through the two contact plugs connected to the same source-drain doped region through the commonly connected source-drain doped region, which can completely characterize the manufacturing environment of the transistor, The device environment of the contact plug is restored, and the transistor does not need to be turned on at the same time, thereby avoiding adding and changing measurement conditions, and the resistance value of the contact plug is measured skillfully and accurately.
  • test structure is closer to the structure of the actual integrated circuit application, such a test structure can better reflect the process conditions of the contact plug, and can test the resistance value of the contact plug more accurately.
  • test structure of the contact plug provided by the embodiments of the present disclosure can be applied to any structure including the contact plug, for example, the measurement of the resistance value of the contact plug of the memory peripheral circuit.
  • the technical features in the technical solutions described in each embodiment can be combined arbitrarily under the condition that there is no conflict.
  • An embodiment of the present disclosure provides a contact plug test structure, including: a substrate; a plurality of active regions disposed on the substrate; a plurality of contact plugs disposed on the substrate, the same At least two contact plugs are formed on the active area, and the bottoms of the contact plugs are electrically connected to the active area; a plurality of connectors, each of which is electrically connected to a different active area
  • the contact plugs so that the active region, the contact plugs and the connecting pieces form a series structure; a plurality of dummy gates located on the substrate, the dummy gates are located at least on the side of the contact plug.

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Abstract

一种接触插塞(107)的测试结构，测试结构包括：衬底(101)；设置于衬底(101)上的多个有源区域(105)；设置于衬底(101)上的多个接触插塞(107)，同一有源区域(105)上形成至少两个接触插塞(107)，且接触插塞(107)的底部与有源区域(105)电连接；多个连接件(103)，每一连接件(103)电连接分别位于不同有源区域(105)上的接触插塞(107)，使得有源区域(105)、接触插塞(107)和连接件(103)形成串联结构；位于衬底(101)上的多个伪栅极(211)，伪栅极(211)至少位于接触插塞(107)的一侧。测试结构与实际集成电路应用的结构接近，能够反映接触插塞(107)的工艺情况，可以较准确地测试出接触插塞(107)的电阻值。

Description

一种接触插塞的测试结构及其形成方法、测试方法
相关申请的交叉引用
本公开基于申请号为202111202890.0、申请日为2021年10月15日、发明名称为“一种接触插塞的测试结构及其形成方法、测试方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种接触插塞的测试结构及其形成方法、测试方法。
背景技术
随着技术的发展，集成电路内包含的晶体管等半导体器件的数目越来越多，为了将半导体器件连接起来，集成电路内一般设置有多个金属层。半导体器件通过导电插塞与金属层连接，各金属层之间则通过通孔连接。其中，互连金属层与衬底中的晶体管等半导体器件之间的导通是通过接触插塞实现的。随着半导体器件特征尺寸不断微缩，运行速度不断提高，接触插塞电阻值的微小变化就会对整个集成电路产生巨大影响。因此，寻求一种能准确反映接触插塞中工艺情况的测试结构是本领域技术人员需要解决的课题。
发明内容
有鉴于此，本公开实施例为解决背景技术中存在的至少一个问题而提供一种接触插塞的测量方法。
为达到上述目的，本公开的技术方案是这样实现的：
根据本公开实施例提供了一种接触插塞的测试结构，包括：
衬底；设置于所述衬底上的多个有源区域；设置于所述衬底上的多个接触插塞，同一所述有源区域上形成至少两个接触插塞，且所述接触插塞的底部与所述有源区域电连接；多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构；位于所述衬底上的多个伪栅极，所述伪栅极至少位于所述接触插塞的一侧。
上述方案中，多个所述伪栅极相互平行排列，且至少一个所述伪栅极 位于同一所述有源区域上的两个所述接触插塞之间，所述伪栅极部分覆盖所述有源区域，且所述伪栅极的宽度小于所述有源区域的宽度。
上述方案中，多个所述伪栅极相互平行排列，且所述伪栅极位于相邻的所述有源区域之间，且所述伪栅极的宽度小于相邻所述有源区域的宽度。
上述方案中，至少一个所述接触插塞的侧壁具有凹陷部，所述接触插塞的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述伪栅极的一侧。
上述方案中，所述有源区域、所述接触插塞和所述连接件以迂回的方式排列成一蛇形结构。
上述方案中，同一接触插塞的两侧存在伪栅极，其中一侧的伪栅极覆盖所述有源区域。
上述方案中，所述接触插塞的材料和所述连接件的材料相同。
本公开实施例还提供了一种接触插塞的测试结构，包括：
衬底；设置于所述衬底上的多个有源区域，所述有源区域包括两个源漏掺杂区和位于两个所述源漏掺杂区之间的沟道掺杂区；设置于所述沟道掺杂区上的栅极，所述栅极、位于所述栅极底部的沟道掺杂区以及位于所述栅极两侧的源漏掺杂区构成晶体管；设置于所述衬底上的多个接触插塞，所述接触插塞的底部与所述晶体管的源漏掺杂区电连接；多个连接件，每一所述连接件电连接相邻两个所述晶体管上的接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
上述方案中，至少一个所述接触插塞的侧壁具有凹陷部，所述接触插塞的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述栅极的一侧。
上述方案中，所述有源区域、所述接触插塞和所述连接件以迂回的方式排列成一蛇形结构。
本公开实施例还提供了一种接触插塞的测试结构的形成方法，包括：
提供衬底；在所述衬底上形成多个有源区域；在所述衬底上形成伪栅极堆叠；刻蚀所述伪栅极堆叠，形成多个伪栅极；在所述衬底上形成介质层，所述介质层覆盖所述伪栅极；刻蚀所述介质层，形成接触孔，同一所述有源区域上形成至少两个接触孔，所述接触孔至少位于所述伪栅极的一侧；沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述有源区域电连接，继续沉积导电材料形成覆盖所述介质层表面的导电材料覆盖层；图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
上述方案中，在所述衬底上形成多个有源区域；在所述衬底上形成伪栅极堆叠，包括：在所述衬底上形成掩膜层，刻蚀所述掩膜层形成有源区域开口；掺杂从所述有源区域开口暴露的所述衬底，形成有源区域；在形 成有源区域之后，沉积伪栅极堆叠。
上述方案中，所述有源区域包括源漏掺杂区，且所述源漏掺杂区的掺杂类型为N型或者P型的一种。
本公开实施例还提供了一种接触插塞的测试结构的形成方法，包括：
提供衬底；在所述衬底上形成沟道掺杂区；在所述衬底上形成栅极堆叠；刻蚀所述栅极堆叠，形成多个栅极；在所述栅极的两侧衬底内形成多个源漏掺杂区，由位于所述栅极两侧的源漏掺杂区和位于栅极底部的沟道掺杂区构成有源区域，所述有源区域和所述栅极构成晶体管；在所述衬底上形成介质层，所述介质层覆盖所述栅极；刻蚀所述介质层，形成接触孔；沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述源漏掺杂区电连接，继续沉积导电材料，形成覆盖所述介质层表面的导电材料覆盖层；图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接相邻两个所述晶体管上的接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
上述方案中，在所述栅极的两侧衬底内形成多个源漏掺杂区，包括：形成覆盖所述栅极侧壁的侧墙结构；以所述栅极与所述侧墙结构为掩膜，自对准离子注入源漏掺杂离子，形成源漏掺杂区。
上述方案中，所述沟道掺杂区通过离子注入掺杂第一离子类型，所述源漏掺杂区通过离子注入掺杂第二离子类型，所述第一、第二离子类型为N型或者P型的一种，且所述第一离子与所述第二离子的类型相反。
本公开实施例还提供了一种接触插塞的测试方法，上述方案中的测试结构，所述测试方法包括：
在串联结构中选择两个不同的接触插塞，分别作为输入端和输出端；将串联在所述两个接触插塞之间的晶体管的栅极加工作电压，使得晶体管导通；在输入端连接第一测试端，在输出端连接第二测试端，第一测试端和第二测试端分别连接恒流源，形成第一回路，以获取测试电流；在输入端连接第三测试端，在输出端连接第四测试端，第三测试端和第四测试端分别连接电压表，形成第二回路，以获取测试电压；由测试电压除以测试电流得出测试电阻；将所述测试电阻与预先设定的理想电阻范围进行比较，若所述测试电阻在所述理想电阻范围内则判定接触插塞的性能合格。
本公开实施例提供了一种接触插塞的测试结构，包括：衬底；设置于所述衬底上的多个有源区域；设置于所述衬底上的多个接触插塞，同一所述有源区域上形成至少两个接触插塞，且所述接触插塞的底部与所述有源区域电连接；多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构；位于所述衬底上的多个伪栅极，所述伪栅极至少位于所述接触插塞的一侧。如此，使得测试结构与实际集成电路应用的结构更加接近，这样的测试结构更加能够反映接触插塞的工艺情况，可以较准确的测试出 接触插塞的电阻值。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1a为相关技术的接触插塞测试结构的平面示意图；
图1b为相关技术的接触插塞测试结构的剖面示意图；
图2a为本公开实施例提供的接触插塞测试结构的平面示意图；
图2b为本公开实施例提供的接触插塞测试结构的剖面示意图；
图3为本公开实施例提供的接触插塞测试结构的的局部放大示意图；
图4a为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图4b为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图5a为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图5b为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图6a为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图6b为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图6c为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图7a为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图7b为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图7c为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图7d为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图8a为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图8b为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图8c为本公开另一实施例提供的接触插塞测试结构的平面示意图；
图8d为本公开另一实施例提供的接触插塞测试结构的剖面示意图；
图9为本公开实施例提供的接触插塞测试结构的形成方法的流程图；
图10a至图10h为本公开实施例提供的接触插塞测试结构在制备过程中的器件结构示意图；
图11为本公开另一实施例提供的接触插塞测试结构的形成方法的流程图；
图12a至图12i为本公开另一实施例提供的接触插塞测试结构在制备过程中的器件结构示意图；
图13为本公开实施例提供的接触插塞测试结构的电路结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实 现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
附图1a是一种接触插塞测试结构的平面示意图，附图1b为沿虚线处的剖面示意图，如附图1a-1b所示，该测试结构包括：衬底101；连接件103；有源区域105；接触插塞107。其中，接触插塞107的底部耦合到有源区域105，接触插塞107的顶部耦合至连接件103；所述衬底101上还包括介质层109，所述介质层109覆盖所述衬底101，所述接触插塞107形成在所述介质层109内。相邻接触插塞通过有源区域或连接件电连接，从而形成串联结构，这种测试结构通称为链接触结构。链接触结构的首尾连接件可分别耦合测试垫，用于测试信号的输入输出。
整个测试结构的电阻由接触插塞电阻、有源区域电阻和连接件电阻串联所得。通过施加测试电压，得到测试电流。由于上层的连接件和有源区域的电阻远小于接触插塞的电阻，因而可以省略。由测试电压与测试电流得到测试电路总阻值，由该阻值除以接触插塞的个数，即可得到单个接触插塞的电阻值。由于上述测试结构中的接触插塞的周围环境与实际集成电路应用中的接触插塞的周围环境相差较大，这会导致上述测试结构测量得到的接触插塞的电阻值与实际应用中的接触插塞的电阻值差异较大，无法反映出接触插塞的真实电阻值。
基于此，本公开实施例提供了一种接触插塞的测试结构，附图2a是本公开实施例提供的接触插塞测试结构的平面示意图，附图2b为沿附图2a中虚线处的剖面示意图，参考附图2a-2b，所述结构包括：衬底101；设置于所述衬底上的多个有源区域105；设置于所述衬底上的多个接触插塞107，同一所述有源区域上形成至少两个接触插塞，且所述接触插塞107的底部与所述有源区域105电连接；多个连接件103，每一所述连接件103电连接分别位于不同有源区域105上的所述接触插塞107，使得所述有源区域105、所述接触插塞107和所述连接件103形成串联结构；位于所述衬底上的多个伪栅极211，所述伪栅极211至少位于所述接触插塞107的一侧。如图2b所示，所述衬底101上还包括介质层109，所述介质层109覆盖所述衬底101，所述接触插塞107形成在所述介质层109内。
如此，使得测试结构与实际集成电路应用的结构更加接近，这样的测试结构更加能够反映接触插塞的工艺情况，可以较准确的测试出接触插塞的电阻值。
在实际操作中，所述衬底可以是硅、硅锗、锗或其他合适的半导体。所述有源区域可以通过掺杂诸如磷、砷、其他n型掺杂剂或其组合的n型掺杂剂来形成N型掺杂区；并且可以通过掺杂诸如硼、铟、其他p型掺杂剂或其组合的p型掺杂剂来形成P型掺杂区，在实际操作中，所述有源区域105包括源漏掺杂区。所述连接件103的材料例如可以为导电材料，包 括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。所述接触插塞107的底部与所述有源区域105电连接还可以通过金属硅化物层实现欧姆接触，以降低串联电阻。所述金属硅化物层中包括铁、钴、镍、铂或它们合金的硅化物，例如低电阻率的硅化镍、硅化铂、硅化钴或其合金。
在一些具体实施例中，如附图2a-2b所示，多个所述伪栅极211相互平行排列，且至少一个所述伪栅极211位于同一所述有源区域105上的两个所述接触插塞107之间，所述伪栅极211部分覆盖所述有源区域105，且所述伪栅极211的宽度W2小于所述有源区域105的宽度W1。在一些其他实施例中，所述接触插塞107的材料和所述连接件103的材料可以相同。例如，在介质层109中形成通孔结构后，通过沉积导电材料，形成接触插塞107，再继续沉积导电材料形成覆盖所述介质层109表面的导电材料覆盖层，图案化所述导电材料覆盖层，形成多个连接件103。一方面可以简化工艺流程，并且可以降低连接件与接触插塞之间的接触电阻。
在一些实施例中，如图2b所示，至少一个所述接触插塞107的侧壁具有凹陷部110，所述接触插塞107的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述伪栅极的一侧。由于实际应用中的接触插塞处在真实的集成电路环境中，集成电路制备工艺中的一些工艺环节会对接触插塞的形貌产生影响，例如在接触插塞的侧壁上形成凹陷等，这会对接触插塞的电阻值产生影响。本公开实施例提供的接触插塞的测试结构中伪栅极通常在接触插塞之前形成，由于接触插塞与伪栅极之间距离很小，在后续打孔填充导电材料形成接触插塞时，由于附近伪栅极的存在，往往会在接触插塞靠近伪栅极的一侧形成如图2b所示的凹陷部。这使得本公开实施例提供的接触插塞在形貌上更加接近实际应用在集成电路中的接触插塞，能够进一步提高接触插塞电阻值测量的准确性。
图3是图2b中虚线圈内结构的放大示意图，如图3所示，在一些实施例中，至少一个所述有源区域105的位于所述伪栅极211下方的部分的上表面高于位于所述接触插塞107与所述伪栅极211之间的部分的上表面，也即图3中的高度H大于h。由于实际应用中的接触插塞处在真实的集成电路环境中，集成电路制备工艺中的一些工艺环节会对衬底的表面高度产生影响，例如栅线的制备会导致栅线两侧衬底的表面发生下陷等问题，这导致真实环境中的接触插塞的底端与衬底之间形成的接合面低于理想情形下接触插塞底端与衬底之间的接合面，也就是说，在实际应用环境中的接触插塞的高度高于理想情形，这导致实际接触插塞电阻值与理想情况存在差异。本公开实施例提供的接触插塞的测试结构，刻蚀形成伪栅极的制备工艺会对伪栅极两侧的衬底的表面产生一定的刻蚀作用，这使得伪栅极两侧衬底的上表面下降，那么，后续形成的接触插塞的底端与有源区域之间的接合面下降，也即使得接触插塞的高度增加。这使得本公开实施例提供 的接触插塞更加接近实际应用在集成电路中的接触插塞，从而能够进一步提高接触插塞电阻值测量的准确性。
在另一实施方式中，如附图4a-4b所示，附图4a是本公开实施例提供的接触插塞测试结构的平面示意图，附图4b为沿附图4a中虚线处的剖面示意图，多个所述伪栅极211相互平行排列，且所述伪栅极211位于有源区域105阵列中相邻的两列所述有源区域105之间的区域，且所述伪栅极的宽度W2小于等于相邻的两列所述有源区域之间的距离W3。这里，伪栅极211在相邻两个串联的接触插塞107之间，连接件103跨过所述伪栅极211连接位于伪栅极211两侧的两个接触插塞107。
在另一实施方式中，如附图5a-5b所示，附图5a是本公开实施例提供的接触插塞测试结构的平面示意图，附图5b为沿附图5a中虚线处的剖面示意图，多个所述伪栅极211相互平行排列，且所述伪栅极211位于有源区域105阵列中相邻的两行所述有源区域105之间的区域，且所述伪栅极211的宽度W2小于等于相邻两行所述有源区域105之间的距离W4。
在上述的实施方式中，伪栅极形成于相邻的有源区域之间的区域，在工艺上可以在衬底上先形成伪栅极图案，再在伪栅极两侧离子注入形成有源区，一方面相比于在有源区上形成伪栅极的方案简化了工艺流程，另一方面该流程更加接近实际集成电路应用下接触插塞的工艺。
在另一实施方式中，如附图6a-6b所示，附图6a是本公开实施例提供的接触插塞测试结构的平面示意图，附图6b为沿附图6a中虚线处的剖面示意图，多个伪栅极211平行排布，且所述伪栅极211的延伸方向与有源区域阵列中每列所述有源区域的排布方向平行，且每个接触插塞107的两侧均设置有伪栅极211。如此，接触插塞的两个侧面均与伪栅极相邻，这使得本公开实施方式中的测试结构更加接近真实的集成电路环境，进一步提高接触插塞电阻值测量的准确性。
在以上的各实施方式中，有源区域阵列为行列垂直的排布方式，然而，上述排布方式仅为一种实施方式的举例，应当理解的是，可以采用各种排布形式实现本公开，而不应被这里阐述的具体实施方式所限制。例如，在另一实施方式中，如附图6c所示，附图6c为本公开实施例提供的接触插塞测试结构的平面示意图，有源区域105阵列的行延伸方向与列延伸方向不垂直，所述伪栅极211延伸的方向与有源区域阵列的行延伸方向垂直，且与有源区域阵列的列延伸方向呈一定夹角，位于相邻两伪栅极211之间的所述连接件103的延伸方可以平行于伪栅极的延伸方向，这可以进一步提高器件的集成度。
在一些其他实施例中，如图6c所示，所述有源区域105、所述接触插塞107和所述连接件103以迂回的方式排列成一蛇形结构。在一些具体实施例中，有源区域105排列成阵列结构，相邻的两个接触插塞通过有源区域或连接件相连以L型、U形、M型、S型或W形的线性方式进行排列或 以迂回的方式形成蛇形的串联结构。如此，通过迂回蛇形串联方式的设计，能够提高测试结构的排布集成度并实现测试结构的小型化。
基于上述方案的测试结构，本实施例还提供了一种接触插塞的测试方法，所述测试方法包括：在串联结构中选择两个不同的接触插塞，分别作为输入端和输出端。在输入端连接第一测试端，在输出端连接第二测试端，第一测试端和第二测试端分别连接恒流源，形成第一回路，以获取测试电流，例如记为I。在输入端连接第三测试端，在输出端连接第四测试端，第三测试端和第四测试端分别连接电压表，形成第二回路，以获取测试电压，例如记为U。由测试电压U除以测试电流I得出测试电阻。将所述测试电阻与预先设定的理想电阻范围进行比较，若所述测试电阻在所述理想电阻范围内则判定接触插塞的性能合格。反之，则该串联结构中存在至少一个接触插塞的性能存在异常。
本公开另一实施例还提供了一种接触插塞的测试结构，附图7a是本公开实施例提供的接触插塞测试结构的平面示意图，附图7b为沿附图7a中虚线处的剖面示意图，参考附图7a-7b，包括：衬底101；设置于所述衬底上的多个有源区域705，所述有源区域705包括两个源漏掺杂区705-1和位于两个所述源漏掺杂区705-1之间的沟道掺杂区705-2；设置于所述沟道掺杂区705-2上的栅极711，有源区域705与栅极711构成晶体管713，也即位于所述栅极711底部的沟道掺杂区705-2以及位于所述栅极两侧的源漏掺杂区705-1与栅极711构成晶体管713；设置于所述衬底101上的多个接触插塞107，所述接触插塞107的底部与所述晶体管713的源漏掺杂区705-1电连接；多个连接件103，每一所述连接件103电连接相邻两个所述晶体管713上的接触插塞107，使得所述有源区域705、所述接触插塞107和所述连接件103形成串联结构。附图7b为沿虚线处的剖面示意图，所述衬底101上还包括介质层109，所述介质层109覆盖所述衬底101，所述接触插塞107形成在所述介质层109内。
如此，使得测试结构与实际集成电路应用的结构最为接近，这样的测试结构更加能够反映接触插塞的实际工艺情况，可以较准确的测试出接触插塞的电阻值。
在实际操作中，所述衬底101可以是硅、硅锗、锗或其他合适的半导体。所述源漏掺杂区705-1或所述沟道掺杂区705-2可以通过掺杂诸如磷、砷、其他n型掺杂剂或其组合的n型掺杂剂来形成N型掺杂区；并且可以通过掺杂诸如硼、铟、其他p型掺杂剂或其组合的p型掺杂剂来形成P型掺杂区。具体的，所述沟道掺杂区705-2的掺杂离子类型与所述源漏掺杂区705-1的掺杂离子类型相反。所述连接件103的材料例如可以为导电材料，包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。所述接触插塞107的底部与所述源漏掺杂区705-1电连接还可以通过金属硅化物层实现欧姆接触，以降低串联电阻。所述金属硅化物 层中包括铁、钴、镍、铂或它们合金的硅化物，例如低电阻率的硅化镍、硅化铂、硅化钴或其合金。
在一些其他实施例中，所述接触插塞107的材料和所述连接件103的材料相同。例如，在介质层109中形成通孔结构后，通过沉积导电材料，形成接触插塞107，再继续沉积导电材料形成覆盖所述介质层109表面的导电材料覆盖层，图案化所述导电材料覆盖层，形成多个连接件103。一方面可以简化工艺流程，并且可以降低连接件与接触插塞之间的接触电阻。
在一些其他实施例中，至少一个所述接触插塞107的侧壁具有凹陷部，所述接触插塞107的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述栅极的一侧(图7b中未示出，可参考图2b中的凹陷结构)。由于实际应用中的接触插塞处在真实的集成电路环境中，集成电路制备工艺中的一些工艺环节会对接触插塞的形貌产生影响，例如在接触插塞的侧壁上形成凹陷等，这会对接触插塞的电阻值产生影响。本公开实施例提供的接触插塞的测试结构中栅极通常在接触插塞之前形成，由于接触插塞与栅极之间距离很小，在后续打孔填充导电材料形成接触插塞时，由于附近栅极的存在，往往会在接触插塞靠近栅极的一侧形成如图2b所示的凹陷部。这使得本公开实施例提供的接触插塞在形貌上更加接近实际应用在集成电路中的接触插塞，进而能够提高接触插塞电阻值测量的准确性。
在一些其他实施例中，至少一个所述衬底的位于所述栅极下方的部分的上表面高于位于所述接触插塞与所述栅极之间的部分的上表面(图7b中未示出，可参考图3)。由于实际应用中的接触插塞处在真实的集成电路环境中，集成电路制备工艺中的一些工艺环节会对衬底的表面高度产生影响，例如栅线的制备会导致衬底的表面发生下陷等问题，这导致真实环境中的接触插塞的底端与衬底的表面之间形成的接合面低于理想情形下接触插塞底端与衬底表面之间的接合面，也就是说，在实际应用环境中的接触插塞的高度高于理想情形，因而实际应用中的接触插塞电阻与理想情形不同。本公开实施例提供的接触插塞的测试结构中，刻蚀形成栅极的制备工艺会对位于栅极两侧的待形成源漏掺杂区的衬底表面产生一定的刻蚀作用，这最终会导致位于栅极两侧的源漏掺杂区的上表面下降，位于栅极两侧的源漏掺杂区的上表面低于位于栅极下方的衬底的上表面，那么，后续形成的接触插塞的底端与源漏掺杂区之间的接合面下降，也即使得接触插塞的高度增加。这使得本公开实施例提供的接触插塞更加接近实际应用在集成电路中的接触插塞，进而能够提高接触插塞电阻值测量的准确性。
在上述的实施方式中，有源区域705均为行列垂直的排布方式，然而，上述排布方式仅为一种实施方式的举例，应当理解的是，可以采用各种排布形式实现本公开，而不应被这里阐述的具体实施方式所限制。例如，在另一实施方式中，如附图7c-7d所示，有源区域705阵列的行延伸方向与列 延伸方向不垂直，所述栅极711延伸的方向与有源区域705阵列的行延伸方向垂直，且与有源区域705阵列的列延伸方向呈一定夹角，位于相邻两栅极711之间的所述连接件103的延伸方向平行于栅极711的延伸方向，这可以提高器件的集成度。
在另一实施方式中，图8a为本公开另外的实施例提供的接触插塞测试结构的平面示意图，图8b为图8a中虚线处的剖面示意图；如图8a-8b所示，所述有源区域705、所述接触插塞107和所述连接件103以迂回的方式排列成一蛇形结构。例如，有源区域705排列成阵列结构，相邻的两个接触插塞通过晶体管或连接件相连以L型、U形、M型、S型或W形的线性方式进行排列或以迂回的方式形成蛇形串联结构。如此，通过迂回蛇形串联方式的设计，能够提高测试结构的排布集成度并实现测试结构的小型化。
在另一实施方式中，图8c为本公开另一实施例提供的接触插塞测试结构的平面示意图，图8d为图8c中沿行延伸方向的虚线处的剖面示意图；如图8c-8d所示，包括多个有源区域705，位于有源区域705上的多个接触插塞107和电连接接触插塞的连接件103；其中，多个所述有源区域705、所述接触插塞107和所述连接件103以迂回的方式排列成一蛇形结构。多个栅极711相互平行排列且沿列延伸方向延伸，其中，相邻的两个栅极711，一个位于有源区域705上，另一个位于相邻两个有源区域705之间的衬底上。如图8d所示的剖面结构，有源区域705包括两个源漏掺杂区705-1和位于两个所述源漏掺杂区705-1之间，且位于栅极711下方的沟道掺杂区705-2，所述有源区域705和其上的栅极711构成晶体管713。同一所述源漏掺杂区705-1上设置两个接触插塞107，所述两个接触插塞107位于栅极711的同一侧。在进行接触插塞电阻测量时，不需要在栅极711上额外施加电压，晶体管713不需要导通，电流不经过沟道掺杂区705-2，而是通过连接于同一源漏掺杂区705-1上的两个接触插塞经由共同连接的源漏掺杂区和所述连接件以迂回的方式排列成一蛇形结构来实现导通。如此，完全表征了晶体管的真实工艺制造环境，还原了接触插塞的实际器件环境，同时在测量接触插塞的电阻时，不需要对晶体管进行开启，进而能够避免增加和改变测量条件，从而巧妙和准确地测量出接触插塞的电阻值。
在一些实施例中，所述源漏掺杂区705-1还可以包括LDD区和Halo区(图中未示出)。在实际操作中，可以对位于栅极或伪栅极两侧的衬底首先采用大角度离子注入，而后采用小角度离子注入工艺实现LDD区和Halo区的形成。
本实施例还提供了一种接触插塞的测试结构的形成方法，具体请参见附图9，如图所示，所述方法包括以下步骤：
步骤901：提供衬底；
步骤902：在所述衬底上形成多个有源区域；
步骤903：在所述衬底上形成伪栅极堆叠；
步骤904：刻蚀所述伪栅极堆叠，形成多个伪栅极；
步骤905：在所述衬底上形成介质层，所述介质层覆盖所述伪栅极；
步骤906：刻蚀所述介质层，形成接触孔，同一所述有源区域上形成至少两个接触孔，所述接触孔至少位于所述伪栅极的一侧；
步骤907：沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述有源区域电连接，继续沉积导电材料形成覆盖所述介质层表面的导电材料覆盖层；
步骤908：图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
下面结合具体实施例对本公开实施例提供的半导体结构的制备方法再作进一步详细的说明。
图10a至图10h为本公开实施例提供的测试结构在制备过程中的器件结构示意图。
首先，执行步骤901，参见图10a，提供衬底101。所述衬底可以是硅、硅锗、锗或其他合适的半导体。
接着，参见图10b，执行步骤902，在所述衬底上形成多个有源区域105。
在实际操作中，可以先在衬底101的上表面生长一层掩膜层，接着对该掩膜层进行图案化，以在掩膜层上显示出要离子注入的图形，形成有源区域开口。可以通过光刻工艺对该掩膜层进行图案化。例如通过曝光、显影和去胶等步骤对该掩膜层进行图案化。接着掺杂从所述有源区域开口暴露的所述衬底，形成有源区域105。在一实施方式中，可以采用离子注入工艺形成有源区域。在一些实施例中，所述有源区域105包括源漏掺杂区，且所述源漏掺杂区的掺杂类型为N型或者P型的一种。具体的，所述有源区域可以通过掺杂诸如磷、砷、其他n型掺杂剂或其组合的n型掺杂剂来形成N型掺杂区；并且可以通过掺杂诸如硼、铟、其他p型掺杂剂或其组合的p型掺杂剂来形成P型掺杂区。
然后，执行步骤903，参见图10c，在所述衬底上形成伪栅极堆叠1011，所述伪栅极堆叠1011包括伪栅极电极层和伪栅极介电层。
接着，执行步骤904，参见图10d，刻蚀所述伪栅极堆叠1011，形成多个伪栅极211。
具体的，可以先在伪栅极堆叠的上表面生长一层掩膜层，接着对该掩膜层进行图案化，以在掩膜层上显示出要刻蚀的图形，可以通过光刻工艺对该掩膜层进行图案化。该掩膜层可以是光致抗蚀剂掩模或者基于光刻掩模进行图案化的硬掩模；当该掩膜层是光致抗蚀剂掩模时，具体通过曝光、显影和去胶等步骤对该掩膜层进行图案化。随后实行蚀刻工艺以将图案从硬掩模层转移至伪栅极堆叠。
具体操作中，所述伪栅极还可以包括伪栅极侧壁外的侧墙结构(图中 未示出)，所述侧墙结构覆盖所述伪栅极的侧壁。
在一些实施例中，多个所述伪栅极211相互平行排列，所述伪栅极211部分覆盖所述有源区域105，且所述伪栅极211的宽度小于所述有源区域105的宽度。本实施例的一些具体实施例提供的结构，至少一个所述有源区域的位于所述伪栅极下方的部分的上表面高于位于所述接触插塞与所述伪栅极之间的部分的上表面，这是由于刻蚀形成伪栅极211时过刻蚀伪栅极211两侧的衬底带来的，这使得本实施例提供的形成方法制备的测试结构，能够提供更加贴近实际集成电路中应用的结构，从而得到更加准确的测量结果。
在实际操作中，可以将所有的有源区域上均形成伪栅极，以提高准确度。
而后，参见图10e，执行步骤905，在所述衬底上形成介质层109，所述介质层109覆盖所述伪栅极211。
接着，参见图10f，执行步骤906，刻蚀所述介质层109，形成接触孔1007，同一所述有源区域上形成至少两个接触孔，所述接触孔至少位于所述伪栅极的一侧。
接着，参见图10g，执行步骤907，沉积导电材料，所述导电材料填充所述接触孔1007形成接触插塞107，所述接触插塞的底部与所述有源区域电连接，继续沉积导电材料形成覆盖所述介质层表面的导电材料覆盖层1003。
由于实际操作中，伪栅极与接触插塞的距离较近，伪栅极的存在往往会导致接触插塞朝向所述伪栅极的一侧形成凹陷部，所述接触插塞的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述伪栅极的一侧。这使得本实施例提供的结构，能够提供更加贴近实际集成电路中应用的接触插塞，从而得到更加准确的测量结果。
最后，执行步骤908，参见图10h，图案化所述导电材料覆盖层1003，形成多个连接件103，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域105、所述接触插塞107和所述连接件103形成串联结构。
需要说明的是，本公开实施例中的各步骤在不冲突的情况下，部分步骤可以同时执行，也可以调用先后顺序执行。例如，步骤902可以在步骤903、904之后执行，在实际操作中，可以先执行步骤903，在所述衬底上形成伪栅极堆叠，所述伪栅极堆叠包括伪栅极电极层和伪栅极介电层。接着，执行步骤904，刻蚀所述伪栅极堆叠，形成多个伪栅极。接着，执行步骤902，在所述衬底上形成多个有源区域，具体的，采用自对准工艺，利用形成的伪栅极作为掩膜，再通过扩散或离子注入在所述伪栅极的两侧衬底内形成多个有源区域。
在另一实施方式中，多个所述伪栅极相互平行排列，且所述伪栅极位 于相邻的所述有源区域之间，且所述伪栅极的宽度小于等于相邻所述有源区域的宽度。
在另一实施方式中，同一接触插塞的两侧存在伪栅极，其中一侧的伪栅极覆盖所述有源区域。
本实施例还提供了一种接触插塞的测试结构的形成方法，具体请参见附图11，如图所示，所述方法包括以下步骤：
步骤1101：提供衬底；
步骤1102：在所述衬底上形成沟道掺杂区；
步骤1103：在所述衬底上形成栅极堆叠；
步骤1104：刻蚀所述栅极堆叠，形成多个栅极；
步骤1105：在所述栅极的两侧衬底内形成多个源漏掺杂区，由位于所述栅极两侧的源漏掺杂区和位于栅极底部的沟道掺杂区构成有源区域，所述有源区域和所述栅极构成晶体管；
步骤1106：在所述衬底上形成介质层，所述介质层覆盖所述栅极；
步骤1107：刻蚀所述介质层，形成接触孔；
步骤1108：沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述源漏掺杂区电连接，继续沉积导电材料，形成覆盖所述介质层表面的导电材料覆盖层；
步骤1109：图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接相邻两个所述晶体管上的接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
下面结合具体实施例对本公开实施例提供的半导体结构的制备方法再作进一步详细的说明。
图12a至图12i为本公开实施例提供的测试结构在制备过程中的器件结构示意图。
首先，执行步骤1101，参见图12a，提供衬底101。所述衬底可以是硅、硅锗、锗或其他合适的半导体。
接着，执行步骤1102，参见图12b，执行步骤1102，在所述衬底101上形成沟道掺杂区705-2。具体操作中，首先在衬底上形成掩膜层，图案化所述掩膜层形成沟道掺杂区开口，接着通过扩散或离子注入工艺掺杂暴露于所述沟道掺杂区开口的衬底，形成沟道掺杂区。在实际操作中，可以根据实际需要调整所述沟道掺杂区位于衬底中的位置。
接着，参见图12c，执行步骤1103，在所述衬底上形成栅极堆叠1111，所述栅极堆叠1111包括栅极电极层和栅极介电层。
然后，执行步骤1104，参见图12d，刻蚀所述栅极堆叠，形成多个栅极711。
具体的，可以先在栅极堆叠的上表面生长一层掩膜层，接着对该掩膜层进行图案化，以在掩膜层上显示出要刻蚀的图形，可以通过光刻工艺对 该掩膜层进行图案化。该掩膜层可以是光致抗蚀剂掩模或者基于光刻掩模进行图案化的硬掩模；当该掩膜层是光致抗蚀剂掩模时，具体通过曝光、显影和去胶等步骤对该掩膜层进行图案化。随后实行蚀刻工艺以将图案从硬掩模层转移至栅极堆叠。
具体操作中，所述栅极还可以包括栅极侧壁外的侧墙结构(图中未示出)，所述侧墙结构覆盖所述栅极的侧壁。
在一些实施例中，可以采用形成沟道掺杂区的掩膜窗口直接形成多个栅极，具体的，首先在衬底上形成掩膜层，图案化所述掩膜层形成沟道掺杂区开口，接着通过扩散或离子注入工艺掺杂暴露于所述沟道掺杂区开口的衬底，形成沟道掺杂区。接着采用形成沟道掺杂区705-2的同一个掩膜窗口直接沉积栅极堆叠材料，以形成多个栅极711，最后去除所述掩膜层。如此，相比于通过沉积刻蚀形成多个栅极的方法。本方法简化了工艺流程，且栅极与沟道掺杂区位置相对应，防止后续刻蚀带来的对位偏移问题。
接着，参见图12e，执行步骤1105，在所述栅极711的两侧衬底内形成多个源漏掺杂区705-1，由位于所述栅极两侧的源漏掺杂区705-1和位于栅极底部的沟道掺杂区705-2构成有源区域705，有源区域705与栅极711构成晶体管713，也即位于栅极两侧的所述源漏掺杂区705-1、位于栅极底部的所述沟道掺杂区705-2和所述栅极711构成晶体管713。
在一些具体实施例中，在所述栅极的两侧衬底内形成多个源漏掺杂区，包括：
形成覆盖所述栅极711侧壁的侧墙结构(图中未示出)；
以所述栅极与所述侧墙结构为掩膜，自对准离子注入源漏掺杂离子，形成源漏掺杂区。
在一些实施例中，所述沟道掺杂区通过离子注入掺杂第一离子类型，所述源漏掺杂区通过离子注入掺杂第二离子类型，所述第一、第二离子类型为N型或者P型的一种，且所述第一离子与所述第二离子的类型相反。
在实际操作中，所述晶体管713可以为金属氧化物半导体晶体管(MOS)，例如P型金属氧化物半导体晶体管(PMOS)或N型金属氧化物半导体晶体管(NMOS)。
而后，参见图12f，执行步骤1106，在所述衬底上形成介质层109，所述介质层109覆盖所述栅极711。
接着，参见图12g，执行步骤1107，刻蚀所述介质层109，形成接触孔1007。
接着，参见图12h，执行步骤1108，沉积导电材料，形成接触插塞107，所述接触插塞的底部与所述源漏掺杂区电连接，继续沉积导电材料，形成覆盖所述介质层表面的导电材料覆盖层1003。
由于实际操作中，栅极与接触插塞的距离较近，栅极的存在往往会导致接触插塞朝向所述栅极的一侧形成凹陷部，所述接触插塞的侧壁在所述 凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述栅极的一侧。这使得本实施例提供的结构，能够提供更加贴近实际集成电路中应用的接触插塞，从而得到更加准确的测量结果。
最后，执行步骤1109，参见图12i，图案化所述导电材料覆盖层1003，形成多个连接件103，每一所述连接件电连接相邻两个所述晶体管上的所述接触插塞，使得所述晶体管713、所述接触插塞107和所述连接件103形成串联结构。
在实际操作中，所述测试结构中的晶体管与接触插塞可以与核心区的实际应用的晶体管和接触插塞在同一形成工艺中形成。具体的，上述测试结构的形成方法中的步骤1101-1109可以与核心区中晶体管与接触插塞的形成步骤为同样的步骤。
基于上述方案的测试结构，本实施例还提供了一种接触插塞的测试方法，适用于附图7a、7c和图8a所对应的测试结构，参见附图13，所述测试方法包括：
在串联结构中选择两个不同的接触插塞，分别作为输入端1305和输出端1306。将串联在所述两个接触插塞之间的晶体管的栅极加工作电压，使得晶体管导通。在输入端连接第一测试端1301，在输出端连接第二测试端1302，第一测试端1301和第二测试端1302分别连接恒流源1307，形成第一回路，以获取测试电流，例如记为I。在输入端连接第三测试端1303，在输出端连接第四测试端1304，第三测试端和第四测试端分别连接电压表1308，形成第二回路，以获取测试电压，例如记为U。由测试电压U除以测试电流I得出测试电阻。将所述测试电阻与预先设定的理想电阻范围进行比较，若所述测试电阻在所述理想电阻范围内则判定接触插塞的性能合格。反之，则该串联结构中存在至少一个接触插塞的性能存在异常。
对于图2a、4a、5a、6a、6c和8c所示的测试结构，在进行测试接触插塞电阻值的测试时，伪栅极或栅极上可以不施加电压。其中对于图2a、4a、5a、6a、6c所示的测试结构，其导电通路为有源区域、接触插塞和连接件形成的串联结构。对于8c所示的测试结构，其导电通路通过连接于同一源漏掺杂区的两个接触插塞经由共同连接的源漏掺杂区来实现导通，这可以完全表征晶体管的工艺制造环境，还原接触插塞的器件环境，同时又不需要开启晶体管，进而避免增加和改变测量条件，巧妙地和准确地测量出了接触插塞的电阻值。
综上所述，本公开测试结构与实际集成电路应用的结构更加接近，这样的测试结构更加能够反映接触插塞的工艺情况，可以较准确的测试出接触插塞的电阻值。
需要说明的是，本公开实施例提供的接触插塞的测试结构可以应用于任何包括接触插塞的结构中，例如存储器外围电路接触插塞电阻值的测量。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以 任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供了一种接触插塞的测试结构，包括：衬底；设置于所述衬底上的多个有源区域；设置于所述衬底上的多个接触插塞，同一所述有源区域上形成至少两个接触插塞，且所述接触插塞的底部与所述有源区域电连接；多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构；位于所述衬底上的多个伪栅极，所述伪栅极至少位于所述接触插塞的一侧。如此，使得测试结构与实际集成电路应用的结构更加接近，这样的测试结构更加能够反映接触插塞的工艺情况，可以较准确的测试出接触插塞的电阻值。

Claims (17)

  1. 一种接触插塞的测试结构，包括：
    衬底；
    设置于所述衬底上的多个有源区域；
    设置于所述衬底上的多个接触插塞，同一所述有源区域上形成至少两个接触插塞，且所述接触插塞的底部与所述有源区域电连接；
    多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构；
    位于所述衬底上的多个伪栅极，所述伪栅极至少位于所述接触插塞的一侧。
  2. 如权利要求1所述的测试结构，其中，多个所述伪栅极相互平行排列，且至少一个所述伪栅极位于同一所述有源区域上的两个所述接触插塞之间，所述伪栅极部分覆盖所述有源区域，且所述伪栅极的宽度小于所述有源区域的宽度。
  3. 如权利要求1所述的测试结构，其中，多个所述伪栅极相互平行排列，且所述伪栅极位于相邻的所述有源区域之间，且所述伪栅极的宽度小于相邻所述有源区域的宽度。
  4. 如权利要求1所述的测试结构，其中，至少一个所述接触插塞的侧壁具有凹陷部，所述接触插塞的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述伪栅极的一侧。
  5. 如权利要求1所述的测试结构，其中，所述有源区域、所述接触插塞和所述连接件以迂回的方式排列成一蛇形结构。
  6. 如权利要求1所述的测试结构，其中，同一接触插塞的两侧存在伪栅极，其中一侧的伪栅极覆盖所述有源区域。
  7. 如权利要求1所述的测试结构，其中，所述接触插塞的材料和所述连接件的材料相同。
  8. 一种接触插塞的测试结构，包括：
    衬底；
    设置于所述衬底上的多个有源区域，所述有源区域包括两个源漏掺杂区和位于两个所述源漏掺杂区之间的沟道掺杂区；
    设置于所述沟道掺杂区上的栅极，所述栅极、位于所述栅极底部的沟道掺杂区以及位于所述栅极两侧的源漏掺杂区构成晶体管；
    设置于所述衬底上的多个接触插塞，所述接触插塞的底部与所述晶体管的源漏掺杂区电连接；
    多个连接件，每一所述连接件电连接相邻两个所述晶体管上的接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
  9. 如权利要求8所述的测试结构，其中，至少一个所述接触插塞的侧壁具有凹陷部，所述接触插塞的侧壁在所述凹陷部处沿侧向方向向内凹陷，且所述凹陷部位于所述接触插塞的朝向相邻的所述栅极的一侧。
  10. 如权利要求8所述的测试结构，其中，所述有源区域、所述接触插塞和所述连接件以迂回的方式排列成一蛇形结构。
  11. 一种接触插塞的测试结构的形成方法，包括：
    提供衬底；
    在所述衬底上形成多个有源区域；
    在所述衬底上形成伪栅极堆叠；
    刻蚀所述伪栅极堆叠，形成多个伪栅极；
    在所述衬底上形成介质层，所述介质层覆盖所述伪栅极；
    刻蚀所述介质层，形成接触孔，同一所述有源区域上形成至少两个接触孔，所述接触孔至少位于所述伪栅极的一侧；
    沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述有源区域电连接，继续沉积导电材料形成覆盖所述介质层表面的导电材料覆盖层；
    图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接分别位于不同有源区域上的所述接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
  12. 如权利要求11所述的形成方法，其中，在所述衬底上形成多个有源区域；在所述衬底上形成伪栅极堆叠，包括：
    在所述衬底上形成掩膜层，刻蚀所述掩膜层形成有源区域开口；
    掺杂从所述有源区域开口暴露的所述衬底，形成有源区域；
    在形成有源区域之后，沉积伪栅极堆叠。
  13. 如权利要求11所述的形成方法，其中，所述有源区域包括源漏掺杂区，且所述源漏掺杂区的掺杂类型为N型或者P型的一种。
  14. 一种接触插塞的测试结构的形成方法，包括：
    提供衬底；
    在所述衬底上形成沟道掺杂区；
    在所述衬底上形成栅极堆叠；
    刻蚀所述栅极堆叠，形成多个栅极；
    在所述栅极的两侧衬底内形成多个源漏掺杂区，由位于所述栅极两侧的源漏掺杂区和位于栅极底部的沟道掺杂区构成有源区域，所述有源区域和所述栅极构成晶体管；
    在所述衬底上形成介质层，所述介质层覆盖所述栅极；
    刻蚀所述介质层，形成接触孔；
    沉积导电材料，所述导电材料填充所述接触孔形成接触插塞，所述接触插塞的底部与所述源漏掺杂区电连接，继续沉积导电材料，形成覆盖所 述介质层表面的导电材料覆盖层；
    图案化所述导电材料覆盖层，形成多个连接件，每一所述连接件电连接相邻两个所述晶体管上的接触插塞，使得所述有源区域、所述接触插塞和所述连接件形成串联结构。
  15. 如权利要求14所述的形成方法，其中，在所述栅极的两侧衬底内形成多个源漏掺杂区，包括：
    形成覆盖所述栅极侧壁的侧墙结构；
    以所述栅极与所述侧墙结构为掩膜，自对准离子注入源漏掺杂离子，形成源漏掺杂区。
  16. 如权利要求15所述的形成方法，其中，所述沟道掺杂区通过离子注入掺杂第一离子类型，所述源漏掺杂区通过离子注入掺杂第二离子类型，所述第一、第二离子类型为N型或者P型的一种，且所述第一离子与所述第二离子的类型相反。
  17. 一种接触插塞的测试方法，基于权利要求8至10任一项的测试结构，所述测试方法包括：
    在串联结构中选择两个不同的接触插塞，分别作为输入端和输出端；
    将串联在所述两个接触插塞之间的晶体管的栅极加工作电压，使得晶体管导通；
    在输入端连接第一测试端，在输出端连接第二测试端，第一测试端和第二测试端分别连接恒流源，形成第一回路，以获取测试电流；
    在输入端连接第三测试端，在输出端连接第四测试端，第三测试端和第四测试端分别连接电压表，形成第二回路，以获取测试电压；
    由测试电压除以测试电流得出测试电阻；
    将所述测试电阻与预先设定的理想电阻范围进行比较，若所述测试电阻在所述理想电阻范围内则判定接触插塞的性能合格。
PCT/CN2021/136327 2021-10-15 2021-12-08 一种接触插塞的测试结构及其形成方法、测试方法 WO2023060732A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117096136A (zh) * 2023-10-20 2023-11-21 墨研计算科学（南京）有限公司 晶体管的栅极电阻测量结构及晶体管的制备方法
CN117594572A (zh) * 2023-12-08 2024-02-23 芯联越州集成电路制造（绍兴）有限公司 Wat测试结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022105A (zh) * 2006-02-16 2007-08-22 中芯国际集成电路制造(上海)有限公司 半导体器件的测试装置和用于制造测试装置的基版
CN203910786U (zh) * 2014-06-26 2014-10-29 中芯国际集成电路制造(北京)有限公司 一种半导体测试结构
US20140332883A1 (en) * 2013-05-07 2014-11-13 Samsung Electronics Co., Ltd. Semiconductor Device Having Dummy Gate and Gate
CN205231023U (zh) * 2015-12-18 2016-05-11 中芯国际集成电路制造（天津）有限公司 导电插塞电阻测量结构
CN206258520U (zh) * 2016-12-09 2017-06-16 中芯国际集成电路制造(北京)有限公司 一种接触电阻测试结构
CN109119350A (zh) * 2017-06-23 2019-01-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、测量电阻的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022105A (zh) * 2006-02-16 2007-08-22 中芯国际集成电路制造(上海)有限公司 半导体器件的测试装置和用于制造测试装置的基版
US20140332883A1 (en) * 2013-05-07 2014-11-13 Samsung Electronics Co., Ltd. Semiconductor Device Having Dummy Gate and Gate
CN203910786U (zh) * 2014-06-26 2014-10-29 中芯国际集成电路制造(北京)有限公司 一种半导体测试结构
CN205231023U (zh) * 2015-12-18 2016-05-11 中芯国际集成电路制造（天津）有限公司 导电插塞电阻测量结构
CN206258520U (zh) * 2016-12-09 2017-06-16 中芯国际集成电路制造(北京)有限公司 一种接触电阻测试结构
CN109119350A (zh) * 2017-06-23 2019-01-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、测量电阻的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117096136A (zh) * 2023-10-20 2023-11-21 墨研计算科学（南京）有限公司 晶体管的栅极电阻测量结构及晶体管的制备方法
CN117096136B (zh) * 2023-10-20 2024-01-30 墨研计算科学（南京）有限公司 晶体管的栅极电阻测量结构及晶体管的制备方法
CN117594572A (zh) * 2023-12-08 2024-02-23 芯联越州集成电路制造（绍兴）有限公司 Wat测试结构
CN117594572B (zh) * 2023-12-08 2024-05-24 芯联越州集成电路制造（绍兴）有限公司 Wat测试结构

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