WO2023051565A1 - 功率半导体器件及其制备方法、电子装置 - Google Patents

功率半导体器件及其制备方法、电子装置 Download PDF

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Publication number
WO2023051565A1
WO2023051565A1 PCT/CN2022/121965 CN2022121965W WO2023051565A1 WO 2023051565 A1 WO2023051565 A1 WO 2023051565A1 CN 2022121965 W CN2022121965 W CN 2022121965W WO 2023051565 A1 WO2023051565 A1 WO 2023051565A1
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functional layer
metal part
groove
layer
barrier
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PCT/CN2022/121965
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English (en)
French (fr)
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吴鸣
周建
丁永欢
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华为技术有限公司
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Publication of WO2023051565A1 publication Critical patent/WO2023051565A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a power semiconductor device, a manufacturing method thereof, and an electronic device.
  • a power semiconductor device such as a power supply, etc.
  • a power semiconductor device such as a power supply, etc.
  • a passivation layer includes a passivation layer, a first metal part, a second metal part and an insulating layer, the first metal part and the second metal part are arranged on the passivation layer at intervals, and the insulating layer Covering the passivation layer, the first metal part and the second metal part, the insulating layer fills the space between the first metal part and the second metal part.
  • the electric field between the first metal part and the second metal part will penetrate the delamination (the first metal part penetrates through the insulating layer and the passivation layer due to delamination.
  • metal migration also known as electromigration
  • Embodiments of the present application provide a power semiconductor device capable of improving reliability, a manufacturing method thereof, and an electronic device.
  • the present application provides a power semiconductor device, including a functional layer, a first metal portion, a second metal portion, and an insulating layer
  • the functional layer includes a first region, a second region, and a third region, and the first The third area is located between the first area and the second area
  • the functional layer further includes a first barrier groove arranged in the third area, and the first metal part covers the first area
  • the second metal portion is disposed on the second region
  • the insulating layer includes a main body and a first barrier portion that are connected, and the main body is disposed on the first metal portion, the second metal portion and the first barrier portion.
  • the first blocking portion fills the first blocking groove
  • the functional layer further includes at least one passivation layer.
  • the insulating layer forms a first barrier part in the first barrier groove, and the first barrier part is not in contact with the first metal part or the second metal part, which means that the insulating layer forms a recessed embedded structure in the functional layer, and the first barrier part Reduce the possibility of delamination between the functional layer and the insulating layer, effectively reduce the possibility of metal migration between the first metal part and the second metal part, and reduce the short circuit between the first metal part and the second metal part possibility, thereby improving the reliability of power semiconductor devices.
  • the first blocking groove includes a first port and a second port, and the first port is set on the functional layer closest to the first port.
  • the functional layer further includes a second barrier groove, the second barrier groove communicates with the second port, and the insulating layer further includes a second barrier portion, the second barrier portion communicates with the second port.
  • the second barrier part embedded in the second barrier groove increases the interface length between the functional layer and the insulating layer, that is, increases the metal migration path between the first metal part and the second metal part, and further reduces the Possibility of short circuit with the second metal part.
  • the diameter of the end of the second blocking groove close to the first blocking groove is larger than The diameter of the second port improves the connection stability between the functional layer and the insulating layer, further reduces the possibility of delamination between the functional layer and the insulating layer, and further reduces the gap between the first metal part and the second metal part. The possibility of intermetallic migration.
  • the functional layer further includes the first functional layer and the second functional layer stacked.
  • Two functional layers the material of the first functional layer is different from the material of the second functional layer, the first metal part and the second metal part are arranged on the first functional layer away from the second function layer, the first barrier groove is located in the first functional layer, the second barrier groove is located in the first functional layer and/or the second functional layer, and the first functional layer and the At least one of the second functional layers is a passivation layer.
  • the first functional layer and the second functional layer One is a passivation layer made of Si 3 N 4
  • the other of the first functional layer and the second functional layer is a passivation layer made of SiO 2
  • the second barrier groove is located at the first Two functional layers.
  • the passivation layer made of different materials can reduce the stress of the adjacent passivation layer and prolong the service life of the power semiconductor device.
  • the first functional layer is a Si layer
  • the second functional layer layer is a passivation layer
  • the second blocking groove is located on the first functional layer.
  • the Si layer is used to protect the passivation layer, and disposing the first blocking groove and the second blocking groove on the Si layer will not damage the structure of the passivation layer, and will not affect the function of the passivation layer.
  • the present application provides an electronic device, including a circuit board and a power semiconductor device provided on the circuit board according to the first aspect or the first to fourth possible implementations of the first aspect , the circuit board is provided with a control circuit, and the control circuit is used to control the turn-on and turn-off of the power semiconductor device.
  • the present application provides a method for manufacturing a power semiconductor device, including the following steps: providing a prefabricated structure, the functional layer, the first metal part and the second metal part, the functional layer includes a first region, a second area and a third area, the third area is located between the first area and the second area, the first metal part is disposed on the first area, and the second metal part is disposed on the On the second area, the functional layer also includes at least one passivation layer; a first barrier groove is formed on the third area of the functional layer; an insulating layer is formed, and the insulating layer includes a main body connected to the first The blocking part, the main body covers the first metal part, the second metal part and the third area, and the first blocking part fills the first blocking groove.
  • a first barrier groove is formed on the third area of the functional layer, and the insulating layer forms a first barrier part of a recessed structure in the functional layer, and the first barrier part can reduce the possibility of delamination between the functional layer and the insulating layer , effectively reducing the possibility of metal migration between the first metal part and the second metal part, reducing the possibility of short circuit between the first metal part and the second metal part, thereby improving the reliability of the power semiconductor device.
  • the preparation method before the formation of the insulating layer, further includes the step of forming a first barrier connected to the first barrier groove on the functional layer.
  • Two blocking grooves the first blocking groove includes a first port and a second port, the first port is set on the side of the functional layer closest to the first metal part, the second blocking groove and the The second port is connected;
  • the insulating layer further includes a second barrier part, and the forming the insulating layer further includes that the second barrier part fills the second barrier groove.
  • the second barrier part embedded in the second barrier groove increases the interface length between the functional layer and the insulating layer, that is, increases the metal migration path between the first metal part and the second metal part, and further reduces the Possibility of short circuit with the second metal part.
  • the functional layer is a single passivation layer
  • the first The blocking groove includes: putting the prefabricated structure into an etching chamber, using dry etching to mask the dielectric film process, injecting the first gas into the etching chamber to etch the functional layer, so that the functional layer is formed on the functional layer
  • the first barrier groove and forming a protective film on the side wall of the first barrier groove, the first gas includes a high carbon molecule fluorocarbon-based gas
  • the formation of the second barrier groove on the functional layer includes, Using a dry etching masking dielectric film process, injecting a second gas into the etching chamber to etch the functional layer, so that a second barrier groove communicating with the second port is formed on the functional layer, and the functional layer is formed on the functional layer.
  • the second gas includes a hydrofluorocarbon-based gas.
  • the functional layer is a single passivation layer structure, which simplifies the structure of the power semiconductor device and simplifies the preparation of the power semiconductor device.
  • the first gas includes a high-carbon molecular fluorocarbon-based gas, and the high-carbon molecular fluorocarbon-based gas can produce relatively There are many fluorocarbon-containing polymer films, and these polymer films are deposited on the groove wall of the first barrier groove to form a protective film, thereby forming anisotropic etching on the functional layer.
  • etching to mask the dielectric film, inject a second gas into the etching chamber to etch the functional layer, the second gas includes hydrocarbon fluorine-based gas, and the hydrocarbon fluorine-based gas chemically etches the functional layer, so that Improve the etching rate and accelerate the preparation efficiency of power semiconductor devices.
  • the functional layer includes a first functional layer and a second functional layer, the material of the first functional layer is different from that of the second functional layer, the first functional layer is a passivation layer made of Si 3 N 4 , and the second functional layer is made of SiO 2
  • the passivation layer formed; the first metal part is arranged on the first functional layer in the first region and the second metal part is arranged on the first functional layer in the second region; the functional layer Forming the first barrier groove on the top includes, putting the prefabricated structure into the etching chamber, using dry etching to mask the dielectric film process, injecting the first gas or the second gas into the etching chamber to etch the functional layer , so that the first barrier groove is formed on the first functional layer, the first gas includes a high-carbon molecular fluorocarbon-based gas, and the second gas includes a hydrofluorocarbon-based gas; Forming a second blocking groove on
  • the functional layer includes a stacked first functional layer and a second Functional layer, the material of the first functional layer is different from the material of the second functional layer, the first functional layer is a Si layer, and the second functional layer is a passivation layer; in the first region The first metal part is provided on the first functional layer and the second metal part is provided on the first functional layer in the second region; the formation of the first barrier groove on the functional layer includes, the prefabricated The structure is placed in an etching chamber, and a dry etching process is used to mask the dielectric film.
  • a third gas is injected into the etching chamber to etch the first functional layer, so that the first functional layer is formed on the first functional layer.
  • a barrier groove, the third gas includes SF 6 ; forming the second barrier groove on the functional layer includes, using a dry etching masking dielectric film process, passing the third gas into the etching chamber The gas performs isotropic etching on the first functional layer, so that the second functional layer forms the second barrier groove.
  • the Si layer serves to protect the passivation layer.
  • the preparation method further includes the step of feeding the first gas into the etching chamber, and using dry etching to mask the dielectric film on the groove wall of the first barrier groove Depositing to form a protective film, the first gas includes a high-carbon molecular fluorocarbon-based gas.
  • the high-carbon fluorocarbon-based gas can produce more fluorocarbon-containing polymer films, and the polymer films are deposited on the groove walls of the first barrier groove to form a protective film, thereby forming anisotropic etching on the functional layer.
  • the first barrier groove on the first functional layer may be formed in other ways, for example, by wet etching.
  • the second barrier groove on the second functional layer can be formed in other ways, for example, by dry etching, such as by HF gas dry etching of the second barrier layer.
  • FIG. 1 is a schematic diagram of an electronic device provided in the first embodiment of the present application.
  • FIG. 2 is a schematic diagram of a stacked structure of a power semiconductor device provided in the first embodiment of the present application
  • FIG. 3 is a flow chart of a method for manufacturing a power semiconductor device provided in the first embodiment of the present application
  • FIG. 4 is a schematic diagram of a stacked structure of a power semiconductor device provided in a second embodiment of the present application.
  • FIG. 5 is a flow chart of a method for manufacturing a power semiconductor device provided in the second embodiment of the present application.
  • FIG. 6 is a schematic structural diagram obtained in step 203 shown in FIG. 5;
  • FIG. 7 is a schematic structural diagram obtained in step 205 shown in FIG. 5;
  • FIG. 8 is a schematic diagram of a stacked structure of a power semiconductor device provided in a third embodiment of the present application.
  • FIG. 9 is a flowchart of a method for manufacturing a power semiconductor device provided in the third embodiment of the present application.
  • FIG. 10 is a schematic structural diagram obtained in step 303 shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram obtained in step 305 shown in FIG. 9;
  • FIG. 12 is a schematic diagram of a stacked structure of a power semiconductor device provided in a fourth embodiment of the present application.
  • FIG. 13 is a flow chart of a method for manufacturing a power semiconductor device provided in the fourth embodiment of the present application.
  • FIG. 14 is a schematic structural diagram obtained in step 403 shown in FIG. 13;
  • FIG. 15 is a schematic structural diagram obtained in step 404 shown in FIG. 14;
  • FIG. 16 is a schematic structural diagram obtained in step 405 shown in FIG. 14 .
  • SMT Surface-mount technology
  • a common power semiconductor device (such as a power supply, etc.) includes a passivation layer, a first metal part, a second metal part, and an insulating layer.
  • the first metal part and the second metal part are arranged on the passivation layer at intervals, and the insulating layer covers On the passivation layer, the first metal part and the second metal part, the insulating layer fills the space between the first metal part and the second metal part.
  • the electric field between the first metal part and the second metal part will penetrate through the delamination (due to the separation between the insulating layer and the passivation layer through which the first metal part penetrates).
  • the boss is provided on the passivation layer, but the metal of the first metal part and the second metal part will still bypass the boss of the passivation layer for metal migration, and the power semiconductor device can be used reliably. Sex is not high.
  • the present application provides a power semiconductor device and a related electronic device.
  • the power semiconductor device includes a functional layer, a first metal part, a second metal part, and an insulating layer.
  • the functional layer includes a first area, a second area, and a third area, and the third area is located between the first area and the between the second regions, the functional layer further includes a first barrier groove disposed on the third region, the first metal part is disposed on the first region, and the second metal part is disposed on the On the second area, the insulating layer includes a main body and a first barrier part connected to each other, the main body covers the first metal part, the second metal part and the third area, the first A blocking portion fills the blocking groove, and the functional layer further includes at least one passivation layer.
  • the power semiconductor device provided in this application can be applied in various electronic devices that need to use the power semiconductor device.
  • Power semiconductor devices are used for power conversion processing, including frequency conversion, voltage conversion, current conversion, power management and so on.
  • the electronic device may be an electrical energy conversion device requiring the use of power semiconductor devices.
  • the power conversion device can be mounted on the power conversion equipment to complete various power functions of the equipment.
  • the electronic device of the present application can be applied in the field of electric vehicle power system, that is, the electric energy conversion device can be an electric vehicle, wherein the electronic device can be a motor controller, and the power semiconductor device is a power conversion unit assembled in the motor controller;
  • the electronic device can also be an on-board charger (OBC), and the power semiconductor device can be an energy conversion unit;
  • the electronic device can also be a low-voltage control power supply, and the power semiconductor device can be a DC-DC conversion unit.
  • OBC on-board charger
  • the electronic device of the present application is not limited to the field of electric vehicles, and can also be widely used in the fields of traditional industrial control, communication, smart grid, electrical appliances, etc., for example, it can be applied to uninterruptible power supplies in data centers supply, UPS), inverters for photovoltaic power generation equipment, power supplies for servers, switching power supplies for electrical appliances (such as refrigerators), etc. It can be understood that this application does not limit electronic devices to power conversion devices, that is, this application does not limit power semiconductor devices to perform power conversion, and power semiconductor devices can also be used in electronic devices to change voltage, frequency, etc. to achieve circuit control functions.
  • UPS data centers supply
  • inverters for photovoltaic power generation equipment power supplies for servers
  • switching power supplies for electrical appliances such as refrigerators
  • this application does not limit electronic devices to power conversion devices, that is, this application does not limit power semiconductor devices to perform power conversion, and power semiconductor devices can also be used in electronic devices to change voltage, frequency, etc. to achieve circuit control functions.
  • the first embodiment of the present application provides an electronic device 100 , including a circuit board 10 and a power semiconductor device 30 on the circuit board 10 .
  • the circuit board 10 may be a network single board.
  • a control circuit (not shown) is provided on the circuit board 10 , and the control circuit is used to control the power semiconductor device 30 to be turned on and off.
  • the present application provides a power semiconductor device 30 , including a functional layer 31 , a first metal portion 33 , a second metal portion 35 and an insulating layer 37 .
  • the functional layer 31 includes a first area 301 , a second area 303 and a third area 305 .
  • the third area 305 is located between the first area 301 and the second area 303 .
  • the functional layer 31 also includes a first barrier groove 311 disposed in the third region 305 .
  • the first metal portion 33 covers the first region 301 .
  • the second metal portion 35 covers the second region 303 .
  • the insulating layer 37 includes a main body 371 and a first blocking portion 373 connected to each other.
  • the main body 371 covers the first metal part 33 , the second metal part 35 and the third region 305 .
  • the first blocking portion 373 fills the first blocking groove 311 .
  • the first blocking portion 373 is used to block metal migration between the first metal portion 33 and the second metal portion 35 , so as to reduce the possibility of a short circuit between the first metal portion 33 and the second metal portion 35 .
  • the power semiconductor device 30 may also include other necessary or unnecessary structures, such as a substrate, etc., which will not be described in detail here.
  • the insulating layer 37 is used for electrically isolating the first metal portion 33 and the second metal portion 35 .
  • the functional layer 31 is a passivation layer made of Si 3 N 4
  • the first metal portion 33 and the second metal portion 35 are a redistribution layer (RDL) made of Cu.
  • RDL redistribution layer
  • Passivation layers are usually used to protect the underlying electronic devices from being polluted by moisture, moisture and impurities, resulting in damage to the physical and electrical properties of the devices, and so on. It can be understood that, in other implementation manners, the first metal part 33 and the second metal part 35 can be made of other materials, such as Sn, Au, Al and so on.
  • the groove wall of the first blocking groove 311 includes a side wall 3114 and a bottom wall 3117 that are connected.
  • the first blocking portion 373 is attached to the side wall 3114 .
  • the first blocking portion 373 is not in contact with the first metal portion 33 and the second metal portion 35 .
  • the insulating layer 37 forms a first barrier part 373 in the first barrier groove 311, and the first barrier part 373 is not in contact with the first metal part 33 or the second metal part 35, which is equivalent to the insulating layer 37 forming a recess in the functional layer 31.
  • the first barrier part 373 reduces the possibility of delamination between the functional layer 31 and the insulating layer 37, effectively reduces the possibility of metal migration between the first metal part 33 and the second metal part 35, and reduces The possibility of short circuit between the first metal part 33 and the second metal part 35 is eliminated, thereby improving the reliability of the power semiconductor device 30 .
  • the metal in the first metal part 33 and the second metal part 35 is difficult The electric field grows in the opposite direction, thereby reducing the occurrence of penetrating metal migration.
  • the first embodiment also provides a method for manufacturing a power semiconductor device 30, including the following steps:
  • Step 101 provide a prefabricated structure, the prefabricated structure includes a functional layer 31, a first metal part 33 and a second metal part 35, the functional layer 31 includes a first area 301, a second area 303 and a third area 305, the third area 305 is located Between the first region 301 and the second region 303 , the first metal part 33 is disposed on the first region 301 , the second metal part 35 is disposed on the second region 303 , and the functional layer 31 further includes at least one passivation layer.
  • Step 103 forming a first barrier groove 311 on the third region 305 of the functional layer 31 .
  • Step 105 forming an insulating layer 37 .
  • the insulating layer 37 includes a main body 371 and a first blocking portion 373 connected to each other.
  • the main body 371 covers the first metal portion 33 , the second metal portion 35 and the third region 305 .
  • the first blocking portion 373 fills the first blocking groove 311 .
  • the second embodiment of the present application provides a power semiconductor device 30
  • the structure of the power semiconductor device 30 provided in the second embodiment is roughly similar to that of the power semiconductor device provided in the first embodiment, except that the functional layer 31 It also includes a second blocking groove 313 communicating with the first blocking groove 311.
  • the insulating layer 37 also includes a second blocking portion 375, which is fixedly connected to the end of the first blocking portion 373 away from the main body 371.
  • the first blocking portion 373 fills the first blocking groove 311
  • the second blocking portion 375 fills the second blocking groove 313 .
  • the power semiconductor device 30 includes a functional layer 31 , a first metal portion 33 , a second metal portion 35 and an insulating layer 37 .
  • the functional layer 31 includes a first area 301 , a second area 303 and a third area 305 .
  • the third area 305 is located between the first area 301 and the second area 303 .
  • the first blocking groove 311 is disposed on the third region 305 of the functional layer 31 .
  • the first metal portion 33 covers the first region 301 .
  • the second metal portion 35 covers the second region 303 .
  • the main body 371 covers the first metal part 33 , the second metal part 35 and the third region 305 .
  • the first blocking groove 311 includes a first port 3111 and a second port 3113 oppositely disposed along a direction parallel to the stacking direction of the first metal portion 33 and the functional layer 31 .
  • the first port 3111 is disposed on the side of the functional layer 31 closest to the first metal portion 33 .
  • the second blocking groove 313 communicates with the second port 3113, the diameter of the second port 3313 of the second blocking groove 313 close to the first blocking groove 311 is larger than the diameter of the second port 3113, and the insulating layer 37 also includes a second blocking portion 375, The second blocking portion 375 fills the second blocking groove 313 .
  • the second barrier part 375 embedded in the second barrier groove 313 increases the interface length between the functional layer 31 and the insulating layer 37, that is, increases the metal migration path between the first metal part 33 and the second metal part 35, further The possibility of a short circuit between the first metal part 33 and the second metal part 35 is reduced.
  • the diameter of the second port 3313 of the second barrier groove 313 close to the first barrier groove 311 is larger than the diameter of the second port 3113, which improves the connection stability between the functional layer 31 and the insulating layer 37, and further reduces the connection between the functional layer 31 and the insulating layer.
  • the possibility of delamination between the layers 37 is further reduced, and the possibility of metal migration between the first metal part 33 and the second metal part 35 is further reduced.
  • the cross section of the first blocking groove 311 is approximately rectangular, and the cross section of the second blocking groove 313 is approximately partially circular. It can be understood that the present application does not limit the cross-sectional shape of the first blocking groove 311 , and the present application makes no limitation on the cross-sectional shape of the second blocking groove 313 .
  • the second embodiment also provides a method for manufacturing a power semiconductor device 30, including the following steps:
  • Step 201 providing a prefabricated structure.
  • the prefabricated structure includes a functional layer 31 , a first metal part 33 and a second metal part 35 .
  • the functional layer 31 includes a first area 301 , a second area 303 and a third area 305 .
  • the third area 305 is located between the first area 301 and the second area 303 .
  • the first metal part 33 covers the first area 301
  • the second metal part 35 covers the second area 303 .
  • a first barrier groove 311 is formed on the third region 305 of the functional layer 31 and a protective film 40 is formed on a sidewall of the first barrier groove 311 .
  • the first blocking groove 311 includes a first port 3111 and a second port 3113 oppositely disposed along a direction parallel to the stacking direction of the first metal portion 33 and the functional layer 31 .
  • the first port 3111 is disposed on the side of the functional layer 31 closest to the first metal portion 33 .
  • the functional layer 31 is a passivation layer made of Si 3 N 4 .
  • a prefabricated structure (sample wafer) with a preset pattern that can be developed by photolithography is put into the etching chamber.
  • Use dry etching to mask the dielectric film process inject the first gas into the etching chamber to etch the functional layer 31, so that the first barrier groove 311 is formed on the functional layer 31 and formed on the side wall of the first barrier groove 311 protective film 40 .
  • the first gas includes high-carbon fluorocarbon (for example, C 4 F 6 or C 4 F 8 ) gas and diluent gas.
  • the high-carbon molecular fluorocarbon-based gas can produce more fluorocarbon-containing polymer films, and these polymer films are deposited on the groove wall of the first barrier groove 311 to form a protective film 40, thereby forming an anisotropic layer 40 on the functional layer 37.
  • Diluent gases include He or Ar.
  • Dry etching masking dielectric film is an important process technology in the manufacture of semiconductor devices.
  • a certain amount of reaction gas is introduced in a vacuum state, and plasma is formed under the action of radio frequency electric field to etch the masking dielectric film of semiconductor material, and the obtained required masking profile.
  • Step 205 as shown in FIG. 7 , forming a second blocking groove 313 communicating with the first blocking groove 311 on the functional layer 31 .
  • the second blocking groove 313 communicates with the second port 3113 .
  • the diameter of the end of the second blocking groove 313 close to the first blocking groove 311 is larger than the diameter of the first port 3111 .
  • the dielectric film is masked by dry etching, and the second gas is injected into the etching chamber to etch the functional layer 31 , so that the second barrier groove 313 communicating with the second port 3113 is formed on the functional layer 31 .
  • the second gas includes a hydrofluorocarbon-based gas, and the hydrofluorocarbon-based gas includes one of CHF 3 , CH 2 F 2 , and CH 3 F.
  • the second gas is used to chemically etch the functional layer 31 to enhance the etching process.
  • the etching rate is increased, and the manufacturing efficiency of the power semiconductor device 30 is accelerated.
  • the etched prefabricated structure is cleaned to remove residual substances on the prefabricated structure, for example, the protective film 40 and the like.
  • Step 207 forming an insulating layer 37 .
  • the insulating layer 37 includes a main body 371, a first blocking portion 373 and a second blocking portion 375 which are connected.
  • the main body 371 covers the first metal portion 33, the second metal portion 35 and the third region 305, and the first blocking portion 373 fills The first blocking groove 311 and the second blocking portion 375 fill the second blocking groove 313 .
  • the third embodiment of the present application provides a power semiconductor device 30
  • the structure of the power semiconductor device 30 provided by the third embodiment is roughly similar to that of the power semiconductor device provided by the second embodiment, except that the functional layer 31 It also includes a stacked first functional layer 315 and a second functional layer 317.
  • the material of the first functional layer 315 is different from the material of the second functional layer 317.
  • the first metal part 33 and the second metal part 35 are arranged on the first functional layer.
  • the first barrier groove 311 runs through the first functional layer 315
  • the second barrier groove 313 is located in the second functional layer 317 .
  • the first functional layer 315 is a passivation layer made of Si 3 N 4
  • the second functional layer 317 is a passivation layer made of SiO 2 .
  • Passivation layers made of different materials can reduce the stress of adjacent passivation layers and prolong the service life of the power semiconductor device 30 .
  • the cross section of the first blocking groove 311 is roughly rectangular, and the cross section of the second blocking groove 313 is roughly trapezoidal. It can be understood that the present application does not limit the cross-sectional shape of the first blocking groove 311 , and the present application makes no limitation on the cross-sectional shape of the second blocking groove 313 .
  • the third embodiment also provides a method for manufacturing a power semiconductor device 30, including the following steps:
  • Step 301 providing a prefabricated structure.
  • the prefabricated structure includes a functional layer 31 , a first metal part 33 and a second metal part 35 .
  • the functional layer 31 includes a first area 301 , a second area 303 and a third area 305 .
  • the third area 305 is located between the first area 301 and the second area 303 .
  • the first metal part 33 covers the first area 301
  • the second metal part 35 covers the second area 303 .
  • the functional layer 31 further includes a first functional layer 315 and a second functional layer 317 which are stacked.
  • the first metal part 33 is disposed on the first functional layer 315 of the first region 301 and the second metal part 35 is disposed on the first functional layer 315 of the second region 303 .
  • the material of the first functional layer 315 is different from that of the second functional layer 317
  • the first metal part 33 and the second metal part 35 are disposed on the side of the first functional layer 315 away from the second functional layer 317 .
  • the first functional layer 315 is a passivation layer made of Si 3 N 4
  • the second functional layer 317 is a passivation layer made of SiO 2 .
  • Step 303 as shown in FIG. 10 , forming a first barrier groove 311 on the first functional layer 315 in the third region 305 .
  • the first blocking groove 311 includes a first port 3111 and a second port 3113 oppositely disposed along a direction parallel to the stacking direction of the first metal portion 33 and the functional layer 31 .
  • the first port 3111 is disposed on a side of the first functional layer 315 closest to the first metal portion 33 .
  • the prefabricated structure (sample wafer) with a preset pattern developed by photolithography is put into the etching chamber, and the dielectric film is masked by dry etching, and the first gas or the second gas is injected into the etching chamber.
  • the gas etches the functional layer 31 to form a first barrier groove 311 on the first functional layer 315 .
  • the first gas includes high-carbon fluorocarbon (for example, C 4 F 6 or C 4 F 8 ) gas and diluent gas.
  • the second gas includes a hydrofluorocarbon-based gas, and the hydrofluorocarbon-based gas includes one of CHF 3 , CH 2 F 2 , and CH 3 F.
  • Step 305 as shown in FIG. 11 , forming a second barrier groove 313 communicating with the first barrier groove 311 on the second functional layer 317 .
  • the diameter of the end of the second blocking groove 313 close to the first blocking groove 311 is larger than the diameter of the second port 3113 .
  • wet etching is used to form the second barrier groove 313 in communication with the first barrier groove 311 in the second functional layer 317, and the etching solution for wet etching may be KOH solution.
  • the prefabricated structure is cleaned with deionized water, ethanol, acetone, ether, etc. in sequence. After cleaning, the prefabricated structure is spin-dried.
  • the etching solution may be other solutions, and the etching solution includes 49% HF and 12% NH 4 F.
  • Step 307 forming an insulating layer 37 .
  • the insulating layer 37 is covered on the first metal portion 33 , the second metal portion 35 and the third region 305 , thereby forming the power semiconductor device 30 .
  • the insulating layer 37 includes a main body 371, a first blocking portion 373 and a second blocking portion 375 which are connected.
  • the main body 371 covers the first metal portion 33, the second metal portion 35 and the third region 305, and the first blocking portion 373 fills The first blocking groove 311 and the second blocking portion 375 fill the second blocking groove 313 .
  • the present application does not limit the material of the passivation layer.
  • the first functional layer 315 can be a passivation layer made of SiO 2
  • the second functional layer 317 can be made of Si 3 N 4 formed passivation layer.
  • the fourth embodiment of the present application provides a power semiconductor device 30
  • the structure of the power semiconductor device 30 provided by the fourth embodiment is roughly similar to that of the power semiconductor device provided by the second embodiment, except that the functional layer 31 It also includes a stacked first functional layer 315 and a second functional layer 317.
  • the material of the first functional layer 315 is different from the material of the second functional layer 317.
  • the first metal part 33 and the second metal part 35 are arranged on the first functional layer.
  • the first barrier groove 311 is located in the first functional layer 315
  • the second barrier groove 313 is located in the first functional layer 315
  • the first functional layer 315 is a Si layer
  • the second functional layer Layer 317 is a passivation layer made of Si 3 N 4 .
  • the Si layer is used to protect the passivation layer, and disposing the first blocking groove 311 and the second blocking groove 313 on the Si layer will not damage the structure of the passivation layer, and will not affect the function of the passivation layer.
  • the cross section of the first blocking groove 311 is roughly rectangular, and the cross section of the second blocking groove 313 is roughly trapezoidal. It can be understood that the present application does not limit the cross-sectional shape of the first blocking groove 311 , and the present application makes no limitation on the cross-sectional shape of the second blocking groove 313 .
  • the fourth embodiment also provides a method for manufacturing a power semiconductor device 30, including the following steps:
  • Step 401 providing a prefabricated structure.
  • the prefabricated structure includes a functional layer 31, a first metal part 33, and a second metal part 35.
  • the functional layer 31 includes a first area 301, a second area 303, and a third area 305.
  • the third area 305 is located at Between the first area 301 and the second area 303 , the first metal part 33 covers the first area 301 , and the second metal part 35 covers the second area 303 .
  • the functional layer 31 also includes a stacked first functional layer 315 and a second functional layer 317, the material of the first functional layer 315 is different from the material of the second functional layer 317, the first metal part 33 and the second metal part 35 are arranged on The side of the first functional layer 315 facing away from the second functional layer 317 .
  • Step 403 forming a first barrier groove 311 on the first functional layer 315 in the third region 305 .
  • the first blocking groove 311 includes a first port 3111 and a second port 3113 oppositely disposed along a direction parallel to the stacking direction of the first metal portion 33 and the functional layer 31 .
  • the first port 3111 is disposed on the side of the functional layer 31 closest to the first metal portion 33 .
  • the prefabricated structure (sample wafer) with a preset pattern developed by photolithography is put into the etching chamber, and the third gas is introduced into the etching chamber, and the process of masking the dielectric film by dry etching is used to
  • the first functional layer 315 is etched to form a first barrier groove 311 on the first functional layer 315 .
  • the third gas includes SF 6 .
  • Step 404 deposits and forms a protective film 40 on the groove wall of the first barrier groove 311 .
  • the protective film 40 is used to protect the groove walls of the first blocking groove 311 .
  • the first gas is introduced into the etching chamber, and the protective film 40 is deposited and formed on the groove wall of the first barrier groove 311 by using a dry etching masking dielectric film process.
  • the first gas includes C 4 F 8 .
  • Step 405 as shown in FIG. 16 , forming a second barrier groove 313 on the first functional layer 315 .
  • the second blocking groove 313 communicates with the second port 3113 .
  • the diameter of the second port 3113 of the second blocking groove 313 close to the first blocking groove 311 is larger than the diameter of the first port 3111 .
  • a third gas is introduced into the etching chamber, and the first functional layer 315 is isotropically etched by a dry etching masking dielectric film process to form the second barrier groove 313 .
  • Step 407 as shown in FIG. 12 , forming an insulating layer 37 .
  • the insulating layer 37 covers the first metal part 33 , the second metal part 35 and the third region 305 to form the power semiconductor device 30 .
  • the insulating layer 37 includes a main body 371, a first blocking portion 373 and a second blocking portion 375 which are connected.
  • the main body 371 covers the first metal portion 33, the second metal portion 35 and the third region 305, and the first blocking portion 373 fills The first blocking groove 311 and the second blocking portion 375 fill the second blocking groove 313 .
  • step 404 may be omitted.
  • the expression “and/or” includes any and all combinations of the associated listed words.
  • the expression “A and/or B” may include A, may include B, or may include both A and B.
  • expressions including ordinal numbers such as "first” and “second” may modify each element.
  • elements are not limited by the above expressions.
  • the above expressions do not limit the order and/or importance of elements.
  • the above expressions are only used to distinguish one element from other elements.
  • the first user equipment and the second user equipment indicate different user equipments, although both the first user equipment and the second user equipment are user equipments.
  • a first element could be termed a second element
  • a second element could be termed a first element, without departing from the scope of the present application.

Abstract

本申请提供一种功率半导体器件及其制备方法、电子装置。功率半导体器件包括功能层、第一金属部、第二金属部及绝缘层，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述功能层还包括设置在所述第三区域的第一阻挡槽，所述第一金属部设置在所述第一区域上，所述第二金属部设置在所述第二区域上，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体覆盖于所述第一金属部、所述第二金属部及所述第三区域上，所述第一阻挡部填充所述第一阻挡槽，所述功能层还包括至少一个钝化层。

Description

功率半导体器件及其制备方法、电子装置
本申请要求在2021年9月30日提交中国国家知识产权局、申请号为202111164572.X、申请名称为“功率半导体器件及其制备方法、电子装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别涉及一种功率半导体器件及其制备方法、电子装置。
背景技术
一种功率半导体器件(例如电源等)结构中，包括钝化层、第一金属部、第二金属部及绝缘层，第一金属部与第二金属部间隔设置于钝化层上，绝缘层覆盖于钝化层、第一金属部、第二金属部上，绝缘层填充第一金属部与第二金属部之间。然而，绝缘层与钝化层分层后，在第一金属部与第二金属部之间的电场、贯穿分层(第一金属部所贯穿的绝缘层与钝化层之间因分层形成的空间或间隙)和离子(例如水汽中产生的一些离子)浓度的作用下，第一金属部与第二金属部之间会发生金属迁移(又称电迁移)，容易导致第一金属部与第二金属部之间短路，造成功率半导体器件损坏的后果。如此，影响功率半导体器件的可靠性。
发明内容
本申请实施例提供了一种能够提高可靠性的功率半导体器件及其制备方法、电子装置。
第一方面，本申请提供一种功率半导体器件，包括功能层、第一金属部、第二金属部及绝缘层，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述功能层还包括设置在所述第三区域的第一阻挡槽，所述第一金属部覆盖于所述第一区域上，所述第二金属部设置在所述第二区域上，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体设置在所述第一金属部、所述第二金属部及所述第三区域上，所述第一阻挡部填充所述第一阻挡槽，所述功能层还包括至少一个钝化层。
绝缘层在第一阻挡槽内形成第一阻挡部，第一阻挡部未与第一金属部或第二金属部接触，相当于绝缘层在功能层内形成了凹嵌式结构，第一阻挡部降低了功能层与绝缘层之间分层的可能性，有效降低了第一金属部与第二金属部之间金属迁移产生的可能性，降低了第一金属部与第二金属部之间短路的可能性，从而提高了功率半导体器件的可靠性。另外，即使功能层与绝缘层之间发生了分层的现象，第一金属部与第二金属部中的金属难以沿着与第一金属部与第二金属部之间产生的电场相反方向进行生长，从而降低了贯穿性金属迁移的发生。
根据第一方面，在第一方面的第一种可能的实现方式中，所述第一阻挡槽包括第一端口与第二端口，所述第一端口设于所述功能层最靠近所述第一金属部的一面，所述功能层还包括第二阻挡槽，所述第二阻挡槽与所述第二端口连通，所述绝缘层还包括第二阻挡部，所述第二阻挡部与所述第一阻挡部远离所述主体的一端固定连接，所述第二阻挡部填充所述第二阻挡槽。
嵌入第二阻挡槽内的第二阻挡部，增加了功能层与绝缘层之间界面长度，即增加了第一金属部与第二金属部之间金属迁移的路径，进一步降低了第一金属部与第二金属部短路的可能性。
根据第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述第二阻挡槽靠近所述第一阻挡槽的一端的口径要大于所述第二端口的口径，提高 了功能层与绝缘层之间的连接稳定性，进一步降低功能层与绝缘层之间分层的可能性，以及进一步降低第一金属部与第二金属部之间金属迁移产生的可能性。
根据第一方面或第一方面的第一种至第二种可能的实现方式，在第一方面的第三种可能的实现方式中，所述功能层还包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一金属部与所述第二金属部设于所述第一功能层背离所述第二功能层的一侧,所述第一阻挡槽位于所述第一功能层，所述第二阻挡槽位于所述第一功能层及/或所述第二功能层，所述第一功能层与所述第二功能层中的至少一个为钝化层。
根据第一方面或第一方面的第一种至第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述第一功能层与所述第二功能层中的一个为Si 3N 4制成的钝化层，所述第一功能层与所述第二功能层中的另一个为SiO 2制成的钝化层，所述第二阻挡槽位于所述第二功能层。不同材质的钝化层，可以减小相邻的钝化层的应力，延长功率半导体器件的使用寿命。
根据第一方面或第一方面的第一种至第四种可能的实现方式，在第一方面的第五种可能的实现方式中，所述第一功能层为Si层，所述第二功能层为钝化层，所述第二阻挡槽位于所述第一功能层。Si层用于保护钝化层，将第一阻挡槽与第二阻挡槽均设于Si层上不会破坏钝化层的结构，进而不会影响钝化层的功能。
第二方面，本申请提供一种电子装置，包括电路板及设于所述电路板上的根据第一方面或第一方面的第一种至第四种可能的实现方式所述的功率半导体器件，所述电路板上设有控制电路，所述控制电路用于控制所述功率半导体器件的导通和关断。
第三方面，本申请提供一种功率半导体器件的制备方法，包括以下步骤，提供预制结构，所述功能层、第一金属部及第二金属部，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述第一金属部设置在所述第一区域上，所述第二金属部设置在所述第二区域上，所述功能层还包括至少一个钝化层；在所述功能层的第三区域上形成第一阻挡槽；形成绝缘层，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体覆盖于所述第一金属部、所述第二金属部及所述第三区域上，所述第一阻挡部填充所述第一阻挡槽。
在功能层的第三区域上形成第一阻挡槽，绝缘层在功能层内形成了凹嵌式结构的第一阻挡部，第一阻挡部能够降低功能层与绝缘层之间分层的可能性，有效降低了第一金属部与第二金属部之间金属迁移产生的可能性，降低了第一金属部与第二金属部之间短路的可能性，从而提高了功率半导体器件的可靠性。另外，即使功能层与绝缘层之间发生了分层的现象，第一金属部与第二金属部中的金属难以沿着与第一金属部与第二金属部之间产生的电场相反方向进行生长，从而降低了贯穿性金属迁移的发生。
根据第三方面，在第三方面的第一种可能的实现方式中，在所述形成绝缘层之前，所述制备方法还包括步骤，在所述功能层上形成与第一阻挡槽连通的第二阻挡槽，所述第一阻挡槽包括第一端口与第二端口，所述第一端口设于所述功能层最靠近所述第一金属部的一面，所述第二阻挡槽与所述第二端口连通；所述绝缘层还包括第二阻挡部，所述形成绝缘层，还包括，所述第二阻挡部填充所述第二阻挡槽。
嵌入第二阻挡槽内的第二阻挡部，增加了功能层与绝缘层之间界面长度，即增加了第一金属部与第二金属部之间金属迁移的路径，进一步降低了第一金属部与第二金属部短路的可 能性。
根据第三方面或第三方面的第一种可能的实现方式，在第三方面的第二种可能的实现方式中，所述功能层为单个钝化层，所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第一气体对功能层进行刻蚀，使所述功能层上形成第一阻挡槽并于所述第一阻挡槽的侧壁上形成保护膜，所述第一气体包括高碳分子碳氟基气体；所述在所述功能层上形成第二阻挡槽，包括，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第二气体对所述功能层进行刻蚀，使所述功能层上形成与所述第二端口连通的第二阻挡槽，所述第二气体包括氢碳氟基气体。
功能层为单个钝化层结构，简化了功率半导体器件的结构，简化了功率半导体器件的制备。另外，利用干法刻蚀掩蔽介质膜，向刻蚀腔体注入第一气体对功能层进行刻蚀时，第一气体包括高碳分子碳氟基气体，高碳分子碳氟基气体能产生较多的含碳氟的聚合物薄膜，该等聚合物薄膜沉积在第一阻挡槽的槽壁形成保护膜，从而对功能层形成各向异性的刻蚀。利用干法刻蚀掩蔽介质膜，向刻蚀腔体注入第二气体对功能层进行刻蚀，第二气体包括氢碳氟基气体，氢碳氟基气体对功能层进行化学性刻蚀，以提升刻蚀速率，加快功率半导体器件的制备效率。
根据第三方面或第三方面的第一种至第二种可能的实现方式，在第三方面的第三种可能的实现方式中，所述功能层包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一功能层为Si 3N 4制成的钝化层，所述第二功能层为SiO 2制成的钝化层；在所述第一区域的第一功能层设置所述第一金属部及在所述第二区域的第一功能层上设置所述第二金属部；所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第一气体或第二气体对功能层进行刻蚀，使所述第一功能层上形成所述第一阻挡槽，所述第一气体包括高碳分子碳氟基气体，所述第二气体包括氢碳氟基气体；所述在所述功能层上形成第二阻挡槽，包括，采用湿法刻蚀，在所述第二功能层上形成所述第二阻挡槽。
根据第三方面或第三方面的第一种至第三种可能的实现方式，在第三方面的第四种可能的实现方式中，所述功能层包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一功能层为Si层，所述第二功能层为钝化层；在所述第一区域的第一功能层设置所述第一金属部及在所述第二区域的第一功能层上设置所述第二金属部；所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第三气体对所述第一功能层进行刻蚀，使所述第一功能层上形成所述第一阻挡槽，所述第三气体包括SF 6；所述在所述功能层上形成第二阻挡槽，包括，采用干法刻蚀掩蔽介质膜工艺，向所述刻蚀腔体通入第三气体对所述第一功能层进行各向同性刻蚀，使所述第二功能层形成所述第二阻挡槽。Si层用于保护钝化层。
根据第三方面或第三方面的第一种至第四种可能的实现方式，在第三方面的第五种可能的实现方式中，所述在功能层上形成第一阻挡槽后，所述在所述功能层上形成第二阻挡槽前，所述制备方法还包括步骤，向刻蚀腔体通入第一气体，利用干法刻蚀掩蔽介质膜工艺在第一阻挡槽的槽壁上沉积形成保护膜，所述第一气体包括高碳分子碳氟基气体。
高碳分子碳氟基气体能产生较多的含碳氟的聚合物薄膜，该等聚合物薄膜沉积在第一阻挡槽的槽壁形成保护膜，从而对功能层形成各向异性的刻蚀。
在其他实现方式中，第一功能层上的第一阻挡槽可以通过其他方式形成，例如，通过湿法刻蚀。第二功能层上的第二阻挡槽可以通过其他方式形成，例如，通过干法刻蚀，例如通 过HF气体干法刻蚀第二阻挡层。
附图说明
图1为本申请第一实施方式提供的电子装置的示意图；
图2为本申请第一实施方式提供的功率半导体器件的叠层结构示意图；
图3为本申请第一实施方式提供的功率半导体器件的制备方法的流程图；
图4为本申请第二实施方式提供的功率半导体器件的叠层结构示意图；
图5为本申请第二实施方式提供的功率半导体器件的制备方法的流程图；
图6为图5所示的步骤203所得到的结构示意图；
图7为图5所示的步骤205所得到的结构示意图；
图8为本申请第三实施方式提供的功率半导体器件的叠层结构示意图；
图9为本申请第三实施方式提供的功率半导体器件的制备方法的流程图；
图10为图9所示的步骤303所得到的结构示意图；
图11为图9所示的步骤305所得到的结构示意图；
图12为本申请第四实施方式提供的功率半导体器件的叠层结构示意图；
图13为本申请第四实施方式提供的功率半导体器件的制备方法的流程图；
图14为图13所示的步骤403所得到的结构示意图；
图15为图14所示的步骤404所得到的结构示意图；
图16为图14所示的步骤405所得到的结构示意图。
具体实施方式
表面贴装技术(surface-mount technology，SMT)是目前电子组装行业里最流行的一种技术和工艺。自70年代初推向市场以来，SMT已逐渐替代传统“人工插件”的波焊组装方式，成为现代电子组装产业的主流。SMT技术推动和促进了电子元器件向片式化、小型化、薄型化、轻量化、高可靠、多功能方向发展。
一种常见的功率半导体器件(例如电源等)包括钝化层、第一金属部、第二金属部及绝缘层，第一金属部与第二金属部间隔设置于钝化层上，绝缘层覆盖于钝化层、第一金属部、第二金属部上，绝缘层填充第一金属部与第二金属部之间。然而，绝缘层与钝化层发生分层现象后，在第一金属部与第二金属部之间的电场、贯穿分层(第一金属部所贯穿的绝缘层与钝化层之间因分层形成的空间或间隙)和离子浓度(例如水汽中产生的一些离子)的作用下，第一金属部与第二金属部之间会发生金属迁移，容易导致第一金属部与第二金属部之间短路，例如，将该等功率半导体器件通过SMT二级封装的形式焊接在电路板(printed circuit board，PCB)上为单板进行供电时，若第一金属部与第二金属部之间短路则会产生大量热量，容易对电路板造成损伤，严重时会“烧板”。如此，影响功率半导体器件及其相关装置的使用可靠性。
在另一种功率半导体器件中，其通过在钝化层设置凸台，但是第一金属部与第二金属部的金属依然会绕过钝化层的凸台进行金属迁移，功率半导体器件使用可靠性不高。
基于此，本申请提供一种功率半导体器件及其相关的电子装置。功率半导体器件包括功能层、第一金属部、第二金属部及绝缘层，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述功能层还包括设置在所述第三区域的第一阻挡槽，所述第一金属部设置在所述第一区域上，所述第二金属部设置在所述第二区域上，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体覆盖于所述第一金属部、 所述第二金属部及所述第三区域上，所述第一阻挡部填充所述阻挡槽，所述功能层还包括至少一个钝化层。
本申请提供的功率半导体器件可以应用在各种需要采用功率半导体器件的电子装置中。功率半导体器件用于进行功率变换处理，包括变频、变压、变流、功率管理等等。电子装置可以是需要采用功率半导体器件的电能转换装置。而电能转换装置又可以搭载在电能转换设备上以完成设备的各类电力功能。例如，本申请的电子装置可以应用在电动汽车动力系统领域，即电能转换设备可以为电动车，其中，电子装置可以为电机控制器，功率半导体器件为装配在电机控制器中的动力转换单元；电子装置也可以为车载充电器(on-board charger，OBC)，功率半导体器件为能量转换单元；电子装置还可以为低压控制电源，功率半导体器件为其中的DC-DC转换单元等等。除此之外，本申请的电子装置也不限于电动汽车领域，也可以广泛地应用在传统工业控制、通信、智能电网、电器等领域，例如，可以应用于数据中心的不间断电源(uninterruptible power supply,UPS)、光伏发电设备的逆变器、服务器的电源、电器(例如冰箱)的开关电源等等。可以理解，本申请不限定电子装置为电能转换装置，即本申请不限定功率半导体器件进行电能转换，功率半导体器件也可以在电子装置中用于改变电压、频率等以实现电路控制功能。
下面将结合具体实施方式及附图对本申请作进一步地详细描述。
请参阅图1，本申请第一实施方式提供一种电子装置100，包括电路板10及位于电路板10上的功率半导体器件30。本实施方式中，电路板10可以为网络单板。例如，电路板10上设有控制电路(图未示)，控制电路用于控制功率半导体器件30的导通和关断。
请参阅图2，本申请提供一种功率半导体器件30，包括功能层31、第一金属部33、第二金属部35及绝缘层37。功能层31包括第一区域301、第二区域303及第三区域305。第三区域305位于第一区域301与第二区域303之间。功能层31还包括设置在第三区域305的第一阻挡槽311。第一金属部33覆盖于第一区域301上。第二金属部35覆盖于第二区域303上。绝缘层37包括连接设置的主体371及第一阻挡部373。主体371覆盖于第一金属部33、第二金属部35及第三区域305上。第一阻挡部373填充第一阻挡槽311。第一阻挡部373用于阻挡第一金属部33与第二金属部35之间的金属迁移，以降低第一金属部33与第二金属部35之间短路的可能性。功率半导体器件30还可以包括其他必要或非必要结构，例如，衬底等，在此不作赘述。
绝缘层37用于对第一金属部33与第二金属部35进行电性隔离。本实施方式中，功能层31为由Si 3N 4制成的钝化层，第一金属部33与第二金属部35由Cu制成的重新布线层(redistribution layer,RDL)。钝化层通常被利用来保护其下的电子器件，防止它们受到水分湿气和杂质的污染，而导致器件的物理性能和电学性能被破坏等等。可以理解，在其他实施方式中，第一金属部33与第二金属部35可以由其他材料制成，例如、Sn、Au、Al等。
本实施方式中，第一阻挡槽311的槽壁包括连接设置的侧壁3114及底壁3117。第一阻挡部373贴附于侧壁3114上。第一阻挡部373未与第一金属部33及第二金属部35接触。
绝缘层37在第一阻挡槽311内形成第一阻挡部373，第一阻挡部373未与第一金属部33或第二金属部35接触，相当于绝缘层37在功能层31内形成了凹嵌式结构，第一阻挡部373降低了功能层31与绝缘层37之间分层的可能性，有效降低了第一金属部33与第二金属部35之间金属迁移产生的可能性，降低了第一金属部33与第二金属部35之间短路的可能性，从而提高了功率半导体器件30的可靠性。另外，即使功能层31与绝缘层37之间发生了分层的现象，第一金属部33与第二金属部35中的金属难以沿着与第一金属部33与第二金属部 35之间电场相反方向进行生长，从而降低了贯穿性金属迁移的发生。
请结合参阅图3，第一实施方式还提供一种功率半导体器件30的制备方法，包括以下步骤：
步骤101，提供预制结构，预制结构包括功能层31、第一金属部33及第二金属部35，功能层31包括第一区域301、第二区域303及第三区域305，第三区域305位于第一区域301与第二区域303之间，第一金属部33设置在第一区域301上，第二金属部35设置在第二区域303上，功能层31还包括至少一个钝化层。
步骤103，在功能层31的第三区域305上形成第一阻挡槽311。
步骤105，形成绝缘层37。绝缘层37包括连接设置的主体371与第一阻挡部373，主体371覆盖于第一金属部33、第二金属部35及第三区域305上，第一阻挡部373填充第一阻挡槽311。
请参阅图4，本申请第二实施方式提供一种功率半导体器件30，第二实施方式提供的功率半导体器件30与第一实施方式提供的功率半导体器件的结构大致相似，不同在于，功能层31还包括与第一阻挡槽311连通的第二阻挡槽313，绝缘层37还包括第二阻挡部375，第二阻挡部375与第一阻挡部373远离主体371的一端固定连接，第一阻挡部373填充第一阻挡槽311，第二阻挡部375填充于第二阻挡槽313。
较为具体的，功率半导体器件30包括功能层31、第一金属部33、第二金属部35及绝缘层37。功能层31包括第一区域301、第二区域303及第三区域305。第三区域305位于第一区域301与第二区域303之间。第一阻挡槽311设置在功能层31的第三区域305。第一金属部33覆盖于第一区域301上。第二金属部35覆盖于第二区域303上。主体371覆盖于第一金属部33、第二金属部35及第三区域305上。
第一阻挡槽311包括沿平行于第一金属部33与功能层31层叠方向而相对设置的第一端口3111与第二端口3113。第一端口3111设于功能层31最靠近第一金属部33的一面。
第二阻挡槽313与第二端口3113连通，第二阻挡槽313靠近第一阻挡槽311的第二端口3313的口径要大于第二端口3113的口径，绝缘层37还包括第二阻挡部375，第二阻挡部375填充第二阻挡槽313。嵌入第二阻挡槽313内的第二阻挡部375，增加了功能层31与绝缘层37之间界面长度，即增加了第一金属部33与第二金属部35之间金属迁移的路径，进一步降低了第一金属部33与第二金属部35短路的可能性。第二阻挡槽313靠近第一阻挡槽311的第二端口3313的口径要大于第二端口3113的口径，提高了功能层31与绝缘层37之间的连接稳定性，进一步降低功能层31与绝缘层37之间分层的可能性，以及进一步降低第一金属部33与第二金属部35之间金属迁移产生的可能性。
本实施方式中，第一阻挡槽311的截面大致呈矩形，第二阻挡槽313的截面大致为部分圆形。可以理解，本申请对第一阻挡槽311的截面形状不作限定，本申请对第二阻挡槽313的截面不作限定。
请结合参阅图5，第二实施方式还提供一种功率半导体器件30的制备方法，包括以下步骤：
步骤201，提供预制结构。预制结构包括功能层31、第一金属部33及第二金属部35。功能层31包括第一区域301、第二区域303及第三区域305。第三区域305位于第一区域301与第二区域303之间。第一金属部33覆盖于第一区域301上，第二金属部35覆盖于第二区域303上。
步骤203，如图6所示，在功能层31的第三区域305上形成第一阻挡槽311并在第一阻挡槽311的侧壁上形成保护膜40。
请结合参阅图4，第一阻挡槽311包括沿平行于第一金属部33与功能层31层叠方向而相对设置的第一端口3111与第二端口3113。第一端口3111设于功能层31最靠近第一金属部33的一面。
本实施方式中，功能层31为Si 3N 4制成的钝化层。将带有可通过光刻显影出预设图形的预制结构(样品晶片)放入刻蚀腔体。采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第一气体对功能层31进行刻蚀，使功能层31上形成第一阻挡槽311并于第一阻挡槽311的侧壁上形成保护膜40。第一气体包括高碳分子碳氟基(例如C 4F 6或C 4F 8)气体、稀释性气体。高碳分子碳氟基气体能产生较多的含碳氟的聚合物薄膜，该等聚合物薄膜沉积在第一阻挡槽311的槽壁形成保护膜40，从而对功能层37形成各向异性的刻蚀。稀释性气体包括He或Ar。
干法刻蚀掩蔽介质膜是半导体器件制作中的一种重要工艺技术，在真空状态下通入一定量的反应气体，在射频电场作用下形成等离子体对半导体材料掩蔽介质膜进行刻蚀，得到所需要的掩蔽外形结构。
步骤205，如图7所示，在功能层31上形成与第一阻挡槽311连通的第二阻挡槽313。第二阻挡槽313与第二端口3113连通。第二阻挡槽313靠近第一阻挡槽311的一端的口径要大于第一端口3111的口径。本实施方式中，利用干法刻蚀掩蔽介质膜，向刻蚀腔体注入第二气体对功能层31进行刻蚀，使功能层31上形成与第二端口3113连通的第二阻挡槽313。第二气体包括氢碳氟基气体，氢碳氟基气体包括CHF 3、CH 2F 2、CH 3F中的一种，第二气体用于对功能层31进行化学性刻蚀，以提升刻蚀速率，加快功率半导体器件30的制备效率。对完成刻蚀的预制结构进行清洗，去除预制结构上的残留物质，例如，保护膜40等。
步骤207，如图4所示，形成绝缘层37。绝缘层37包括连接设置的主体371、第一阻挡部373及第二阻挡部375，主体371覆盖于第一金属部33、第二金属部35及第三区域305上，第一阻挡部373填充第一阻挡槽311，第二阻挡部375填充第二阻挡槽313。
请参阅图8，本申请第三实施方式提供一种功率半导体器件30，第三实施方式提供的功率半导体器件30与第二实施方式提供的功率半导体器件的结构大致相似，不同在于，功能层31还包括层叠设置的第一功能层315与第二功能层317，第一功能层315的材质不同于第二功能层317的材质，第一金属部33与第二金属部35设于第一功能层315背离第二功能层317的一侧,第一阻挡槽311贯穿第一功能层315，第二阻挡槽313位于第二功能层317。
其中，第一功能层315为Si 3N 4制成的钝化层，第二功能层317为SiO 2制成的钝化层。不同材质的钝化层，可以减小相邻的钝化层的应力，延长功率半导体器件30的使用寿命。
本实施方式中，第一阻挡槽311的截面大致呈矩形，第二阻挡槽313的截面大致呈梯形。可以理解，本申请对第一阻挡槽311的截面形状不作限定，本申请对第二阻挡槽313的截面不作限定。
如图9所示，第三实施方式还提供一种功率半导体器件30的制备方法，包括以下步骤：
步骤301，提供预制结构。预制结构包括功能层31、第一金属部33及第二金属部35。功能层31包括第一区域301、第二区域303及第三区域305。第三区域305位于第一区域301与第二区域303之间。第一金属部33覆盖于第一区域301上，第二金属部35覆盖于第二区域303上。功能层31还包括层叠设置的第一功能层315与第二功能层317。
在第一区域301的第一功能层315设置第一金属部33及在第二区域303的第一功能层 315上设置第二金属部35。本实施方式中，第一功能层315的材质不同于第二功能层317的材质，第一金属部33与第二金属部35设于第一功能层315背离第二功能层317的一侧。第一功能层315为Si 3N 4制成的钝化层，第二功能层317为SiO 2制成的钝化层。
步骤303，如图10所示，在第三区域305的第一功能层315上形成第一阻挡槽311。第一阻挡槽311包括沿平行于第一金属部33与功能层31层叠方向而相对设置的第一端口3111与第二端口3113。第一端口3111设于第一功能层315最靠近第一金属部33的一面。
本实施方式中，将带有光刻显影出预设图形的预制结构(样品晶片)放入刻蚀腔体，利用干法刻蚀掩蔽介质膜，向刻蚀腔体注入第一气体或第二气体对功能层31进行刻蚀，使第一功能层315上形成第一阻挡槽311。第一气体包括高碳分子碳氟基(例如C 4F 6或C 4F 8)气体、稀释性气体。第二气体包括氢碳氟基气体，氢碳氟基气体包括CHF 3、CH 2F 2、CH 3F中的一种。
步骤305，如图11所示，在第二功能层317上形成与第一阻挡槽311连通的第二阻挡槽313。第二阻挡槽313靠近第一阻挡槽311的一端的口径要大于第二端口3113的口径。本实施方式中，采用湿法刻蚀，在第二功能层317形成与第一阻挡槽311连通的第二阻挡槽313，进行湿法刻蚀的腐蚀溶液可为KOH溶液。对第二功能层317进行湿法刻蚀完成后，再依次用去离子水、乙醇、丙酮、乙醚等对预制结构进行清洗。清洗完成后，对预制结构进行甩干。在其他实施方式中，腐蚀溶液可以为其他溶液，腐蚀溶液包括含49％HF、12％NH 4F。
步骤307，如图8所示，形成绝缘层37。在第一金属部33、第二金属部35及第三区域305上覆盖绝缘层37，进而形成功率半导体器件30。绝缘层37包括连接设置的主体371、第一阻挡部373及第二阻挡部375，主体371覆盖于第一金属部33、第二金属部35及第三区域305上，第一阻挡部373填充第一阻挡槽311，第二阻挡部375填充第二阻挡槽313。
可以理解，本申请对钝化层的材质不作限定，在其他实施方式中，例如，第一功能层315可以为SiO 2制成的钝化层，第二功能层317可以为Si 3N 4制成的钝化层。
请参阅图12，本申请第四实施方式提供一种功率半导体器件30，第四实施方式提供的功率半导体器件30与第二实施方式提供的功率半导体器件的结构大致相似，不同在于，功能层31还包括层叠设置的第一功能层315与第二功能层317，第一功能层315的材质不同于第二功能层317的材质，第一金属部33与第二金属部35设于第一功能层315背离第二功能层317的一侧,第一阻挡槽311位于第一功能层315，第二阻挡槽313位于第一功能层315，其中，第一功能层315为Si层，第二功能层317为Si 3N 4制成的钝化层。Si层用于保护钝化层，将第一阻挡槽311与第二阻挡槽313均设于Si层上不会破坏钝化层的结构，进而不会影响钝化层的功能。
本实施方式中，第一阻挡槽311的截面大致呈矩形，第二阻挡槽313的截面大致呈梯形。可以理解，本申请对第一阻挡槽311的截面形状不作限定，本申请对第二阻挡槽313的截面不作限定。
请结合参阅图13，第四实施方式还提供一种功率半导体器件30的制备方法，包括以下步骤：
步骤401，提供预制结构，预制结构包括功能层31、第一金属部33及第二金属部35，功能层31包括第一区域301、第二区域303及第三区域305，第三区域305位于第一区域301与第二区域303之间，第一金属部33覆盖于所述第一区域301上，第二金属部35覆盖于所述第二区域303上。
功能层31还包括层叠设置的第一功能层315与第二功能层317，第一功能层315的材质 不同于第二功能层317的材质，第一金属部33与第二金属部35设于第一功能层315背离第二功能层317的一侧。
步骤403，如图14所示，在第三区域305的第一功能层315上形成第一阻挡槽311。第一阻挡槽311包括沿平行于第一金属部33与功能层31层叠方向而相对设置的第一端口3111与第二端口3113。第一端口3111设于功能层31最靠近第一金属部33的一面。
本实施方式中，将带有光刻显影出预设图形的预制结构(样品晶片)放入刻蚀腔体，向刻蚀腔体通入第三气体，利用干法刻蚀掩蔽介质膜工艺对第一功能层315进行刻蚀，使第一功能层315上形成第一阻挡槽311。第三气体包括SF 6。
步骤404，如图15所示，在第一阻挡槽311的槽壁上沉积形成保护膜40。保护膜40用于保护第一阻挡槽311的槽壁。在本实施方式中，向刻蚀腔体通入第一气体，利用干法刻蚀掩蔽介质膜工艺在第一阻挡槽311的槽壁上沉积形成保护膜40。第一气体包括C 4F 8。
步骤405，如图16所示，在第一功能层315上形成第二阻挡槽313。第二阻挡槽313与第二端口3113连通。第二阻挡槽313靠近第一阻挡槽311的第二端口3113的口径要大于第一端口3111的口径。本实施方式中，向刻蚀腔体通入第三气体，利用干法刻蚀掩蔽介质膜工艺对第一功能层315进行各向同性刻蚀形成第二阻挡槽313。
步骤407，如图12所示，形成绝缘层37。在第一金属部33、第二金属部35及第三区域305上覆盖绝缘层37，以形成功率半导体器件30。绝缘层37包括连接设置的主体371、第一阻挡部373及第二阻挡部375，主体371覆盖于第一金属部33、第二金属部35及第三区域305上，第一阻挡部373填充第一阻挡槽311，第二阻挡部375填充第二阻挡槽313。
可以理解，在其他实施方式中，可以省略步骤404。
应当理解的是，可以在本申请中使用的诸如“包括”以及“可以包括”之类的表述表示所公开的功能、操作或构成要素的存在性，并且并不限制一个或多个附加功能、操作和构成要素。在本申请中，诸如“包括”和/或“具有”之类的术语可解释为表示特定特性、数目、操作、构成要素、部件或它们的组合，但是不可解释为将一个或多个其它特性、数目、操作、构成要素、部件或它们的组合的存在性或添加可能性排除在外。
此外，在本申请中，表述“和/或”包括关联列出的词语中的任意和所有组合。例如，表述“A和/或B”可以包括A，可以包括B，或者可以包括A和B这二者。
在本申请中，包含诸如“第一”和“第二”等的序数在内的表述可以修饰各要素。然而，这种要素不被上述表述限制。例如，上述表述并不限制要素的顺序和/或重要性。上述表述仅用于将一个要素与其它要素进行区分。例如，第一用户设备和第二用户设备指示不同的用户设备，尽管第一用户设备和第二用户设备都是用户设备。类似地，在不脱离本申请的范围的情况下，第一要素可以被称为第二要素，类似地，第二要素也可以被称为第一要素。
当部件被称作“连接”或“接入”其他部件时，应当理解的是：该部件不仅直接连接到或接入到其他部件，而且在该部件和其它部件之间还可以存在另一部件。另一方面，当部件被称作“直接连接”或“直接接入”其他部件的情况下，应该理解它们之间不存在部件。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种功率半导体器件，其特征在于，包括功能层、第一金属部、第二金属部及绝缘层，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述功能层还包括设置在所述第三区域的第一阻挡槽，所述第一金属部设置在所述第一区域上，所述第二金属部设置在所述第二区域上，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体覆盖于所述第一金属部、所述第二金属部及所述第三区域上，所述第一阻挡部填充所述第一阻挡槽，所述功能层还包括至少一个钝化层。
  2. 根据权利要求1所述的功率半导体器件，其特征在于，所述第一阻挡槽包括第一端口与第二端口，所述第一端口设于所述功能层最靠近所述第一金属部的一面，所述功能层还包括第二阻挡槽，所述第二阻挡槽与所述第二端口连通，所述绝缘层还包括第二阻挡部，所述第二阻挡部与所述第一阻挡部远离所述主体的一端固定连接，所述第二阻挡部填充所述第二阻挡槽。
  3. 根据权利要求2所述的功率半导体器件，其特征在于，所述第二阻挡槽靠近所述第一阻挡槽的一端的口径要大于所述第二端口的口径。
  4. 根据权利要求2或3所述的功率半导体器件，其特征在于，所述功能层还包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一金属部与所述第二金属部设于所述第一功能层背离所述第二功能层的一侧,所述第一阻挡槽位于所述第一功能层，所述第二阻挡槽位于所述第一功能层及/或所述第二功能层，所述第一功能层与所述第二功能层中的至少一个为钝化层。
  5. 根据权利要求4所述的功率半导体器件，其特征在于，所述第一功能层与所述第二功能层中的一个为Si 3N 4制成的钝化层，所述第一功能层与所述第二功能层中的另一个为SiO 2制成的钝化层，所述第二阻挡槽位于所述第二功能层。
  6. 根据权利要求4所述的功率半导体器件，其特征在于，所述第一功能层为Si层，所述第二功能层为钝化层，所述第二阻挡槽位于所述第一功能层。
  7. 一种电子装置，其特征在于，包括电路板及设于所述电路板上的根据权利要求1-6任意一项所述的功率半导体器件，所述电路板上设有控制电路，所述控制电路用于控制所述功率半导体器件的导通和关断。
  8. 一种功率半导体器件的制备方法，其特征在于，包括以下步骤，
    提供预制结构，所述功能层、第一金属部及第二金属部，所述功能层包括第一区域、第二区域及第三区域，所述第三区域位于所述第一区域与所述第二区域之间，所述第一金属部设置在所述第一区域上，所述第二金属部设置在所述第二区域上，所述功能层还包括至少一个钝化层；
    在所述功能层的第三区域上形成第一阻挡槽；
    形成绝缘层，所述绝缘层包括连接设置的主体及第一阻挡部，所述主体覆盖于所述第一金属部、所述第二金属部及所述第三区域上，所述第一阻挡部填充所述第一阻挡槽。
  9. 根据权利要求8所述的制备方法，其特征在于，在所述形成绝缘层之前，所述制备方法还包括步骤，在所述功能层上形成与所述第一阻挡槽连通的第二阻挡槽，所述第一阻挡槽包括第一端口与第二端口，所述第一端口设于所述功能层最靠近所述第一金属部的一面，所述第二阻挡槽与所述第二端口连通；
    所述绝缘层还包括第二阻挡部，所述形成绝缘层，还包括，所述第二阻挡部填充所述第二阻挡槽。
  10. 根据权利要求9所述的制备方法，其特征在于，所述功能层为单个钝化层，所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第一气体对功能层进行刻蚀，使所述功能层上形成第一阻挡槽并于所述第一阻挡槽的侧壁上形成保护膜，所述第一气体包括高碳分子碳氟基气体；
    所述在所述功能层上形成第二阻挡槽，包括，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第二气体对所述功能层进行刻蚀，使所述功能层上形成与所述第二端口连通的第二阻挡槽，所述第二气体包括氢碳氟基气体。
  11. 根据权利要求9所述的制备方法，其特征在于，所述功能层包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一功能层为Si 3N 4制成的钝化层，所述第二功能层为SiO 2制成的钝化层；
    所述第一区域的第一功能层设置有所述第一金属部及所述第二区域的第一功能层上设置有所述第二金属部；
    所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第一气体或第二气体对功能层进行刻蚀，使所述第一功能层上形成所述第一阻挡槽，所述第一气体包括高碳分子碳氟基气体，所述第二气体包括氢碳氟基气体；
    所述在所述功能层上形成第二阻挡槽，包括，采用湿法刻蚀，在所述第二功能层上形成所述第二阻挡槽。
  12. 根据权利要求9所述的制备方法，其特征在于，所述功能层包括层叠设置的第一功能层与第二功能层，所述第一功能层的材质不同于所述第二功能层的材质，所述第一功能层为Si层，所述第二功能层为钝化层；
    所述第一区域的第一功能层设置有所述第一金属部及所述第二区域的第一功能层上设置有所述第二金属部；
    所述在功能层上形成第一阻挡槽，包括，将所述预制结构放入刻蚀腔体，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体注入第三气体对所述第一功能层进行刻蚀，使所述第一功能层上形成所述第一阻挡槽，所述第三气体包括SF 6；
    所述在所述功能层上形成第二阻挡槽，包括，采用干法刻蚀掩蔽介质膜工艺，向所述刻蚀腔体通入第三气体对所述第一功能层进行各向同性刻蚀，使所述第二功能层形成所述第二阻挡槽。
  13. 根据权利要求12所述的制备方法，其特征在于，所述在功能层上形成第一阻挡槽后，所述在所述功能层上形成第二阻挡槽前，所述制备方法还包括步骤，采用干法刻蚀掩蔽介质膜工艺，向刻蚀腔体通入第一气体，在所述第一阻挡槽的槽壁上沉积形成保护膜，所述第一气体包括高碳分子碳氟基气体。
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