WO2023051172A1 - 编码方法、译码方法及装置 - Google Patents

编码方法、译码方法及装置 Download PDF

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Publication number
WO2023051172A1
WO2023051172A1 PCT/CN2022/116922 CN2022116922W WO2023051172A1 WO 2023051172 A1 WO2023051172 A1 WO 2023051172A1 CN 2022116922 W CN2022116922 W CN 2022116922W WO 2023051172 A1 WO2023051172 A1 WO 2023051172A1
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matrix
sequence
reliability
equal
extended
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PCT/CN2022/116922
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English (en)
French (fr)
Inventor
秦康剑
李榕
张华滋
王献斌
王俊
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of communication technologies, and in particular to an encoding method, a decoding method and a device.
  • polar codes As a channel coding scheme that can prove to "reach" Shannon's channel capacity, polar codes have both the characteristics of algebraic coding structure and probabilistic decoding. In general, polar codes can be used for control channel coding.
  • the data channel coding adopts low-density parity check (low-density parity check, LDPC) code. Since the code length of the polar code is not easy to expand flexibly, its application on the data channel is limited.
  • low-density parity check low-density parity check
  • the present application provides an encoding method, a decoding method and a device, which can flexibly extend the code length according to different M, and improve the flexibility of code length extension.
  • the embodiment of the present application provides an encoding method, the method including:
  • the first bit sequence includes K information bits, the K is an integer greater than or equal to 1, and the M is an integer greater than or equal to 1;
  • the sending end determines the number of parity bits E according to the given sending code length M and N, so as to perform the second channel coding and obtain E parity bits.
  • the method provided by the embodiment of the present application can flexibly extend the code length according to different M, for example, E number of parity bits can be extended, which improves the flexibility of code length extension.
  • the method provided by the embodiment of this application can not only combine the advantages of polar code coding, but also flexibly extend the code length, so that polar code coding can be more flexibly applied to data channels superior.
  • the performing the second channel coding according to the second bit sequence includes: performing the second channel coding according to the second bit sequence and an extension matrix, and the extension matrix includes N rows and E columns , the extended matrix is obtained according to the extended base matrix, the extended base matrix includes N 0 rows and E 0 columns, and both the E 0 and the N 0 are integers greater than or equal to 1.
  • Z N/N 0
  • the Z is an expansion factor of the expanded basis matrix
  • Z 16.
  • the E columns of the extended matrix are the first E columns of the first matrix, and the first matrix is a matrix obtained by extending the extended base matrix according to the extended factor; or, the extended matrix
  • the E columns in the first matrix are adjacent E columns in the first matrix, and the adjacent E columns in the first matrix are determined according to the code rate of the first channel coding, and the first matrix is the extended base matrix according to the extended Matrix after factor expansion.
  • the column weight of a certain column in the extended matrix is related to the N, the K, and the E.
  • the column weight of a certain column in the extended matrix satisfies any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N Negatively correlated with K/N and positively correlated with K/N.
  • the column weight of the first column in the extended matrix satisfies any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N is negatively correlated, and K/N is positively correlated.
  • the column weights of at least two columns in the extended matrix satisfy any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N is negatively correlated, and K/N is positively correlated.
  • the column weight of each column in the extended matrix satisfies any one or more of the following relationships: negatively correlated with the E, positively correlated with the K, and positively correlated with the N Negatively correlated with K/N and positively correlated with K/N.
  • the positions of the K information bits are determined according to a first reliability sequence, the length of the first reliability sequence is the N, and the first reliability sequence is the second reliability sequence.
  • the second reliability sequence satisfies the following relationship:
  • the reliability sequence is the reliability sequence, where the element is the serial number of the subchannel, Indicates the reliability corresponding to the reliability sequence, and the i is an integer greater than or equal to 1 and less than or equal to N max .
  • the performing the first channel coding on the first bit sequence includes: determining the reliability of each of the N positions according to the channel state and the spreading matrix, and the reliability of one position It is positively correlated with the number of parity bits involved; determining the first reliability sequence according to the order of the reliability of the N positions from low to high; performing the first reliability sequence on the first bit sequence according to the first reliability sequence A channel code.
  • the performing first channel coding on the first bit sequence includes: performing first channel coding on the first bit sequence according to an inner interleaver sequence, and the inner interleaver sequence according to The spreading matrix determines that the size of the blocks of the inner interleaver sequence is equal to the spreading factor of the spreading matrix.
  • an embodiment of the present application provides a decoding method, the method including:
  • the second sequence to be decoded includes information of N bits and information of E check bits, where N is an integer greater than or equal to 1, and E is greater than or equal to 1 is an integer; perform second channel decoding on the second sequence to be decoded according to an extension matrix to obtain a first sequence to be decoded, the extension matrix includes N rows and E columns, and the extension matrix is obtained according to the extension base matrix,
  • the extended basic matrix includes N 0 rows and E 0 columns
  • the first sequence to be decoded includes the information of the N bits
  • the E 0 and the N 0 are both integers greater than or equal to 1;
  • the A reliability sequence performs first channel decoding on the first sequence to be decoded to obtain a first bit sequence, the length of the first reliability sequence is the N, and the first reliability sequence is the second A subsequence of a reliability sequence, the length of the second reliability sequence is N max , the N max is greater than or equal to the N, and the first bit sequence includes K information
  • the information of E check bits can be understood as a soft information sequence after E check bits pass through a channel
  • the information of N bits can be understood as a soft information sequence after N bits pass through a channel. It can be understood that the information of N bits included in the first sequence to be decoded may be the same as or different from the information of N bits included in the second sequence to be decoded.
  • the first reliability sequence is a subsequence of the second reliability sequence.
  • the first reliability sequence may also be obtained according to the extended matrix, for example, the receiving end may obtain the first reliability sequence through an online construction method.
  • Z N/N 0
  • the Z is an expansion factor of the expanded basis matrix
  • Z 16.
  • the E columns of the extended matrix are the first E columns of the first matrix, and the first matrix is a matrix obtained by extending the extended base matrix according to the extended factor; or, the extended matrix
  • the E columns in the first matrix are adjacent E columns in the first matrix, and the adjacent E columns in the first matrix are determined according to the code rate of the first channel coding, and the first matrix is the extended base matrix according to the extended Matrix after factor expansion.
  • the column weight of a certain column in the extended matrix is related to the N, the K, and the E.
  • the column weight of a certain column in the extended matrix satisfies any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N Negatively correlated with K/N and positively correlated with K/N.
  • the column weight of the first column in the extended matrix satisfies any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N is negatively correlated, and K/N is positively correlated.
  • the column weights of at least two columns in the extended matrix satisfy any one or more of the following relationships: being negatively correlated with the E, positively correlated with the K, and positively correlated with the N is negatively correlated, and K/N is positively correlated.
  • the column weight of each column in the extended matrix satisfies any one or more of the following relationships: negatively correlated with the E, positively correlated with the K, and positively correlated with the N Negatively correlated with K/N and positively correlated with K/N.
  • the second reliability sequence satisfies the following relationship:
  • the reliability sequence is the reliability sequence, where the element is the serial number of the subchannel, Indicates the reliability corresponding to the reliability sequence, and the i is an integer greater than or equal to 1 and less than or equal to N max .
  • the performing first channel decoding on the first sequence to be decoded according to the first reliability sequence includes: performing the first channel decoding on the first sequence to be decoded according to the first reliability sequence and an inner interleaver sequence.
  • the first sequence to be decoded is subjected to first channel decoding, the inner interleaver sequence is determined according to the spreading matrix, and the block size of the inner interleaver sequence is equal to the spreading factor of the spreading matrix.
  • the embodiment of the present application provides a communication device, configured to execute the method in the first aspect or any possible implementation manner of the first aspect.
  • the communication device includes a unit for performing the method in the first aspect or any possible implementation manner of the first aspect.
  • the communication device may be a sending end or a chip in the sending end.
  • the embodiment of the present application provides a communication device, configured to execute the method in the second aspect or any possible implementation manner of the second aspect.
  • the communication device includes a corresponding method for performing the method in the second aspect or any possible implementation manner of the second aspect.
  • the communication device may be a receiving end or a chip in the receiving end.
  • the above communication device may include an input and output unit and a processing unit.
  • the input and output unit and the processing unit reference may also be made to the device embodiments shown below.
  • an embodiment of the present application provides a communication device, where the communication device includes a processor, configured to execute the method described in the first aspect or any possible implementation manner of the first aspect.
  • the processor is used to execute a program stored in the memory, and when the program is executed, the method shown in the first aspect or any possible implementation manner of the first aspect is executed.
  • the process of sending information or outputting information (such as the third bit sequence) or obtaining information (such as obtaining the first bit sequence, etc.) in the above method can be understood as the process of outputting the above information by the processor , or the process by which the processor receives the input of the above information.
  • the processor When outputting information, the processor outputs the aforementioned information to the transceiver for transmission by the transceiver. After the above information is output by the processor, other processing may be required before reaching the transceiver.
  • the processor receives the above-mentioned input information
  • the transceiver receives the above-mentioned information and inputs it to the processor. Furthermore, after the transceiver receives the above information, the above information may need to be processed before being input to the processor.
  • the acquisition of the first bit sequence mentioned in the foregoing method may be understood as the processor receiving the input first bit sequence.
  • the output of the third bit sequence mentioned in the foregoing method may be understood as the processor outputting the third bit sequence and the like.
  • the above-mentioned processor may be a processor dedicated to performing these methods, or may be a processor that executes computer instructions in a memory to perform these methods, such as a general-purpose processor.
  • the above-mentioned memory can be a non-transitory (non-transitory) memory, such as a read-only memory (read only memory, ROM), which can be integrated with the processor on the same chip, or can be respectively arranged on different chips.
  • ROM read-only memory
  • the embodiment does not limit the type of the memory and the arrangement of the memory and the processor. It can be understood that the description of the processor and the memory is also applicable to the sixth aspect shown below, and for the sake of brevity, the description of the sixth aspect of the processor and the memory will not be described in detail.
  • the memory is located outside the communication device.
  • the memory is located in the above communication device.
  • the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.
  • the memory may be used to store one or more items of the second reliability sequence or the extended basis matrix, and the like.
  • the communication device further includes a transceiver, where the transceiver is configured to receive a signal or send a signal.
  • the transceiver may also be used to send a sequence obtained according to the third bit sequence, and the like.
  • the communication device may be the sending end or a chip in the sending end.
  • an embodiment of the present application provides a communication device, where the communication device includes a processor configured to execute the method described in the second aspect or any possible implementation manner of the second aspect.
  • the processor is used to execute the program stored in the memory, and when the program is executed, the method shown in the above second aspect or any possible implementation manner of the second aspect is executed.
  • the memory is located outside the communication device.
  • the memory is located in the above communication device.
  • the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.
  • the memory may be used to store any one or more items of the second reliability sequence or the extended basis matrix.
  • the communication device further includes a transceiver, where the transceiver is configured to receive a signal or send a signal.
  • the transceiver may be used to receive a sequence (the received sequence shown in FIG. 10 ) and the like.
  • the communication device may be a receiving end or a chip in the receiving end.
  • the embodiment of the present application provides a communication device, the communication device includes a logic circuit and an interface, the logic circuit is coupled to the interface; the logic circuit is used to obtain the first bit sequence; the logic circuit , is also used to perform first channel coding on the first bit sequence to obtain a second bit sequence; and perform second channel coding according to the second bit sequence to obtain a third bit sequence; the interface is also used to outputting the third bit sequence.
  • the first bit sequence includes K information bits, and the K is an integer greater than or equal to 1;
  • the second bit sequence includes N bits, and the N is an integer greater than or equal to 1;
  • the logic circuit shown above is used to obtain the first bit sequence; it can also be understood as: the logic circuit is used to input data to be processed through the interface and process the data to be processed, The first bit sequence is obtained.
  • the first bit sequence may be input to the logic circuit from other devices or components through the interface, or may be obtained by the logic circuit after processing other data input by the interface, which is not limited in this embodiment of the present application.
  • the logic circuit is specifically configured to perform second channel coding according to the second bit sequence and the spreading matrix.
  • the extended matrix includes N rows and E columns, and the extended matrix is obtained according to the extended base matrix, and the extended base matrix includes N 0 rows and E 0 columns, and the E 0 and the N 0 are both greater than or equal to 1 an integer of .
  • the logic circuit is specifically configured to perform first channel coding on the first bit sequence according to an inner interleaver sequence, the inner interleaver sequence is determined according to the spreading matrix, and the The block size of the inner interleaver sequence is equal to the spreading factor of the spreading matrix.
  • the embodiment of the present application provides a communication device, the communication device includes a logic circuit and an interface, the logic circuit is coupled to the interface; the logic circuit is used to obtain the second sequence to be decoded, and according to The spreading matrix performs second channel decoding on the second sequence to be decoded to obtain a first sequence to be decoded; and performs first channel decoding on the first sequence to be decoded according to the first reliability sequence to obtain first bit sequence.
  • the second sequence to be decoded includes information of N bits and information of E check bits, the N is an integer greater than or equal to 1, and the E is an integer greater than or equal to 1;
  • the extension The matrix includes N rows and E columns, the extended matrix is obtained according to the extended base matrix, the extended base matrix includes N 0 rows E 0 columns, the first sequence to be decoded includes the information of the N bits, and the E 0 and the N 0 are integers greater than or equal to 1;
  • the length of the first reliability sequence is the N
  • the first reliability sequence is a subsequence of the second reliability sequence
  • the second The length of the reliability sequence is N max , the N max is greater than or equal to the N, and the first bit sequence includes K information bits.
  • the logic circuit shown above is used to obtain the third bit sequence; it can also be understood as: an interface for inputting data to be processed (such as a receiving sequence obtained through a channel, etc.), and a logic circuit for inputting to the interface
  • the data to be processed is processed to obtain a second sequence to be decoded; or, the logic circuit inputs the second sequence to be decoded through an interface.
  • the logic circuit is specifically configured to perform first channel decoding on the first sequence to be decoded according to the first reliability sequence and the inner interleaver sequence, and the inner interleaving
  • the inner interleaver sequence is determined according to the spreading matrix, and the block size of the inner interleaver sequence is equal to the spreading factor of the spreading matrix.
  • the embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program, and when it is run on a computer, any of the above-mentioned first aspect or the first aspect is possible
  • the method shown in the implementation manner is executed; or, the method shown in the second aspect or any possible implementation manner of the second aspect is executed.
  • the embodiment of the present application provides a computer program product, the computer program product includes a computer program or computer code, and when it is run on a computer, the above first aspect or any possible implementation of the first aspect can achieve The method shown in the second aspect is executed; or, the method shown in the second aspect or any possible implementation manner of the second aspect is executed.
  • the embodiment of the present application provides a computer program.
  • the computer program When the computer program is run on a computer, the method shown in the above-mentioned first aspect or any possible implementation of the first aspect is executed; or, the above-mentioned second aspect The method shown in any possible implementation of the aspect or the second aspect is executed.
  • the embodiment of the present application provides a wireless communication system
  • the wireless communication system includes a sending end and a receiving end
  • the sending end is used to implement the above first aspect or any possible implementation of the first aspect
  • the receiving end is configured to execute the method shown in the above second aspect or any possible implementation manner of the second aspect.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • Fig. 2 is a schematic diagram of a polar code encoding provided by an embodiment of the present application
  • FIG. 3 is a schematic tree structure diagram of decoding of a serial elimination list (successive cancellation list, SCL) provided by the embodiment of the present application;
  • Fig. 4a is a schematic flowchart of an encoding method provided by an embodiment of the present application.
  • FIG. 4b is a schematic diagram of a second channel coding provided by an embodiment of the present application.
  • Fig. 5a is a schematic diagram of an extended basis matrix provided by an embodiment of the present application.
  • Fig. 5b is a schematic diagram of another extended basis matrix provided by the embodiment of the present application.
  • Fig. 5c is a schematic flowchart of a method for generating an extended basis matrix provided by an embodiment of the present application.
  • Fig. 5d is a schematic flowchart of another method for generating an extended basis matrix provided by an embodiment of the present application.
  • Fig. 6a is a schematic diagram of the decoding performance corresponding to a different construction sequence provided by the embodiment of the present application.
  • Fig. 6b is a schematic diagram of reliability differences and block features between bit channels provided by an embodiment of the present application.
  • Fig. 6c is a schematic diagram of a verification relationship between a verification node and a variable node provided in an embodiment of the present application;
  • Fig. 6d is a schematic diagram of the relationship between an extended matrix and the first reliability sequence provided by the embodiment of the present application.
  • Fig. 7a is a schematic diagram of a comparison of decoding performance between a coding method proposed in the present application and a polar code coding method provided by an embodiment of the present application;
  • Fig. 7b is a schematic diagram of the comparison of the decoding performance of the repeated coding of the coding method proposed in the present application and the polar code coding method provided by the embodiment of the present application;
  • Fig. 8 is a schematic flow chart of a decoding method provided by an embodiment of the present application.
  • Fig. 9a is a schematic flow chart of a large iterative decoding provided by the embodiment of the present application.
  • Fig. 9b is a schematic diagram of a decoding method provided by an embodiment of the present application.
  • Fig. 9c is a schematic diagram of a comparison between the maximum decoding complexity and the average decoding complexity provided by the embodiment of the present application.
  • Fig. 9d to Fig. 9g are schematic diagrams showing the performance comparison of the coding method, the repetitive coding method and the long code coding method proposed in the embodiment of the present application;
  • Fig. 10 is a schematic diagram of an encoding method and a decoding method provided by an embodiment of the present application.
  • 11 to 13 are schematic structural diagrams of a communication device provided by an embodiment of the present application.
  • an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application.
  • the occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.
  • At least one (item) means one or more
  • “multiple” means two or more
  • “at least two (items)” means two or three and three
  • “and/or” is used to describe the association relationship of associated objects, which means that there can be three kinds of relationships, for example, "A and/or B” can mean: only A exists, only B exists, and A and B exist at the same time A case where A and B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an "or” relationship.
  • “At least one of the following” or similar expressions refer to any combination of these items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c ".
  • the method provided by this application can be applied to various communication systems, for example, it can be an Internet of Things (Internet of Things, IoT) system, a narrowband Internet of Things (NB-IoT) system, a long term evolution (long term evolution) , LTE) system, or the fifth-generation (5th-generation, 5G) communication system (such as including enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (ultra reliable and low latency communication, URLLC) and enhanced machine type communication (eMTC), as well as new communication systems (such as 6G) that will emerge in future communication development.
  • eMBB enhanced mobile broadband
  • URLLC ultra-reliable and low-latency communication
  • eMTC enhanced machine type communication
  • new communication systems such as 6G
  • the method provided in this application can also be applied to a wireless local area network (wireless local area network, WLAN) system, such as wireless-fidelity (wireless-fidelity, Wi-Fi) and the like.
  • WLAN wireless local area network
  • the technical solution provided by this application can also be applied to machine type communication (machine type communication, MTC), inter-machine communication long-term evolution technology (Long Term Evolution-machine, LTE-M), device-to-device (device-to-device, D2D) network , machine to machine (machine to machine, M2M) network, Internet of things (internet of things, IoT) network or other networks.
  • MTC machine type communication
  • LTE-M inter-machine communication long-term evolution technology
  • device-to-device device-to-device
  • M2M machine to machine
  • IoT Internet of things
  • the IoT network may include, for example, the Internet of Vehicles.
  • the communication methods in the Internet of Vehicles system are collectively referred to as vehicle to other devices (vehicle to X, V2X, X can represent anything), for example, the V2X can include: vehicle to vehicle (vehicle to vehicle, V2V) communication, vehicle and Infrastructure (vehicle to infrastructure, V2I) communication, vehicle to pedestrian (vehicle to pedestrian, V2P) or vehicle to network (vehicle to network, V2N) communication, etc.
  • vehicle to vehicle vehicle to vehicle
  • V2V vehicle to vehicle
  • V2I vehicle to infrastructure
  • V2P vehicle to pedestrian
  • V2N vehicle to network
  • the terminal equipment in this application is a device with wireless transceiver function.
  • the terminal device may communicate with an access network device (or also called an access device) in a radio access network (radio access network, RAN).
  • radio access network radio access network
  • the terminal equipment may also be called user equipment (user equipment, UE), access terminal, terminal (terminal), subscriber unit (subscriber unit), subscriber station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent or user device, etc.
  • the terminal device may be deployed on land, including indoor or outdoor, handheld or vehicle-mounted; it may also be deployed on water (such as a ship, etc.).
  • the terminal device may be a handheld device with a wireless communication function, a vehicle-mounted device, a wearable device, a sensor, a terminal in the Internet of Things, a terminal in the Internet of Vehicles, a drone, a fifth-generation ( 5th generation, 5G) network and any form of terminal equipment in the future network, etc., this application does not limit this.
  • the terminal equipment shown in this application may not only include vehicles (such as automobiles) in the Internet of Vehicles, but also include vehicle-mounted devices or vehicle-mounted terminals in the Internet of Vehicles.
  • vehicle-mounted devices such as automobiles
  • vehicle-mounted terminals in the Internet of Vehicles.
  • the specific form is not limited.
  • the terminal devices shown in this application can also communicate with each other through technologies such as D2D, V2X, or M2M, and this application does not limit the communication method between terminal devices.
  • the network device in this application may be a device deployed in a wireless access network to provide wireless communication services for terminal devices.
  • the network device may also be called an access network device, an access device, or a RAN device.
  • the network device may be a next generation node B (next generation node B, gNB), a next generation evolved base station (next generation evolved nodeB, ng-eNB), or a network device in future 6G communications.
  • the network device may be any device with a wireless transceiver function, including but not limited to the above-mentioned base stations (including base stations deployed on satellites).
  • the network device may also be a device with a base station function in the sixth generation communication system.
  • the network device may be an access node, a wireless relay node, a wireless backhaul node, etc. in a wireless local area network (wireless fidelity, WiFi) system.
  • the network device may be a wireless controller in a cloud radio access network (cloud radio access network, CRAN) scenario.
  • the network device may be a wearable device or a vehicle-mounted device.
  • the network device may also be a small station, a transmission reception point (transmission reception point, TRP) (or may also be called a transmission point), etc.
  • TRP transmission reception point
  • the network device may also be a base station, a satellite, etc. in a public land mobile network (public land mobile network, PLMN) that will evolve in the future.
  • PLMN public land mobile network
  • the network device may also be a device carrying base station functions in a non-terrestrial communication system, D2D, V2X, or M2M, and the present application does not limit the specific type of the network device.
  • the names of devices capable of network device functions may be different.
  • the network device may include a centralized unit (centralized unit, CU) and a distributed unit (distributed unit, DU).
  • the CU can also be divided into CU-control plane (control plane, CP) and CU-user plane (user plan, UP).
  • the network equipment may also be an open radio access network (open radio access network, ORAN) architecture, etc., and this application does not limit the specific deployment manner of the network equipment.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • the communication system may include at least one network device and at least one terminal device, such as terminal device 1 to terminal device 4 in FIG. 1 .
  • the terminal device 3 and the terminal device 4 shown in FIG. 1 may communicate directly.
  • direct communication between terminal devices can be realized through D2D technology.
  • terminal device 1 to terminal device 4 may respectively communicate with network devices.
  • the terminal device 3 and the terminal device 4 may communicate with the network device directly, or may communicate with the network device indirectly, such as communicating with the network device via other terminal devices (not shown in FIG. 1 ).
  • FIG. 1 exemplarily shows a network device, multiple terminal devices, and communication links between communication devices.
  • the communication system may include multiple network devices, and the coverage of each network device may include other numbers of terminal devices, for example, more or fewer terminal devices. This application does not limit this.
  • the network architecture and business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions provided by the embodiments of the present application.
  • the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
  • the QC matrix may also be called a quasi-cyclic shift, a QC form, or a quasi-cyclic shift matrix.
  • matrix is a QC matrix with a lifting size equal to 5, and the non-zero elements in the QC matrix are called shifting values. Then the matrix corresponding to the binary field can be obtained as follows:
  • the value of the non-zero element in the above-mentioned QC matrix is called the shifting value (shifting value), then the unit matrix at the position of the non-zero element can be cyclically shifted to the right by z columns.
  • the matrix corresponding to the non-zero element 3 in the above QC matrix can be obtained by cyclically shifting 3 columns from I to the right, namely
  • the non-zero element 5 in the above QC matrix is equal to the expansion factor, it is equivalent to not performing right shifting of the columns.
  • the matrix corresponding to the non-zero element 1 in the above-mentioned QC matrix can be obtained by cyclically shifting 1 column to the right by I, that is
  • the matrix corresponding to the non-zero element 2 in the above-mentioned QC matrix can be obtained by cyclically shifting 2 columns from I to the right, namely
  • the binary domain matrix corresponding to the above QC matrix can be shown as follows:
  • the translation value when the translation value is equal to the expansion factor, it is equivalent to not performing rightward circular translation on the unit matrix. If the translation value is greater than the expansion factor, it is equivalent to cyclically shifting the mod(shifting value, lifting size) column to the right of the unit matrix.
  • the expansion factor 5 shown above is only an example, and the application does not limit the size of the expansion factor. Exemplarily, the expansion factor may also be equal to 3 or 7, and so on. At the same time, this application does not limit other names of the expansion factor.
  • the column weight of a corresponding column (also called a certain column) of the matrix shown in this application may be represented by the number of non-zero elements in the corresponding column (also called a certain column) in the matrix.
  • the column weight of the first column of the QC matrix can be represented by 2.
  • both the second column and the third column of the above QC matrix include 1 non-zero element, then the column weights of the second column and the third column of the QC matrix can both be represented by 1.
  • the column weight of the corresponding column of the QC matrix is equal to the column weight of the corresponding column of the matrix on the binary field of the QC matrix.
  • the column weight of the first column of the QC matrix is 2.
  • the first column of the QC matrix corresponds to the first column to the fifth column of its binary field matrix, so the binary field of the QC matrix
  • the column weights of the first to fifth columns in the matrix are all 2.
  • the column weight of the second column of the QC matrix is 1, then the column weights of the sixth column to the tenth column in the binary field matrix of the QC matrix are all 1.
  • the column weight of the first column is greater than that of the sixth column. That is, the greater the number of non-zero elements in the corresponding column in the matrix, the heavier the column weight of the corresponding column in the matrix (also called the greater the column weight). Similarly, the less the number of non-zero elements in the corresponding column in the matrix, the lighter the column weight of the corresponding column in the matrix (also called the smaller column weight).
  • Fig. 2 is a schematic diagram of a polar code encoding provided by an embodiment of the present application.
  • the bits to be coded can be classified into two types according to their respective reliability rankings: frozen bits (frozen) (also called fixed bits) and information bits (data).
  • frozen bits also called fixed bits
  • information bits data
  • bits with higher reliability are set as data bits
  • bits with lower reliability are set as frozen bits
  • the value of frozen bits (frozen) is usually set to 0.
  • the sending end and The receiving end is known.
  • u 7 , u 6 , u 5 , and u 3 are the four bits with the highest reliability, which are set as information bits (data)
  • u 4 , u 2 , u 1 , and u 0 are the four bits with the highest reliability.
  • the last four bits are set as frozen bits (frozen).
  • the reliability sequence is a sort sequence of position numbers from low to high reliability.
  • a reliability sequence A [a 1 ,a 2 ,...,a N ] with a length of N, the first bit a 1 is the position number with the lowest reliability, and the last bit a N is the reliability Highest position number.
  • the sorting sequence from high to low reliability can also be used. Since the essence is the same, this application will still use the sorting sequence of position numbers from low to high reliability as an example for illustration. Alternatively, the location number with the lowest reliability may also start from 0, etc., which is not limited in this application.
  • the K information bits can be placed in A as the last On the reliable K positions such as [a N-K+1 ,...,a N ] (example only), place frozen bits on the remaining NK positions [a 1 ,...,a NK ] in A (such as 0), so as to obtain the information bearing sequence [b 1 ,b 2 ,...,b N ].
  • U 1 can be judged from the channel received signal Y N first (if U 1 is a frozen bit, it can be directly judged), and then the obtained U 1 and channel received signal Y N can be regarded as the second polarized channel And decode it to get U 2 . This process is repeated until the Nth bit UN is decoded, and the decoding ends.
  • FIG. 3 is a schematic diagram of a tree structure of SCL decoding provided by an embodiment of the present application.
  • each bit U i is represented by the i-th layer, where 1 ⁇ i ⁇ 4.
  • each path has a corresponding weight, and its value is determined by the probability of the corresponding U value on the path. Therefore, the path with the largest weight is selected among the final output L paths as the final output of the SCL decoder.
  • the output of the SCL decoder is 1000.
  • This application provides an encoding method, decoding method and device, which not only has the advantages of flexible code length expansion and easy generation of soft values of LDPC codes, but also maintains the strong structure of polar codes and high decoding efficiency The characteristics of LDPC codes and polar codes are effectively combined.
  • the method provided in this application may be applied to the terminal device or network device shown above.
  • the terminal device can be used as the sending end, such as encoding K information bits, and then sending the encoded bits obtained according to the K information bits to the network device; The coded sequence is decoded to obtain K information bits.
  • a network device may serve as a sending end, and a terminal device may serve as a receiving end.
  • the method provided by this application can also be applied to application specific integrated circuit (application specific integrated circuit, ASIC) (also can be referred to as application specific integrated chip, etc.), field programmable logic gate array (field programmable gate array, FPGA) or Programmable chips, etc.
  • the method provided in this application may also be implemented by software (such as by program code stored in a memory). This application is not limited to this.
  • Fig. 4a is a schematic flowchart of an encoding method provided by an embodiment of the present application. As shown in Figure 4a, the method includes:
  • the sending end acquires a first bit sequence and a target code length M, where the first bit sequence includes K information bits, K is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.
  • the first bit sequence can be understood as a bit sequence to be sent obtained by the sending end.
  • the first bit sequence can be understood as a bit sequence that contains information, or needs to be transmitted.
  • the above-mentioned first bit sequence can be understood as being composed of the above-mentioned K information bits.
  • the K information bits may include cyclic redundancy check (cyclic redundancy check, CRC) bits and/or parity check (parity check, PC) bits.
  • CRC cyclic redundancy check
  • PC parity check
  • the K information bits may not include CRC bits; or, may not include PC bits or the like.
  • the sending end can add CRC bits according to the obtained K information bits, or, the sending end can obtain the second bit sequence (as shown in the steps below) 402), adding CRC bits to N bits.
  • the sender can add PC bits to the obtained K information bits, or the sender can add PC bits to the N bits after obtaining the second bit sequence. PC bits.
  • the K information bits neither include CRC bits nor PC bits
  • the sending end may add CRC bits and PC bits according to the obtained K information bits, or, after obtaining the first bit sequence, the sending end may, CRC bits and PC bits are added to the N initial transmission bits.
  • the embodiment of the present application does not limit the position where the sending end adds CRC bits or PC bits. It can be understood that the CRC bits and PC bits shown above are both a verification method, and this embodiment of the present application does not limit other verification methods.
  • the target code length can be understood as a given transmission code length, and the target code length can also be understood as a flexibly extensible code length, a flexibly extensible polarization (extension flexible-polar, EF-polar) code length, etc. , the embodiment of the present application does not limit the name of the target code length.
  • the target code length may be determined according to channel transmission resources and modulation order.
  • the target code length may be set by a network device; or, the target code length may be specified by a protocol or a standard, and the embodiment of the present application does not limit the method for setting the target code length.
  • obtaining the first bit sequence at the sending end may include: generating the first bit sequence at the sending end, or the device for encoding at the sending end obtaining the first bit sequence from other devices at the sending end, etc.,
  • the embodiment of the present application does not limit how the sender acquires the first bit sequence.
  • the sending end performs first channel coding on the first bit sequence to obtain a second bit sequence, where the second bit sequence includes N bits, where N is an integer greater than or equal to 1.
  • the first channel coding includes polar code coding, Bosch-Chandra-Hocquenghem (bose–chaudhuri–hocquenghem, BCH) code coding, Reed-Solomon (RS) code coding, LDPC coding or convolution Any one or more of codes, etc.
  • the first channel coding may be probabilistic coding (such as LDPC coding), or algebraic coding (such as BCH coding), which is not limited in this embodiment of the present application.
  • N may be the mother code length, or may also be the code length after rate matching.
  • the mother code length is greater than N
  • the sender can obtain bits with a length of N through rate matching. That is, when the mother code length is greater than N, the sending end can adapt to the length of the available resource through a rate matching method, so as to obtain the second bit sequence.
  • the rate matching method may include repetition (repetition), puncture (puncture), shortening (shortening), etc., which are not limited in this embodiment of the present application.
  • the second channel coding may also be called redundant coding, redundant extension coding, redundant channel coding, etc., and the name of the second channel coding is not limited in this embodiment of the present application.
  • the above performing the second channel coding according to the second bit sequence includes: performing the second channel coding according to the second bit sequence and an extension matrix, the extension matrix includes N rows and E columns, the extension matrix is obtained according to the extension base matrix, the extension base matrix Including N 0 rows and E 0 columns, both E 0 and N 0 are integers greater than or equal to 1.
  • the sending end may perform second channel coding on the second bit sequence according to the spreading matrix to obtain the third bit sequence.
  • the extended matrix is obtained according to the extended base matrix, that is, the extended base matrix can be adapted to different N and/or different E, so as to obtain an extended matrix matching N and E.
  • the extended base matrix can also be called base matrix (base matrix), base graph (base graph) or original graph (protograph), etc., and the extended matrix can also be called check matrix, redundant extended matrix or redundant coding matrix, etc.
  • the embodiment of the present application does not limit the names of the extended base matrix and the extended matrix. It can be understood that both the extended matrix and the extended base matrix have a QC structure.
  • FIG. 5a to FIG. 5d For the specific description of the extended basis matrix, reference may also be made to the relevant descriptions of FIG. 5a to FIG. 5d , which will not be described in detail here.
  • the extended matrix is represented by H
  • the E parity bits are represented by P
  • the second bit sequence is represented by C
  • the relationship between H and P can be as follows:
  • c 1 , c 2 ,...c N represent N bits of the second bit sequence
  • Fig. 4b is a schematic diagram of a second channel coding provided by an embodiment of the present application.
  • K information bits such as u 1 , u 2 ,...u K are polar coded to obtain a second bit sequence such as c 1 , c 2 ,...c N .
  • the second bit sequence can be output sequentially through the unit matrix of N rows and N columns, as the first N bits of the third bit sequence, and the second bit sequence can obtain E checksums through the expansion matrix H.
  • Check bits, as the last E bits of the third bit sequence so as to achieve the purpose of extending the code length. It can be understood that the form of the unit matrix (such as S NN ) and the extended matrix H shown in FIG.
  • G check [S NN , H NE ] shown in the embodiment of the present application can also be understood as a form of the extended matrix shown in the embodiment of the present application.
  • the above matrix operations can be performed in a binary domain or in a non-binary domain.
  • the expansion matrix can also be in the form of a non-binary domain.
  • the expansion matrix shown in FIG. matrix When the expansion matrix shown in FIG. matrix.
  • the extended matrix shown in Figure 4b is a matrix of a non-binary field, the rows of the extended matrix shown in Figure 4b may not be N, and the number of columns may not be E, but the binary of the N rows and E columns The number of rows and columns when converting a domain matrix to a matrix over a non-binary domain. That is to say, the second channel coding shown in FIG. 4b is only an example, and should not be understood as a limitation to this embodiment of the present application.
  • the encoding method shown in the embodiment of the present application can be degenerated to: the sending end obtains the first bit sequence and the target code length M, and then performs the first channel coding on the first bit sequence to obtain the second A two-bit sequence; output the second bit sequence.
  • the sending end outputs a third bit sequence.
  • the sending end may not perform rate matching again after outputting the third bit sequence.
  • the sending end may perform rate matching after step 404.
  • the sending end may also perform modulation, etc., and send the modulated sequence to the receiving end through a channel, which is not limited in this embodiment of the present application.
  • the sending end determines the number of parity bits E according to the given sending code length M and N, so as to perform the second channel coding and obtain E parity bits.
  • the method provided by the embodiment of the present application can flexibly extend the code length according to different M, for example, E number of parity bits can be extended, which improves the flexibility of code length extension.
  • the method provided by the embodiment of this application can not only combine the advantages of strong structure and high decoding efficiency of polar code, but also can flexibly expand the code length, so that polar code coding Can be more flexibly applied to the data channel.
  • the transmitting end needs to determine the size of the spreading matrix H, for example, the size of the spreading matrix H can be determined according to the length N of the second bit sequence and the target code length M, and for another example, the spreading matrix H can be determined according to the spreading base matrix and the The extension factor (lifting size) of the extension base matrix determines the size of the extension matrix H, etc.
  • the extended matrix shown in the embodiment of the present application can have the property of double nesting, for example, it can be flexibly adapted to different N and E, as shown below:
  • N can be adapted according to the row number N 0 of the extended base matrix and the expansion factor Z.
  • N 0 16
  • N 0 16
  • the length N of the second bit sequence may also be determined according to N 0 and Z. That is to say, Z can also be a fixed value.
  • the sending end can first determine N according to N 0 and Z, and then perform first channel coding on the first bit sequence to obtain the second bit sequence, and according to the second bit sequence and The spreading matrix performs second channel coding and so on.
  • N is determined by the above method, if N is greater than M, N can be shortened or punctured to be smaller than M according to a rate matching method. As for which value N is shortened or punctured to be smaller than M according to the method of rate matching, this embodiment of the present application does not make a limitation.
  • N N 0 *Z.
  • the extended matrix H NE also has the flexibility to adapt to different code rates.
  • the extended matrix H NE can satisfy the property of sub-matrix nesting.
  • the sub-matrix nesting property can be understood as: the extended matrix with a lower code rate is a sub-matrix of the extended matrix with a higher code rate. That is to say, the spreading matrix shown in the embodiment of the present application can be compatible with different code rates. It can be understood that the code rate shown in the embodiment of the present application may be understood as the code rate of the first channel coding.
  • the extended matrix has the flexibility to adapt to different numbers of check bits E, that is, H NE can satisfy the property of column nesting.
  • the column nesting property can be understood as: the extended matrix H N,e1 corresponding to e 1 parity bits is the extended matrix H N,e1+e2 corresponding to e 1 +e 2 parity bits submatrix. That is to say, the sub-matrix H N, e1 obtained by intercepting the first e 1 columns of the extended matrix H N,e1+e2 with the number of check bits e 1 + e 2 can also be obtained well when the number of check bits is e 1 performance. That is to say, the extension matrix shown in the embodiment of the present application can be compatible with different E.
  • the E columns of the extension matrix are the first E columns of the first matrix
  • the first matrix is a matrix after the extension base matrix is extended according to the extension factor.
  • the code rate of the first channel coding is equal to the highest supported code rate
  • the E columns of the extended matrix are the first E columns of the first matrix.
  • the first matrix may be obtained, and then the first E columns of the first matrix are determined as the E columns of the extended matrix according to M-N. It can be understood that, for the description about the extension factor, reference may be made to the above description about adapting to different N, and no further details are given here.
  • the highest supported code rate shown in the embodiment of the present application may also be called the highest designed code rate, etc., and the name of the highest supported code rate is not limited in the embodiment of the present application.
  • the specific value of the highest supported code rate may be set by a network device, or defined by a standard or protocol, etc., which is not limited in this embodiment of the present application.
  • the E column of the extended matrix is the adjacent E column in the first matrix, and the adjacent E column in the first matrix is determined according to the code rate of the first channel coding (also referred to as the same as the first channel coding rate). is related to the code rate of the channel coding), the first matrix is a matrix obtained by extending the extended base matrix according to the extended factor.
  • the code rate obtained by K/N is less than the highest supported code rate
  • column E of the extended matrix may be adjacent column E in the first matrix. That is to say, it may be determined according to an operation result between the code rate obtained by K/N and the highest supported code rate that column E of the extended matrix is an adjacent column E in the first matrix.
  • the E columns of the extended matrix are not the first E columns in the first matrix.
  • the operation result j between the code rate obtained by K/N and the highest supported code rate the first column of the extension matrix is obtained. That is, j is related to K/N, the highest supported code rate and N.
  • j can satisfy any one of the following relations:
  • R K/N
  • Rh represents the highest supported code rate
  • N represents the length of the second bit sequence
  • ⁇ represents an offset value, which can be a real number (such as a positive integer, 0 or a negative integer, etc.).
  • Indicates rounding up Indicates rounding down.
  • ⁇ may be equal to 0.
  • the ⁇ may be equal to -1, -2, -3, -4 or -5, etc., which will not be exemplified here.
  • the ⁇ may be equal to 1, 2, 3, 4 or 5, etc., which will not be listed one by one here.
  • Rh 0.75
  • 512 columns of the first matrix can be taken to the right to obtain the first column of the extended matrix.
  • the first column of the extended matrix is the 513th column of the first matrix
  • the 200th column of the extended matrix Column is the 712th column of the first matrix.
  • the extended matrix shown in the embodiment of the present application can be flexibly adapted to different E, that is, the performance of the second channel coding can be guaranteed under different values of E.
  • the column weight of a certain column in the extended matrix satisfies any one or more of the following relationships: negatively correlated with E, positively correlated with K, negatively correlated with N, and K/N (that is, the first A code rate of channel coding) is positively correlated.
  • the greater the code rate of the first channel coding the heavier the column weight of the certain column.
  • the column weight of the first column in the extended matrix may satisfy the above relationship.
  • the column weight of each column in at least two columns in the extended matrix satisfies the above relationship.
  • the column weight of each column in the extended matrix satisfies the above relationship.
  • the column weight of each column is used as an example below to illustrate the relationship between the column weight and the above parameters.
  • the column weight is heavier (that is, the column weight is larger); or, when K is larger, the column weight is heavier; or, when N is smaller, the column weight is heavier; or, when K The larger the /N, the heavier the column weight.
  • the column weight is lighter (that is, the column weight is smaller); or, when K is smaller, the column weight is lighter; or, when N is larger, the column weight is lighter; or, when K The smaller the /N, the lighter the column weight.
  • the column weight may be a function of N, K and E.
  • K/N when K/N is constant, the smaller E is, the heavier the column weight will be.
  • E when K/N is constant, the larger the K/N, the heavier the column weight.
  • E when E is constant, the smaller the K/N, the lighter the column weight.
  • K/N when K/N is larger and E is smaller, the column weight is heavier.
  • K/N when K/N is smaller and E is larger, the column weight is lighter.
  • the maximum column weight (such as the column weight of a certain column) of the extended basis matrix shown in Figure 5a is smaller than that of the extended basis matrix shown in Figure 5b
  • the maximum column weight of the basis matrix (such as the column weight of a certain column).
  • the minimum column weight in the extended basis matrix shown in FIG. 5a is 1 and the maximum is 5, and the minimum column weight in the extended basis matrix shown in FIG. 5b is 1 and the maximum is 8.
  • the column weight of the first column of the extended basis matrix shown in FIG. 5 a is 3, and the column weight of the first column of the extended basis matrix shown in FIG. 5 b is 8.
  • Fig. 5a and Fig. 5b show an example of an extended base matrix with N rows and E columns
  • the embodiment of the present application expresses the extended base matrix through the unit matrix and the matrix shown in Fig. It is better to assist in drawing the Tanner diagram, thereby assisting in the decoding of the belief propagation (BP) algorithm.
  • the extended matrix is represented by H NE
  • the receiving end can also autonomously add the unit matrix S NN when decoding.
  • the embodiment of the present application also provides a method for generating an extended base matrix.
  • the double-nesting property of the extended base matrix shown in the embodiment of the present application can be realized by using a tree search algorithm based on the QC matrix.
  • the method for generating the extended basis matrix shown in the embodiment of the present application may be implemented by the transmitting end, or may be implemented by the receiving end, etc., which is not limited in the embodiment of the present application.
  • the extended basis matrix is implemented by the sending end, and the sending end may send the information of the extended basis matrix to the receiving end.
  • the extended basis matrix is implemented by the receiving end, and the receiving end may send the information of the extended basis matrix to the transmitting end.
  • the extended base matrix shown in the embodiment of the present application may also be predefined by a protocol or standard, which is not limited in the embodiment of the present application.
  • FIG. 5c and FIG. 5d are schematic flowcharts of a method for generating an extended basis matrix provided by an embodiment of the present application.
  • L represents the search width, for example, the search width can be understood as the number of initialized random matrices and the like.
  • D max and D min represent the maximum and minimum column weights of the extended basis matrix, respectively;
  • E 0 represents the maximum number of columns of the extended basis matrix;
  • maxIter represents the protograph-based extrinsic information transfer, PEXIT) the maximum number of iterations adopted;
  • Z represents the expansion factor (lifting size) of the QC matrix corresponding to the extended base matrix;
  • N 0 represents the maximum number of rows of the extended base matrix;
  • K represents the length of the first bit sequence (also can understood as the length of information bits, etc.);
  • e represents the number of columns of the currently generated extended basis matrix.
  • Figure 5c and Figure 5d show the progressive tree search process.
  • the expansion factor Z in FIG. 5c and FIG. 5d may also be a prime number.
  • the method for generating the extended base matrix includes: generating L QC matrices according to the input parameters L, D max , D min , E 0 , maxIter, Z, N 0 and K, the L QC matrices
  • the QC matrix can be understood as the first column of the initialized extended basis matrix.
  • L QC matrices with N 0 rows and 1 column can be randomly generated on the basis of the above L QC matrices according to the maximum column weight, the minimum column weight and the expansion factor.
  • L QC matrices For example, according to the above L QC matrices, another matrix is randomly generated on the basis of each matrix, that is, L*L QC matrices are obtained. Then the SC decoding performance of L*L QC matrices (just an example), and keep the top L QC matrices with the best performance. In this way, when the column number e of the current matrix is equal to E 0 , the extended base matrix with N 0 rows and E 0 columns with the best performance is output.
  • the method for generating the extended basis matrix includes:
  • L QC matrices without four rings may be randomly generated according to a shifting value.
  • L QC matrices without four rings may be randomly generated according to column weights. For example, if the column weight ranges from 1 to 9, it means that the range of the column weight of L randomly generated QC matrices with N 0 rows and 1 column is greater than or equal to 1 and less than or equal to 9.
  • the generated QC matrix is tetracyclic-free according to the lifting size and the translation value.
  • the embodiments of the present application will not be described in detail.
  • the L QC matrices may also be sorted according to performance (for example, according to SC decoding performance).
  • the QC matrix obtained by sorting the performance from good to bad is (About the method shown in Figure 5d, it is taken as an example to perform good or bad performance sorting). It can be understood that the form of the matrix with the best performance in the L QC matrices shown in Figure 5d (the form in the description of the accompanying drawing) is the same as It should not be construed as a limitation on the embodiment of the present application.
  • progressive formula obtains the QC matrix of L N 0 rows E 0 columns
  • the extended matrix shown in the present application is illustrated with N rows and E columns as an example, the transposition matrix of the extended matrix, such as a matrix with E rows and N columns, or the displacement of the extended matrix (such as right shift or Leftward matrix) matrix, or the rotation and other transformations of the extended matrix, all belong to the protection scope of the present application.
  • the deformation of the extended basis matrix also belongs to the protection scope of the present application.
  • the column weight of each column in the extended matrix satisfies any one or more of the following relationships: negatively correlated with E, positively correlated with K, negatively correlated with N, and K/N (that is, the code rate of the first channel coding) are positively correlated.
  • the obtained relationship can be: the row weight of each row in the extended matrix satisfies any one or more of the following relations: negatively correlated with E, positively correlated with K, and positively correlated with N It is negatively correlated and positively correlated with K/N (that is, the code rate of the first channel coding).
  • the method of E check bits obtained by expanding the matrix shown above can also obtain the E check bits through the check matrix of Luby transform LDPC (Luby transform-LDPC, LT-LDPC) code or LT code. bits, or the E check bits are obtained through the generation matrix of the LT-LDPC code.
  • Luby transform LDPC Luby transform-LDPC, LT-LDPC
  • bits, or the E check bits are obtained through the generation matrix of the LT-LDPC code.
  • the sending end needs to perform first channel coding on the first bit sequence.
  • the sending end may perform first channel coding on the first bit sequence according to the first reliability sequence.
  • the positions of the K information bits shown in Figure 4a are determined according to the first reliability sequence, the length of the first reliability sequence is N, the first reliability sequence is a subsequence of the second reliability sequence, and the second The length of the reliability sequence is N max , where N max is greater than or equal to N.
  • FIG. 6a is a schematic diagram of decoding performance corresponding to a sequence of different structures provided by the embodiment of the present application.
  • Fig. 6a respectively shows the decoding performance comparison among the online construction sequence, the offline construction sequence shown in this application, the NR polar construction sequence and the polarization weight (polarization weight, PW) construction sequence.
  • the performance of the second reliability sequence provided by the embodiment of the present application is the best, and the performance of the second reliability sequence can also be close to the sequence obtained by online construction.
  • the second reliability sequence in this embodiment of the present application may support a maximum code length N max and/or support a maximum number of parity bits E max .
  • the second reliability sequence may also support different expansion factors, for example, the second reliability sequence may support the largest expansion factor Z max .
  • the sending end may perform first channel coding on the first bit sequence according to a set of the same first reliability sequence.
  • the second reliability sequence can be shown in Table 1, where is the number of bits before the first channel coding.
  • second reliability sequence is based on reliability A sequence sorted in ascending order, where, is the bit number the corresponding reliability.
  • the second reliability sequence can be shown in Table 2, where is the number of bits before the first encoding.
  • second reliability sequence is based on reliability A sequence sorted in ascending order, where, is the bit number the corresponding reliability.
  • the channels corresponding to N bits are no longer independent and identically distributed.
  • the check bits are strengthened compared with one or more bits among the N bits participating in the check, thus causing differences in the reliability of the N bits.
  • the more verification relationships one bit among the N bits participates in the higher the reliability of the virtual channel corresponding to this one bit will be. That is to say, the reliability of N bits is related to the column weight of the extended matrix.
  • the enhanced N-bit channel also exhibits a block-wise characteristic, that is, the reliability within a block is the same, and the reliability among blocks is different.
  • the block size is equal to the lifting size of the extended base matrix.
  • Fig. 6b is a schematic diagram of reliability differences and block characteristics between bit channels provided by the embodiment of the present application. As shown in FIG. 6b, the check relationship between N bits and E check bits can be obtained according to the check relationship between check nodes and variable nodes. The reliability among the N bits included in the second bit sequence obtained by coding with the polar code may be as shown on the right side of FIG. 6b.
  • FIG. 6b shows that the length of the second bit sequence is 1024, the code rate of the first channel coding is 0.75, and the extension factor is 16 as an example. It can be understood that since the extension factor is 16, each column shown in FIG. 6b can represent 16 bits. It can be understood that for the relationship between the N bits and the E parity bits on the left side of FIG. 6b, reference can be made to FIG. 6c. It can be understood that the reliability among different bits shown in Fig. 6b is only an example.
  • Table 1 and Table 2 are reliability sequences shown in an offline construction mode, and an embodiment of the present application also provides an online construction mode.
  • the sending end can determine the reliability of each of the N positions according to the channel state and the spreading matrix, and the reliability of a position is positively correlated with the number of parity bits involved; and according to the reliability of the N positions A first reliability sequence is determined from low to high; and first channel coding is performed on K information bits according to the first reliability sequence.
  • the channel state may be a channel state between the sending end and the receiving end.
  • the online construction sequence shown in the embodiment of the present application may be a function of N, K, E, and Z. That is, the online construction sequence is not only related to N and K, but also related to E and Z.
  • the method for constructing the first reliability sequence online may be as follows:
  • the mean ⁇ i is sorted from low to high to get as follows
  • the length of the second bit sequence is 8, that is, c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8
  • the extended basis matrix is as follows:
  • Fig. 6d is a schematic diagram of a relationship between an extended matrix and a first reliability sequence provided by an embodiment of the present application.
  • p 1 +c 2 +c 5 +c 8 0 in the binary domain
  • p 2 c 1 +c 6 +c 7 .
  • FIG. 6d only exemplarily shows the relationship between some parity bits and N bits.
  • c 1 and c 2 both participate in one check bit
  • c 3 and c 4 both participate in two check bits
  • c 5 and c 6 both participate in three check bits
  • c 7 and c 8 correspond to the same block, the reliability of the positions corresponding to c 7 and c 8 same.
  • FIG. 6d is a schematic diagram for illustrating the relationship between the extension matrix and the first reliability sequence, and this embodiment of the present application does not limit the extension matrix shown in FIG. 6d.
  • the virtual channels corresponding to N bits have different reliability, and the optimized construction sequence is obtained by sorting these channels according to the reliability from low to high. Therefore, a corresponding inner interleaver is also required in the encoding and decoding processes. That is, in the method shown in Figure 4a, the transmitting end can perform the first channel coding on the first bit sequence according to the inner interleaver sequence, the inner interleaver sequence is determined according to the extension matrix, and the block size of the inner interleaver sequence is equal to the extension The expansion factor for the matrix.
  • the inner interleaver sequence reference may be made to the above description about the first reliability sequence, which will not be described in detail here.
  • the inner interleaver sequence may have the feature of block-wise interleaving, such as interleaving between blocks in order of reliability from low to high, interleaving or non-interleaving within a block, and block size may be equal to lifting size.
  • block-wise interleaving such as interleaving between blocks in order of reliability from low to high, interleaving or non-interleaving within a block
  • block size may be equal to lifting size.
  • the corresponding row in the first matrix is punctured/shortened; or, the row with the largest row weight (Z ⁇ N 0 -N) in the extended matrix is punctured to obtain a code length of N
  • the number of rows H N of the expansion matrix is punctured/shortened.
  • each column of the H perm corresponds to one parity bit.
  • the first column of the expansion matrix adapted to the code rate of the first channel coding can be intercepted by shifting to the right, and different code lengths can be adapted through rate matching.
  • FIG. 7a is a schematic diagram of a comparison of decoding performance between a coding method proposed in the present application and a polar code coding method provided in an embodiment of the present application. It can be understood that Fig. 7a shows a performance comparison between the encoding method proposed in the present application and the polar code encoding method using long code extension.
  • the abscissa represents SNR, such as expressed by Es/N0, and the unit is dB; the ordinate represents BLER.
  • QPSK quadrature phase shift keying
  • AWGN additive white gaussian noise
  • the polar code long code extension construction is based on the PW sequence, and the rate matching adopts BIV+Shorten extension; the encoding method proposed in this application adopts the off-line optimization sequence shown in Table 1, and the extension matrix H is shown in Figure 5a.
  • Fig. 7b is a schematic diagram of a comparison of the decoding performance of the repeated coding of the coding method proposed in the present application and the polar code coding method provided by the embodiment of the present application. It can be understood that Fig. 7b shows a performance comparison between the encoding method proposed in this application and the polar code encoding method using repetition extension.
  • the abscissa represents SNR, such as expressed by Es/N0, and the unit is dB; the ordinate represents BLER.
  • the polar code code repetition expansion construction adopts NR sequence, and the rate matching adopts the repeated expansion of repeated bits from the back to the front;
  • the encoding method proposed in this application adopts the off-line optimization sequence shown in Table 1, and the expansion matrix H is shown in Figure 5a Show.
  • the second channel coding method proposed in this application can also be called EF-polar code coding method.
  • the second decoding method proposed in this application can also be It can be called EF-polar code decoding method.
  • the second channel encoding method and the second channel decoding method proposed in this application may be collectively referred to as EF-polar codes.
  • Fig. 8 is a schematic flow chart of a decoding method provided by an embodiment of the present application. As shown in Fig. 8, the decoding method includes:
  • the receiving end obtains a second sequence to be decoded, the second sequence to be decoded includes information of N bits and information of E check bits, where N is an integer greater than or equal to 1, and E is greater than or equal to Integer of 1.
  • the receiving end obtaining the second sequence to be decoded means that the receiving end can process the received sequence, and then obtain the second sequence to be decoded. For example, the receiving end may perform processing such as demodulation on the received sequence to obtain the second sequence to be decoded.
  • the information of E check bits can be understood as a soft information sequence after E check bits pass through a channel; or, the information of N bits can be understood as a soft information sequence after N bits pass through a channel. It can be understood that the information of N bits included in the first sequence to be decoded may be the same as or different from the information of N bits included in the second sequence to be decoded.
  • the receiving end performs second channel decoding on the second sequence to be decoded according to the extension matrix to obtain the first sequence to be decoded.
  • the extension matrix includes N rows and E columns.
  • the extension matrix is obtained according to the extension base matrix, and the extension base
  • the matrix includes N 0 rows and E 0 columns, the first sequence to be decoded includes N bits of information, and both E 0 and N 0 are integers greater than or equal to 1.
  • the receiving end performs first channel decoding on the first sequence to be decoded according to the first reliability sequence to obtain a first bit sequence, the length of the first reliability sequence is N, and the first reliability sequence is the second A subsequence of the reliability sequence, the length of the second reliability sequence is N max , N max is greater than or equal to N, and the first bit sequence includes K information bits.
  • the following uses a large iterative decoding process as an example to illustrate the decoding method provided by the embodiment of the present application.
  • the decoding method shown below should not be construed as limiting the embodiment of the present application.
  • the receiving end it can input: received sequence y 1 , y 2 , ..., y T , T is the length of the received sequence; encoding parameters: target code length M, number of parity bits E, extension matrix H, inner interleaver sequence I, the first reliability sequence (according to the first reliability sequence, the message position indicator sequence B can be obtained, the position of 0 in the sequence B represents the frozen bit, and the position of 1 represents the information bit), Puncturing mode Q, CRC polynomial crc_poly; decoding parameters: BP decoding maximum iteration number ITER max , CRC-aided SCL (CRC-Aided SCL, CA-SCL) decoding list dimension List.
  • the List shown here may be equal to any value in ⁇ 1, 2, 4, 8, 16, 32 ⁇ .
  • the information sequence output by the receiving end includes information bits as an example, for example, the information sequence output by the receiving end also includes frozen bits.
  • the receiving end may also output N bits, and the N bits include K information bits and NK frozen bits.
  • the soft value L s and the soft value L c shown above may also be referred to as the soft value L EF , that is, the soft value L EF includes the soft value L s and the soft value L c .
  • FIG. 9a is a schematic flowchart of a large iterative decoding provided by the embodiment of the present application.
  • FIG. 9b is a schematic diagram of a decoding method provided by an embodiment of the present application.
  • the receiving end obtains the received sequence y 1 , y 2 , ..., y M (that is, the second sequence to be decoded shown above), and it can be understood that M shown here represents the length of the received symbol.
  • the received sequence of N bits (that is, the first sequence to be decoded shown above) is obtained by LDPC decoding (LDPC Dec), and the decoding of N bits is obtained by polar code decoding (polar Dec)
  • LDPC Dec LDPC Dec
  • polar Dec polar code decoding
  • LDPC decoding and polar code decoding are performed again according to the external information lex 1 ,..., lex N until the decoding is correct or ITER max is reached, and the best decoding is output Code path u 1 ,...,u K .
  • L s and L c can also be output.
  • FIG. 9a and FIG. 9b are only examples, and should not be construed as limiting the embodiment of the present application.
  • the above-mentioned LDPC decoding and polar code decoding are only examples of the embodiments of the present application, and the specific methods of the second channel decoding and the first channel decoding are not limited.
  • the method provided by the embodiment of this application can assist the decoding of N bits through the soft value generated by E check bits, and supports an early-stop decoding strategy, that is, LDPC Dec iterates one round at a time, and then decodes The result is sent to Polar Dec for decoding, the maximum number of trial rounds allowed is ITER max , and the stop condition is reaching ITER max or Polar Dec decoding is successful.
  • the EF-polar code provided by this application not only maintains the characteristics of strong structure and high decoding efficiency of polar codes, but also has the advantages of flexible code length extension and easy generation of soft values of LDPC codes, effectively integrating LDPC codes and NR codes. Advantages of polar codes.
  • the online construction of repetitive coding and long code coding adopts natural order (nature, NAT)+Puncture+Gaussian approximation (gaussian Approximition, GA), and the online construction of the coding method proposed in the embodiment of the present application can be given in the above-mentioned embodiment Online construction process.
  • the offline construction of repeated coding adopts 5G NR offline sequence
  • the offline construction of long code coding adopts bit reversal (bit reversal, BIV)+Shorten+polarization weight (polarization weight, PW)
  • the optimized offline sequences in Table 1 or Table 2 were used for offline construction.
  • the modulation method is QPSK.
  • Fig. 9d shows the performance comparison under the online configuration when the code length is the same and the code rate is different.
  • Figure 9e shows the performance comparison under the online configuration when the code length is different and the code rate is the same.
  • Figure 9f shows the performance comparison under the off-line configuration when the code length is the same and the code rate is different.
  • Figure 9g shows the performance comparison under the off-line configuration when the code length is different and the code rate is the same.
  • the encoding method proposed in the embodiment of the present application is superior to the repeated encoding method, and at the same time, the performance of the encoding method proposed in the embodiment of the present application has a small gap with the performance of long code encoding, and in some scenarios Even better than long code performance.
  • the coding method proposed in the embodiment of the present application not only has a relatively large coding gain, but is especially better than long code coding under SC or CA-SCL8 decoding performance.
  • Fig. 10 is a schematic diagram of an encoding method and a decoding method provided by an embodiment of the present application.
  • the sender can perform first channel coding on K information bits such as u 1 ,...,u K to obtain a second bit sequence such as c 1 , c 2 ...,c N ; and then obtain through inner interleaving Sequence d 1 , d 2 ..., d N (such as obtained by the inner interleaver sequence); second channel coding is performed on the sequence d 1 , d 2 ..., d N to obtain a third bit sequence such as x 1 , x 2 ... ,x N ,x N+1 ,...,x N+E .
  • first channel coding and the second channel coding shown in FIG. 10 may be implemented by different encoders, or the first channel encoding and the second channel encoding may also be implemented by one encoder.
  • the first channel coding, inner interleaving, and second channel coding shown in FIG. 10 may also be called coding, as shown by the dotted line in FIG. 10 .
  • the receiving end obtains the received sequence r 1 , r 2 ..., r T through the channel, where T is the length of the received sequence.
  • T is the length of the received sequence.
  • the receiving end demodulates the received sequence to obtain the second to-be-decoded sequence y 1 , y 2 ..., y M , and then performs second channel decoding on the second to-be-decoded sequence y 1 , y 2 ..., y M code and the first channel decoding to obtain K information bits.
  • the receiving end obtains K information bits after demodulating and decoding the received sequence.
  • the first channel decoding and the second channel decoding can be realized by one decoder, or the first channel decoding and the second channel decoding can also be realized by different decoders. Examples are not limited.
  • both demodulation and decoding may be implemented by the same device, which is not limited in this embodiment of the present application.
  • using polar codes to generate N bits of EF-polar codes can obtain better error correction performance than NR polar codes.
  • Using the extension matrix to generate the parity bits of the EF-polar code can extend the code length more flexibly and generate soft values more easily.
  • the use of large iterative decoding can generate corresponding soft values while generating information bit estimates, so it is more suitable for scenarios such as multi-user detection in data channels; and the EF-polar decoding strategy proposed by this application has The feature of early stopping can effectively reduce the decoding delay and decoding complexity.
  • the encoding method and decoding method shown above in this application can also be applied to the data packet level, that is, the N bits shown above can be a data block at the data packet level.
  • the verification data packet can also be extended by Matrix generation.
  • the present application divides the communication device into functional modules according to the above method embodiments.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in this application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.
  • the communication device according to the embodiment of the present application will be described in detail below with reference to FIG. 11 to FIG. 13 .
  • FIG. 11 is a schematic structural diagram of a communication device provided by an embodiment of the present application. As shown in FIG. 11 , the communication device includes a processing unit 1101 and a transceiver unit 1102 .
  • the communication device may be the sending end or a chip in the sending end shown above. That is, the communication device can be used to perform the steps or functions performed by the sending end in the above method embodiments.
  • the processing unit 1101 is configured to obtain a first bit sequence and a target code length M; perform first channel coding on the first bit sequence to obtain a second bit sequence; perform second channel coding according to the second bit sequence to obtain a third bit sequence;
  • a processing unit 1101 configured to output a third bit sequence.
  • the acquisition of the first bit sequence by the processing unit 1101 may also include: the processing unit 1101 performs data processing on the data to be processed input by the transceiver unit 1102 to obtain the first bit sequence; or, the processing unit 1101 acquires the first bit sequence through the transceiver unit 1102.
  • the bit sequence and the like are not limited in this embodiment of the present application.
  • the processing unit 1101 is specifically configured to perform second channel coding according to the second bit sequence and the spreading matrix.
  • the processing unit 1101 is specifically configured to perform first channel coding on the first bit sequence according to the inner interleaver sequence.
  • the first bit sequence, the second bit sequence, the third bit sequence, the first channel coding, the second channel coding, the spreading matrix, the spreading base matrix, the first reliability sequence and the second reliability sequence For the description of etc., reference may be made to the method embodiments shown above, which will not be described in detail here. Exemplarily, reference may be made to FIGS. 5 a to 5 d for descriptions about the extension matrix and the extension base matrix, and reference may be made to FIGS. 6 a to 6 d for the first reliability sequence and the second reliability sequence.
  • the processing unit 1101 may also be configured to execute the steps or functions of generating the extended basis matrix shown in FIG. 5c and FIG. 5d .
  • the communication device may be the receiving end or a chip in the receiving end shown above. That is, the communication device can be used to perform the steps or functions performed by the receiving end in the above method embodiments.
  • the processing unit 1101 is configured to acquire a second sequence to be decoded; perform second channel decoding on the second sequence to be decoded according to the spreading matrix to obtain a first sequence to be decoded; and obtain the second sequence to be decoded according to the first reliability sequence
  • a sequence to be decoded is subjected to first channel decoding to obtain a first bit sequence.
  • the processing unit 1101 shown above which is used to obtain the second sequence to be decoded, can also be understood as: the transceiver unit 1102, which is used to input data to be processed (such as a receiving sequence); The data is processed to obtain a second sequence to be decoded; or, the processing unit 1101 obtains the third sequence to be decoded from other devices or components through the transceiver unit 1102 .
  • the processing unit 1101 is specifically configured to perform first channel decoding on the first sequence to be decoded according to the first reliability sequence and the inner interleaver sequence.
  • the first bit sequence, the first sequence to be decoded, the second sequence to be decoded, the first channel coding, the second channel coding, the spreading matrix, the spreading base matrix, the first reliability sequence and the second For descriptions of the two reliability sequences, etc., reference may be made to the method embodiments shown above, and details will not be detailed here. Exemplarily, reference may be made to FIGS. 5 a to 5 d for descriptions about the extension matrix and the extension base matrix, and reference may be made to FIGS. 6 a to 6 d for the first reliability sequence and the second reliability sequence.
  • the processing unit 1101 may also be configured to execute steps or functions of the decoding method shown in FIG. 9a and FIG. 9b .
  • the processing unit 1101 may be one or more processors
  • the transceiver unit 1102 may be a transceiver, or the transceiver unit 1102 may also be a sending unit and a receiving unit
  • the sending unit may be a transmitter
  • the receiving unit may be a receiver
  • the sending unit and the receiving unit are integrated into one device, such as a transceiver.
  • the processor and the transceiver may be coupled, and the connection manner of the processor and the transceiver is not limited in the embodiment of the present application.
  • the communication device 120 includes one or more processors 1220 and a transceiver 1210 .
  • the processor 1220 is configured to obtain a first bit sequence and a target code length M; perform a first channel operation on the first bit sequence Encoding to obtain a second bit sequence; performing second channel coding according to the second bit sequence to obtain a third bit sequence; and outputting the third bit sequence.
  • the processor 1220 is configured to acquire a second sequence to be decoded; Two-channel decoding to obtain a first sequence to be decoded; and performing first channel decoding on the first sequence to be decoded according to a first reliability sequence to obtain a first bit sequence.
  • the first bit sequence, the first sequence to be decoded, the second sequence to be decoded, the first channel coding, the second channel coding, the spreading matrix, the spreading base matrix, the first reliability sequence and the second For descriptions of the two reliability sequences, etc., reference may be made to the method embodiments shown above, and details will not be detailed here.
  • the transceiver may include a receiver and a transmitter, the receiver is used to perform a function (or operation) of reception, and the transmitter is used to perform a function (or operation) of transmission ). And the transceiver is used to communicate with other devices/devices through the transmission medium.
  • the communication device 120 may further include one or more memories 1230 for storing program instructions and/or data.
  • the memory 1230 is coupled to the processor 1220 .
  • the coupling in the embodiments of the present application is an indirect coupling or a communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information exchange between devices, units or modules.
  • Processor 1220 may cooperate with memory 1230 .
  • Processor 1220 may execute program instructions stored in memory 1230 .
  • at least one of the above one or more memories may be included in the processor.
  • any one or more items of the extended basis matrix or the second reliability sequence may be stored in the memory 1230 . Exemplarily, the memory shown in FIG.
  • the dotted line in FIG. 12 indicates that the extended basis matrix and the second reliability sequence are stored in the memory, because the extended basis matrix and the second reliability sequence may be stored in the memory, or only the extended basis matrix may be stored, or The extended basis matrix, the second reliability sequence, etc. are not stored.
  • a specific connection medium among the transceiver 1210, the processor 1220, and the memory 1230 is not limited.
  • the memory 1230, the processor 1220, and the transceiver 1210 are connected through a bus 1240.
  • the bus is represented by a thick line in FIG. 12, and the connection between other components is only for schematic illustration. , is not limited.
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 12 , but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc., and may realize Or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.
  • a general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the memory may include but not limited to hard disk drive (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD) and other non-volatile memory, random access memory (Random Access Memory, RAM), Erasable Programmable ROM (EPROM), Read-Only Memory (ROM) or Portable Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), etc.
  • the memory is any storage medium that can be used to carry or store program codes in the form of instructions or data structures, and can be read and/or written by a computer (such as the communication device shown in this application, etc.), but is not limited thereto.
  • the memory in the embodiment of the present application may also be a circuit or any other device capable of implementing a storage function, and is used for storing program instructions and/or data.
  • the processor 1220 is mainly used to process communication protocols and communication data, control the entire communication device, execute software programs, and process data of the software programs.
  • the memory 1230 is mainly used to store software programs and data.
  • the transceiver 1210 may include a control circuit and an antenna, and the control circuit is mainly used for converting a baseband signal to a radio frequency signal and processing the radio frequency signal.
  • Antennas are mainly used to send and receive radio frequency signals in the form of electromagnetic waves.
  • Input and output devices, such as touch screens, display screens, and keyboards, are mainly used to receive data input by users and output data to users.
  • the processor 1220 can read the software program in the memory 1230, interpret and execute the instructions of the software program, and process the data of the software program.
  • the processor 1220 performs baseband processing on the data to be sent, and then outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 1220, and the processor 1220 converts the baseband signal into data and processes the data deal with.
  • the radio frequency circuit and the antenna can be set independently from the processor for baseband processing.
  • the radio frequency circuit and antenna can be arranged remotely from the communication device. .
  • the communication device shown in the embodiment of the present application may have more components than those shown in FIG. 12 , which is not limited in the embodiment of the present application.
  • the method performed by the processor and the transceiver shown above is only an example, and for the specific steps performed by the processor and the transceiver, reference may be made to the method introduced above.
  • the processing unit 1101 may be one or more logic circuits, and the transceiver unit 1102 may be an input-output interface, or a communication interface, or an interface circuit , or interfaces and so on.
  • the transceiver unit 1102 may also be a sending unit and a receiving unit, the sending unit may be an output interface, and the receiving unit may be an input interface, and the sending unit and the receiving unit are integrated into one unit, such as an input and output interface.
  • the communication device shown in FIG. 13 includes a logic circuit 1301 and an interface 1302 .
  • the above-mentioned processing unit 1101 can be realized by a logic circuit 1301
  • the transceiver unit 1102 can be realized by an interface 1302 .
  • the logic circuit 1301 may be a chip, a processing circuit, an integrated circuit or a system on chip (SoC) chip, etc.
  • the interface 1302 may be a communication interface, an input/output interface, or a pin.
  • FIG. 13 takes the aforementioned communication device as a chip as an example, and the chip includes a logic circuit 1301 and an interface 1302 .
  • the logic circuit and the interface may also be coupled to each other.
  • the embodiment of the present application does not limit the specific connection manner of the logic circuit and the interface.
  • the logic circuit 1301 when the communication device is used to execute the method or function or step performed by the sending end, the logic circuit 1301 is used to obtain the first bit sequence; the logic circuit 1301 is also used to perform the first channel on the first bit sequence encoding to obtain a second bit sequence; and performing second channel coding according to the second bit sequence to obtain a third bit sequence; the interface 1302 is also used to output the third bit sequence.
  • the logic circuit 1301 shown above is used to obtain the first bit sequence; it can also be understood as: the logic circuit 1301 is used to input the data to be processed through the interface 1302, and process the data to be processed to obtain the first bit sequence.
  • the first bit sequence may be input to the logic circuit from other devices or components through the interface, or may be obtained by the logic circuit after processing other data input by the interface, which is not limited in this embodiment of the present application.
  • the interface shown above is used to output the third bit sequence, and can also be understood as: a logic circuit, which controls the interface to output the third bit sequence; or, a logic circuit, which is used to perform other processing on the third bit sequence Afterwards, the sequence obtained after processing the third bit sequence is output through the interface.
  • the logic circuit 1301 when the communication device is used to execute the method or function or step performed by the receiving end, the logic circuit 1301 is configured to obtain a second sequence to be decoded, and perform a second sequence on the second sequence to be decoded according to the spreading matrix. channel decoding to obtain a first bit sequence to be decoded; and performing first channel decoding on the first sequence to be decoded according to the first reliability sequence to obtain a first bit sequence.
  • the logic circuit 1301 shown above is used to obtain the second sequence to be decoded; it can also be understood as: the interface 1302 is used to input the data to be processed (such as the received sequence obtained through the channel, etc.), the logic circuit 1301 , process the data to be processed input by the interface 1302 to obtain a second sequence to be decoded; or, the logic circuit 1301 inputs the second sequence to be decoded through the interface 1302 and the like.
  • the communication device further includes a memory 1303, which can be used to store one or more items of the extended basis matrix or the second reliability sequence.
  • the communication device shown in the embodiment of the present application may implement the method provided in the embodiment of the present application in the form of hardware, or may implement the method provided in the embodiment of the present application in the form of software, which is not limited in the embodiment of the present application.
  • the first bit sequence the second bit sequence, the third bit sequence, the first sequence to be decoded, the second sequence to be decoded, the first channel coding, the second channel coding, the spreading matrix, the spreading base matrix, the first reliable
  • the degree sequence and the second reliability sequence etc., reference may be made to the method embodiments shown above, and details will not be detailed here.
  • An embodiment of the present application also provides a wireless communication system, the wireless communication system includes a sending end and a receiving end, and the sending end and the receiving end may be used to execute the method in any of the preceding embodiments.
  • the present application also provides a computer program, which is used to realize the operation and/or processing performed by the sending end in the method provided in the present application.
  • the present application also provides a computer program, which is used to implement the operations and/or processing performed by the receiving end in the method provided in the present application.
  • the present application also provides a computer-readable storage medium, where computer code is stored in the computer-readable storage medium, and when the computer code is run on the computer, the computer is made to perform the operations performed by the sender in the method provided by the present application and/or or process.
  • the present application also provides a computer-readable storage medium, in which computer code is stored, and when the computer code is run on the computer, the computer is made to perform the operations performed by the receiving end in the method provided by the present application and/or or process.
  • the present application also provides a computer program product, the computer program product includes computer code or computer program, when the computer code or computer program is run on the computer, the operation performed by the sender in the method provided by the present application and/or Processing is performed.
  • the present application also provides a computer program product, the computer program product includes computer code or computer program, when the computer code or computer program is run on the computer, the operation performed by the receiving end in the method provided by the present application and/or Processing is performed.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to realize the technical effects of the solutions provided by the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the storage medium includes several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned readable storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk, etc., which can store program codes. medium.

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Abstract

本申请公开了一种编码方法、译码方法及装置，该编码方法包括：获取第一比特序列和目标码长M；然后对该第一比特序列进行第一信道编码，获得第二比特序列，以及根据该第二比特序列进行第二信道编码，获得第三比特序列；输出该第三比特序列。其中，第一比特序列包括K个信息比特，第二比特序列包括N个比特，第三比特序列包括N个比特和E个校验比特，M>N，且E＝M-N。上述M、K、N和E均为大于或等于1的整数。该编码方法能够根据不同的M灵活地扩展码长，提高了码长扩展的灵活性。

Description

编码方法、译码方法及装置
本申请要求于2021年09月30日提交中国专利局、申请号为202111173210.7、申请名称为“编码方法、译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种编码方法、译码方法及装置。
背景技术
作为一种能够证明可以“达到”香农信道容量的信道编码方案，极化码兼具了代数编码结构和概率译码的特点。一般的，极化码可以用于控制信道编码。而数据信道编码则采用低密度奇偶校验(low-density parity check，LDPC)码。由于极化码的码长不易灵活扩展，因此限制了其在数据信道上的应用。
因此，如何将极化码的编码方式应用于数据信道上亟待解决。
发明内容
本申请提供一种编码方法、译码方法及装置，能够根据不同的M灵活地扩展码长，提高了码长扩展的灵活性。
第一方面，本申请实施例提供一种编码方法，所述方法包括：
获取第一比特序列和目标码长M，所述第一比特序列包括K个信息比特，所述K为大于或等于1的整数，所述M为大于或等于1的整数；对所述第一比特序列进行第一信道编码，获得第二比特序列，所述第二比特序列包括N个比特，所述N为大于或等于1的整数；根据所述第二比特序列进行第二信道编码，获得第三比特序列，所述第三比特序列包括所述N个比特和E个校验比特，所述E为大于或等于1的整数，M>N，且E＝M-N；输出所述第三比特序列。
发送端根据给定发送码长M以及N确定出校验比特数E，从而进行第二信道编码，获得E个校验比特。本申请实施例提供的方法，能够根据不同的M灵活地扩展码长，如扩展出E个校验比特，提高了码长扩展的灵活性。尤其是对于极化码编码来说，本申请实施例提供的方法，不仅能够结合极化码编码的优点，还能够灵活地扩展码长，从而使得极化码编码能够更灵活地应用于数据信道上。
在一种可能的实现方式中，所述根据所述第二比特序列进行第二信道编码包括：根据所述第二比特序列和扩展矩阵进行第二信道编码，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述E 0和所述N 0都是大于或等于1的整数。
在一种可能的实现方式中，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
在一种可能的实现方式中，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
在一种可能的实现方式中，Z＝16。
在一种可能的实现方式中，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，所述扩展矩阵的E列是第一矩阵中相邻 的E列，所述第一矩阵中相邻的E列是根据第一信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
在一种可能的实现方式中，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
在一种可能的实现方式中，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中第一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中至少两列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中每一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述K个信息比特的位置根据第一可靠度序列确定，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N。
在一种可能的实现方式中，所述第二可靠度序列满足如下关系：
Figure PCTCN2022116922-appb-000001
Figure PCTCN2022116922-appb-000002
Figure PCTCN2022116922-appb-000003
其中，
Figure PCTCN2022116922-appb-000004
为可靠度序列，其中元素是子信道的序号，
Figure PCTCN2022116922-appb-000005
表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
在一种可能的实现方式中，所述对所述第一比特序列进行第一信道编码包括：根据信道状态和所述扩展矩阵确定N个位置上每个位置的可靠度，一个位置的可靠度与参与的校验比特的数量成正相关；根据所述N个位置的可靠度从低到高的顺序确定第一可靠度序列；根据所述第一可靠度序列对所述第一比特序列进行第一信道编码。
在一种可能的实现方式中，所述对所述第一比特序列进行第一信道编码包括：根据内交织器序列对所述第一比特序列进行第一信道编码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
第二方面，本申请实施例提供一种译码方法，所述方法包括：
获取第二待译码序列，所述第二待译码序列包括N个比特的信息和E个校验比特的信息，所述N为大于或等于1的整数，所述E为大于或等于1的整数；根据扩展矩阵对所述第二待 译码序列进行第二信道译码，获得第一待译码序列，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述第一待译码序列包括所述N个比特的信息，所述E 0和所述N 0都是大于或等于1的整数；根据第一可靠度序列对所述第一待译码序列进行第一信道译码，获得第一比特序列，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N，所述第一比特序列包括K个信息比特。
示例性的，E个校验比特的信息可以理解为是E个校验比特经过信道后的软信息序列，N个比特的信息可以理解为是N个比特经过信道后的软信息序列。可理解，第一待译码序列中包括的N个比特的信息与第二待译码序列中包括的N个比特的信息可能相同，也可能不同。
可理解，以上所示的方法中，第一可靠度序列是第二可靠度序列的子序列。然而，本申请实施例中，第一可靠度序列还可以根据扩展矩阵得到，如接收端可以通过在线构造的方法得到该第一可靠度序列。
在一种可能的实现方式中，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
在一种可能的实现方式中，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
在一种可能的实现方式中，Z＝16。
在一种可能的实现方式中，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，所述扩展矩阵的E列是第一矩阵中相邻的E列，所述第一矩阵中相邻的E列是根据第一信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
在一种可能的实现方式中，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
在一种可能的实现方式中，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中第一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中至少两列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述扩展矩阵中每一列的列重满足如下关系中的任一项或多项：与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
在一种可能的实现方式中，所述第二可靠度序列满足如下关系：
Figure PCTCN2022116922-appb-000006
Figure PCTCN2022116922-appb-000007
Figure PCTCN2022116922-appb-000008
Figure PCTCN2022116922-appb-000009
其中，
Figure PCTCN2022116922-appb-000010
为可靠度序列，其中元素是子信道的序号，
Figure PCTCN2022116922-appb-000011
表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
在一种可能的实现方式中，所述根据第一可靠度序列对所述第一待译码序列进行第一信道译码包括：根据所述第一可靠度序列和内交织器序列对所述第一待译码序列进行第一信道译码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
第三方面，本申请实施例提供一种通信装置，用于执行第一方面或第一方面的任意可能的实现方式中的方法。该通信装置包括具有执行第一方面或第一方面的任意可能的实现方式中的方法的单元。
示例性的，该通信装置可以为发送端或发送端中的芯片等。
第四方面，本申请实施例提供一种通信装置，用于执行第二方面或第二方面的任意可能的实现方式中的方法。该通信装置包括具有执行第二方面或第二方面的任意可能的实现方式中的方法的相应方法。
示例性的，该通信装置可以为接收端或接收端中的芯片等。
在第三方面或第四方面中，上述通信装置可以包括输入输出单元和处理单元。对于输入输出单元和处理单元的具体描述还可以参考下文示出的装置实施例。
第五方面，本申请实施例提供一种通信装置，该通信装置包括处理器，用于执行上述第一方面或第一方面的任意可能的实现方式所示的方法。或者，该处理器用于执行存储器中存储的程序，当该程序被执行时，上述第一方面或第一方面的任意可能的实现方式所示的方法被执行。
在执行上述方法的过程中，上述方法中有关发送信息或输出信息(如第三比特序列)或获取信息(如获取第一比特序列等)的过程，可以理解为由处理器输出上述信息的过程，或者处理器接收输入的上述信息的过程。在输出信息时，处理器将该上述信息输出给收发器，以便由收发器进行发射。该上述信息在由处理器输出之后，还可能需要进行其他的处理，然后才到达收发器。类似的，处理器接收输入的上述信息时，收发器接收该上述信息，并将其输入处理器。更进一步的，在收发器收到该上述信息之后，该上述信息可能需要进行其他的处理，然后才输入处理器。
基于上述原理，举例来说，前述方法中提及的获取第一比特序列可以理解为处理器接收输入的第一比特序列。前述方法中提及的输出第三比特序列可以理解为处理器输出第三比特序列等。
对于处理器所涉及的发射、发送和接收等操作，如果没有特殊说明，或者，如果未与其在相关描述中的实际作用或者内在逻辑相抵触，则均可以更加一般性的理解为处理器输出和接收、输入等操作，而不是直接由射频电路和天线所进行的发射、发送和接收操作。
在实现过程中，上述处理器可以是专门用于执行这些方法的处理器，也可以是执行存储器中的计算机指令来执行这些方法的处理器，例如通用处理器。上述存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请实施例对存储器的类型以及存储器与处理器的设置方式不做限定。可理解，对于处理器和存储器的说明同样适用于下文示出的第六方面，为简洁起见，对于处理器和存储器的说明第六方面不再详述。
在一种可能的实现方式中，存储器位于上述通信装置之外。
在一种可能的实现方式中，存储器位于上述通信装置之内。
本申请实施例中，处理器和存储器还可以集成于一个器件中，即处理器和存储器还可以被集成在一起。
示例性的，存储器可以用于存储第二可靠度序列或扩展基矩阵中的一项或多项等。
在一种可能的实现方式中，通信装置还包括收发器，该收发器，用于接收信号或发送信号。示例性的，该收发器还可以用于发送根据第三比特序列得到的序列等。
本申请实施例中，该通信装置可以为发送端或发送端中的芯片等。
第六方面，本申请实施例提供一种通信装置，该通信装置包括处理器，用于执行上述第二方面或第二方面的任意可能的实现方式所示的方法。或者，处理器用于执行存储器中存储的程序，当该程序被执行时，上述第二方面或第二方面的任意可能的实现方式所示的方法被执行。
在一种可能的实现方式中，存储器位于上述通信装置之外。
在一种可能的实现方式中，存储器位于上述通信装置之内。
在本申请实施例中，处理器和存储器还可以集成于一个器件中，即处理器和存储器还可以被集成在一起。
示例性的，存储器可以用于存储第二可靠度序列或扩展基矩阵中的任一项或多项等。
在一种可能的实现方式中，通信装置还包括收发器，该收发器，用于接收信号或发送信号。示例性的，该收发器可以用于接收序列(如图10所示的接收到的序列)等。
本申请实施例中，该通信装置可以为接收端或接收端中的芯片等。
第七方面，本申请实施例提供一种通信装置，该通信装置包括逻辑电路和接口，所述逻辑电路和所述接口耦合；所述逻辑电路，用于获取第一比特序列；所述逻辑电路，还用于对所述第一比特序列进行第一信道编码，获得第二比特序列；以及根据所述第二比特序列进行第二信道编码，获得第三比特序列；所述接口，还用于输出所述第三比特序列。其中，所述第一比特序列包括K个信息比特，所述K为大于或等于1的整数；所述第二比特序列包括N个比特，所述N为大于或等于1的整数；所述第三比特序列包括所述N个比特和E个校验比特，所述E为大于或等于1的整数，M>N，且E＝M-N；所述M为目标码长，所述M为大于或等于1的整数。
可理解，以上所示的逻辑电路，用于获取第一比特序列；还可以理解为：所述逻辑电路，用于通过所述接口输入待处理的数据，以及对该待处理的数据进行处理，获得该第一比特序列。该第一比特序列可以是通过接口从其他装置或部件中输入至逻辑电路中的，也可以是逻辑电路对接口输入的其他数据进行处理后获得的，本申请实施例对此不作限定。
在一种可能的实现方式中，所述逻辑电路，具体用于根据所述第二比特序列和扩展矩阵进行第二信道编码。其中，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述E 0和所述N 0都是大于或等于1的整数。
在一种可能的实现方式中，所述逻辑电路，具体用于根据内交织器序列对所述第一比特序列进行第一信道编码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
可理解，关于第一比特序列、第二比特序列、第三比特序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述，可以参考上述第一方面的描述；或者，还可以参考下文示出的方法实施例，这里不再详述。
第八方面，本申请实施例提供一种通信装置，该通信装置包括逻辑电路和接口，所述逻辑电路和所述接口耦合；所述逻辑电路，用于获得第二待译码序列，并根据扩展矩阵对所述第二待译码序列进行第二信道译码，获得第一待译码序列；以及根据第一可靠度序列对所述第一待译码序列进行第一信道译码，获得第一比特序列。其中，所述第二待译码序列包括N个比特的信息和E个校验比特的信息，所述N为大于或等于1的整数，所述E为大于或等于1的整数；所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述第一待译码序列包括所述N个比特的信息，所述E 0和所述N 0都是大于或等于1的整数；所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N，所述第一比特序列包括K个信息比特。
可理解，以上所示的逻辑电路，用于获得第三比特序列；还可以理解为：接口，用于输入待处理的数据(如通过信道获得的接收序列等)，逻辑电路，对该接口输入的待处理的数据进行处理，获得第二待译码序列；或者，逻辑电路，通过接口输入该第二待译码序列等。
在一种可能的实现方式中，所述逻辑电路，具体用于根据所述第一可靠度序列和内交织器序列对所述第一待译码序列进行第一信道译码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
可理解，关于第一比特序列、第一待译码序列、第二待译码序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述，可以参考上述第二方面的描述；或者，还可以参考下文示出的方法实施例，这里不再详述。
第九方面，本申请实施例提供一种计算机可读存储介质，该计算机可读存储介质用于存储计算机程序，当其在计算机上运行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被执行；或者，使得上述第二方面或第二方面的任意可能的实现方式所示的方法被执行。
第十方面，本申请实施例提供一种计算机程序产品，该计算机程序产品包括计算机程序或计算机代码，当其在计算机上运行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被执行；或者，使得上述第二方面或第二方面的任意可能的实现方式所示的方法被执行。
第十一方面，本申请实施例提供一种计算机程序，该计算机程序在计算机上运行时，上述第一方面或第一方面的任意可能的实现方式所示的方法被执行；或者，上述第二方面或第二方面的任意可能的实现方式所示的方法被执行。
第十二方面，本申请实施例提供一种无线通信系统，该无线通信系统包括发送端和接收端，所述发送端用于执行上述第一方面或第一方面的任意可能的实现方式所示的方法，所述接收端用于执行上述第二方面或第二方面的任意可能的实现方式所示的方法。
附图说明
图1是本申请实施例提供的一种通信系统的架构示意图；
图2是本申请实施例提供的一种极化码编码的示意图；
图3是本申请实施例提供的一种串行消除列表(successive cancellation list，SCL)译码的树状结构示意图；
图4a是本申请实施例提供的一种编码方法的流程示意图；
图4b是本申请实施例提供的一种第二信道编码的示意图；
图5a是本申请实施例提供的一种扩展基矩阵的示意图；
图5b是本申请实施例提供的另一种扩展基矩阵的示意图；
图5c是本申请实施例提供的一种扩展基矩阵的生成方法的流程示意图；
图5d是本申请实施例提供的另一种扩展基矩阵的生成方法的流程示意图；
图6a是本申请实施例提供的一种不同构造序列对应的译码性能的示意图；
图6b是本申请实施例提供的一种比特信道间的可靠度差异和分块特征的示意图；
图6c是本申请实施例提供的一种校验节点和变量节点之间的校验关系示意图；
图6d是本申请实施例提供的一种扩展矩阵与第一可靠度序列之间的关系的示意图；
图7a是本申请实施例提供的一种本申请提出的编码方法和极化码编码方法的译码性能的比较示意图；
图7b是本申请实施例提供的一种本申请提出的编码方法和极化码编码方法的重复编码的译码性能的比较示意图；
图8是本申请实施例提供的一种译码方法的流程示意图；
图9a是本申请实施例提供的一种大迭代译码的流程示意图；
图9b是本申请实施例提供的一种译码方法的示意图；
图9c是本申请实施例提供的一种最大译码复杂度和平均译码复杂度的对比示意图；
图9d至图9g示出的是本申请实施例提出的编码方法、重复编码方法、长码编码方法的性能对比示意图；
图10是本申请实施例提供的一种编码方法和译码方法的示意图；
图11至图13是本申请实施例提供的一种通信装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地描述。
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等仅用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备等，没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元等，或可选地还包括对于这些过程、方法、产品或设备等固有的其它步骤或单元。
在本文中提及的“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上，“至少两个(项)”是指两个或三个及三个以上，“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”。
本申请提供的方法可以应用于各类通信系统，例如，可以是物联网(internet of things， IoT)系统、窄带物联网(narrow band internet of things，NB-IoT)系统、长期演进(long term evolution，LTE)系统，也可以是第五代(5th-generation，5G)通信系统(如包括增强移动带宽(enhanced mobile broadband，eMBB)、超可靠低时延通信(ultra reliable and low latency communication，URLLC)和增强机器类通信(enhanced machine type communication，eMTC))，以及未来通信发展中出现的新的通信系统(如6G)等。以及本申请提供的方法还可以应用于无线局域网(wireless local area network，WLAN)系统，如无线保真(wireless-fidelity，Wi-Fi)等。
本申请提供的技术方案还可以应用于机器类通信(machine type communication，MTC)、机器间通信长期演进技术(Long Term Evolution-machine，LTE-M)、设备到设备(device-todevice，D2D)网络、机器到机器(machine to machine，M2M)网络、物联网(internet of things，IoT)网络或者其他网络。其中，IoT网络例如可以包括车联网。其中，车联网系统中的通信方式统称为车到其他设备(vehicle to X，V2X，X可以代表任何事物)，例如，该V2X可以包括：车辆到车辆(vehicle to vehicle，V2V)通信，车辆与基础设施(vehicle to infrastructure，V2I)通信、车辆与行人之间的通信(vehicle to pedestrian，V2P)或车辆与网络(vehicle to network，V2N)通信等。
以下详细介绍本申请涉及的术语。
1、终端设备
本申请中的终端设备是一种具有无线收发功能的装置。终端设备可以与无线接入网(radio access network，RAN)中的接入网设备(或者也可以称为接入设备)进行通信。
终端设备也可以称为用户设备(user equipment，UE)、接入终端、终端(terminal)、用户单元(subscriber unit)、用户站、移动站、远方站、远程终端、移动设备、用户终端、用户代理或用户装置等。在一种可能的实现方式中，终端设备可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上(如轮船等)。在一种可能的实现方式中，终端设备可以是具有无线通信功能的手持设备、车载设备、可穿戴设备、传感器、物联网中的终端、车联网中的终端、无人机、第五代(5th generation，5G)网络以及未来网络中的任意形态的终端设备等，本申请对此不作限定。
可理解，本申请示出的终端设备不仅可以包括车联网中的车辆(如汽车)、而且还可以包括车联网中的车载设备或车载终端等，本申请对于该终端设备应用于车联网时的具体形态不作限定。可理解，本申请示出的终端设备与终端设备之间还可以通过D2D、V2X或M2M等技术进行通信，本申请对于终端设备与终端设备之间的通信方法不作限定。
2、网络设备
本申请中的网络设备可以是一种部署在无线接入网中，为终端设备提供无线通信服务的装置。该网络设备也可以称为接入网设备、接入设备或RAN设备等。
示例性的，网络设备可以是下一代节点B(next generation node B，gNB)、下一代演进型基站(next generation evolved nodeB，ng-eNB)、或者未来6G通信中的网络设备等。网络设备可以是任意一种具有无线收发功能的设备，包括但不限于以上所示的基站(包括部署于卫星上的基站)。该网络设备还可以是第六代通信系统中具有基站功能的装置。可选的，该网络设备可以为无线局域网(wireless fidelity，WiFi)系统中的接入节点、无线中继节点、无线回传节点等。可选的，该网络设备可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。可选的，该网络设备可以是可穿戴设备或车载设备等。可选的，该网络 设备还可以是小站，传输接收节点(transmission reception point，TRP)(或也可以称为传输点)等。可理解，该网络设备还可以是未来演进的公共陆地移动网络(public land mobile network，PLMN)中的基站、卫星等等。该网络设备还可以为非地面通信系统、D2D、V2X或M2M中承载基站功能的设备等，本申请对网络设备的具体类型不作限定。在不同的无线接入技术的系统中，具备网络设备功能的设备的名称可能会有所不同。
可选的，在网络设备的一些部署中，网络设备可以包括集中式单元(centralized unit，CU)和分布式单元(distributed unit，DU)等。在网络设备的另一些部署中，CU还可以划分为CU-控制面(control plane，CP)和CU-用户面(user plan，UP)等。在网络设备的又一些部署中，网络设备还可以是开放的无线接入网(openradioaccessnetwork，ORAN)架构等，本申请对于网络设备的具体部署方式不作限定。
基于上文介绍的终端设备和网络设备，本申请实施例提供了一种通信系统。图1是本申请实施例提供的一种通信系统的架构示意图。如图1所示，该通信系统可以包括至少一个网络设备，以及至少一个终端设备，如图1中的终端设备1至终端设备4。
示例性的，如图1所示的终端设备3与终端设备4之间可以直接通信。例如可以通过D2D技术实现终端设备之间的直接通信。又例如，终端设备1至终端设备4可以分别与网络设备通信。可理解，终端设备3和终端设备4可以直接与网络设备通信，也可以间接地与网络设备通信，如经由其他终端设备(图1未示出)与网络设备通信。应理解，图1示例性地示出了一个网络设备和多个终端设备，以及各通信设备之间的通信链路。可选地，该通信系统可以包括多个网络设备，并且每个网络设备的覆盖范围内可以包括其它数量的终端设备，例如更多或更少的终端设备。本申请对此不做限定。
本申请实施例描述的网络架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着网络架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
3、准循环(quasi cyclic，QC)矩阵
该QC矩阵也可以称为准循环移位、QC形式或准循环移位矩阵等。示例性的，矩阵
Figure PCTCN2022116922-appb-000012
是一个扩展因子(lifting size)等于5的QC矩阵，该QC矩阵中非零元素称为平移值(shifting value)。则该矩阵对应到二元域时的矩阵可以通过如下方式获得：
将上述QC矩阵中的每个元素都转换成大小等于扩展因子的单位阵I。
如将上述QC矩阵中的非零元素的取值称为平移值(shifting value)，则可以将非零元素位置上的单位阵向右循环平移z列。
例如，上述QC矩阵中的非零元素3对应的矩阵可以是由I向右循环平移3列得到，即
Figure PCTCN2022116922-appb-000013
又例如，由于上述QC矩阵中的非零元素5等于扩展因子，则相当于没有进行列的右移。又例如，上述QC矩阵中的非零元素1对应的矩阵可以是由I向右循环平移1列得到，即
Figure PCTCN2022116922-appb-000014
又例如，上述QC矩阵中的非零元素2对应的矩阵可以是由I向 右循环平移2列得到，即
Figure PCTCN2022116922-appb-000015
根据扩展因子5，上述QC矩阵对应的二元域矩阵可以如下所示：
Figure PCTCN2022116922-appb-000016
即上述3行3列的QC矩阵，根据扩展因子转换成二元域上的矩阵后，可以获得15行15列的二元域矩阵。
一般的，当平移值等于扩展因子时，则相当于不对单位阵进行向右循环平移。如果平移值大于扩展因子时，则相当于对单位阵向右循环平移mod(shifting value，lifting size)列。可理解，以上所示的扩展因子5仅为示例，本申请对于该扩展因子的大小不作限定。示例性的，该扩展因子还可以等于3或7等。同时，对于该扩展因子的其他名称，本申请也不作限定。
示例性的，本申请所示的矩阵对应列(也可以称为某一列)的列重可以用该矩阵中对应列(也可以称为某一列)的非零元素的个数表示。例如，上述QC矩阵的第一列包括2个非零元素，则该QC矩阵的第一列的列重可以用2表示。又例如，上述QC矩阵的第二列和第三列都包括1个非零元素，则该QC矩阵的第二列和第三列的列重都可以用1表示。同时，QC矩阵转换为二元域上的矩阵后，QC矩阵对应列的列重等于该QC矩阵的二元域上的矩阵的对应列的列重。例如，QC矩阵的第一列的列重为2，根据扩展因子，可以得到该QC矩阵的第一列对应其二元域矩阵的第一列至第五列，因此该QC矩阵的二元域矩阵中第一列至第五列的列重都是2。类似的，QC矩阵的第二列的列重为1，则该QC矩阵的二元域矩阵中第六列至第十列的列重都是1。可理解，第一列的列重大于第六列的列重。即矩阵中对应列的非零元素的个数越多，则表示该矩阵中对应列的列重越重(也可以称为列重越大)。类似的，矩阵中对应列的非零元素的个数越少，则表示该矩阵中对应列的列重越轻(也可以称为列重越小)。
4、极化(polar)码编码
Polar码的编码矩阵G可以根据标准极化核
Figure PCTCN2022116922-appb-000017
进行n次克罗内克积得到。例如当n＝2时，即可得到码长为N＝4的极化码编码矩阵
Figure PCTCN2022116922-appb-000018
图2是本申请实施例提供的一种极化码编码的示意图。如当n＝3时，码长为N＝8的极化码编码矩阵G如下所示：
Figure PCTCN2022116922-appb-000019
如图2所示，待编码比特可以根据各自的可靠度排序分为冻结比特(frozen)(也可以称为固定比特)和信息比特(data)两类。一般的，可靠度较高的比特设置为信息比特(data)，可靠度较低的比特设置为冻结比特(frozen)，冻结比特(frozen)的值通常设置为0，在实际传输中发送端和接收端都已知。如图2所示，u 7,u 6,u 5,u 3为可靠度靠前的四位比特，设置为信息比特(data)，u 4，u 2，u 1，u 0为可靠度靠后的四位比特，设置为冻结比特(frozen)。
5、可靠度序列
可靠度序列是位置编号按照可靠度从低到高的排序序列。示例性的，一个长度为N的可靠度序列A＝[a 1,a 2,...,a N]，第一位a 1是可靠度最低的位置编号，最后一位a N是可靠度最高的位置编号。当然，也可以按照可靠度从高到低的排序序列，由于实质一样，本申请还是以位置编号按照可靠度从低到高的排序序列为例进行说明。或者，可靠度最低的位置编号也可以从0开始等，本申请对此不作限定。示例性的，给定一个K长的信息比特和一个N长的可靠度序列A＝[a 1,a 2,...,a N]，则可以将该K个信息比特放在A中最可靠的K个位置如[a N-K+1,...,a N](仅为示例)上，A中剩余的N-K个位置[a 1,...,a N-K]上放置冻结比特(比如0)，从而得到信息承载序列[b 1,b 2,...,b N]。
6、极化码的串行消除(successive cancellation，SC)译码及串行消除列表(successive cancellation list，SCL)译码
SC译码是极化码时序译码的一种方式，其可以对极化码的极化信道
Figure PCTCN2022116922-appb-000020
进行逐一译码，从i＝1开始到i＝N结束。示例性的，可以先从信道接收信号Y N判决U 1(如果U 1是冻结比特则直接判决)，再将得到的U 1和信道接收信号Y N视为第二个极化信道
Figure PCTCN2022116922-appb-000021
并对其译码得到U 2。重复此过程直到第N个比特U N被解出，译码结束。
SCL译码则是建立在SC的基础之上，只是在对每一
Figure PCTCN2022116922-appb-000022
译码时不立刻对U i判决，而是同时保持U i＝0和U i＝1两种可能性。一般的，由于译码池的候选序列大小按指数增长，为控制译码复杂度，对SCL译码器的宽度(list)大小会进行一定限制，即每次只保留概率值最大的L条候选路径。而在最终输出U N时，在L条候选路径中选择概率值最大的路径作为译码结果。图3是本申请实施例提供的一种SCL译码的树状结构示意图。示例性的，N＝4，L＝4，每个比特U i由第i层表示，其中1≤i≤4。对每一层的U i，SCL译码器根据之前的判决比特
Figure PCTCN2022116922-appb-000023
分别对U i＝0和U i＝1进行概率计算。因此随着i的增大，得到的层数也不断增加，形成图3中的树形结构。如图3所示，每条路径都有相应的权重，其值由该路径上对应U值的概率决定。从而在最终输出的L条路径中选择权重最大的路径作为SCL译码器的最终输出。如图3所示，该SCL译码器的输出为1000。
可理解，本申请实施例对于SC译码和SCL译码的介绍仅为示例，对于该SC译码和SCL译码的具体方式，本申请实施例不作限定。
本申请提供了一种编码方法、译码方法及装置，该方法不仅兼具了LDPC码的码长扩展灵活和易于产生软值的优点，而且保持了极化码结构性强以及译码效率高的特点，有效融合了LDPC码和极化码的优点。
可选的，本申请提供的方法可以应用于上文所示的终端设备或网络设备上。例如，终端 设备可以作为发送端，如对K个信息比特进行编码，然后向网络设备发送根据该K个信息比特获得的编码后的比特等；网络设备作为接收端，对从终端设备接收到的编码后的序列进行译码，获得K个信息比特。又例如，网络设备可以作为发送端，终端设备作为接收端。本申请对此不作限定。可选的，本申请提供的方法还可以应用于专用集成电路(application specific integrated circuit，ASIC)(也可以称为专用集成芯片等)、现场可编程逻辑门阵列(field programmable gate array，FPGA)或可编程芯片等。可选的，本申请提供的方法还可以通过软件(如通过存储器中存储的程序代码)实现等。本申请对此不作限定。
以下将详细介绍本申请所示的编码方法和译码方法。
图4a是本申请实施例提供的一种编码方法的流程示意图。如图4a所示，该方法包括：
401、发送端获取第一比特序列和目标码长M，该第一比特序列包括K个信息比特，K为大于或等于1的整数，M为大于或等于1的整数。
该第一比特序列可以理解为发送端获取到的待发送的比特序列。如该第一比特序列可以理解为包含信息量的，或者，需要传输的比特序列等。可选的，上述第一比特序列可以理解为是由上述K个信息比特构成的。
在一种可能的实现方式中，该K个信息比特可以包括循环冗余校验(cyclic redundancy check，CRC)比特和/或奇偶校验(parity check，PC)比特。示例性的，针对上行传输，K可以大于或等于18比特，CRC比特可以包括6个比特或11个比特等。又如，针对下行传输，K可以大于或等于36比特，CRC比特可以包括16个比特或者24个比特等。
在另一种可能的实现方式中，该K个信息比特还可以不包括CRC比特；或者，不包括PC比特等。作为一示例，该K个信息比特不包括CRC比特时，则发送端可以根据获得的K个信息比特中增加CRC比特，或者，发送端可以在获得第二比特序列之后(如下文所示的步骤402)，在N个比特中增加CRC比特。作为又一示例，该K个信息比特不包括PC比特时，发送端可以根据获得的K个信息比特中增加PC比特，或者，发送端可以在获得第二比特序列之后，在N个比特中增加PC比特。又一示例，该K个信息比特既不包括CRC比特又不包括PC比特，发送端可以根据获得的K个信息比特增加CRC比特和PC比特，或者，发送端可以在获得第一比特序列之后，在N个初传比特中增加CRC比特和PC比特。本申请实施例对于发送端增加CRC比特或PC比特的位置不作限定。可理解，以上所示的CRC比特和PC比特均是一种校验方法，本申请实施例对于其他校验方法不作限定。
目标码长可以理解为是给定的发送码长，该目标码长还可以理解为是可灵活扩展的码长、可灵活扩展的极化(extension flexible-polar，EF-polar)码码长等，本申请实施例对于该目标码长的名称不作限定。示例性的，该目标码长可以根据信道传输的资源和调制阶数确定。示例性的，该目标码长可以由网络设备设置；或者，该目标码长可以由协议或标准规定等，本申请实施例对于该目标码长的设置方法不作限定。
示例性的，发送端获取第一比特序列可以包括：该发送端生成第一比特序列，或者，该发送端中用于编码的装置从该发送端中的其他装置中获取第一比特序列等，本申请实施例对于发送端如何获取第一比特序列不作限定。
402、发送端对第一比特序列进行第一信道编码，获得第二比特序列，该第二比特序列包括N个比特，N为大于或等于1的整数。
第一信道编码包括极化码编码、博世-钱德拉-霍克詹海姆(bose–chaudhuri–hocquenghem，BCH)码编码、里所(reed-solomon，RS)码编码、LDPC编码或卷积码等中的任一种或多种。该第一信道编码可以采用概率编码(如LDPC编码)，也可以采用代数编码(如BCH编码)， 本申请实施例对此不作限定。
上述N可以为母码长，或者，也可以为经过速率匹配的码长。例如，N为母码长，则发送端可以对信息比特如U＝u 1,u 2,…u K进行极化码编码，获得第二比特序列，如该第二比特序列为C＝c 1,c 2,…c N。又例如，母码长大于N，则发送端可以通过速率匹配获得长度为N的比特。即在母码长大于N时，发送端可以通过速率匹配的方法适配到可用资源的长度，从而获得第二比特序列。速率匹配的方法可以包括重复(repetition)、打孔(puncture)、缩短(shorten)等，本申请实施例对此不作限定。
403、发送端根据第二比特序列进行第二信道编码，获得第三比特序列，该第三比特序列包括N个比特和E个校验比特，E为大于或等于1的整数，M>N，且E＝M-N。
第二信道编码还可以称为冗余编码、冗余扩展编码或冗余信道编码等，本申请实施例对于第二信道编码的名称不作限定。
上述根据第二比特序列进行第二信道编码包括：根据该第二比特序列和扩展矩阵进行第二信道编码，该扩展矩阵包括N行E列，该扩展矩阵根据扩展基矩阵得到，该扩展基矩阵包括N 0行E 0列，E 0和N 0都是大于或等于1的整数。
即发送端可以根据扩展矩阵对第二比特序列进行第二信道编码，获得第三比特序列。该扩展矩阵是根据扩展基矩阵得到的，即该扩展基矩阵可以适配不同的N和/或不同的E，从而得到与N和E相匹配的扩展矩阵。该扩展基矩阵还可以称为基矩阵(base matrix)、基图(base graph)或原图(protograph)等，扩展矩阵还可以称为校验矩阵、冗余扩展矩阵或冗余编码矩阵等，本申请实施例对于该扩展基矩阵和该扩展矩阵的名称不作限定。可理解，该扩展矩阵和该扩展基矩阵都具有QC结构。关于扩展基矩阵的具体说明还可以参考关于图5a至图5d的相关描述，这里先不详述。
示例性的，扩展矩阵用H表示，E个校验比特用P表示，第二比特序列用C表示，则H与P之间的关系可以如下所示：
Figure PCTCN2022116922-appb-000024
其中，c 1,c 2,…c N表示第二比特序列的N个比特，P＝p 1,p 2,…p E表示E个校验比特。
图4b是本申请实施例提供的一种第二信道编码的示意图。如图4b所示，K个信息比特如u 1,u 2,…u K进行极化码编码，获得第二比特序列如c 1,c 2,…c N。示例性的，该第二比特序列经过N行N列的单位阵，可以按顺序依次输出，作为第三比特序列的前N个比特，该第二比特序列经过扩展矩阵H，可以获得E个校验比特，作为第三比特序列的后E个比特，从而实现扩展码长的目的。可理解，图4b所示的单位阵(如S NN)和扩展矩阵H的形式仅为示例，本申请实施例对此不作限定。可理解，本申请实施例所示的G check＝[S NN，H NE]也可以理解为本申请实施例所示的扩展矩阵的一种形式。
可理解，上述矩阵运算可以在二元域也可以在非二元域。示例性的，扩展矩阵也可以是非二元域的形式，如图4b所示的扩展矩阵是非二元域的矩阵时，则每个黑色正方形可以是维度为Z*Z的根据平移值向右平移的矩阵。可理解，当图4b所示的扩展矩阵是非二元域的矩阵时，图4b所示的扩展矩阵的行可以不是N，列数也可以不是E，而是对该N行E列的二元域矩阵转换为非二元域上的矩阵时的行数和列数。也就是说，图4b所示的第二信道编码仅为示例，不应将其理解为对本申请实施例的限定。
为便于描述，下文将以扩展矩阵H是二元域上的矩阵为例说明本申请提供的方法。
可理解，当M＝N时，本申请实施例所示的编码方法可以退化为：发送端获取第一比特序列和目标码长M，然后对该第一比特序列进行第一信道编码，获得第二比特序列；输出该第二比特序列。
404、发送端输出第三比特序列。
可理解，如果发送端在步骤402就已经进行了速率匹配，则输出第三比特序列之后，该发送端可以不再次进行速率匹配。当然，如果发送端在步骤402未进行速率匹配，则发送端在步骤404之后可以进行速率匹配。
可选的，发送端在步骤404之后，还可以进行调制等，以及通过信道将调制后的序列发送给接收端等，本申请实施例对此不作限定。
发送端根据给定发送码长M以及N确定出校验比特数E，从而进行第二信道编码，获得E个校验比特。本申请实施例提供的方法，能够根据不同的M灵活地扩展码长，如扩展出E个校验比特，提高了码长扩展的灵活性。尤其是对于极化码编码来说，本申请实施例提供的方法，不仅能够结合极化码的结构性强、译码效率高等的优点，还能够灵活地扩展码长，从而使得极化码编码能够更灵活地应用于数据信道上。
以下详细介绍本申请实施例所示的扩展基矩阵和扩展矩阵。
在进行第二信道编码时，发送端需要确定扩展矩阵H的大小，如可以根据第二比特序列的长度N和目标码长M确定扩展矩阵H的大小，又如，可以根据扩展基矩阵和该扩展基矩阵的扩展因子(lifting size)确定扩展矩阵H的大小等。本申请实施例所示的扩展矩阵可以具有双嵌套的性质，如可以灵活地适配不同的N和E，如下所示：
1、适配不同的N
为了能够适配不同N，需要保证扩展矩阵H的行数能够灵活地伸缩。即可以根据改变扩展因子Z和/或速率匹配方法来适配不同的N。
作为一示例，可以根据扩展基矩阵的行数N 0和扩展因子Z适配不同的N。例如，N 0＝16，发送端进行第一信道编码时需要得到比特数为1024长的第二比特序列，则Z＝N/N 0＝64。即可以通过扩展因子Z＝64，将扩展基矩阵转换成二元域上的矩阵，从而得到扩展矩阵。又例如，N 0＝16，发送端进行第一信道编码时需要得到比特数为512长的第二比特序列，则Z＝N/N 0＝32。即可以通过扩展因子Z＝32，将扩展基矩阵转换成二元域上的矩阵，从而得到扩展矩阵。可理解，本申请实施例所示的扩展基矩阵的行数N 0＝16仅为示例，例如，该扩展基矩阵的行数N 0＝32或N 0＝64等，本申请实施例对此不作限定。例如，N 0＝64，发送端进行第一信道编码时需要得到比特数为1024长的第二比特序列，则Z＝N/N 0＝16。即可以通过扩展因子Z＝16，将扩展基矩阵转换成二元域上的矩阵，从而得到扩展矩阵。可理解，本申请实施例中，Z＝2 n，该n为大于或等于0的整数(即n可以为自然数)。例如，n＝0、1、2、3、4、5、6等。
作为又一示例，可以根据扩展基矩阵的行数N 0、扩展因子Z和速率匹配方法适配不同的N。例如，N 0＝16，发送端进行第一信道编码时需要得到比特数为1000长的第二比特序列，则可以根据
Figure PCTCN2022116922-appb-000025
(即N/N 0向上取整)，且Z＝2 n确定Z，即Z＝64。即可以通过扩展因子Z＝64，将扩展基矩阵转换成二元域上的矩阵(即包括1024行的矩阵)，然后通过打孔(puncture)或缩短(shorten)得到行数为1000的扩展矩阵。例如，N 0＝64，发送端进行第一信道编码时需要得到比特数为2000长的第二比特序列，则根据
Figure PCTCN2022116922-appb-000026
由于32是2的幂次方，因此Z＝32。即通过Z＝32将扩展基矩阵转换成二元域上的矩阵(即包括2048行的矩阵)，然后通过打孔(puncture)或缩短(shorten)得到行数为2000的扩展矩阵。
可理解，以上是以根据N 0和Z适配不同的N为例示出的，然而，本申请实施例中，还可以根据N 0和Z确定第二比特序列的长度N。也就是说，Z也可以是固定值，如发送端可以先根据N 0和Z确定N，然后对第一比特序列进行第一信道编码，获得第二比特序列，以及根据该第二比特序列和扩展矩阵进行第二信道编码等。可理解，当通过上述方法确定N时，该N大于M的情况下，可以根据速率匹配的方法将N缩短或凿孔到小于M。至于该N根据速率匹配的方法缩短或凿孔到小于M的哪个值，本申请实施例不作限定。
示例性的，N＝N 0*Z。例如，N 0＝16，Z＝64，则N＝1024，即发送端获得的第二比特序列的长度为1024。又例如，N 0＝16，Z＝32，则N＝512，即发送端获得的第二比特序列的长度为521。本申请实施例中，Z＝2 n，该n为大于或等于0的整数(即n可以为自然数)。例如，n＝0、1、2、3、4、5、6等。
2、适配不同的码率R
该扩展矩阵H NE还具有适配不同码率的灵活性。示例性的，该扩展矩阵H NE可以满足子矩阵嵌套的性质。该子矩阵嵌套性质可以理解为：码率较低的扩展矩阵是码率较高的扩展矩阵的一个子矩阵。也就是说，本申请实施例所示的扩展矩阵可以兼容不同的码率。可理解，本申请实施例所示的码率可以理解为是第一信道编码的码率。
3、适配不同的E
根据N和码率R，扩展矩阵具有适配不同校验比特数E的灵活性，即H NE可以满足列嵌套的性质。示例性的，该列嵌套性质可以理解为：e 1个校验比特所对应的扩展矩阵H N,e1是e 1+e 2个校验比特所对应的扩展矩阵H N,e1+e2的子矩阵。即要求对校验比特数为e 1+e 2的扩展矩阵H N,e1+e2的前e 1列进行截取得到的子矩阵H N,e1在校验比特数e 1时也能得到很好的性能。也就是说，本申请实施例所示的扩展矩阵可以兼容不同的E。
作为一示例，扩展矩阵的E列是第一矩阵的前E列，该第一矩阵是扩展基矩阵根据扩展因子扩展后的矩阵。示例性的，在第一信道编码的码率等于最高支持码率时，扩展矩阵的E列是第一矩阵的前E列。示例性的，在根据扩展因子对扩展基矩阵进行扩展后，可以获得第一矩阵，然后根据M-N将第一矩阵的前E列确定为扩展矩阵的E列。可理解，关于扩展因子的说明可以参考上述关于适配不同的N的描述，这里不再详述。可理解，本申请实施例所示的最高支持码率还可以称为最高设计码率等，本申请实施例对于该最高支持码率的名称不作限定。示例性的，该最高支持码率的具体取值可以由网络设备设置，或者，由标准或协议定义等，本申请实施例不作限定。
作为又一示例，扩展矩阵的E列是第一矩阵中相邻的E列，该第一矩阵中相邻的E列是根据第一信道编码的码率确定的(也可以称为与第一信道编码的码率有关)，该第一矩阵是扩展基矩阵根据扩展因子扩展后的矩阵。示例性的，在K/N获得的码率小于最高支持码率时，该扩展矩阵的E列可以是第一矩阵中相邻的E列。也就是说，可以根据K/N获得的码率和最高支持码率之间的运算结果确定扩展矩阵的E列是第一矩阵中相邻的E列。该情况下，扩展矩阵的E列就不是第一矩阵中的前E列。示例性的，根据K/N获得的码率和最高支持码率之间的运算结果j，得到扩展矩阵的第一列。即j与K/N、最高支持码率和N有关。示例性的，j可以满足如下关系中的任一项：
Figure PCTCN2022116922-appb-000027
Figure PCTCN2022116922-appb-000028
Figure PCTCN2022116922-appb-000029
Figure PCTCN2022116922-appb-000030
其中，R＝K/N，R h表示最高支持码率，N表示第二比特序列的长度，Δ表示偏移值，该可以为实数(如为正整数、0或负整数等)。
Figure PCTCN2022116922-appb-000031
表示向上取整，
Figure PCTCN2022116922-appb-000032
表示向下取整。示例性的，Δ可以等于0。或者，该Δ可以等于-1、-2、-3、-4或-5等，这里不再一一举例。或者，该Δ可以等于1、2、3、4或5等，这里不再一一举例。
举例来说，R＝K/N＝0.5，最高支持码率Rh＝0.75，N＝1024，则根据上述关系j＝1024*0.25/0.5＝512。校验比特数E＝200，则可以将第一矩阵向右取512列，得到扩展矩阵的第一列。示例性的，Δ＝0时，则可以从第一矩阵的第513列开始截取200列，得到扩展矩阵，该扩展矩阵的第一列为第一矩阵的第513列，该扩展矩阵的第200列为第一矩阵的第712列。
本申请实施例中所示的扩展矩阵能够灵活适配不同的E，即在不同的E取值下都能够保证第二信道编码的性能。示例性的，对E＝200的扩展矩阵的前180列进行截取得到的子矩阵H sub在E＝180时也能得到很好的性能。
本申请实施例中，扩展矩阵中某一列的列重满足如下关系中的任一项或多项：与E成负相关、与K成正相关、与N成负相关、与K/N(即第一信道编码的码率)成正相关。示例性的，第一信道编码的码率越大，则该某一列的列重越重。示例性的，扩展矩阵中第一列的列重可以满足上述关系。又如，扩展矩阵中至少两列中每一列的列重满足上述关系。又如，扩展矩阵中每一列的列重满足上述关系。为便于描述，下文均以每一列的列重为例说明列重与上述各个参数之间的关系。
示例性的，当E越小时，列重越重(即列重越大)；或者，当K越大时，列重越重；或者，当N越小时，列重越重；或者，当K/N越大时，列重越重。类似的，当E越大时，列重越轻(即列重越小)；或者，当K越小时，列重越轻；或者，当N越大时，列重越轻；或者，当K/N越小时，列重越轻。
本申请实施例中，列重可以是N、K和E的函数。示例性的，当K/N一定时，E越小，列重越重。类似的，当K/N一定时，E越大，列重越轻。示例性的，当E一定时，K/N越大，列重越重。类似的，当E一定时，K/N越小，列重越轻。示例性的，当K/N越大，以及E越小时，列重越重。类似的，当K/N越小，E越大时，列重越轻。可理解，以上关于扩展矩阵的说明同样适用于扩展基矩阵。同时，对于扩展基矩阵的说明同样适用于扩展矩阵。
结合上述所示的扩展矩阵，本申请实施例示例性给出了两种扩展基矩阵。图5a和图5b是本申请实施例提供的一种扩展基矩阵的示意图。可理解，图5a和图5b是以QC的形式示出的，但是，不应将其理解为对本申请实施例的限定。示例性的，图5a示出的是当E＝1024，Z＝16，N＝1024，K＝512时示出的扩展基矩阵。图5b示出的是当E＝1024，Z＝16，N＝1024，K＝768时示出的扩展基矩阵。由于图5a和图5b所示的E相同，且512/1024小于768/1024，因此，图5a所示的扩展基矩阵的最大列重(如某一列的列重)小于图5b所示的扩展基矩阵的最大列重(如某一列的列重)。图5a所示的扩展基矩阵中的列重最小为1，最大为5，图5b所示的扩展基矩阵中的列重最小为1，最大为8。示例性的，图5a所示的扩展基矩阵的第一列的列重为3，图5b所示的扩展基矩阵的第一列的列重为8。
可理解，图5a和图5b是以N行E列的扩展基矩阵为例示出的，但是，本申请实施例所示的扩展基矩阵还可以包括1024行1024列的单位阵(根据Z＝16，则该单位阵转换QC形式时，可以表示为64行64列的矩阵)(可以如图4b所示)。本申请实施例通过单位阵以及图5a或图5b所示所示的矩阵表示扩展基矩阵的原因之一在于：接收端在译码时需要把扩展矩阵转换为Tanner图，通过包括单位阵SNN可以更好的辅助画出Tanner图，从而辅助置信度传 播(belief propagation，BP)算法译码。当然，如果扩展矩阵用H NE表示时，接收端在译码时，也可以自主添加上单位阵S NN。
结合上述关于扩展矩阵的说明，本申请实施例还提供了一种生成扩展基矩阵的方法。示例性的，本申请实施例所示的扩展基矩阵的双嵌套性质可以基于QC矩阵通过树搜索算法实现。可理解，本申请实施例所示的扩展基矩阵的生成方法可以由发送端实现，或者，由接收端实现等，本申请实施例对此不作限定。例如，该扩展基矩阵由发送端实现，则该发送端可以将该扩展基矩阵的信息发送给接收端。又例如，该扩展基矩阵由接收端实现，则该接收端可以将该扩展基矩阵的信息发送给发送端。可理解，本申请实施例所示的扩展基矩阵还可以由协议或标准预先定义等，本申请实施例对此不作限定。
图5c和图5d是本申请实施例提供的一种扩展基矩阵的生成方法的流程示意图。图5c和图5d中，L表示搜索宽度，如该搜索宽度可以理解为是初始化随机矩阵的个数等。D max和D min分别表示扩展基矩阵的最大列重和最小列重；E 0表示扩展基矩阵的最大列数；maxIter表示计算扩展基矩阵性能时基于原图的外信息传播(protograph-based extrinsic information transfer，PEXIT)采用的最大迭代次数；Z表示扩展基矩阵对应的QC矩阵的扩展因子(lifting size)；N 0表示扩展基矩阵的最大行数；K表示第一比特序列的长度(也可以理解为信息比特的长度等)；e表示当前已生成的扩展基矩阵的列数。图5c和图5d示出的是递进式的树搜索过程。可选的，图5c和图5d所示的树搜索过程中，为降低搜索的复杂度，在图5c和图5d中的扩展因子Z也可以是素数。
示例性的，如图5c所示，扩展基矩阵的生成方法包括：根据输入的参数L、D max、D min、E 0、maxIter、Z、N 0和K生成L个QC矩阵，该L个QC矩阵可以理解为是初始化的扩展基矩阵的第一列。在当前矩阵的列数e小于E 0时，则可以在上述L个QC矩阵的基础上根据最大列重、最小列重和扩展因子再随机生成L个N 0行1列的QC矩阵。如根据上述L个QC矩阵在每一个矩阵的基础上随机生成另一个矩阵，即得到L*L个QC矩阵。然后L*L个QC矩阵的SC译码性能(仅为示例)，并保留性能最好的前L个QC矩阵。以此进行循环，当当前矩阵的列数e等于E 0时，则输出性能最优的N 0行E 0列的扩展基矩阵。
示例性的，如图5d所示，该扩展基矩阵的生成方法包括：
501、初始化扩展基矩阵为空集。
502、随机生成L个无四环的N 0行1列的QC矩阵。
示例性的，可以根据平移值(shifting value)随机生成L个无四环的QC矩阵。例如，该平移值为小于或等于16的正整数，即shifting value＝1～16，则表示生成的L个N 0行1列的QC矩阵的非零元素的取值范围为大于或等于1，且小于或等于16。示例性的，可以根据列重随机生成L个无四环的QC矩阵。例如，列重范围为1～9，则表示随机生成的L个N 0行1列的QC矩阵的列重的范围为大于或等于1，且小于或等于9。
示例性的，可以根据扩展因子(lifting size)和平移值来确定生成的QC矩阵是否是无四环的。关于无四环的具体说明，本申请实施例不作详述。
示例性的，在随机生成L个无四环的N 0行1列的QC矩阵后，还可以根据性能好坏对该L个QC矩阵进行排序(如根据SC译码性能的好坏)。如图5d所示，按照性能从好到坏排序得到的QC矩阵依次为
Figure PCTCN2022116922-appb-000033
(关于图5d所示的方法以都进行性能好坏排序为例)。可理解，图5d所示的L个QC矩阵中性能最好的矩阵的形式(附图说明中的形式)与
Figure PCTCN2022116922-appb-000034
有所不同，不应将其理解为对本申请实施例的限定。
503、在每个N 0行1列的QC矩阵
Figure PCTCN2022116922-appb-000035
的基础上再额外随机生成1列，得 到L 2个N 0行2列的QC矩阵
Figure PCTCN2022116922-appb-000036
504、计算(N,K)-polar码在L 2个N 0行2列的QC矩阵
Figure PCTCN2022116922-appb-000037
下的性能，根据性能排序得到性能最好的L个N 0行2列的QC矩阵作为扩展基矩阵的前2列。
505、根据上述性能最好的L个N 0行2列的QC矩阵为基础，再随机生成扩展基矩阵的第3列，得到L 2个N 0行3列的QC矩阵
Figure PCTCN2022116922-appb-000038
506、以此类推(根据上述步骤503和步骤504所示的方法)，递进式得到L个N 0行E 0列的QC矩阵
Figure PCTCN2022116922-appb-000039
507、选择
Figure PCTCN2022116922-appb-000040
作为最终输出的扩展基矩阵。
可理解，以上所示的将
Figure PCTCN2022116922-appb-000041
作为扩展基矩阵的原因在于：在得到L个N 0行E 0列的QC矩阵时，都是按照性能好坏排序的。也就是说，该
Figure PCTCN2022116922-appb-000042
是性能最好的QC矩阵。当然，也可以不进行排序，直接输出性能最好的QC矩阵最为扩展基矩阵，本申请实施例对此不作限定。
可理解，以上所示的扩展基矩阵的生成方法，同样适用于扩展矩阵，这里不再详述。
结合图5c和图5d所示的方法，以下举例说明扩展基矩阵的生成方法。
示例性的，N＝1024、K＝512，M＝2024，E＝1000，lifting size＝16，shifting value＝1～16，列重范围为1～9，L＝50。本申请实施例中，扩展矩阵是一个1024行1000列的二元域上的矩阵，扩展基矩阵可以是一个
Figure PCTCN2022116922-appb-000043
行×
Figure PCTCN2022116922-appb-000044
列＝64行×63列的矩阵。因此本申请实施例所示的搜索树(如图5d所示)需要递进式地产生63列，对应到树搜索过程即搜索树需要递进地向下生长63层，每层都需要保留性能最优的L＝50个备选矩阵。
首先，产生第0层中的L＝50个空矩阵，并设置e＝0。由于e<63，因此随机产生L＝50个64行1列的QC矩阵，作为第一层的备选矩阵，同时e＝e+1＝1。然后在每个64行1列的QC矩阵的基础上再额外随机生成1列，从而得到2500个64行2列的随机QC矩阵，同时这些随机QC矩阵的列重满足最大取9最小取1。利用PEXIT算法和高斯近似(gaussian approximition，GA)算法计算(N＝1024，K＝512)的Polar码在这2500个64行2列的随机QC矩阵下达到BLER＝0.01所需的信噪比(signal-to-noise ratio，SNR)。在这2500个随机QC矩阵中挑选SNR最小的L＝50个矩阵作为第二层的备选矩阵，同时e＝e+1＝2，至此搜索树完成了第二层的生长。由于e依然小于63，因此搜索树继续向下生长：以第二层中每个矩阵为基础再额外随机产生L＝50个64行1列且列重在1～9之间的QC矩阵，从而得到位于第3层的2500个64行3列的随机QC矩阵。利用PEXIT算法和GA算法计算(N＝1024,K＝512)的Polar码在这2500个随机QC校验矩阵下达到BLER＝0.01所需的SNR，在这2500个64行3列随机QC校验矩阵中挑选SNR最小的L＝50个矩阵作为第三层的备选矩阵，同时e＝e+1＝3，至此搜索树完成了第三层的生长。以此类推，直至搜索树长到第63层(e＝63)，便可以得到L＝50个64行63列的备选矩阵，并将第一个性能最好的备选矩阵输出作为扩展基矩阵。
可理解，图5c和图5d所示的扩展基矩阵的生成方法仅为示例，本申请实施例对此不作限定。
可理解，本申请所示的扩展矩阵是以N行E列为例示出的，该扩展矩阵的转置矩阵，如E行N列的矩阵，或者，该扩展矩阵的位移(如向右位移或向左矩阵)矩阵，或者，该扩展矩阵的旋转等变形，都属于本申请的保护范围。同样的，对于扩展基矩阵的变形也属于本申请的保护范围。示例性的，如上文所示：扩展矩阵中每一列的列重满足如下关系中的任一项或多项：与E成负相关、与K成正相关、与N成负相关、与K/N(即第一信道编码的码率)成正相关。则将该扩展矩阵进行转置后，则得到的关系可以是：扩展矩阵中每一行的行重满足如下关系中的任一项或多项：与E成负相关、与K成正相关、与N成负相关、与K/N(即第一信道编码的码率)成正相关。
可理解，以上所示的通过扩展矩阵得到的E个校验比特的方法，还可以通过卢比变换LDPC(Luby transform-LDPC，LT-LDPC)码或LT码的校验矩阵得到该E个校验比特，或者，通过LT-LDPC码的生成矩阵得到该E个校验比特。
图4a所示的方法中，发送端需要对第一比特序列进行第一信道编码。示例性的，发送端可以根据第一可靠度序列对该第一比特序列进行第一信道编码。如图4a所示的K个信息比特的位置根据第一可靠度序列确定，该第一可靠度序列的长度为N，该第一可靠度序列为第二可靠度序列的子序列，该第二可靠度序列的长度为N max，该N max大于或等于N。
由于第一可靠度序列需要根据不同的码长而灵活地改变，具有该类特征的序列可以有很多，如图6a所示。图6a是本申请实施例提供的一种不同构造序列对应的译码性能的示意图。图6a分别示出了在线构造序列、本申请所示的离线构造序列、NR polar构造序列和极化权重(polarization weight，PW)构造序列之间的译码性能对比。从图6a可以看出，本申请实施例提供的第二可靠度序列的性能最优，而且该第二可靠度序列的性能还能够接近通过在线构造方式得到的序列。本申请实施例中的第二可靠度序列可以支持最大码长N max和/或支持最大校验比特数E max。可选的，该第二可靠度序列还可以支持不同的扩展因子，如该第二可靠度序列可以支持最大的扩展因子Z max。
示例性的，发送端可以根据一套相同的第一可靠度序列对该第一比特序列进行第一信道编码。如第一可靠度序列可以表示为
Figure PCTCN2022116922-appb-000045
Q N中的元素
Figure PCTCN2022116922-appb-000046
表示子信道的序号，其取值不超过N，且按照可靠度
Figure PCTCN2022116922-appb-000047
从低到高进行排序，i＝1,…,N。又如第二可靠度序列可以表示为
Figure PCTCN2022116922-appb-000048
Q N是
Figure PCTCN2022116922-appb-000049
的一个子序列，
Figure PCTCN2022116922-appb-000050
中的元素
Figure PCTCN2022116922-appb-000051
的取值不超过N max，且按照可靠度
Figure PCTCN2022116922-appb-000052
从低到高进行排序，i＝1,...,N max。
示例性的，第二可靠度序列
Figure PCTCN2022116922-appb-000053
可以如表1所示，其中
Figure PCTCN2022116922-appb-000054
Figure PCTCN2022116922-appb-000055
是进行第一信道编码前的比特的编号。第二可靠度序列
Figure PCTCN2022116922-appb-000056
是根据可靠度
Figure PCTCN2022116922-appb-000057
进行升序排序的序列，其中，
Figure PCTCN2022116922-appb-000058
是比特编号
Figure PCTCN2022116922-appb-000059
所对应的可靠度。
表1
Figure PCTCN2022116922-appb-000060
Figure PCTCN2022116922-appb-000061
Figure PCTCN2022116922-appb-000062
示例性的，第一可靠度序列还可以表示为
Figure PCTCN2022116922-appb-000063
Q N-1中的元素
Figure PCTCN2022116922-appb-000064
表示子信道的序号，其取值不超过N-1，且按照可靠度
Figure PCTCN2022116922-appb-000065
从低到高进行排序，i＝0,…,N-1。又如第二可靠度序列可以表示为
Figure PCTCN2022116922-appb-000066
Q N是
Figure PCTCN2022116922-appb-000067
的一个子序列，
Figure PCTCN2022116922-appb-000068
中的元素
Figure PCTCN2022116922-appb-000069
的取值不超过N max-1，并且按照可靠度
Figure PCTCN2022116922-appb-000070
从低到高进行排序，i＝0,1,...,N max-1。
示例性的，第二可靠度序列
Figure PCTCN2022116922-appb-000071
可以如表2所示，其中
Figure PCTCN2022116922-appb-000072
Figure PCTCN2022116922-appb-000073
是进行第一编码前的比特的编号。第二可靠度序列
Figure PCTCN2022116922-appb-000074
是根据可靠度
Figure PCTCN2022116922-appb-000075
进行升序排序的序列，其中，
Figure PCTCN2022116922-appb-000076
是比特编号
Figure PCTCN2022116922-appb-000077
所对应的可靠度。
表2
Figure PCTCN2022116922-appb-000078
Figure PCTCN2022116922-appb-000079
Figure PCTCN2022116922-appb-000080
示例性的，可以按照在线构造方法得到的序列
Figure PCTCN2022116922-appb-000081
作为离线构造序列的性能，从而得到不同的校验比特数E情况下的
Figure PCTCN2022116922-appb-000082
示例性的，根据该不同E对应的
Figure PCTCN2022116922-appb-000083
可以得到表1或表2所示的离线构造序列。
本申请实施例中，示例性的，该第一信道编码包括极化码编码时，由于本申请实施例提供的方法引入了校验比特，因此N个比特对应的信道之间不再独立同分布。示例性的，校验比特会比参与校验的N个比特中的一个或多个比特进行加强，从而会导致N个比特之间的可靠度上存在差异。示例性的，N个比特中的一个比特参与的校验关系越多，则该一个比特对应的虚拟信道的可靠度会越高。也就是说，N个比特的可靠度和扩展矩阵的列重有关。同时，由于扩展矩阵具有QC形式，所以被加强的N个比特的信道也呈现出分块(block-wise)的特性，即block内的可靠度相同，block间的可靠度不同。示例性的，该block size等于扩展基矩阵的lifting size。示例性的，图6b是本申请实施例提供的一种比特信道间的可靠度差异和分块特征的示意图。如图6b所示，可以根据校验节点和变量节点之间的校验关系，获得N个比特和E个校验比特之间的校验关系。通过极化码编码得到的第二比特序列包括的N个比特之间的可靠度可以如图6b右边所示的图。图6b右边所示的图放大后可以如图6b中下边的图所示。示例性的，图6b是以第二比特序列的长度为1024，第一信道编码的码率为0.75，扩展因子为16为例示出的。可理解，由于扩展因子为16，则图6b示出的每列都可以表示16个比特。可理解，图6b中左边关于N个比特与E个校验比特之间的关系可以参考图6c。可 理解，图6b所示的不同比特之间的可靠度仅为示例。
表1和表2是以离线构造方式示出的可靠度序列，本申请实施例还提供了一种在线构造方式。示例性的，发送端可以根据信道状态和扩展矩阵确定N个位置上每个位置的可靠度，一个位置的可靠度与参与的校验比特的数量成正相关；以及根据该N个位置的可靠度从低到高的顺序确定第一可靠度序列；根据该第一可靠度序列对K个信息比特进行第一信道编码。其中，信道状态可以是发送端与接收端之间的信道状态。也就是说，本申请实施例所示的在线构造序列可以是N、K、E以及Z的函数。即在线构造序列不仅和N、K有关，还和E以及Z有关。
示例性的，在线构造第一可靠度序列的方法可以如下所示：
1)、输入第一信道编码后的比特长度N、信息比特数K、校验比特数E(也可以是目标码长M)，扩展矩阵的扩展因子Z、SNR的搜索范围SNR min～SNR max(如SNR min＝-5，SNR max＝20)和SNR step(如0.25)，PEXIT分析的最大迭代次数iterMax(如4)和目标BLER如用BLER*表示(如10 -2)。
2)、根据N、E、Z确定扩展矩阵H，初始化SNR cur＝SNR min–SNR step。
3)、令SNR cur＝SNR cur+SNR step，基于H利用PEXIT计算从校验节点发往变量节点的外信息I EC。
4)、利用高斯信道下的EXIT函数如J(·)和J -1(·)求出变量节点c i(i＝1,2,…,N)对应的信道的转移概率的方差
Figure PCTCN2022116922-appb-000084
和均值
Figure PCTCN2022116922-appb-000085
可理解，这里所示的以均值表示可靠度的高低仅为示例。
5)、对均值σ i进行从低到高的排序得到如
Figure PCTCN2022116922-appb-000086
以及内交织器序列如I＝[i 1…,i N]，基于
Figure PCTCN2022116922-appb-000087
利用GA计算出polar码比特信道的可靠度
Figure PCTCN2022116922-appb-000088
6)、对比特信道的标号按照
Figure PCTCN2022116922-appb-000089
进行升序排序得到构造序列
Figure PCTCN2022116922-appb-000090
选择可靠度最高的K个位置作为信息位，并计算这K个位置在当前SNR cur下的BLER。
7)、如果BLER≤BLER*则输出当前序列
Figure PCTCN2022116922-appb-000091
作为构造序列；否则返回步骤2)。
可理解，以上所示的在线构造方法仅为示例，对于具体的构造方法，本申请实施例不作限定。
以下将结合具体例子说明扩展矩阵与第一可靠度序列之间的关系。举例来说，第二比特序列的长度为8，即c 1c 2c 3c 4c 5c 6c 7c 8，扩展基矩阵如下所示：
Figure PCTCN2022116922-appb-000092
例如，Z＝2，则首先将扩展基矩阵转换成二元域上的矩阵可以如下所示：
Figure PCTCN2022116922-appb-000093
根据shifting value向右平移相应的列，得到的扩展矩阵如下所示：
Figure PCTCN2022116922-appb-000094
图6d是本申请实施例提供的一种扩展矩阵与第一可靠度序列之间的关系的示意图。如图6d所示，根据校验节点与变量节点之间的校验关系，可以得到在二元域下p 1+c 2+c 5+c 8＝0，p 2+c 1+c 6+c 7＝0，即p 1＝c 2+c 5+c 8，p 2＝c 1+c 6+c 7。可理解，图6d仅示例性的示出的部分校验比特与N个比特之间的关系。根据图6d所示的示意图，可以看出，c 1和c 2均参与了一个校验比特，c 3和c 4均参与了两个校验比特，c 5和c 6均参与了三个校验比特，c 7和c 8均参与了四个校验比特，则表示在构造第一可靠度序列时，如果N＝8，则第7个位置和第8个位置的可靠度最高，第1个位置和第2个位置的可靠度最低。由于扩展因子Z＝2，则表示内交织器的块的大小等于2。如c 1和c 2对应同一个块，该c 1和c 2对应的位置的可靠度相同，又如，c 7和c 8对应同一个块，该c 7和c 8对应的位置的可靠度相同。如对可靠度序列从低到高排序得到内交织器序列I＝[12345678]。
可理解，图6d所示是为了说明扩展矩阵与第一可靠度序列之间的关系的示意图，对于图6d所示的扩展矩阵本申请实施例不作限定。
本申请实施例中，N个比特所对应的虚拟信道具有不同可靠度，优化后的构造序列是通过对这些信道按照可靠度从低到高进行排序后得到的。因此，在编码和译码程中还需要有与之相对应的内交织器。即图4a所示的方法中，发送端可以根据内交织器序列对第一比特序列进行第一信道编码，该内交织器序列根据扩展矩阵确定，该内交织器序列的块的大小等于该扩展矩阵的扩展因子。示例性的，内交织器序列的说明可以参考上述关于第一可靠度序列的描述，这里不再详述。
示例性的，内交织器序列可以具有block-wise交织的特征，如block间按照可靠度从低到高进行交织，block内可以交织或不交织，block size可以等于lifting size。根据本申请实施例所示的内交织器序列的说明，举例来说，Lifting Size＝16，N＝256的Polar码所对应的内交织器序列I可以具有如表3所示的形式：
表3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
可理解，表3所示的内交织器序列仅为示例，不应将其理解为对本申请实施例的限定。
以下结合具体例子说明本申请实施例所示的编码方法。示例性的，如下所示：
1)输入码长N和码率R，内交织器序列I perm，以及校验比特数E。
2)根据
Figure PCTCN2022116922-appb-000095
确定扩展基矩阵的扩展因子，并对扩展基矩阵进行扩展，得到第一矩阵。
3)根据Polar码的速率匹配方式对第一矩阵中对应的行进行打孔/缩短；或者，将扩展矩阵中行重最大的(Z×N 0-N)行打孔，得到码长为N的扩展矩阵的行数H N。
4)在H N的基础上从第
Figure PCTCN2022116922-appb-000096
列开始向右提取E列，得到码率为R的N行×E列的扩展矩阵H R。
可理解，这里所示的j的计算方式仅为示例，对于该j的具体说明还可以参考上述关于j、R、R h、N以及Δ的描述，这里不再赘述。
5)对H R的前N行按照Polar码的交织器序列I perm进行行转置操作，得到H perm；
6)根据H perm产生E个校验比特，即H perm的每一列对应一个校验比特。示例性的，第e(e＝1,2,…,E)个校验比特c e＝[c 1,c 2,…,c N]×H perm(1:N,e)。
示例性的，通过向右平移可以截取适配第一信道编码的码率的扩展矩阵的第一列，通过速率匹配可以适配不同的码长。
举例来说，下面给出利用扩展矩阵适配不同码率的例子：
假设码长N＝2 10(即1024)，Lifting Size＝16时，码率R＝0.5，最高支持码率为R h＝0.75；则根据上述编码方法中的步骤4)，需要从第一矩阵的第一列开始向右平移
Figure PCTCN2022116922-appb-000097
列。示例性的，如果校验比特数为E＝400，则从第一矩阵的第513行开始再向右截取400行，即可得到码率为0.5，重校验比特数为400的扩展矩阵。可理解，关于第一矩阵的说明可以参考上文，这里不再赘述。
又举例来说，下面给出利用扩展矩阵来适配不同初传码长的例子：
假设码率R＝0.75，Lifting Size＝16时，码长N＝992，最高支持码率为R h＝0.75＝R，也就是说无需适配码率的操作。为了适配码长，可以根据5G NR Polar速率匹配的方法，根据凿孔模式打掉32(1024-992)列，即可得到码长为N＝992的扩展矩阵。
可理解，以上的例子仅为示例，不应将其理解为对本申请实施例的限定。
作为示例，图7a是本申请实施例提供的一种本申请提出的编码方法和极化码编码方法的译码性能的比较示意图。可理解，图7a示出的是本申请提出的编码方法和极化码编码方法使用长码扩展的性能对比。图7a中，横坐标表示SNR，如用Es/N0表示，单位是dB；纵坐标表示BLER。如图7a所示，图7a中的(1)表示的是K＝512，N＝1024，list＝8，E＝60，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。图7a中的(2)表示的是K＝512，N＝1024，list＝8，E＝120，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。图7a中的(3)表示的是K＝512，N＝1024，list＝8，E＝180，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。
极化码码长码扩展构造基于PW序列，速率匹配采用BIV+Shorten的方式扩展；本申请提出的编码方法采用如表1所示的离线优化序列，扩展矩阵H如图5a所示。
从图7a可以看出，在达到相同的BLER时，本申请提出的编码方法的SNR(如用Es/N0) 小于极化码编码方法。类似的，在达到相同的SNR时，本申请提出的编码方法的BLER低于极化码编码方法。
图7b是本申请实施例提供的一种本申请提出的编码方法和极化码编码方法的重复编码的译码性能的比较示意图。可理解，图7b示出的是本申请提出的编码方法和极化码编码方法使用重复扩展的性能对比。图7b中，横坐标表示SNR，如用Es/N0表示，单位是dB；纵坐标表示BLER。图7b中的(1)表示的是K＝512，N＝1024，list＝8，E＝60，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。图7b中的(2)表示的是K＝512，N＝1024，list＝8，E＝120，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。图7b中的(3)表示的是K＝512，N＝1024，list＝8，E＝180，采用的调制方法包括正交相移键控(quadrature phase shift keying，QPSK)，通道模型采用的是加性高斯白噪声(additive white gaussian noise，AWGN)。
极化码码重复扩展构造采用NR序列，速率匹配采用重复比特从后往前进行的方式重复扩展；本申请提出的编码方法采用如表1所示的离线优化序列，扩展矩阵H如图5a所示。
从图7b可以看出，在达到相同的BLER时，本申请提出的编码方法的SNR(如用Es/N0)小于极化码编码方法。类似的，在达到相同的SNR时，本申请提出的编码方法的BLER低于极化码编码方法。
可理解，当上述第一信道编码包括极化码编码时，本申请提出的第二信道编码方法还可以称为EF-极化码编码方法，类似的，本申请提出的第二译码方法还可以称为EF-极化码译码方法。或者，当上述第一信道编码包括极化码编码时，本申请提出的第二信道编码方法和第二信道译码方法可以统称为EF-polar码。
以上是本申请实施例提供的编码方法，本申请实施例还提供了一种译码方法。图8是本申请实施例提供的一种译码方法的流程示意图，如图8所示，该译码方法包括：
801、接收端获得第二待译码序列，该第二待译码序列包括N个比特的信息和E个校验比特的信息，该N为大于或等于1的整数，该E为大于或等于1的整数。
可理解，这里所示的接收端获得第二待译码序列，指的是接收端可以对接收序列进行处理，然后获得该第二待译码序列。例如，接收端可以对接收序列进行解调等处理，获得第二待译码序列。E个校验比特的信息可以理解为是E个校验比特经过信道后的软信息序列；或者，N个比特的信息可以理解为是N个比特经过信道后的软信息序列。可理解，第一待译码序列中包括的N个比特的信息与第二待译码序列中包括的N个比特的信息可能相同，也可能不同。
802、接收端根据扩展矩阵对第二待译码序列进行第二信道译码，获得第一待译码序列，该扩展矩阵包括N行E列，该扩展矩阵根据扩展基矩阵得到，该扩展基矩阵包括N 0行E 0列，第一待译码序列包括N个比特的信息，E 0和N 0都是大于或等于1的整数。
803、接收端根据第一可靠度序列对第一待译码序列进行第一信道译码，获得第一比特序列，该第一可靠度序列的长度为N，该第一可靠度序列为第二可靠度序列的子序列，该第二可靠度序列的长度为N max，N max大于或等于N，第一比特序列包括K个信息比特。
可理解，关于图8所示的第一可靠度序列、第二可靠度序列、第一比特序列、第一待译码序列、第二待译码序列、扩展矩阵和矩阵基矩阵等的具体说明可以参考本申请上文所示的编码方法，这里不再详述。示例性的，关于扩展矩阵和扩展基矩阵的说明可以参考上文关于 图5a至图5d所示的描述；关于第一可靠度序列和第二可靠度序列可以参考上文关于表1、表2以及图6a至图6d所示的描述等。这里不再一一详述。
可理解，对于接收端和发送端如何获知扩展基矩阵和第二可靠度序列，本申请实施例不作限定。
示例性的，以下以大迭代译码流程为例说明本申请实施例提供的译码方法。但是，不应将下文所示的译码方法理解为对本申请实施例的限定。
示例性的，对于接收端来说，其可以输入：接收序列y 1，y 2，…,y T，T是接收序列的长度；编码参数：目标码长M，校验比特数E，扩展矩阵H，内交织器序列I，第一可靠度序列(根据该第一可靠度序列可以得到消息位置指示序列B，该序列B中0所在的位置表示冻结位，1所在的位置表示信息位)，凿孔模式Q，CRC多项式crc_poly；译码参数：BP译码最大迭代轮数ITER max，CRC辅助SCL(CRC-Aided SCL，CA-SCL)译码列表维度List。示例性的，这里所示的List可以等于{1,2,4,8,16,32}中的任一数值。
根据上述输入，接收端可以输出：本申请提出的译码方法的译码结果如信息序列u 1,…,u K、K个信息比特对应的软值L s＝l s1,…,l sN以及校验比特对应的软值L c＝L c1,…,L cE。可理解，这里是以接收端输出的信息序列包括信息比特为例示出的，如该接收端输出的信息序列还包括冻结比特。如该接收端还可以输出N个比特，该N个比特包括K个信息比特和N-K个冻结比特。本申请实施例对于接收端的输出结果是只包括信息比特，还是既包括信息比特，又包括冻结比特不作限定。可理解，以上所示的软值L s和软值L c还可以称为软值L EF，即该软值L EF包括软值L s和软值L c。
示例性的，图9a是本申请实施例提供的一种大迭代译码的流程示意图。如图9a所示，该译码方法包括：确定接收序列、编码参数和译码参数；然后用接收序列的软值初始化EF-polar码的软值L EF，如l EF1，…，l EFM，用其中的N个比特的软值L s(如ls 1，…，ls N)初始化EF-polar码的前N个比特的软值L p；当curIter(表示当前的迭代轮数)小于ITER max时，计算外信息L ex＝L p-L s；接着，将L EF和L ex输入到BP译码器进行一轮迭代，得到更新后的EF-polar码的软值L EF；同时，将L EF中N个比特所在的位置上的软值L s取出，输入到CA-SCL译码器进行译码，得到polar码的最佳译码路径u 1,…,u K以及对应的序列c 1,…,c N的软值L p，如lp 1,…,lp N；当u 1,…,u K未通过CRC校验时进行下一轮迭代。以此类推，直至curIter不小于ITER max，输出最佳译码路径u 1,…,u K以及L s和L c。
示例性的，图9b是本申请实施例提供的一种译码方法的示意图。接收端获取接收序列y 1，y 2，…,y M(即上文所示的第二待译码序列)，可理解，这里所示的M表示接收符号长度。然后，通过LDPC译码(LDPC Dec)获得N个比特的接收序列(即上文所示的第一待译码序列)，以及通过极化码译码(polar Dec)获得N个比特的译码路径u 1,…,u K以及对应的lp 1,…,lp N。如果译码错误或未达到ITER max，则根据外信息lex 1,…,lex N再次进行LDPC译码和polar码译码(polar Dec)，直至译码正确或达到了ITER max，输出最佳译码路径u 1,…,u K。可选的，还可以输出L s和L c。
可理解，图9a和图9b所示的方法仅为示例，不应将其理解为对本申请实施例的限定。如上述LDPC译码和极化码译码仅为本申请实施例的一种举例，对于第二信道译码和第一信道译码的具体方法不作限定。
本申请实施例提供的方法，可以通过E个校验比特产生的软值来辅助N个比特的译码，而且支持早停的译码策略，即LDPC Dec每次迭代一轮，然后将译码结果送给Polar Dec译码，允许最大尝试轮数为ITER max，停止条件为达到ITER max或者Polar Dec译码成功。
图9c是本申请实施例提供的一种EF-polar码的最大译码复杂度和平均译码复杂度的对比示意图。可理解，图9c中的横轴表示SNR，坐标表示迭代次数(iterNum)。图9c左边示出的是以R＝0.5，N＝1024，K＝512，E＝{0,2004,400,600,800,1000}为例示出的EF-polar码在大迭代译码下的最大以及平均迭代轮数。图9c右边示出的是以R＝0.75，N＝1024，K＝768，E＝{0,2004,400,600,800,1000}为例示出的EF-polar码在大迭代译码下的最大以及平均迭代轮数。从图9c可以看出：给定目标码长M，平均迭代轮数随着SNR增加而快速降低；随着目标码长M的增加，性能收敛所需的最小迭代次数呈现上升趋势。可理解，图9c中，采用的调制方式为QPSK或AWGN。
本申请提供的EF-polar码在保持polar码结构性强以及译码效率高等特点的同时，还兼具了LDPC码的码长扩展灵活和易于产生软值的优点，有效融合了LDPC码和NR polar码的优点。
图9d至图9g示出的是本申请实施例提出的编码方法、重复编码方法、长码编码方法的性能对比示意图。可理解，图9d至图9g中，校验比特的范围是0到1000比特，码长N＝{1024，992}，码率R＝{0.5，0.75}。示例性的，重复编码和长码编码的译码采用CA24-SCL8译码，本申请实施例提出的译码采用图9a中的译码流程，最大迭代轮数为12轮。示例性的，重复编码和长码编码的在线构造采用自然顺序(nature，NAT)+Puncture+高斯近似(gaussian Approximition，GA)，本申请实施例提出的编码方法的在线构造可以上述实施例给出的在线构造流程。示例性的，重复编码离线构造采用5G NR离线序列，长码编码的离线构造采用比特逆序(bit reversal，BIV)+Shorten+极化权重(polarization weight，PW)，本申请实施例提出的编码方法的离线构造采用表1或表2中的优化的离线序列。调制方式为QPSK。
可理解，图9d示出的是码长相同，码率不同时，在线构造下的性能对比。图9e示出的是码长不同，码率相同时，在线构造下的性能对比。图9f示出的是码长相同，码率不同时，离线构造下的性能对比。图9g示出的是码长不同，码率相同时，离线构造下的性能对比。
从图9d至图9g可以看出：本申请实施例提出的编码方法优于重复编码方法，同时，本申请实施例提出的编码方法的性能与长码编码性能的差距较小，在一些场景下甚至要优于长码性能。如本申请实施例提出的编码方法不仅具有较大的编码增益，尤其是在SC或CA-SCL8译码性能下能够优于长码编码的性能。
图10是本申请实施例提供的一种编码方法和译码方法的示意图。如图10所示，发送端可以对K个信息比特如u 1,…,u K进行第一信道编码，获得第二比特序列，如c 1,c 2…,c N；然后通过内交织获得序列d 1,d 2…,d N(如通过内交织器序列得到)；对该序列d 1,d 2…,d N进行第二信道编码，获得第三比特序列如x 1,x 2…,x N,x N+1,…,x N+E。然后通过对该第三比特序列进行调制，获得发送序列如s 1,s 2…,s T。可理解，图10所示的第一信道编码和第二信道编码可以通过不同的编码器实现，或者该第一信道编码和第二信道编码还可以通过一个编码器实现。示例性的，图10所示的第一信道编码、内交织和第二信道编码也可以称为编码，如图10所示的虚线部分。
如图10所示，接收端通过信道获得接收序列r 1,r 2…,r T，T为接收序列的长度。可理解，图10是以发送序列与接收序列的长度相同为例示出的，在具体实现中，该发送序列与接收序列的长度可能会所有不同。接收端对该接收序列进行解调，获得第二待译码序列y 1,y 2…,y M，然后对该第二待译码序列y 1,y 2…,y M进行第二信道译码和第一信道译码，获得K个信息比特。或者，接收端对接收序列进行解调及译码后，获得K个信息比特。可理解，第一信道译码和第二信道译码可以通过一个译码器实现的，或者该第一信道译码和该第二信道译码还可以通 过不同的译码器实现，本申请实施例不作限定。或者，解调和译码都可以通过同一个器件实现等，本申请实施例不作限定。
从上文所示的EF-polar码的编码方法可以看出，相同目标码长M下的EF-polar码编码复杂度要低于基于长码扩展的NR polar编码复杂度；比基于重复扩展的NR polar编码方案略高，且高出值仅和校验比特数目
Figure PCTCN2022116922-appb-000098
相关。表4给出了不同编码策略的编码复杂度。从灵活扩展的角度来看，EF-polar码的灵活程度远高于NR polar长码扩展的编码方案，特别是编码长度M超出polar母码长N较少的时候，使用EF-polar的性价比最高。
表4
Figure PCTCN2022116922-appb-000099
从译码角度看，EF-polar在CA-SCL译码下所需的存储空间和搜索复杂度相比于NR polar长码要更低，因为EF-polar码在SCL译码过程中所需维护的路径长度更短。同时和纯LDPC译码相比，EF-polar规则的系统编码结构使其具有更高的译码效率，在相同码长下比纯LDPC码具有更低的复杂度。同时EF-polar译码可以输出包括扩展比特在内的多种软值，解决了NR polar不易产生软值的问题。
本申请实施例中，利用polar码产生EF-polar码的N个比特可以获得比NR polar码更好的纠错性能。利用扩展矩阵产生EF-polar码的校验比特，可以更灵活的扩展码长，并且更容易产生软值。同时，利用大迭代译码在产生可以在信息比特估计值的同时，还能产生相应的软值，因此更适合数据信道中多用户检测等场景；而且本申请提出的EF-polar译码策略具有早停的特点，能有效降低译码时延和译码复杂度。
本申请上文所示的编码方法和译码方法还可以应用于数据包层面，即上文所示的N个比特可以是数据包层面的数据块，同样的，校验数据包也可以通过扩展矩阵生成。
以下将介绍本申请实施例提供的通信装置。
本申请根据上述方法实施例对通信装置进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。下面将结合图11至图13详细描述本申请实施例的通信装置。
图11是本申请实施例提供的一种通信装置的结构示意图，如图11所示，该通信装置包括处理单元1101和收发单元1102。
在本申请的一些实施例中，该通信装置可以是上文示出的发送端或发送端中的芯片等。即该通信装置可以用于执行上文方法实施例中由发送端执行的步骤或功能等。
处理单元1101，用于获取第一比特序列和目标码长M；对该第一比特序列进行第一信道编码，获得第二比特序列；根据该第二比特序列进行第二信道编码，获得第三比特序列；
处理单元1101，用于输出第三比特序列。
可理解，上述处理单元1101获取第一比特序列还可以包括：处理单元1101对收发单元1102输入的待处理数据进行数据，获得该第一比特序列；或者，处理单元1101通过收发单元1102获取第一比特序列等，本申请实施例对此不作限定。
在一种可能的实现方式中，处理单元1101，具体用于根据第二比特序列和扩展矩阵进行 第二信道编码。
在一种可能的实现方式中，处理单元1101，具体用于根据内交织器序列对第一比特序列进行第一信道编码。
本申请实施例中，关于第一比特序列、第二比特序列、第三比特序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述可以参考上文所示的方法实施例，这里不再一一详述。示例性的，关于扩展矩阵和扩展基矩阵的说明可以参考关于图5a至图5d，关于第一可靠度序列和第二可靠度序列可以参考图6a至图6d等。
可理解，本申请实施例示出的收发单元和处理单元的具体说明仅为示例，对于收发单元和处理单元的具体功能或执行的步骤等，可以参考上述方法实施例，这里不再详述。示例性的，处理单元1101还可以用于执行图5c和图5d所示的生成扩展基矩阵的步骤或功能等。
复用图11，在本申请的另一些实施例中，该通信装置可以是上文示出的接收端或接收端中的芯片等。即该通信装置可以用于执行上文方法实施例中由接收端执行的步骤或功能等。
处理单元1101，用于获取第二待译码序列；根据扩展矩阵对该第二待译码序列进行第二信道译码，获得第一待译码序列；以及根据第一可靠度序列对该第一待译码序列进行第一信道译码，获得第一比特序列。
可理解，以上所示的处理单元1101，用于获取第二待译码序列还可以理解为：收发单元1102，用于输入待处理的数据(如接收序列)；逻辑电路，对该待处理的数据进行处理，获得第二待译码序列；或者，处理单元1101通过收发单元1102从其他装置或部件等获得该第三二待译码序列。
在一种可能的实现方式中，处理单元1101，具体用于根据第一可靠度序列和内交织器序列对第一待译码序列进行第一信道译码。
本申请实施例中，关于第一比特序列、第一待译码序列、第二待译码序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述可以参考上文所示的方法实施例，这里不再一一详述。示例性的，关于扩展矩阵和扩展基矩阵的说明可以参考关于图5a至图5d，关于第一可靠度序列和第二可靠度序列可以参考图6a至图6d等。
可理解，本申请实施例示出的收发单元和处理单元的具体说明仅为示例，对于收发单元和处理单元的具体功能或执行的步骤等，可以参考上述方法实施例，这里不再详述。示例性的，处理单元1101还可以用于执行图9a和图9b所示的译码方法的步骤或功能等。
以上介绍了本申请实施例的发送端和接收端，以下介绍所述发送端和接收端可能的产品形态。应理解，但凡具备上述图11所述的发送端的功能的任何形态的产品，或者，但凡具备上述图11所述的接收端的功能的任何形态的产品，都落入本申请实施例的保护范围。还应理解，以下介绍仅为举例，不限制本申请实施例的发送端和接收端的产品形态仅限于此。
在一种可能的实现方式中，图11所示的通信装置中，处理单元1101可以是一个或多个处理器，收发单元1102可以是收发器，或者收发单元1102还可以是发送单元和接收单元，发送单元可以是发送器，接收单元可以是接收器，该发送单元和接收单元集成于一个器件，例如收发器。本申请实施例中，处理器和收发器可以被耦合等，对于处理器和收发器的连接方式，本申请实施例不作限定。
如图12所示，该通信装置120包括一个或多个处理器1220和收发器1210。
示例性的，当该通信装置用于执行上述发送端执行的步骤或方法或功能时，处理器1220，用于获取第一比特序列和目标码长M；对该第一比特序列进行第一信道编码，获得第二比特 序列；根据该第二比特序列进行第二信道编码，获得第三比特序列；以及输出第三比特序列。
示例性的，当该通信装置用于执行上述接收端执行的步骤或方法或功能时，处理器1220，用于获取第二待译码序列；根据扩展矩阵对该第二待译码序列进行第二信道译码，获得第一待译码序列；以及根据第一可靠度序列对该第一待译码序列进行第一信道译码，获得第一比特序列。
本申请实施例中，关于第一比特序列、第一待译码序列、第二待译码序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述可以参考上文所示的方法实施例，这里不再一一详述。
可理解，对于处理器和收发器的具体说明还可以参考图11所示的处理单元和收发单元的介绍，这里不再赘述。
在图12所示的通信装置的各个实现方式中，收发器可以包括接收机和发射机，该接收机用于执行接收的功能(或操作)，该发射机用于执行发射的功能(或操作)。以及收发器用于通过传输介质和其他设备/装置进行通信。
可选的，通信装置120还可以包括一个或多个存储器1230，用于存储程序指令和/或数据。存储器1230和处理器1220耦合。本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器1220可能和存储器1230协同操作。处理器1220可以执行存储器1230中存储的程序指令。可选的，上述一个或多个存储器中的至少一个可以包括于处理器中。本申请实施例中，存储器1230中可以存储有扩展基矩阵或第二可靠度序列等中的任一项或多项等。示例性的，图12示出的存储器中仅示例性的示出了扩展基矩阵和第二可靠度序列等。可理解，图12中用虚线表示存储器中存储了扩展基矩阵和第二可靠度序列，是因为该存储器中可能扩展基矩阵和第二可靠度序列，或者，也可能仅存储扩展基矩阵，或者不存储扩展基矩阵和第二可靠度序列等。
本申请实施例中不限定上述收发器1210、处理器1220以及存储器1230之间的具体连接介质。本申请实施例在图12中以存储器1230、处理器1220以及收发器1210之间通过总线1240连接，总线在图12中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图12中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成等。
本申请实施例中，存储器可包括但不限于硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等非易失性存储器，随机存储记忆体(Random Access Memory，RAM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、只读存储器(Read-Only Memory，ROM)或便携式只读存储器(Compact Disc Read-Only Memory，CD-ROM)等等。存储器是能够用于携带或存储具有指令或数据结构形式的程序代码，并能够由计算机(如本申请示出的通信装置等)读和/或写的任何存储介质，但不限于此。本申请实施例中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
处理器1220主要用于对通信协议以及通信数据进行处理，以及对整个通信装置进行控制， 执行软件程序，处理软件程序的数据。存储器1230主要用于存储软件程序和数据。收发器1210可以包括控制电路和天线，控制电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。
当通信装置开机后，处理器1220可以读取存储器1230中的软件程序，解释并执行软件程序的指令，处理软件程序的数据。当需要通过无线发送数据时，处理器1220对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到通信装置时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器1220，处理器1220将基带信号转换为数据并对该数据进行处理。
在另一种实现中，所述的射频电路和天线可以独立于进行基带处理的处理器而设置，例如在分布式场景中，射频电路和天线可以与独立于通信装置，呈拉远式的布置。
可理解，本申请实施例示出的通信装置还可以具有比图12更多的元器件等，本申请实施例对此不作限定。以上所示的处理器和收发器所执行的方法仅为示例，对于该处理器和收发器具体所执行的步骤可参照上文介绍的方法。
在另一种可能的实现方式中，图11所示的通信装置中，处理单元1101可以是一个或多个逻辑电路，收发单元1102可以是输入输出接口，又或者称为通信接口，或者接口电路，或接口等等。或者收发单元1102还可以是发送单元和接收单元，发送单元可以是输出接口，接收单元可以是输入接口，该发送单元和接收单元集成于一个单元，例如输入输出接口。如图13所示，图13所示的通信装置包括逻辑电路1301和接口1302。即上述处理单元1101可以用逻辑电路1301实现，收发单元1102可以用接口1302实现。其中，该逻辑电路1301可以为芯片、处理电路、集成电路或片上系统(system on chip，SoC)芯片等，接口1302可以为通信接口、输入输出接口、管脚等。示例性的，图13是以上述通信装置为芯片为例出的，该芯片包括逻辑电路1301和接口1302。
本申请实施例中，逻辑电路和接口还可以相互耦合。对于逻辑电路和接口的具体连接方式，本申请实施例不作限定。
示例性的，当通信装置用于执行上述发送端执行的方法或功能或步骤时，逻辑电路1301，用于获取第一比特序列；逻辑电路1301，还用于对第一比特序列进行第一信道编码，获得第二比特序列；以及根据第二比特序列进行第二信道编码，获得第三比特序列；接口1302，还用于输出第三比特序列。
可理解，以上所示的逻辑电路1301，用于获取第一比特序列；还可以理解为：逻辑电路1301，用于通过接口1302输入待处理的数据，以及对该待处理的数据进行处理，获得该第一比特序列。该第一比特序列可以是通过接口从其他装置或部件中输入至逻辑电路中的，也可以是逻辑电路对接口输入的其他数据进行处理后获得的，本申请实施例对此不作限定。可理解，以上所示的接口，用于输出第三比特序列，还可以理解为：逻辑电路，控制接口输出该第三比特序列；或者，逻辑电路，用于对该第三比特序列进行其他处理后，通过接口输出对第三比特序列进行处理后得到的序列。
示例性的，当通信装置用于执行上述接收端执行的方法或功能或步骤时，逻辑电路1301，用于获得第二待译码序列，并根据扩展矩阵对第二待译码序列进行第二信道译码，获得第一待译码比特序列；以及根据第一可靠度序列对第一待译码序列进行第一信道译码，获得第一 比特序列。
可理解，以上所示的逻辑电路1301，用于获得第二待译码序列；还可以理解为：接口1302，用于输入待处理的数据(如通过信道获得的接收序列等)，逻辑电路1301，对该接口1302输入的待处理的数据进行处理，获得第二待译码序列；或者，逻辑电路1301，通过接口1302输入该第二待译码序列等。
可选的，该通信装置还包括存储器1303，该存储器1303可以用于存储扩展基矩阵或第二可靠度序列中的一项或多项。
可理解，本申请实施例示出的通信装置可以采用硬件的形式实现本申请实施例提供的方法，也可以采用软件的形式实现本申请实施例提供的方法等，本申请实施例对此不作限定。
关于第一比特序列、第二比特序列、第三比特序列、第一待译码序列、第二待译码序列、第一信道编码、第二信道编码、扩展矩阵、扩展基矩阵、第一可靠度序列和第二可靠度序列等的描述可以参考上文所示的方法实施例，这里不再一一详述。
对于图13所示的各个实施例的具体实现方式，还可以参考上述各个实施例，这里不再详述。
本申请实施例还提供了一种无线通信系统，该无线通信系统包括发送端和接收端，该发送端和该接收端可以用于执行前述任一实施例中的方法。
此外，本申请还提供一种计算机程序，该计算机程序用于实现本申请提供的方法中由发送端执行的操作和/或处理。
本申请还提供一种计算机程序，该计算机程序用于实现本申请提供的方法中由接收端执行的操作和/或处理。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机代码，当计算机代码在计算机上运行时，使得计算机执行本申请提供的方法中由发送端执行的操作和/或处理。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机代码，当计算机代码在计算机上运行时，使得计算机执行本申请提供的方法中由接收端执行的操作和/或处理。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机代码或计算机程序，当该计算机代码或计算机程序在计算机上运行时，使得本申请提供的方法中由发送端执行的操作和/或处理被执行。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机代码或计算机程序，当该计算机代码或计算机程序在计算机上运行时，使得本申请提供的方法中由接收端执行的操作和/或处理被执行。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例提供的方案的技 术效果。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个可读存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的可读存储介质包括：U盘、移动硬盘、只读存储器(read-only memory,ROM)、随机存取存储器(random access memory,RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (45)

  1. 一种编码方法，其特征在于，所述方法包括：
    获取第一比特序列和目标码长M，所述第一比特序列包括K个信息比特，所述K为大于或等于1的整数，所述M为大于或等于1的整数；
    对所述第一比特序列进行第一信道编码，获得第二比特序列，所述第二比特序列包括N个比特，所述N为大于或等于1的整数；
    根据所述第二比特序列进行第二信道编码，获得第三比特序列，所述第三比特序列包括所述N个比特和E个校验比特，所述E为大于或等于1的整数，M>N，且E＝M-N；
    输出所述第三比特序列。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第二比特序列进行第二信道编码包括：
    根据所述第二比特序列和扩展矩阵进行第二信道编码，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述E 0和所述N 0都是大于或等于1的整数。
  3. 根据权利要求2所述的方法，其特征在于，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
  4. 根据权利要求2或3所述的方法，其特征在于，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
  5. 根据权利要求3或4所述的方法，其特征在于，Z＝16。
  6. 根据权利要求2-5任一项所述的方法，其特征在于，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，
    所述扩展矩阵的E列是第一矩阵中相邻的E列，所述第一矩阵中相邻的E列是根据第一信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
  7. 根据权利要求2-6任一项所述的方法，其特征在于，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
  8. 根据权利要求7所述的方法，其特征在于，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：
    与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，所述K个信息比特的位置根据第一可靠度序列确定，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N。
  10. 根据权利要求9所述的方法，其特征在于，所述第二可靠度序列满足如下关系：
    Figure PCTCN2022116922-appb-100001
    Figure PCTCN2022116922-appb-100002
    Figure PCTCN2022116922-appb-100003
    Figure PCTCN2022116922-appb-100004
    其中，
    Figure PCTCN2022116922-appb-100005
    为可靠度序列，其中元素是子信道的序号，
    Figure PCTCN2022116922-appb-100006
    表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
  11. 根据权利要求2-10任一项所述的方法，其特征在于，所述对所述第一比特序列进行第一信道编码包括：
    根据内交织器序列对所述第一比特序列进行第一信道编码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
  12. 一种译码方法，其特征在于，所述方法包括：
    获取第二待译码序列，所述第二待译码序列包括N个比特的信息和E个校验比特的信息，所述N为大于或等于1的整数，所述E为大于或等于1的整数；
    根据扩展矩阵对所述第二待译码序列进行第二信道译码，获得第一待译码序列，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述第一待译码序列包括所述N个比特的信息，所述E 0和所述N 0都是大于或等于1的整数；
    根据第一可靠度序列对所述第一待译码序列进行第一信道译码，获得第一比特序列，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N，所述第一比特序列包括K个信息比特。
  13. 根据权利要求12所述的方法，其特征在于，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
  14. 根据权利要求12或13所述的方法，其特征在于，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
  15. 根据权利要求13或14所述的方法，其特征在于，Z＝16。
  16. 根据权利要求12-15任一项所述的方法，其特征在于，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，
    所述扩展矩阵的E列是第一矩阵中相邻的E列，所述第一矩阵中相邻的E列是根据第一信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
  17. 根据权利要求12-16任一项所述的方法，其特征在于，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
  18. 根据权利要求17所述的方法，其特征在于，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：
    与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
  19. 根据权利要求12-18任一项所述的方法，其特征在于，所述第二可靠度序列满足如下关系：
    Figure PCTCN2022116922-appb-100007
    Figure PCTCN2022116922-appb-100008
    Figure PCTCN2022116922-appb-100009
    Figure PCTCN2022116922-appb-100010
    其中，
    Figure PCTCN2022116922-appb-100011
    为可靠度序列，其中元素是子信道的序号，
    Figure PCTCN2022116922-appb-100012
    表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
  20. 根据权利要求12-19任一项所述的方法，其特征在于，所述根据第一可靠度序列对所述第一待译码序列进行第一信道译码包括：
    根据所述第一可靠度序列和内交织器序列对所述第一待译码序列进行第一信道译码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
  21. 一种通信装置，其特征在于，包括：
    处理单元，用于获取第一比特序列和目标码长M，所述第一比特序列包括K个信息比特，所述K为大于或等于1的整数，所述M为大于或等于1的整数；
    所述处理单元，还用于对所述第一比特序列进行第一信道编码，获得第二比特序列，所述第二比特序列包括N个比特，所述N为大于或等于1的整数；
    所述处理单元，还用于根据所述第二比特序列进行第二信道编码，获得第三比特序列，所述第三比特序列包括所述N个比特和E个校验比特，所述E为大于或等于1的整数，M>N，且E＝M-N；
    所述处理单元，还用于输出所述第三比特序列。
  22. 根据权利要求21所述的装置，其特征在于，所述处理单元，具体用于根据所述第二比特序列和扩展矩阵进行第二信道编码，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述E 0和所述N 0都是大于或等于1的整数。
  23. 根据权利要求22所述的装置，其特征在于，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
  24. 根据权利要求22或23所述的装置，其特征在于，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
  25. 根据权利要求23或24所述的装置，其特征在于，Z＝16。
  26. 根据权利要求22-25任一项所述的装置，其特征在于，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，
    所述扩展矩阵的E列是第一矩阵中相邻的E列，所述第一矩阵中相邻的E列是根据第一信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
  27. 根据权利要求22-26任一项所述的装置，其特征在于，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
  28. 根据权利要求27所述的装置，其特征在于，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：
    与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
  29. 根据权利要求21-28任一项所述的装置，其特征在于，所述K个信息比特的位置根据第一可靠度序列确定，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N。
  30. 根据权利要求29所述的装置，其特征在于，所述第二可靠度序列满足如下关系：
    Figure PCTCN2022116922-appb-100013
    Figure PCTCN2022116922-appb-100014
    Figure PCTCN2022116922-appb-100015
    其中，
    Figure PCTCN2022116922-appb-100016
    为可靠度序列，其中元素是子信道的序号，
    Figure PCTCN2022116922-appb-100017
    表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
  31. 根据权利要求22-30任一项所述的装置，其特征在于，所述处理单元，具体用于根据内交织器序列对所述第一比特序列进行第一信道编码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
  32. 一种通信装置，其特征在于，包括：
    处理单元，用于获取第二待译码序列，所述第二待译码序列包括N个比特的信息和E个校验比特的信息，所述N为大于或等于1的整数，所述E为大于或等于1的整数；
    所述处理单元，还用于根据扩展矩阵对所述第二待译码序列进行第二信道译码，获得第一待译码序列，所述扩展矩阵包括N行E列，所述扩展矩阵根据扩展基矩阵得到，所述扩展基矩阵包括N 0行E 0列，所述第一待译码序列包括所述N个比特的信息，所述E 0和所述N 0都是大于或等于1的整数；
    所述处理单元，还用于根据第一可靠度序列对所述第一待译码序列进行第一信道译码，获得第一比特序列，所述第一可靠度序列的长度为所述N，所述第一可靠度序列为第二可靠度序列的子序列，所述第二可靠度序列的长度为N max，所述N max大于或等于所述N，所述第一比特序列包括K个信息比特。
  33. 根据权利要求32所述的装置，其特征在于，所述扩展基矩阵的扩展因子Z为素数；或者，Z＝2 n，所述Z为所述扩展基矩阵的扩展因子，所述n为大于或等于0的整数。
  34. 根据权利要求32或33所述的装置，其特征在于，Z＝N/N 0，所述Z为所述扩展基矩阵的扩展因子。
  35. 根据权利要求33或34所述的装置，其特征在于，Z＝16。
  36. 根据权利要求32-35任一项所述的装置，其特征在于，所述扩展矩阵的E列是第一矩阵的前E列，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵；或者，
    所述扩展矩阵的E列是第一矩阵中相邻的E列，所述第一矩阵中相邻的E列是根据第一 信道编码的码率确定的，所述第一矩阵是所述扩展基矩阵根据扩展因子扩展后的矩阵。
  37. 根据权利要求32-36任一项所述的装置，其特征在于，所述扩展矩阵中某一列的列重与所述N、所述K和所述E有关。
  38. 根据权利要求37所述的装置，其特征在于，所述扩展矩阵中某一列的列重满足如下关系中的任一项或多项：
    与所述E成负相关、与所述K成正相关、与所述N成负相关、与K/N成正相关。
  39. 根据权利要求32-38任一项所述的装置，其特征在于，所述第二可靠度序列满足如下关系：
    Figure PCTCN2022116922-appb-100018
    Figure PCTCN2022116922-appb-100019
    Figure PCTCN2022116922-appb-100020
    其中，
    Figure PCTCN2022116922-appb-100021
    为可靠度序列，其中元素是子信道的序号，
    Figure PCTCN2022116922-appb-100022
    表示与可靠度序列对应的可靠度，所述i为大于或等于1，且小于或等于N max的整数。
  40. 根据权利要求32-39任一项所述的装置，其特征在于，所述处理单元，具体用于根据所述第一可靠度序列和内交织器序列对所述第一待译码序列进行第一信道译码，所述内交织器序列根据所述扩展矩阵确定，所述内交织器序列的块的大小等于所述扩展矩阵的扩展因子。
  41. 一种通信装置，其特征在于，包括处理器和存储器；
    所述存储器用于存储指令；
    所述处理器用于执行所述指令，使得权利要求1-20任一项所述的方法被执行。
  42. 一种通信装置，其特征在于，包括逻辑电路和输入输出接口，所述逻辑电路和所述输入输出接口耦合；
    所述输入输出接口用于输入待处理的数据，所述逻辑电路按照如权利要求1-20任一项所述的方法对所述待处理的数据进行处理，获得处理后的数据，所述输入输出接口用于输出所述处理后的数据。
  43. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质用于存储计算机程序，当所述计算机程序被执行时，权利要求1-20任一项所述的方法被执行。
  44. 一种包括指令的计算机程序产品，其特征在于，当所述指令在计算机上运行时，使得权利要求1-20任一项所述的方法被执行。
  45. 一种通信系统，其特征在于，所述系统包括发送端和接收端，所述发送端用于执行如权利要求1-10任一项所述的方法，所述接收端用于执行如权利要求11-20任一项所述的方法。
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