WO2023241626A1 - Ldpc的编译码方法和相关装置 - Google Patents

Ldpc的编译码方法和相关装置 Download PDF

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Publication number
WO2023241626A1
WO2023241626A1 PCT/CN2023/100206 CN2023100206W WO2023241626A1 WO 2023241626 A1 WO2023241626 A1 WO 2023241626A1 CN 2023100206 W CN2023100206 W CN 2023100206W WO 2023241626 A1 WO2023241626 A1 WO 2023241626A1
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Prior art keywords
matrix
check matrix
check
integer
cpm
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PCT/CN2023/100206
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English (en)
French (fr)
Inventor
蒙托里西基多
贝勒迪多塞吉奥
林伟
杨讯
辛岩
淦明
马梦瑶
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华为技术有限公司
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Publication of WO2023241626A1 publication Critical patent/WO2023241626A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes

Definitions

  • the present application relates to the field of communication technology, and in particular to an LDPC encoding and decoding method and related devices.
  • Wireless local area networks (WLAN) transmission standards such as IEEE802.11n/ac/ax/be focus on improving user experience in large-bandwidth scenarios, including improving average user throughput and energy efficiency of battery-powered equipment.
  • the 60GHz large-bandwidth scenario needs to support high-speed and reliable transmission of data, video and other services on limited frequency and power resources, so a highly reliable and efficient channel coding and decoding solution is required.
  • Turbo codes and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods. They both have performance close to the Shannon limit.
  • LDPC codes have: good bit error performance without the need for deep interleaver; better frame error rate performance; greatly reduced error level; support for parallel decoding, small decoding delay Etc.
  • LDPC codes have become the standard channel coding scheme for low-frequency short-distance WLAN communication systems such as IEEE802.11n/ac/ax, and become the necessary channel coding scheme when IEEE802.11ax is greater than or equal to 40MHz bandwidth. Based on this, we can consider designing new LDPC codes for the next generation WLAN standard or ultra wide band (UWB) to further improve the reliability and system performance of the next generation WLAN system or UWB system.
  • UWB ultra wide band
  • the embodiment of the present application discloses an LDPC encoding and decoding method and related devices, which can reduce the complexity of encoding.
  • embodiments of the present application provide an LDPC code encoding method.
  • the method includes: performing low-density parity check LDPC encoding on the first bit sequence according to a check matrix to obtain the first data packet.
  • the check The matrix includes a first check matrix and a second check matrix. Both the first check matrix and the second check matrix conform to the first basis matrix.
  • the code length of the first check matrix and the third check matrix are The code lengths of the two check matrices are different; send the first data packet.
  • both the first check matrix and the second check matrix conform to the first basis matrix.
  • the first base matrix that is, the first base matrix
  • the first check matrix and the second check matrix with different code lengths are obtained by expansion.
  • Implementing multiple basis matrices requires greater power consumption and increased coding complexity than implementing one basis matrix.
  • multiple check matrices are obtained by extending a base matrix. Only one base matrix needs to be implemented instead of multiple base matrices, which can reduce the power consumption of the hardware and reduce the complexity of coding.
  • performing low-density parity check LDPC encoding on the first bit sequence according to the check matrix to obtain the first data packet includes: when the length of the first bit sequence is located in the first interval In the case of , perform low-density parity check LDPC encoding on the first bit sequence according to the first check matrix to obtain the first data packet; or, when the length of the first bit sequence is in the second In the case of interval, perform low-density parity check LDPC encoding on the first bit sequence according to the second check matrix to obtain the first data packet; the first interval and The second intervals do not overlap.
  • a check matrix with an appropriate code length is flexibly selected according to the length of the first bit sequence to perform LDPC encoding on the first bit sequence.
  • the most reasonable check matrix can be expanded to perform LDPC encoding, which can improve resource utilization.
  • embodiments of the present application provide a method for decoding LDPC codes.
  • the method includes: obtaining the first log-likelihood ratio LLR sequence corresponding to the received first channel reception sequence; and, according to the check matrix, The first LLR sequence is decoded, and the check matrix includes a first check matrix and a second check matrix, and both the first check matrix and the second check matrix conform to the first basis matrix, so The code length of the first check matrix and the code length of the second check matrix are different.
  • both the first check matrix and the second check matrix conform to the first basis matrix.
  • the first base matrix that is, the first base matrix
  • the first check matrix and the second check matrix with different code lengths are obtained by expansion.
  • Implementing multiple basis matrices requires greater power consumption and increased coding complexity than implementing one basis matrix.
  • multiple check matrices are obtained by extending a base matrix. Only one base matrix needs to be implemented instead of multiple base matrices, which can reduce the power consumption of the hardware and reduce the complexity of coding.
  • the specific value of the expansion factor of the cyclic displacement matrix CPM at the first position in the first check matrix is b, and in the first check matrix
  • the expansion factor of the CPM at the first position is Z1
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z)
  • the first position in the second check matrix is Z2
  • the Z, the Z1, and the Z2 are all integers greater than 0, the Z1 is greater than or equal to the Z, and the Z2 is less than the Z.
  • the first position can be any position in the first check matrix.
  • Z is an integral multiple of 27, such as 27, 54, 81, etc.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z).
  • the first check matrix and the second check matrix are obtained by extending the first base matrix. Only the first base matrix needs to be implemented, and multiple base matrices need to be implemented, which can reduce the power consumption of the hardware and reduce the complexity of coding.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the first value in the first check matrix is
  • the expansion factor of the CPM of the position is Z3
  • the specific value of the expansion factor of the CPM of the first position in the second check matrix is any one of b, (b+Z), (b+2Z), and the third
  • the expansion factor of the CPM at the first position in the two check matrices is Z4, the Z, the Z3, and the Z4 are all integers greater than 0, the Z3 is less than the Z, and the Z4 is greater than or equal to Describe Z.
  • the first position can be any position in the first check matrix.
  • Z and Z4 are both integral multiples of 27, for example, Z is 27, Z4 is 54, 81, etc.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is b, (b+Z ), (b+2Z) any one.
  • the first check matrix and the second check matrix are obtained by extending the first base matrix. Only the first base matrix needs to be implemented, and multiple base matrices do not need to be implemented, which can reduce the complexity and power consumption of hardware implementation.
  • the first basis matrix corresponds to the original check matrix
  • the expansion factor of the CPM in the original check matrix is Z
  • the original check matrix The specific value of the expansion factor of the CPM at the first position of the matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b.
  • the expansion factor of CPM is Z1
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z)
  • the expansion factor of the CPM at the first position in the second check matrix is Z2
  • the Z, the Z1, and the Z2 are all integers greater than 0, the Z1 is greater than or equal to the Z, and the Z2 is less than the Z.
  • Z is an integral multiple of 27, such as 27, 54, 81, etc.
  • the check matrix further includes the original check matrix.
  • the specific value of the expansion factor of the cyclic displacement matrix CPM at the first position in the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z); can quickly expand to obtain the required check matrix.
  • the first basis matrix corresponds to the original check matrix
  • the expansion factor of the CPM in the original check matrix is Z
  • the original check matrix The specific value of the expansion factor of the CPM at the first position of the matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is (b mod Z)
  • the specific value of the expansion factor in the first check matrix is
  • the expansion factor of the CPM at the first position is Z3
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is any one of b, (b+Z), and (b+2Z)
  • the expansion factor of the CPM at the first position in the second check matrix is Z4, the Z, the Z3, and the Z4 are all integers greater than 0, the Z3 is less than the Z, and the Z4 is greater than or equal to the Z.
  • Z and Z4 are both integral multiples of 27, for example, Z is 27, Z4 is 54, 81, etc.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is (b mod Z)
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is b
  • the method further includes: extending the first basis matrix to obtain an original check matrix, and the expansion factor of the CPM in the original check matrix is Z; According to the original check matrix, obtain the first check matrix or the second check matrix, the expansion factor of the CPM at the first position in the first check matrix is Z1, and the third check matrix
  • the expansion factor of the CPM at the first position in the second check matrix is Z2, the specific value of the expansion factor of the cyclic displacement matrix CPM at the first position of the original check matrix is b, and the third check matrix in the first check matrix
  • the specific value of the expansion factor of the cyclic displacement matrix CPM at one position is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z)
  • the Z1, the The Z2 is an integer greater than 0, the Z1 is greater than or equal to the Z, and the Z2 is less than the Z.
  • the original check matrix may be the matrix shown in Figure 6, Figure 14 or Figure 15 below.
  • the first check matrix or the second check matrix is obtained based on the original check matrix; the required check matrix can be quickly obtained.
  • the method further includes: extending the first basis matrix to obtain an original check matrix, and the expansion factor of the CPM in the original check matrix is Z; According to the original check matrix, obtain the first check matrix or the second check matrix, the expansion factor of the CPM at the first position in the first check matrix is Z3, and the third check matrix
  • the expansion factor of the CPM at the first position in the second check matrix is Z4, the specific value of the expansion factor of the cyclic displacement matrix CPM at the first position of the original check matrix is b, and the first check matrix in the first check matrix has an expansion factor of
  • the specific value of the expansion factor of the CPM at one position is (b mod Z), and the specific value of the expansion factor of the CPM at the first position in the second check matrix is b, (b+Z), (b+2Z)
  • Any one of Z, Z3, and Z4 are all integers greater than 0, Z3 is less than Z, and Z4 is greater than or equal to Z.
  • Z and Z4 are both integral multiple
  • the first check matrix or the second check matrix is obtained based on the original check matrix; the required check matrix can be quickly obtained.
  • an embodiment of the present application provides a communication device, which has the function of implementing the behavior in the method embodiment of the first aspect.
  • the communication device may be a communication device, a component of the communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the communication device.
  • the functions of the communication device can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the communication device includes an interface module and a processing module, wherein: the processing module is configured to perform low-density processing on the first bit sequence according to the check matrix.
  • Parity check LDPC encoding is used to obtain the first data packet.
  • the check matrix includes a first check matrix and a second check matrix. Both the first check matrix and the second check matrix conform to the first check matrix.
  • the base matrix, the code length of the first check matrix and the code length of the second check matrix are different; the interface module is used to send the first data packet.
  • an embodiment of the present application provides a communication device, which has the function of implementing the behavior in the method embodiment of the second aspect.
  • the communication device may be a communication device, a component of the communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the communication device.
  • the functions of the communication device can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the communication device includes an interface module and a processing module, wherein: the interface module is used to receive the first channel reception sequence; the processing module is used to obtain the first channel reception sequence The corresponding first log-likelihood ratio LLR sequence; decode the first LLR sequence according to the check matrix, the check matrix includes a first check matrix and a second check matrix, the first Both the check matrix and the second check matrix conform to the first basis matrix, and the code length of the first check matrix and the code length of the second check matrix are different.
  • inventions of the present application provide another communication device.
  • the communication device includes a processor.
  • the processor is coupled to a memory.
  • the memory is used to store programs or instructions.
  • the communication device is caused to execute the above-mentioned first aspect or the method shown in any possible implementation of the first aspect, or, when the program or instruction is executed by the processor, the communication device is caused to execute the above-mentioned second aspect or the second aspect. Any possible implementation of the method shown.
  • the process of sending information (or signals) in the above method can be understood as a process of outputting information based on instructions of the processor.
  • the processor In outputting information, the processor outputs the information to the transceiver for transmission by the transceiver. After the information is output by the processor, it may also need to undergo other processing before reaching the transceiver.
  • the processor receives incoming information
  • the transceiver receives the information and feeds it into the processor. Furthermore, after the transceiver receives the information, the information may need to undergo other processing before being input to the processor.
  • the above-mentioned processor may be a processor specifically designed to perform these methods, or may be a processor that executes computer instructions in a memory to perform these methods, such as a general-purpose processor.
  • the processor may also be configured to execute a program stored in the memory.
  • the communication device performs the method shown in the above-mentioned first aspect or any possible implementation of the first aspect.
  • the memory is located outside the communication device. In a possible implementation, the memory is located within the above communication device.
  • the processor and the memory may be integrated into one device, that is, the processor and the memory may be integrated together.
  • the communication device further includes a transceiver, which is used to receive signals or send signals. No. etc.
  • the present application provides another communication device.
  • the communication device includes a processing circuit and an interface circuit.
  • the interface circuit is used to obtain data or output data; the processing circuit is used to perform the above-mentioned first aspect or any of the first aspects.
  • the corresponding method shown in the possible implementation manner, or the processing circuit is used to perform the corresponding method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect.
  • the present application provides a computer-readable storage medium.
  • a computer program is stored in the computer-readable storage medium.
  • the computer program includes program instructions. When executed, the program instructions cause the computer to perform the above-mentioned first aspect or the third aspect.
  • the present application provides a computer program product.
  • the computer program product includes a computer program.
  • the computer program includes program instructions. When executed, the program instructions cause the computer to perform the above-mentioned first aspect or any possible method of the first aspect. The method shown in the implementation manner, or, when executed, the program instructions cause the computer to perform the method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect.
  • the present application provides a communication system, including the communication device described in the above third aspect or any possible implementation of the third aspect, and the communication device described in the above fourth aspect or any possible implementation of the fourth aspect. Communication device.
  • Figure 1 is an example of a check matrix H of an LDPC code provided by this application.
  • Figure 2 is a Tanner diagram of a check matrix H of an LDPC code provided by an embodiment of the present application
  • Figure 3 is an example of the encoding process of an LDPC code provided by this application.
  • Figure 4 is a schematic diagram of the shortening operation part in an LDPC encoding process provided by an embodiment of the present application
  • FIG. 5 is an example of four types of CPM provided by the embodiment of this application.
  • Figure 6 is an example of a check matrix obtained by extending a base matrix of size (12 ⁇ 24) provided by the embodiment of the present application;
  • Figure 7 is an example of a wireless communication system to which the technical solution provided by this application is applicable.
  • Figure 8 is an interactive flow chart of an LDPC code encoding method provided by this application.
  • Figure 9 is an interactive flow chart of another LDPC code encoding method provided by this application.
  • Figure 10 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • Figure 11 is an example of a matrix representing a first basis matrix and a specific value matrix of expansion factors of four check matrices obtained by extending the first basis matrix according to the embodiment of the present application;
  • Figure 12 is an example of a first check matrix provided by an embodiment of the present application.
  • Figure 13 is an example of another matrix characterizing the first basis matrix and specific value matrices of expansion factors of four check matrices obtained by extending the first basis matrix according to the embodiment of the present application;
  • Figure 14 is an example of a check matrix obtained based on the expansion of base matrix 2 provided by this application.
  • Figure 15 is an example of a check matrix obtained based on the expansion of base matrix 2 provided by this application.
  • Figure 16A is a schematic diagram comparing the FER simulation performance of an LDPC code under 25 hierarchical decoding iterations provided by the embodiment of the present application;
  • Figure 16B is a comparison of FER simulation performance under 15 hierarchical decoding iterations of an LDPC code provided by the embodiment of the present application. schematic diagram;
  • Figure 16C is a schematic diagram comparing the FER simulation performance of an LDPC code under 5 hierarchical decoding iterations provided by the embodiment of the present application;
  • Figure 17A is a schematic diagram of the performance of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by an embodiment of the present application under 10 decoding iterations;
  • Figure 17B is a performance diagram of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by the embodiment of the present application under 15 decoding iterations;
  • Figure 17C is a performance diagram of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by the embodiment of the present application under 25 decoding iterations;
  • Figure 18A is a performance diagram of a check matrix 51, a check matrix 52, a check matrix 53, and a check matrix 54 provided by an embodiment of the present application under 10 decoding iterations;
  • Figure 18B is a performance diagram of a check matrix 51, a check matrix 52, a check matrix 53, and a check matrix 54 provided by the embodiment of the present application under 15 decoding iterations;
  • Figure 18C is a performance diagram of a check matrix 51, a check matrix 52, a check matrix 53, and a check matrix 54 provided by the embodiment of the present application under 25 decoding iterations;
  • Figure 19 is a schematic structural diagram of a communication device 1900 provided by an embodiment of the present application.
  • Figure 20 is a schematic structural diagram of another communication device 200 provided by an embodiment of the present application.
  • Figure 21 is a schematic structural diagram of another communication device 210 provided by an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • a corresponds to B means that A and B have a corresponding relationship, and B can be determined based on A.
  • determining (or generating) B according to (or based on) A does not mean only determining (or generating) B according to (or based on) A. It can also be determined according to (or based on) A and/or other information. or generate)B.
  • LDPC code low density parity check code.
  • the full name of LDPC code is low density parity check code.
  • it is a parity check code with low density properties.
  • the low density refers to the low density of the check matrix of the LDPC code. Therefore, to understand what LDPC code is, we must first understand the three concepts of parity check code, check matrix and low density.
  • Parity check code is a coding method that adds redundant bits so that the number of "1"s in the codeword is always an odd or even number. It is an error detection code. Parity check codes are often used for digital encoding in the binary field of 0-1. One or several bits (check bits) are added at the end of the code word, and the code is judged by whether the number of 1's in the code word is odd or even. Whether the word has errors before or after transmission. For example, if the codeword 100 uses parity check, then the check bit can be 1. At this time, the value s that satisfies the sum (exclusive OR) of all codewords is 0, which is 1001.
  • the algorithm fails. Therefore, further, multiple check bits can be set.
  • the four-bit codeword 1101 can be grouped and the first bit of the check bit is used to check the first and second bits of the information bit (that is, the first two bits of the information bit 11). For example, if the sum of the first two bits of the information bit is 0, then the first bit of the check bit should be 0.
  • the second bit of the check bit can check the last two information bits of codeword 1101, so the second bit of the check bit is set to 1.
  • the encoded codeword is 110101.
  • the low-density property of the LDPC code means that the number of 1's in the check matrix of the LDPC code is very small.
  • LDPC code is a linear block code, and its check matrix is a sparse matrix.
  • the number of zero elements in the check matrix of the LDPC code is far more than the number of non-zero elements.
  • the row weight (that is, the number of 1's in each row) and the column weight (that is, the number of 1's in each column) of the check matrix are very small numbers compared to the code length of the LDPC code.
  • the check relationship between the information bits and check bits of the codeword can be written in the form of a matrix. Record the information bits as c1, c2, c3, c4, and the check bits as p1, p2.
  • c [c1,c2,c3,c4]
  • x [c1,c2,c3,c4,p1,p2].
  • c and x are the codewords before and after encoding respectively.
  • H is the check matrix
  • s is the syndrome
  • H T represents the transpose of H.
  • ⁇ represents a matrix multiplication operation
  • a ⁇ B represents the matrix multiplication product of matrix A and matrix B.
  • c represents the unencoded codeword (or bit sequence)
  • G represents the generating matrix
  • the generating matrix can be obtained by transforming the check matrix. In other words, if you know the check matrix, you can get the generating matrix corresponding to the check matrix.
  • c can be called the information codeword
  • x can be called the transmission codeword.
  • Formula (2) shows that the transmitted codeword is obtained by multiplying the information codeword and the generator matrix.
  • Tanner represented the code words of the LDPC code graphically in 1981.
  • This kind of graph is now called a Tanner graph, and the Tanner graph has a one-to-one correspondence with the check matrix.
  • the Tanner graph consists of two types of vertices, one type of vertices are variable nodes, representing codeword bits, and the other type of vertices are check nodes, representing check constraint relationships.
  • Each verification node represents a verification constraint relationship, which will be explained below with reference to Figures 1 and 2.
  • Figure 1 is an example of a check matrix H of an LDPC code provided by this application.
  • ⁇ V i ⁇ represents the variable node set
  • ⁇ C i ⁇ represents the check node set.
  • Each row of the check matrix H corresponds to a check equation
  • each column corresponds to a codeword bit.
  • FIG. 2 is a Tanner diagram of a check matrix H of an LDPC code provided by an embodiment of the present application.
  • the Tanner diagram represents the check matrix of the LDPC code.
  • the Tanner graph contains two types of nodes, namely n variable nodes (also called information nodes or bit nodes) and m check nodes, m, n are all integers greater than 0.
  • n variable nodes also called information nodes or bit nodes
  • m check nodes are all integers greater than 0.
  • the above-mentioned n variable nodes respectively correspond to n columns of the check matrix H
  • the above-mentioned m check nodes respectively correspond to m rows of the check matrix H.
  • the cycle in the Tanner graph is composed of vertices connected to each other.
  • the cycle uses a vertex in this group of vertices as both the starting point and the end point, and only passes through each node once.
  • the length of a loop is defined as the number of connections it contains, and the girth of the graph can also be called the size of the graph, which is defined as the smallest loop length in the graph, as in Figure 2, and the girth is 6, as in Figure 2 Shown in black.
  • FIG. 3 is an example of the encoding process of an LDPC code provided by this application.
  • I represents the information bit part
  • P represents the parity bit part
  • x is the transmission codeword
  • the decoding algorithms of LDPC codes include the following three categories: hard-decision decoding, soft-decision decoding and hybrid decoding.
  • Some WLAN standards use orthogonal frequency division multiplexing (OFDM) technology.
  • the LDPC encoding module needs to encode the data bits (which can be called information bits) into an integer number of OFDM symbols, and these encoded bits must fit into an integer number of LDPC codewords.
  • the sending end calculates the LDPC code length used in the current transmission and the required number of codewords. For most combinations of bit lengths and coding modulation schemes of the data to be encoded, there are not enough data bits to fill the data bit portion of the LDPC codeword. Shortening operation is performed before parity bits are formed. The data bits in the LDPC codeword only contain information bits (or data bits) and do not contain parity bits (or parity bits).
  • the shortening operation refers to filling in a certain number of 0s in the data bits of the codeword information before generating the check bits through LDPC encoding, and then deleting these 0s after encoding the check bits.
  • Figure 4 is a schematic diagram of the shortening operation part in an LDPC encoding process provided by an embodiment of the present application.
  • 401 represents the data bits to be encoded (payload bits); step 1 is to calculate the length and number of codewords required to send the data bits to be encoded, and 402 shows the LDPC code The length of the word and the number of codewords; Step 2 is to shorten the data bits to be encoded, 403 shows a codeword containing data bits and shortening zero bits (shortening zero bits); Step 3 is to utilize the data bits and shorten the 0 bits , generate parity bits, 404 shows a codeword containing data bits, shortened 0 bits and parity bits; these shortening 0 bits are then deleted (discard shortening bits), 405 shows a codeword containing only data bits and the codeword of the check bits.
  • the base matrix of the LDPC code can be expanded to the check matrix of the LDPC code of various code lengths as needed.
  • the basis matrix of the LDPC code only contains two elements: 0 and 1.
  • 0 in the base matrix can be replaced by a blank, "-", "-1", or other numbers or symbols, which is not limited by this application.
  • the 1's in the base matrix can be expanded to a non-all-zero square matrix (also called a non-all-zero square matrix), and the 0 elements in the base matrix can be expanded to all-zero.
  • Square matrix also called all-0 square matrix).
  • an all-zero square matrix refers to a square matrix in which each element is 0, such as a square matrix with a size of (27 ⁇ 27).
  • a non-all-zero square matrix refers to a square matrix including at least one non-zero element, such as a circulant permutation matrix (CPM).
  • CPM is the cyclic shift of the unit matrix. In other words, the cyclic shift of the unit matrix is called CPM. This is the meaning of subsequent CPM, and will not be described in detail later.
  • any CPM can be represented by a numerical value and an expansion factor. In other words, any CPM corresponds to a value and an expansion factor.
  • the different sizes of the two CPMs mean that the corresponding expansion factors of the two CPMs are different.
  • the value corresponding to the CPM may be called a specific value of the expansion factor, an expansion factor value, a cyclic shift factor, etc.
  • the value corresponding to CPM can be called a cyclic shift coefficient.
  • the expansion factor corresponding to the CPM represents the size of the CPM, that is, CPMs of different sizes have different expansion factors.
  • a CPM of size (27 ⁇ 27) has a spreading factor of 27.
  • the expansion factor of a certain CPM is 27, which means the size of the CPM is (27 ⁇ 27).
  • the expansion factor of a CPM of size (54 ⁇ 54) is 54.
  • the expansion factors of each CPM in the check matrix are the same.
  • the size of a base matrix is (12 ⁇ 24).
  • the expansion factor of each CPM in the check matrix is Z.
  • the numerical value (integer) corresponding to CPM represents the number of bits that the unit matrix is cyclically shifted to the right.
  • Figure 5 is an example of four types of CPM (4 ⁇ 4) provided by this application. As shown in Figure 5, P 0 represents a (4 ⁇ 4) unit matrix. P 0 can be regarded as a CPM with an expansion factor of 4 and a corresponding value of 0.
  • P 1 is a CPM with an expansion factor of 4 and a corresponding value of 1.
  • P 2 is a CPM with an expansion factor of 4 and a corresponding value of 2
  • P 3 is a CPM with an expansion factor of 4 and a corresponding value of 3.
  • Figure 5 is an example of four types of CPM provided by the embodiment of this application. It should be understood that any CPM can be obtained by cyclically shifting the corresponding unit matrix to the right, which will not be described in detail here. It should be understood that 1 in the base matrix can be expanded to a CPM of any size, and 0 in the base matrix can be expanded to an all-zero square matrix of any size. The meaning or function of 1 or 0 in the base matrix below is consistent with the previous introduction and will not be described again.
  • the check matrix can be obtained by extending the base matrix as follows: replace 1 in the base matrix with CPM, and replace 0 with an all-0 square matrix of corresponding size. For example, each element in the base matrix is 0 or 1.
  • each 0 in the base matrix is expanded into an all-zero matrix of (Z ⁇ Z).
  • the base Each 1 in the matrix is expanded to a CPM of (Z ⁇ Z), and Z is the expansion factor corresponding to the CPM.
  • the values corresponding to different CPMs are the same or different. Therefore, a series of check matrices of LDPC codes can be obtained from the basis matrix. The size of these check matrices and the expansion factor of each CPM can be different, But correspond to or conform to the same basis matrix.
  • Figure 6 is an example of a check matrix obtained by extending a base matrix (hereinafter base matrix 1) of size (12 ⁇ 24) provided by an embodiment of the present application.
  • the "-" in the check matrix represents an all-zero matrix of size (K ⁇ K)
  • the 0 in the check matrix represents an identity matrix (or unit matrix) of size (K ⁇ K).
  • matrix) the elements greater than 0 in the check matrix represent the CPM corresponding to the value of the element of size (K ⁇ K)
  • K represents the expansion factor.
  • the identity matrix of size (K ⁇ K) Circularly shift the values of elements greater than 0 in the check matrix.
  • LDPC codes have been widely used in WLAN standards.
  • the new IEEE 802.15ab standard can introduce new LDPC coding technology to greatly improve the data transmission reliability of the system. Therefore, it is possible to consider designing new LDPC codes for the next generation WLAN standard or UWB standard to further improve the reliability and system performance of the next generation WLAN system or UWB system.
  • this application proposes two types of designs for the next generation WLAN system or UWB system that use a single base matrix to expand to obtain check matrices with different code lengths.
  • the solution provided by this application is to use a single base matrix to expand to obtain check matrices of different code lengths. It is suitable for transmission scenarios where medium packets, short packets and long packets exist, and the coding complexity is low.
  • the first type of scheme is to use the base matrix corresponding to the existing check matrix to expand to obtain check matrices of different code lengths.
  • check matrices with different code lengths are obtained by expanding.
  • the second type of solution is to comprehensively consider multiple factors such as the performance of the LDPC code, decoding convergence speed, decoding complexity, etc., and design several groups of base matrices and corresponding corrections of the LDPC code with low complexity and fast decoding convergence. test matrix.
  • the technical solution of this application is mainly applicable to wireless communication systems.
  • the wireless communication system can comply with the wireless communication standards of the third generation partnership project (3GPP) or other wireless communication standards.
  • 3GPP third generation partnership project
  • IEEE Institute of Electrical and Electronics Engineers
  • the technical solution of this application can also be applied to wireless local area network systems such as Internet of Things (IoT) networks, UWB systems, and Vehicle to X (V2X).
  • IoT Internet of Things
  • UWB systems UWB systems
  • V2X Vehicle to X
  • LTE long term evolution
  • FDD frequency division duplex
  • FDD time division duplex
  • UMTS duplex
  • WiMAX global interoperability for microwave access
  • the embodiments of this application are mainly explained by taking the deployment of a WLAN system or a UWB system, especially a network applying the IEEE 802.11 standard, as an example. It is easy for those skilled in the art to understand that various aspects involved in this application can be extended to other networks using various standards or protocols, such as BLUETOOTH (Bluetooth), high performance wireless LAN (HIPERLAN) (a kind of communication with IEEE A wireless standard similar to the 802.11 standard, mainly used in Europe), as well as a wide area network (WAN), a personal area network (PAN), or other networks now known or later developed. Therefore, the various aspects provided herein may be applicable to any suitable wireless network, regardless of the coverage and wireless access protocols used.
  • BLUETOOTH Bluetooth
  • HIPERLAN high performance wireless LAN
  • WAN wide area network
  • PAN personal area network
  • FIG 7 is an example of a wireless communication system to which the technical solution provided by this application is applicable.
  • the communication system includes an access point (AP) and one or more STAs (only STA1 and STA2 are shown).
  • both the access point and the STA support WLAN protocols, which can include IEEE 802.11be (or Wi-Fi 7, EHT protocol), and can also include IEEE 802.15ab, IEEE802.11ax, IEEE 802.11ac and other protocols.
  • the WLAN protocol can also include the next generation protocol of IEEE802.11be and so on.
  • the device that implements the method of the present application may be an access point or STA in the WLAN, or a chip or processing system installed in the access point or STA.
  • An access point is a device with wireless communication capabilities that supports communication using the WLAN protocol and has the function of communicating with other devices in the WLAN network (such as sites or other access points). Of course, it can also have the function of communicating with other devices.
  • a WLAN system it includes one or more access point (AP)-type stations and one or more non-access point-type stations (none access point station, non-AP STA).
  • AP access point
  • non-AP STA non-access point-type stations
  • this article calls the access point type site an access point (AP), and the non-access point type site is called a station (STA).
  • the access point can be a complete device, or a chip or processing system installed in the complete device. Devices equipped with these chips or processing systems can implement the methods and functions of the embodiments of the present application under the control of the chips or processing systems (ie, AP).
  • the AP in the embodiment of this application is a device that provides services for a station (Station, STA), and can support 802.11 series protocols, such as 802.15ab, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, 802.11be, Wi- Fi8 or its next generation etc.
  • the AP can be a communication entity such as a communication server, router, switch, and bridge.
  • APs can include macro base stations, micro base stations (also called small stations), pico base stations, femto base stations, relay stations, access points, gNBs, transmission reception points (TRP), evolved Node Bs (evolved Node B , eNB), radio network controller (radio network controller, RNC), home base station (for example, home evolved NodeB, or home Node B, HNB), base band unit (base band unit, BBU), WiFi access point (access point , AP), integrated access and backhaul (IAB), etc.
  • the AP can also be chips and processing systems in these various forms of devices, thereby implementing the methods and functions of the embodiments of the present application.
  • a site is a device with wireless communication function that supports communication using WLAN protocol and has the ability to communicate with WLAN The ability to communicate with other stations or access points on the network.
  • STA is any communication device that allows the user to communicate with the AP and then with the WLAN.
  • the communication device can be a complete device, or it can be a chip or processing system installed in the complete device. Equipment equipped with these chips or processing systems can implement the methods and functions of the embodiments of the present application under the control of the chips or processing systems (ie, sites).
  • STA can include mobile phones (mobile phones), mobile stations (MS), tablets (pads), computers with wireless transceiver functions (such as laptops), virtual reality (VR) devices, augmented reality (Augmented) reality, AR) equipment, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, and wireless terminals in smart grid , wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, subscriber units, cellular phones, wireless data Cards, personal digital assistant (PDA) computers, tablet computers, laptop computers, machine type communication (MTC) terminals, etc.
  • Stations may include a variety of handheld devices, vehicle-mounted devices, wearable devices, computing devices, or other processing devices connected to wireless modems with wireless communications capabilities.
  • the station can be a handheld device (handset) with wireless communication function, a vehicle-mounted device, a wearable device or a terminal in the Internet of Things, the Internet of Vehicles, 5G and any form of terminal in the communication system evolved after 5G, etc.
  • the site can support 802.11 series protocols, such as 802.15ab, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, 802.11be, Wi-Fi 8 or its next generation and other WLAN standards.
  • Figure 8 is an interactive flow chart of an LDPC code encoding method provided by this application. As shown in Figure 8, the method includes:
  • the sending end performs LDPC encoding on the first bit sequence according to the check matrix to obtain the first data packet.
  • the sending end can be a station or an access point.
  • the sending end in the embodiment of this application can be regarded as an encoding device.
  • the above check matrix includes two or more check matrices that conform to the first basis matrix.
  • the code lengths of any two check matrices among the two or more check matrices included in the above check matrix that conform to the first basis matrix are different.
  • the following description takes the check matrix including the first check matrix and the second check matrix as an example.
  • the above-mentioned first check matrix and the above-mentioned second check matrix both conform to the first basis matrix.
  • the code length of the above-mentioned first check matrix and the code length of the above-mentioned second check matrix are different.
  • step 801 is as follows: obtain the first information according to the generator matrix corresponding to the first bit sequence and the first check matrix; obtain the first data packet based on the first information.
  • Another possible implementation of step 801 is as follows: obtain the first information according to the generator matrix corresponding to the first bit sequence and the second check matrix; obtain the first data packet based on the first information.
  • the transmitting end can use any check matrix among multiple check matrices conforming to the same base matrix to perform LDPC encoding on the bit sequence to be encoded according to needs or preset rules. For the specific process, please refer to the encoding of the LDPC code described above and the LDPC encoding in WLAN.
  • This application does not limit the specific manner of LDPC encoding the first bit sequence according to a check matrix (such as a first check matrix or a second check matrix). Since it is a common technical method in this field to obtain the corresponding data packet based on the encoded information, such as the first information, it will not be described in detail here.
  • a check matrix such as a first check matrix or a second check matrix
  • the sending end sends the first data packet.
  • the above sending steps may include but are not limited to: the sending end performs stream analysis (strean parser), constellation mapping (Constellation mapper), LDPC carrier mapping, or may include Inverse discrete fourier transform (IDFT) and other processing are performed in order to send it out on the channel.
  • stream analysis strean parser
  • constellation mapping Constellation mapper
  • LDPC carrier mapping or may include Inverse discrete fourier transform (IDFT) and other processing are performed in order to send it out on the channel.
  • IDFT Inverse discrete fourier transform
  • the receiving end receives a signal from the transmitting end carrying the aforementioned encoded first bit sequence (for convenience of description, it may also be called a first data packet).
  • the sending end is a station and the receiving end is an access point.
  • the sending end is the access point and the receiving end is the station.
  • step 802 is as follows: the sending end broadcasts the first data packet.
  • the receiving end receives a first channel reception sequence (corresponding to the first data packet) from the transmitting end.
  • the first channel reception sequence corresponds to the first signal received by the receiving end through the first channel, that is, the first data packet sent by the sending end is transmitted through the channel and received by the receiving end.
  • step 802 is as follows: the sending end sends the first data packet to the receiving end (corresponding to the unicast mode). The receiving end receives a first channel reception sequence (corresponding to the first data packet) from the transmitting end.
  • the receiving end determines the first log likelihood ratio (LLR) sequence corresponding to the first channel received sequence, and decodes the first LLR sequence according to the check matrix to obtain the first decoding result.
  • LLR log likelihood ratio
  • the receiving end decodes the first LLR sequence according to the first check matrix; if the sending end performs LDPC encoding on the first bit sequence according to the second check matrix
  • the receiving end decodes the first LLR sequence according to the second check matrix.
  • the receiving end can learn the check matrix used to decode the first LLR sequence according to the control information from the transmitting end.
  • the receiving end can also learn the check matrix used to decode the first LLR sequence through other methods, which is not limited in this application.
  • the receiving end may use any one of hard-decision decoding, soft-decision decoding, and hybrid decoding to decode the first LLR sequence according to the first check matrix, which is not limited here.
  • the receiving end outputs the first decoding result.
  • Step 804 is optional but not required.
  • the receiving end can output the first decoding result through an output device, such as a monitor, a display screen, an audio device, etc.
  • the receiving end sends retransmission indication information to the sending end to request the sending end to retransmit.
  • the receiving end can save the first LLR sequence to combine it with the subsequently received retransmitted LLR sequence for decoding.
  • both the first check matrix and the second check matrix conform to the first basis matrix.
  • the first check matrix and the second check matrix are obtained by extending the first basis matrix, which can reduce the coding complexity.
  • Figure 9 is an interactive flow chart of another LDPC code encoding method provided by this application. As shown in Figure 9, the method includes:
  • the sending end performs LDPC encoding on the first bit sequence according to the first check matrix to obtain the first data packet.
  • step 901 please refer to step 801.
  • the sending end performs LDPC encoding on the second bit sequence according to the second check matrix to obtain the second data packet.
  • step 902 please refer to step 801.
  • the order of step 901 and step 902 is not limited.
  • the code length of the first check matrix and the code length of the second check matrix are different.
  • the above-mentioned first check matrix and the above-mentioned second check matrix both conform to the first basis matrix.
  • the above-mentioned first check matrix and the above-mentioned second check matrix are both expanded according to the base matrix or the sub-matrix of the above-mentioned base matrix.
  • the main principle of this application is to obtain check matrices of different code lengths based on the expansion of the same base matrix, so as to reduce the complexity of coding.
  • the code rates of the first check matrix and the second check matrix are not limited.
  • the check matrix of the LDPC code can be shortened or punched to obtain other code rates. Please refer to Figure 4 for the shortening operation.
  • the type of the above-mentioned first data packet and the type of the above-mentioned second data packet may be different.
  • the type of the first data packet and the type of the second data packet may be any two of short packet, medium packet, and long packet.
  • the type of the first data packet is long packet
  • the type of the second data packet is short packet.
  • the type of the first data packet is a medium packet
  • the type of the second data packet is a long packet. It should be understood that the length of the short bag is smaller than that of the medium bag, and the length of the medium bag is smaller than that of the long bag.
  • the length of the above-mentioned first bit sequence is different from the length of the above-mentioned second bit sequence.
  • the above-mentioned first bit sequence and the above-mentioned second bit sequence need to use check matrices with different code lengths for LDPC encoding.
  • the above-mentioned first bit sequence and the above-mentioned second bit sequence need to be sent through different types of data packets.
  • the first bit sequence includes 20 bits and the second bit sequence includes 1500 bits.
  • the transmitter performs LDPC encoding on the first bit sequence according to the first check matrix with a code length of 648 bits to obtain the first bit sequence.
  • the sending end performs LDPC encoding on the second bit sequence according to the second check matrix with a code length of 1944 bits to obtain the second data Packets; the first data packet is a short packet, and the second data packet is a long packet. From this example, it can be seen that when the sending end sends different types of data packets, it needs to perform LDPC encoding on the bit sequences to be encoded based on check matrices of different code lengths.
  • the above-mentioned first check matrix and the above-mentioned second check matrix are obtained by extending the above-mentioned first basis matrix through the same hardware circuit, and the above-mentioned first check matrix and the above-mentioned second check matrix correspond to different extension method or extension parameters. That is to say, the transmitting end can expand the first base matrix through the same hardware circuit to obtain check matrices of two or more code lengths. In other words, by changing or adjusting the expansion method or expansion parameters used by a certain hardware circuit, the transmitting end can obtain two or more check matrices with two or more code lengths based on the first base matrix expansion.
  • the first hardware circuit in the transmitting end is used to expand based on the first base matrix to obtain multiple check matrices; when the first hardware circuit adopts the first expansion method (or first expansion parameter), according to the first A base matrix is expanded to obtain a first check matrix; when the first hardware circuit adopts a second expansion method (or second expansion parameter), a second check matrix is obtained by expansion based on the first base matrix.
  • the transmitting end can expand the first base matrix through the same hardware circuit to obtain two or more check matrices with code lengths, and the coding complexity is low.
  • the sending end sends the first data packet and the second data packet.
  • the sending end sends the first data packet and the second data packet independently, that is, sends the first data packet and the second data packet through different signals or channels. Or, the sending end sends the first data packet and the second data packet successively.
  • the receiving end receives a signal from the transmitting end carrying the aforementioned encoded first bit sequence (for convenience of description, it can also be called a first data packet), and a signal carrying the aforementioned encoded second bit sequence (for description convenience). Conveniently, it can also be called the second data packet).
  • the sending end is a station and the receiving end is an access point.
  • the sending end is the access point and the receiving end is the station.
  • step 903 is as follows: the sending end broadcasts the first data packet and the second data packet.
  • the receiving end receives a first channel receiving sequence (corresponding to the first data packet) and a second channel receiving sequence (corresponding to the second data packet) from the transmitting end.
  • the first channel reception sequence corresponds to the first signal received by the receiving end through the first channel, that is, the first data packet sent by the sending end is transmitted through the channel and received by the receiving end.
  • the second channel reception sequence corresponds to the second signal received by the receiving end through the second channel, that is, the second data packet sent by the sending end is transmitted through the channel and received by the receiving end.
  • step 903 is as follows: the sending end sends the first data packet and the second data packet to the receiving end (corresponding to the unicast mode).
  • the receiving end receives a first channel receiving sequence (corresponding to the first data packet) and a second channel receiving sequence (corresponding to the second data packet) from the transmitting end.
  • the receiving end determines the first LLR sequence corresponding to the first channel received sequence, and decodes the first LLR sequence according to the first check matrix to obtain the first decoding result.
  • the receiving end will output the first decoding result.
  • Step 905 is optional but not required.
  • step 905 please refer to step 804.
  • the receiving end determines the second LLR sequence corresponding to the second channel received sequence, and decodes the second LLR sequence according to the second check matrix to obtain the second decoding result.
  • the receiving end outputs the second decoding result.
  • Step 907 is optional but not required.
  • step 907 please refer to step 804.
  • both the first check matrix and the second check matrix conform to the first basis matrix.
  • the transmitting end can reduce the coding complexity by using check matrices with different code lengths that conform to the first base matrix to perform LDPC encoding.
  • Figure 10 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • the method interaction flow in Figure 10 is a possible implementation of the method described in Figure 9 .
  • the sending end obtains a check matrix of the required code length based on the first base matrix expansion based on the length of the bit sequence to be encoded, which is suitable for sending data packets of different lengths and reduces the complexity of encoding.
  • the transmitting end obtains the first check matrix according to the first base matrix expansion.
  • the first interval may be an interval configured as needed, which is not limited in this application.
  • the first interval may be less than or equal to 40 bytes.
  • the transmitting end needs to use the first check matrix of the first code length to perform LDPC encoding on the bit sequence.
  • the first code length may be 320 bits, 640 bits, 648 bits, etc.
  • the length of the first bit sequence to be encoded is located in the first interval, which can be understood as a condition that needs to be met to obtain the first check matrix based on the expansion of the first base matrix.
  • the length of the first bit sequence to be encoded is located in the first interval, which is a condition that triggers the transmitting end to obtain the first check matrix according to the first base matrix expansion.
  • the sending end can also obtain the first check matrix by extending the first base matrix when other conditions are met. For example, when the transmitting end determines that a check matrix of the first code length needs to be used for encoding, it expands the first base matrix to obtain a first check matrix with a code length of the first code length.
  • the sending end performs LDPC encoding on the first bit sequence according to the first check matrix to obtain the first data packet.
  • the sending end sends the first data packet.
  • the receiving end receives the first channel reception sequence (corresponding to the first data packet) from the sending end.
  • the first channel reception sequence corresponding to the first data packet
  • the sending end receives the first channel reception sequence (corresponding to the first data packet) from the sending end.
  • step 1003 please refer to step 802.
  • the receiving end determines the first LLR sequence corresponding to the first channel received sequence, and decodes the first LLR sequence according to the first check matrix to obtain the first decoding result.
  • the receiving end outputs the first decoding result.
  • Step 1005 is optional but not required.
  • the transmitting end expands the first base matrix to obtain the second check matrix.
  • the sending end needs to use the second check matrix of the second code length to perform LDPC encoding on the bit sequence.
  • the second code length may be 1280 bits, 1296 bits, 1944 bits, 2560 bits, etc., which is not limited in this application.
  • the second interval does not overlap with the first interval.
  • the intersection of the first interval and the second interval is the empty set.
  • Both the first interval and the second interval are continuous intervals.
  • the first interval is (0, first value]
  • the second interval is (second value, third value]
  • the second value is greater than the first value
  • the third value is greater than the second value
  • the first value is greater than 0.
  • the first interval is (0, first value]
  • the second interval is (first value, third value]
  • the second value is greater than the first value
  • the first value is greater than 0.
  • the second interval can be greater than 40 bybes . It should be understood that the sending end can set the first interval and the second interval accordingly according to actual needs, which is not limited in this application.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the expansion factor of the CPM in the first check matrix is Z1
  • the specific value of the second check matrix is Z1.
  • the specific value of the expansion factor of the CPM at the first position in the matrix is (b mod Z)
  • the expansion factor of the CPM in the second check matrix is Z2
  • the above Z, the above Z1, and the above Z2 are all integers greater than 0,
  • the above-mentioned Z1 is greater than or equal to the above-mentioned Z
  • the above-mentioned Z2 is smaller than the above-mentioned Z.
  • the first position can be any position in the first check matrix.
  • Elements at the same position in the first check matrix and the second check matrix correspond one to one. That is to say, if the specific value of the expansion factor of the CPM at any position in the first check matrix is b, then the specific value of the expansion factor of the CPM at the corresponding position in the second check matrix is (b mod Z).
  • mod means modulo operation or remainder operation.
  • Z is an integral multiple of 27, such as 27, 54, 81, etc.
  • the above-mentioned first basis matrix corresponds to the original check matrix
  • the expansion factor of the CPM in the above-mentioned original check matrix is Z
  • the specific value of the expansion factor of the CPM at the first position of the above-mentioned original check matrix is b
  • the above-mentioned The specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the expansion factor of the CPM in the first check matrix is Z1
  • the expansion factor of the CPM at the first position in the second check matrix is The specific value of the factor is (b mod Z).
  • the expansion factor of the CPM in the above-mentioned second check matrix is Z2.
  • the above-mentioned Z, the above-mentioned Z1 and Z2 are both integers greater than 0, Z1 is greater than or equal to Z, and Z2 is less than Z.
  • Z is an integral multiple of 27, such as 27, 54, 81, etc.
  • the above check matrix also includes the above original check matrix.
  • the original check matrix corresponding to the base matrix can be the matrix shown in Figure 6, or it can be a WLAN LDPC check matrix with a code rate of 1/2, a code length of 1296, and an expansion factor of 54, or it can be a code rate of 1 /2.
  • the WLAN LDPC check matrix with a code length of 1944 and an expansion factor of 81 can also be other check matrices, which are not limited in this application.
  • the specific value of the expansion factor of the cyclic displacement matrix CPM at the first position in the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b mod Z); can quickly expand to obtain the required check matrix.
  • the specific value of the expansion factor of the CPM at the first position in the first check matrix is b
  • the expansion factor of the CPM in the first check matrix is Z3
  • the specific value of the second check matrix is Z3.
  • the specific value of the expansion factor of the CPM at the first position in the matrix is any one of b, (b+Z), and (b+2Z).
  • the expansion factor of the CPM in the above-mentioned second check matrix is Z4.
  • the above-mentioned Z, The above Z3 and the above Z4 are both integers greater than 0, the above Z3 is smaller than the above Z, and the above Z4 is greater than or equal to the above Z. It should be noted that it is necessary to ensure that each element in the second check matrix is less than or equal to Z4.
  • the first position can be any position in the first check matrix.
  • Z and Z4 are both integral multiples of 27, for example, Z is 27, Z4 is 54, 81, etc. Elements at the same position in the first check matrix and the second check matrix correspond one to one. It can be understood that if the specific value of the expansion factor of the CPM at any position in the first check matrix is b, then the specific value of the expansion factor of the CPM at the corresponding position in the second check matrix is b, (b+Z), ( Any one of b+2Z). It should be noted that the specific value of the expansion factor of each position in the second check matrix is any one of b, (b+Z), and (b+2Z).
  • the specific value of the expansion factor of the CPM at the first position of the first check matrix is b
  • the specific value of the expansion factor of the CPM at the first position in the second check matrix is (b+Z)
  • the first check matrix The specific value of the expansion factor of the CPM at the third position is a
  • the specific value of the expansion factor of the CPM at the third position in the second check matrix is (a+2Z).
  • the required check matrix can be quickly expanded.
  • the above-mentioned first basis matrix corresponds to the original check matrix
  • the expansion factor of the CPM in the above-mentioned original check matrix is Z
  • the expansion factor of the CPM at the first position of the above-mentioned original check matrix is specific
  • the value is b
  • the specific value of the expansion factor of the CPM at the first position in the above-mentioned first check matrix is (b mod Z)
  • the expansion factor of the CPM in the above-mentioned first check matrix is Z3
  • the specific value of the expansion factor of the CPM at the first position in is any one of b, (b+Z), (b+2Z)
  • the expansion factor of the CPM in the above-mentioned second check matrix is Z4
  • the above-mentioned Z, the above-mentioned Z3 and the above-mentioned Z4 are both integers greater than 0, the above-mentioned Z3 is smaller than the above-mentione
  • each element in the first check matrix is less than or equal to Z4.
  • Z and Z4 are both integral multiples of 27, for example, Z is 27, Z4 is 54, 81, etc.
  • the required check matrix can be quickly expanded.
  • the sending end performs LDPC encoding on the second bit sequence according to the second check matrix to obtain the second data packet.
  • the sending end sends the second data packet.
  • the receiving end receives the second channel reception sequence (corresponding to the second data packet) from the sending end.
  • the second channel reception sequence corresponding to the second data packet
  • the receiving end determines the second LLR sequence corresponding to the second channel received sequence, and decodes the second LLR sequence according to the second check matrix to obtain the second decoding result.
  • the receiving end If the decoding is successful, the receiving end outputs the second decoding result.
  • Step 1010 is optional but not required.
  • step 1010 please refer to step 804.
  • the sender does not necessarily generate a check matrix with corresponding code length in all intervals.
  • the above-mentioned first interval and second interval are only examples. It should be understood that as long as the transmitting end generates a check matrix of corresponding code length according to the length of the bit sequence, it falls within the protection scope of this application. This application is not limited to generating a check matrix of corresponding code length in all intervals.
  • the method flow of Figure 10 describes the situation where the sending end, when the length of the first bit sequence to be encoded is located in the first interval,
  • the first check matrix is obtained by extending the first base matrix
  • the second check matrix is obtained by extending the first base matrix.
  • Figure 10 is only an example of obtaining two check matrices (i.e., the first check matrix and the second check matrix) according to the expansion of the first base matrix.
  • the transmitting end can obtain three or three check matrices according to the expansion of the first base matrix. There are more than three types of check matrices, and each check matrix can correspond to an interval.
  • the transmitting end obtains the first check matrix according to the first base matrix expansion
  • the second check matrix is obtained according to the first base matrix expansion
  • the transmitting end obtains the third check matrix according to the first base matrix expansion; wherein, the Any two of the first check matrix, the second check matrix, and the third check matrix have different code lengths, and any two of the first interval, the second interval, and the third interval do not overlap.
  • the first interval is (0, first value]
  • the second interval is (second value, third value]
  • the third interval is (third value, fourth value]
  • the code length of the first check matrix is 648 bits
  • the code length of the second check matrix is 1296 bits
  • the code length of the third check matrix is 1944 bits.
  • the first value is greater than 0, the second value is greater than the first value
  • the third value is greater than the second value.
  • the fourth value is greater than the third value.
  • the first interval, the second interval and the third interval can be set according to actual needs, and this application does not limit it.
  • Figure 6 is reused, and Figure 6 shows a first calibration An example of the parity check matrix. Refer to Figure 6.
  • 0 represents (27 ⁇ 27)
  • the unit matrix of the elements greater than 0 represent the CPM of (27 ⁇ 27), and "-" represents the all-zero matrix of (27 ⁇ 27).
  • 22 represents the CPM of (27 ⁇ 27) with a specific expansion factor value of 22.
  • the transmitting end obtains the first check matrix according to the first base matrix expansion; when the length of the bit sequence to be encoded is located in the second interval, the transmitting end In the case of When the length of the bit sequence to be encoded is in the fourth interval, a fourth check matrix is obtained according to the first base matrix expansion; wherein, the first check matrix, the second check matrix, the third check matrix, the fourth check matrix Any two code lengths in the check matrix are different, and any two of the first interval, the second interval, the third interval, and the fourth interval do not overlap.
  • the first interval is (0, first value], the second interval is (second value, third value], the third interval is (third value, fourth value], and the fourth interval is (fourth value , the fifth value],
  • the code length of the first check matrix is 320 bits
  • the code length of the second check matrix is 640 bits
  • the code length of the third check matrix is 1280 bits
  • the code length of the fourth check matrix is is 2560 bits.
  • the first value is greater than 0, the second value is greater than the first value, the third value is greater than the second value, the fourth value is greater than the third value, and the fifth value is greater than the fourth value. In practical applications, it can be based on actual It is necessary to set the first interval, the second interval, the third interval and the fourth interval, which is not limited in this application.
  • FIG. 11 is an example of a matrix representing a first basis matrix and a specific value matrix of expansion factors of four check matrices obtained by extending the first basis matrix according to an embodiment of the present application.
  • the matrix characterizing the first basis matrix can be regarded as the first basis matrix.
  • the reason why the first basis matrix is not written directly is that the first basis matrix is a (16 ⁇ 32) matrix and is difficult to display.
  • this application does not directly show the (16 ⁇ 32) check matrix, but shows the specific value matrix of the expansion factor of the check matrix. Since it is difficult to directly display the (16 ⁇ 32) check matrix, and the expansion factor of the check matrix can represent the check matrix, the specific value matrix of the expansion factor of the check matrix can be regarded as the check matrix.
  • each rectangular box includes a matrix.
  • the five rectangular boxes shown in Figure 11 include, from left to right, the matrix representing the first basis matrix, the specific value matrix of the expansion factor of the fourth check matrix, The specific value matrix of the expansion factor of the third check matrix, the specific value matrix of the expansion factor of the second check matrix, and the specific value matrix of the expansion factor of the first check matrix.
  • the matrix characterizing the first basis matrix can be regarded as the first basis matrix.
  • the first basis matrix is represented by a matrix characterizing the first basis matrix.
  • the first basis matrix only includes two elements: 0 and 1.
  • a matrix characterizing the first basis matrix may show the position of the 1's in each row of the first basis matrix and thus may characterize the first basis matrix.
  • the element of the i-th row of the matrix that represents the first basis matrix is the same as the i-th element of the first basis matrix.
  • the position of element 1 in the row corresponds one-to-one, and the i-th row corresponds to any row.
  • any element in the i-th row of the matrix representing the first basis matrix is u, indicating that the element in the (u+1)-th column of the i-th row of the first basis matrix is 1, and the i-th row is any row, u is an integer from 0 to 31.
  • the elements in the first row of the matrix representing the first basis matrix are: 0, 2, 4, 6, 12, 14, 17, indicating that the 1st and 3rd columns of the first row of the first basis matrix
  • the elements in column, column 5, column 7, column 13, column 15, and column 18 are 1, and the elements in other columns of the first row of the first basis matrix are all 0
  • the elements in the second row of are: 1, 2, 3, 9, 12, 17, 18, indicating that the 2nd, 3rd, 4th, 10th, and 10th columns of the second row of the first basis matrix
  • the elements in columns 13, 18, and 19 are 1, and the elements in other columns of the second row of the first basis matrix are all 0; and so on. It can be seen that the matrix characterizing the first basis matrix can be regarded as the first basis matrix itself.
  • the following uses the first check matrix as an example to explain why the specific value matrix of the expansion factor of the check matrix can be regarded as a check matrix.
  • the element at the second position (any position) of the j-th row of the matrix representing the first basis matrix is p, and the second element of the j-th row of the first specific value matrix (that is, the specific value matrix of the expansion factor of the first check matrix)
  • the element at the position is q
  • the element in the (p+1)th column of the j-th row of the first check matrix is q.
  • the 0 in the first check matrix represents a unit matrix of size (10 ⁇ 10)
  • the elements greater than 0 in the first check matrix represent the specific value of the expansion factor of the CPM of size (10 ⁇ 10).
  • Figure 12 is an example of a first check matrix provided by an embodiment of the present application.
  • FIG. 12 is a check matrix represented by the specific value matrix of the expansion factor of the first check matrix in FIG. 11 .
  • the first check matrix shown in Figure 12 can be obtained.
  • 0, 1, ..., 31 correspond to the first column to the 32nd column of the first check matrix in sequence
  • 0, 1, ..., 15 correspond to the first row to the 32nd column of the first check matrix in sequence.
  • the elements in the second column represent the row weight of the corresponding row
  • the elements in the second row represent the column weight of the corresponding column.
  • the left (16 ⁇ 16) part of the matrix corresponds to the information part
  • the right (16 ⁇ 16) matrix part is the check part.
  • the leftmost rectangular box in Figure 11 includes a matrix representing the first basis matrix (hereinafter may be referred to as matrix 1)
  • the rightmost rectangular box in Figure 11 includes the first specific value matrix, matrix 1 and
  • the size of the first specific value matrix is the same, and the elements at the same position in matrix 1 and the first specific value matrix correspond one to one; from the description in the previous paragraph, it can be seen that the elements in the first row of (16 ⁇ 32) matrix 1 are: 0, 2, 4, 6, 12, 14, 17, indicating that the elements of the first row, column 1, column 3, column 5, column 7, column 13, column 15, and column 18 of matrix 1 are 1, then the element in the first row and first column of matrix 1 is 0, indicating that there is a value in the first row and first column of the first specific value matrix.
  • the element in the first specific value matrix is 5
  • the element in the first row and first column of the value matrix is 5
  • the element in the first row and first column of the first check matrix is 5
  • the position of the first row and first column of the first check matrix is The CPM of size (10 ⁇ 10) is circularly shifted by 5; the elements in the first row and second column of matrix 1 are 2, indicating that there are values in the first row and second column of the first specific value matrix, see again the first specific value matrix The element in is 5.
  • the element in the first row and second column of the first specific value matrix is 5, which means that the element in the first row and third column of the first check matrix is 5, that is, the first check matrix
  • the position of the first row and third column is the CPM circular shift of size (10 ⁇ 10) by 5; the element of the first row and third column of matrix 1 is 4, indicating that the first row and third column of the first specific value matrix has a value. See again that the element in the first specific value matrix is 4. It can be seen that the first row and third column of the first specific value matrix are 4, which means that the element in the first row and fifth column of the first check matrix is 4. ;And so on.
  • the specific value matrix of the expansion factor of any check matrix combined with the basis matrix that the check matrix conforms to can characterize the check matrix. It can be seen that the first specific value matrix can be regarded as the first check matrix itself. In the same way, the specific value matrix of the expansion factor of any check matrix can be regarded as the check matrix.
  • FIG. 13 is an example of another matrix characterizing the first basis matrix and specific value matrices of expansion factors of four check matrices obtained by extending the first basis matrix according to the embodiment of the present application.
  • each rectangular box includes a matrix
  • the five rectangular boxes shown in Figure 13 include, in order from left to right, the matrix representing the first basis matrix, the specific value matrix of the expansion factor of the fourth check matrix, the specific value matrix of the expansion factor of the third check matrix, The specific value matrix of the expansion factor of the second check matrix, and the specific value matrix of the expansion factor of the first check matrix.
  • the matrix characterizing the first basis matrix can be regarded as the first basis matrix.
  • the specific value matrix of the expansion factor of the fourth check matrix combined with the matrix representing the first basis matrix can represent the fourth check matrix.
  • the specific value matrix of the expansion factor of the third check matrix combined with the matrix representing the first basis matrix can represent the third check matrix.
  • the specific value matrix of the expansion factor of the second check matrix combined with the matrix representing the first basis matrix can represent the second check matrix.
  • the specific value matrix of the expansion factor of the first check matrix combined with the matrix representing the first basis matrix may represent the first check matrix.
  • the sending end obtains a check matrix of the required code length based on the first base matrix expansion based on the length of the bit sequence to be encoded, which is suitable for sending data packets of different lengths and reduces the complexity of coding.
  • the LDPC encoding method provided by this application has been described in detail above. The following focuses on the basis matrices provided in this application, as well as some examples of check matrices extended by these basis matrices.
  • the base matrix provided by this application can be expanded to a check matrix of LDPC codes of various code lengths as needed.
  • the check matrix of the LDPC code of various code lengths can be obtained.
  • multiple check matrices of LDPC codes can be obtained from one base matrix.
  • the size of these check matrices and the expansion factor of each CPM can be different, but they correspond to the same base matrix.
  • the basis matrix obtained by various row and column permutations of the basis matrix provided in this application is equivalent to the basis matrix provided in this application. That is to say, the basis matrix obtained by permuting the rows and columns of the basis matrix provided by this application also belongs to the basis matrix protected by this application.
  • Various row and column permutations of the base matrix refer to the replacement of one or more elements in the base matrix with other elements. That is, one or more elements in a base matrix are equivalent to the base matrix when replaced with other elements. In other words, replacing one or more elements in the base matrix with other elements can also be regarded as the base matrix.
  • the row-column permutation of the base matrix may include any of the following: one or more elements in a row of the base matrix are replaced with other elements, one or more elements in a column of the base matrix are replaced with other elements, the base matrix Multiple elements located in different rows in the base matrix are replaced with other elements, multiple elements located in different columns in the base matrix are replaced with other elements, the positions of multiple rows in the base matrix are changed, and the positions of multiple columns in the base matrix are changed, For example, the positions of two columns in the basis matrix are interchanged.
  • Replacement of an element by another element means that the element is replaced by any element that is different from that element.
  • one or more elements 0 in the basis matrix are replaced with elements 1.
  • one or more elements 1 in the basis matrix are replaced with elements.
  • This application provides two types of designs that use a single base matrix to expand to obtain check matrices of different code lengths.
  • the first type of scheme is to use the base matrix corresponding to the existing check matrix to expand to obtain check matrices of different code lengths. For example, based on the base matrix corresponding to a check matrix with a code rate of 1/2 of the LDPC code in the IEEE 802.11n standard, check matrices with different code lengths are obtained by expanding.
  • the second type of solution is to comprehensively consider multiple factors such as the performance of the LDPC code, decoding convergence speed, decoding complexity, etc., and design several groups of base matrices and corresponding corrections of the LDPC code with low complexity and fast decoding convergence. test matrix.
  • the first type of design provided by this application is to directly start from a base matrix that an existing check matrix conforms to, and expand the base matrix by using different expansion factors Z, thereby obtaining multiple check matrices based on the base matrix.
  • the corresponding base matrix is to replace all non-"-" characters in the check matrix with 1. , replace all "-" in the check matrix with 0, and obtain the corresponding (12 ⁇ 24) matrix.
  • By expanding the base matrix with Z 27, an expanded (324 ⁇ 648) check matrix can be obtained. Each non-zero entry in the base matrix corresponds to a specific value of the expansion factor in the check matrix.
  • Figure 6 shows an example of a check matrix expanded according to the base matrix 1.
  • Figure 14 is an example of a check matrix expanded based on base matrix 2 provided by this application.
  • “-” represents the all-zero matrix of (54 ⁇ 54)
  • 0 represents the identity matrix of (54 ⁇ 54)
  • elements greater than 0 represent the specific value of the expansion factor of the CPM of (54 ⁇ 54).
  • Figure 15 is an example of a check matrix expanded based on base matrix 2 provided by this application.
  • “-” means The all-zero matrix of (81 ⁇ 81), 0 represents the identity matrix of (81 ⁇ 81), and the elements greater than 0 represent the specific value of the expansion factor of the CPM of (81 ⁇ 81).
  • the aforementioned base matrix 1, base matrix 2, and base matrix 3 are base matrices corresponding to three existing check matrices.
  • the first basis matrix can be any basis matrix that matches the existing check matrix, and will not be listed one by one here.
  • Matrix 10 can represent the basis matrix 4 of (12 ⁇ 32). It has been described above that the matrix characterizing the first basis matrix can be regarded as the first basis matrix. In the same way, the matrix 10 representing the basis matrix 4 can be regarded as the basis matrix 4, which will not be described in detail here.
  • the expansion factor specific value matrix 41 represents the check matrix 41 .
  • the expansion factor of any check matrix has been described previously.
  • the value matrix can be considered as this check matrix.
  • the expansion factor specific value matrix 41 can be regarded as the check matrix 41, which will not be described in detail here.
  • the matrix 42 of expansion factor specific values represents the check matrix 42 .
  • the expansion factor specific value matrix 43 represents the check matrix 43 .
  • the matrix 44 of expansion factor specific values represents the check matrix 44 .
  • Matrix 20 representing basis matrix 5:
  • Matrix 20 may represent a (12 ⁇ 32) basis matrix 5. It has been described above that the matrix characterizing the first basis matrix can be regarded as the first basis matrix. In the same way, the matrix 20 representing the basis matrix 5 can be regarded as the basis matrix 5, which will not be described in detail here.
  • the expansion factor specific value matrix 51 represents the check matrix 51 .
  • the matrix 52 of expansion factor specific values represents the check matrix 52 .
  • the expansion factor specific value matrix 53 represents the check matrix 53 .
  • the matrix 51 of expansion factor specific values represents the check matrix 54 .
  • the basis matrix 1 to the basis matrix 5 are only some examples of the first basis matrix provided in this application, but not all examples. It should be understood that the basis matrix obtained by permuting the rows and columns of the basis matrix provided by this application also belongs to the basis matrix protected by this application. Similarly, the check matrix obtained by extending the basis matrix shown above is only a partial example, not all examples. It should be noted that the first basis matrix provided by this application may include H rows or M columns of any of the above-mentioned basis matrices 1 to 3.
  • the above-mentioned H is an integer from 1 to 12, and the above-mentioned M is from 1 to 24. integer in .
  • Line H can be continuous or discontinuous.
  • Column M can be continuous or discontinuous.
  • the first basis matrix provided by this application may include L rows or F columns in the above-mentioned basis matrix 4 or 5.
  • L is an integer from 1 to 12
  • the above-mentioned F is an integer from 1 to 32.
  • Line L can be continuous or discontinuous.
  • Column F can be continuous or discontinuous. That is to say, the first basis matrix may include part of the rows or part of the columns of any of the basis matrices 1 to 5 .
  • the check matrix provided by this application may include the above check matrix 41, check matrix 42, check matrix 43, check matrix 44, check matrix 51, check matrix 52, check matrix 53, check matrix Partial rows or partial columns of any check matrix in matrix 54. This application not only protects the entire basis matrix and check matrix provided, but also protects some rows and columns in the basis matrix, and some rows and columns in the check matrix.
  • the following introduces the possible implementation methods of obtaining check matrices with different code lengths based on the expansion of the same base matrix.
  • the transmitting end expands the first basis matrix to obtain the check matrix 0 (the original check matrix above).
  • the specific value of the expansion factor in 0 is used as the specific value of the expansion factor at the corresponding position in the check matrix 1; if it is necessary to obtain the check matrix 2 with the expansion factor Z2 (less than Z), the specific value of the expansion factor in the check matrix 0
  • the value obtained by the modulo Z operation is used as the specific value of the expansion factor of the corresponding position in the check matrix 2.
  • the check matrix 1 may be the aforementioned first check matrix
  • the check matrix 2 may be the aforementioned second check matrix. Both check matrix 1 and check matrix 2 conform to the first basis matrix. Both check matrix 1 and check matrix 2 can be regarded as check matrices expanded based on the first basis matrix. In this application, elements with the same position in multiple check matrices obtained based on the expansion of the same base matrix correspond one to one. For example, the transmitting end obtains the check matrix 0 based on the first basis matrix expansion, such as the matrix shown in Figure 6.
  • Each element in the check matrix 0 is a (Z ⁇ Z) matrix, and the check matrix 0 is The specific value of the expansion factor in is used as the specific value of the expansion factor at the corresponding position in the check matrix 1; the difference between the check matrix 1 and the check matrix 0 is that each element in the check matrix 1 is one (Z1 ⁇ Z1) matrix, Z1 is greater than Z.
  • the matrix shown in FIG. 6 can represent the check matrix 1 and the check matrix 0.
  • the transmitting end obtains the check matrix 0 based on the expansion of the first basis matrix, such as the matrix shown in Figure 6.
  • Each element in the check matrix 0 is a (Z ⁇ Z) matrix.
  • the specific value of the expansion factor in 0 is taken as the value obtained by the modulo Z operation as the specific value of the expansion factor at the corresponding position in the check matrix 2.
  • the specific value of an expansion factor in the check matrix 0 is b
  • the specific value of the expansion factor in the check matrix 2 is b
  • the specific value of the expansion factor at the corresponding position is (b mod Z).
  • the sending end can first expand to obtain the check matrix 0, and then perform a simple transformation based on the check matrix 0 to obtain the check matrix of the required expansion factor. It can be seen that in this implementation, the sending end performs the same expansion operation by using any expansion factor to expand the first base matrix, and does not need to perform different expansion operations, so the coding complexity is low.
  • the transmitting end expands the check matrix 0 based on the first base matrix to obtain the check matrix 0.
  • the specific value of the expansion factor in check matrix 0 plus the integer multiple of Z is used as the specific value of the expansion factor at the corresponding position in check matrix 1.
  • the specific value of an expansion factor in check matrix 0 is b
  • the specific value of the expansion factor in check matrix 1 is b.
  • the specific value of the expansion factor at the corresponding position in is b, (b+Z) or (b+2Z).
  • the check matrix 0 may be the aforementioned first check matrix
  • the check matrix 1 may be the aforementioned second check matrix. Both check matrix 0 and check matrix 1 conform to the first basis matrix.
  • the expansion factor Z may be the smallest expansion factor that may be used by the transmitting end to expand the first basis matrix.
  • the expansion factors of the CPMs in the check matrix that the sender needs to obtain are all greater than or equal to Z. Therefore, there is no need to obtain a check matrix with an expansion factor smaller than Z.
  • the sending end can first expand to obtain the check matrix 0, and then perform a simple transformation based on the check matrix 0 to obtain the check matrix of the required expansion factor. It can be seen that in this implementation, the sending end performs the same expansion operation by using any expansion factor to expand the first base matrix, and does not need to perform different expansion operations, so the coding complexity is low.
  • the transmitting end expands the check matrix 0 based on the first base matrix to obtain the check matrix 0.
  • the specific value of the expansion factor in matrix 0 is taken as the value obtained by the modulo Z operation as the specific value of the expansion factor at the corresponding position in check matrix 3.
  • the specific value of an expansion factor in check matrix 0 is b, and in check matrix 3
  • the specific value of the expansion factor at the corresponding position is (b mod Z); if you need to obtain the check matrix 4 with the expansion factor Z4 (greater than or equal to Z), add the specific value of the expansion factor in the check matrix 0 to Z
  • the integer multiple is used as the specific value of the expansion factor at the corresponding position in the check matrix 4.
  • the specific value of an expansion factor in the check matrix 0 is b
  • the specific value of the expansion factor at the corresponding position in the check matrix 4 is b, (b +Z) or (b+2Z).
  • the check matrix 3 may be the aforementioned first check matrix
  • the check matrix 4 may be the aforementioned second check matrix.
  • Both check matrix 3 and check matrix 4 conform to the first basis matrix. Both check matrix 3 and check matrix 4 can be regarded as check matrices expanded based on the first basis matrix. It should be noted that each element in the check matrix 4 cannot be larger than Z1.
  • the sending end can first expand to obtain the check matrix 0, and then perform a simple transformation based on the check matrix 0 to obtain the check matrix of the required expansion factor. It can be seen that in In this implementation, when the transmitter uses any expansion factor to expand the first base matrix, the same expansion operation is performed. There is no need to perform different expansion operations, and the coding complexity is low.
  • This application describes the way in which the sending end obtains multiple check matrices based on the expansion of the first base matrix. It should be understood that the receiving end can use a similar method to expand multiple check matrices based on the first basis matrix, which will not be described again here.
  • the second type of solution provided by this application is to comprehensively consider multiple factors such as the performance of the LDPC code, decoding convergence speed, decoding complexity, etc., and design several groups of base matrices of the LDPC code with low complexity and fast decoding convergence. and the corresponding check matrix.
  • the base matrix of the LDPC code can be designed according to the quasi-rule check degree, that is, the weight (number of non-zero entries) of all rows of the base matrix has only two values: d and d+1.
  • the maximum degree of the check node is minimized as much as possible in this application (as mentioned above, d+1).
  • the maximum degree of the check node refers to the maximum number of edges of the check node or the maximum row weight of the check matrix.
  • this application introduces two control variables: average variable node degree and slope.
  • the basis matrix and check matrix provided by this application can effectively balance the performance, decoding convergence speed, complexity and other factors of the designed LDPC code.
  • the average variable node degree refers to the average column weight of the check matrix, that is, the average number of non-zero items contained in each column; here the slope refers to the fitting slope of the EBP-GEXIT graph curve of the designed LDPC code.
  • the decoding complexity is expressed by the average variable node degree ( ⁇ )
  • the specific complexity of LDPC iterative decoding can be expressed by the product of the average number of iterations and the decoding complexity: C ⁇ n ⁇ n it .
  • C represents the order of magnitude of the approximate decoding operation complexity
  • eta represents the average variable node degree
  • n it represents the average number of iterations.
  • the following takes the LDPC codes (i.e., parity check matrix) with code lengths of 320 bits and 640 bits as examples to specifically illustrate the different designs using different control variables (average variable node degree, slope).
  • SNR signal noise ratio
  • the first column represents the slope in the above control parameters
  • the second column to the last column in the first row describe the average column weight of the basis matrix
  • each item in the table represents the corresponding slope
  • two typical optimally designed codes i.e. basis matrices
  • Table 2 Shown in bold numbers.
  • the base matrix of the designed LDPC code can be obtained first, and then the base matrix can be expanded to obtain check matrices of LDPC codes with different code lengths.
  • the code rates of the check matrix 41, the check matrix 42, the check matrix 43, and the check matrix 44 provided by the embodiment of this application are all 1/2, and the code lengths are 320, 640, 1280, and 2560 bits respectively.
  • the code rates of the check matrix 51, the check matrix 52, the check matrix 53, and the check matrix 54 provided by the embodiment of this application are all 1/2, and the code lengths are 320, 640, 1280, and 2560 bits respectively.
  • the complexity of the basis matrix 4 that the check matrix 41, the check matrix 42, the check matrix 43 and the check matrix 44 conform to is 3.2, and the check matrix 51, the check matrix 52, the check matrix 53 and the check matrix 54 conform to The complexity of the basis matrix 5 is 3.6.
  • the complexity of the base matrix can represent the complexity of a single decoding using the check matrix extended by the base matrix. It can be understood that the better the complexity of the base matrix, the higher the complexity of a single decoding using the check matrix extended by the base matrix. In this application, the complexity of the base matrix is the complexity of the LDPC code obtained from the base matrix.
  • the following describes the simulation performance of the frame error rate (FER) of the LDPC codes with complexity 3.2 and 3.6 provided by this application under different hierarchical decoding iterations in conjunction with the accompanying drawings.
  • the LDPC codes of 3.2 and 3.6 can be understood as LDPC encoding or decoding schemes using the basis matrix provided by this application.
  • FIG. 16A is a schematic diagram showing the comparison of FER simulation performance under 25 hierarchical decoding iterations of an LDPC code provided by the embodiment of the present application.
  • the abscissa represents SNR
  • the ordinate represents FER
  • NR 320 represents the FER under 15 hierarchical decoding iterations in the NR system based on a check matrix with a code rate of 1/2 and a code length of 320 bits
  • WiFi 312 Indicates the FER of a WiFi device (such as a station or access point) under 15 hierarchical decoding iterations based on a parity check matrix with a code rate of 1/2 and a code length of 320 bits.
  • 320 3.2 indicates that the receiving end uses a code rate of 1/ 2.
  • 640 3.6 means that the receiving end is based on a code rate of 1/2, a code length of 320 bits, and a complexity of 3.6.
  • NR 640 represents the FER under 15 layered decoding iterations in the NR system based on a check matrix with a code rate of 1/2 and a code length of 640 bits
  • WiFi 624 represents WiFi device (such as a station or access point) performs FER under 15 hierarchical decoding iterations based on a parity check matrix with a code rate of 1/2 and a code length of 640 bits.
  • 640 3.2 means that the receiving end uses a code rate of 1/2
  • 640 3.6 indicates that the receiving end is based on an LDPC code with a code rate of 1/2, a code length of 640 bits, and a complexity of 3.6 FER under 15 hierarchical decoding iterations
  • NR 1280 represents the FER under 15 hierarchical decoding iterations in the NR system based on a check matrix with a code rate of 1/2 and a code length of 1280 bits
  • WiFi 1248 represents WiFi
  • the device (such as a station or access point) performs FER under 15 hierarchical decoding iterations based on a check matrix with a code rate of 1/2 and a code length of 1280 bits.
  • 1280 3.2 indicates that the receiving end performs FER based on a code rate of 1/2 and a code length of 1280 bits.
  • 1280 3.6 indicates that the receiving end is based on an LDPC code with a code rate of 1/2, a code length of 1280 bits, and a complexity of 3.6.
  • FER under 15 layered decoding iterations NR 2560 represents the FER under 15 layered decoding iterations based on a check matrix with a code rate of 1/2 and a code length of 2560 bits in the NR system
  • WiFi 2496 represents WiFi equipment (such as a station or access point)
  • 2560 3.2 means that the receiving end uses a code rate of 1/2 and a code length of 2560 bits.
  • 2560 3.6 means that the receiving end performs the decoding based on an LDPC code with a code rate of 1/2, a code length of 2560 bits, and a complexity of 3.6.
  • Figure 16B is a schematic diagram showing the comparison of FER simulation performance under 15 hierarchical decoding iterations of an LDPC code provided by this application.
  • Figure 16C is a schematic diagram of the FER simulation performance comparison under 5 hierarchical decoding iterations of an LDPC code provided by this application.
  • the meanings of the lines in Figure 16B and Figure 16C are similar to the meanings of the lines in Figure 16A and will not be described again here.
  • the LDPC code designed in this application can obtain better performance when the number of decoding iterations is smaller (for example, 5 iterations), and the trade-off between decoding complexity and performance can be flexibly controlled. of equilibrium.
  • Table 3, Table 4, and Table 5 respectively show a comprehensive comparison between the performance and complexity of the LDPC code provided by this application and WLAN LDPC and NR LDPC under different numbers of decoding iterations. It can be seen that in the case of low complexity, the LDPC code provided by this application can obtain better performance, and only needs to implement the expansion of a single basis matrix.
  • Table 3 shows a comprehensive comparison between the performance and complexity of the LDPC code provided by this application and WLAN LDPC and NR LDPC under 5 split decoding iterations.
  • New 3.2 represents the LDPC code provided by this application with a code rate of 1/2, a code length of 2560 bits, and a complexity of 3.2 (corresponding to a basis matrix provided by this application).
  • New 3.6 represents the LDPC code provided by this application with a code rate of 1/2, a code length of 2560 bits, and a complexity of 3.6 (corresponding to another basis matrix provided by this application).
  • the second column represents the average variable node degree
  • Table 4 shows a comprehensive comparison between the performance and complexity of the LDPC code provided by this application and WLAN LDPC and NR LDPC under 15 split decoding iterations. The meaning of each parameter in Table 4 can be found in Table 3.
  • Table 5 shows a comprehensive comparison between the performance and complexity of the LDPC code provided by this application and WLAN LDPC and NR LDPC under 25 split decoding iterations. The meaning of each parameter in Table 5 can be found in Table 3.
  • Figure 17A is a schematic diagram of the performance of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by an embodiment of the present application under 10 decoding iterations.
  • Figure 17B is a schematic diagram of the performance of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by an embodiment of the present application under 15 decoding iterations.
  • Figure 17C is a schematic diagram of the performance of a check matrix 41, a check matrix 42, a check matrix 43, and a check matrix 44 provided by an embodiment of the present application under 25 decoding iterations.
  • FIG 1701 represents the performance curve of the check matrix 41
  • 1702 represents the performance curve of the check matrix 42
  • 1703 represents the performance curve of the check matrix 43
  • 1704 represents the performance curve of the check matrix 44 .
  • Figure 18A is a schematic diagram of the performance of a check matrix 51, a check matrix 52, a check matrix 53, and a check matrix 54 provided by an embodiment of the present application under 10 decoding iterations.
  • Figure 18B is a schematic diagram of the performance of a check matrix 51, a check matrix 52, a check matrix 53, and a check matrix 54 provided by an embodiment of the present application under 15 decoding iterations.
  • Figure 18C is a performance diagram of the parity check matrix 51, parity check matrix 52, parity check matrix 53, and parity check matrix 54 provided by the embodiment of the present application under 25 decoding iterations.
  • 1801 represents the performance curve of the check matrix 51
  • 1802 represents the performance curve of the check matrix 52
  • 1803 represents the performance curve of the check matrix 53
  • 1804 represents the performance curve of the check matrix 54.
  • FIG 19 is a schematic structural diagram of a communication device 1900 provided by an embodiment of the present application.
  • the communication device 1900 can correspond to the functions or steps implemented by the sending end in each of the above method embodiments, and can also correspond to the functions or steps implemented by the receiving end in each of the above method embodiments.
  • the communication device may include a processing module 1910 and a transceiver module 1920.
  • a storage unit may also be included, which may be used to store instructions (code or programs) and/or data.
  • the processing module 1910 and the transceiver module 1920 can be coupled with the storage unit.
  • the processing module 1910 can read the instructions (code or program) and/or data in the storage unit to implement the corresponding method.
  • Each of the above units can be set up independently or partially or fully integrated.
  • the transceiver module 1920 may include a sending module and a receiving module.
  • the sending module can be a transmitter
  • the receiving module can be a receiver.
  • the entity corresponding to the transceiver module 1920 may be a transceiver or a communication interface.
  • the communication device 1900 can correspondingly implement the behaviors and functions of the sending end in the above method embodiments.
  • the communication device 1900 may be a station, or may be a component (such as a chip or a circuit) used in the station.
  • the communication device 1900 may be an access point, or may be a component (such as a chip or circuit) used in the access point.
  • the transceiver module 1920 may, for example, be used to perform all receiving or sending operations performed by the sending end in the embodiments of FIG. 8, FIG. 9, and FIG. 10, such as step 802 in the embodiment shown in FIG. 8, and step 802 in the embodiment shown in FIG. 9.
  • the processing module 1910 is used to perform all operations performed by the sending end in the embodiments of Figures 8, 9, and 10 except for the sending and receiving operations, such as step 801 in the embodiment shown in Figure 8, as shown in Figure 9 Steps 902 and 902 in the embodiment, and steps 1001, 1002, 1006 and 1007 in the embodiment shown in FIG. 10 .
  • the communication device 1900 can correspondingly implement the behaviors and functions of the receiving end in the above method embodiments.
  • the communication device 1900 may be an access point, or may be a component (such as a chip or circuit) used in the access point.
  • the communication device 1900 may be a station, or may be a component (such as a chip or a circuit) used in the station.
  • the transceiver module 1920 may, for example, be used to perform all receiving or sending operations performed by the receiving end in the embodiments of FIG. 8, FIG. 9, and FIG. 10, such as step 802 in the embodiment shown in FIG. 8, and step 802 in the embodiment shown in FIG. 9.
  • the processing module 1910 is used to perform all operations performed by the receiving end except for the sending and receiving operations, such as steps 803 and 804 in the embodiment shown in Figure 8, and steps 904 and 904 in the embodiment shown in Figure 9. 905, step 906, step 907, and step 1004, step 1005, step 1009, and step 1010 in the embodiment shown in FIG. 10 .
  • Figure 20 is a schematic structural diagram of another communication device 200 provided by an embodiment of the present application.
  • the communication device in Figure 20 may be the above-mentioned sending end or the above-mentioned receiving end.
  • the communication device 200 includes at least one processor 2010 and a transceiver 2020 .
  • the processor 2010 and the transceiver 2020 may be used to perform functions or operations performed by the sending end, etc.
  • the transceiver 2020 performs, for example, all receiving or transmitting operations performed by the transmitting end in the embodiments of FIG. 8, FIG. 9, and FIG. 10.
  • the processor 2010 is, for example, configured to perform all operations performed by the sending end in the embodiments of FIG. 8, FIG. 9, and FIG. 10 except for the sending and receiving operations.
  • the processor 2010 and the transceiver 2020 may be used to perform functions or operations performed by the receiving end, etc.
  • the transceiver 2020 performs, for example, all receiving or transmitting operations performed by the receiving endpoint in the embodiments of FIG. 8, FIG. 9, and FIG. 10.
  • the processor 2010 is used to perform all operations performed by the receiving end except for the sending and receiving operations.
  • Transceiver 2020 is used to communicate with other devices/devices over transmission media.
  • the processor 2010 uses the transceiver 2020 to send and receive data and/or signaling, and is used to implement the method in the above method embodiment.
  • the processor 2010 can implement the function of the processing module 1910, and the transceiver 2020 can implement the function of the transceiver module 1920.
  • the transceiver 2020 may include a radio frequency circuit and an antenna.
  • the radio frequency circuit is mainly used for conversion of baseband signals and radio frequency signals and processing of radio frequency signals.
  • Antennas are mainly used to send and receive radio frequency signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, keyboards, etc., are mainly used to receive data input by users and output data to users.
  • the communication device 200 may also include at least one memory 2030 for storing program instructions and/or data.
  • Memory 2030 and processor 2010 are coupled.
  • the coupling in the embodiment of this application is an indirect coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information interaction between devices, units or modules.
  • the processor 2010 may cooperate with the memory 2030.
  • Processor 2010 may execute program instructions stored in memory 2030. At least one of the at least one memory may be included in the processor.
  • the processor 2010 can read the software program in the memory 2030, interpret and execute the instructions of the software program, and process the data of the software program.
  • the processor 2010 performs baseband processing on the data to be sent, and then outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit performs radio frequency processing on the baseband signal and then sends the radio frequency signal out in the form of electromagnetic waves through the antenna.
  • the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 2010.
  • the processor 2010 converts the baseband signal into data and performs processing on the data. deal with.
  • the above-mentioned radio frequency circuit and antenna can be arranged independently of the processor that performs baseband processing.
  • the radio frequency circuit and antenna can be arranged remotely and independently of the communication device.
  • connection medium between the above-mentioned transceiver 2020, processor 2010 and memory 2030 is not limited in the embodiment of the present application.
  • the memory 2030, the processor 2010 and the transceiver 2020 are connected through a bus 2040 in Figure 20.
  • the bus is represented by a thick line in Figure 20.
  • the connection methods between other components are only schematically explained. , is not limited.
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 20, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which may implement or Execute each method, step and logical block diagram disclosed in the embodiment of this application.
  • a general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware processor for execution, or can be executed by a combination of hardware and software modules in the processor.
  • Figure 21 is a schematic structural diagram of another communication device 210 provided by an embodiment of the present application.
  • the communication device shown in FIG. 21 includes a logic circuit 2101 and an interface 2102 .
  • the processing module 1910 in Figure 19 can be implemented by the logic circuit 2101, and the transceiver module 1920 in Figure 19 can be implemented by the interface 2102.
  • the logic circuit 2101 can be a chip, a processing circuit, an integrated circuit or a system on chip (SoC) chip, etc.
  • the interface 2102 can be a communication interface, Input and output interfaces, etc.
  • the logic circuit and the interface may also be coupled to each other.
  • the embodiments of this application do not limit the specific connection methods of the logic circuits and interfaces.
  • the logic circuit and interface may be used to perform the above functions or operations performed by the sending end, etc.
  • the logic circuit and interface may be used to perform the above functions or operations performed by the receiving end, etc.
  • This application also provides a computer-readable storage medium, which stores computer programs or instructions.
  • the computer program or instructions When the computer program or instructions are run on a computer, the computer is caused to execute the method of the above embodiments.
  • the computer program product includes instructions or computer programs. When the instructions or computer programs are run on a computer, the methods in the above embodiments are executed.
  • This application also provides a communication system, including the above-mentioned sending end and the above-mentioned receiving end.

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Abstract

本申请公开了一种LDPC的编译码方法和相关装置，本申请应用于支持IEEE802.11ax下一代Wi-Fi协议，Wi-Fi8等802.11系列协议的无线局域网系统，还可以应用于基于UWB的无线个人局域网系统。该方法包括：根据校验矩阵，对第一比特序列进行低密度奇偶校验LDPC编码，得到第一数据包，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同；发送所述第一数据包。通过同一个基矩阵，即第一基矩阵，扩展得到第一校验矩阵和第二校验矩阵，能够降低编码的复杂度。

Description

LDPC的编译码方法和相关装置
本申请要求于2022年06月18日提交中国专利局、申请号为202210688993.0、申请名称为“LDPC的编译码方法和相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及LDPC的编译码方法和相关装置。
背景技术
IEEE802.11n/ac/ax/be等无线局域网(wireless local area networks，WLAN)传输标准主要研究在大带宽场景下提升用户的体验，包括提升用户平均吞吐量以及电池类供电设备的能量使用效率。60GHz大带宽场景需要支持在有限的频率和功率资源上实现数据、视频等业务的高速可靠传输，因此需要高可靠性和高效率的信道编译码方案。在信道编码领域，Turbo码和低密度奇偶校验(low-density parity-check,LDPC)码是目前应用最成熟和广泛的两种信道编码方法，它们都有接近香农(Shannon)限的性能。与Turbo码相比，LDPC码具有：不需要深度交织器即可获得很好的误码性能；具有更好的误帧率性能；错误平层大大降低；支持并行译码，译码延时小等优点。
因此，LDPC码已成为IEEE802.11n/ac/ax等低频短距WLAN通信系统的标准信道编码方案，在IEEE802.11ax大于等于40MHz带宽情况下成为必选信道编码方案。基于此，可考虑针对下一代WLAN标准或超宽带(ultra wide band，UWB)设计新的LDPC码，以进一步提高下一代WLAN系统或UWB系统的可靠性和系统性能。
发明内容
本申请实施例公开了一种LDPC的编译码方法和相关装置，能够降低编码的复杂度。
第一方面，本申请实施例提供一种LDPC码的编码方法，该方法包括：根据校验矩阵，对第一比特序列进行低密度奇偶校验LDPC编码，得到第一数据包，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同；发送所述第一数据包。
本申请实施例中，第一校验矩阵和第二校验矩阵均符合第一基矩阵。通过同一个基矩阵，即第一基矩阵，扩展得到不同码长的第一校验矩阵和第二校验矩阵。实现多个基矩阵与实现一个基矩阵相比，需要更大的功耗以及提升编码复杂度。本申请实施例中，通过一个基矩阵扩展得到多个校验矩阵，仅需要实现一个基矩阵，而不是多个基矩阵，能够降低硬件的功耗，以及降低编码的复杂度。
在一种可能的实现方式中，所述根据校验矩阵，对第一比特序列进行低密度奇偶校验LDPC编码，得到第一数据包包括：在所述第一比特序列的长度位于第一区间的情况下，根据所述第一校验矩阵对所述第一比特序列进行低密度奇偶校验LDPC编码，得到所述第一数据包；或者，在所述第一比特序列的长度位于第二区间的情况下，根据所述第二校验矩阵对所述第一比特序列进行低密度奇偶校验LDPC编码，得到所述第一数据包；所述第一区间和 所述第二区间不重叠。
在该实现方式中，根据第一比特序列的长度灵活地选择恰当码长的校验矩阵对该第一比特序列进行LDPC编码。也就是说，根据第一比特序列的长度可扩展得到最合理的校验矩阵来进行LDPC编码，可提高资源利用率。
第二方面，本申请实施例提供一种LDPC码的译码方法，该方法包括：获取接收到的第一信道接收序列对应的第一对数似然比LLR序列；根据校验矩阵，对所述第一LLR序列进行译码，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同。
本申请实施例中，第一校验矩阵和第二校验矩阵均符合第一基矩阵。通过同一个基矩阵，即第一基矩阵，扩展得到不同码长的第一校验矩阵和第二校验矩阵。实现多个基矩阵与实现一个基矩阵相比，需要更大的功耗以及提升编码复杂度。本申请实施例中，通过一个基矩阵扩展得到多个校验矩阵，仅需要实现一个基矩阵，而不是多个基矩阵，能够降低硬件的功耗，以及降低编码的复杂度。
在第一方面和第二方面的一种可能的实现方式中，所述第一校验矩阵中的第一位置的循环位移矩阵CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z1，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z2，所述Z、所述Z1、所述Z2均为大于0的整数，所述Z1大于或等于所述Z，所述Z2小于所述Z。第一位置可以是第一校验矩阵中的任意一个位置。可选的，Z为27的整倍数，例如27、54、81等。
在该实现方式中，第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)。通过第一基矩阵扩展得到第一校验矩阵和第二校验矩阵，仅需要实现第一基矩阵，需要实现多个基矩阵，能够降低硬件的功耗，以及降低编码的复杂度。
在第一方面和第二方面的一种可能的实现方式中，所述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z3，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z4，所述Z、所述Z3、所述Z4均为大于0的整数，所述Z3小于所述Z，所述Z4大于或等于所述Z。第一位置可以是第一校验矩阵中的任意一个位置。可选的，Z和Z4均为27的整倍数，例如Z为27，Z4为54、81等。
在该实现方式中，第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个。通过第一基矩阵扩展得到第一校验矩阵和第二校验矩阵，仅需要实现第一基矩阵，不需要实现多个基矩阵，能够降低硬件实现的复杂度、功耗。
在第一方面和第二方面的一种可能的实现方式中，所述第一基矩阵对应于原校验矩阵，所述原校验矩阵中的CPM的扩展因子为Z，所述原校验矩阵的第一位置的CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z1，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z2，所述Z、所述Z1、所述Z2均为大于0的整数，所述Z1大于或等于所述Z，所述Z2小于所述Z。可选的，Z为27的整倍数，例如27、54、81等。可选的，所述校验矩阵还包括所述原校验矩阵。
在该实现方式中，第一校验矩阵中的第一位置的循环位移矩阵CPM的扩展因子具体值为b，第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)；能够快速地扩展得到所需的校验矩阵。
在第一方面和第二方面的一种可能的实现方式中，所述第一基矩阵对应于原校验矩阵，所述原校验矩阵中的CPM的扩展因子为Z，所述原校验矩阵的第一位置的CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z3，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z4，所述Z、所述Z3、所述Z4均为大于0的整数，所述Z3小于所述Z，所述Z4大于或等于所述Z。可选的，Z和Z4均为27的整倍数，例如Z为27，Z4为54、81等。
在该实现方式中，第一校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，能够快速地扩展得到所需的校验矩阵。
在第一方面和第二方面的一种可能的实现方式中，所述方法还包括：根据所述第一基矩阵扩展得到原校验矩阵，所述原校验矩阵中的CPM的扩展因子为Z；根据所述原校验矩阵，得到所述第一校验矩阵或者所述第二校验矩阵，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z1，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z2，所述原校验矩阵的第一位置的循环位移矩阵CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的循环位移矩阵CPM的扩展因子具体值为b，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述Z、所述Z1、所述Z2均为大于0的整数，所述Z1大于或等于所述Z，所述Z2小于所述Z。原校验矩阵可以是下文图6、图14或图15所示的矩阵。
在该实现方式中，根据原校验矩阵，得到第一校验矩阵或者第二校验矩阵；可以快速得到所需的校验矩阵。
在第一方面和第二方面的一种可能的实现方式中，所述方法还包括：根据所述第一基矩阵扩展得到原校验矩阵，所述原校验矩阵中的CPM的扩展因子为Z；根据所述原校验矩阵，得到所述第一校验矩阵或者所述第二校验矩阵，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z3，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z4，所述原校验矩阵的第一位置的循环位移矩阵CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，所述Z、所述Z3、所述Z4均为大于0的整数，所述Z3小于所述Z，所述Z4大于或等于所述Z。可选的，Z和Z4均为27的整倍数，例如Z为27，Z4为54、81等。
在该实现方式中，根据原校验矩阵，得到第一校验矩阵或者第二校验矩阵；可以快速得到所需的校验矩阵。
第三方面，本申请实施例提供一种通信装置，该通信装置具有实现上述第一方面方法实施例中的行为的功能。该通信装置可以是通信设备，也可以是通信设备的部件(例如处理器、芯片、或芯片系统等)，还可以是能实现全部或部分该通信设备的功能的逻辑模块或软件。该通信装置的功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，该硬件或软件包括一个或多个与上述功能相对应的模块或单元。在一种可能的实现方式中，该通信装置包括接口模块和处理模块，其中：所述处理模块，用于根据校验矩阵，对第一比特序列进行低密 度奇偶校验LDPC编码，得到第一数据包，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同；所述接口模块，用于发送所述第一数据包。
第三方面的通信装置的可能的实现方式可参见第一方面的各种可能的实现方式。
关于第三方面的各种可能的实现方式所带来的技术效果，可参考对于第一方面或第一方面的各种可能的实现方式的技术效果的介绍。
第四方面，本申请实施例提供一种通信装置，该通信装置具有实现上述第二方面方法实施例中的行为的功能。该通信装置可以是通信设备，也可以是通信设备的部件(例如处理器、芯片、或芯片系统等)，还可以是能实现全部或部分该通信设备的功能的逻辑模块或软件。该通信装置的功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，该硬件或软件包括一个或多个与上述功能相对应的模块或单元。在一种可能的实现方式中，该通信装置包括接口模块和处理模块，其中：所述接口模块，用于接收第一信道接收序列；所述处理模块，用于获取所述第一信道接收序列对应的第一对数似然比LLR序列；根据校验矩阵，对所述第一LLR序列进行译码，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同。
第四方面的通信装置的可能的实现方式可参见第二方面的各种可能的实现方式。
关于第四方面的各种可能的实施方式所带来的技术效果，可参考对于第二方面或第二方面的各种可能的实施方式的技术效果的介绍。
第五方面，本申请实施例提供另一种通信装置，该通信装置包括处理器，该处理器与存储器耦合，该存储器用于存储程序或指令，当该程序或指令被该处理器执行时，使得该通信装置执行上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，当该程序或指令被该处理器执行时，使得该通信装置执行上述第二方面或第二方面的任意可能的实现方式所示的方法。
本申请实施例中，在执行上述方法的过程中，上述方法中有关发送信息(或信号)的过程，可以理解为基于处理器的指令进行输出信息的过程。在输出信息时，处理器将信息输出给收发器，以便由收发器进行发射。该信息在由处理器输出之后，还可能需要进行其他的处理，然后到达收发器。类似的，处理器接收输入的信息时，收发器接收该信息，并将其输入处理器。更进一步的，在收发器收到该信息之后，该信息可能需要进行其他的处理，然后才输入处理器。
对于处理器所涉及的发送和/或接收等操作，如果没有特殊说明，或者，如果未与其在相关描述中的实际作用或者内在逻辑相抵触，则可以一般性的理解为基于处理器的指令输出。
在实现过程中，上述处理器可以是专门用于执行这些方法的处理器，也可以是执行存储器中的计算机指令来执行这些方法的处理器，例如通用处理器等。例如，处理器还可以用于执行存储器中存储的程序，当该程序被执行时，使得该通信装置执行如上述第一方面或第一方面的任意可能的实现方式所示的方法。
在一种可能的实现方式中，存储器位于上述通信装置之外。在一种可能的实现方式中，存储器位于上述通信装置之内。
在一种可能的实现方式中，处理器和存储器还可能集成于一个器件中，即处理器和存储器还可能被集成于一起。
在一种可能的实现方式中，通信装置还包括收发器，该收发器，用于接收信号或发送信 号等。
第六方面，本申请提供另一种通信装置，该通信装置包括处理电路和接口电路，该接口电路用于获取数据或输出数据；处理电路用于执行如上述第一方面或第一方面的任意可能的实现方式所示的相应的方法，或者，处理电路用于执行如上述第二方面或第二方面的任意可能的实现方式所示的相应的方法。
第七方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，该计算机程序包括程序指令，该程序指令被执行时使得计算机执行如上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，该程序指令被执行时使得计算机执行如上述第二方面或第二方面的任意可能的实现方式所示的方法。
第八方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序，该计算机程序包括程序指令，该程序指令被执行时使得计算机执行如上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，该程序指令被执行时使得计算机执行如上述第二方面或第二方面的任意可能的实现方式所示的方法。
第九方面，本申请提供一种通信系统，包括上述第三方面或第三方面的任意可能的实现方式所述的通信装置、上述第四方面或第四方面的任意可能的实现方式所述的通信装置。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1为本申请提供的一种LDPC码的校验矩阵H的示例；
图2为本申请实施例提供的一种LDPC码的校验矩阵H的Tanner图；
图3为本申请提供的一种LDPC码的编码过程的示例；
图4为本申请实施例提供的一种LDPC编码流程中缩短操作部分的示意图；
图5为本申请实施例提供的4种CPM的示例；
图6为本申请实施例提供的一种由大小为(12×24)的基矩阵扩展得到的一个校验矩阵的示例；
图7为本申请提供的技术方案适用的一种无线通信系统的示例；
图8为本申请提供的一种LDPC码的编码方法交互流程图；
图9为本申请提供的另一种LDPC码的编码方法交互流程图；
图10为本申请实施例提供的另一种LDPC码的编码方法交互流程图；
图11为本申请实施例提供的一种表征第一基矩阵的矩阵以及根据该第一基矩阵扩展得到的四种校验矩阵的扩展因子具体值矩阵的示例；
图12为本申请实施例提供的一种第一校验矩阵的示例；
图13为本申请实施例提供的另一种表征第一基矩阵的矩阵以及根据该第一基矩阵扩展得到的四种校验矩阵的扩展因子具体值矩阵的示例；
图14为本申请提供的一种基于基矩阵2扩展得到的校验矩阵的示例；
图15为本申请提供的一种基于基矩阵2扩展得到的校验矩阵的示例；
图16A为本申请实施例提供的一种LDPC码25次分层译码迭代下的FER仿真性能对比示意图；
图16B为本申请实施例提供的一种LDPC码15次分层译码迭代下的FER仿真性能对比 示意图；
图16C为本申请实施例提供的一种LDPC码5次分层译码迭代下的FER仿真性能对比示意图；
图17A为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在10次译码迭代次数下的性能示意图；
图17B为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在15次译码迭代次数下的性能示意图；
图17C为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在25次译码迭代次数下的性能示意图；
图18A为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在10次译码迭代次数下的性能示意图；
图18B为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在15次译码迭代次数下的性能示意图；
图18C为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在25次译码迭代次数下的性能示意图；
图19为本申请实施例提供的一种通信装置1900的结构示意图；
图20为本申请实施例提供的另一种通信装置200的结构示意图；
图21为本申请实施例提供的另一种通信装置210的结构示意图。
具体实施方式
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等仅用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备等，没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元等，或可选地还包括对于这些过程、方法、产品或设备等固有的其它步骤或单元。
本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”、“举例来说”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“举例来说”或者“例如”等词旨在以具体方式呈现相关概念。
在本文中提及的“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括复数表达形式，除非其上下文中明确地有相反指示。还应当理解，本申请中使用的术语“和/或”是指并包含一个或多个所列出项目的任何或所有可能组合。例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。本申请中使用的术语“多个”是指两个或两个以上。
可以理解，在本申请各实施例中，“A对应的B”表示A与B存在对应关系，根据A可以确定B。但还应理解，根据(或基于)A确定(或生成)B并不意味着仅仅根据(或基于)A确定(或生成)B，还可以根据(或基于)A和/或其它信息确定(或生成)B。
为了便于理解本申请的方案，首先对本申请中LDPC码的相关概念进行介绍。
LDPC码全名是低密度奇偶校验码，从字面意思理解，就是一种具有低密度性质的奇偶校验码。这里的低密度指的是LDPC码的校验矩阵具有低密度。因此，要弄明白LDPC码是什么，首先要弄明白奇偶校验码、校验矩阵以及低密度这三个概念。
1.奇偶校验码
奇偶校验码是一种通过增加冗余位使得码字中"1"的个数恒为奇数或偶数的编码方法,它是一种检错码。奇偶校验码常用于0-1的二元域上的数字编码，在码字的最后添加一位或者若干位(校验位)，通过码字中1的个数是奇数还是偶数来判断码字在传输前后是否出错。比如100这个码字，采用奇偶校验，那么校验位就可以取1，这时候满足所有码字加起来(异或)的值s为0，即1001。如果传输后变为了1101，错误了一个信息位(可称为比特位)，那么这时候s为1，可以判断传输出错。应理解，如果错误的是偶数个信息位，那么算法失效。因此，进一步的，可以设置多个校验位。例如，1101这个四位码字，可以分组，使用校验位的第一位来校验信息位的第一位和第二位(即信息位的前两位11)。例如，使信息位的前两位的和为0，那么校验位的第一位就应该取0。同理，校验位的第二位可以检验码字1101的后两位信息位，那么就校验位的第二位取1。因此，编码后的码字是110101。这其实就是LDPC码的校验思想，即“PC”的含义。可见，LDPC码是一种分组码，并且使用的其实就是奇偶校验。如果再加上低密度的特性，就能得到LDPC码。
2.LDPC码的低密度性质
LDPC码的低密度性质指的就是LDPC码的校验矩阵中为1的个数很少。LDPC码是一种线性分组码，其校验矩阵是一种稀疏矩阵。LDPC码的校验矩阵中零元素的个数远远多于非零元素的个数。或者说，校验矩阵的行重(即每行中的1的个数)和列重(即每列中的1的个数)与LDPC码的码长相比是很小的数。
3.LDPC码的校验矩阵和生成矩阵
以上面的1101码字举例，码字的信息位和校验位之间的校验关系可以写为矩阵的形式。记信息位为c1,c2,c3,c4，校验位为p1,p2。c＝[c1,c2,c3,c4]，x＝[c1,c2,c3,c4,p1,p2]。这里c和x分别是编码前后的码字。在码字1101的举例中，码字1101的信息位和校验位之间的校验关系可表示为如下线性关系：c1+c2+p1＝0，c3+c4+p2＝0。该线性关系可以写为如下公式：
x·HT＝s＝0   (1)；
其中，H为：s＝(0,0)。这里的H就是校验矩阵，s为校验子，HT表示H的转置。公式(1)的思想就是原来的码字(未编码的码字)c经过生成矩阵G(G由H决定)编码后，得到的发送码字x需要满足x·HT＝0。为了方便的判断这个结果是不是0，我们引入校验子s的概念，只要s全为0，那么传输就是没问题的。本申请中，“·”表示矩阵乘法运算，“A·B”表示矩阵A和矩阵B的矩阵相乘的乘积。
c经过生成矩阵G编码得到的发送码字x可满足如下公式：
x＝c·G；   (2)；
其中，c表示未编码的码字(或者说比特序列)，G表示生成矩阵。G和HT彼此正交， 即G·HT＝0。生成矩阵可由校验矩阵经过变换而得来。也就是说，知道了校验矩阵，就可得到该校验矩阵对应的生成矩阵。c可称为信息码字，x可称为发送码字。公式(2)表明发送码字是由信息码字与生成矩阵相乘得到的。
4.Tanner图
Tanner在1981年将LDPC码的码字用图的方式表示了出来。现在将这种图称为Tanner图，Tanner图和校验矩阵一一对应。Tanner图由两类顶点组成，一类顶点为变量节点，代表码字比特，另一类顶点为校验节点，代表校验约束关系。每个校验节点代表一个校验约束关系，下面结合图1和图2进行说明。
参见图1，图1为本申请提供的一种LDPC码的校验矩阵H的示例。图1中，{Vi}表示变量节点集，{Ci}表示校验节点集。校验矩阵H的每行对应一个校验方程，每列对应一个码字比特。图1中，变量节点为8个，校验节点为4个。如果一个码字比特包含在相应的校验方程中，就用一条连线将所涉及的变量节点和校验节点连起来，得到Tanner图。
参见图2，图2为本申请实施例提供的一种LDPC码的校验矩阵H的Tanner图。如图2所示，Tanner图表示的即是LDPC码的校验矩阵。例如，对于大小为m行n列的校验矩阵H，Tanner图中包含两类节点，分别为n个变量节点(也可称为信息节点或比特节点)和m个校验节点，m、n均为大于0的整数。其中，上述n个变量节点分别和校验矩阵H的n个列对应，上述m个校验节点分别和校验矩阵H的m个行对应。Tanner图中的循环是由互相连接在一起的顶点组成，循环以这群顶点中的一个顶点同时作为起点和终点，且只经过每个节点一次。循环的长度定义为它所包含的连线的数量，而图形的围长也可以称作图形的尺寸，定义为图中最小的循环长度，如图2中，围长为6，如图2中加黑连线所示。
5.LDPC码的编码
基于上面的描述可知，发送码字是由信息码字与生成矩阵相乘得到的，生成矩阵可由校验矩阵经过变换而得来。因此，整个LDPC码编码过程其实就是一个校验矩阵的构造过程。参见图3，图3为本申请提供的一种LDPC码的编码过程的示例。如图3所示，校验矩阵H通过高斯消元方可变成H＝[I P]；由G·HT＝0，得到生成矩阵G＝[-PT I]；信息码字c经过生成矩阵G编码得到发送码字x，即x＝c·G。其中，I表示信息比特部分，P表示校验比特部分，x为发送码字，
6.LDPC码的译码
LDPC码译码过程是通过校验位(或者称为校验码元)和信息位(或者称为信息码元)之间的校验规律在变量节点与校验节点之间不停进行消息迭代直至找到满足x·HT＝的码字，输出x即为解码后的码字。LDPC码的译码算法包括以下三大类：硬判决译码，软判决译码和混合译码。
7.WLAN场景中的LDPC编码
一些WLAN标准(例如IEEE 802.11n/ac)采用正交频分复用(orthogonal frequency division multiplexing，OFDM)技术，LDPC编码模块需要将数据比特(可称为信息比特)经编码后放入整数个OFDM符号中，而这些编码后的比特也须恰好可放入整数个LDPC码字中。执行上述步骤，发送端首先计算得到本次传输所需的最少OFDM符号数目NSYM；再根据NSYM和当前编码调制方案，计算所有OFDM符号中可存放的总编码比特数目NTCB＝NCBPS*NSYM，其中NCBPS为每个OFDM符号可存放的比特数。随后，发送端根据以上所得结果，计算当前传输所采用的LDPC码长和所需的码字数目。对于大多数的待编码数据的比特长度和编码调制方案组合，由于没有足够多的数据比特可填满LDPC码字中的数据比特部分，因此需要在生 成校验比特之前进行缩短操作。LDPC码字中的数据比特部分仅包含信息位(或者数据比特)，而不包含校验位(或者说校验比特)。
本申请中，缩短操作是指在通过LDPC编码生成校验比特之前，在码字信息的数据比特部分填入一定数目的0，编码生成校验比特之后再将这些0删除。图4为本申请实施例提供的一种LDPC编码流程中缩短操作部分的示意图。如图4所示，401表示待编码的数据比特(payload bits)；步骤(step)1为计算发送待编码的数据比特所需的LDPC码字的长度和码字数目，402示出了LDPC码字的长度和码字数目；步骤2为对待编码的数据比特进行缩短操作，403示出了包含数据比特、缩短0比特(shortening zero bits)的码字；步骤3为利用数据比特和缩短0比特，生成校验比特(parity bits)，404示出了包含数据比特、缩短0比特以及校验比特的码字；随后将这些缩短0比特删除(discard shortening bits)，405示出了仅包含数据比特和校验比特的码字。
8.由基矩阵扩展得到校验矩阵
LDPC码的基矩阵可根据需要扩展为各种码长的LDPC码的校验矩阵。LDPC码的基矩阵中仅包含0和1两种元素。本申请中，基矩阵中的0可替换为空白、“-”、“-1”、或者其他数字或符号，本申请不作限定。本申请中，由基矩阵扩展得到校验矩阵时，基矩阵中的1可扩展为非全零方阵(也可称为非全0方阵)，基矩阵中的0元素可扩展为全零方阵(也可称为全0方阵)。本申请中，全零方阵是指包括的每个元素均为0的方阵，例如大小为(27×27)的方阵。本申请中，非全零方阵是指至少包括一个非0元素的方阵，例如循环位移矩阵(circulant permutation matrix，CPM)。CPM是单位阵的循环移位。或者说，单位阵的循环移位称为CPM。后续CPM的含义均为此，后续不再赘述。本申请中，任意CPM可用一个数值和一个扩展因子共同表示。或者说，任意CPM对应一个数值和一个扩展因子。两个CPM的大小不同是指这两个CPM对应的扩展因子不同。本申请中，CPM对应的数值可称为扩展因子具体值、扩展因子值、或循环移位因子等。CPM对应的数值可称为循环移位系数。CPM对应的扩展因子表征CPM的大小，即不同大小的CPM的扩展因子不同。例如，大小为(27×27)的CPM的扩展因子为27。或者说，某个CPM的扩展因子为27，表示该CPM的大小为(27×27)。又例如，大小为(54×54)的CPM的扩展因子为54。后续CPM的扩展因子的含义均为此，后续不再赘述。需要说明，校验矩阵中的各CPM的扩展因子相同。举例来说，一个基矩阵的大小为(12×24)，利用扩展因子Z＝27扩展该基矩阵，得到校验矩阵，该校验矩阵中的每个CPM的扩展因子为Z。本申请中，CPM对应的数值(整数)表示单位阵向右循环移位的位数。图5为本申请提供的(4×4)的4种CPM的示例。如图5所示，P0表示(4×4)单位阵，P0可视为扩展因子为4且对应的数值为0的CPM，P1为扩展因子为4且对应的数值为1的CPM，P2为扩展因子为4且对应的数值为2的CPM，P3为扩展因子为4且对应的数值为3的CPM。图5为本申请实施例提供的4种CPM的示例。应理解，任意CPM均可由相应的单位阵向右循环移位得到，这里不再详述。应理解，基矩阵中的1可扩展为任意大小的CPM，基矩阵中的0可扩展为任意大小的全零方阵。后文基矩阵中的1或者0的含义或者功能与前述介绍一致，将不再赘述。
由基矩阵扩展得到校验矩阵的方式可如下：将基矩阵中的1替换为CPM，而将0替换为相应大小的全0方阵。示例性的，基矩阵中的每个元素为0或1，由该基矩阵扩展得到校验矩阵时，将该基矩阵中的每个0扩展为(Z×Z)的全零矩阵，该基矩阵中的每个1扩展为(Z×Z)的CPM，Z为CPM对应的扩展因子，不同CPM对应的数值相同或不同。因此，可由基矩阵可得到一系列LDPC码的校验矩阵。这些校验矩阵的大小和每个CPM的扩展因子可不同， 但对应或者符合同一基矩阵。
下面介绍由基矩阵扩展得到校验矩阵的一个示例。一个大小为(12×24)的基矩阵的示例如下：
参见图6，图6为本申请实施例提供的一种由大小为(12×24)的基矩阵(下文的基矩阵1)扩展得到的一个校验矩阵的示例。如图6所示，校验矩阵中的“-”表示大小为(K×K)的全零矩阵，该校验矩阵中的0表示大小为(K×K)的单位矩阵(或者称为单位阵)，该校验矩阵中的大于0的元素表示对应该元素的数值的大小为(K×K)的CPM，K表示扩展因子，换句话说，在大小为(K×K)的单位矩阵循环移位该校验矩阵中的大于0的元素的值。本申请中，校验矩阵中的“-”(表示全零矩阵)可替换为空白、“-1”、或者其他数字或符号，本申请不作限定。后文的校验矩阵中的“-”或者0的含义或者功能如前所述，将不再赘述。
以上通过一个示例，对由基矩阵到校验矩阵的扩展过程进行了介绍。应理解，可采用相同的方式对任意基矩阵进行扩展以得到所需码长的校验矩阵。本申请，若某个校验矩阵由某个基矩阵扩展得到，则可理解为该校验矩阵符合(或者说满足)该基矩阵或者该校验矩阵对应于该基矩阵。
为了提高无线传输系统的传输可靠性，LDPC码已在WLAN标准得到了广泛的应用。而新的IEEE 802.15ab标准相对于IEEE 802.15.4z标准可引入新的LDPC编码技术，以便大幅提升系统的数据传输可靠性。因此，可考虑针对下一代WLAN标准或UWB标准设计新的LDPC码，以进一步提高下一代WLAN系统或UWB系统的可靠性和系统性能。
为了提高下一代WLAN系统或UWB系统的可靠性和系统性能，本申请针对下一代WLAN系统或UWB系统提出了两类采用单个基矩阵扩展得到不同码长的校验矩阵的设计。本申请提供的采用单个基矩阵扩展得到不同码长的校验矩阵的方案，适用于中包、短包以及长包均存在的传输场景，编码复杂度较低。第一类方案是利用已有的校验矩阵对应的基矩阵扩展得到不同码长的校验矩阵。例如，基于IEEE 802.11n标准中的LDPC码的其中一个码率为1/2的校验矩阵对应的基矩阵，扩展得到不同码长的校验矩阵。第二类方案是综合考虑LDPC码的性能、译码收敛速度、译码复杂度等中的多项因素，设计了几组复杂度低且译码收敛快的LDPC码的基矩阵和相应的校验矩阵。
本申请的技术方案主要适用于无线通信系统，该无线通信系统可以遵从第三代合作伙伴计划(third generation partnership project，3GPP)的无线通信标准，也可以遵从其它无线通信标准，例如，电气电子工程师学会(institute of electrical andelectronics engineers，IEEE)的802系 列(例如，802.11，802.15，或者802.20)的无线通信标准。本申请的技术方案还可以适用于物联网(internet of things，IoT)网络、UWB系统、车联网(Vehicle to X，V2X)等无线局域网系统中。当然，本申请实施例还可以适用于其他可能的通信系统，例如，长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、第五代(5th generation，5G)通信系统,以及未来的第六代(6th generation，6G)通信系统等。
本申请实施例主要以部署WLAN系统或UWB系统，尤其是应用IEEE 802.11标准的网络为例进行说明。本领域技术人员容易理解，本申请涉及的各个方面可以扩展到采用各种标准或协议的其它网络，例如，BLUETOOTH(蓝牙),高性能无线LAN(high performance radio LAN，HIPERLAN)(一种与IEEE 802.11标准类似的无线标准，主要在欧洲使用)以及广域网(WAN)、个人区域网(personal area network,PAN)或其它现在已知或以后发展起来的网络。因此，无论使用的覆盖范围和无线接入协议如何，本申请提供的各种方面可以适用于任何合适的无线网络。
上述适用本申请的通信系统仅是举例说明，适用本申请的通信系统不限于此，在此统一说明，以下不再赘述。
参阅图7，图7为本申请提供的技术方案适用的一种无线通信系统的示例。该通信系统包括接入点(access point，AP)，一个或多个STA(仅示出了STA1和STA2)。其中，接入点和STA均支持WLAN协议，该WLAN协议可以包括IEEE 802.11be(或称为Wi-Fi 7，EHT协议)，还可以包括IEEE 802.15ab，IEEE802.11ax，IEEE 802.11ac等协议。当然，随着通信技术的不断演进和发展，该WLAN协议还可以包括IEEE802.11be的下一代协议等。以WLAN为例，该实现本申请方法的装置可以是WLAN中的接入点或STA，或者是，安装在接入点或STA中的芯片或处理系统。
接入点是一种具有无线通信功能的装置，支持采用WLAN协议进行通信，具有与WLAN网络中其他设备(比如站点或其他接入点)通信的功能。当然，还可以具有与其他设备通信的功能。在WLAN系统中，包括一个或多个接入点(access point，AP)类的站点和一个或多个非接入点类的站点(none access point station，non-AP STA)。为便于描述，本文将接入点类型的站点称为接入点(AP)，非接入点类的站点称为站点(STA)。
接入点可以为一个整机设备，还可以是安装在整机设备中的芯片或处理系统等。安装这些芯片或处理系统的设备可以在芯片或处理系统(即AP)的控制下，实现本申请实施例的方法和功能。本申请实施例中的AP是为站点(Station，STA)提供服务的装置，可以支持802.11系列协议，例如802.15ab、802.11ac、802.11n、802.11g、802.11b及802.11a、802.11be、Wi-Fi8或其下一代等。例如，AP可以为通信服务器、路由器、交换机、网桥等通信实体。AP可以包括宏基站、微基站(也称为小站)、微微基站、毫微微基站、中继站、接入点、gNB、传输接收点(transmission reception point，TRP)、演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)、WiFi接入点(access point，AP)、接入回传一体化(integrated access and backhaul，IAB)等。当然AP还可以为这些各种形式的设备中的芯片和处理系统，从而实现本申请实施例的方法和功能。
站点是一种具有无线通信功能的装置，支持采用WLAN协议进行通信，具有与WLAN 网络中的其他站点或接入点通信的能力。例如，STA是允许用户与AP通信进而与WLAN通信的任何通信装置，该通信装置可以为一个整机设备，还可以是安装在整机设备中的芯片或处理系统等。安装这些芯片或处理系统的设备可以在芯片或处理系统(即站点)的控制下，实现本申请实施例的方法和功能。STA可包括手机(mobile phone)、移动台(mobile station，MS)、平板电脑(pad)、带无线收发功能的电脑(例如笔记本电脑)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端、用户单元(subscriber unit)、蜂窝电话(cellular phone)、无线数据卡、个人数字助理(personal digital assistant，PDA)电脑、平板型电脑、膝上型电脑(laptop computer)、机器类型通信(machine type communication,MTC)终端等。站台可包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。可选的，站台可以是具有无线通信功能的手持设备(handset)、车载设备、可穿戴设备或物联网、车联网中的终端、5G以及5G之后演进的通信系统中的任意形态的终端等，本申请对此并不限定。站点可支持802.11系列协议，例如802.15ab、802.11ac、802.11n、802.11g、802.11b、802.11a、802.11be、Wi-Fi 8或其下一代等多种WLAN标准。
下面结合附图结合本申请提供的LDPC码的编码方法。
图8为本申请提供的一种LDPC码的编码方法交互流程图。如图8所示，该方法包括：
801、发送端根据校验矩阵，对第一比特序列进行LDPC编码，得到第一数据包。
发送端可以是站点，也可以是接入点。本申请实施例中的发送端可视为编码设备。上述校验矩阵包括两种或两种以上符合第一基矩阵的校验矩阵。上述校验矩阵包括的两种或两种以上符合第一基矩阵的校验矩阵中的任意两个校验矩阵的码长不同。下文以校验矩阵包括第一校验矩阵和第二校验矩阵为例进行描述。上述第一校验矩阵和上述第二校验矩阵均符合第一基矩阵。上述第一校验矩阵的码长和上述第二校验矩阵的码长不同。
步骤801一种可能的实现方式如下：根据第一比特序列与第一校验矩阵对应的生成矩阵，得到第一信息；基于该第一信息，得到第一数据包。步骤801另一种可能的实现方式如下：根据第一比特序列与第二校验矩阵对应的生成矩阵，得到第一信息；基于该第一信息，得到第一数据包。可理解，发送端可根据需要或预设规则采用符合同一基矩阵的多个校验矩阵中的任一校验矩阵对待编码的比特序列进行LDPC编码。具体过程可参阅上文描述的LDPC码的编码以及WLAN中的LDPC编码。本申请不对根据校验矩阵(例如第一校验矩阵或第二校验矩阵)对第一比特序列进行LDPC编码的具体方式作限定。由于基于编码后的信息，例如第一信息，得到相应的数据包是本领域的惯用技术手段，故这里不再详述。
802、发送端发送第一数据包。
具体的，上述发送步骤可以包括但不限于：发送端根据LDPC编码后的比特(即第一数据包)进行流分析(strean parser)，星座映射(Constellation mapper)，LDPC载波映射，或者可能的包括傅里叶逆变换(inverse discrete fourier transform，IDFT)等等处理，以便于在信道上发送出去。
相应的，接收端接收来自发送端的承载前述编码后的第一比特序列的信号(为描述方便，也可以称为第一数据包)。可选的，发送端为站点，接收端为接入点。可选的，发送端为接入点，接收端为站点。
步骤802一种可能的实现方式如下：发送端广播第一数据包。接收端接收来自发送端的第一信道接收序列(对应于第一数据包)。第一信道接收序列对应于接收端通过第一信道接收到的第一信号，即发送端发送的第一数据包经信道传输被接收端接收到的信号。
步骤802一种可能的实现方式如下：发送端向接收端(对应于单播方式)发送第一数据包。接收端接收来自发送端的第一信道接收序列(对应于第一数据包)。
803、接收端确定第一信道接收序列对应的第一对数似然比(log likelihood rate,LLR)序列，并根据校验矩阵，对第一LLR序列进行译码，得到第一译码结果。
应理解，若发送端根据第一校验矩阵对第一比特序列进行LDPC编码，则接收端根据第一校验矩阵对第一LLR序列进行译码；若发送端根据第二校验矩阵对第一比特序列进行LDPC编码，则接收端根据第二校验矩阵对第一LLR序列进行译码。接收端可根据来自发送端的控制信息获知对第一LLR序列进行译码采用的校验矩阵。接收端还可通过其他方式获知对第一LLR序列进行译码采用的校验矩阵，本申请不作限定。
接收端可采用硬判决译码、软判决译码、混合译码中的任一种，根据第一校验矩阵，对第一LLR序列进行译码，这里不作限定。
804、接收端若译码成功，则输出第一译码结果。
步骤804是可选的，而非必要的。输出第一译码结果可以接收端通过输出设备，例如显示器、显示屏、音频设备等，输出第一译码结果。可选的，如果接收端译码错误(或者说译码失败)，则接收端向发送端发送重传指示信息，以请求发送端重传。此外，如果译码失败，接收端可保存第一LLR序列，以和后续接收到的重传的LLR序列合并译码。
本申请实施例中，第一校验矩阵和第二校验矩阵均符合第一基矩阵。通过第一基矩阵扩展得到第一校验矩阵和第二校验矩阵，能够降低编码的复杂度。
图9为本申请提供的另一种LDPC码的编码方法交互流程图。如图9所示，该方法包括：
901、发送端根据第一校验矩阵，对第一比特序列进行LDPC编码，得到第一数据包。
步骤901可参阅步骤801。
902、发送端根据第二校验矩阵，对第二比特序列进行LDPC编码，得到第二数据包。
步骤902可参阅步骤801。步骤901和步骤902的先后顺序不作限定。第一校验矩阵的码长和第二校验矩阵的码长不同。上述第一校验矩阵和上述第二校验矩阵均符合第一基矩阵。或者说，上述第一校验矩阵和上述第二校验矩阵均根据基矩阵或上述基矩阵的子矩阵扩展得到。本申请的主要原理是基于同一基矩阵扩展得到不同码长的校验矩阵，以便降低编码的复杂度。下文再详述基于同一个基矩阵扩展得到不同码长的校验矩阵的实现方式。本申请中，不对第一校验矩阵和第二校验矩阵的码率做限定。本申请中，LDPC码的校验矩阵均可通过缩短或打孔得到其他码率，缩短操作可参阅图4。
上述第一数据包的类型和上述第二数据包的类型可不同。第一数据包的类型和第二数据包的类型可以为短包、中包、长包中的任意两种。例如，第一数据包的类型为长包，第二数据包的类型为短包。又例如，第一数据包的类型为中包，第二数据包的类型为长包。应理解，短包的长度小于中包，中包的长度小于长包。上述第一比特序列的长度和上述第二比特序列的长度不同。上述第一比特序列和上述第二比特序列需要采用不同码长的校验矩阵进行LDPC编码。或者说，上述第一比特序列和上述第二比特序列需要通过不同类型的数据包发送。举例来说，第一比特序列包括20比特(bites)，第二比特序列包括1500比特，发送端根据码长为648比特的第一校验矩阵对该第一比特序列进行LDPC编码，得到第一数据包；发送端根据码长为1944比特的第二校验矩阵对该第二比特序列进行LDPC编码，得到第二数据 包；第一数据包为短包，第二数据包为长包。通过该举例可知，发送端发送不同类型的数据包时，需要根据不同码长的校验矩阵对待编码的比特序列进行LDPC编码。
在一种可能的实现方式中，上述第一校验矩阵和上述第二校验矩阵通过相同的硬件电路扩展上述第一基矩阵得到，上述第一校验矩阵和上述第二校验矩阵对应不同的扩展方式或扩展参数。也就是说，发送端可通过同一硬件电路扩展第一基矩阵得到两种或两种以上码长的校验矩阵。或者说，发送端通过改变或者调整某个硬件电路采用的扩展方式或扩展参数，可根据第一基矩阵扩展得到两种或两种以上码长的校验矩阵。示例性的，发送端中的第一硬件电路用于基于第一基矩阵扩展得到多个校验矩阵；当该第一硬件电路采用第一扩展方式(或第一扩展参数)时，根据该第一基矩阵扩展得到第一校验矩阵；当该第一硬件电路采用第二扩展方式(或第二扩展参数)时，根据该第一基矩阵扩展得到第二校验矩阵。在本申请提供的可能的实现方式中，发送端可通过同一硬件电路扩展第一基矩阵得到两种或两种以上码长的校验矩阵，编码的复杂度较低。
903、发送端发送第一数据包以及第二数据包。
可选的，发送端独立发送第一数据包和第二数据包，即通过不同的信号或信道发送第一数据包和第二数据包。或者，发送端先后发送第一数据包和第二数据包。
相应的，接收端接收来自发送端的承载前述编码后的第一比特序列的信号(为描述方便，也可以称为第一数据包)，以及承载前述编码后的第二比特序列的信号(为描述方便，也可以称为第二数据包)。可选的，发送端为站点，接收端为接入点。可选的，发送端为接入点，接收端为站点。
步骤903一种可能的实现方式如下：发送端广播第一数据包和第二数据包。接收端接收来自发送端的第一信道接收序列(对应于第一数据包)以及第二信道接收序列(对应于第二数据包)。第一信道接收序列对应于接收端通过第一信道接收到的第一信号，即发送端发送的第一数据包经信道传输被接收端接收到的信号。第二信道接收序列对应于接收端通过第二信道接收到的第二信号，即发送端发送的第二数据包经信道传输被接收端接收到的信号。
步骤903一种可能的实现方式如下：发送端向接收端(对应于单播方式)发送第一数据包和第二数据包。接收端接收来自发送端的第一信道接收序列(对应于第一数据包)和第二信道接收序列(对应于第二数据包)。
904、接收端确定第一信道接收序列对应的第一LLR序列，并根据第一校验矩阵，对第一LLR序列进行译码，得到第一译码结果。
905、接收端若译码成功，则输出第一译码结果。
步骤905是可选的，而非必要的。步骤905可参阅步骤804。
906、接收端确定第二信道接收序列对应的第二LLR序列，并根据第二校验矩阵，对第二LLR序列进行译码，得到第二译码结果。
907、接收端若译码成功，则输出第二译码结果。
步骤907是可选的，而非必要的。步骤907可参阅步骤804。
本申请实施例中，第一校验矩阵和第二校验矩阵均符合第一基矩阵。发送端通过采用符合第一基矩阵的不同码长的校验矩阵进行LDPC编码，能够降低编码的复杂度。
图10为本申请实施例提供的另一种LDPC码的编码方法交互流程图。图10中的方法交互流程是图9描述的方法的一种可能的实现方式。在该实现方式中，发送端根据待编码的比特序列的长度，基于第一基矩阵扩展得到所需码长的校验矩阵，适用于发送不同长度的数据包，并降低编码的复杂度。
1001、发送端在待编码的第一比特序列的长度位于第一区间的情况下，根据第一基矩阵扩展得到第一校验矩阵。
第一区间可以是根据需要配置的一个区间，本申请不作限定。第一区间可以是小于等于40字节(bytes)。当待编码的任意比特序列(例如第一比特序列)的长度位于第一区间时，发送端需要采用第一码长的第一校验矩阵对该比特序列进行LDPC编码。该第一码长可以是320比特、640比特、648比特等。待编码的第一比特序列的长度位于第一区间可理解为根据第一基矩阵扩展得到第一校验矩阵需要满足的一种条件。或者说，待编码的第一比特序列的长度位于第一区间为触发发送端根据第一基矩阵扩展得到第一校验矩阵的条件。应理解，发送端还可以在满足其他条件时，根据第一基矩阵扩展得到第一校验矩阵。例如，发送端在确定需要采用第一码长的校验矩阵进行编码时，根据第一基矩阵扩展得到码长为第一码长的第一校验矩阵。
1002、发送端根据第一校验矩阵，对第一比特序列进行LDPC编码，得到第一数据包。
1003、发送端发送第一数据包。
相应的，接收端接收来自发送端的第一信道接收序列(对应于第一数据包)。步骤1003可参阅步骤802。
1004、接收端确定第一信道接收序列对应的第一LLR序列，并根据第一校验矩阵，对第一LLR序列进行译码，得到第一译码结果。
1005、接收端若译码成功，则输出第一译码结果。
步骤1005是可选的，而非必要的。步骤1005可参阅步骤804。
1006、发送端在待编码的第二比特序列的长度位于第二区间的情况下，根据第一基矩阵扩展得到第二校验矩阵。
当待编码的任意比特序列(例如第二比特序列)的长度位于第二区间时，发送端需要采用第二码长的第二校验矩阵对该比特序列进行LDPC编码。该第二码长可以是1280比特、1296比特、1944比特、2560比特等，本申请不作限定。
第二区间和第一区间不重叠。或者说，第一区间和第二区间的交集为空集。第一区间和第二区间均为连续的区间。例如，第一区间为(0,第一值]，第二区间为(第二值，第三值]，第二值大于第一值，第三值大于第二值，第一值大于0。又例如，第一区间为(0,第一值]，第二区间为(第一值，第三值]，第二值大于第一值，第一值大于0。第二区间可以是大于40bybes。应理解，发送端可根据实际需要相应的设置第一区间和第二区间，本申请不作限定。
在一种可能的实现方式中，上述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，上述第一校验矩阵中的CPM的扩展因子为Z1，上述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，上述第二校验矩阵中的CPM的扩展因子为Z2，上述Z、上述Z1、上述Z2均为大于0的整数，上述Z1大于或等于上述Z，上述Z2小于上述Z。第一位置可以是第一校验矩阵中的任意一个位置。第一校验矩阵和第二校验矩阵中相同位置的元素一一对应。也就是说，若第一校验矩阵中的任意一个位置的CPM的扩展因子具体值为b，则第二校验矩阵的相应位置的CPM的扩展因子具体值为(b mod Z)。mod表示取模运算或取余运算。可选的，Z为27的整倍数，例如27、54、81等。示例性的，上述第一基矩阵对应于原校验矩阵，上述原校验矩阵中的CPM的扩展因子为Z，上述原校验矩阵的第一位置的CPM的扩展因子具体值为b，上述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，上述第一校验矩阵中的CPM的扩展因子为Z1，上述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，上述第二校验矩阵中的CPM的扩展因子为Z2，上述Z、上述 Z1、上述Z2均为大于0的整数，上述Z1大于或等于上述Z，上述Z2小于上述Z。可选的，Z为27的整倍数，例如27、54、81等。可选的，上述校验矩阵还包括上述原校验矩阵。基矩阵对应的原校验矩阵可以是图6所示的矩阵，也可以是码率为1/2、码长为1296、扩展因子为54的WLAN LDPC校验矩阵，还可以是码率为1/2、码长为1944、扩展因子为81的WLAN LDPC校验矩阵，还可以是其他校验矩阵，本申请不作限定。在该实现方式中，第一校验矩阵中的第一位置的循环位移矩阵CPM的扩展因子具体值为b，第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)；能够快速地扩展得到所需的校验矩阵。
在一种可能的实现方式中，上述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，上述第一校验矩阵中的CPM的扩展因子为Z3，上述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，上述第二校验矩阵中的CPM的扩展因子为Z4，上述Z、上述Z3、上述Z4均为大于0的整数，上述Z3小于上述Z，上述Z4大于或等于上述Z。需要注意，需要保证第二校验矩阵中的各元素均小于或等于Z4。第一位置可以是第一校验矩阵中的任意一个位置。可选的，Z和Z4均为27的整倍数，例如Z为27，Z4为54、81等。第一校验矩阵和第二校验矩阵中相同位置的元素一一对应。可理解，若第一校验矩阵中的任意一个位置的CPM的扩展因子具体值为b，则第二校验矩阵的相应位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个。需要注意，第二校验矩阵中的每个位置的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个。例如，第一校验矩阵的第一位置的CPM的扩展因子具体值为b，第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b+Z)，第一校验矩阵的第三位置的CPM的扩展因子具体值为a，第二校验矩阵中的第三位置的CPM的扩展因子具体值为(a+2Z)。在该实现方式中，能够快速地扩展得到所需的校验矩阵。
在一种可能的实现方式中，上述第一基矩阵对应于原校验矩阵，上述原校验矩阵中的CPM的扩展因子为Z，上述原校验矩阵的第一位置的CPM的扩展因子具体值为b，上述第一校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，上述第一校验矩阵中的CPM的扩展因子为Z3，上述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，上述第二校验矩阵中的CPM的扩展因子为Z4，上述Z、上述Z3、上述Z4均为大于0的整数，上述Z3小于上述Z，上述Z4大于或等于上述Z。需要注意，需要保证第一校验矩阵中的各元素均小于或等于Z4。可选的，Z和Z4均为27的整倍数，例如Z为27，Z4为54、81等。在该实现方式中，能够快速地扩展得到所需的校验矩阵。
1007、发送端根据第二校验矩阵，对第二比特序列进行LDPC编码，得到第二数据包。
1008、发送端发送第二数据包。
相应的，接收端接收来自发送端的第二信道接收序列(对应于第二数据包)。步骤1008可参阅步骤802。
1009、接收端确定第二信道接收序列对应的第二LLR序列，并根据第二校验矩阵，对第二LLR序列进行译码，得到第二译码结果。
1010、接收端若译码成功，则输出第二译码结果。
步骤1010是可选的，而非必要的。步骤1010可参阅步骤804。
在实际发送数据中，发送端并不一定会在所有的区间上都生成相应码长的校验矩阵。上述第一区间和第二区间仅为示例。应理解，只要发送端根据比特序列的长度生成相应码长的校验矩阵就属于本申请的保护范围，本申请不限定在所有区间上都生成相应码长的校验矩阵。
图10的方法流程描述了发送端在待编码的第一比特序列的长度位于第一区间的情况下， 根据第一基矩阵扩展得到第一校验矩阵，以及在待编码的第二比特序列的长度位于第二区间的情况下，根据第一基矩阵扩展得到第二校验矩阵。应理解，图10仅为根据第一基矩阵扩展得到两种校验矩阵(即第一校验矩阵和第二校验矩阵)的示例，发送端可根据第一基矩阵扩展得到三种或三种以上校验矩阵，每种校验矩阵可对应一个区间。
示例性的，发送端在待编码的比特序列的长度位于第一区间的情况下，根据第一基矩阵扩展得到第一校验矩阵；发送端在待编码的比特序列的长度位于第二区间的情况下，根据第一基矩阵扩展得到第二校验矩阵；发送端在待编码的比特序列的长度位于第三区间的情况下，根据第一基矩阵扩展得到第三校验矩阵；其中，第一校验矩阵、第二校验矩阵、第三校验矩阵中的任意两个的码长不同，第一区间、第二区间、第三区间中的任意两个不重叠。例如，第一区间为(0,第一值]，第二区间为(第二值，第三值]，第三区间为(第三值，第四值]，第一校验矩阵的码长为648比特，第二校验矩阵的码长为1296比特，第三校验矩阵的码长为1944比特。第一值大于0，第二值大于第一值，第三值大于第二值，第四值大于第三值。在实际应用中，可根据实际需要设置第一区间、第二区间以及第三区间，本申请不作限定。复用图6，图6示出了一种第一校验矩阵的示例。参阅图6，第一校验矩阵的码长N＝648(比特)，码率R＝1/2，扩展因子Z＝27。在图6中，0表示(27×27)的单位阵，大于0的元素表示(27×27)的CPM，“-”表示(27×27)的全零矩阵，例如22表示扩展因子具体值为22的(27×27)的CPM。
示例性的，发送端在待编码的比特序列的长度位于第一区间的情况下，根据第一基矩阵扩展得到第一校验矩阵；发送端在待编码的比特序列的长度位于第二区间的情况下，根据第一基矩阵扩展得到第二校验矩阵；发送端在待编码的比特序列的长度位于第三区间的情况下，根据第一基矩阵扩展得到第三校验矩阵；发送端在待编码的比特序列的长度位于第四区间的情况下，根据第一基矩阵扩展得到第四校验矩阵；其中，第一校验矩阵、第二校验矩阵、第三校验矩阵、第四校验矩阵中的任意两个的码长不同，第一区间、第二区间、第三区间、第四区间中的任意两个不重叠。例如，第一区间为(0,第一值]，第二区间为(第二值，第三值]，第三区间为(第三值，第四值]，第四区间为(第四值，第五值]，第一校验矩阵的码长为320比特，第二校验矩阵的码长为640比特，第三校验矩阵的码长为1280比特，第四校验矩阵的码长为2560比特。第一值大于0，第二值大于第一值，第三值大于第二值，第四值大于第三值，第五值大于第四值。在实际应用中，可根据实际需要设置第一区间、第二区间、第三区间以及第四区间，本申请不作限定。
图11为本申请实施例提供的一种表征第一基矩阵的矩阵以及根据该第一基矩阵扩展得到的四种校验矩阵的扩展因子具体值矩阵的示例。本申请中，表征第一基矩阵的矩阵可视为第一基矩阵，未直接写出第一基矩阵的原因是该第一基矩阵为(16×32)的矩阵，难以展示。同理，本申请也未直接示出(16×32)的校验矩阵，而是示出校验矩阵的扩展因子具体值矩阵。由于难以直接展示(16×32)的校验矩阵，并且校验矩阵的扩展因子可表示该校验矩阵，因此校验矩阵的扩展因子具体值矩阵可视为校验矩阵。参阅图11，每个矩形框中包括一个矩阵，图11所示的五个矩形框从左向右的顺序依次包括表征第一基矩阵的矩阵、第四校验矩阵的扩展因子具体值矩阵、第三校验矩阵的扩展因子具体值矩阵、第二校验矩阵的扩展因子具体值矩阵、第一校验矩阵的扩展因子具体值矩阵。表征第一基矩阵的矩阵可视为该第一基矩阵。或者说，第一基矩阵通过表征第一基矩阵的矩阵来表示。本申请实施例中，第一基矩阵中仅包括0和1两种元素。表征第一基矩阵的矩阵可示出该第一基矩阵的各行中的1的位置，因此可表征该第一基矩阵。或者说，表征第一基矩阵的矩阵的第i行的元素与第一基矩阵的第i 行中的元素1的位置一一对应，第i行为任一行。可选的，表征第一基矩阵的矩阵的第i行的任一元素为u，表明第一基矩阵的第i行的第(u+1)列的元素为1，第i行为任一行，u为0至31中的整数。参阅图11，表征第一基矩阵的矩阵的第一行的元素分别为：0、2、4、6、12、14、17，表明第一基矩阵的第一行的第1列、第3列、第5列、第7列、第13列、第15列、第18列的元素为1，第一基矩阵的第一行的其他列的元素均为0；表征第一基矩阵的矩阵的第二行的元素分别为：1、2、3、9、12、17、18，表明第一基矩阵的第二行的第2列、第3列、第4列、第10列、第13列、第18列、19列的元素为1，第一基矩阵的第二行的其他列的元素均为0；以此类推。可见，表征第一基矩阵的矩阵可视为第一基矩阵本身。
参阅图11，第一校验矩阵中的CPM的扩展因子Z＝10，码长N＝320；第二校验矩阵中的CPM的扩展因子Z＝20，码长N＝640；第三校验矩阵中的CPM的扩展因子Z＝40，码长N＝1280；第四校验矩阵中的CPM的扩展因子Z＝80，码长N＝2560；第一校验矩阵、第二校验矩阵、第三校验矩阵以及第四校验矩阵均符号第一基矩阵。下面以第一校验矩阵为例来说明为何校验矩阵的扩展因子具体值矩阵可视为校验矩阵。表征第一基矩阵的矩阵的第j行的第二位置(任意位置)的元素为p，第一具体值矩阵(即第一校验矩阵的扩展因子具体值矩阵)的第j行的第二位置的元素为q，第一校验矩阵的第j行的第(p+1)列的元素为q。第一校验矩阵中的0表示大小为(10×10)的单位阵，第一校验矩阵中的大于0的元素表示大小为(10×10)的CPM的扩展因子具体值。图12为本申请实施例提供的一种第一校验矩阵的示例。图12所示的第一校验矩阵为图11中的第一校验矩阵的扩展因子具体值矩阵表征的校验矩阵。或者说，展开图11中的第一校验矩阵的扩展因子具体值矩阵可得到图12所示的第一校验矩阵。图12中，0、1、…、31依次对应于第一校验矩阵的第一列至第三十二列，0、1、…、15依次对应于第一校验矩阵的第一行至第十六行，第二列中的元素表示相应行的行重，第二行中的元素表示相应列的列重。图12中，矩阵左边(16×16)部分对应信息部分，而右侧(16×16)的矩阵部分为校验部分。参阅图11和图12，图11中最左边的矩形框包括表征第一基矩阵的矩阵(下文可称为矩阵1)，图11中最右边的矩形框包括第一具体值矩阵，矩阵1和第一具体值矩阵的大小相同，矩阵1和第一具体值矩阵中相同位置的元素一一对应；由上段的描述可知，(16×32)矩阵1的第一行的元素分别为：0、2、4、6、12、14、17，表明矩阵1的第一行的第1列、第3列、第5列、第7列、第13列、第15列、第18列的元素为1，则矩阵1的第一行第一列的元素为0，表明第一具体值矩阵的第一行第一列有值，再参见第一具体值矩阵中的元素为5，可知第一具体值矩阵的第一行第一列的元素为5，则表示第一校验矩阵的第一行第一列的元素为5，即第一校验矩阵的第一行第一列的位置上为大小(10×10)的CPM循环移位5；矩阵1的第一行第二列的元素为2，表明第一具体值矩阵的第一行第二列有值，再参见第一具体值矩阵中的元素为5，可知第一具体值矩阵的第一行第二列的元素为5，则表示第一校验矩阵的第一行第三列的元素为5，即第一校验矩阵的第一行第三列的位置上为大小(10×10)的CPM循环移位5；矩阵1的第一行第三列的元素为4，表明第一具体值矩阵的第一行第三列有值，再参见第一具体值矩阵中的元素为4，可知第一具体值矩阵的第一行第三列为4，则表示第一校验矩阵的第一行第五列的元素为4；依次类推。应理解，任意校验矩阵的扩展因子具体值矩阵结合该校验矩阵符合的基矩阵可表征该校验矩阵。可见，第一具体值矩阵可视为第一校验矩阵本身。同理，任意校验矩阵的扩展因子具体值矩阵可视为该校验矩阵。
图13为本申请实施例提供的另一种表征第一基矩阵的矩阵以及根据该第一基矩阵扩展得到的四种校验矩阵的扩展因子具体值矩阵的示例。参阅图13，每个矩形框中包括一个矩阵， 图13所示的五个矩形框从左向右的顺序依次包括表征第一基矩阵的矩阵、第四校验矩阵的扩展因子具体值矩阵、第三校验矩阵的扩展因子具体值矩阵、第二校验矩阵的扩展因子具体值矩阵、第一校验矩阵的扩展因子具体值矩阵。表征第一基矩阵的矩阵可视为第一基矩阵。第四校验矩阵的扩展因子具体值矩阵结合表征第一基矩阵的矩阵可表征第四校验矩阵。第三校验矩阵的扩展因子具体值矩阵结合表征第一基矩阵的矩阵可表征第三校验矩阵。第二校验矩阵的扩展因子具体值矩阵结合表征第一基矩阵的矩阵可表征第二校验矩阵。第一校验矩阵的扩展因子具体值矩阵结合表征第一基矩阵的矩阵可表征第一校验矩阵。
本申请实施例中，发送端根据待编码的比特序列的长度，基于第一基矩阵扩展得到所需码长的校验矩阵，适用于发送不同长度的数据包，并降低编码的复杂度。
以上对本申请提供的LDPC编码的方法进行了详细说明。下面着重介绍本申请提供的基矩阵，以及由这些基矩阵扩展的一些校验矩阵的示例。
本申请提供的基矩阵可根据需要扩展为各种码长的LDPC码的校验矩阵。如前文上述将基矩阵中的1替换为各种循环因子的CPM以及将0替换为相应大小的全0方阵，就能得到各种码长的LDPC码的校验矩阵。也就是说，由一个基矩阵可得到多个LDPC码的校验矩阵，这些校验矩阵的大小和每个CPM的扩展因子可不同，但对应同一基矩阵。
需要注意，本申请提供的基矩阵的各种行列置换所得到的基矩阵与本申请提供的基矩阵等效。也就是说，对本申请提供的基矩阵进行行列置换所得到的基矩阵同样属于本申请保护的基矩阵。基矩阵的各种行列置换是指基矩阵中的一个或多个元素替换为其他元素。也就是说，基矩阵中的一个或多个元素替换为其他元素之后与该基矩阵等效。或者说，基矩阵中的一个或多个元素替换为其他元素同样可视为该基矩阵。本申请中，基矩阵的行列置换可包括以下任一项：基矩阵的一行中的一个或多个元素替换为其他元素、基矩阵的一列中的一个或多个元素替换为其他元素、基矩阵中的位于不同行的多个元素替换为其他元素、基矩阵中的位于不同列的多个元素替换为其他元素、基矩阵中的多行的位置改变、基矩阵中的多列的位置改变，例如基矩阵中的两列的位置互换。一个元素替换为其他元素可理解为该元素替换为与该元素不同的任意元素。例如，基矩阵中的一个或多个元素0替换为元素1。又例如，基矩阵中的一个或多个元素1替换为元素。
本申请提供了两类采用单个基矩阵扩展得到不同码长的校验矩阵的设计。第一类方案是利用已有的校验矩阵对应的基矩阵扩展得到不同码长的校验矩阵。例如，基于IEEE 802.11n标准中的LDPC码的其中一个码率为1/2的校验矩阵对应的基矩阵，扩展得到不同码长的校验矩阵。第二类方案是综合考虑LDPC码的性能、译码收敛速度、译码复杂度等中的多项因素，设计了几组复杂度低且译码收敛快的LDPC码的基矩阵和相应的校验矩阵。
本申请提供的第一类设计是直接从已有的一个校验矩阵符合的基矩阵出发，通过采用不同扩展因子Z扩展该基矩阵，从而得到基于该基矩阵的多个校验矩阵。以图6所示R＝1/2，N＝648，Z＝27的WLAN LDPC码的校验矩阵为例，其符合的基矩阵为将该校验矩阵中的非“-”均替换为1，将该校验矩阵中的“-”均替换为0，得到相应(12×24)的矩阵。对该基矩阵以Z＝27进行扩展，则可得到扩展后(324×648)的校验矩阵，基矩阵中的每个非零项对应校验矩阵中的一个扩展因子具体值。
下面示出了本申请提供的一些第一基矩阵的示例。
基矩阵1：

图6示出了根据基矩阵1扩展得到的一个校验矩阵的示例。
基矩阵2：
图14为本申请提供的一种基于基矩阵2扩展得到的校验矩阵的示例。图14中，“-”表示(54×54)的全零矩阵，0表示(54×54)的单位矩阵，大于0的元素表示(54×54)的CPM的扩展因子具体值。
基矩阵3：
图15为本申请提供的一种基于基矩阵2扩展得到的校验矩阵的示例。图15中，“-”表示 (81×81)的全零矩阵，0表示(81×81)的单位矩阵，大于0的元素表示(81×81)的CPM的扩展因子具体值。
前述基矩阵1、基矩阵2、基矩阵3为三种已有的校验矩阵对应的基矩阵。本申请，第一基矩阵可以是任意已有的校验矩阵符合的基矩阵，这里不再一一例举。
表征基矩阵4的矩阵10：
矩阵10可表征(12×32)的基矩阵4。前文已描述了表征第一基矩阵的矩阵可视为第一基矩阵。同理，表征基矩阵4的矩阵10可视为基矩阵4，这里不再详述。
基于基矩阵4扩展的校验矩阵41对应的扩展因子具体值矩阵41：
扩展因子具体值矩阵41表征校验矩阵41。前文已描述了任意校验矩阵的扩展因子具体 值矩阵可视为该校验矩阵。同理，扩展因子具体值矩阵41可视为校验矩阵41，这里不再详述。
基于基矩阵4扩展的校验矩阵42对应的扩展因子具体值矩阵42：
扩展因子具体值矩阵42表征校验矩阵42。
基于基矩阵4扩展的校验矩阵43对应的扩展因子具体值矩阵43：
扩展因子具体值矩阵43表征校验矩阵43。
基于基矩阵4扩展的校验矩阵44对应的扩展因子具体值矩阵44：

扩展因子具体值矩阵44表征校验矩阵44。
表征基矩阵5的矩阵20：
矩阵20可表征(12×32)的基矩阵5。前文已描述了表征第一基矩阵的矩阵可视为第一基矩阵。同理，表征基矩阵5的矩阵20可视为基矩阵5，这里不再详述。
基于基矩阵5扩展的校验矩阵51对应的扩展因子具体值矩阵51：

扩展因子具体值矩阵51表征校验矩阵51。
基于基矩阵5扩展的校验矩阵52对应的扩展因子具体值矩阵52：
扩展因子具体值矩阵52表征校验矩阵52。
基于基矩阵5扩展的校验矩阵53对应的扩展因子具体值矩阵53：

扩展因子具体值矩阵53表征校验矩阵53。
基于基矩阵5扩展的校验矩阵54对应的扩展因子具体值矩阵54：
扩展因子具体值矩阵51表征校验矩阵54。
基矩阵1至基矩阵5仅为本申请提供的第一基矩阵的一些示例，而不是全部的举例。应理解，对本申请提供的基矩阵进行行列置换所得到的基矩阵同样属于本申请保护的基矩阵。同理，上述示出的由基矩阵扩展得到的校验矩阵也仅是部分示例，而不是全部的示例。需要注意，本申请提供的第一基矩阵可包括上述基矩阵1至基矩阵3中的任一基矩阵的H行或M列，上述H为1至12中的整数，上述M为1至24中的整数。H行可以是连续的，也可以是不连续的。M列可以是连续的，也可以是不连续的。本申请提供的第一基矩阵可包括上述基矩阵4或基矩阵5中的L行或F列。L为1至12中的整数，上述F为1至32中的整数。L行可以是连续的，也可以是不连续的。F列可以是连续的，也可以是不连续的。也就是说，第一基矩阵可包括基矩阵1至基矩阵5中的任一基矩阵的部分行或部分列。同理，本申请提供的校验矩阵可包括上述校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44、校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54中的任一校验矩阵的部分行或部分列。本申请不仅保护提供的整个基矩阵和校验矩阵，还保护基矩阵中的部分行和部分列，以及校验矩阵中的部分行和部分列。
下面介绍基于同一个基矩阵扩展得到不同码长的校验矩阵可能的实现方式。
方式一
发送端基于第一基矩阵扩展得到校验矩阵0(上文的原校验矩阵)，校验矩阵0的扩展因子为Z，例如Z＝27；若需要得到扩展因子为Z1(大于或等于Z)的校验矩阵1，将校验矩阵 0中的扩展因子具体值作为校验矩阵1中的相应位置的扩展因子具体值；若需要得到扩展因子为Z2(小于Z)的校验矩阵2，将校验矩阵0中的扩展因子具体值取模Z运算得到的值作为校验矩阵2中的相应位置的扩展因子具体值。校验矩阵1可以为前述第一校验矩阵，校验矩阵2可以为前述第二校验矩阵。校验矩阵1和校验矩阵2均符合第一基矩阵。校验矩阵1和校验矩阵2均可视为基于第一基矩阵扩展得到的校验矩阵。本申请中，基于同一个基矩阵扩展得到的多个校验矩阵中位置相同的元素一一对应。举例来说，发送端基于第一基矩阵扩展得到校验矩阵0，例如图6所示的矩阵，校验矩阵0中的每个元素为一个(Z×Z)的矩阵，将校验矩阵0中的扩展因子具体值作为校验矩阵1中的相应位置的扩展因子具体值；校验矩阵1与校验矩阵0的区别在于，校验矩阵1中的每个元素为一个(Z1×Z1)的矩阵，Z1大于Z。在该举例中，图6所示的矩阵可表示校验矩阵1与校验矩阵0。又举例来说，发送端基于第一基矩阵扩展得到校验矩阵0，例如图6所示的矩阵，校验矩阵0中的每个元素为一个(Z×Z)的矩阵，将校验矩阵0中的扩展因子具体值取模Z运算得到的值作为校验矩阵2中的相应位置的扩展因子具体值，例如校验矩阵0中的一个扩展因子具体值为b，校验矩阵2中的相应位置的扩展因子具体值为(b mod Z)。在该实现方式中，发送端可先扩展得到校验矩阵0，再基于校验矩阵0做简单变换得到所需扩展因子的校验矩阵。可见，在该实现方式中，发送端采用任何扩展因子扩展第一基矩阵均执行相同的扩展操作，不需要执行不同的扩展操作，编码复杂度较低。
方式二
发送端基于第一基矩阵扩展得到校验矩阵0，校验矩阵0的扩展因子为Z，例如Z＝27；若需要得到扩展因子为Z1(大于或等于Z)的校验矩阵1时，将校验矩阵0中的扩展因子具体值加上Z的整倍数作为校验矩阵1中的相应位置的扩展因子具体值，例如校验矩阵0中的一个扩展因子具体值为b，校验矩阵1中的相应位置的扩展因子具体值为b、(b+Z)或(b+2Z)。这里，校验矩阵0可以为前述第一校验矩阵，校验矩阵1可以为前述第二校验矩阵。校验矩阵0和校验矩阵1均符合第一基矩阵。在方式二中，扩展因子Z可以是发送端扩展第一基矩阵可能采用的最小的扩展因子。或者说，发送端需要得到的校验矩阵中的CPM的扩展因子均大于或等于Z，因此不存在需要得到扩展因子小于Z的校验矩阵的情况。在该实现方式中，发送端可先扩展得到校验矩阵0，再基于校验矩阵0做简单变换得到所需扩展因子的校验矩阵。可见，在该实现方式中，发送端采用任何扩展因子扩展第一基矩阵均执行相同的扩展操作，不需要执行不同的扩展操作，编码复杂度较低。
方式三
发送端基于第一基矩阵扩展得到校验矩阵0，校验矩阵0的扩展因子为Z，例如Z＝27；若需要得到扩展因子为Z3(小于Z)的校验矩阵3时，将校验矩阵0中的扩展因子具体值取模Z运算得到的值作为校验矩阵3中的相应位置的扩展因子具体值，例如校验矩阵0中的一个扩展因子具体值为b，校验矩阵3中的相应位置的扩展因子具体值为(b mod Z)；若需要得到扩展因子为Z4(大于或等于Z)的校验矩阵4时，将校验矩阵0中的扩展因子具体值加上Z的整倍数作为校验矩阵4中的相应位置的扩展因子具体值，例如校验矩阵0中的一个扩展因子具体值为b，校验矩阵4中的相应位置的扩展因子具体值为b、(b+Z)或(b+2Z)。校验矩阵3可以为前述第一校验矩阵，校验矩阵4可以为前述第二校验矩阵。校验矩阵3和校验矩阵4均符合第一基矩阵。校验矩阵3和校验矩阵4均可视为基于第一基矩阵扩展得到的校验矩阵。需要注意，校验矩阵4中的各元素均不能大于Z1。在该实现方式中，发送端可先扩展得到校验矩阵0，再基于校验矩阵0做简单变换得到所需扩展因子的校验矩阵。可见，在 该实现方式中，发送端采用任何扩展因子扩展第一基矩阵均执行相同的扩展操作，不需要执行不同的扩展操作，编码复杂度较低。
本申请描述了发送端基于第一基矩阵扩展得到多个校验矩阵的方式。应理解，接收端可采用类似的方式基于第一基矩阵扩展得到多个校验矩阵，这里不再赘述。
本申请提供的第二类方案是综合考虑LDPC码的性能、译码收敛速度、译码复杂度等中的多项因素，设计的几组复杂度低且译码收敛快的LDPC码的基矩阵和相应的校验矩阵。本申请中，LDPC码的基矩阵可按照准规则校验度进行设计，即基矩阵所有行的重量(非零项的个数)仅有两个值：d和d+1。d为大于0的整数，例如d＝7。这种设计可提高LDPC译码流程中校验节点处理的效率，即不会造成资源浪费。同时，由于译码的时延或复杂度与校验节点的最大度相关度较高，因此本申请中尽可能最小化校验节点的最大度(如上上述d+1)。校验节点的最大度是指校验节点最大边的数目或校验矩阵的最大行重。
另外，针对变量节点的度分布优化，为了平衡编码性能、复杂度等因素，本申请引入了两个控制变量：平均变量节点度、斜率(slope)。通过调整上述两个控制变量，本申请提供的基矩阵和校验矩阵可有效平衡所设计LDPC码的性能、译码收敛速度、复杂度等因素。其中，平均变量节点度指校验矩阵的平均列重，即平均每列包含非零项的数目；这里斜率指所设计LDPC码的EBP-GEXIT图曲线的拟合斜率，具体原理和解释参见文献[1]；[1]G.Montorsi,“Design of LDPC codes with tunable slope of their EXIT charts,”in Turbo Codes and Iterative Information Processing(ISTC),2016 9th International Symposium on.IEEE,2016,pp.126–130.
本申请中，译码复杂度采用平均变量节点度(η)表述，则具体LDPC迭代译码的复杂度可由平均迭代次数与译码复杂度的乘积表示：C∝η·nit。其中，C表示大致译码运算复杂度的数量级，η表示平均变量节点度，nit表示平均迭代次数。为了说明本申请的基本设计思路，下面以码长320比特和640比特的LDPC码(即校验矩阵)为例，具体说明了采用不同的控制变量(平均变量节点度、斜率)所设计的不同LDPC码(对应于基矩阵)，并给出了其性能分别在译码5、15和25次迭代达到FER＝10-2和10-3所需的信噪比(signal noise ratio，SNR)。表1示出了根据码长n＝320比特的校验矩阵进行5次译码迭代达到FER＝10-3所需的SNR。表2示出了根据码长n＝640比特的校验矩阵进行25次译码迭代达到FER＝10-3所需的SNR。
表1
表2

表1和表2中，第一列表示上述控制参数中的斜率，第一行中的第二列至最后一列描述的是基矩阵的平均列重，表中的每一项表示在相应斜率(行)和平均列重(列)下达到FER＝10-3所需的SNR值，该SNR值越低表示相应码的性能越优。下面取了两个典型的在性能和复杂度达到很好均衡的优化设计的码(即基矩阵)：低复杂度(η＝3.2)和高复杂度(η＝3.6)，如表2中加粗的数值所示。本申请中，可先得到所设计的LDPC码的基矩阵，再对该基矩阵进行扩展从而得到不同码长的LDPC码的校验矩阵。
本申请实施例提供的校验矩阵41、校验矩阵42、校验矩阵43以及校验矩阵44的码率均为1/2，码长分别为320、640、1280、2560比特。本申请实施例提供的校验矩阵51、校验矩阵52、校验矩阵53以及校验矩阵54的码率均为1/2，码长分别为320、640、1280、2560比特。校验矩阵41、校验矩阵42、校验矩阵43以及校验矩阵44符合的基矩阵4的复杂度为3.2，校验矩阵51、校验矩阵52、校验矩阵53以及校验矩阵54符合的基矩阵5的复杂度为3.6。基矩阵的复杂度可表征利用该基矩阵扩展的校验矩阵进行单次译码的复杂度。可理解，基矩阵的复杂度越好，表示利用该基矩阵扩展的校验矩阵进行单次译码的复杂度越高。本申请中，基矩阵的复杂度即为由该基矩阵得到的LDPC码的复杂度。
下面结合附图来描述本申请提供的复杂度分别为3.2和3.6的LDPC码在不同次分层译码迭代下的误包率(frame error rate，FER)仿真性能。3.2和3.6的LDPC码可以理解为采用本申请提供的基矩阵的进行LDPC编码或译码的方案。
图16A为本申请实施例提供的一种LDPC码25次分层译码迭代下的FER仿真性能对比示意图。参阅图16A，横坐标表示SNR，纵坐标表示FER，NR 320表示NR系统中根据码率为1/2、码长为320比特的校验矩阵进行15分层译码迭代下的FER，WiFi 312表示WiFi设备(例如站点或接入点)根据码率为1/2、码长为320比特的校验矩阵进行15分层译码迭代下的FER，320 3.2表示接收端根据码率为1/2、码长为320比特且复杂度为3.2的LDPC码进行15分层译码迭代下的FER，640 3.6表示接收端根据码率为1/2、码长为320比特且复杂度为3.6的LDPC码进行15分层译码迭代下的FER；NR 640表示NR系统中根据码率为1/2、码长为640比特的校验矩阵进行15分层译码迭代下的FER，WiFi 624表示WiFi设备(例如站点或接入点)根据码率为1/2、码长为640比特的校验矩阵进行15分层译码迭代下的FER，640 3.2表示接收端根据码率为1/2、码长为640比特且复杂度为3.2的LDPC码进行15分层译码迭代下的FER，640 3.6表示接收端根据码率为1/2、码长为640比特且复杂度为3.6的LDPC码进行15分层译码迭代下的FER；NR 1280表示NR系统中根据码率为1/2、码长为1280比特的校验矩阵进行15分层译码迭代下的FER，WiFi 1248表示WiFi设备(例如站点或接入点)根据码率为1/2、码长为1280比特的校验矩阵进行15分层译码迭代下的FER，1280 3.2表示接收端根据码率为1/2、码长为1280比特且复杂度为3.2的LDPC码进行15分层译码迭代下的FER，1280 3.6表示接收端根据码率为1/2、码长为1280比特且复杂度为3.6的LDPC码进行15分层译码迭代下的FER；NR 2560表示NR系统中根据码率为1/2、码长为2560比特的校验矩阵进行15分层译码迭代下的FER，WiFi 2496表示WiFi设备(例如站点或接入点)根据码率为1/2、码长为2560比特的校验矩阵进行15分层译码迭代下的FER，2560 3.2表示接收端根据码率为1/2、码长为2560比特且复杂度为3.2的LDPC码进行15分层译码迭代下的FER，2560 3.6表示接收端根据码率为1/2、码长为2560比特且复杂度为3.6的LDPC码进行15分层译码迭代下的FER。
图16B为本申请提供的一种LDPC码15次分层译码迭代下的FER仿真性能对比示意图。 图16C为本申请提供的一种LDPC码5次分层译码迭代下的FER仿真性能对比示意图。图16B和图16C中的各线条的含义与图16A中的各线条的含义类似，这里不再赘述。
参阅图16A、图16B以及图16C，本申请所设计LDPC码在译码迭代次数较小(例如5次迭代)下，可获得更优异的性能，且可灵活控制译码复杂度和性能之间的均衡。表3、表4、表5分别示出了本申请提供的LDPC码与WLAN LDPC和NR LDPC在不同译码迭代次数下性能和复杂度之间的全面比较。可见，在低复杂度情况下，本申请提供的LDPC码可获得更优的性能，且仅需实现单个基矩阵的扩展。
表3
表3示出了本申请提供的LDPC码与WLAN LDPC和NR LDPC在5次分成译码迭代下的性能和复杂度之间的全面比较。New 3.2表示本申请提供的码率为1/2、码长为2560比特且复杂度为3.2的LDPC码(对应于本申请提供的一种基矩阵)。New 3.6表示本申请提供的码率为1/2、码长为2560比特且复杂度为3.6的LDPC码(对应于本申请提供的另一种基矩阵)。第二列表示平均变量节点度，SNR@1e-2表示译码5次迭代达到FER＝10-2所需的SNR。SNR@1e-2表示译码5次迭代达到FER＝10-3所需的SNR。
表4

表4示出了本申请提供的LDPC码与WLAN LDPC和NR LDPC在15次分成译码迭代下的性能和复杂度之间的全面比较。表4中各参数的含义可参阅表3。
表5
表5示出了本申请提供的LDPC码与WLAN LDPC和NR LDPC在25次分成译码迭代下的性能和复杂度之间的全面比较。表5中各参数的含义可参阅表3。
下面分别给出采用本申请提供的校验矩阵在10、15和25次译码迭代次数下的性能比较。图17A为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在10次译码迭代次数下的性能示意图。图17B为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在15次译码迭代次数下的性能示意图。图17C为本申请实施例提供的一种校验矩阵41、校验矩阵42、校验矩阵43、校验矩阵44在25次译码迭代次数下的性能示意图。在图17A、图17B、图17C中，1701代表校验矩阵41的性能曲线， 1702代表校验矩阵42的性能曲线，1703代表校验矩阵43的性能曲线，1704代表校验矩阵44的性能曲线。图18A为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在10次译码迭代次数下的性能示意图。图18B为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在15次译码迭代次数下的性能示意图。图18C为本申请实施例提供的一种校验矩阵51、校验矩阵52、校验矩阵53、校验矩阵54在25次译码迭代次数下的性能示意图。在图18A、图18B、图18C中，1801代表校验矩阵51的性能曲线，1802代表校验矩阵52的性能曲线，1803代表校验矩阵53的性能曲线，1804代表校验矩阵54的性能曲线。
从图17A、图17B、图17C、图18A、图18B、图18C可以看出，本申请采用单个基矩阵和不同扩展因子可获得优异的译码性能，同时在译码性能和复杂度之间可取的很好的折衷。
下面结合附图介绍可实施本申请实施例提供的LDPC码的编码方法或LDPC码的译码方法的通信装置的结构。
图19为本申请实施例提供的一种通信装置1900的结构示意图。该通信装置1900可以对应实现上述各个方法实施例中发送端实现的功能或者步骤，也可以对应实现上述各个方法实施例中接收端实现的功能或者步骤。该通信装置可以包括处理模块1910和收发模块1920。可选的，还可以包括存储单元，该存储单元可以用于存储指令(代码或者程序)和/或数据。处理模块1910和收发模块1920可以与该存储单元耦合，例如，处理模块1910可以读取存储单元中的指令(代码或者程序)和/或数据，以实现相应的方法。上述各个单元可以独立设置，也可以部分或者全部集成。例如，收发模块1920可包括发送模块和接收模块。发送模块可以是发射机，接收模块可以是接收机。收发模块1920对应的实体可以是收发器，也可以是通信接口。
在一些可能的实施方式中，通信装置1900能够对应实现上述方法实施例中发送端的行为和功能。例如通信装置1900可以为站点，也可以为应用于站点中的部件(例如芯片或者电路)。例如通信装置1900可以为接入点，也可以为应用于接入点中的部件(例如芯片或者电路)。收发模块1920例如可以用于执行图8、图9、图10的实施例中由发送端所执行的全部接收或发送操作，例如图8所示的实施例中的步骤802，图9所示的实施例中的步骤903，图10所示的实施例中的步骤1003、步骤1007，和/或用于支持本文所描述的技术的其它过程。处理模块1910用于执行图8、图9、图10的实施例中由发送端所执行的除了收发操作之外的全部操作，例如图8所示的实施例中的步骤801，图9所示的实施例中的步骤902、步骤902，图10所示的实施例中的步骤1001、步骤1002、步骤1006、步骤1007。
在一些可能的实施方式中，通信装置1900能够对应实现上述方法实施例中接收端的行为和功能。例如通信装置1900可以为接入点，也可以为应用于接入点中的部件(例如芯片或者电路)。例如通信装置1900可以为站点，也可以为应用于站点中的部件(例如芯片或者电路)。收发模块1920例如可以用于执行图8、图9、图10的实施例中由接收端所执行的全部接收或发送操作，例如图8所示的实施例中的步骤802，图9所示的实施例中的步骤903，图10所示的实施例中的步骤1003、步骤1008，和/或用于支持本文所描述的技术的其它过程。处理模块1910用于执行由接收端所执行的除了收发操作之外的全部操作，例如图8所示的实施例中的步骤803、步骤804，图9所示的实施例中的步骤904、步骤905、步骤906、步骤907，图10所示的实施例中的步骤1004、步骤1005、步骤1009、步骤1010。
图20为本申请实施例提供的另一种通信装置200的结构示意图。图20中的通信装置可以是上述发送端，也可以是上述接收端。
如图20所示，该通信装置200包括至少一个处理器2010和收发器2020。
在本申请的一些实施例中，处理器2010和收发器2020可以用于执行发送端执行的功能或操作等。收发器2020例如执行图8、图9、图10的实施例中由发送端所执行的全部接收或发送操作。处理器2010例如用于执行图8、图9、图10的实施例中由发送端所执行的除了收发操作之外的全部操作。
在本申请的一些实施例中，处理器2010和收发器2020可以用于执行接收端执行的功能或操作等。收发器2020例如执行图8、图9、图10的实施例中由接收端点所执行的全部接收或发送操作。处理器2010用于执行由接收端所执行的除了收发操作之外的全部操作。
收发器2020用于通过传输介质和其他设备/装置进行通信。处理器2010利用收发器2020收发数据和/或信令，并用于实现上述方法实施例中的方法。处理器2010可实现处理模块1910的功能，收发器2020可实现收发模块1920的功能。
可选的，收发器2020可以包括射频电路和天线，射频电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。
可选的，通信装置200还可以包括至少一个存储器2030，用于存储程序指令和/或数据。存储器2030和处理器2010耦合。本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器2010可能和存储器2030协同操作。处理器2010可能执行存储器2030中存储的程序指令。该至少一个存储器中的至少一个可以包括于处理器中。
当通信装置200开机后，处理器2010可以读取存储器2030中的软件程序，解释并执行软件程序的指令，处理软件程序的数据。当需要通过无线发送数据时，处理器2010对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到通信装置时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器2010，处理器2010将基带信号转换为数据并对该数据进行处理。
在另一种实现中，上述的射频电路和天线可以独立于进行基带处理的处理器而设置，例如在分布式场景中，射频电路和天线可以与独立于通信装置，呈拉远式的布置。
本申请实施例中不限定上述收发器2020、处理器2010以及存储器2030之间的具体连接介质。本申请实施例在图20中以存储器2030、处理器2010以及收发器2020之间通过总线2040连接，总线在图20中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图20中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
图21为本申请实施例提供的另一种通信装置210的结构示意图。如图21所示，图21所示的通信装置包括逻辑电路2101和接口2102。图19中的处理模块1910可以用逻辑电路2101实现，图19中的收发模块1920可以用接口2102实现。其中，该逻辑电路2101可以为芯片、处理电路、集成电路或片上系统(system on chip，SoC)芯片等，接口2102可以为通信接口、 输入输出接口等。本申请实施例中，逻辑电路和接口还可以相互耦合。对于逻辑电路和接口的具体连接方式，本申请实施例不作限定。
在本申请的一些实施例中，该逻辑电路和接口可用于执行上述发送端执行的功能或操作等。
在本申请的一些实施例中，该逻辑电路和接口可用于执行上述接收端执行的功能或操作等。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令在计算机上运行时，使得计算机执行上述实施例的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括指令或计算机程序，当该指令或计算机程序在计算机上运行时，使得上述实施例中的方法被执行。
本申请还提供一种通信系统，包括上述发送端和上述接收端。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以上述权利要求的保护范围为准。

Claims (22)

  1. 一种LDPC码的编码方法，其特征在于，包括：
    根据校验矩阵，对第一比特序列进行低密度奇偶校验LDPC编码，得到第一数据包，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同；
    发送所述第一数据包。
  2. 一种LDPC码的译码方法，其特征在于，包括：
    获取接收到的第一信道接收序列对应的第一对数似然比LLR序列；
    根据校验矩阵，对所述第一LLR序列进行译码，所述校验矩阵包括第一校验矩阵和第二校验矩阵，所述第一校验矩阵和所述第二校验矩阵均符合第一基矩阵，所述第一校验矩阵的码长和所述第二校验矩阵的码长不同。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一校验矩阵中的第一位置的循环位移矩阵CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z1，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为(b mod Z)，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z2，所述Z、所述Z1、所述Z2均为大于0的整数，所述Z1大于或等于所述Z，所述Z2小于所述Z。
  4. 根据权利要求1或2所述的方法，其特征在于，所述第一校验矩阵中的第一位置的CPM的扩展因子具体值为b，所述第一校验矩阵中的第一位置的CPM的扩展因子为Z3，所述第二校验矩阵中的第一位置的CPM的扩展因子具体值为b、(b+Z)、(b+2Z)中的任一个，所述第二校验矩阵中的第一位置的CPM的扩展因子为Z4，所述Z、所述Z3、所述Z4均为大于0的整数，所述Z3小于所述Z，所述Z4大于或等于所述Z。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一基矩阵包括如下所示(12×24)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至24中的整数。
  6. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一基矩阵包括如下所示(12×24)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至24中的整数。
  7. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一基矩阵包括如下所示(12×24)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至24中的整数。
  8. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一基矩阵包括如下所示(12×7)的第一矩阵对应的(12×32)的第二矩阵中的L行或F列：

    所述第一矩阵的第i行的任一元素为u，所述第二矩阵的第i行的第(u+1)列的元素为1，所述i和所述L为1至12中的整数，所述F为1至32中的整数。
  9. 根据权利要求8所述的方法，其特征在于，所述第一校验矩阵包括如下所示(12×7)的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至79中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  10. 根据权利要求8所述的方法，其特征在于，所述第一校验矩阵包括如下所示(12×7)的第三矩阵对应的(12×32)第四矩阵中的S行或T列：

    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至39中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  11. 根据权利要求8所述的方法，其特征在于，所述第一校验矩阵包括如下所示(12×7)的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小 为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至19中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  12. 根据权利要求8所述的方法，其特征在于，所述第一校验矩阵包括如下所示(12×7)的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至9中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  13. 根据权利要求1至4任一项所述的方法，其特征在于，所述第一基矩阵包括如下所示的第一矩阵对应的(12×32)的第二矩阵中的L行或F列：

    所述第一矩阵的第i行的任一元素为u，所述第二矩阵的第i行的第(u+1)列的元素为1，所述i和所述L为1至12中的整数，所述F为1至32中的整数。
  14. 根据权利要求13所述的方法，其特征在于，所述第一校验矩阵包括如下所示的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至79中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  15. 根据权利要求13所述的方法，其特征在于，所述第一校验矩阵包括如下所示的第三矩阵对应的(12×32)第四矩阵中的S行或T列：

    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至39中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  16. 根据权利要求13所述的方法，其特征在于，所述第一校验矩阵包括如下所示的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0 至19中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  17. 根据权利要求13所述的方法，其特征在于，所述第一校验矩阵包括如下所示的第三矩阵对应的(12×32)第四矩阵中的S行或T列：
    所述第一矩阵的第j行的第二位置的元素为p，所述第三矩阵的第j行的所述第二位置的元素为q，所述第四矩阵的第j行的第(p+1)列的元素为q，所述第四矩阵中的0表示大小为(K×K)的单位矩阵，所述第四矩阵中的大于0的元素表示大小为(K×K)的CPM，所述第二位置为任一位置，所述j为1至12中的整数，所述p为0至31中的整数，所述q为0至9中的整数，所述K为大于1的整数，所述S为1至12中的整数，所述T为1至32中的整数。
  18. 一种通信装置，其特征在于，包括用于实现权利要求1至17中任一项所述的方法的模块或单元。
  19. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，所述计算机程序包括程序指令，所述程序指令被执行时使得计算机执行如权利要求1至17中任一项所述的方法。
  20. 一种通信装置，其特征在于，包括处理器，所述处理器与存储器耦合，所述存储器存储指令，所述处理器用于执行所述指令，使得所述通信装置执行如权利要求1至17任一项所述的方法。
  21. 一种芯片系统，其特征在于，包括：处理器，用于从存储器中调用并运行计算机程序，使得安装有所述芯片系统的通信设备执行权利要求1至17中任一项所述的方法。
  22. 一种计算机程序产品，其特征在于，当所述计算机程序产品在计算机上运行时，使得计算机执行如权利要求1至17中任一项所述的方法。
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