WO2023216991A1 - Ldpc的编译码方法和相关装置 - Google Patents

Ldpc的编译码方法和相关装置 Download PDF

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WO2023216991A1
WO2023216991A1 PCT/CN2023/092280 CN2023092280W WO2023216991A1 WO 2023216991 A1 WO2023216991 A1 WO 2023216991A1 CN 2023092280 W CN2023092280 W CN 2023092280W WO 2023216991 A1 WO2023216991 A1 WO 2023216991A1
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matrix
check
columns
check matrix
size
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PCT/CN2023/092280
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English (en)
French (fr)
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林伟
蒙托里西基多
贝勒迪多塞吉奥
杨讯
辛岩
淦明
马梦瑶
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present application relates to the field of communication technology, and in particular to an LDPC encoding and decoding method and related devices.
  • Wireless local area networks (WLAN) transmission standards such as IEEE802.11n/ac/ax/be focus on improving user experience in large-bandwidth scenarios, including improving average user throughput and energy efficiency of battery-powered equipment.
  • the 60GHz large-bandwidth scenario needs to support high-speed and reliable transmission of data, video and other services on limited frequency and power resources, so a highly reliable and efficient channel coding and decoding solution is required.
  • Turbo codes and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods. They both have performance close to the Shannon limit.
  • LDPC codes have: good bit error performance without the need for deep interleaver; better frame error rate performance; greatly reduced error level; support for parallel decoding, small decoding delay Etc.
  • LDPC codes have become the standard channel coding scheme for low-frequency short-distance WLAN communication systems such as IEEE802.11n/ac/ax, and become the necessary channel coding scheme when IEEE802.11ax is greater than or equal to 40MHz bandwidth. Based on this, we can consider designing new LDPC codes for the next generation WLAN standard or ultra wide band (UWB) to further improve the reliability and system performance of the next generation WLAN system or UWB system.
  • UWB ultra wide band
  • the embodiments of this application disclose a method that can improve decoding performance and support multiple code rates.
  • embodiments of the present application provide an LDPC code encoding method.
  • the method includes: performing low-density parity check LDPC encoding on an information bit sequence according to a check matrix to obtain a first codeword; the check The matrix conforms to a base matrix, and the base matrix satisfies one of the following: each row in the first two columns of the base matrix includes at least one 1, or the first two columns of the base matrix include regularly alternating "1 0" ” and “0 1”, and “1 0” and “0 1” include “1 1”; or, the first two columns of the base matrix conform to the following rules: one column includes multiple “1 1 1 0” in order , the other column includes multiple "1 0 1 1” in sequence; send the first codeword.
  • the check matrix conforms to the base matrix.
  • the design of the base matrix enables the check matrix conforming to the base matrix to quickly transmit, exchange and decode information between the codeword bits corresponding to each column in the check matrix. Updated to speed up the overall decoding convergence speed of the system.
  • embodiments of the present application provide another LDPC code encoding method.
  • the method includes: the receiving end determines the first log-likelihood ratio sequence corresponding to the signal received on the first channel, and based on the check matrix, Decode the first LLR sequence; wherein the check matrix conforms to a base matrix, and the base matrix satisfies one of the following: each row in the first two columns of the base matrix includes at least one 1, or the The first two columns of the basis matrix include regularly alternating "1 0" and "0 1", and "10" and "0 1” include “1 1” in between; or, the first two columns of the base matrix conform to the following rules: one column includes multiple "1 1 1 0" in order, and the other column includes multiple "1 1 1 0" in order. "1 0 1 1".
  • the check matrix conforms to the base matrix.
  • the design of the base matrix enables the check matrix conforming to the base matrix to quickly transmit, exchange and decode information between the codeword bits corresponding to each column in the check matrix. Updated to speed up the overall decoding convergence speed of the system.
  • one of the first two columns of the base matrix includes the following elements: 1 1 1 0 1 1 1 0 1 1 0, and the base matrix
  • the other of the first two columns contains the following elements: 1 0 1 1 1 0 1 1 1 0 1 1, 1 in the base matrix corresponds to the cyclic displacement matrix CPM, and 0 in the base matrix corresponds to the all-zero square Array.
  • one of the first two columns of the basis matrix contains the following elements: 1 1 1 0 1 1 1 0 1 1 1 0, and the other of the first two columns of the basis matrix contains the following elements: 1 0 1 1 1 0 1 1 1 0 1 1;
  • a good compromise can be obtained between coding complexity and decoding performance.
  • an embodiment of the present application provides a communication device, which has the function of implementing the behavior in the method embodiment of the first aspect.
  • the communication device may be a communication device, a component of the communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the communication device.
  • the functions of the communication device can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the communication device includes an interface module and a processing module, wherein: the processing module is used to perform low-density parity check LDPC encoding on the information bit sequence according to the check matrix to obtain the first code word; the check matrix conforms to a base matrix, and the base matrix satisfies one of the following: each row in the first two columns of the base matrix includes at least one 1, or the first two columns of the base matrix include "1 0" and "0 1" alternate regularly, and "1 0" and "0 1” include “1 1” in between; or, the first two columns of the base matrix conform to the following rules: one column includes multiple "1 1 1 0", the other column includes multiple "1 0 1 1” in sequence; the interface module is used to send the first codeword.
  • the processing module is used to perform low-density parity check LDPC encoding on the information bit sequence according to the check matrix to obtain the first code word
  • the check matrix conforms to a base matrix, and the base matrix satisfies one of
  • the check matrix conforms to the base matrix.
  • the design of the base matrix enables the check matrix conforming to the base matrix to quickly transmit, exchange and decode information between the codeword bits corresponding to each column in the check matrix. Updated to speed up the overall decoding convergence speed of the system.
  • an embodiment of the present application provides a communication device, which has the function of implementing the behavior in the method embodiment of the second aspect.
  • the communication device may be a communication device, a component of the communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the communication device.
  • the functions of the communication device can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the communication device includes an interface module and a processing module, wherein: the interface module is used to receive a signal from the sending end; the processing module is used to determine whether the signal received by the first channel corresponds to The first log-likelihood ratio sequence, and decode the first LLR sequence according to the check matrix; wherein the check matrix conforms to the base matrix, and the base matrix satisfies one of the following: the base matrix Each row in the first two columns of includes at least one 1, or the first two columns of the base matrix include regularly alternating "1 0" and "0 1", and "1 0" and "0 1” include "1 1"; or, the first two columns of the base matrix conform to the following rules: one column includes multiple "1 1 1 0" in order, and the other column includes multiple "1 0 1 1" in order.
  • the check matrix conforms to the base matrix.
  • the design of the base matrix enables the check matrix conforming to the base matrix to quickly transmit, exchange and decode information between the codeword bits corresponding to each column in the check matrix. Updated to speed up the overall decoding convergence speed of the system.
  • one of the first two columns of the base matrix includes the following elements: 1 1 1 0 1 1 1 0 1 1 1 0, and The other of the first two columns contains the following elements: 1 0 1 1 1 0 1 1 1 0 1 1, 1 in the base matrix corresponds to the cyclic displacement matrix CPM, and 0 in the base matrix corresponds to an all-zero square matrix.
  • one of the first two columns of the basis matrix contains the following elements: 1 1 1 0 1 1 1 0 1 1 1 0, and the other of the first two columns of the basis matrix contains the following elements: 1 0 1 1 1 0 1 1 1 0 1 1;
  • a good compromise can be obtained between coding complexity and decoding performance.
  • inventions of the present application provide another communication device.
  • the communication device includes a processor.
  • the processor is coupled to a memory.
  • the memory is used to store programs or instructions.
  • the communication device is caused to execute the above-mentioned first aspect or the method shown in any possible implementation of the first aspect, or, when the program or instruction is executed by the processor, the communication device is caused to execute the above-mentioned second aspect or the second aspect. Any possible implementation of the method shown.
  • the process of sending information (or signals) in the above method can be understood as a process of outputting information based on instructions of the processor.
  • the processor In outputting information, the processor outputs the information to the transceiver for transmission by the transceiver. After the information is output by the processor, it may also need to undergo other processing before reaching the transceiver.
  • the processor receives incoming information
  • the transceiver receives the information and feeds it into the processor. Furthermore, after the transceiver receives the information, the information may need to undergo other processing before being input to the processor.
  • the above-mentioned processor may be a processor specifically designed to perform these methods, or may be a processor that executes computer instructions in a memory to perform these methods, such as a general-purpose processor.
  • the processor may also be configured to execute a program stored in the memory.
  • the communication device performs the method shown in the above-mentioned first aspect or any possible implementation of the first aspect.
  • the memory is located outside the communication device. In a possible implementation, the memory is located within the above communication device.
  • the processor and the memory may be integrated into one device, that is, the processor and the memory may be integrated together.
  • the communication device further includes a transceiver, which is used to receive signals or send signals, etc.
  • the present application provides another communication device.
  • the communication device includes a processing circuit and an interface circuit.
  • the interface circuit is used to obtain data or output data; the processing circuit is used to perform the above-mentioned first aspect or any of the first aspects.
  • the corresponding method shown in the possible implementation manner, or the processing circuit is used to perform the corresponding method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect.
  • the present application provides a computer-readable storage medium.
  • a computer program is stored in the computer-readable storage medium.
  • the computer program includes program instructions. When executed, the program instructions cause the computer to perform the above-mentioned first aspect or the third aspect.
  • the present application provides a computer program product.
  • the computer program product includes a computer program.
  • the computer program includes program instructions. When executed, the program instructions cause the computer to perform the above-mentioned first aspect or any possible method of the first aspect. The method shown in the implementation manner, or, when executed, the program instructions cause the computer to perform the method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect.
  • the present application provides a communication system, including the communication device described in the above third aspect or any possible implementation of the third aspect, and the communication device described in the above fourth aspect or any possible implementation of the fourth aspect. Communication device.
  • Figure 1 is an example of the check matrix H of the LDPC code
  • Figure 2 is the Tanner diagram of the check matrix H of the LDPC code
  • Figure 3 shows an example of the encoding process of the LDPC code
  • Figure 4 is a schematic diagram of the shortening operation part in the LDPC encoding process
  • Figure 5 is an example of a mother matrix obtained by extending H MC ;
  • Figure 6 shows an example of a check matrix expanded by a base matrix of size (12 ⁇ 22);
  • FIG. 7 is a system architecture diagram suitable for embodiments of this application.
  • Figure 8 is an interactive flow chart of an LDPC code encoding method provided by this application.
  • Figure 9 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • Figure 10 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • Figure 11 is an example of a basis matrix provided by this application.
  • Figure 12 is an example of a check matrix provided by this application.
  • Figure 13 is an example of another basis matrix provided by this application.
  • Figure 14 is a performance comparison diagram of an LDPC code provided by this application.
  • Figure 15A is a schematic diagram of an LDPC code punching provided by this application.
  • Figure 15B is a schematic diagram of shortening and punching an LDPC code provided by this application.
  • Figure 15C is a schematic diagram of another LDPC code shortening and punching provided by this application.
  • Figure 16 is a schematic structural diagram of a communication device 1600 provided by an embodiment of the present application.
  • Figure 17 is a schematic structural diagram of another communication device 170 provided by an embodiment of the present application.
  • Figure 18 is a schematic structural diagram of another communication device 180 provided by an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • a corresponds to B means that A and B have a corresponding relationship, and B can be determined based on A.
  • determining (or generating) B according to (or based on) A does not mean only determining (or generating) B according to (or based on) A. It can also be determined according to (or based on) A and/or other information. or generate)B.
  • LDPC code low density parity check code.
  • the full name of LDPC code is low density parity check code.
  • it is a parity check code with low density properties.
  • the low density refers to the low density of the check matrix of the LDPC code. Therefore, to understand what LDPC code is, we must first understand the three concepts of parity check code, check matrix and low density.
  • Parity check code is a coding method that adds redundant bits so that the number of "1"s in the codeword is always an odd or even number. It is an error detection code. Parity check codes are often used for digital encoding in the binary field of 0-1. One or several bits (check bits) are added at the end of the code word, and the code is judged by whether the number of 1's in the code word is odd or even. Whether the word has errors before or after transmission. For example, if the codeword 100 uses parity check, then the check bit can be 1. At this time, the value s that satisfies the sum (exclusive OR) of all codewords is 0, which is 1001.
  • the algorithm fails. Therefore, further, multiple check bits can be set.
  • the four-bit codeword 1101 can be grouped and the first bit of the check bit is used to check the first and second bits of the information bit (that is, the first two bits of the information bit 11). For example, if the sum of the first two bits of the information bit is 0, then the first bit of the check bit should be 0.
  • the second bit of the check bit can check the last two information bits of codeword 1101, so the second bit of the check bit is set to 1.
  • the encoded codeword is 110101.
  • the check relationship between the information bits and check bits of the codeword can be written in the form of a matrix. Record the information bits as c1, c2, c3, c4, and the check bits as p1, p2.
  • c [c1,c2,c3,c4]
  • x [c1,c2,c3,c4,p1,p2].
  • c and x are the codewords before and after encoding respectively.
  • H is the check matrix
  • s is the syndrome
  • H T represents the transpose of H.
  • ⁇ represents a matrix multiplication operation
  • a ⁇ B represents the matrix multiplication product of matrix A and matrix B.
  • c represents the unencoded codeword (or bit sequence)
  • G represents the generating matrix
  • the generating matrix can be obtained by transforming the check matrix. In other words, if you know the check matrix, you can get the generating matrix corresponding to the check matrix.
  • c can be called the information codeword
  • x can be called the transmission codeword.
  • Formula (2) shows that the transmitted codeword is obtained by multiplying the information codeword and the generator matrix.
  • the low-density property of the LDPC code means that the number of 1's in the check matrix of the LDPC code is very small.
  • LDPC code is a linear block code, and its check matrix is a sparse matrix.
  • the number of zero elements in the check matrix of the LDPC code is far more than the number of non-zero elements.
  • the row weight (that is, the number of 1's in each row) and the column weight (that is, the number of 1's in each column) of the check matrix are very small numbers compared to the code length of the LDPC code.
  • Tanner represented the code words of the LDPC code graphically in 1981.
  • This kind of graph is now called a Tanner graph, and the Tanner graph has a one-to-one correspondence with the check matrix.
  • the Tanner graph consists of two types of vertices, one type of vertices are variable nodes, representing codeword bits, and the other type of vertices are check nodes, representing check constraint relationships.
  • Each verification node represents a verification constraint relationship, which will be explained below with reference to Figures 1 and 2.
  • FIG. 1 shows the check matrix H of the LDPC code.
  • ⁇ V i ⁇ represents the variable node set
  • ⁇ C i ⁇ represents the check node set.
  • Each row of the check matrix H corresponds to a check equation
  • each column corresponds to a codeword bit.
  • the Tanner diagram represents the check matrix of the LDPC code.
  • the Tanner graph contains two types of nodes, namely n variable nodes (also called information nodes or bit nodes) and m check nodes, m, n are all integers greater than 0.
  • n variable nodes also called information nodes or bit nodes
  • m check nodes are all integers greater than 0.
  • the above-mentioned n variable nodes respectively correspond to n columns of the check matrix H
  • the above-mentioned m check nodes respectively correspond to m rows of the check matrix H.
  • the cycle in the Tanner graph is composed of vertices connected to each other.
  • the cycle uses a vertex in this group of vertices as both the starting point and the end point, and only passes through each node once.
  • the length of a loop is defined as the number of connections it contains, and the girth of the graph can also be called the size of the graph, which is defined as the smallest loop length in the graph, as in Figure 2, and the girth is 6, as in Figure 2 Shown in black.
  • the transmission codeword is obtained by multiplying the information codeword and the generator matrix, and the generator matrix can be obtained by transforming the check matrix. Therefore, the entire LDPC code encoding process is actually a check matrix construction process.
  • Figure 3 shows an example of the encoding process of the LDPC code.
  • the decoding algorithms of LDPC codes include the following three categories: hard-decision decoding, soft-decision decoding and hybrid decoding.
  • the LDPC code used in the IEEE 802.11ac and 802.11ax standards is the QC-LDPC code.
  • QC-LDPC code is a type of structured LDPC code. Due to the unique structure of its check matrix, a simple feedback shift register can be used during encoding to reduce the encoding complexity of LDPC codes.
  • Some WLAN standards use orthogonal frequency division multiplexing (OFDM) technology.
  • the LDPC encoding module needs to encode the data bits (which can be called information bits) into an integer number of OFDM symbols, and these encoded bits must fit into an integer number of LDPC codewords.
  • the sending end calculates the LDPC code length used in the current transmission and the required number of codewords. For most combinations of bit length and coding modulation scheme of the data to be encoded, since there are not enough data bits to fill the data bit portion of the LDPC codeword, a shortening operation is required before generating the parity bits.
  • the data bits in the LDPC codeword only contain information bits (or data bits) and do not contain parity bits (or parity bits).
  • the shortening operation refers to filling in a certain number of 0s in the data bits of the codeword information before generating the check bits through LDPC encoding, and then deleting these 0s after encoding the check bits.
  • Figure 4 is a schematic diagram of the shortening operation part in the LDPC encoding process.
  • 401 represents the data bits to be encoded (payload bits); step 1 is to calculate the length and number of codewords required to send the data bits to be encoded, and 402 shows the LDPC code The length of the word and the number of codewords; Step 2 is to shorten the data bits to be encoded, 403 shows a codeword containing data bits and shortening zero bits (shortening zero bits); Step 3 is to utilize the data bits and shorten the 0 bits , generate parity bits, 404 shows a codeword containing data bits, shortened 0 bits and parity bits; these shortening 0 bits are then deleted (discard shortening bits), 405 shows a codeword containing only data bits and the codeword of the check bits.
  • the mother matrix is a larger matrix from which check matrices of different sizes can be read.
  • Check matrices of different sizes read from the mother matrix correspond to different code rates.
  • the mother matrix can be expanded by a check matrix (hereinafter referred to as the basic matrix).
  • the basic matrix is the check matrix.
  • the code rate corresponding to the check matrix is the largest.
  • the mother matrix is the check matrix.
  • the code rate corresponding to the check matrix is the smallest.
  • H MC represent the basic matrix of size (4 ⁇ 24) (such as the WLAN LDPC check matrix with code length 1944 and code rate 5/6), 0 4 ⁇ 100 represents the all-zero matrix of size (4 ⁇ 100), I 100 ⁇ 100 represents a unit matrix of size (100 ⁇ 100), then the matrix H IR of size (100 ⁇ 24) is defined together with H MC , 0 4 ⁇ 100 and I 100 ⁇ 100 to form the expanded mother Matrix H, that is
  • H MC and H IR design and optimization If you want to extend the H MC to obtain incremental redundant bits corresponding to a lower code rate, you can extend the H MC to the required number of columns according to the required code rate. For example, if you need to reduce the code rate from 5/6 corresponding to H MC to 4/7, or if you need to add 324 new incremental redundant bits corresponding to 4 columns on the basis of H MC , you need to follow the H MC Expand H MC downward, that is, expand 4 lines downward and 4 lines rightward.
  • FIG. 5 is an example of a mother matrix obtained by extending H MC .
  • the rectangular box at the upper left corner of the mother matrix is the matrix H MC .
  • Each blank grid in Figure 5 represents an all-zero matrix of size (81 ⁇ 81).
  • the upper left corner of the parent matrix is the matrix H MC of size (4 ⁇ 24).
  • the upper right corner is the first fixed matrix.
  • the fixed matrix is 0 4 ⁇ 100 .
  • the lower left corner of the parent matrix is the matrix H IR , and the lower right corner of the parent matrix is the second fixed matrix.
  • the fixed matrix is large I 100 ⁇ 100 .
  • the size of the matrix obtained after H MC expansion is (8 ⁇ 28), as shown in Figure 5 for the entire matrix.
  • Each element in the parent matrix (except for blank cells) is a cyclic shift matrix of size (81 ⁇ 81). It should be understood that the overall mother matrix size is (8 ⁇ 28), and the final mother matrix size obtained by expanding each item is (648 ⁇ 2268). If you need to obtain the remaining code rate or the remaining number of incremental redundant bits, you can use the above method to take the required part from the upper left part of H as the check matrix. If (81 ⁇ j) incremental redundant check bits need to be generated in addition to the codeword bits corresponding to the original H MC , then the size of the upper left part of the obtained check matrix is (4+j) ⁇ ( 24+j), j is a positive integer.
  • the above uses the check matrix H MC as an example to introduce the expansion process from the basic matrix to the mother matrix.
  • the expansion of other check matrices to obtain the mother matrix is also based on the same design concept.
  • the base matrix of the LDPC code can be expanded to the check matrix of the LDPC code of various code lengths as needed.
  • the check matrix of LDPC codes of various code lengths can be obtained by extending the base matrix as needed.
  • the basis matrix contains only two elements, 0 and 1.
  • 0 in the base matrix can be replaced by a blank, "-", "-1", or other numbers or symbols, which is not limited by this application.
  • 1 in the base matrix corresponds to a non-all-zero square matrix (also called a non-all-0 square matrix), and a 0 element in the base matrix corresponds to an all-zero square matrix (also called an all-0 square matrix). .
  • an all-zero square matrix refers to a square matrix in which each element is 0, such as a square matrix with a size of (34 ⁇ 34).
  • a non-all-zero square matrix refers to a square matrix including at least one non-zero element, such as a circulant permutation matrix (CPM).
  • CPM circulant permutation matrix
  • the check matrix is obtained by extending the base matrix as follows: replacing 1 in the base matrix with the CPM of various cyclic factors, and replacing 0 with an all-0 square matrix of corresponding size. Therefore, a series of check matrices of LDPC codes can be obtained from the basis matrix.
  • the size of these check matrices and the expansion factor of each CPM can be different, but they correspond to or conform to the same base matrix.
  • the cyclic factor and the expansion factor have the same meaning, so the cyclic factor and the expansion factor can be replaced with each other.
  • FIG. 6 shows an example of a check matrix (check matrix 11 below) obtained by extending a basis matrix (base matrix 1 below) of size (12 ⁇ 22).
  • -1 in the check matrix represents an all-zero matrix of size (K ⁇ K)
  • 0 in the check matrix represents an identity matrix of size (K ⁇ K).
  • the elements greater than 0 represent a cyclic shift matrix of size (K ⁇ K).
  • -1 (representing an all-zero matrix) in the check matrix can be replaced by a blank, "-", or other numbers or symbols, which is not limited by this application.
  • the meaning or function of -1 or 0 in the check matrix later is as mentioned above and will not be described again.
  • LDPC codes have been widely used in WLAN standards.
  • the new IEEE 802.15ab standard can introduce new LDPC coding technology to greatly improve the data transmission reliability of the system. Therefore, it is possible to consider designing new LDPC codes for the next generation WLAN standard or UWB standard to further improve the reliability and system performance of the next generation WLAN system or UWB system.
  • this application proposes the design of a set of LDPC code base matrices and corresponding check matrices for the next generation WLAN system or UWB system.
  • the basis matrix provided by this application can effectively support multiple code rates, such as 2/3 to 1/2 code rates.
  • the LDPC encoding scheme provided by this application can well support the encoding of short packets, such as 20-byte (160-bit) data encoding, and obtain excellent error control performance.
  • the base matrix of the LDPC code provided in this application can be flexibly extended to various code lengths, so that excellent error control performance can be obtained at each code length using a single base matrix.
  • the technical solution of this application is mainly applicable to wireless communication systems.
  • the wireless communication system can comply with the wireless communication standards of the third generation partnership project (3GPP) or other wireless communication standards, such as the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics Engineers). , IEEE) 802 series (for example, 802.11, 802.15, or 802.20) wireless communication standards.
  • 3GPP third generation partnership project
  • IEEE 802 series for example, 802.11, 802.15, or 802.20 wireless communication standards.
  • the wireless communication system includes at least one access network device and one or more terminal devices.
  • the above-mentioned at least one access network device and one or more terminal devices communicate using wireless communication technology.
  • (a) of Figure 7 shows communication between an access network device and a single terminal device.
  • (b) of Figure 7 shows that one access network device communicates with multiple terminal devices.
  • the communication between the access network device and the terminal device may include downlink transmission of signals sent by the access network device to the terminal device, and may also include uplink transmission of signals sent by the terminal device to the access network device, which is not limited herein.
  • Terminal equipment is a device with wireless sending and receiving functions. Terminal equipment can be accessed via the radioaccess network (radioaccess network, An access network device (or access device) in a RAN communicates with one or more core network (CN) devices (or core device). Terminal equipment can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it can also be deployed on water (such as ships, etc.); it can also be deployed in the air (such as aircraft, balloons, satellites, etc.).
  • radioaccess network radioaccess network
  • An access network device (or access device) in a RAN communicates with one or more core network (CN) devices (or core device).
  • CN core network
  • Terminal equipment can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it can also be deployed on water (such as ships, etc.); it can also be deployed in the air (such as aircraft, balloons, satellites, etc.).
  • the terminal device may also be called a terminal (terminal) or user equipment (UE), and may be a mobile phone (mobile phone), a station (station, STA), a mobile station (mobile station, MS), Tablet computers (pads), computers with wireless transceiver functions, virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, wireless terminal equipment in industrial control (industrial control), driverless driving Wireless terminal equipment in (self driving), wireless terminal equipment in remote medical (remote medical), wireless terminal equipment in smart grid (smart grid), wireless terminal equipment in transportation safety (transportation safety), smart city (smart Wireless terminal equipment in the city), wireless terminal equipment in the smart home (smart home), subscriber unit (subscriber unit), cellular phone (cellular phone), wireless data card, personal digital assistant (personal digital assistant, PDA) computer, Tablet computers, laptop computers, machine type communication (MTC) terminal equipment, etc.
  • VR virtual reality
  • AR augmented reality
  • wireless terminal equipment in industrial control industrial control
  • driverless driving Wireless terminal equipment in self driving
  • Terminal devices may include various handheld devices with wireless communication capabilities, vehicle-mounted devices, wearable devices, computing devices, or other processing devices connected to wireless modems.
  • the terminal device can be a handheld device (handset) with wireless communication function, a vehicle-mounted device, a wearable device, or a terminal device in the Internet of Things, the Internet of Vehicles, 5G and any form of terminal in the communication system evolved after 5G. Equipment, etc., this application is not limited to this.
  • the terminal device may support the wireless communication standard of 3GPP or the wireless communication standard of the IEE802 series (for example, 802.11, 802.15, or 802.20).
  • the access network device can be any device that has wireless transceiver functions and can communicate with the terminal, such as a RAN node that connects the terminal to the wireless network.
  • RAN nodes include: macro base stations, micro base stations (also called small stations), relay stations, access points, gNBs, transmission reception points (TRP), evolved Node B, eNB), wireless network controller (radio network controller, RNC), home base station (e.g., home evolved NodeB, or home Node B, HNB), base band unit (base band unit, BBU), wireless access point (access point, AP), integrated access and backhaul (IAB), transmission reception point (TRP) or transmission node (TP), etc.
  • the access network equipment can also be a network node that constitutes a gNB or TRP, such as a BBU, a centralized unit (CU) or a distributed unit (DU), etc.
  • the access network equipment may support the wireless communication standards of 3GPP or the wireless communication standards of the IEE802 series (for example, 802.11, 802.15, or 802.20).
  • Figure 8 is an interactive flow chart of an LDPC code encoding method provided by this application. As shown in Figure 8, the method includes:
  • the sending end performs LDPC encoding on the information bit sequence according to the check matrix to obtain the encoded bits.
  • the sending end can be a terminal device or an access network device.
  • LDPC encoding of the information bit sequence according to the check matrix may be: multiplying the information bit sequence and the generator matrix corresponding to the check matrix to obtain the first codeword.
  • the specific process please refer to the encoding of the LDPC code described above and the LDPC encoding in WLAN. This application does not limit the specific method of LDPC encoding the information bit sequence according to the check matrix.
  • the operations or processing performed by the receiving end can be performed by the receiving end or by a chip or circuit system provided in the transmitting end.
  • the above-mentioned circuit system may be, for example, an integrated circuit or a logic circuit.
  • the above-mentioned chip may be, for example, a system-on-chip (SoC) chip or a baseband modem chip, which is not limited herein.
  • SoC system-on-chip
  • the following description takes the sending end as an example. It should be understood that the sending end in the embodiment of this application is also the encoding device.
  • the operation or processing performed by the receiving end may be performed by the receiving end, or may be performed by a chip or circuit system installed in the receiving end.
  • the above-mentioned circuit system may be, for example, an integrated circuit, a logic Edit circuit.
  • the above-mentioned chip may be, for example, an SoC chip or a baseband modem chip, etc., which is not limited herein.
  • the following uses the receiving end as an example for explanation.
  • the receiving end can be a terminal device or an access network device. It should be understood that the receiving end in the embodiment of this application is also the decoding device.
  • the above check matrix conforms to (or satisfies) the basis matrix.
  • the check matrix is expanded according to the base matrix or the sub-matrix of the above-mentioned base matrix. Since the process of obtaining the check matrix by expanding the base matrix has been introduced before, it will not be described here again.
  • the check matrix can be divided into two parts, one part is the information symbol (or called information bit), and the other part is the check code word (or called check bit).
  • the first F column of the check matrix is the information symbol part, the (F+1)th to the last column is the check symbol part, and F is an integer greater than 0.
  • the above-mentioned base matrix includes a core matrix, an extended matrix, a first fixed matrix and a second fixed matrix.
  • the above-mentioned core matrix is located at the upper left corner of the above-mentioned base matrix, and the above-mentioned expansion matrix is located at the lower left corner of the above-mentioned base matrix.
  • the above-mentioned first fixed matrix is located at the upper right corner of the above-mentioned base matrix.
  • the above-mentioned second fixed matrix is located at the lower right corner of the above-mentioned base matrix.
  • the number of rows of the above-mentioned core matrix is equal to the number of rows of the above-mentioned first fixed matrix.
  • the number of rows of the above-mentioned extended matrix is equal to the number of rows of the above-mentioned second fixed matrix
  • the number of columns of the above-mentioned extended matrix is equal to the number of columns of the above-mentioned core matrix.
  • the number of columns of the first fixed matrix is equal to the number of columns of the second fixed matrix.
  • the above-mentioned second fixed matrix is an identity matrix.
  • the first fixed matrix is an all-zero matrix.
  • the transmitting end stores one or more check matrices conforming to the base matrix, and different check matrices have different code lengths and/or code rates.
  • the transmitting end may select a check matrix that requires symbol code length and code rate from one or more stored check matrices.
  • the sending end accurately and quickly obtains the required check matrix based on the code length and code rate.
  • the sending end stores one or more basis matrices. Before executing step 801, the sending end can obtain a check matrix of the required code length and code rate by expanding a certain base matrix or a sub-matrix of a certain matrix based on the code rate and code length selected for LDPC encoding of the information bit sequence. .
  • the sending end stores a base matrix with a size of (12 ⁇ 22), and the first two columns of the base matrix are punctured columns; the sending end can expand the base matrix to obtain a size of ((12*34) ⁇ (22*34)) check matrix.
  • H′ represents the basis matrix
  • H′ MC represents the core matrix of size (p ⁇ q)
  • H′ IR represents the expansion matrix of size (r ⁇ q)
  • 0 p ⁇ r represents the size of (p ⁇ r).
  • An all-zero matrix, I r ⁇ r represents an identity matrix of size (r ⁇ r).
  • p, q, r are all integers greater than 0.
  • p is 6, q is 16, and r is 6.
  • p is 6, q is 17, and r is 5.
  • p is 6, q is 16, and r is 6.
  • p is 8, q is 18, r is 4.
  • H′ is a matrix of size (12 ⁇ 22) (basis matrix 1 below).
  • An example of a basis matrix is as follows:
  • the basis matrix is a matrix of size (12 ⁇ 22), that is, a matrix with 12 rows and 22 columns.
  • the specific parameter selection of the base matrix of 12 rows and 22 columns is a compromise between the implementation complexity of the base matrix and the decoding performance.
  • the smaller the basis matrix the lower the implementation complexity, but the degree of freedom in designing the basis matrix is also affected.
  • the base matrix can be expanded using a CPM of appropriate size according to the actual required code length.
  • the base matrix is not limited to a (12 ⁇ 22) matrix, and can also be a matrix of other sizes.
  • the size of the basis matrix can be selected based on the implementation complexity and decoding performance of the basis matrix.
  • the first two columns of the base matrix conform to or satisfy the following rules: the first two columns of the base matrix include regularly alternating “1 0" and “0 1", and the middle "1 0" and “0 1” include “1 1". Or, the first two columns of the base matrix conform to the following rules: one column includes “1 1 1 0" in order, and the other column includes the cyclic shift "1 0 1 1” of "1 1 1 0" in order. Since the first two columns of the base matrix conform to or satisfy the above rules, decoding using a check matrix that conforms to the base matrix can improve decoding performance.
  • the sending end sends the encoded bits.
  • the sending step may include but is not limited to: the sending end performs stream analysis (strean parser), constellation mapper (Constellation mapper), LDPC carrier mapping, or may include IDFT (Inverse Discrete Fourier Transform) based on the LDPC encoded bits. ) Inverse Fourier transform and so on, in order to send it out on the channel.
  • stream analysis stream analysis
  • constellation mapper Constellation mapper
  • LDPC carrier mapping or may include IDFT (Inverse Discrete Fourier Transform) based on the LDPC encoded bits. ) Inverse Fourier transform and so on, in order to send it out on the channel.
  • IDFT Inverse Discrete Fourier Transform
  • the receiving end receives the first channel from the transmitting end to receive the signal carrying the aforementioned encoded bits (for convenience of description, it may also be called the first codeword).
  • the sending end is a terminal device, and the receiving end is an access network device.
  • the sending end is the access network device, and the receiving end is the terminal device.
  • step 802 is as follows: the sending end broadcasts the first codeword.
  • the receiving end receives a first channel reception sequence (corresponding to the first codeword) from the transmitting end.
  • step 802 is as follows: the sending end sends the first codeword to the receiving end (corresponding to the unicast mode). The receiving end receives a first channel reception sequence (corresponding to the first codeword) from the transmitting end.
  • the receiving end determines the first log-likelihood ratio (LLR) sequence corresponding to the first channel received sequence, and decodes the first LLR sequence according to the check matrix.
  • LLR log-likelihood ratio
  • the receiving end may use any one of hard-decision decoding, soft-decision decoding, and hybrid decoding to decode the first LLR sequence according to the check matrix, which is not limited here.
  • the receiving end will output the decoding result.
  • Step 804 is optional but not required.
  • the decoding result can be output through an output device, such as a monitor, a display screen, an audio device, etc.
  • the receiving end decodes errors (or decoding fails)
  • the receiving end sends retransmission indication information to the sending end to request the sending end device to retransmit.
  • the receiving end saves the first LLR sequence for combined decoding with the subsequently received retransmitted LLR sequence.
  • the check matrix is expanded according to the base matrix or the sub-matrix of the base matrix, and check matrices with different code rates and/or code lengths can be obtained.
  • check matrices for LDPC encoding can not only be compatible with a variety of codes rate, and can obtain diversity gain, thereby improving coding performance.
  • Figure 9 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • the method interaction flow in Figure 9 is a possible implementation of the method described in Figure 8 .
  • the sending end punctures some information bits in the codeword obtained by LDPC encoding, which can improve the decoding performance.
  • the method includes:
  • the transmitting end performs LDPC encoding on the information bit sequence according to the check matrix to obtain the first codeword.
  • step 901 please refer to step 801.
  • the above-mentioned check matrix is expanded according to the base matrix or the sub-matrix of the above-mentioned base matrix.
  • the first codeword can be understood as the encoded bits obtained by LDPC encoding the information bit sequence at the transmitter according to the check matrix.
  • any row in the first two columns of the above-mentioned basis matrix includes at least one 1.
  • at least one of the two elements in each row is 1.
  • One of the first two columns of the basis matrix contains the following elements in sequence: 1 1 1 0 1 1 1 0 1 1 0.
  • the other column of the first two columns of the above basis matrix contains the following elements in sequence. includes the following elements: 1 0 1 1 1 0 1 1 1 0 1 1, 1 in the above-mentioned basis matrix corresponds to the cyclic displacement matrix CPM, and 0 in the above-mentioned basis matrix corresponds to an all-zero square matrix.
  • the first submatrix is a matrix with 12 rows and 2 columns.
  • the heavier columns of the first two columns of the base matrix can quickly transmit, exchange and decode the information between the codeword bits corresponding to each column in the check matrix (corresponding to the base matrix). Accelerate the overall decoding convergence speed of the system.
  • the first two columns of the above-mentioned basis matrix are perforated columns.
  • the first information bit in the above-mentioned first codeword does not participate in the transmission, and the above-mentioned first information bit is obtained by performing LDPC encoding according to the sub-matrix corresponding to the first two columns of the above-mentioned base matrix in the above-mentioned check matrix.
  • the first two columns of the basis matrix are punched nodes. Puncturing here refers to a common operation in channel coding in which the corresponding bits are not transmitted after encoding, and will not be described again here.
  • the first two columns of the check matrix that conform to the base matrix participate in encoding, but the information bits encoded based on these two columns do not participate in transmission.
  • the specific design principle of the perforated columns in the first two columns of the base matrix is: the heavier the perforated columns, the better their performance in long codes.
  • excessive column weight will cause subgraph structures such as short loops or trap sets to appear in the corresponding factor graph that harm decoding performance. Therefore, the weight and sparsity of the first two columns of the basis matrix of the present application are controlled by designing as shown in Example 1 above, and a compromise is made between short code and long code performance.
  • the first two columns with heavier weight in the base matrix are directly punched and do not participate in the transmission, because the two columns with heavier weight can quickly transmit, exchange and decode information between the codeword bits corresponding to each column in the matrix. Accelerate the overall decoding convergence speed of the system.
  • the column weights of these two columns are relatively heavy, if an error occurs in the corresponding bits during transmission, the error will quickly propagate to the remaining codeword bits, thereby adversely affecting the decoding. Therefore, these two columns participate in the actual encoding, but the corresponding bits are punctured and not transmitted.
  • the 17th column of the base matrix only includes one 1 and the 1 is located in the 7th row of the base matrix, at least one element in the first two columns of the 7th row of the base matrix is 0, and the 1st of the base matrix
  • the element of column 17 of row 7 is 1.
  • the first two columns of the basis matrix in Example 1 can be replaced with two columns that meet similar characteristics.
  • the first two columns of the basis matrix include regularly alternating "1 0" and “0 1", and "1 0" and “0 1” include “1 1” in between.
  • the first two columns of the base matrix conform to the following rules: each column includes “1 1 1 0” or the cyclic shift "1 0 1 1” of "1 1 1 0" in order.
  • the sending end sends the second codeword.
  • the receiving end receives the second channel reception sequence (corresponding to the second codeword) from the transmitting end.
  • the sending end is a terminal device, and the receiving end is an access network device.
  • the sending end is the access network device, and the receiving end is the terminal device.
  • step 902 please refer to step 802.
  • the sending end punches the first codeword to obtain the second codeword.
  • the sending end punctures the first information bits in the first codeword to obtain the second codeword; wherein, the above-mentioned first information bits are It is obtained by performing LDPC encoding on the sub-matrices corresponding to the first two columns of the above-mentioned base matrix in the above-mentioned check matrix.
  • the second codeword can be understood as the bits obtained by puncturing the encoded bits.
  • the receiving end determines the second LLR sequence corresponding to the second channel received sequence, and decodes the second LLR sequence according to the check matrix.
  • the decoding process can use hard-decision decoding, soft-decision decoding or hybrid decoding. The details will not be described again.
  • the receiving end will output the decoding result.
  • Step 904 is optional but not required.
  • step 904 please refer to step 804.
  • the sending end punctures some information bits in the codeword obtained by LDPC encoding, which can accelerate the overall decoding convergence speed of the system and avoid adverse effects on decoding.
  • Figure 10 is an interactive flow chart of another LDPC code encoding method provided by an embodiment of the present application.
  • the method interaction flow in Figure 10 is a possible implementation of the method described in Figure 8 .
  • the receiving end uses a check matrix with a lower code rate to perform LDPC encoding and decode the combined LLR sequence. Since retransmission adds incremental redundant check bits on the basis of the information bit sequence and reduces the channel coding rate, it can improve the decoding success rate of the receiving device, reduce the number of retransmissions, reduce retransmission delays, and improve translation code performance.
  • the transmitting end performs LDPC encoding on the information bit sequence according to the first check matrix to obtain the first codeword.
  • step 1001 please refer to step 801.
  • the above-mentioned first check matrix is obtained by extending the base matrix or the sub-matrix of the above-mentioned base matrix.
  • the first check matrix used by the sending end to perform step 1001 may be the same as the check matrix used to perform step 801.
  • the sending end sends the second codeword.
  • the receiving end receives the second channel reception sequence (corresponding to the second codeword) from the transmitting end.
  • the second channel reception sequence (corresponding to the second codeword) from the transmitting end.
  • step 1002 please refer to step 802.
  • the receiving end determines the second LLR sequence corresponding to the second channel received sequence, and decodes the second LLR sequence according to the first check matrix.
  • step 1003 please refer to step 803.
  • the receiving end sends retransmission instruction information to the sending end device.
  • the sending end receives the retransmission indication information from the receiving end.
  • a decoding error means that the receiving end decodes the second LLR sequence based on the first check matrix and fails to obtain a correct decoding result. In other words, none of the decoding results obtained by decoding the second LLR sequence at the receiving end can pass the check of the first check matrix.
  • the transmitting end performs LDPC encoding on the information bit sequence according to the second check matrix to obtain the third codeword.
  • the above-mentioned second check matrix is obtained by extending the base matrix or the sub-matrix of the above-mentioned base matrix.
  • the above-mentioned first check matrix and the above-mentioned second check matrix can be obtained by extending the same base matrix.
  • the code rate of the above-mentioned second check matrix is lower than the code rate of the above-mentioned first check matrix.
  • the sending end sends the fourth codeword to the receiving end.
  • the receiving end receives the third channel reception sequence (corresponding to the fourth codeword) from the transmitting end.
  • the sending end punches the third codeword to obtain the fourth codeword.
  • the transmitting end punctures the second information bits in the third codeword to obtain the fourth codeword; wherein the second information bits are based on the first two bits of the second check matrix corresponding to the base matrix.
  • the column sub-matrix is obtained by LDPC encoding.
  • the receiving end determines the third LLR sequence corresponding to the third channel received sequence, and decodes the combined LLR sequence according to the second check matrix.
  • the combined LLR sequence is obtained by combining the second LLR sequence and the third LLR sequence at the receiving end.
  • the second LLR sequence and the third LLR sequence are combined bitwise.
  • the second LLR sequence and the third LLR sequence are the same
  • the LLR values at the position index are merged, and the LLR values at different index positions continue to be retained.
  • the decoding result is output. If the receiving end fails to decode the combined LLR sequence according to the second check matrix, the next retransmission is performed. By analogy, until the decoding is successful or the set maximum number of retransmissions is reached, the decoding fails.
  • the sending end encodes the information bit sequence according to the check matrix corresponding to a lower code rate, which can increase the number of redundant bits and reduce the code rate of the encoded codeword. Since retransmission adds incremental redundant check bits on the basis of the information bit sequence and reduces the channel coding rate, it can improve the decoding success rate of the receiving device, reduce the number of retransmissions, reduce retransmission delays, and improve translation code performance.
  • the LDPC encoding method provided by this application has been described in detail above. According to the encoding method provided by this application, it can be compatible with multiple code rates. The following focuses on the basis matrices provided in this application, as well as some examples of check matrices extended by these basis matrices.
  • the base matrix provided by this application can be expanded to a check matrix of LDPC codes of various code lengths as needed.
  • the check matrix of the LDPC code of various code lengths can be obtained. That is to say, a series of check matrices of LDPC codes can be obtained from a base matrix.
  • the expansion sizes of these check matrices and the expansion factors of each CPM can be different, but they correspond to the same base matrix.
  • the basis matrix obtained by various row and column permutations of the basis matrix provided in this application is equivalent to the basis matrix provided in this application. That is to say, the basis matrix obtained by permuting the rows and columns of the basis matrix provided by this application also belongs to the basis matrix protected by this application.
  • Various row and column permutations of the base matrix refer to the replacement of one or more elements in the base matrix with other elements. That is, one or more elements in a base matrix are equivalent to the base matrix when replaced with other elements. In other words, replacing one or more elements in the base matrix with other elements can also be regarded as the base matrix.
  • the row-column permutation of the base matrix may include any of the following: one or more elements in a row of the base matrix are replaced with other elements, one or more elements in a column of the base matrix are replaced with other elements, the base matrix Multiple elements located in different rows in the base matrix are replaced with other elements, multiple elements located in different columns in the base matrix are replaced with other elements, the positions of multiple rows in the base matrix are changed, and the positions of multiple columns in the base matrix are changed, For example, the positions of two columns in the basis matrix are interchanged.
  • Replacement of an element by another element means that the element is replaced by any element that is different from that element.
  • one or more elements 0 in the basis matrix are replaced with elements 1.
  • one or more elements 1 in the basis matrix are replaced with elements.
  • Figure 11 is an example of a basis matrix provided by this application.
  • the matrix in the rectangular box 1101 is the core matrix of the base matrix
  • the matrix in the rectangular box 1102 is the extended matrix of the base matrix
  • the matrix in the rectangular box 1103 is a sub-matrix of the base matrix.
  • the lower right corner of is the unit matrix.
  • This application also protects the local matrices (ie sub-matrices) of the basis matrix provided by this application, such as the matrix in the rectangular box 1101, the matrix in the rectangular box 1102 or the matrix in the rectangular box 1103.
  • the basis matrix provided by this application is a (12 ⁇ 22) two-dimensional matrix.
  • the first two columns of the basis matrix provided by this application are perforated columns.
  • the base matrix can be expanded to obtain a check matrix with different code rates, which can effectively support multiple code rates, such as 1/2 to 2/3.
  • this application provides an example of a check matrix.
  • the check matrix in Figure 12 can be obtained by extending the base matrix shown in Figure 11 using a (34 ⁇ 34) CPM.
  • Matrix in rectangular box 1201 Corresponds to the matrix in the rectangular box 1101 in Figure 11.
  • the base matrix provided by this application can be expanded into a check matrix for LDPC codes of various code lengths as needed. It can be seen that excellent error control performance can be obtained at each code length using a single basis matrix. Therefore, the base matrix provided by this application can be flexibly expanded to obtain check matrices with different code rates and code lengths.
  • An example of a coding is as follows: for the basis matrix (i.e., check matrix) expanded by CPM of size (Z ⁇ Z), the information bit sequence can first be divided into sub-information sequences of size (10 ⁇ Z), where The part that is less than (10 ⁇ Z) can be filled with 0 at any position in the sub-information sequence. Generally, the 0-filled part is located at the end of the sub-information sequence (that is, the shortening operation in traditional channel coding). Subsequently, regardless of the code rate required by the system (i.e., the transmitter), the portion of the expanded basis matrix corresponding to the rectangular frame 1201 is first used for encoding.
  • the encoding method is similar to the LDPC encoding method in 802.11n.
  • the remaining parts of the expanded basis matrix can be used to continue to compile the remaining check bit sequence.
  • the remaining check bit sequence encoding method can be recursively operated and encoded.
  • the specific method is similar to the existing 5G NR LDPC encoding method.
  • the information bits corresponding to the first two columns of the base matrix are punctured and not transmitted, and then the supplementary 0 bits during encoding are removed, and finally the codeword bit sequence required for system transmission is obtained.
  • the specific coding process is shown in Figure 2.
  • the information bits corresponding to the first two columns of the base matrix are encoded using the extended parts of the first two columns of the base matrix.
  • FIG 13 is an example of another basis matrix provided by this application.
  • the matrix in the rectangular box is matrix 1.
  • R10 indicates that the maximum number of 1s in each row of matrix 1 does not exceed 10.
  • C04 indicates that the number of 1s in each row of matrix 1 does not exceed 10.
  • the maximum column weight (excluding the first two columns) does not exceed 4
  • C08 indicates that the maximum column weight of the base matrix does not exceed 8
  • R09 indicates that the maximum row weight of the base matrix except matrix 1 does not exceed 9.
  • C04 indicates that the column weights of the 3rd to 16th columns of matrix 1 do not exceed 4.
  • R09 indicates that the row weights of rows 7 to 12 of the base matrix do not exceed 9.
  • C04_R10_C08_R09 is only an example of the row and column weight constraints of a base matrix, and the meanings of other row and row weight constraints are similar to the meanings of C04_R10_C08_R09.
  • Thr is the decoding threshold when the basis matrix of the present application takes 1/2 of the phase code rate.
  • the decoding threshold refers to the minimum Eb/N0 required for successful decoding of the LDPC code corresponding to the base matrix when the code length is infinite.
  • Gap refers to the distance between the decoding threshold and the corresponding Eb/N0 of the corresponding code rate channel capacity (in terms of expressed in dB).
  • Eb represents the signal energy averaged to each bit
  • N0 represents the power spectral density of the noise.
  • Thr_2 refers to the decoding threshold when the base matrix of this application takes the code rate 2/3 part
  • Gap_2 refers to the distance (expressed in dB) between the decoding threshold and the corresponding Eb/N0 of the corresponding code rate channel capacity.
  • Thr 0.5418dB
  • Gap 0.3799dB
  • Thr_2 1.3982dB
  • Gap_2 0.3159dB.
  • the decoding threshold corresponding to the base matrix For long codes, the smaller the decoding threshold (i.e. Thr and Thr_2) corresponding to the base matrix, the better the decoding performance of the check matrix that conforms to the base matrix. Similarly, for long codes, the decoding threshold corresponding to the basis matrix corresponds to the corresponding code rate channel capacity. The smaller the distance between Eb/N0 (ie Gap and Gap_2), the better the decoding performance of the check matrix that conforms to the base matrix.
  • the decoding threshold corresponding to each base matrix as well as the distance between the decoding threshold and the corresponding code rate channel capacity corresponding Eb/N0 are small, so it is consistent with this
  • the decoding performance of the check matrix of the base matrix is better.
  • the first two columns of each basis matrix have higher weights. For short codes, too heavy column weight will cause subgraph structures such as short loops or trap sets to appear in the corresponding factor graph that harm decoding performance.
  • the first two columns with heavier weights in the base matrix are directly punched and do not participate in transmission, which can avoid excessive column weights from affecting the decoding performance of short codes. Therefore, the basis matrix in this application can ensure the decoding performance of both long codes and short codes, that is, a good compromise between the performance of short codes and long codes is achieved.
  • any element other than "-1" in the check matrix in the above example represents a (34 ⁇ 34) CPM.
  • "-1" in the check matrix represents an all-0 square matrix of size (34 ⁇ 34).
  • the base matrix is expanded using different expansion factors to obtain check matrices of different sizes. For example, a (68 ⁇ 68) CPM is used to expand the base matrix. In practical applications, CPM of any size can be used to expand the base matrix as needed to obtain the required check matrix.
  • the basis matrix 1 to the basis matrix 15 are only some examples of the basis matrices provided in this application, but not all examples. It should be understood that the basis matrix obtained by permuting the rows and columns of the basis matrix provided by this application also belongs to the basis matrix protected by this application. Similarly, the check matrix obtained by extending the basis matrix shown above is only a partial example, not all examples.
  • Figure 14 is a performance comparison diagram of an LDPC code provided by this application.
  • the abscissa represents the signal noise ratio (SNR), and the ordinate represents the block error rate (BLER), which is the block error rate.
  • BLER block error rate
  • New UWB LDPC represents the LDPC code of this application.
  • New UWB LDPC (340,680) vs. WLAN LDPC (324,648) Performance comparison between the LDPC code (340,680) of this application and WLAN LDPC (324,648) at a code rate of 1/2, where (k, n) k refers to the number of information bits before encoding, and n refers to the number of codeword sequence bits after encoding.
  • the LDPC code of this application can obtain about 0.25dB performance gain.
  • the base matrix (base matrix 1) of the LDPC code in this application contains 76 CPMs, while the base matrix corresponding to the WLAN LDPC code contains 88 CPMs. Therefore, the complexity of the LDPC code of this application is low.
  • New UWB LDPC (340,510) vs. two WLAN LDPC (324,486): performance comparison when the code rate R 2/3. Comparison of performance when the LDPC code of this application is punctured to (340,510) and WLAN LDPC (324,486) when the code rate is 2/3.
  • Figure 15A is a schematic diagram of an LDPC code punching provided by this application.
  • Figure 15B is a schematic diagram of shortening and puncturing an LDPC code provided by this application.
  • New UWB LDPC (160,320) vs. WLAN LDPC (160,320) at the code rate R 1/2:
  • This application Please compare the performance when the LDPC code and the WLAN LDPC code with a code rate of 1/2 are simultaneously shortened and punched to (160,320). Among them, the WLAN LDPC code is shortened and punched at the same time, as shown in Figure 15C.
  • Figure 15C is a schematic diagram of another LDPC code shortening and puncturing provided by this application.
  • FIG 16 is a schematic structural diagram of a communication device 1600 provided by an embodiment of the present application.
  • the communication device 1600 can correspond to the functions or steps implemented by the sending end in each of the above method embodiments, and can also correspond to the functions or steps implemented by the receiving end in each of the above method embodiments.
  • the communication device may include a processing module 1610 and an interface module 1620.
  • a storage unit may also be included, which may be used to store instructions (code or programs) and/or data.
  • the processing module 1610 and the interface module 1620 can be coupled with the storage unit.
  • the processing module 1610 can read the instructions (code or program) and/or data in the storage unit to implement the corresponding method.
  • Each of the above units can be set up independently or partially or fully integrated.
  • the interface module 1620 may include a sending module and a receiving module.
  • the sending module can be a transmitter
  • the receiving module can be a receiver.
  • the entity corresponding to the interface module 1620 may be a transceiver or a
  • the communication device 1600 can correspondingly implement the behaviors and functions of the sending end in the above method embodiments.
  • the communication device 1600 may be a transmitting end, or may be a component (such as a chip or circuit) used in the transmitting end.
  • the interface module 1620 can, for example, be used to perform all receiving or sending operations performed by the sending end in the embodiments of FIG. 8, FIG. 9, and FIG. 10, such as step 802 in the embodiment shown in FIG. 8, and step 802 in the embodiment shown in FIG. 9. Step 902 in the embodiment, step 1002, step 1004, step 1006 in the embodiment shown in Figure 10, and/or other processes used to support the technology described herein.
  • the processing module 1610 is used to perform all operations performed by the sending end in the embodiments of Figures 8, 9, and 10 except for the sending and receiving operations, such as step 801 in the embodiment shown in Figure 8, as shown in Figure 9 Step 901 in the embodiment, Step 1001 and Step 1005 in the embodiment shown in Figure 10 .
  • the communication device 1600 can correspondingly implement the behaviors and functions of the receiving end in the above method embodiments.
  • the communication device 1600 may be a receiving end, or may be a component (such as a chip or circuit) used in the receiving end.
  • the interface module 1620 can, for example, be used to perform all receiving or sending operations performed by the receiving end in the embodiments of FIG. 8, FIG. 9, and FIG. 10, such as step 802 in the embodiment shown in FIG. 8, and step 802 in the embodiment shown in FIG. 9. Step 902 in the embodiment, step 1002, step 1004, step 1006 in the embodiment shown in Figure 10, and/or other processes used to support the technology described herein.
  • the processing module 1610 is used to perform all operations performed by the receiving end in the embodiments of FIG. 8, FIG.
  • FIG. 9 except for the sending and receiving operations, such as steps 803 and 804 in the embodiment shown in FIG. 8, FIG. Steps 903 and 904 in the embodiment shown in FIG. 9 and steps 1003, 1004 and 1007 in the embodiment shown in FIG. 10 .
  • Figure 17 is a schematic structural diagram of another communication device 170 provided by an embodiment of the present application.
  • the communication device in Figure 17 may be the above-mentioned transmitter, or may be the above-mentioned receiver.
  • the communication device 170 includes at least one processor 1710 and a transceiver 1720 .
  • the processor 1710 and the transceiver 1720 may be used to perform functions or operations performed by the initiator, etc.
  • the transceiver 1720 performs, for example, all receiving or transmitting operations performed by the transmitting end in the embodiments of FIG. 8, FIG. 9, and FIG. 10.
  • the processor 1710 is, for example, configured to perform all operations performed by the sending end in the embodiments of FIG. 8, FIG. 9, and FIG. 10 except for the sending and receiving operations.
  • the processor 1710 and the transceiver 1720 may be used to perform functions or operations performed by the receiving end, etc.
  • the transceiver 1720 for example, performs all reception or reception performed by the receiving end in the embodiments of FIG. 8, FIG. 9, and FIG. Send operation.
  • the processor 1710 is, for example, configured to perform all operations performed by the receiving end in the embodiments of FIG. 8, FIG. 9, and FIG. 10 except for the sending and receiving operations.
  • Transceiver 1720 is used to communicate with other devices/devices over transmission media.
  • the processor 1710 uses the transceiver 1720 to send and receive data and/or signaling, and is used to implement the method in the above method embodiment.
  • the processor 1710 can implement the function of the processing module 1610, and the transceiver 1720 can implement the function of the interface module 1620.
  • the communication device 170 may also include at least one memory 1730 for storing program instructions and/or data.
  • Memory 1730 and processor 1710 are coupled.
  • the coupling in the embodiment of this application is an indirect coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information interaction between devices, units or modules.
  • Processor 1710 may cooperate with memory 1730.
  • Processor 1710 may execute program instructions stored in memory 1730 . At least one of the at least one memory may be included in the processor.
  • connection medium between the above-mentioned transceiver 1720, processor 1710 and memory 1730 is not limited in the embodiment of the present application.
  • the memory 1730, the processor 1710 and the transceiver 1720 are connected through a bus 1740 in Figure 17.
  • the bus is represented by a thick line in Figure 17.
  • the connection methods between other components are only schematically explained. , is not limited.
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 17, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which may implement or Execute each method, step and logical block diagram disclosed in the embodiment of this application.
  • a general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware processor for execution, or can be executed by a combination of hardware and software modules in the processor.
  • Figure 18 is a schematic structural diagram of another communication device 180 provided by an embodiment of the present application.
  • the communication device shown in FIG. 18 includes a logic circuit 1801 and an interface 1802 .
  • the processing module 1610 in Figure 16 can be implemented by the logic circuit 1801, and the interface module 1620 in Figure 16 can be implemented by the interface 1802.
  • the logic circuit 1801 can be a chip, a processing circuit, an integrated circuit or a system on chip (SoC) chip, etc.
  • SoC system on chip
  • the interface 1802 can be a communication interface, an input-output interface, etc.
  • the logic circuit and the interface may also be coupled to each other. The embodiments of this application do not limit the specific connection methods of the logic circuits and interfaces.
  • the logic circuit and interface may be used to perform the above functions or operations performed by the sending end, etc.
  • the logic circuit and interface may be used to perform the above functions or operations performed by the receiving end, etc.
  • This application also provides a computer-readable storage medium, which stores computer programs or instructions.
  • the computer program or instructions When the computer program or instructions are run on a computer, the computer is caused to execute the method of the above embodiments.
  • the computer program product includes instructions or computer programs. When the instructions or computer programs are run on a computer, the methods in the above embodiments are executed.
  • This application also provides a communication system, including the above-mentioned sending end and the above-mentioned receiving end.

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Abstract

本申请公开了一种LDPC的编译码方法和相关装置，本申请应用于支持IEEE802.11ax下一代Wi-Fi协议，Wi-Fi8等802.11系列协议的无线局域网系统，还可以应用于基于UWB的无线个人局域网系统。该方法包括：根据校验矩阵，对信息比特序列进行低密度奇偶校验LDPC编码，得到第一码字；校验矩阵符合基矩阵，基矩阵满足下述之一：基矩阵的前两列中的每行至少包括一个1，或者，基矩阵的前两列中包括规律交替的"1 0"和"0 1"，且"1 0"和"0 1"中间包括"1 1"；发送第一码字。校验矩阵符合基矩阵，可加速系统的译码整体收敛速度。

Description

LDPC的编译码方法和相关装置
本申请要求于2022年05月10日提交中国专利局、申请号为202210505542.9、申请名称为“LDPC的编译码方法和相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及LDPC的编译码方法和相关装置。
背景技术
IEEE802.11n/ac/ax/be等无线局域网(wireless local area networks，WLAN)传输标准主要研究在大带宽场景下提升用户的体验，包括提升用户平均吞吐量以及电池类供电设备的能量使用效率。60GHz大带宽场景需要支持在有限的频率和功率资源上实现数据、视频等业务的高速可靠传输，因此需要高可靠性和高效率的信道编译码方案。在信道编码领域，Turbo码和低密度奇偶校验(low-density parity-check,LDPC)码是目前应用最成熟和广泛的两种信道编码方法，它们都有接近香农(Shannon)限的性能。与Turbo码相比，LDPC码具有：不需要深度交织器即可获得很好的误码性能；具有更好的误帧率性能；错误平层大大降低；支持并行译码，译码延时小等优点。
因此，LDPC码已成为IEEE802.11n/ac/ax等低频短距WLAN通信系统的标准信道编码方案，在IEEE802.11ax大于等于40MHz带宽情况下成为必选信道编码方案。基于此，可考虑针对下一代WLAN标准或超宽带(ultra wide band，UWB)设计新的LDPC码，以进一步提高下一代WLAN系统或UWB系统的可靠性和系统性能。
发明内容
本申请实施例公开了一种能够提升译码性能，并支持多种码率。
第一方面，本申请实施例提供了一种LDPC码的编码方法，该方法包括：根据校验矩阵，对信息比特序列进行低密度奇偶校验LDPC编码，得到第一码字；所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：所述基矩阵的前两列中的每行至少包括一个1，或者，所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”；或者，所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”；发送所述第一码字。
本申请实施例中，校验矩阵符合基矩阵，该基矩阵的设计使得符合该基矩阵的校验矩阵可将信息快速在校验矩阵中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。
第二方面，本申请实施例提供了另一种LDPC码的编码方法，该方法包括：接收端确定第一信道接收到的信号对应的第一对数似然比序列，并根据校验矩阵，对第一LLR序列进行译码；其中，所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：所述基矩阵的前两列中的每行至少包括一个1，或者，所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且 “10”和“0 1”中间包括“1 1”；或者，所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”。
本申请实施例中，校验矩阵符合基矩阵，该基矩阵的设计使得符合该基矩阵的校验矩阵可将信息快速在校验矩阵中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。
在第一方面和第二方面的一种可能的实现方式中，所述基矩阵的前两列中的一列包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，所述基矩阵的前两列中的另一列包括如下元素：1 0 1 1 1 0 1 1 1 0 1 1，所述基矩阵中的1对应于循环位移矩阵CPM，所述基矩阵中的0对应于全零方阵。
在该实现方式中，基矩阵的前两列中的一列包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，该基矩阵的前两列中的另一列包括如下元素：1 0 1 1 1 0 1 1 1 0 1 1；能够在编码复杂度和译码性能之间获得较好的折中。
第三方面，本申请实施例提供一种通信装置，该通信装置具有实现上述第一方面方法实施例中的行为的功能。该通信装置可以是通信设备，也可以是通信设备的部件(例如处理器、芯片、或芯片系统等)，还可以是能实现全部或部分该通信设备的功能的逻辑模块或软件。该通信装置的功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，该硬件或软件包括一个或多个与上述功能相对应的模块或单元。在一种可能的实现方式中，该通信装置包括接口模块和处理模块，其中：所述处理模块，用于根据校验矩阵，对信息比特序列进行低密度奇偶校验LDPC编码，得到第一码字；所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：所述基矩阵的前两列中的每行至少包括一个1，或者，所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”；或者，所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”；所述接口模块，用于发送所述第一码字。
本申请实施例中，校验矩阵符合基矩阵，该基矩阵的设计使得符合该基矩阵的校验矩阵可将信息快速在校验矩阵中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。
第四方面，本申请实施例提供一种通信装置，该通信装置具有实现上述第二方面方法实施例中的行为的功能。该通信装置可以是通信设备，也可以是通信设备的部件(例如处理器、芯片、或芯片系统等)，还可以是能实现全部或部分该通信设备的功能的逻辑模块或软件。该通信装置的功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，该硬件或软件包括一个或多个与上述功能相对应的模块或单元。在一种可能的实现方式中，该通信装置包括接口模块和处理模块，其中：所述接口模块，用于接收来自发送端的信号；所述处理模块，用于确定第一信道接收到的信号对应的第一对数似然比序列，并根据校验矩阵，对第一LLR序列进行译码；其中，所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：所述基矩阵的前两列中的每行至少包括一个1，或者，所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”；或者，所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”。
本申请实施例中，校验矩阵符合基矩阵，该基矩阵的设计使得符合该基矩阵的校验矩阵可将信息快速在校验矩阵中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。
在第三方面和第四方面的一种可能的实现方式中，所述基矩阵的前两列中的一列包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，所述基矩阵的前两列中的另一列包括如下元素：1 0 1 1 1 0 1 1  1 0 1 1，所述基矩阵中的1对应于循环位移矩阵CPM，所述基矩阵中的0对应于全零方阵。
在该实现方式中，基矩阵的前两列中的一列包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，该基矩阵的前两列中的另一列包括如下元素：1 0 1 1 1 0 1 1 1 0 1 1；能够在编码复杂度和译码性能之间获得较好的折中。
第五方面，本申请实施例提供另一种通信装置，该通信装置包括处理器，该处理器与存储器耦合，该存储器用于存储程序或指令，当该程序或指令被该处理器执行时，使得该通信装置执行上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，当该程序或指令被该处理器执行时，使得该通信装置执行上述第二方面或第二方面的任意可能的实现方式所示的方法。
本申请实施例中，在执行上述方法的过程中，上述方法中有关发送信息(或信号)的过程，可以理解为基于处理器的指令进行输出信息的过程。在输出信息时，处理器将信息输出给收发器，以便由收发器进行发射。该信息在由处理器输出之后，还可能需要进行其他的处理，然后到达收发器。类似的，处理器接收输入的信息时，收发器接收该信息，并将其输入处理器。更进一步的，在收发器收到该信息之后，该信息可能需要进行其他的处理，然后才输入处理器。
对于处理器所涉及的发送和/或接收等操作，如果没有特殊说明，或者，如果未与其在相关描述中的实际作用或者内在逻辑相抵触，则可以一般性的理解为基于处理器的指令输出。
在实现过程中，上述处理器可以是专门用于执行这些方法的处理器，也可以是执行存储器中的计算机指令来执行这些方法的处理器，例如通用处理器等。例如，处理器还可以用于执行存储器中存储的程序，当该程序被执行时，使得该通信装置执行如上述第一方面或第一方面的任意可能的实现方式所示的方法。
在一种可能的实现方式中，存储器位于上述通信装置之外。在一种可能的实现方式中，存储器位于上述通信装置之内。
在一种可能的实现方式中，处理器和存储器还可能集成于一个器件中，即处理器和存储器还可能被集成于一起。
在一种可能的实现方式中，通信装置还包括收发器，该收发器，用于接收信号或发送信号等。
第六方面，本申请提供另一种通信装置，该通信装置包括处理电路和接口电路，该接口电路用于获取数据或输出数据；处理电路用于执行如上述第一方面或第一方面的任意可能的实现方式所示的相应的方法，或者，处理电路用于执行如上述第二方面或第二方面的任意可能的实现方式所示的相应的方法。
第七方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，该计算机程序包括程序指令，该程序指令被执行时使得计算机执行如上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，该程序指令被执行时使得计算机执行如上述第二方面或第二方面的任意可能的实现方式所示的方法。
第八方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序，该计算机程序包括程序指令，该程序指令被执行时使得计算机执行如上述第一方面或第一方面的任意可能的实现方式所示的方法，或者，该程序指令被执行时使得计算机执行如上述第二方面或第二方面的任意可能的实现方式所示的方法。
第九方面，本申请提供一种通信系统，包括上述第三方面或第三方面的任意可能的实现方式所述的通信装置、上述第四方面或第四方面的任意可能的实现方式所述的通信装置。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1为LDPC码的校验矩阵H的一个示例；
图2为LDPC码的校验矩阵H的Tanner图；
图3示出了LDPC码的编码过程的示例；
图4为LDPC编码流程中缩短操作部分的示意图；
图5为对HMC进行扩展得到的母矩阵的一个示例；
图6示出了由大小为(12×22)的基矩阵扩展得到的一个校验矩阵的示例；
图7为适用于本申请实施例的系统架构图；
图8为本申请提供的一种LDPC码的编码方法交互流程图；
图9为本申请实施例提供的另一种LDPC码的编码方法交互流程图；
图10为本申请实施例提供的另一种LDPC码的编码方法交互流程图；
图11为本申请提供的一种基矩阵的示例；
图12为本申请提供的一个校验矩阵的示例；
图13为本申请提供的另一种基矩阵的示例；
图14为本申请提供的一种LDPC码的性能对比示意图；
图15A为本申请提供的一种LDPC码打孔的示意图；
图15B为本申请提供的一种LDPC码缩短和打孔的示意图；
图15C为本申请提供的另一种LDPC码缩短和打孔的示意图；
图16为本申请实施例提供的一种通信装置1600的结构示意图；
图17为本申请实施例提供的另一种通信装置170的结构示意图；
图18为本申请实施例提供的另一种通信装置180的结构示意图。
具体实施方式
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等仅用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备等，没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元等，或可选地还包括对于这些过程、方法、产品或设备等固有的其它步骤或单元。
本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”、“举例来说”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“举例来说”或者“例如”等词旨在以具体方式呈现相关概念。
在本文中提及的“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对 本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括复数表达形式，除非其上下文中明确地有相反指示。还应当理解，本申请中使用的术语“和/或”是指并包含一个或多个所列出项目的任何或所有可能组合。例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。本申请中使用的术语“多个”是指两个或两个以上。
可以理解，在本申请各实施例中，“A对应的B”表示A与B存在对应关系，根据A可以确定B。但还应理解，根据(或基于)A确定(或生成)B并不意味着仅仅根据(或基于)A确定(或生成)B，还可以根据(或基于)A和/或其它信息确定(或生成)B。
为了便于理解本申请的方案，首先对本申请中LDPC码的相关概念进行介绍。
LDPC码全名是低密度奇偶校验码，从字面意思理解，就是一种具有低密度性质的奇偶校验码。这里的低密度指的是LDPC码的校验矩阵具有低密度。因此，要弄明白LDPC码是什么，首先要弄明白奇偶校验码和校验矩阵以及低密度这三个概念。
1.奇偶校验码
奇偶校验码是一种通过增加冗余位使得码字中"1"的个数恒为奇数或偶数的编码方法,它是一种检错码。奇偶校验码常用于0-1的二元域上的数字编码，在码字的最后添加一位或者若干位(校验位)，通过码字中1的个数是奇数还是偶数来判断码字在传输前后是否出错。比如100这个码字，采用奇偶校验，那么校验位就可以取1，这时候满足所有码字加起来(异或)的值s为0，即1001。如果传输后变为了1101，错误了一个信息位(可称为比特位)，那么这时候s为1，可以判断传输出错。应理解，如果错误的是偶数个信息位，那么算法失效。因此，进一步的，可以设置多个校验位。例如，1101这个四位码字，可以分组，使用校验位的第一位来校验信息位的第一位和第二位(即信息位的前两位11)。例如，使信息位的前两位的和为0，那么校验位的第一位就应该取0。同理，校验位的第二位可以检验码字1101的后两位信息位，那么就校验位的第二位取1。因此，编码后的码字是110101。这其实就是LDPC码的校验思想，即“PC”的含义。可见，LDPC码是一种分组码，并且使用的其实就是奇偶校验。如果再加上低密度的特性，就能得到LDPC码。
2.校验矩阵和生成矩阵
以上面的1101码字举例，码字的信息位和校验位之间的校验关系可以写为矩阵的形式。记信息位为c1,c2,c3,c4，校验位为p1,p2。c＝[c1,c2,c3,c4]，x＝[c1,c2,c3,c4,p1,p2]。这里c和x分别是编码前后的码字。在码字1101的举例中，码字1101的信息位和校验位之间的校验关系可表示为如下线性关系：c1+c2+p1＝0，c3+c4+p2＝0。该线性关系可以写为如下公式：
x·HT＝s＝0  (1)；
其中，H为：s＝(0,0)。这里的H就是校验矩阵，s为校验子，HT表示H的转置。公式(1)的思想就是原来的码字(未编码的码字)c经过生成矩阵G(G由H决定)编码后，得到的发送码字x需要满足x·HT＝0。为了方便的判断这个结果是不是0，我们引入校验子s的概念，只要s全为0，那么传输就是没问题的。本申请中，“·”表示矩阵乘法运算，“A·B”表示矩阵A和矩阵B的矩阵相乘的乘积。
c经过生成矩阵G编码得到的发送码字x可满足如下公式：
x＝c·G；  (2)；
其中，c表示未编码的码字(或者说比特序列)，G表示生成矩阵。G和HT彼此正交， 即G·HT＝0。生成矩阵可由校验矩阵经过变换而得来。也就是说，知道了校验矩阵，就可得到该校验矩阵对应的生成矩阵。c可称为信息码字，x可称为发送码字。公式(2)表明发送码字是由信息码字与生成矩阵相乘得到的。
3.LDPC码的低密度性质
LDPC码的低密度性质指的就是LDPC码的校验矩阵中为1的个数很少。LDPC码是一种线性分组码，其校验矩阵是一种稀疏矩阵。LDPC码的校验矩阵中零元素的个数远远多于非零元素的个数。或者说，校验矩阵的行重(即每行中的1的个数)和列重(即每列中的1的个数)与LDPC码的码长相比是很小的数。
4.Tanner图
Tanner在1981年将LDPC码的码字用图的方式表示了出来。现在将这种图称为Tanner图，Tanner图和校验矩阵一一对应。Tanner图由两类顶点组成，一类顶点为变量节点，代表码字比特，另一类顶点为校验节点，代表校验约束关系。每个校验节点代表一个校验约束关系，下面结合图1和图2进行说明。
参见图1，图1为LDPC码的校验矩阵H。图1中，{Vi}表示变量节点集，{Ci}表示校验节点集。校验矩阵H的每行对应一个校验方程，每列对应一个码字比特。图1中，变量节点为8个，校验节点为4个。如果一个码字比特包含在相应的校验方程中，就用一条连线将所涉及的变量节点和校验节点连起来，得到Tanner图。
参见图2，图2为LDPC码的校验矩阵H的Tanner图。如图2所示，Tanner图表示的即是LDPC码的校验矩阵。例如，对于大小为m行n列的校验矩阵H，Tanner图中包含两类节点，分别为n个变量节点(也可称为信息节点或比特节点)和m个校验节点，m、n均为大于0的整数。其中，上述n个变量节点分别和校验矩阵H的n个列对应，上述m个校验节点分别和校验矩阵H的m个行对应。Tanner图中的循环是由互相连接在一起的顶点组成，循环以这群顶点中的一个顶点同时作为起点和终点，且只经过每个节点一次。循环的长度定义为它所包含的连线的数量，而图形的围长也可以称作图形的尺寸，定义为图中最小的循环长度，如图2中，围长为6，如图2中加黑连线所示。
5.LDPC码的编码
基于上面的描述可知，发送码字是由信息码字与生成矩阵相乘得到的，生成矩阵可由校验矩阵经过变换而得来。因此，整个LDPC码编码过程其实就是一个校验矩阵的构造过程。参见图3，图3示出了LDPC码的编码过程的示例。如图3所示，校验矩阵H通过高斯消元方可变成H＝[I P]；由G·HT＝0，得到生成矩阵G＝[-PT I]；信息码字c经过生成矩阵G编码得到发送码字x，即x＝c·G。其中，I表示信息比特部分，P表示校验比特部分，x为发送码字，
6.LDPC码的译码
LDPC码译码过程是通过校验位(或者称为校验码元)和信息位(或者称为信息码元)之间的校验规律在变量节点与校验节点之间不停进行消息迭代直至找到满足x·HT＝的码字，输出x即为解码后的码字。LDPC码的译码算法包括以下三大类：硬判决译码，软判决译码和混合译码。
7.准循环低密度奇偶校验(quasi-cyclic low density parity check，QC-LDPC)码
IEEE 802.11ac以及802.11ax标准中采用的LDPC码为QC-LDPC码。QC-LDPC码是一类结构化的LDPC码。由于其校验矩阵的独特结构，编码时可以利用简单的反馈移位寄存器实现，降低LDPC码的编码复杂度。
IEEE802.11ac标准中码长N＝1944、码率R＝5/6的LDPC码的校验矩阵H如下：
校验矩阵H为一个大小为(4×24)的矩阵。校验矩阵H中的每个元素(除“-”之外)表示一个z＝N/24阶方阵。其中，校验矩阵中的“-”代表(z×z)的全零方阵。校验矩阵中的每一项Pi表示一个(z×z)的循环置换矩阵，i(0≤i≤z-1)表示循环移位值。以校验矩阵中的第一行第一列的元素为例，Pi＝13。
例如，Pi＝0表示大小为(z×z)的单位阵，而Pi＝1则表示如下循环移位矩阵：
8.WLAN中的LDPC编码
一些WLAN标准(例如IEEE 802.11n/ac)采用正交频分复用(orthogonal frequency division multiplexing，OFDM)技术，LDPC编码模块需要将数据比特(可称为信息比特)经编码后放入整数个OFDM符号中，而这些编码后的比特也须恰好可放入整数个LDPC码字中。执行上述步骤，发送端首先计算得到本次传输所需的最少OFDM符号数目NSYM；再根据NSYM和当前编码调制方案，计算所有OFDM符号中可存放的总编码比特数目NTCB＝NCBPS*NSYM，其中NCBPS为每个OFDM符号可存放的比特数。随后，发送端根据以上所得结果，计算当前传输所采用的LDPC码长和所需的码字数目。对于大多数的待编码数据的比特长度和编码调制方案组合，由于没有足够多的数据比特可填满LDPC码字中的数据比特部分，因此需要在生成校验比特之前进行缩短操作。LDPC码字中的数据比特部分仅包含信息位(或者数据比特)，而不包含校验位(或者说校验比特)。
本申请中，缩短操作是指在通过LDPC编码生成校验比特之前，在码字信息的数据比特部分填入一定数目的0，编码生成校验比特之后再将这些0删除。图4为LDPC编码流程中缩短操作部分的示意图。如图4所示，401表示待编码的数据比特(payload bits)；步骤(step)1为计算发送待编码的数据比特所需的LDPC码字的长度和码字数目，402示出了LDPC码字的长度和码字数目；步骤2为对待编码的数据比特进行缩短操作，403示出了包含数据比特、缩短0比特(shortening zero bits)的码字；步骤3为利用数据比特和缩短0比特，生成校验比特(parity bits)，404示出了包含数据比特、缩短0比特以及校验比特的码字；随后将这些缩短0比特删除(discard shortening bits)，405示出了仅包含数据比特和校验比特的码字。
9.由校验矩阵扩展得到母矩阵
母矩阵是一个较大的矩阵，从母矩阵中可以读取不同大小的校验矩阵。从母矩阵中读取的不同大小的校验矩阵对应不同的码率。母矩阵可由一个校验矩阵(后续称为基础矩阵)扩展得到。例如，从母矩阵中读取基础矩阵的情况下，基础矩阵即为校验矩阵，此种情况下，校验矩阵对应的码率最大。在读取整个母矩阵的情况下，母矩阵即为校验矩阵，此种情况下，校验矩阵对应的码率最小。下面结合示例来描述如何由校验矩阵扩展得到母矩阵。
令HMC表示大小为(4×24)的基础矩阵(例如码长1944、码率5/6的WLAN LDPC校验矩阵)，04×100表示大小为(4×100)的全零矩阵，I100×100表示大小为(100×100)的单位阵，则定义大小为(100×24)的矩阵HIR与HMC、04×100以及I100×100一起组成扩展后的母 矩阵H，即
由上式可见，由于04×100和I100×100均为固定矩阵，母矩阵能够速率兼容(即从母矩阵中可以读取不同码率的校验矩阵)的关键在于HMC和HIR的设计和优化。若想通过对HMC进行扩展以得到更低码率所对应的增量冗余比特，则可按照所需码率对HMC扩展所需列数。例如，若需将码率由HMC所对应的5/6降低为4/7，或者需要在HMC的基础上增加4列所对应的324个新的增量冗余比特，则需按照H对HMC向坐下方扩展，即往下扩展4行，同时往右扩展4行。
参见图5，图5为对HMC进行扩展得到的母矩阵的一个示例。如图5所示，母矩阵的左上角位置的矩形框中为矩阵HMC，将HMC向右扩展4列，同时将HMC向下扩展4行，得到图5所示的母矩阵。图5中的每个空白格子表示大小为(81×81)的全零矩阵，母矩阵的左上角位置是大小为(4×24)的矩阵HMC，右上角为第一固定矩阵，第一固定矩阵为04×100。母矩阵的左下角为矩阵HIR，母矩阵的右下角为第二固定矩阵，固定矩阵是大I100×100。
HMC扩展之后得到的矩阵的大小为(8×28)，如图5所示的整个矩阵。母矩阵中的每个元素(除空白格子之外)是大小为(81×81)的循环移位矩阵。应理解，整体母矩阵大小为(8×28)，展开每一项得到最终的母矩阵大小为(648×2268)。若需得到其余码率或其余增量冗余比特数目，则可按照如上上述方法在H中左上部分取所需部分作为校验矩阵即可。若除原始HMC所对应的码字比特外还需要生成(81·j)个增量冗余校验比特，则所取校验矩阵为H中左上部分的大小为(4+j)×(24+j)的部分，j为正整数。
以上以校验矩阵HMC作为示例，对从基础矩阵到母矩阵的扩展过程进行了介绍，通过其他校验矩阵扩展得到母矩阵也是基于相同的设计构思。
10.由基矩阵扩展得到校验矩阵
LDPC码的基矩阵可根据需要扩展为各种码长的LDPC码的校验矩阵。或者说，根据需要可以由基矩阵扩展得到各种码长的LDPC码的校验矩阵。基矩阵中仅包含0和1两种元素。本申请中，基矩阵中的0可替换为空白、“-”、“-1”、或者其他数字或符号，本申请不作限定。本申请中，基矩阵中的1对应于非全零方阵(也可称为非全0方阵)，基矩阵中的0元素对应于全零方阵(也可称为全0方阵)。本申请中，全零方阵是指包括的每个元素均为0的方阵，例如大小为(34×34)的方阵。本申请中，非全零方阵是指至少包括一个非0元素的方阵，例如循环位移矩阵(circulant permutation matrix，CPM)。可理解，基矩阵中的1可扩展为任意大小的CPM，基矩阵中的0可扩展为任意大小的全零方阵。后文基矩阵1-基矩阵15中的1或者0的含义或者功能与前述介绍一致，将不再赘述。
由基矩阵扩展得到校验矩阵的方式如下：将基矩阵中的1替换为各种循环因子的CPM，而将0替换为相应大小的全0方阵。因此，可由基矩阵可得到一系列LDPC码的校验矩阵。这些校验矩阵的大小和每个CPM的扩展因子可不同，但对应或者符合同一基矩阵。本申请中，循环因子和扩展因子的含义相同，因此循环因子和扩展因子可相关替换。
下面介绍由基矩阵扩展得到校验矩阵的一个示例。一个大小为(12×22)的基矩阵的示例如下：

参见图6，图6示出了由大小为(12×22)的基矩阵(下文的基矩阵1)扩展得到的一个校验矩阵(下文的校验矩阵11)的示例。如图6所示，校验矩阵中的-1表示大小为(K×K)的全零矩阵，该校验矩阵中的0表示大小为(K×K)的单位矩阵，该校验矩阵中的大于0的元素表示大小为(K×K)的循环移位矩阵。本申请中，校验矩阵中的-1(表示全零矩阵)可替换为空白、“-”、或者其他数字或符号，本申请不作限定。后文的校验矩阵中的-1或者0的含义或者功能如前所述，将不再赘述。
以上通过一个示例，对由基矩阵到校验矩阵的扩展过程进行了介绍。应理解，可采用相同的方式对任意基矩阵进行扩展以得到所需码长的校验矩阵。本申请，若某个校验矩阵由某个基矩阵扩展得到，则可理解为该校验矩阵符合(或者说满足)该基矩阵或者该校验矩阵对应于该基矩阵。
为了提高无线传输系统的传输可靠性，LDPC码已在WLAN标准得到了广泛的应用。而新的IEEE 802.15ab标准相对于IEEE 802.15.4z标准可引入新的LDPC编码技术，以便大幅提升系统的数据传输可靠性。因此，可考虑针对下一代WLAN标准或UWB标准设计新的LDPC码，以进一步提高下一代WLAN系统或UWB系统的可靠性和系统性能。
为了提高下一代WLAN系统或UWB系统的可靠性和系统性能，本申请针对下一代WLAN系统或UWB系统提出了一组LDPC码的基矩阵和相应的校验矩阵的设计。本申请提供的基矩阵，可有效支持多个码率，例如2/3到1/2码率。本申请提供的LDPC编码方案能够很好支持短包的编码，例如20字节(160比特)的数据编码，并获得优异差错控制性能。另外，本申请提供的LDPC码的基矩阵可灵活扩展至各种码长，从而采用单个基矩阵即可在各个码长获得优异差错控制性能。
本申请的技术方案主要适用于无线通信系统，该无线通信系统可以遵从第三代合作伙伴计划(thirdgenerationpartnershipproject，3GPP)的无线通信标准，也可以遵从其它无线通信标准，例如，电气电子工程师学会(instituteofelectricalandelectronicsengineers，IEEE)的802系列(例如，802.11，802.15，或者802.20)的无线通信标准。
下面结合附图本申请的技术方案适用的一种无线通信系统的示例。
参见图7，图7的(a)和(b)为适用于本申请实施例的系统架构图。该无线通信系统包括至少一个接入网设备以及一个或多个终端设备。上述至少一个接入网设备以及一个或多个终端设备采用无线通信技术进行通信。例如，图7的(a)示出了一个接入网设备与单个终端设备之间进行通信。图7的(b)中示出了一个接入网设备与多个终端设备进行通信。接入网设备与终端设备之间的通信可以包括接入网设备向终端设备发送信号的下行传输，也可以包括终端设备向接入网设备发送信号的上行传输，本文不作限定。
终端设备是一种具有无线收发功能的设备。终端设备可经无线接入网(radioaccess network， RAN)中的接入网设备(或者称为接入设备)与一个或多个核心网(core network，CN)设备(或者称为核心设备)进行通信。终端设备可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。本申请实施例中，终端设备也可以称为终端(terminal)或者用户设备(user equipment，UE)，可以是手机(mobile phone)、站点(station，STA)、移动台(mobile station，MS)、平板电脑(pad)、带无线收发功能的电脑、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、工业控制(industrial control)中的无线终端设备、无人驾驶(self driving)中的无线终端设备、远程医疗(remote medical)中的无线终端设备、智能电网(smart grid)中的无线终端设备、运输安全(transportation safety)中的无线终端设备、智慧城市(smart city)中的无线终端设备、智慧家庭(smart home)中的无线终端设备、用户单元(subscriber unit)、蜂窝电话(cellular phone)、无线数据卡、个人数字助理(personal digital assistant，PDA)电脑、平板型电脑、膝上型电脑(laptop computer)、机器类型通信(machine type communication,MTC)终端设备等。终端设备可包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。可选的，终端设备可以是具有无线通信功能的手持设备(handset)、车载设备、可穿戴设备或物联网、车联网中的终端设备、5G以及5G之后演进的通信系统中的任意形态的终端设备等，本申请对此并不限定。终端设备可支持3GPP的无线通信标准，也可以支持IEE802系列(例如，802.11，802.15，或者802.20)的无线通信标准。
接入网设备可以是任意一种具有无线收发功能且能和终端通信的设备，例如将终端接入到无线网络的RAN节点。目前，一些RAN节点的举例包括：宏基站、微基站(也称为小站)、中继站、接入点、gNB、传输接收点(transmission reception point，TRP)、演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)、无线接入点(access point，AP)、接入回传一体化(integrated access and backhaul，IAB)、发送接收点(transmissionreceptionpoint,TRP)或发送节点(transmissionpoint,TP)等。此外，接入网设备还可以为构成gNB或TRP的网络节点，例如，BBU、集中式单元(centralizedunit,CU)或分布式单元(distributed unit,DU)等。接入网设备可支持3GPP的无线通信标准，也可以支持IEE802系列(例如，802.11，802.15，或者802.20)的无线通信标准。
下面结合附图结合本申请提供的LDPC码的编码方法。
图8为本申请提供的一种LDPC码的编码方法交互流程图。如图8所示，该方法包括：
801、发送端根据校验矩阵，对信息比特序列进行LDPC编码，得到编码后的比特。
发送端可以是终端设备，也可以是接入网设备。本申请中，根据校验矩阵，对信息比特序列进行LDPC编码可以是：将信息比特序列与该校验矩阵对应的生成矩阵相乘，得到第一码字。具体过程可参阅上文描述的LDPC码的编码以及WLAN中的LDPC编码。本申请不对根据校验矩阵对信息比特序列进行LDPC编码的具体方式作限定。
本申请中，接收端执行的操作或处理(例如图8中的方法流程中发送端执行的操作或处理)，可由接收端执行，也可以由设置于发送端内的芯片或电路系统等执行。上述电路系统例如可以为集成电路、逻辑电路。上述芯片例如可以是片上系统(systemonchip,SoC)芯片或者基带调制解调(modem)芯片，本文不作限定。下文以发送端为例进行说明。应理解，本申请实施例中的发送端也即编码设备。本申请中，接收端执行的操作或处理，可以由接收端执行，也可以由设置于接收端内的芯片或电路系统等执行。上述电路系统例如可以为集成电路、逻 辑电路。上述芯片例如可以是SoC芯片、或者基带调制解调(modem)芯片等，本文不作限定。下文以接收端为例进行说明。接收端可以为终端设备或者接入网设备。应理解，本申请实施例中的接收端也即译码设备。
上述校验矩阵符合(或者说)满足基矩阵。或者说，校验矩阵根据基矩阵或上述基矩阵的子矩阵扩展得到。由于前面已介绍了由基矩阵扩展得到校验矩阵的过程，故这里不再陈述。校验矩阵可分为两部分，一部分为信息码元(或者称为信息比特)，另一部分为校验码字(或者称为校验比特)。例如，校验矩阵的前面F列为信息码元部分，第(F+1)列至最后一列为校验码元部分，F为大于0的整数。上述基矩阵包括核心矩阵、扩展矩阵、第一固定矩阵和第二固定矩阵。上述核心矩阵位于上述基矩阵的左上角位置，上述扩展矩阵位于上述基矩阵的左下角位置。上述第一固定矩阵位于上述基矩阵的右上角位置。上述第二固定矩阵位于上述基矩阵的右下角位置。上述核心矩阵的行数和上述第一固定矩阵的行数相等。上述扩展矩阵的行数和上述第二固定矩阵的行数相等，上述扩展矩阵的列数和上述核心矩阵的列数相等。上述第一固定矩阵的列数和上述第二固定矩阵的列数相等。可选的，上述第二固定矩阵为单位矩阵。可选的，第一固定矩阵为全零矩阵。
在一种可能的实现方式中，发送端存储有一个或多个符合基矩阵的校验矩阵，不同校验矩阵的码长和/或码率不同。发送端在执行步骤801之前，可从存储的一个或多个校验矩阵中选择符号码长和码率要求的校验矩阵。在该实现方式中，发送端根据码长和码率，准确、快速地获取所需的校验矩阵。
在一种可能的实现方式中，发送端存储有一个或多个基矩阵。发送端在执行步骤801之前，可根据对信息比特序列进行LDPC编码选择的码率和码长，由某个基矩阵或某个矩阵的子矩阵扩展得到所需码长和码率的校验矩阵。示例性的，发送端存储有一个大小为(12×22)的基矩阵，该基矩阵的前两列为打孔列；发送端根据该基矩阵可扩展得到大小为((12*34)×(22*34))的校验矩阵。若发送端根据该校验矩阵进行码率为1/2的编码，则由10*34＝340个信息比特，编码得到长为(22-2)*34＝640比特的码字序列。若信息比特不足340比特，则可按照业界惯例在信息比特后面补0再进行编码。同时，编码后也可对编码所得校验比特进行打孔，得到更高码率或更短的码长。在该实现方式中，发送端仅需存储一个或多个基矩阵，占用的存储空间较少。
本申请提供的基矩阵的一种示例如下所示：
其中，H′表示基矩阵，H′MC表示大小为(p×q)的核心矩阵，H′IR表示大小为(r×q)的扩展矩阵，0p×r表示大小为(p×r)的全零矩阵，Ir×r表示大小为(r×r)的单位矩阵。p、q、r均为大于0的整数。示例性的，p为6，q为16，r为6。示例性的，p为6，q为17，r为5。示例性的，p为6，q为16，r为6。可选的，p为8，q为18，r为4。这三个示例仅为p、q、r三种可能的示例，而不是全部的示例。本申请不对p、q、r的取值作限定。
在一种可能的实现方式中，p为6，q为16，r为6，H′为大小为(12×22)的矩阵(下文的基矩阵1)。基矩阵的一个举例如下所示：

在该实现方式中，基矩阵为大小为(12×22)的矩阵，即12行22列的矩阵。这里基矩阵为12行22列的具体参数选择是在基矩阵实现复杂度和译码性能之间的折衷。一般来说，基矩阵越小则实现复杂度越低，但设计基矩阵的自由度也受到影响。具体可根据实际所需码长，将该基矩阵利用适当大小的CPM进行扩展。本申请中，基矩阵不限定为(12×22)的矩阵，还可以是其他大小的矩阵。在实际应用中，可根据基矩阵的实现复杂度和译码性能来选择采用多大的基矩阵。
可以注意到，该基矩阵的前两列符合或者满足如下规律：基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”。或者，该基矩阵的前两列符合如下规律：一列按照顺序包括“1 1 1 0”，另一列按照顺序相应的包括“1 1 1 0”的循环移位“1 0 1 1”。由于基矩阵的前两列符合或者满足上述规律，因此利用符合该基矩阵的校验矩阵进行译码，能够提升译码性能。
802、发送端发送编码后的比特。
具体的，所述发送步骤可以包括但不限于：发送端根据LDPC编码后的比特进行流分析(strean parser)，星座映射(Constellation mapper)，LDPC载波映射，或者可能的包括IDFT(Inverse Discrete Fourier Transform)傅里叶逆变换等等处理，以便于在信道上发送出去。
相应的，接收端接收来自发送端的第一信道接收承载前述编码后的比特的信号(为描述方便，也可以称为第一码字)。可选的，发送端为终端设备，接收端为接入网设备。可选的，发送端为接入网设备，接收端为终端设备。
步骤802一种可能的实现方式如下：发送端广播第一码字。接收端接收来自发送端的第一信道接收序列(对应于第一码字)。
步骤802一种可能的实现方式如下：发送端向接收端(对应于单播方式)发送第一码字。接收端接收来自发送端的第一信道接收序列(对应于第一码字)。
803、接收端确定第一信道接收序列对应的第一对数似然比(loglikelihoodrate,LLR)序列，并根据校验矩阵，对第一LLR序列进行译码。
接收端可采用硬判决译码、软判决译码、混合译码中的任一种，根据校验矩阵，对第一LLR序列进行译码，这里不作限定。
804、接收端若译码成功，则输出译码结果。
步骤804是可选的，而非必要的。输出译码结果可以通过输出设备，例如显示器、显示屏、音频设备等，输出译码结果。可选地，如果接收端译码错误(或者说译码失败)，则接收端向发送端发送重传指示信息，以请求发送端设备重传。此外，如果译码失败，接收端保存第一LLR序列，以和后续接收到的重传的LLR序列合并译码。
本申请实施例中，校验矩阵根据基矩阵或基矩阵的子矩阵扩展得到，能够得到不同码率和/码长的校验矩阵，采用这些校验矩阵进行LDPC编码，不仅可以兼容多种码率，而且可以获得分集增益，从而提升编码性能。
图9为本申请实施例提供的另一种LDPC码的编码方法交互流程图。图9中的方法交互流程是图8描述的方法的一种可能的实现方式。在该实现方式中，发送端对经LDPC编码得到的码字中的部分信息比特进行打孔，能够提升译码性能。如图13所示，该方法包括：
901、发送端根据校验矩阵，对信息比特序列进行LDPC编码，得到第一码字。
步骤901可参阅步骤801。上述校验矩阵根据基矩阵或上述基矩阵的子矩阵扩展得到。第一码字可理解为发送端根据校验矩阵，对信息比特序列进行LDPC编码，得到的编码后的比特。
在一种可能的实现方式中，上述基矩阵的前两列中的任意行至少包括一个1。或者说，基矩阵的前两列中，每一行的两个元素中至少一个元素为1。基矩阵的前两列的举例1，基矩阵的前两列中的一列顺序的包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，上述基矩阵的前两列中的另一列顺序的包括如下元素：1 0 1 1 1 0 1 1 1 0 1 1，上述基矩阵中的1对应于循环位移矩阵CPM，上述基矩阵中的0对应于全零方阵。在该示例中，第一子矩阵为12行2列的矩阵。
在该实现方式中，基矩阵的前两列的重量较重的列可将信息快速在校验矩阵(对应于该基矩阵)中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。
在一种可能的实现方式中，上述基矩阵的前两列为打孔列。或者说，上述第一码字中的第一信息比特不参与传输，上述第一信息比特根据上述校验矩阵中对应于上述基矩阵的前两列的子矩阵做LDPC编码得到。又或者说，基矩阵的前两列为打孔节点。这里打孔是指编码后相应比特不传输的一种信道编码中的常见操作，这里不再赘述。符合基矩阵的校验矩阵的前两列参与编码但根据这两列编码得到的信息比特不参与传输。
基矩阵的前两列为打孔列的具体设计原理为：打孔列重量越重，则其在长码时可得更优性能。然而对于短码，列重过于重会造成相应因子图中出现短环或陷阱集等有损译码性能的子图结构。因此，本申请的基矩阵的前两列通过如上述举例1所示设计控制了重量和稀疏度，在短码和长码性能之间取了一个折衷。
基矩阵中重量较重的前两列直接打孔不参与传输，是因为该两列重量较重的列可将信息快速在矩阵中各列对应的码字比特之间传输交换和译码更新，加速系统的译码整体收敛速度。然而，由于该两列的列重较重，因此若传输且其对应比特发生错误，则错误会快速传播至其余码字比特，从而对译码造成不利影响。因此该两列参与实际编码，但对应比特打孔不传输。
可选的，基矩阵的第17列只包括一个1且该1位于该基矩阵的第7行，该基矩阵的第7行的前两列中的至少一个元素为0，该基矩阵的第7行的第17列的元素为1。基矩阵的前两列与该基矩阵的第7行(除前两列外对应位置只有一个1)和第17列(只有一个1)结合，可大幅改善译码性能。
在其他的实施方式中，前述举例1的基矩阵的前两列可以替换为满足类似特点的两列。如前文所述，基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”。或者，该基矩阵的前两列符合如下规律：每一列中按照顺序包括“1 1 1 0”或者“1 1 1 0”的循环移位“1 0 1 1”。
902、发送端发送第二码字。
相应的，接收端接收来自发送端的第二信道接收序列(对应于第二码字)。可选的，发送端为终端设备，接收端为接入网设备。可选的，发送端为接入网设备，接收端为终端设备。步骤902可参阅步骤802。
可选的，发送端在发送第二码字之前，对第一码字进行打孔，得到第二码字。示例性的，发送端对第一码字中的第一信息比特进行打孔，得到第二码字；其中，上述第一信息比特根 据上述校验矩阵中对应于上述基矩阵的前两列的子矩阵做LDPC编码得到。第二码字可理解为对编码后的比特打孔后的比特。
903、接收端确定第二信道接收序列对应的第二LLR序列，并根据校验矩阵，对第二LLR序列进行译码。
这里是打孔后的译码，其译码过程可以使用硬判决译码、软判决译码或者混合译码，细节不赘述。
904、接收端若译码成功，则输出译码结果。
步骤904是可选的，而非必要的。步骤904可参阅步骤804。
本申请实施例中，发送端对经LDPC编码得到的码字中的部分信息比特进行打孔，能够加速系统的译码整体收敛速度，并避免对译码造成不利影响。
图10为本申请实施例提供的另一种LDPC码的编码方法交互流程图。图10中的方法交互流程是图8描述的方法的一种可能的实现方式。在该实现方式中，如果首次传输失败，接收端采用码率更低的校验矩阵进行LDPC编码，对合并后的LLR序列进行译码。由于重传在信息比特序列的基础上，增加了增量冗余校验比特，信道编码率降低，因此可以提高接收端设备解码的成功率，减少重传次数，降低重传时延，提高译码性能。
1001、发送端根据第一校验矩阵，对信息比特序列进行LDPC编码，得到第一码字。
步骤1001可参阅步骤801。上述第一校验矩阵根据基矩阵或上述基矩阵的子矩阵扩展得到。发送端执行步骤1001采用的第一校验矩阵可与执行步骤801采用的校验矩阵相同。
1002、发送端发送第二码字。
相应的，接收端接收来自发送端的第二信道接收序列(对应于第二码字)。步骤1002可参阅步骤802。
1003、接收端确定第二信道接收序列对应的第二LLR序列，并根据第一校验矩阵，对第二LLR序列进行译码。
步骤1003可参阅步骤803。
1004、接收端在译码错误的情况下，向发送端设备发送重传指示信息。
相应的，发送端接收来自接收端的重传指示信息。译码错误是指接收端根据第一校验矩阵，对第二LLR序列进行译码，未得到正确的译码结果。或者说，接收端对第二LLR序列进行译码得到的译码结果均不能通过第一校验矩阵的校验。
1005、发送端根据第二校验矩阵，对信息比特序列进行LDPC编码，得到第三码字。
步骤1005可参阅步骤801。上述第二校验矩阵根据基矩阵或上述基矩阵的子矩阵扩展得到。上述第一校验矩阵和上述第二校验矩阵可由同一个基矩阵扩展得到。可选的，上述第二校验矩阵的码率低于上述第一校验矩阵的码率。
1006、发送端向接收端发送第四码字。
相应的，接收端接收来自发送端的第三信道接收序列(对应于第四码字)。步骤1006可参阅步骤802。可选的，发送端在发送第四码字之前，对第三码字进行打孔，得到第四码字。示例性的，发送端对第三码字中的第二信息比特进行打孔，得到第四码字；其中，上述第二信息比特根据上述第二校验矩阵中对应于上述基矩阵的前两列的子矩阵做LDPC编码得到。
1007、接收端确定第三信道接收序列对应的第三LLR序列，并根据第二校验矩阵对合并后的LLR序列进行译码。
合并后的LLR序列是指接收端将第二LLR序列和第三LLR序列合并得到的。可选的，第二LLR序列和第三LLR序列是按位合并的。其中，第二LLR序列和第三LLR序列的相同 位置索引上的LLR值进行合并，不同索引位置上的LLR值继续保留。
进一步地，如果接收端根据第二校验矩阵对合并后的LLR序列译码成功，则输出译码结果。如果接收端根据第二校验矩阵，对合并后的LLR序列译码失败，则执行下一次重传。以此类推，直到译码成功或者达到设定的最大重传次数，则译码失败。
可以看出，在一次传输失败之后，发送端根据更低码率对应的校验矩阵对信息比特序列进行编码，可以增加冗余比特的数量，使得编码后的码字的码率降低。由于重传在信息比特序列的基础上，增加了增量冗余校验比特，信道编码率降低，因此可以提高接收端设备解码的成功率，减少重传次数，降低重传时延，提高译码性能。
以上对本申请提供的LDPC编码的方法进行了详细说明。根据本申请提供的编码方法，可以在兼容多种码率。下面着重介绍本申请提供的基矩阵，以及由这些基矩阵扩展的一些校验矩阵的示例。
本申请提供的基矩阵可根据需要扩展为各种码长的LDPC码的校验矩阵。如前文上述将基矩阵中的1替换为各种循环因子的CPM以及将0替换为相应大小的全0方阵，就能得到各种码长的LDPC码的校验矩阵。也就是说，由一个基矩阵可得到一系列LDPC码的校验矩阵，这些校验矩阵的扩展大小和每个CPM的扩展因子可不同，但对应同一基矩阵。
需要注意，本申请提供的基矩阵的各种行列置换所得到的基矩阵与本申请提供的基矩阵等效。也就是说，对本申请提供的基矩阵进行行列置换所得到的基矩阵同样属于本申请保护的基矩阵。基矩阵的各种行列置换是指基矩阵中的一个或多个元素替换为其他元素。也就是说，基矩阵中的一个或多个元素替换为其他元素之后与该基矩阵等效。或者说，基矩阵中的一个或多个元素替换为其他元素同样可视为该基矩阵。本申请中，基矩阵的行列置换可包括以下任一项：基矩阵的一行中的一个或多个元素替换为其他元素、基矩阵的一列中的一个或多个元素替换为其他元素、基矩阵中的位于不同行的多个元素替换为其他元素、基矩阵中的位于不同列的多个元素替换为其他元素、基矩阵中的多行的位置改变、基矩阵中的多列的位置改变，例如基矩阵中的两列的位置互换。一个元素替换为其他元素可理解为该元素替换为与该元素不同的任意元素。例如，基矩阵中的一个或多个元素0替换为元素1。又例如，基矩阵中的一个或多个元素1替换为元素。
图11为本申请提供的一种基矩阵的示例。如图11所示，矩形框1101中的矩阵为基矩阵的核心矩阵，矩形框1102中的矩阵为基矩阵的扩展矩阵，矩形框1103中的矩阵为该基矩阵的一个子矩阵，该基矩阵的右下角为单位阵。本申请还保护本申请提供的基矩阵的局部矩阵(即子矩阵)，例如矩形框1101中的矩阵、矩形框1102中的矩阵或者矩形框1103中的矩阵。
参阅图11，本申请提供的基矩阵为(12×22)的二维矩阵。可选的，本申请提供的基矩阵的前两列为打孔列。本申请提供的基矩阵中，前10列对应于信息比特，后续列(即后12列)对应于校验比特，因此该基矩阵的最低码率为R＝10/(22-2)＝1/2。可理解，由基矩阵扩展得到的校验矩阵的码率为1/2。若发送端工作在码率R＝2/3情况，则该发送端采用的校验矩阵由基矩阵的左上角部分的子矩阵扩展得到(参阅矩形框1101)：R＝10/(17-2)＝2/3。可见，由基矩阵可扩展得到码率不同的校验矩阵，即可有效支持多个码率，例如1/2到2/3。除上述两种码率，本申请提供的基矩阵也可工作在其它码率，具体取决于编码时取矩阵的行列数目。例如，若利用基矩阵前9行和前19列，则可得码率R＝10/(17-2+2)＝10/17。
参阅图12，本申请提供的一个校验矩阵的示例。图12中的校验矩阵可采用(34×34)的CPM对图11示出的基矩阵扩展得到。如图12所示，矩形框1201中的矩阵作为校验矩阵时的码率为R＝2/3，图12示出的整个矩阵作为校验矩阵时码率为1/2。矩形框1201中的矩阵 对应于图11中的矩形框1101中的矩阵。另外，本申请提供的基矩阵可根据需要扩展为各种码长的LDPC码的校验矩阵。可见，采用单个基矩阵即可在各个码长获得优异差错控制性能。因此，由本申请提供的基矩阵可灵活的扩展得到不同码率和码长的校验矩阵。
一种编码的示例如下：针对利用大小为(Z×Z)的CPM扩展后的基矩阵(即校验矩阵)，可首先将信息比特序列划分为(10×Z)大小的子信息序列，其中不足(10×Z)的部分可于子信息序列中任意位置补0，一般补0位于子信息序列的尾部(即传统信道编码中的缩短操作)。随后，无论系统(即发送端)所需码率如何，首先利用扩展后的基矩阵对应于矩形框1201的部分进行编码，编码方法类似于802.11n中LDPC编码方法。随后可根据所需码率或传输比特数目，根据已编码字序列，利用扩展后的基矩阵的其余部分继续编出剩余校验比特序列。其中，剩余校验比特序列编码方法可递归运算编码，具体方法类似于现有5G NR LDPC编码方法。最后，对应于基矩阵前两列的信息比特打孔不传输，再去除编码时的补0比特，最后得到系统传输所需码字比特序列。具体编码部分流程如图2所示。对应于基矩阵前两列的信息比特利用基矩阵的前两列扩展的部分编码得到。
参阅图13，图13为本申请提供的另一种基矩阵的示例，矩形框中的矩阵为矩阵1，R10指示矩阵1的每行中1的个数最大不超过10，C04指示矩阵1的最大列重(除去前两列)不超过4，C08指示基矩阵的最大列重不超过8，R09指示基矩阵中除矩阵1之外部分的最大行重不超过9。或者说，C04指示矩阵1的第3列至第16列的列重均不超过4。R09指示基矩阵的第7行至第12行的行重均不超过9。图13示出的基矩阵满足行列重量约束条件C04_R10_C08_R09。应理解，C04_R10_C08_R09仅为一种基矩阵的行列重量约束条件的示例，其他行列重量约束条件的含义与C04_R10_C08_R09的含义类似。
需要指出的是，Thr为本申请的基矩阵取相码率1/2部分时的译码阈值。译码阈值指该基矩阵所对应LDPC码在码长无限长时译码成功所需最小的Eb/N0，Gap是指译码阈值与相应码率信道容量对应Eb/N0之间的距离(以dB表示)。Eb代表平均到每个比特上的信号能量，N0代表噪声的功率谱密度。相应的，Thr_2是指本申请的基矩阵取码率2/3部分时其译码阈值，Gap_2是指译码阈值与相应码率信道容量对应Eb/N0之间的距离(以dB表示)。
下面示出本申请提供的满足行列重量约束条件C04_R10_C08_R09的基矩阵的示例。这些基矩阵可兼顾基矩阵的实现复杂度和译码性能。
基矩阵1：
基矩阵1对应的参数信息如下：Thr＝0.5571dB,Gap＝0.3953dB Thr_2＝1.4078dB, Gap_2＝0.3255dB。
由基矩阵1扩展的校验矩阵11：
由基矩阵1扩展的校验矩阵12：
由基矩阵1扩展的校验矩阵13：

基矩阵2：
基矩阵2对应的参数信息如下：Thr＝0.5418dB,Gap＝0.3799dB Thr_2＝1.3982dB,Gap_2＝0.3159dB。
基矩阵3：
基矩阵3对应的参数信息如下：Thr＝0.5993dB,Gap＝0.4374dB Thr_2＝1.4771dB,Gap_2＝0.3948dB。
基矩阵4：

基矩阵4对应的参数信息如下：Thr＝0.6033dB,Gap＝0.4415dB Thr_2＝1.4119dB,Gap_2＝0.3296dB。
基矩阵5：
基矩阵5对应的参数信息如下：Thr＝0.6056dB,Gap＝0.4438dB Thr_2＝1.4204dB,Gap_2＝0.3381dB.
基矩阵6：
基矩阵6对应的参数信息如下：Thr＝0.6076dB,Gap＝0.4457dB Thr_2＝1.4406dB,Gap_2＝0.3583dB。
由基矩阵6扩展的校验矩阵61：
由基矩阵6扩展的校验矩阵62：
基矩阵7：
基矩阵7对应的参数信息如下：Thr＝0.6081dB,Gap＝0.4462dB Thr_2＝1.5081dB,Gap_2＝0.4258dB。
由基矩阵7扩展的校验矩阵71：
由基矩阵7扩展的校验矩阵72：
基矩阵8：

基矩阵8对应的参数信息如下：Thr＝0.4803dB,Gap＝0.3184dB Thr_2＝1.4491dB,Gap_2＝0.3668dB。
基矩阵9：
基矩阵9对应的参数信息如下：Thr＝0.4988dB,Gap＝0.3369dB Thr_2＝1.4274dB,Gap_2＝0.3451dB。
下面示出本申请提供的满足行列重量约束条件C04_R9_C08_R08的基矩阵的示例。这些基矩阵可兼顾基矩阵的实现复杂度和译码性能。
基矩阵10：
基矩阵10对应的参数信息如下：Thr＝0.3963dB,Gap＝0.2345dB Thr_2＝1.3798dB,Gap_2＝0.2975dB。
由基矩阵10扩展的校验矩阵101：

基矩阵11：
基矩阵11对应的参数信息如下：Thr＝0.3888dB,Gap＝0.2270dB Thr_2＝1.3749dB,Gap_2＝0.2926dB。
下面示出本申请提供的满足行列重量约束条件C04_R8_C07_R08的基矩阵的示例。这些基矩阵可兼顾基矩阵的实现复杂度和译码性能。
基矩阵12：
基矩阵12对应的参数信息如下：Thr＝0.3397dB,Gap＝0.1778dB Thr_2＝1.3738dB, Gap_2＝0.2915dB。
由基矩阵12扩展的校验矩阵1201：
下面示出本申请提供的满足行列重量约束条件C04_R8_C07_R07的基矩阵的示例。这些基矩阵可兼顾基矩阵的实现复杂度和译码性能。
基矩阵13：
基矩阵13对应的参数信息如下：Thr＝0.3435dB,Gap＝0.1817dB Thr_2＝1.4154dB,Gap_2＝0.3331dB。
由基矩阵13扩展的校验矩阵1301：

下面示出本申请提供的满足行列重量约束条件C04_R8_C06_R07的基矩阵的示例。这些基矩阵可兼顾基矩阵的实现复杂度和译码性能。
基矩阵14：
基矩阵14对应的参数信息如下：Thr＝0.3322dB,Gap＝0.1703dB Thr_2＝1.3743dB,Gap_2＝0.2920dB。
基矩阵15：
基矩阵15对应的参数信息如下：Thr＝0.3255dB,Gap＝0.1637dB Thr_2＝1.3946dB,Gap_2＝0.3123dB。
对于长码来说，基矩阵对应的译码阈值(即Thr和Thr_2)越小，符合该基矩阵的校验矩阵的译码性能越好。同样，对于长码来说，基矩阵对应的译码阈值与相应码率信道容量对应 Eb/N0之间的距离(即Gap和Gap_2)越小，符合该基矩阵的校验矩阵的译码性能越好。从上述基矩阵1至基矩阵15对应的参数信息可知，每个基矩阵对应的译码阈值，以及译码阈值与相应码率信道容量对应Eb/N0之间的距离均较小，因此符合该基矩阵的校验矩阵的译码性能较好。从基矩阵1至基矩阵15可以看出，每个基矩阵的前两列的重量较高。对于短码，列重过于重会造成相应因子图中出现短环或陷阱集等有损译码性能的子图结构。本申请中，基矩阵中重量较重的前两列直接打孔不参与传输，可避免列重过于重影响对短码的译码性能。因此，本申请中的基矩阵既能保证长码的译码性能，又能保证短码的译码性能，即在短码和长码性能之间取了一个较好的折衷。
上述例举的校验矩阵中除“-1”之外的任意元素表示一个(34×34)的CPM，校验矩阵中的“-1”表示大小为(34×34)的全0方阵。应理解，采用不同的扩展因子对基矩阵进行扩展，得到不同大小的校验矩阵。例如，采用(68×68)的CPM对基矩阵进行扩展。在实际应用中，可根据需要采用任意大小的CPM对基矩阵进行扩展，进而得到所需的校验矩阵。
基矩阵1至基矩阵15仅为本申请提供的基矩阵的一些示例，而不是全部的举例。应理解，对本申请提供的基矩阵进行行列置换所得到的基矩阵同样属于本申请保护的基矩阵。同理，上述示出的由基矩阵扩展得到的校验矩阵也仅是部分示例，而不是全部的示例。
以上示出了本申请提供的基矩阵和校验矩阵的示例。下面结合附图以符合上述基矩阵1的校验矩阵11为例说明本申请提供的编码方法的有益效果。
图14为本申请提供的一种LDPC码的性能对比示意图。图14中，横坐标表示信噪比(signal noise ratio，SNR)，纵坐标表示块差错率(block error rate，BLER)，即误块率。图14中，New UWB LDPC表示本申请的LDPC码。
参阅图14，New UWB LDPC(340,680)vs.WLAN LDPC(324,648)：本申请的LDPC码(340,680)与WLAN LDPC(324,648)在码率1/2时的性能比较，其中(k,n)中k指编码前信息比特数目，而n指编码后码字序列比特数目。
在BLER＝10-4时本申请的LDPC码可获得约0.25dB性能增益。
复杂度方面，本申请的LDPC码的基矩阵(基矩阵1)中包含76个CPM，而WLAN LDPC码对应的基矩阵中包含88个CPM。因此，本申请的LDPC码的复杂度较低。
参阅图14，New UWB LDPC(340,510)vs.two WLAN LDPC(324,486)：在码率R＝2/3时的性能比较。本申请的LDPC码打孔至(340,510)时与WLAN LDPC(324,486)码率2/3时的性能比较。two WLAN LDPC(324,486)包括图14中的Original WLAN LDPC R＝2/3(432,648)→(324,486)和WLAN LDPC R＝2/3(324,648)→(324,486)。
其中，WLAN LDPC R＝2/3(324,648)→(324,486)指按照图15A将码率为R＝1/2的WLAN LDPC码进行打孔至码率为R＝2/3。图15A为本申请提供的一种LDPC码打孔的示意图。
其中，Original WLAN LDPC R＝2/3(432,648)→(324,486)指按照图15B将码率为R＝1/2的WLAN LDPC码同时进行缩短和打孔至码率为R＝2/3。图15B为本申请提供的一种LDPC码缩短和打孔的示意图。
如图14可见，在相似的码长下，本申请的LDPC码比WLAN码率为2/3的LDPC码可获得约0.35dB的性能增益，且相对WLAN码率1/2的LDPC码打孔至R＝2/3可获得大于2.5dB的性能增益。
与R＝2/3WLAN LDPC相比复杂度：50CPMS(New UWB LDPC)vs 88CPMs(WLAN LDPC)。因此，本申请的LDPC码的复杂度较低。
参阅图14，New UWB LDPC(160,320)vs.WLAN LDPC(160,320)在码率R＝1/2：本申 请的LDPC码和码率1/2的WLAN LDPC码同时缩短和打孔至(160,320)时性能比较。其中，WLAN LDPC码同时缩短和打孔如图15C所示。图15C为本申请提供的另一种LDPC码缩短和打孔的示意图。
可见，本申请所设计的LDPC码在短包(例如：k＝160比特＝20bytes)下性能优异，相对WLAN LDPC可达大于3dB的性能增益。
下面结合附图介绍可实施本申请实施例提供的LDPC码的编码方法或LDPC码的译码方法的通信装置的结构。
图16为本申请实施例提供的一种通信装置1600的结构示意图。该通信装置1600可以对应实现上述各个方法实施例中发送端实现的功能或者步骤，也可以对应实现上述各个方法实施例中接收端实现的功能或者步骤。该通信装置可以包括处理模块1610和接口模块1620。可选的，还可以包括存储单元，该存储单元可以用于存储指令(代码或者程序)和/或数据。处理模块1610和接口模块1620可以与该存储单元耦合，例如，处理模块1610可以读取存储单元中的指令(代码或者程序)和/或数据，以实现相应的方法。上述各个单元可以独立设置，也可以部分或者全部集成。例如，接口模块1620可包括发送模块和接收模块。发送模块可以是发射机，接收模块可以是接收机。接口模块1620对应的实体可以是收发器，也可以是通信接口。
在一些可能的实施方式中，通信装置1600能够对应实现上述方法实施例中发送端的行为和功能。例如通信装置1600可以为发送端，也可以为应用于发送端中的部件(例如芯片或者电路)。接口模块1620例如可以用于执行图8、图9、图10的实施例中由发送端所执行的全部接收或发送操作，例如图8所示的实施例中的步骤802，图9所示的实施例中的步骤902，图10所示的实施例中的步骤1002、步骤1004、步骤1006，和/或用于支持本文所描述的技术的其它过程。处理模块1610用于执行图8、图9、图10的实施例中由发送端所执行的除了收发操作之外的全部操作，例如图8所示的实施例中的步骤801，图9所示的实施例中的步骤901，图10所示的实施例中的步骤1001、步骤1005。
在一些可能的实施方式中，通信装置1600能够对应实现上述方法实施例中接收端的行为和功能。例如通信装置1600可以为接收端，也可以为应用于接收端中的部件(例如芯片或者电路)。接口模块1620例如可以用于执行图8、图9、图10的实施例中由接收端所执行的全部接收或发送操作，例如图8所示的实施例中的步骤802，图9所示的实施例中的步骤902，图10所示的实施例中的步骤1002、步骤1004、步骤1006，和/或用于支持本文所描述的技术的其它过程。处理模块1610用于执行图8、图9、图10的实施例中由接收端所执行的除了收发操作之外的全部操作，例如图8所示的实施例中的步骤803、步骤804，图9所示的实施例中的步骤903、步骤904，图10所示的实施例中的步骤1003、步骤1004、步骤1007。
图17为本申请实施例提供的另一种通信装置170的结构示意图。图17中的通信装置可以是上述发送端者，也可以是上述接收端。
如图17所示，该通信装置170包括至少一个处理器1710和收发器1720。
在本申请的一些实施例中，处理器1710和收发器1720可以用于执行发起者执行的功能或操作等。收发器1720例如执行图8、图9、图10的实施例中由发送端所执行的全部接收或发送操作。处理器1710例如用于执行图8、图9、图10的实施例中由发送端所执行的除了收发操作之外的全部操作。
在本申请的一些实施例中，处理器1710和收发器1720可以用于执行接收端执行的功能或操作等。收发器1720例如执行图8、图9、图10的实施例中由接收端所执行的全部接收或 发送操作。处理器1710例如用于执行图8、图9、图10的实施例中由接收端所执行的除了收发操作之外的全部操作。
收发器1720用于通过传输介质和其他设备/装置进行通信。处理器1710利用收发器1720收发数据和/或信令，并用于实现上述方法实施例中的方法。处理器1710可实现处理模块1610的功能，收发器1720可实现接口模块1620的功能。
可选的，通信装置170还可以包括至少一个存储器1730，用于存储程序指令和/或数据。存储器1730和处理器1710耦合。本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器1710可能和存储器1730协同操作。处理器1710可能执行存储器1730中存储的程序指令。该至少一个存储器中的至少一个可以包括于处理器中。
本申请实施例中不限定上述收发器1720、处理器1710以及存储器1730之间的具体连接介质。本申请实施例在图17中以存储器1730、处理器1710以及收发器1720之间通过总线1740连接，总线在图17中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图17中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
图18为本申请实施例提供的另一种通信装置180的结构示意图。如图18所示，图18所示的通信装置包括逻辑电路1801和接口1802。图16中的处理模块1610可以用逻辑电路1801实现，图16中的接口模块1620可以用接口1802实现。其中，该逻辑电路1801可以为芯片、处理电路、集成电路或片上系统(system on chip，SoC)芯片等，接口1802可以为通信接口、输入输出接口等。本申请实施例中，逻辑电路和接口还可以相互耦合。对于逻辑电路和接口的具体连接方式，本申请实施例不作限定。
在本申请的一些实施例中，该逻辑电路和接口可用于执行上述发送端执行的功能或操作等。
在本申请的一些实施例中，该逻辑电路和接口可用于执行上述接收端执行的功能或操作等。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令在计算机上运行时，使得计算机执行上述实施例的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括指令或计算机程序，当该指令或计算机程序在计算机上运行时，使得上述实施例中的方法被执行。
本申请还提供一种通信系统，包括上述发送端和上述接收端。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以上述权利要求的保护范围为准。

Claims (18)

  1. 一种LDPC码的编码方法，其特征在于，包括：
    根据校验矩阵，对信息比特序列进行低密度奇偶校验LDPC编码，得到第一码字；所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：
    所述基矩阵的前两列中的每行至少包括一个1，或者，
    所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”；或者，
    所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”；
    发送所述第一码字。
  2. 一种LDPC码的译码方法，其特征在于，包括：
    接收端确定第一信道接收到的信号对应的第一对数似然比序列，并根据校验矩阵，对第一LLR序列进行译码；
    其中，所述校验矩阵符合基矩阵，所述基矩阵满足下述之一：
    所述基矩阵的前两列中的每行至少包括一个1，或者，
    所述基矩阵的前两列中包括规律交替的“1 0”和“0 1”，且“1 0”和“0 1”中间包括“1 1”；或者，
    所述基矩阵的前两列符合如下规律：一列按照顺序包括多个“1 1 1 0”，另一列按照顺序相应的包括多个“1 0 1 1”。
  3. 根据权利要求1或2所述的方法，其特征在于，所述基矩阵的前两列中的一列包括如下元素：1 1 1 0 1 1 1 0 1 1 1 0，所述基矩阵的前两列中的另一列包括如下元素：1 0 1 1 1 0 1 1 1 0 1 1，所述基矩阵中的1对应于循环位移矩阵CPM，所述基矩阵中的0对应于全零方阵。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，所述基矩阵包括如下所示(12×22)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至22中的整数。
  5. 根据权利要求4所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：
    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  6. 根据权利要求4所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：
    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  7. 根据权利要求1至3任一项所述的方法，其特征在于，所述基矩阵包括如下所示(12×22)矩阵中的H行或M列：

    所述H为1至12中的整数，所述M为1至22中的整数。
  8. 根据权利要求7所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：
    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  9. 根据权利要求7所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：

    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  10. 根据权利要求1至3任一项所述的方法，其特征在于，所述基矩阵包括如下所示(12×22)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至22中的整数。
  11. 根据权利要求10所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：
    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  12. 根据权利要求10所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：
    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  13. 根据权利要求1至3任一项所述的方法，其特征在于，所述基矩阵包括如下所示(12×22)矩阵中的H行或M列：
    所述H为1至12中的整数，所述M为1至22中的整数。
  14. 根据权利要求13所述的方法，其特征在于，所述校验矩阵包括如下所示(12×22)矩阵中的L行或F列：

    其中，所述校验矩阵中的-1表示大小为(K×K)的全零矩阵，所述校验矩阵中的0表示大小为(K×K)的单位矩阵，所述校验矩阵中的大于0的元素表示大小为(K×K)的CPM，所述L为1至12中的整数，所述F为1至22中的整数。
  15. 一种通信装置，其特征在于，包括用于实现权利要求1至14中任一项所述的方法的模块或单元。
  16. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，所述计算机程序包括程序指令，所述程序指令被执行时使得计算机执行如权利要求1至14中任一项所述的方法。
  17. 一种通信装置，其特征在于，包括处理器，所述处理器与存储器耦合，所述存储器存储指令，所述处理器用于执行所述指令，使得所述通信装置执行如权利要求1至14任一项所述的方法。
  18. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序，所述计算机程序包括程序指令，所述程序指令被执行时使得计算机执行如权利要求1至14中任一项所述的方法。
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