WO2024067350A1 - 级联码的编码和译码的方法以及通信装置 - Google Patents

级联码的编码和译码的方法以及通信装置 Download PDF

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WO2024067350A1
WO2024067350A1 PCT/CN2023/120418 CN2023120418W WO2024067350A1 WO 2024067350 A1 WO2024067350 A1 WO 2024067350A1 CN 2023120418 W CN2023120418 W CN 2023120418W WO 2024067350 A1 WO2024067350 A1 WO 2024067350A1
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matrix
code
columns
base matrix
vector
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PCT/CN2023/120418
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English (en)
French (fr)
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伊万诺夫费多尔
秦康剑
张华滋
王俊
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the embodiments of the present application relate to the field of channel coding, and more specifically, to a method for encoding and decoding a cascaded code and a communication device.
  • concatenated codes can achieve higher coding gain and lower decoding delay.
  • a concatenated coding strategy usually includes inner code and outer code.
  • the role of the inner code can be considered to be to obtain a better super channel by "noising" the physical channel, so that the channel condition seen by the outer code is better than the original physical channel.
  • LDPC concatenated code scheme of polarization code and low-density parity check codes
  • RS concatenated code scheme of Reed-Solomon
  • LDGM concatenated code scheme of polarization code and low-density generation matrix
  • the embodiment of the present application provides a method for encoding and decoding a cascaded code, which can improve the decoding performance of the cascaded code and meet the requirements of rate compatibility.
  • a method for encoding a cascade code comprising: performing polarization code encoding on a message bit sequence to be encoded to obtain a first encoding codeword of length N_o, where N_o is a positive integer; performing improved low density parity check (LDPC) code encoding on a second encoding codeword to obtain a cascade code codeword of length N_i, where the second encoding codeword is determined based on the first encoding codeword, where N_i is a positive integer; outputting the cascade code codeword; wherein the first t columns of a basis matrix of the improved LDPC code are all-zero columns, where t is a positive integer, and 2 ⁇ t ⁇ T, where T is equal to the ratio of N_o to p, where p is a multiple of the basis matrix that needs to be expanded, and where p is a positive integer; and the check matrix of the improved LDPC code includes at least s columns with a column weight
  • the second encoding codeword is the same as the first encoding codeword, or the second encoding codeword is obtained by interleaving the first encoding codeword.
  • the soft values of the polar code outer code and the soft values of the improved LDPC code do not exchange soft values at the all-zero columns, and the partial update of the soft values can improve the large iterative decoding performance.
  • the method provided in the embodiment of the present application has low coding complexity and can achieve rate compatibility.
  • the size of the base matrix is m rows and n columns
  • the updated basis matrix is obtained according to the lifting matrix and the basis matrix.
  • H opt ⁇ M represents the Hadamard product of H opt and M
  • H opt2 ⁇ M represents the Hadamard product of H opt2 and M.
  • the Hadamard product may also be called a basic product.
  • a method for decoding a concatenated code comprising: obtaining a channel reception vector of length N_i, where N_i is the length of an inner code of the concatenated code, the inner code of the concatenated code is an improved LDPC code, the outer code of the concatenated code is a polarization code, and N_i is a positive integer; using a soft input soft output (SISO) decoding algorithm of the improved LDPC code to decode the channel reception vector to obtain a first soft information sequence of length N_i, the SISO decoding algorithm being related to a check matrix of the improved LDPC code; based on a second soft information sequence, the channel reception vector and a preset maximum number of iterations of the concatenated code, through a soft continuous cancellation list (succ) of the polarization code.
  • SISO soft input soft output
  • the improved LDPC code is provided with a SISO decoding algorithm and a sparse cancellation list (SCL) decoding algorithm, and the improved LDPC code is provided with a SISO decoding algorithm, and soft information is iteratively decoded to obtain a third soft information sequence, wherein the second soft information sequence is determined according to the first soft information sequence; a hard decision is performed on the third soft information sequence to obtain a decoding estimation sequence; and the decoding estimation sequence is output; wherein the first t columns of the basis matrix of the improved LDPC code are all-zero columns, t is a positive integer, and 2 ⁇ t ⁇ T, T is equal to the ratio of N_o to p, p is the multiple by which the basis matrix needs to be expanded, and p is a positive integer; the check matrix of the improved LDPC code includes at least s columns with a column weight of 1, and the at least s columns include the last (N_i-N_o) columns, and s is a positive integer.
  • SCL spars
  • the receiving end deinterleaves the first soft information sequence, and reads the soft information at the first N_o positions from the deinterleaved first soft information sequence to obtain the second soft information sequence. Alternatively, the receiving end reads the soft information at the first N_o positions of the first soft information sequence to obtain the second soft information sequence.
  • the decoding adopts soft information iterative decoding combining the soft SCL decoding algorithm and the SISO decoding algorithm, which can reduce the decoding complexity.
  • the size of the base matrix is m rows and n columns
  • H opt ⁇ M represents the Hadamard product of H opt and M
  • H opt2 ⁇ M represents the Hadamard product of H opt2 and M.
  • the Hadamard product may also be called a basic product.
  • a method for decoding a cascade code comprising: obtaining a channel reception vector of length N_i, where N_i is the length of an inner code of the cascade code, the inner code of the cascade code is an improved LDPC code, the outer code of the cascade code is a polarization code, and N_i is a positive integer; wherein the first t columns of a base matrix of the improved LDPC code are all-zero columns, t is a positive integer, and 2 ⁇ t ⁇ T, T is equal to the ratio of N_o to p, p is a multiple by which the base matrix needs to be expanded, and p is a positive integer; the check matrix of the improved LDPC code includes at least s columns with a column weight of 1, the at least s columns include the last (N_i-N_o) columns, and s is a positive integer; decoding the channel reception vector and outputting a decoding result.
  • the soft values of the polar code outer code and the soft values of the improved LDPC code do not exchange soft values at the all-zero columns, and the partial update of the soft values can improve the large iterative decoding performance.
  • the size of the base matrix is m rows and n columns
  • H opt ⁇ M represents the Hadamard product of H opt and M
  • H opt2 ⁇ M represents the Hadamard product of H opt2 and M.
  • the Hadamard product may also be called a basic product.
  • a communication device which has the function of implementing the method in the first aspect or any possible implementation of the first aspect.
  • the function can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the above functions.
  • a communication device which has the function of implementing the method in the second aspect or any possible implementation of the second aspect, or the communication device has the function of implementing the method in the third aspect or any possible implementation of the third aspect.
  • the function can be implemented by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the above functions.
  • a communication device comprising a processor and a memory.
  • a transceiver may also be included.
  • the memory is used to store a computer program
  • the processor is used to call and run the computer program stored in the memory, and control the transceiver to send and receive signals, so that the communication device performs the method in the first aspect or any possible implementation of the first aspect.
  • a communication device comprising a processor and a memory.
  • a transceiver may also be included.
  • the memory is used to store a computer program
  • the processor is used to call and run the computer program stored in the memory, and control the transceiver to send and receive signals, so that the communication device executes the method in the second aspect or any possible implementation of the second aspect, or so that the communication device executes the method in the third aspect or any possible implementation of the third aspect.
  • a communication device comprising a processor and a communication interface, wherein the communication interface is used to receive data and/or information and transmit the received data and/or information to the processor, and the processor processes the data and/or information; and the communication interface is also used to output Output data and/or information processed by the processor so that the method in the first aspect, or any possible implementation manner of the first aspect, is executed.
  • a communication device comprising a processor and a communication interface, wherein the processor processes data and/or information to be sent, and the communication interface is also used to output the data and/or information processed by the processor, so that the method in the second aspect, or any possible implementation of the second aspect, is executed, or, so that the method in the third aspect, or any possible implementation of the third aspect, is executed.
  • a computer-readable storage medium in which computer instructions are stored.
  • the method in the first aspect, or the second aspect, or the third aspect, or any possible implementation of these aspects is executed.
  • a computer program product which includes a computer program code.
  • the computer program code runs on a computer, the method in any possible implementation of the first aspect, or the second aspect, or the third aspect, or any of these aspects is executed.
  • a communication system comprising the communication device as described in the fourth aspect and/or the communication device as described in the fifth aspect.
  • FIG1 is a schematic diagram of a system architecture of a communication system applicable to the technical solution of the present application
  • FIG2 is a schematic diagram of a communication system process
  • FIG3 is a schematic diagram of cascade coding
  • FIG4 is a schematic diagram of a method for encoding and decoding a concatenated code provided by the present application
  • FIG5 is a schematic flow chart of a method for encoding and decoding a concatenated code provided in the present application
  • FIG6 is a schematic diagram of the encoding process of the concatenated code provided by the present application.
  • FIG7 is a schematic diagram of the encoding process of the transmitting end provided by the present application.
  • FIG8 is a schematic diagram of a base graph of a base matrix provided by the present application.
  • FIG9 is a schematic diagram of the technical effect of the improved LDPC code check matrix provided by the present application.
  • FIG10 is a schematic diagram of a decoding process of a receiving end provided by the present application.
  • FIG11 is a schematic diagram of a soft information iterative decoding solution at a receiving end provided by the present application.
  • FIG12 is a performance comparison between the solution provided by the present application and the existing solution
  • FIG13 is a schematic block diagram of a communication device provided by the present application.
  • FIG14 is a schematic structural diagram of the communication device provided in the present application.
  • the technical solution of the embodiment of the present application can be applied to various communication systems, including but not limited to: satellite communication system, the 5th generation (5G) system or new radio (NR) system, long term evolution (LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc.
  • the technical solution provided in the present application can also be applied to future communication systems, such as the sixth generation mobile communication system.
  • it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication system or other communication systems, etc., which are not limited in this article.
  • D2D device to device
  • V2X vehicle-to-everything
  • M2M machine to machine
  • MTC machine type communication
  • IoT Internet of Things
  • the communication system applicable to the present application may include one or more transmitting ends and one or more receiving ends.
  • one of the transmitting end and the receiving end may be a terminal device, and the other may be a network device.
  • both the transmitting end and the receiving end may be terminal devices.
  • the transmitting end may also be considered as an encoding end or encoding device, and the receiving end may also be considered as a decoding end or decoding device.
  • the terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device.
  • UE user equipment
  • the terminal device in the embodiment of the present application may be a device that provides voice and/or data connectivity to the user, and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc.
  • the terminal device in the embodiment can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.
  • the UE can be used to act as a base station.
  • the UE can act as a scheduling entity that provides sidelink signals between UEs in V2X or D2D, etc.
  • the device for realizing the function of the terminal can be a terminal, or a device capable of supporting the terminal to realize the function, such as a chip system or a chip, which can be installed in the terminal.
  • the chip system can be composed of a chip, or can include a chip and other discrete devices.
  • a network device may be a device with wireless transceiver functions, which may be a device that provides wireless communication function services, and is usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the fifth generation (5th generation, 5G) communication system, the base station in the sixth generation (6th generation, 6G) mobile communication system, the base station in the future mobile communication system or the access node in the wireless fidelity (wireless fidelity, Wi-Fi) system, the evolved node B (eNB) in the long term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB, or home Node B, HNB), the baseband unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), etc.
  • the next generation base station gNodeB, gNB
  • 5th generation, 5G fifth generation
  • the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, a relay station, a vehicle-mounted device, and a wearable device in a cloud radio access network (CRAN) scenario.
  • the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof.
  • the base station may also refer to a communication module, a modem, or a chip used to be set in the aforementioned device or apparatus.
  • the base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, a device that performs the base station function in a future communication system, and the like.
  • the base station may support networks with the same or different access technologies without limitation.
  • the device for realizing the function of the network device can be a network device, or a device capable of supporting the network device to realize the function, such as a chip system or a chip, which can be installed in the network device.
  • the chip system can be composed of a chip, or can include a chip and other discrete devices.
  • the concatenated code encoding or decoding scheme provided in the present application i.e., the channel encoding and decoding scheme
  • can be used in dedicated network equipment or general equipment can be applied to various network equipment (e.g., base station equipment) as described above, and can also be applied to various terminal equipment as described above.
  • the channel encoding or channel decoding scheme is mainly implemented by the channel encoding unit or channel decoding unit in these devices.
  • the functions of the transmitting end or the receiving end can be implemented by an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc., or by software (for example, program code in a memory), without limitation.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • software for example, program code in a memory
  • Figure 1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application.
  • the encoding and decoding methods of the cascade code provided by the present application can be applicable to the communication between the network device and the terminal, that is, the uplink or downlink communication.
  • the transmitting end in this article can be a terminal in the uplink communication or a network device in the downlink communication
  • the receiving end can be a network device in the uplink communication or a terminal in the downlink communication.
  • the technical solution of the present application can also be applied to the sidelink communication.
  • the transmitting end is the transmitting terminal in the sidelink communication
  • the receiving end is the receiving terminal in the sidelink communication.
  • it can also be applied to other communication scenarios, which will not be repeated.
  • channel coding is located between source coding and modulation, and is responsible for channel coding the bits generated by the source, and then after modulation, the modulation symbols are sent through the noisy channel to the receiving end for demodulation, and then channel decoding is performed.
  • Channel decoding is located between demodulation and source decoding, and is responsible for recovering the source bit stream.
  • polar codes i.e., polar codes
  • LDPCs low-density parity checks
  • check codes LDPC codes and concatenated codes.
  • Channel coding and decoding is one of the core technologies in the field of wireless communications. The improvement of its performance will directly improve network coverage and user transmission rate.
  • polar codes are channel coding technologies that can be theoretically proven to reach the Shannon limit and have practical linear complexity coding and decoding capabilities.
  • Polar codes are a linear block code whose coding matrix (also called generator matrix) is F N . The coding process can be expressed as follows:
  • LDPC codes a type of linear block code with a sparse check matrix, that is, the density of non-zero elements in the check matrix is relatively low, which means that the number of zero elements in the check matrix is much larger than the number of non-zero elements.
  • a [N, K] linear block code can be understood as encoding an information sequence of length K to obtain coded bits of length N.
  • the base graph can be represented as an m ⁇ n matrix, including zero elements and non-zero elements, where zero elements can be represented by 0, -1 or null, and non-zero elements can be represented by 1. It can be used to indicate the position of non-zero elements in the base matrix, that is, the row and column positions of non-zero elements in the matrix. In some implementation methods, it can also be simplified to a table indicating the row and column positions of non-zero elements.
  • the check matrix H that can be used to construct the LDPC code.
  • the size of the basis matrix Hb can be m ⁇ n, the same as the base graph, and the size of the corresponding check matrix H is (m ⁇ p) ⁇ (n ⁇ p), where p is called the lifting size of the check matrix, or the multiple by which the basis matrix needs to be expanded, and m, n, and p are all positive integers.
  • the expression of the basis matrix can be as follows, where the element values corresponding to the non-zero elements in the basis graph are greater than or equal to 0, and the element values corresponding to the zero elements can be -1 or null:
  • Check matrix The expression of the check matrix of LDPC code can be shown as follows:
  • Each element I(a i,j ) (0 ⁇ i ⁇ m-1, 0 ⁇ j ⁇ n-1) in the check matrix H can be a zero matrix or a cyclic shift matrix. If a i,j is greater than or equal to 0, the cyclic shift matrix (for example, I(a i,j )) can be obtained by cyclically shifting the identity matrix of dimension p ⁇ p by a i,j positions. Therefore, a i,j is also called the shift factor of the cyclic shift matrix.
  • the value range of a i,j can be -1 ⁇ a i,j ⁇ p.
  • each non-zero element a i,j (0 ⁇ i ⁇ m-1, 0 ⁇ j ⁇ n-1) in the base matrix can be used to indicate the number of bits that need to be cyclically shifted in the corresponding unit matrix in the constructed check matrix.
  • a 0,0 can be used to indicate that the number of bits that need to be cyclically shifted in the unit matrix I(a 0,0 ) with a dimension of p ⁇ p in the upper left corner of the check matrix is a 0,0 .
  • I(a 0,0 ) is regarded as a whole, the position of I(a 0,0 ) in the check matrix is the same as the position of a 0,0 in the base matrix, that is, row 0 and column 0.
  • the zero elements in the base graph or base matrix are replaced with a p ⁇ p zero matrix.
  • Hadamard product is a type of matrix operation.
  • the minimum value of the Hamming distance between any two codes is called the minimum Hamming distance of the code group, also known as the minimum Hamming weight.
  • Soft value also known as log-likelihood ratio (LLR).
  • LLR log-likelihood ratio
  • Cascade coding includes outer code coding and inner code coding.
  • the input of the outer code coding is the information bit sequence to be encoded, and the output of the outer code is used as the input of the inner code.
  • the output of the inner code coding is the codeword after the cascade coding is completed.
  • outer code and inner code are relative concepts. Take a system that includes three encodings as an example. The first encoding is an outer code encoding relative to the second encoding, and the second encoding is an inner code encoding relative to the first encoding.
  • the second encoding is an outer code encoding relative to the third encoding
  • the third encoding is an inner code encoding relative to the second encoding.
  • the first is the outer code encoding
  • the second is the inner code encoding.
  • the output of the outer code encoding is used as the input of the inner code encoding.
  • FIG 3 is a schematic diagram of concatenated coding.
  • a concatenated coding strategy usually includes an inner code and an outer code.
  • the role of the inner code can be considered to be to obtain a better super channel by "noising" the physical channel, so that the channel condition seen by the outer code is better than the original physical channel.
  • BLER block error rate
  • the parameter N in the brackets represents the code length
  • K represents the number of message bits
  • D represents the minimum Hamming distance of the code.
  • the inner code can be a binary domain
  • the outer code can be other non-binary domains.
  • the codeword after concatenation is also a linear code.
  • the decoding of cascaded codes usually adopts iterative soft input soft output (SISO) decoding. Iterative SISO decoding is sometimes called turbo decoding.
  • SISO decoding is sometimes called turbo decoding.
  • turbo decoding One of the key points of this decoding method is to use the soft output of the first decoder as the soft input of the second decoder, and then use the soft output of the second decoder as the soft input of the first decoder. This repetitive iteration eventually produces a more reliable decision result.
  • a parallel concatenated code (PCC) architecture is used to concatenate polar and LDPC codes.
  • the polar code can obtain the advantage of flexible code length extension of rateless LDPC, thereby improving the expansion flexibility of polar code.
  • the reason why the rateless structure can make the code length extension of polar code more flexible is that the structure has a nested characteristic.
  • the rateless nested structure makes the short code always a subcode of the long code. As the code length increases, the previously encoded part does not need to be changed, and the code length can be extended by adding redundant bits of additional length.
  • the existing cascade code design of polar code and rateless LDPC code is mainly based on density polarization theory. Gaussian approximation and independence assumption make this optimization method have errors, so the performance of the cascade code scheme obtained based on this method needs to be improved.
  • an embodiment of the present application provides an encoding and decoding scheme of a concatenated code of a polar code and an improved LDPC code, which further improves the decoding performance and construction flexibility of the concatenated code and meets the requirements of rate compatibility.
  • the "improved LDPC code" provided in this application is different from the traditional LDPC code. Since the improved LDPC code can further reduce the bit error rate (BER) compared with the traditional LDPC code and meet the rate compatibility requirements, the improved LDPC code is also referred to as a nested error reducing-LDPC (N-ER-LDPC) code in this article.
  • BER bit error rate
  • FIG4 is a schematic diagram of a method for encoding and decoding a cascade code provided by the present application.
  • the message bit sequence u to be encoded first obtains the codeword c through the polar code encoder, and the codeword c is interleaved by the interleaver P to obtain the input sequence P(c) of the N-ER-LDPC code encoder.
  • P(c) is encoded by the N-ER-LDPC code to obtain the final cascade codeword C_N-ER-LDPC(P(c)), which is sent to the channel for transmission.
  • the receiving end uses soft information iterative decoding.
  • the receiving end receives the channel receiving vector y, and then uses the soft information iterative decoding scheme of the cascade code provided by the present application to decode the channel receiving vector y. Based on the preset maximum number of iterations, the soft information iterative decoding is performed to obtain the soft information sequence output by the soft successive cancellation list (SCL) decoder, and the final decoding estimation sequence is obtained after hard decision.
  • SCL soft successive cancellation list
  • the N-ER-LDPC decoder first decodes the sequence received from the channel (hereinafter referred to as the channel received sequence) to obtain soft information, which is used as the input of the soft SCL decoder. After being decoded by the soft SCL decoder, the soft value of the decoded sequence is generated. Then, the soft value is subtracted from the soft information to obtain the external information, and the external information and the channel received sequence are added and input into the N-ER-LDPC decoder for decoding to generate new soft information.
  • the channel received sequence the sequence received from the channel (hereinafter referred to as the channel received sequence) to obtain soft information, which is used as the input of the soft SCL decoder.
  • the soft value of the decoded sequence is generated. Then, the soft value is subtracted from the soft information to obtain the external information, and the external information and the channel received sequence are added and input into the N-ER-LDPC decoder for decoding to generate new soft information.
  • the new soft information is subtracted from the input of the N-ER-LDPC decoder (the input of the N-ER-LDPC decoder is obtained by adding the external information and the channel received sequence) to obtain new external information, and then the new external information is input into the soft SCL decoder for decoding to generate a new soft value of the decoded sequence. This is repeated iteratively. After reaching the maximum number of iterations, the soft value of the decoded sequence generated by the soft SCL decoder is hard-determined to obtain the final estimated sequence.
  • the codeword c may not be interleaved but directly encoded by the N-ER-LDPC code, and this embodiment of the present application does not limit this. If the codeword c is not interleaved, the decoding process does not include deinterleaving.
  • the channel coding scheme at the transmitting end and the channel decoding scheme at the receiving end are described in detail below.
  • FIG. 5 is a schematic flow chart of a method 500 for encoding and decoding a concatenated code provided in the present application.
  • the sending end performs concatenation coding on the message bit sequence to be coded to obtain a concatenated code word.
  • the transmitting end sends a concatenated code word.
  • the receiving end receives a channel receiving vector (or called a channel receiving sequence).
  • the receiving end uses a soft information iterative decoding scheme to decode the channel receiving vector to obtain a decoding estimation sequence.
  • the soft information iterative decoding scheme adopted in this application is a soft information iterative decoding algorithm that combines the soft SCL decoding algorithm and the belief propagation (BP) decoding algorithm, and has low decoding complexity.
  • FIG. 6 is a schematic diagram of a concatenated code encoding process provided by the present application.
  • the main process of the concatenated coding at the transmitting end can be as follows:
  • the above interleaving of the polar code codeword Co is an optional step, that is, the polar code codeword Co can be directly N-ER-LDPC encoded without interleaving.
  • S710 A transmitting end performs polar code encoding on a message bit sequence to be encoded to obtain a first encoded codeword with a length of N_o.
  • the message bit sequence to be encoded may also be referred to as an information bit sequence.
  • the transmitting end completes the outer code encoding of the concatenated code, and the first encoded codeword can be called a polar codeword or an outer codeword.
  • method 700 also includes S720.
  • the transmitting end interleaves the first encoded codeword to obtain a second encoded codeword.
  • the interleaving in S720 includes outer interleaving and inner interleaving.
  • the outer interleaving can be implemented by an outer interleaver, and the inner interleaving can be implemented by an inner interleaver.
  • the labels corresponding to the R frozen bits of the first coded codeword are mapped to the R rows of the generator matrix of the improved LDPC code, and the row weight of the R rows is lower than or equal to the row weight of the other rows of the generator matrix except the R rows, and the labels corresponding to the I message bits of the first coded codeword are mapped to the I rows of the generator matrix of the improved LDPC code, and the row weight of the I rows is higher than or equal to the row weight of the other rows of the generator matrix except the I rows.
  • R N_o-K_o
  • I K_o.
  • the number of non-zero elements contained in each column of the generator matrix of the improved LDPC code is called the column weight.
  • the outer interleaving maps the labels corresponding to the R frozen bits of the first encoded codeword to the R rows corresponding to the first R row indices in the set, and maps the labels corresponding to the message bits of the first encoded codeword to the I rows corresponding to the last I row indices in the set.
  • set F is mapped to the first R elements of set S, that is, F->S[1:R]
  • set J is mapped to the last I elements of set S, that is, J->S[(N_o-I+1):N_o].
  • the inner interleaving includes: interleaving the mapping relationship between the labels corresponding to the R frozen bits and the R rows, and interleaving the mapping relationship between the labels corresponding to the I message bits and the I rows.
  • the inner interleaving may be any one of the following:
  • the transmitting end performs improved LDPC code encoding on the second encoded codeword to obtain a concatenated codeword of length N_i.
  • the second encoded codeword is obtained by interleaving the first encoded codeword. If the method 700 does not perform S720, the second encoded codeword is the same as the first encoded codeword.
  • the improved LDPC code is obtained according to the base matrix and the lifting matrix of the improved LDPC code.
  • Figure 9 shows a schematic diagram of the BER performance of the improved LDPC code provided in an embodiment of the present application as an inner code. As shown in Figure 9, since the improved LDPC code has an all-zero column, the corresponding SNR range is wider when the BER is equal to 0.1.
  • the check matrix of the improved LDPC code includes at least s columns with a column weight of 1, where s is a positive integer. At least s columns include the last (N_i-N_o) columns of the check matrix. It can be understood that the columns with a column weight of 1 correspond to the unit matrix in the check matrix of the improved LDPC code. This feature can ensure that the improved LDPC code has nested performance, and can make the cascade coding provided in the embodiment of the present application meet the requirements of rate compatibility.
  • the difference between the number of columns and the number of rows of the parity check matrix of the improved LDPC code is divisible by 2. It can be understood that the outer code of the improved LDPC code is a polar code with the length of the mother code, and the length of the polar code is a power of 2, that is, N_o is divisible by 2. Because the difference between the number of columns and the number of rows of the parity check matrix of the improved LDPC code is N_o, the difference between the number of columns and the number of rows of the parity check matrix of the improved LDPC code is divisible by 2.
  • the improved LDPC code base matrix can be extended by a special lifting method to obtain the improved LDPC code check matrix.
  • the following introduces the design of the lifting matrix and the steps of obtaining the improved LDPC code check matrix based on the lifting matrix and the improved LDPC code base matrix.
  • the base matrix of the LDPC code is a matrix with m rows and n columns, and it is necessary to expand the base matrix p times, that is, to obtain a check matrix with a dimension equal to mp*np (m ⁇ n), where m and n are both positive integers.
  • the steps to obtain the improved check matrix of the LDPC code are as follows:
  • j) is the element of the i-th row and j-th column in the updated lifting matrix
  • H opt represents the basis matrix
  • H opt (i, j) is the element of the i-th row and j-th column in the basis matrix.
  • H m can be called the Hadamard product or basic product of H opt and M.
  • H opt2 (i, j) is the element in the i-th row and j-th column of the matrix H opt2 .
  • H m can be called the Hadamard product or basic product of H opt2 and M.
  • the check matrix of the improved LDPC code is obtained by expanding the updated base matrix by p times.
  • the expression of the updated basis matrix can be as follows:
  • Each element I(a i,j ) (1 ⁇ i ⁇ m, 1 ⁇ j ⁇ v) in the check matrix H can be a zero matrix or a cyclic shift matrix. If a i,j is greater than or equal to 0, the cyclic shift matrix (for example, I(a i,j )) can be obtained by cyclically shifting the identity matrix of dimension p ⁇ p by a i,j positions. Therefore, a i,j is also called the shift factor of the cyclic shift matrix.
  • the value range of a i,j can be -1 ⁇ a i,j ⁇ p.
  • the improved LDPC code check matrix is obtained according to the updated base matrix, including: expanding the updated base matrix by P times to obtain an intermediate check matrix; supplementing t*p columns of all-zero columns before the first column of the intermediate check matrix to obtain the improved LDPC code check matrix.
  • the expression of the obtained improved LDPC code check matrix can be shown as follows:
  • the element I(0) in the check matrix H represents an all-zero matrix with a size of p rows and t*p columns.
  • the lifting matrix can be obtained by multiplying the following two vectors:
  • the dimensions of the two vectors are m and v, respectively, and it must be satisfied that any two elements in the vectors do not overlap. For example, select two random sets (difference sets) with dimensions 1*m and 1*v respectively;
  • the proposed extension scheme represents the BER performance of the N-ER-LDPC code obtained according to the lifting matrix provided by the present application
  • the approximated cycle extrinsic message degres (ACE) extension scheme represents the BER performance of the N-ER-LDPC code obtained according to the lifting matrix designed according to the ACE algorithm. It can be seen that in the interval where BER is less than 0.1, the BER of the present application scheme is greater than that of ACE This means a higher BER for the solution, which means a larger SNR dynamic range.
  • the second encoding codeword may be encoded according to the check matrix of the improved LDPC code, thereby obtaining a concatenated codeword of length N_i.
  • the transmitting end can directly encode the second encoding codeword according to the check matrix of the improved LDPC code.
  • the transmitting end does not need to determine the check matrix of the improved LDPC code according to the above method before encoding the second code.
  • the transmitting end outputs a concatenated code word.
  • FIG. 10 is a schematic diagram of the decoding process of the receiving end provided in the present application.
  • the receiving end obtains a channel receiving vector having a length of N_i .
  • N_i is the length of the inner code of the concatenated code
  • the inner code of the concatenated code is an improved LDPC code
  • the outer code of the concatenated code is a polar code (specifically, the first encoding codeword mentioned above)
  • N_i is a positive integer.
  • the step of decoding the channel reception vector at the receiving end may include S1020 to S1050.
  • the receiving end uses the improved SISO decoding algorithm of the LDPC code to decode the channel receiving vector to obtain a first soft information sequence with a length of N_i .
  • the "soft information” or “soft value” in the present application refers to LLR.
  • the length of the first soft information sequence is N_i , which means that the first soft information sequence contains N_i LLRs, and the N_i LLRs are obtained by decoding the channel reception vector y using a SISO decoder of an improved LDPC code.
  • the number of iterations of the SISO decoder is denoted as inner_iter.
  • the receiving end deinterleaves the first soft information sequence to obtain the deinterleaved first soft information sequence, and extracts the soft information at the first N_o positions in the deinterleaved first soft information sequence to obtain the second soft information sequence, where N_o is the length of the outer code of the concatenated code, and N_o is a positive integer.
  • the receiving end completes the deinterleaving of the first soft information sequence, and reads the soft information at the first N_o positions from the deinterleaved first soft information sequence to obtain the soft information sequence of the polar outer code, that is, to obtain the second soft information sequence.
  • the receiving end directly reads the soft information at the first N_o positions from the first soft information sequence to obtain the soft information sequence of the polar outer code, that is, obtains the second soft information sequence.
  • the receiving end performs soft information iterative decoding based on the second soft information sequence, the channel reception vector, and a preset maximum number of iterations of the concatenated code by using a soft SCL decoding algorithm of the polar code and an improved SISO decoding algorithm of the LDPC code to obtain a third soft information sequence.
  • the improved SISO decoding algorithm of LDPC code is related to the improved check matrix of LDPC code described in the above method 700.
  • the receiving end performs the improved SISO decoding algorithm of LDPC code according to the improved check matrix of LDPC code.
  • the receiving end can directly perform the SISO decoding algorithm of the improved LDPC code according to the parity check matrix of the improved LDPC code.
  • the receiving end does not need to determine the parity check matrix of the improved LDPC code in the manner described in method 700 before performing the SISO decoding algorithm of the improved LDPC code.
  • the receiving end adopts the soft information iterative decoding of the present application. After reaching a preset maximum number of iterations max_Iter through iterative decoding, the soft SCL decoder outputs a third soft information sequence, which is a soft value sequence of the decoding sequence.
  • the process of iterative decoding of the soft information is as follows:
  • the (j-1)th soft information sequence output by the soft SCL decoding algorithm is obtained;
  • the j-th extrinsic information of the SISO decoding algorithm is obtained by subtracting the soft information sequence input to the soft SCL decoding algorithm in the (j-1)-th soft information iterative decoding process from the (j-1)-th soft information sequence;
  • the sum of the jth external information and the channel receiving vector is used as the input of the SISO decoding algorithm in the jth soft information iterative decoding process. Obtain the output of the SISO decoding algorithm in the jth soft information iteration process;
  • the j-th soft information sequence of the soft SCL decoding algorithm is obtained by subtracting the sum of the j-th external information and the channel reception vector from the output of the SISO decoding algorithm in the j-th soft information iteration process.
  • the j-th soft information sequence of the soft SCL decoding algorithm is the soft information sequence output by the soft SCL decoding algorithm during the j-th soft information iteration.
  • the jth extrinsic information of the SISO decoding algorithm is the extrinsic information input to the SISO decoding algorithm during the jth soft information iteration process.
  • the second soft information sequence is the soft information sequence input to the soft SCL decoding algorithm during the first soft information iteration process
  • the third soft information sequence is the soft information sequence output by the soft SCL decoding algorithm during the last soft information iteration process
  • S1050 The receiving end performs hard decision on the third soft information sequence to obtain a decoding estimation sequence.
  • S1060 The receiving end outputs a decoding estimation sequence.
  • FIG11 is a schematic diagram of the soft information iterative decoding scheme at the receiving end provided in the present application.
  • the channel received vector y (y_1, y_2, ..., y_N i ) is first sent to the SISO decoder of the N-ER-LDPC for decoding.
  • the soft_SCL decoder is used to decode the polar code to obtain two outputs L_out and L_code.
  • L_out is the soft value of the message on the U side of the polar code
  • L_code is the soft value of the codeword on the C side of the polar code.
  • the UE side of the polar code represents the message side of the polar code
  • the soft value of the message on the U side of the polar code refers to the soft value corresponding to the message sequence before the polar code is encoded.
  • the message sequence before the polar code is encoded includes message bits and frozen bits.
  • the C side of the Polar code represents the codeword side of the polar code
  • the soft value of the codeword on the C side of the polar code refers to the soft value corresponding to the codeword obtained after the polar code is encoded.
  • the soft_SCL decoder has two inputs, L_polar and List, where L_polar is the soft information sequence of the polar outer code described in step (3), L_polar is the soft input LLR value of the polar code soft_SCL decoder, and List is the size of the decoding list, which is a power of 2, such as 1, 2, 4, 8, 16, 32, etc.
  • (b) Calculate the extrinsic information (soft value) sent to the N-ER-LDPC decoder.
  • the length of this extrinsic information is equal to the length of the channel reception vector, which is also N_i bits, of which the values of N_i-N_o non-systematic bits are 0, and the values of the other N_o positions are equal to (P(L_code)-L_polar), that is, the N_o non-zero elements are equal to the result of subtracting the first input of the soft_SCL decoder from the second output (after interleaving) of the soft_SCL decoder.
  • the soft information iterative decoding process involves two decoders, namely a soft SCL decoder for polar codes (ie, outer codes of concatenated codes) and a decoder for N-ER-LDPC codes (ie, inner codes of concatenated codes).
  • the deinterleaving in the above decoding process is an optional step. If the encoding process does not include the interleaving step, the decoding process does not include the deinterleaving step.
  • the soft values of the polar outer code and the soft values of the improved LDPC code do not exchange soft values at the all-zero columns during the large iterative decoding process, and the soft values Partial updates can improve large-iteration decoding performance.
  • the method provided in the embodiment of the present application has low coding complexity and can achieve rate compatibility.
  • the coding and decoding methods of the concatenated code provided in the embodiment of the present application and the performance of the NR LDPC code were tested and compared under the conditions that the simulated channel is an additive white Gaussian noise (AWG) channel and the modulation mode is binary phase shift key (BPSK).
  • the outer code coding scheme is a polar code concatenated with a 2-bit CRC, and the polar code is constructed in a density evolution manner.
  • the polar outer code decoder in the decoder is a soft SCL decoding with a list length of 4, the inner code decoder adopts BP decoding with 10 iterations, the first 2p columns of the check matrix of the improved LDPC code are punctured, and the maximum number of iterations of the concatenated code decoding is 10.
  • the performance of the NR LDPC code under BP decoding with 50 and 100 iterations was tested.
  • r LDPC is the number of rows of the improved LDPC check matrix
  • n LDPC is the number of columns of the improved LDPC check matrix
  • p is the lifting size
  • PN is the puncturing position of the improved LDPC code
  • R N-ER-LDPC is the code rate of the inner code
  • K LDPC is the number of message bits of the inner code
  • R polar is the code rate of the Polar outer code (ie, K polar /K LDPC )
  • CRC is the length of the outer code
  • K polar is the length of the payload message bit of the Polar outer code (excluding CRC)
  • N CC is the code length of the overall concatenated code
  • R CC is the code rate of the overall concatenated code.
  • the simulation parameters of the NR LDPC code are shown in Table 3. Where K NR-LDPC is the number of message bits of the NR LDPC code, and R NR-LDPC is the code rate of the NR LDPC code.
  • the performance comparison of the concatenated code provided by the embodiment of the present application and the performance of the NR LDPC code is shown in Figure 12.
  • the horizontal axis is the number of message bits
  • the vertical axis is the SNR required to achieve a bit error rate of 0.01.
  • the scheme proposed in this application can meet the requirements of rate compatibility, and has better error correction performance than the existing NR LDPC code at different code lengths and code rates.
  • Fig. 13 is a schematic block diagram of a communication device provided in the present application.
  • the communication device 1300 includes a processing unit 1310 and a transceiver unit 1320 .
  • the communication device 1300 may correspond to the transmitting end in the method embodiment of the present application.
  • each unit of the communication device 1300 is used to implement the following functions:
  • the processing unit 1310 is used to: perform polarization coding on a message bit sequence to be coded to obtain a first coded codeword of length N_o, where N_o is a positive integer; perform improved LDPC code coding on a second coded codeword to obtain a concatenated code codeword of length N_i, where the second coded codeword is determined according to the first coded codeword, and N_i is a positive integer; wherein the first t columns of a base matrix of the improved LDPC code are all-zero columns, where t is a positive integer, and 2 ⁇ t ⁇ T, where T is equal to a ratio of N_o to p, where p is a multiple by which the base matrix needs to be expanded, and where p is a positive integer; and the check matrix of the improved LDPC code includes at least s columns with a column weight of 1, where the at least s columns include the last (N_i-N_o) columns.
  • the transceiver unit 1320 is configured to output the concatenated code word.
  • the communication device 1300 may correspond to the receiving end in the method embodiment of the present application.
  • each unit of the communication device 1300 is used to implement the following functions:
  • the transceiver unit 1320 is used to obtain a channel reception vector with a length of N_i, where N_i is the length of an inner code of the concatenated code, the inner code of the concatenated code is an improved LDPC code, the outer code of the concatenated code is a polar code, and N_i is a positive integer.
  • the processing unit 1310 is used to: use the improved SISO decoding algorithm of the LDPC code to decode the channel receiving vector to obtain a length of N_ i , the SISO decoding algorithm is related to the parity check matrix of the improved LDPC code; wherein the first t columns of the base matrix of the improved LDPC code are all-zero columns, t is a positive integer, and 2 ⁇ t ⁇ T, T is equal to the ratio of N_o to p, p is a multiple of the base matrix that needs to be expanded, and p is a positive integer; the parity check matrix of the improved LDPC code includes at least s columns with a column weight of 1, and the at least s columns include the last (N_i-N_o) columns; based on the second soft information sequence, the channel reception vector and the preset maximum number of iterations of the concatenated code, soft information iterative decoding is performed through the soft SCL decoding algorithm of the polar code and the SISO decoding algorithm of the improved LD
  • the transceiver unit 1320 is configured to output the estimated sequence.
  • the processing unit 1310 is used to perform the processing and/or operation implemented by the transmitting end in addition to the sending and receiving actions.
  • the transceiver unit 1320 is used to perform the receiving (or input) action of the transmitting end, and/or, to perform the sending (or output) action of the transmitting end.
  • the processing unit 1310 is used to execute S510
  • the transceiver unit 1320 is used to execute S520 .
  • the processing unit 1310 is used to execute S710 - S730
  • the transceiver unit 1320 is used to execute S740 .
  • the processing unit 1310 is used to perform processing and/or operations implemented by the receiving end in addition to the sending and receiving actions.
  • the transceiver unit 1320 is used to perform the receiving (or input) action of the receiving end, and/or, to perform the sending (or output) action of the receiving end.
  • the processing unit 1310 is configured to execute S530 .
  • the transceiver unit 1320 is used to execute S1010
  • the processing unit 1320 is used to execute S1020 - S1050
  • the transceiver unit 1320 is used to execute S1060 .
  • the communication device 1400 includes: one or more processors 1410, one or more memories 1420, and one or more communication interfaces 1430.
  • the processor 1410 is used to control the communication interface 1430 to send and receive signals
  • the memory 1420 is used to store a computer program
  • the processor 1410 is used to call and run the computer program from the memory 1420, so that the communication device 1400 performs the processing performed by the transmitting end or the receiving end in each method embodiment of the present application.
  • the processor 1410 may have the function of the processing unit 1310 shown in Figure 13, and the communication interface 1430 may have the function of the transceiver unit 1320 shown in Figure 13.
  • the processor 1410 may be used to execute the processing or operation performed by the communication device, and the communication interface 1430 is used to execute the sending and/or receiving operation of the communication device.
  • the dotted box behind a device indicates that there may be more than one device.
  • the memory and the processor in the above-mentioned device embodiments may be physically independent units, or the memory may be integrated with the processor, which is not limited in this document.
  • the present application also provides a computer-readable storage medium, in which computer instructions are stored.
  • computer instructions are executed on a computer, the operations and/or processing performed by the sending end in each method embodiment of the present application are executed.
  • the present application also provides a computer-readable storage medium, in which computer instructions are stored.
  • computer instructions are executed on a computer, the operations and/or processing performed by the receiving end in each method embodiment of the present application are executed.
  • the present application also provides a computer program product, which includes computer program code or instructions.
  • a computer program product which includes computer program code or instructions.
  • the present application also provides a computer program product, which includes computer program code or instructions.
  • a computer program product which includes computer program code or instructions.
  • the present application also provides a chip, which includes a processor, a memory for storing computer programs is set independently of the chip, and the processor is used to execute the computer program stored in the memory, so that a device equipped with the chip performs the operations and/or processing performed by the sending end in any method embodiment.
  • the chip may further include a communication interface.
  • the communication interface may be an input/output interface, or an interface circuit, etc.
  • the chip may further include the memory.
  • the present application also provides a chip, which includes a processor, a memory for storing computer programs which is set independently of the chip, and the processor is used to execute the computer program stored in the memory, so that a device equipped with the chip performs the operations and/or processing performed by the receiving end in any one of the method embodiments.
  • the chip may further include a communication interface.
  • the communication interface may be an input/output interface, or an interface circuit, etc.
  • the chip may further include the memory.
  • the processor may be one or more, the memory may be one or more, and the memory may be one or more.
  • the present application also provides a communication device (for example, a chip or a chip system), including a processor and a communication interface, according to the operation and/or processing performed by the transmitting end in any of the aforementioned method embodiments, the communication interface is used to receive (or referred to as input) message bits to be encoded, and the processor encodes the message bits to be encoded.
  • the communication interface is also used to send (or referred to as output) data and/or information processed by the processor, for example, sending a cascade code word.
  • the present application also provides a communication device (for example, a chip or a chip system), including a processor and a communication interface, according to the operation and/or processing performed by the receiving end in any of the foregoing method embodiments, the communication interface is used to receive (or be called input) a channel reception vector, and the processor is used to decode the channel reception vector.
  • the communication interface is also used to send (or be called output) a decoding estimation sequence.
  • the present application also provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is used to execute a computer program or instruction stored in the at least one memory, so that the communication device performs the operations and/or processing performed by the sending end in any one of the method embodiments.
  • the present application also provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is used to execute a computer program or instruction stored in the at least one memory, so that the communication device performs the operations and/or processing performed by the receiving end in any one of the method embodiments.
  • the present application also provides a communication system, including a transmitting end and a receiving end in the method embodiment of the present application.
  • the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories.
  • the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.
  • the volatile memory may be a random access memory (RAM), which is used as an external cache.
  • RAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchlink DRAM
  • DRRAM direct rambus RAM
  • the method provided in the above embodiment can be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software When implemented by software, it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product may include one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated.
  • numbers such as “first” and “second” are used to distinguish between identical or similar items with substantially identical functions and effects.
  • the first information and the second information are only used to distinguish different information, and the order of sending/receiving them is not limited.
  • numbers such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit them to be different.
  • messages bit and “information bit” are sometimes used interchangeably.
  • the message bit of the polar outer code can also be expressed as the information bit of the polar outer code.
  • N_o and N o may also be used interchangeably
  • N_i and N i may also be used interchangeably. There are some similar replacement expressions in the text, which will not be repeated one by one.
  • "at least one” means one or more, and “more” means two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that three relationships may exist.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an "or” relationship.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art.
  • the computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

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Abstract

本申请实施例提供了一种级联码的编码和译码的方法以及通信装置，该级联码以极化码为外码，且以本申请提供的N-ER-LDPC码为内码。本申请提供该E-NR-LDPC码的基矩阵以及基矩阵的提升策略。根据该提升策略对基矩阵进行提升，可以获得N-ER-LDPC码的校验矩阵，该校验矩阵具有明显的外部特征，可以在提升译码性能的同时满足速率兼容的需求。

Description

级联码的编码和译码的方法以及通信装置
本申请要求于2022年9月29日提交俄罗斯专利局、申请号为2022125446、申请名称为“一种嵌套级联码编码方案”的俄罗斯专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及信道编码领域，更具体地，涉及一种级联码的编码和译码的方法以及通信装置。
背景技术
在信道编码领域，级联码(concatenated code)可以实现更高的编码增益和更低的译码时延。一个级联编码策略通常包含内码和外码，内码的作用可以认为是通过给物理信道“降噪”来获得更好的超级信道，使得外码所看到的信道状况优于原始的物理信道。
目前，级联不同码字的方案有很多，例如，极化码和低密度奇偶校验(low density parity check codes，LDPC)码的级联码方案、里德-所罗门(reed-solomon，RS)码和极化码的级联码方案，以及极化码和低密度生成矩阵(low density generation matrix，LDGM)的级联方案等。但是总体而言，这样级联码的译码性能都有待提升。
发明内容
本申请实施例提供一种级联码的编码和译码的方法，可以提升级联码的译码性能，满足速率兼容的需求。
第一方面，提供了一种级联码的编码的方法，该方法包括：对待编码的消息比特序列进行极化码编码，得到长度为N_o的第一编码码字，该N_o为正整数；对第二编码码字进行改进的低密度奇偶校验(low density parity check codes，LDPC)码编码，得到长度为N_i的级联码码字，该第二编码码字是根据该第一编码码字确定的，该N_i为正整数；输出该级联码码字；其中，该改进的LDPC码的基矩阵的前t列为全零列，该t为正整数，且2≤t＜T，该T等于该N_o与p的比值，该p为该基矩阵需要扩展的倍数，该p为正整数；该改进的LDPC码的校验矩阵包括至少s列列重为1的列，该至少s列包括后(N_i-N_o)列，该s为正整数。
其中，第二编码码字与第一编码码字相同，或者，第二编码码字是对第一编码码字进行交织后得到的。
在本申请实施例中，由于改进的LDPC码的基矩阵的前t列为全零列，因此本申请实施例提供的方法在大迭代译码过程中，极化码外码的软值和改进的LDPC码的软值在全零列处不交换软值，而软值的部分更新可以提升大迭代译码性能。
此外，由于改进的LDPC码的校验矩阵的后(N_i-N_o)列的列重为1，因此本申请实施例提供的方法编码复杂度低，可以实现速率兼容。
结合第一方面，在第一方面的某些实现方式中，该基矩阵的大小为m行n列，该方法还包括：构造一个大小为m的行矢量和一个大小为v的列矢量，且，该行矢量中任意两个元素不同，该列矢量中任意两个元素不同，该m、该n和该v均为正整数，该m和该v均小于或等于该p，v＝n，或者，v＝n-t；根据该行矢量和该列矢量，得到提升矩阵；根据该提升矩阵和该基矩阵，得到更新后的基矩阵；根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵。
结合第一方面，在第一方面的某些实现方式中，该根据该行矢量和该列矢量，得到该提升矩阵，包括：构造该提升矩阵M(i,j)＝ri·cjmodp，其中，该行矢量Crows＝(r1,r2,...,rm)，ri为该行矢量Crows中的第i个元素，1≤i≤m，该列矢量Ccols＝(c1,c2,...,cv)，cj为该列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
结合第一方面，在第一方面的某些实现方式中，该根据提升矩阵和该基矩阵，得到更新后的基矩 阵，包括：若v＝n，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，若v＝n-t，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；其中，该Hopt为所述基矩阵，该Hopt2为通过提取所述基矩阵中的非零列得到的矩阵，该M为所述提升矩阵。
其中，Hopt⊙M表示Hopt和M的哈达马积，Hopt2⊙M表示Hopt2和M的哈达马积。哈达马积也可以称为基本积。
基于上述技术方案，由于基矩阵的前t列为全零列，因此可以构造维度v＝n-t的列矢量，从而可以降低计算复杂度。
结合第一方面，在第一方面的某些实现方式中，该根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵，包括：若v＝n，则对该更新后的基矩阵进行p倍的扩展得到所述校验矩阵；或者，若v＝n-t，则对该更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对该中间校验矩阵补充t*p列全零列得到该校验矩阵。
第二方面，提供了一种级联码的译码的方法，该方法包括：获取长度为N_i的信道接收矢量，该N_i为级联码的内码的长度，该级联码的内码为改进的LDPC码，该级联码的外码为极化码，该N_i为正整数；采用该改进的LDPC码的软输入软输出(soft input soft output，SISO)译码算法，对该信道接收矢量进行译码，获得长度为N_i的第一软信息序列，该SISO译码算法与该改进的LDPC码的校验矩阵相关；基于第二软信息序列、该信道接收矢量和该级联码的预设定的最大迭代次数，通过该极化码的软连续取消列表(successive cancellation list，SCL)译码算法和该改进的LDPC码的SISO译码算法，进行软信息迭代译码，获得第三软信息序列，该第二软信息序列是根据该第一软信息序列确定的；对该第三软信息序列进行硬判决，获得译码估计序列；输出该译码估计序列；其中，该改进的LDPC码的基矩阵的前t列为全零列，该t为正整数，且2≤t＜T，该T等于该N_o与p的比值，该p为该基矩阵需要扩展的倍数，该p为正整数；该改进的LDPC码的校验矩阵包括至少s列列重为1的列，该至少s列包括后(N_i-N_o)列，该s为正整数。
其中，接收端对第一软信息序列进行解交织，并从解交织后的第一软信息序列中读取前N_o个位置上的软信息，获得第二软信息序列。或者，接收端读取第一软信息序列的前N_o个位置上的软信息，获得第二软信息序列。
针对本申请提供的polar码和改进的LDPC码(也称N-ER-LDPC码)的级联码，其译码采用软SCL译码算法和SISO译码算法相结合的软信息迭代译码，可以降低译码复杂度。
结合第二方面，在第二方面的某些实现方式中，该基矩阵的大小为m行n列，该方法还包括：构造一个大小为m的行矢量和一个大小为v的列矢量，且，该行矢量中任意两个元素不同，该列矢量中任意两个元素不同，该m、该n和该v均为正整数，该m和该v均小于或等于该p，v＝n，或者，v＝n-t；根据该行矢量和该列矢量，得到提升矩阵；根据该提升矩阵和该基矩阵，得到更新后的基矩阵；根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵。
结合第二方面，在第二方面的某些实现方式中，该根据该行矢量和该列矢量，得到该提升矩阵，包括：构造该提升矩阵M(i,j)＝ri·cjmodp，其中，该行矢量Crows＝(r1,r2,...,rm)，ri为该行矢量Crows中的第i个元素，1≤i≤m，该列矢量Ccols＝(c1,c2,...,cv)，cj为该列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
结合第二方面，在第二方面的某些实现方式中，根据提升矩阵和该基矩阵，得到更新后的基矩阵，包括：若v＝n，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，若v＝n-t，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；其中，该Hopt为该基矩阵，该Hopt2为通过提取该基矩阵中的非零列得到的矩阵，该M为该提升矩阵。
其中，Hopt⊙M表示Hopt和M的哈达马积，Hopt2⊙M表示Hopt2和M的哈达马积。哈达马积也可以称为基本积。
基于上述技术方案，由于基矩阵的前t列为全零列，因此可以构造维度v＝n-t的列矢量，从而可以降低计算复杂度。
结合第二方面，在第二方面的某些实现方式中，该根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵，包括：若v＝n，则对该更新后的基矩阵进行p倍的扩展得到该校验矩阵；或者，若v＝n-t，则对该更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对该中间校验矩阵补充t*p列全零列得 到该校验矩阵。
第三方面，提供了一种级联码的译码的方法，该方法包括：获取长度为N_i的信道接收矢量，该N_i为级联码的内码的长度，该级联码的内码为改进的LDPC码，该级联码的外码为极化码，该N_i为正整数；其中，该改进的LDPC码的基矩阵的前t列为全零列，该t为正整数，且2≤t＜T，该T等于该N_o与p的比值，该p为该基矩阵需要扩展的倍数，该p为正整数；该改进的LDPC码的校验矩阵包括至少s列列重为1的列，该至少s列包括后(N_i-N_o)列，该s为正整数；对该信道接收矢量进行译码，输出译码结果。
在本申请实施例中，由于改进的LDPC码的基矩阵的前t列为全零列，因此本申请实施例提供的方法在大迭代译码过程中，极化码外码的软值和改进的LDPC码的软值在全零列处不交换软值，而软值的部分更新可以提升大迭代译码性能。
结合第三方面，在第三方面的某些实现方式中，该基矩阵的大小为m行n列，该方法还包括：构造一个大小为m的行矢量和一个大小为v的列矢量，且，该行矢量中任意两个元素不同，该列矢量中任意两个元素不同，该m、该n和该v均为正整数，该m和该v均小于或等于该p，v＝n，或者，v＝n-t；根据该行矢量和该列矢量，得到提升矩阵；根据该提升矩阵和该基矩阵，得到更新后的基矩阵；根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵。
结合第三方面，在第三方面的某些实现方式中，该根据该行矢量和该列矢量，得到该提升矩阵，包括：构造该提升矩阵M(i,j)＝ri·cjmodp，其中，该行矢量Crows＝(r1,r2,...,rm)，ri为该行矢量Crows中的第i个元素，1≤i≤m，该列矢量Ccols＝(c1,c2,...,cv)，cj为该列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
结合第三方面，在第三方面的某些实现方式中，根据提升矩阵和该基矩阵，得到更新后的基矩阵，包括：若v＝n，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，若v＝n-t，则确定该更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；其中，该Hopt为该基矩阵，该Hopt2为通过提取该基矩阵中的非零列得到的矩阵，该M为该提升矩阵。
其中，Hopt⊙M表示Hopt和M的哈达马积，Hopt2⊙M表示Hopt2和M的哈达马积。哈达马积也可以称为基本积。
基于上述技术方案，由于基矩阵的前t列为全零列，因此可以构造维度v＝n-t的列矢量，从而可以降低计算复杂度。
结合第三方面，在第三方面的某些实现方式中，该根据该更新后的基矩阵，得到该改进的LDPC码的校验矩阵，包括：若v＝n，则对该更新后的基矩阵进行p倍的扩展得到该校验矩阵；或者，若v＝n-t，则对该更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对该中间校验矩阵补充t*p列全零列得到该校验矩阵。
第四方面，提供了一种通信装置，该通信装置具有实现第一方面或第一方面的任一可能的实现方式中的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元。
第五方面，提供了一种通信装置，该通信装置具有实现第二方面或第二方面的任一可能的实现方式中的方法的功能，或者，该通信装置具有实现第三方面或第三方面的任一可能的实现方式中的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的单元。
第六方面，提供一种通信装置，包括处理器和存储器。可选地，还可以包括收发器。其中，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，并控制收发器收发信号，以使通信装置执行如第一方面或第一方面的任一可能的实现方式中的方法。
第七方面，提供一种通信装置，包括处理器和存储器。可选地，还可以包括收发器。其中，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，并控制收发器收发信号，以使通信装置执行如第二方面或第二方面的任一可能的实现方式中的方法，或者，以使通信装置执行如第三方面或第三方面的任一可能的实现方式中的方法。
第八方面，提供一种通信装置，包括处理器和通信接口，该通信接口用于接收数据和/或信息，并将接收到的数据和/或信息传输至该处理器，该处理器处理该数据和/或信息，以及，通信接口还用于输 出经处理器处理之后的数据和/或信息，以使得如第一方面，或第一方面的任一可能的实现方式中的方法被执行。
第九方面，提供一种通信装置，包括处理器和通信接口，该处理器处理待发送的数据和/或信息，以及，通信接口还用于输出经处理器处理之后的数据和/或信息，以使得如第二方面，或第二方面的任一可能的实现方式中的方法被执行，或者，以使得如第三方面，或第三方面的任一可能的实现方式中的方法被执行。
第十方面，提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得如第一方面，或第二方面，或，第三方面，或这些方面的任一可能的实现方式中的方法被执行。
第十一方面，提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得如第一方面，或第二方面，或第三方面，或这些方面中的任一方面的任一可能的实现方式中的方法被执行。
第十二方面，提供一种通信系统，包括如第四方面所述的通信装置，和/或如第五方面所述的通信装置。
附图说明
图1是适用于本申请的技术方案的通信系统的系统架构的示意图；
图2为通信系统流程的示意图；
图3为级联编码的示意图；
图4为本申请提供的级联码的编码和译码的方法的示意图；
图5为本申请提供的级联码的编码和译码的方法的示意性流程图；
图6为本申请提供的级联码的编码流程的示意图；
图7为本申请提供的发送端的编码流程的示意图；
图8为本申请提供的基矩阵的基图的示意图；
图9为本申请提供的改进的LDPC码的校验矩阵的技术效果的示意图；
图10为本申请提供的接收端的译码流程的示意图；
图11为本申请提供的接收端的软信息迭代译码方案的示意图；
图12为本申请提供的方案和现有方案的性能对比；
图13为本申请提供的通信装置的示意性框图；
图14为本申请提供的通信装置的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信系统，包括但不限于：卫星通信系统、第五代(the5th generation，5G)系统或新无线(new radio，NR)系统、长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)系统等。本申请提供的技术方案还可以应用于未来的通信系统，例如第六代移动通信系统。此外，还可以应用于设备到设备(device to device，D2D)通信，车联万物(vehicle-to-everything，V2X)通信，机器到机器(machine to machine，M2M)通信，机器类型通信(machine type communication，MTC)，以及物联网(internet of things，IoT)通信系统或者其它通信系统等，本文对此不作限定。
适用于本申请的通信系统，可以包括一个或多个发送端，以及，一个或多个接收端。可选地，发送端和接收端中的一个可以为终端设备，另一个可以为网络设备。或者，发送端和接收端均为终端设备。发送端又可以认为是编码端或编码设备，接收端又可以认为是解码端或解码设备。
示例性地，终端设备也可以称为用户设备(user equipment，UE)、接入终端、用户单元、用户站、移动站、移动台、移动终端(mobile terminal，MT)、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。本申请实施例中的终端设备可以是指向用户提供语音和/或数据连通性的设备，可以用于连接人、物和机，例如具有无线连接功能的手持式设备、车载设备等。本申请 的实施例中的终端设备可以是手机(mobile phone)、平板电脑(pad)、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备，虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。可选地，UE可以用于充当基站。例如，UE可以充当调度实体，其在V2X或D2D等中的UE之间提供侧行链路信号。
本申请实施例中，用于实现终端的功能的装置可以是终端，也可以是能够支持终端实现该功能的装置，例如芯片系统或芯片，该装置可以被安装在终端中。本申请实施例中，芯片系统可以由芯片构成，也可以包括芯片和其他分立器件。
示例性地，网络设备可以是具有无线收发功能的设备，该网络设备可以是提供无线通信功能服务的设备，通常位于网络侧，包括但不限于第五代(5th generation，5G)通信系统中的下一代基站(gNodeB，gNB)、第六代(6th generation，6G)移动通信系统中的基站、未来移动通信系统中的基站或无线保真(wireless fidelity，Wi-Fi)系统中的接入节点，长期演进(long term evolution，LTE)系统中的演进型节点B(evolved node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(node B，NB)、基站控制器(base station controller，BSC)、家庭基站(例如,home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)，传输接收点(transmission reception point，TRP)、发射点(transmitting point，TP)、基站收发台(base transceiver station，BTS)等。在一种网络结构中，网络设备可以包括集中单元(centralized unit，CU)节点，或包括分布单元(distributed unit，DU)节点，或包括CU节点和DU节点的RAN设备，或包括控制面CU节点和用户面CU节点，以及DU节点的RAN设备，或者，网络设备还可以为云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器、中继站、车载设备以及可穿戴设备等。此外，基站可以是宏基站、微基站、中继节点、施主节点，或其组合。基站还可以指用于设置于前述设备或装置内的通信模块、调制解调器或芯片。基站还可以是移动交换中心以及D2D、V2X、M2M通信中承担基站功能的设备、6G网络中的网络侧设备、未来的通信系统中承担基站功能的设备等。基站可以支持相同或不同接入技术的网络，不作限定。
本申请实施例中，用于实现网络设备的功能的装置可以是网络设备，也可以是能够支持网络设备实现该功能的装置，例如芯片系统或芯片，该装置可以被安装在网络设备中。本申请实施例中，芯片系统可以由芯片构成，也可以包括芯片和其他分立器件。
应理解，本申请提供的级联码(concatenated code)的编码或译码的方案也即信道编、译码方案，可以用于专用网设备或通用设备，可以应用于如上所述的各种网络设备(例如，基站设备)，也可以应用于如上所述的各种终端设备。具体地，该信道编码或信道译码的方案，主要通过这些设备中的信道编码单元或信道译码单元实现。
本申请实施例中，发送端或接收端的功能，可以通过应用特有集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)等实现，也可以通过软件(例如，存储器中的程序代码)实现，不作限定。
此外，本申请的技术方案可以应用于多种通信场景，如图1，图1为适用于本申请的技术方案的通信系统的系统架构的示意图。
如图1的示例，本申请提供的级联码的编码和译码的方法，可以适用于网络设备和终端之间的通信，也即上行或下行的通信。在此通信场景下，本文的发送端可以为上行通信中的终端或下行通信中的网络设备，接收端可以为上行通信中的网络设备或下行通信中的终端。此外，可选的，本申请的技术方案也可以应用于侧行链路通信中，在此通信场景下，发送端为侧行链路通信中的发送终端，接收端为侧行链路通信中的接收终端。此外，还可以应用于其它通信场景中，不再赘述。
参考图2，图2为通信系统的流程示意图。如图2，信道编码位于信源编码和调制之间，负责将信源产生的比特进行信道编码，再经过调制后，发送调制符号经过有噪声信道至接收端解调，然后进行信道译码，信道译码位于解调和信源译码之间，负责恢复出信源比特流。
本申请的技术方案中涉及编码领域的极化码(即polar码)、低密度奇偶校验(low density parity  check codes，LDPC)码和级联码。
下面对本申请中涉及到的术语或相关概念作简单介绍。
1、极化码：
信道编解码是无线通信领域的核心技术之一，其性能的改进将直接提升网络覆盖及用户传输速率。目前，极化码(polar codes)是可理论证明达到香农极限，并且具有可实用的线性复杂度编译码能力的信道编码技术。Polar码是一种线性块码，其编码矩阵(也称为生成矩阵)为FN，编码过程可以由下式表示：
其中，是一个二进制的行矢量(也即，信息比特序列)，长度为N，且N＝2n，n为正整数。FN是一个N×N的矩阵，定义为log2N个矩阵F2的克罗内克(Kronecker)乘积，以上各式中涉及的加法、乘法操作均为二进制伽罗华域上的加法、乘法操作。
2、低密度奇偶校验(low density parity check codes，LDPC)码：一类具有稀疏校验矩阵的线性分组码，即校验矩阵中非零元素的密度比较低，也就是要求校验矩阵中零元素远远多于非零元素。一个[N，K]的线性分组码，可理解为将长度为K的信息序列，通过编码得到码长为N的编码比特。
3、基图：基图可以表示成m×n的矩阵，包括零元素和非零元素，其中零元素可以用0、-1或null等表示，非零元素可以用1表示，可以用于指示基矩阵中非零元素的位置，也就是非零元素在矩阵中的行、列位置。在有些实现方法中也可以简化的表示成指示非零元素的行、列位置的表格。
4、基矩阵：可用于构造LDPC码的校验矩阵H。基矩阵Hb的大小可以为m×n，与基图相同，相应的校验矩阵H的大小为(m·p)×(n·p)，其中，将p称作校验矩阵的扩展因子(lifting size)，或者称为基矩阵需要扩展的倍数，m、n、p均为正整数。
基矩阵的表达式可以如下所示，其中，与基图中非零元素对应的位置的元素取值大于或者等于0，与零元素对应的位置的元素取值可以为-1或者null：
5、校验矩阵：LDPC码的校验矩阵的表达式可以如下所示：
该校验矩阵H中的每一个元素I(ai,j)(0≤i≤m-1，0≤j≤n-1)可以是零矩阵或者是循环移位矩阵。其中，若ai,j大于或者等于0，循环移位矩阵(例如，I(ai,j))可以是对维度为p×p的单位矩阵循环移位ai,j位得到的。因此，也将ai,j称作循环移位矩阵的移位因子。ai,j的取值范围可以是-1≤ai,j＜p。
换句话说，基矩阵中的每个非零元素ai,j(0≤i≤m-1，0≤j≤n-1)可用于指示其所构造的校验矩阵中对应的单位矩阵需要进行循环移位的位数。例如，a0,0可用于指示校验矩阵的左上角维度为p×p的单位矩阵I(a0,0)需要循环移位的位数为a0,0。若将I(a0,0)看做一个整体，I(a0,0)在校验矩阵中的位置与a0,0在基矩阵的位置是相同的，即，第0行第0列。而基图或基矩阵中零元素则是用p×p的零矩阵替换。
6、哈达马积(Hadamard product)：哈达马积是矩阵的一类运算。
设且A＝{aij}，B＝{bij}，1≤i≤m，1≤j≤n，则称如下所示的矩阵C为矩阵A和矩阵B的哈达马积，记作C＝A⊙B。
7、汉明距离：在一个码组集合中，任意两个码字之间对应位置上码字取值不同的位置数目定义为这两个码字之间的汉明距离。例如，码字x和码字y之间的汉明距离为d(x,y)，i＝0,1,…,n-1，其中，x，y都是n位的编码，n为正整数，表示异或。例如，(00)与(01)的汉明距离为1，(110)和(101)的汉明距离为2。
在一个码组集合中，任意两个编码之间汉明距离的最小值称为这个码组的最小汉明距离，又称最小汉明重量。最小汉明距离越大，表明码的抗干扰能力越强。
8、软值(soft value)：也即对数似然比(log-likelihood ratio，LLR)。其中，一个码字比特c的LLR定义为log(c＝0的概率/c＝1的概率)。c的LLR大于0，c在硬判决时被判为0，c的LLR小于0，c在硬判决时被判决为1。这是LLR的符号的作用。同时，LLR的幅度反映了硬判决的可靠程度，LLR的绝对值越大，说明该硬判决就越肯定。
9、级联码：
在将信道编码技术应用于实际中时，常常需要考虑很多实际的因素，例如，效率、性能和时延等。由信道编码理论可知，随着码长N的增加，译码错误概率以指数方式趋近于零。因此，为提高纠错码的有效性，就必须使用长码。但码长增加，码率会相应下降，译码器的复杂性与计算量也相应增加。级联码正是为了解决这个矛盾而提出，它将编码过程分为几级完成，可以满足信道纠错对编码长度的要求，获得和长码接近甚至相同的纠错能力和高编码增益。而且，随之增加的编译码复杂度并不是很大。换句话说，如果一个系统包括多次(至少两次)编码，这多次编码就认为是级联编码。级联编码包括外码编码和内码编码。其中，外码编码的输入是待编码的信息比特序列，外码的输出作为内码的输入。内码编码的输出即是完成级联编码后的码字。应理解，外码和内码是一个相对的概念。以一个系统包括三次编码为例，第一次编码相对于第二次编码是外码编码，第二次编码相对于第一次编码是内码编码。第一次编码完成之后，第二次编码相对于第三次编码是外码编码，第三次编码相对于第二次编码是内码编码。再以一个系统包括两次编码为例，先进行的是外码编码，后进行的是内码编码。外码编码的输出作为内码编码的输入。
图3为级联编码的示意图。如图3，一个级联编码策略通常会包含内码和外码，内码的作用可以认为是通过给物理信道“降噪”来获得一个更好的超级信道，使得外码所看到的信道状况好于原始的物理信道。已有研究表明，级联码可以在所有低于信道容量的码率下降低块误码率(block error rate，BLER)。
本文中，将级联码的外码和内码分别用Cout(N_o,K_o,D_o)和Cin(N_i,K_i,D_i)来表示，并将级联码用C(N,K,D)来标识，N＝N_o*N_i,K＝K_o*K_i，D≥D_o*D_i。其中，括号中的参数N表示码长，K表示消息比特数目，D表示该码的最小汉明距离。在本申请中，不要求内外码字都处于相同的代数域，内码可以为二元域，外码可以为其它的非二元域。此外，如果内码和外码都是线性码，则级联之后的码字也是线性码。
级联码的译码通常采用迭代软输入软输出(soft input soft output，SISO)译码。迭代SISO译码有时被称为涡轮(turbo decoding)，这种译码方式的重点之一在于将第一个译码器的软输出作为第二个译码器的软输入，然后将第二个译码器的软输出作为第一个译码器的软输入，如此循环往复的迭代最终产生更为可靠的判决结果。
将不同的码字进行级联的方法有多种，按照级联的方式分类大致可以分为串行级联码和并行级联码。目前，级联码有如下方案：
(1)polar码+LDPC码串行级联策略。
(2)通过并行级联码(parallel concatenated codes，PCC)架构将polar和LDPC码级联的并行级联策略。
(3)里德-所罗门(reed-solomon，RS)码+交织器+polar码的级联策略。
(4)polar码+低密度生成矩阵(low density generation matrix，LDGM)的级联策略。
其中，通过级联polar和无速率LDPC码，可以时polar码获得无速率LDPC码长扩展灵活的优势，提高了polar码的扩展灵活性。无速率结构之所以可以使polar码的码长扩展更灵活，是因为该结构具有嵌套特性，无速率的嵌套结构让短码总是长码的一个子码，随着码长的增加，前面已经编码结束的部分无需改变，只需增加额外长度的冗余比特即可扩展码长。然而现有polar码和无速率LDPC码的级联码设计主要基于密度极化理论，高斯近似和独立假设使得这种优化方式存在误差，因此基于该方式获得的级联码方案性能有待提升。
有鉴于此，本申请实施例提供一种polar码与改进的LDPC码的级联码的编码和译码方案，进一步提升级联码的译码性能和构造灵活性，并且满足速率兼容的要求。
其中，本申请中提供的“改进的LDPC码”与传统的LDPC码不同。由于该改进的LDPC码相较于传统的LDPC码可以进一步降低误比特率(bit error rate，BER)，以及满足速率兼容的要求，因此，本文中也将该改进的LDPC码称之为嵌套降错LDPC(nested error reducing-LDPC，N-ER-LDPC)码。
图4为本申请提供的一种级联码的编码和译码的方法的示意图。如图4，在发送端，待编码的消息比特序列u首先通过极化码编码器获得码字c，码字c经过交织器P交织之后，得到N-ER-LDPC码编码器的输入序列P(c)。P(c)经过N-ER-LDPC码编码，得到最终的级联码字C_N-ER-LDPC(P(c))，并发送到信道进行传输。
在接收端，接收端采用软信息迭代译码。
接收端接收信道接收矢量y，然后采用本申请提供的级联码的软信息迭代译码方案，对信道接收矢量y进行译码。基于预设定的最大迭代次数，通过软信息迭代译码，获得软(soft)连续取消列表(successive cancellation list，SCL)译码器输出的软信息序列，经过硬判决，获得最终的译码估计序列。
具体地，N-ER-LDPC译码器首先对从信道接收到的序列(以下称为信道接收序列)进行译码，得到软信息，该软信息作为软SCL译码器的输入，经过软SCL译码器的译码产生译码序列的软值。然后将该软值减去上述软信息得到外信息，并将外信息和信道接收序列相加之后输入到N-ER-LDPC译码器中进行译码，产生新的软信息。进而将该新的软信息减去N-ER-LDPC译码器的输入(N-ER-LDPC译码器的输入是外信息和信道接收序列相加得到的)后得到新的外信息，再将该新的外信息输入至软SCL译码器进行译码，产生新的译码序列的软值。如此往复迭代，达到最大迭代次数之后，对软SCL译码器产生的译码序列的软值进行硬判决，获得最终的估计序列。
需要说明的是，待编码的消息比特序列u通过极化码编码器获得码字c之后，码字c可以不经过交织，而是直接经过N-ER-LDPC码编码，本申请实施例对此不做限定。若码字c不经过交织，则译码流程不包括解交织。
下面对发送端的信道编码方案和接收端的信道译码方案进行详细说明。
参见图5，图5为本申请提供的一种级联码的编码和译码的方法500的示意性流程图。
S510，发送端对待编码的消息比特序列进行级联编码，获得级联码码字。
其中，关于S510的详细说明可以参见图6和图7的进一步说明。
S520，发送端发送级联码码码字。
接收端接收信道接收矢量(或称为信道接收序列)。
S530，接收端采用软信息迭代译码方案，对信道接收矢量进行译码，获得译码估计序列。
本申请中采用的软信息迭代译码方案，是一种将软SCL译码算法和置信传播(belief propagation，BP)译码算法相结合的软信息迭代译码算法，译码复杂度较低。
其中，关于S530的详细说明可以参见图10和图11中的详细说明。
参见图6，图6为本申请提供的一种级联码的编码流程的示意图。如图6，发送端的级联编码的主要流程可以如下：
(1)给定级联码的待编码消息比特序列u＝(u_1,u_2,...,u_K)，K为正整数；
(2)对待编码消息比特序列u添加r个CRC校验比特，得到长度为K+r的序列，r为正整数；
(3)对长度为K+r的序列进行polar码编码，得到码长为N_o，消息比特数为K_o的内码，也即得到极化码码字C_o，其中，K_o＝K+r，N_o为正整数；
(4)对C_o进行交织，得到交织后的码字P(C_o)，其中，交织器的长度为N_o；
(5)对码字P(C_o)进行N-ER-LDPC编码，得到消息比特数为K_i，长度为N_i的级联码字， K_i＝N_o，N_i为正整数。
需要说明的是，上述对极化码码字C_o进行交织为可选的步骤，即极化码码字C_o可以在不经过交织的情况下，直接进行N-ER-LDPC编码。
参见图7，图7为本申请提供的发送端的编码流程的示意图。
S710，发送端对待编码的消息比特序列进行极化码编码，得到长度为N_o的第一编码码字。
其中，待编码的消息比特序列也可以称为信息比特序列。
应理解，经过S710，发送端完成了级联码的外码编码，第一编码码字可以称为polar码字或外码码字。
可选的，方法700还包括S720。
S720，发送端对第一编码码字进行交织，获得第二编码码字。
其中，S720中的交织包括外交织和内交织。外交织可以通过外交织器实现，内交织可以通过内交织器实现。
具体地，经过外交织，将第一编码码字的R个冻结位对应的标号映射至改进的LDPC码的生成矩阵的R个行，该R个行的行重低于或等于生成矩阵的除了该R个行之外的其它行的行重，以及，将第一编码码字的I个消息位对应的标号映射至该改进的LDPC码的生成矩阵的I个行，该I个行的行重高于或等于生成矩阵的除了该I个行之外的其它行的行重。其中，R＝N_o-K_o，I＝K_o。改进的LDPC码的生成矩阵中每列包含的非零元素的数目称为列重。
也就是说，如果生成矩阵的行索引构成一个集合，该集合中的行索引按照行重从小到大的顺序排序，则外交织将第一编码码字的R个冻结位对应的标号映射到该集合中的前R个行索引对应的R个行，将第一编码码字的消息位对应得的标号映射至该集合中的后I个行索引对应的I个行。
例如，将第一编码码字的冻结位对应的标号集合记作集合F＝{f1,f2,…,fR}，集合F经过了自然顺序排序，其中，f1具有最小值，fR具有最大值；将第一编码码字的消息位对应的标号集合记作集合J＝{j1,j2,…,jI}；将改进的LDPC码的生成矩阵G的行标(或者说行索引)集合记作集合S＝{j1,j2,…,jN_o}，集合S中的行标号按照行重从低到高进行排序。进而，经过外交织，将集合F映射到集合S的前R个元素，即F->S[1：R]，以及将集合J映射到集合S的后I个元素，即J->S[(N_o-I+1)：N_o]。
内交织包括：对上述R个冻结位对应的标号与上述R个行的映射关系的交织，对上述I个消息位对应的标号与上述I个行的映射关系的交织。
可选地，内交织可以为如下几种中的任意一种：
(a)随机交织；
(b)二次方交织：j->(a*j*(j-1)/2 mod L)+1，其中，L是内交织器长度，a为任意奇数，j＝1,2,3,…,L，例如，a＝3，L＝8，序列[1 2 3 4 5 6 7 8]经过二次方交织后得到序列[1 4 2 3 7 6 8 5]；
(c)循环交织：j->(b*j+r)mod L+1，b是一个和L互质的整数，其中，L为内交织器长度，r为任意整数，例如，r＝6，b＝7，序列[1 2 3 4 5 6 7 8]经过循环交织后得到序列[6 5 4 3 2 1 8 7]。
S730，发送端对第二编码码字进行改进的LDPC码编码，获得长度为N_i的级联码码字。
可以理解，若方法700执行了的S720，则第二编码码字是对第一编码码字进行交织得到的。若方法700未执行S720，则第二编码码字与第一编码码字相同。
其中，改进的LDPC码是根据改进的LDPC码的基矩阵和提升矩阵获得的。
改进的LDPC码的基矩阵具有至少如下特征之一：
(1)前t列为全零列，t为正整数，且2≤t＜T，T为N_o与p的比值，即T＝N_o/p，p为基矩阵需要扩展的倍数，p也可以称为扩展因子。N_o和p都可以被2整除。示例性的，当t＝2时，改进的LDPC码的基矩阵对应的基图如图8所示。可以理解，全零列有利于保证级联编码性能，全零列对应的位置上的BER性能不会发生改变，BER曲线的斜率更平缓，对应的信噪比(signal noise ratio，SNR)的动态范围更广。图9示出了本申请实施例提供的改进的LDPC码作为内码的BER性能示意图。如图9所示，由于改进的LDPC码具有全零列，所以在BER等于0.1时对应的SNR范围更广。
(2)包括至少s’列列重为1的列，s’为正整数。至少s’列包括基矩阵的后s”列，s”为N_i减去N_o的差值与p的比值，即s”＝(N_i-N_o)/p。
改进的LDPC码的校验矩阵具有至少如下特征之一：
(1)改进的LDPC码的校验矩阵包括至少s列列重为1的列，s为正整数。至少s列包括校验矩阵的后(N_i-N_o)列。可以理解，列重为1的列对应改进的LDPC码的校验矩阵中的单位阵。该特征是可以保证改进的LDPC码具有嵌套性能，可以使本申请实施例所提供的级联编码满足速率兼容的要求。
(2)改进的LDPC码的校验矩阵的列数减去行数的差值可以被2整除。可以理解，改进的LDPC码的外码是具有母码长的polar码，polar码的长度为2的幂次方，即N_o可以被2整除。又因为，改进的LDPC码的校验矩阵的列数减去行数的差值为N_o，所以改进的LDPC码的校验矩阵的列数减去行数的差值可以被2整除。
(3)改进的LDPC码的校验矩阵的列重分布满足表1。
表1
改进的LDPC码的基矩阵可以通过特殊的提升方法进行码长的扩展，进而得到改进的LDPC码的校验矩阵。下面介绍提升矩阵(lifting matrix)的设计，以及根据提升矩阵和改进的LDPC码的基矩阵获得改进的LDPC码的校验矩阵的步骤。
假设LDPC码的基矩阵是一个m行n列的矩阵，并且需要将基矩阵扩展p倍，即得到一个维度等于mp*np的校验矩阵(m<n)，m和n均为正整数。获得改进的LDPC码的校验矩阵的步骤如下：
(1)构造一个大小为m的行矢量和一个大小为v的列矢量，且行矢量中任意两个元素不同，列矢量中任意两个元素不同，m和v均小于或等于p，v等于n，或者，v＝(n-t)，t等于LDPC码的基矩阵中全零列的数目。
示例性的，所构造的行矢量Crows可以表示为：Crows＝(r1,r2,…,rm)，Crows中任意两个元素不相等，即ri≠ri’，ri表示行矢量Crows中的第i个元素，ri’表示行矢量Crows中的第i’个元素，1≤i≤m，1≤i’≤m，i≠i’。
所构造的列矢量Ccols可以表示为：Ccols＝(c1,c2,…,cv)，列矢量Ccols中任意两个元素不相等，即cj’≠cj，cj’为列矢量Ccols中的第j’个元素，cj为列矢量Ccols中的第j个元素，1≤j≤v，1≤j’≤v，j’≠j。
(2)根据行矢量和列矢量，得到提升矩阵。
示例性的，根据行矢量和列矢量，所构造的提升矩阵M可以表示为：M(i,j)＝ri*cj mod p，mod为取余运算，M(i,j)为提升矩阵中的第i行第j列的元素，ri*cj表示ri与cj相乘。
(3)根据提升矩阵和基矩阵，得到更新后的基矩阵。
若v＝n，则根据提升矩阵和基矩阵，得到的更新后的基矩阵Hm可以表示为：Hm＝Hopt⊙M，即更新后的基矩阵中的元素Hm(i,j)等于基矩阵中的元素Hopt(i,j)与提升矩阵中的元素M(i,j)的乘积。Hm(i, j)为更新后的提升矩阵中的第i行第j列的元素，Hopt表示基矩阵，Hopt(i,j)为基矩阵中的第i行第j列的元素。Hm可以称为Hopt和M的哈达马积或基本积。
若v＝n-t，则根据提升矩阵和基矩阵得到更新后的基矩阵，包括：提取基矩阵Hopt中的非零列得到矩阵Hopt2；根据矩阵Hopt2和提升矩阵M得到更新后的基矩阵Hm，更新后的基矩阵Hm可以表示为：Hm＝Hopt2⊙M，即更新后的基矩阵中的元素Hm(i,j)等于矩阵Hopt2中的元素Hopt2(i,j)与提升矩阵中的元素M(i,j)的乘积。Hopt2(i,j)为矩阵Hopt2中的第i行第j列的元素。Hm可以称为Hopt2和M的哈达马积或基本积。
(4)根据更新后的基矩阵，得到改进的LDPC码的校验矩阵。
若v＝n，则改进的LDPC码的校验矩阵是对更新后的基矩阵进行p倍扩展得到的。
示例性的，更新后基矩阵的表达式可以如下所示：
对更新后的基矩阵进行p倍扩展得到的改进的LDPC码的校验矩阵的表达式可以如下所示：
该校验矩阵H中的每一个元素I(ai,j)(1≤i≤m，1≤j≤v)可以是零矩阵或者是循环移位矩阵。其中，若ai,j大于或者等于0，循环移位矩阵(例如，I(ai,j))可以是对维度为p×p的单位矩阵循环移位ai,j位得到的。因此，也将ai,j称作循环移位矩阵的移位因子。ai,j的取值范围可以是-1≤ai,j＜p。
若v＝n-t，则根据更新后的基矩阵得到改进的LDPC码的校验矩阵，包括：对更新后的基矩阵进行P倍扩展得到中间校验矩阵；对中间校验矩阵第一列之前补充t*p列全零列得到改进的LDPC码的校验矩阵。
根据更新后的基矩阵，得到的改进的LDPC码的校验矩阵的表达式可以如下所示：
该校验矩阵H中的元素I(0)表示大小为p行t*p列的全零矩阵。
根据上文的描述可知，在本申请提供的方案中，对于一个维度为m*n的改进的LDPC码的基矩阵，其对应的提升矩阵具有至少如下外部特征之一：
(1)可以通过如下两个矢量相乘得到提升矩阵：
Crows＝(r1,…,rm),其中，ri≠ri'；
Ccols＝(c1,…,cv),其中，cj≠cj'；
(2)上述两个矢量的维度分别为m和v，并且必须满足矢量中任意两个元素不重合。例如，选择两个维度分别为1*m和1*v的随机集合(difference set)；
(3)对于任何p>max(m,v)，构造提升矩阵M(i,j)＝(ri*cj)mod p。
参见图9，图示出了本申请提供的提升矩阵的技术效果的示意图。在图9中，仿真参数为：N_i＝1024，N_o＝768，和积算法迭代次数为50次(sum-product-50)。其中，所提的扩展方案(proposed extension)表示根据本申请提供的提升矩阵得到的N-ER-LDPC码的BER性能，近似环外信息度(approximated cycle extrinsic message degres，ACE)扩展方案(ACE extension)表示根据ACE算法设计的提升矩阵得到的N-ER-LDPC码的BER性能。可以看出，在BER小于0.1的区间内，本申请方案的BER大于ACE 方案的BER，这意味着更大的SNR动态范围。
获得改进的LDPC码的校验矩阵之后，则可以根据改进的LDPC码的校验矩阵对第二编码码字进行编码，从而获得长度为N_i的级联码码字。
需要说明的是，若发送端预先保存了根据上述方法确定的改进的LDPC码的校验矩阵，则发送端可以直接根据改进的LDPC码的校验矩阵对第二编码码字进行编码。换句话说，若发送端预先保存了根据上述方法确定的改进的LDPC码的校验矩阵，则发送端对第二编码进行编码之前，无需再按照上述方法确定改进的LDPC码的校验矩阵。
S740，发送端输出级联码码字。
参见图10，图10为本申请提供的接收端的译码流程的示意图。
S1010，接收端获取长度为N_i的信道接收矢量。
其中，N_i为级联码的内码的长度，级联码的内码为改进的LDPC码，级联码的外码为极化码(具体为上述第一编码码字)，N_i为正整数。
接收端对信道接收矢量进行译码的步骤可以包括S1020至S1050。
S1020，接收端采用改进的LDPC码的SISO译码算法，对信道接收矢量进行译码，获得长度为N_i的第一软信息序列。
应理解，本申请中的“软信息”或“软值”均指LLR。示例性地，第一软信息序列的长度为N_i，即是指第一软信息序列中包含N_i个LLR，该N_i个LLR是采用改进的LDPC码的SISO译码器对信道接收矢量y进行译码获得的。
其中，SISO译码器的迭代次数记作inner_iter。
S1030，接收端对第一软信息序列进行解交织，获得解交织后的第一软信息序列，并提取该解交织后的第一软信息序列中的前N_o个位置上的软信息，获得第二软信息序列，N_o为级联码的外码的长度，N_o为正整数。
应理解，若上述第二编码码字是对第一编码码字进行交织后得到的，则在S1030中，接收端完成对第一软信息序列的解交织，并从解交织后的第一软信息序列中读取前N_o个位置上的软信息，获得polar外码的软信息序列，即获得第二软信息序列。
若上述第二编码码字与第一编码码字相同，则在S1030中，接收端直接从第一软信息序列中读取前N_o个位置上的软信息，获得polar外码的软信息序列，即获得第二软信息序列。
S1040，接收端基于第二软信息序列、信道接收矢量和级联码的预设定的最大迭代次数，通过极化码的软SCL译码算法和改进的LDPC码的SISO译码算法，进行软信息迭代译码，获得第三软信息序列。
还可以理解，改进的LDPC码的SISO译码算法与上文方法700所述的改进的LDPC码的校验矩阵相关。或者说，在S1040中，接收端根据改进的LDPC码的校验矩阵进行改进的LDPC码的SISO译码算法。
需要说明的是，接收端确定改进的LDPC码的校验矩阵的方式与发送端确定改进的LDPC码的校验矩阵的方式，具体参考上文方法700中的描述。
还需要说明的是，若接收端预先保存了根据方法700所述的方式确定的改进的LDPC码的校验矩阵，则接收端可以直接根据改进的LDPC码的校验矩阵进行改进的LDPC码的SISO译码算法。换句话说，若接收端预先保存了根据方法700所述的方式确定的改进的LDPC码的校验矩阵，则接收端进行改进的LDPC码的SISO译码算法之前，无需再按照方法700所述的方式确定改进的LDPC码的校验矩阵。
在S1040中，接收端采用本申请的软信息迭代译码，通过迭代译码，在达到预设定的最大迭代次数max_Iter之后，软SCL译码器输出第三软信息序列，即为译码序列的软值序列。
具体地，以任意相邻两次迭代过程为例，该软信息迭代译码的过程如下：
通过执行(j-1)次的软信息迭代译码，获得软SCL译码算法输出的第(j-1)个软信息序列；
将第(j-1)个软信息序列减去第(j-1)次的软信息迭代译码过程中软SCL译码算法输入的软信息序列，获得SISO译码算法的第j个外信息；
将第j个外信息和信道接收矢量之和作为第j次的软信息迭代译码过程中SISO译码算法的输入， 获得SISO译码算法在第j次的软信息迭代过程中的输出；
将SISO译码算法在第j次的软信息迭代过程中的输出，减去第j个外信息和信道接收矢量之和，获得软SCL译码算法的第j个软信息序列，
其中，软SCL译码算法的第j个软信息序列，为第j次的软信息迭代过程中软SCL译码算法输出的软信息序列，
SISO译码算法的第j个外信息，为第j次的软信息迭代过程中输入给SISO译码算法的外信息，
第二软信息序列为第1次的软信息迭代过程中输入给软SCL译码算法的软信息序列，第三软信息序列为最后一次的软信息迭代过程中所述软SCL译码算法输出的软信息序列，
1<j≤max_Iter，j为正整数。
S1050，接收端对第三软信息序列进行硬判决，获得译码估计序列。
S1060，接收端输出译码估计序列。
下面结合图11对接收端执行软信息迭代译码的过程进行详细介绍。
图11为本申请提供的接收端的软信息迭代译码方案的示意图。
如图11，接收端执行软信息迭代译码的过程如下：
(1)信道接收矢量y＝(y_1,y_2,…,y_Ni)首先被送到N-ER-LDPC的SISO译码器中进行译码，SISO译码器的迭代次数为inner-iter，输出的译码软消息长度为N_i，记为序列d＝(d_1,d_2,…,d_Ni)。
(2)找到和编码侧交织器P相对应的解交织器，即为P_inv。
(3)对译码得到的长度为N_i的序列d的前N_o个值进行提取，得到polar外码的软信息序列L_polar＝P_inv(LN-ER-LDPC_No＝(L_1,L_2,…,L_No))。需要说明的是，长度为N_i的序列d的前N_o个值包括与N-ER-LDPC码的校验矩阵中的全零列对应的值，全零列对应的极化码码字比特在大迭代译码过程中的软信息不会更新。
(4)执行如下循环：
for i＝1:max_Iter
(a)[L_out,L_code]＝soft_SCL(L_polar,List)：
采用soft_SCL译码器对polar码进行译码，得到两个输出L_out和L_code。其中，L_out是polar码U侧的消息软值，L_code是polar码C侧码字的软值。其中，polar码的UE侧表示极化码的消息侧，polar码U侧的消息软值指的是极化码编码前的消息序列对应的软值，极化码编码前的消息序列包括消息比特和冻结比特。Polar码的C侧表示极化码的码字侧，polar码C侧码字的软值指的是极化码编码后得到的码字对应的软值。
soft_SCL译码器有两个输入，分别为L_polar和List，其中，L_polar为步骤(3)所述的polar外码的软信息序列，L_polar是极化码soft_SCL译码器的软输入LLR值，List是译码列表的大小，取值为2的幂次方，如1,2,4,8,16,32等。
(b)计算送给N-ER-LDPC译码器的外信息(软值)，该外信息的长度等于信道接收矢量的长度，也是N_i个比特，其中N_i-N_o个非系统位上的取值为0，另外N_o个位置上的取值等于(P(L_code)-L_polar)，即N_o个非零元素等于soft_SCL译码器的第二个输出(交织后的)减去soft_SCL译码器的第一个输入后的结果。该外信息的矢量记作E＝[P(L_code)-L_polar；0000…0(共有N_i-N_o个零)]。
(c)对N-ER-LDPC再次进行SISO译码。此次，SISO译码器的输入除了长度为N_i的信道接收矢量y＝(y_1,y_2,…,y_Ni)之外，还需要再加上步骤(b)得到的外信息的矢量E，即SISO译码器的输入L_d表示为：L_d＝soft LDPC decode(y+E,inner_iter)。
(d)提取N-ER-LDPC的前N_o个位置上的软值，然后再减去N-ER-LDPC译码器的输入来产生下一轮polar的soft SCL译码的输入。
综上所述，该软信息迭代译码流程中涉及到两个译码器，分别为polar码(即，级联码的外码)的软SCL译码器，和N-ER-LDPC码(即，级联码的内码)译码器。
需要说明的是，上述译码流程中的解交织为可选的步骤，若编码流程不包括交织步骤，则译码流程不包括解交织步骤。
在本申请实施例中，由于改进的LDPC码的基矩阵的前t列为全零列，因此本申请实施例提供的方法在大迭代译码过程中，polar外码的软值和改进的LDPC码的软值在全零列处不交换软值，而软值 的部分更新可以提升大迭代译码性能。
此外，由于改进的LDPC码的校验矩阵的后(N_i-N_o)列的列重为1，因此本申请实施例提供的方法编码复杂度低，可以实现速率兼容。
为了验证改进的LDPC码的有益效果，测试并对比了仿真信道为加性高斯白噪声(additive white gaussian noise，AWG)信道、调制方式为二相相移键控(binary phase shift key，BPSK)下，本申请实施例提供的级联码的编码和译码方法与NR LDPC码的性能。本申请实施例提供的方法中，外码编码方案为级联了2比特CRC的polar码，polar码的构造方式为密度进化。译码器中polar外码译码器为list长度为4的soft SCL译码，内码译码器采用迭代10次的BP译码，改进的LDPC码的校验矩阵的前2p列打孔，级联码译码的大迭代次数为10次。作为对比，测试了NR LDPC码在BP译码下迭代50次和100次的性能。
本申请实施例提供的级联码的仿真参数如表2所示。其中，rLDPC是改进的LDPC的校验矩阵的行数，nLDPC是改进的LDPC的校验矩阵的列数，p是提升大小，PN为改进的LDPC码的打孔位置，RN-ER-LDPC为内码的码率，KLDPC为内码的消息比特数，Rpolar为Polar外码的码率(即Kpolar/KLDPC)，CRC为外码CRC的长度，Kpolar是Polar外码的负载消息比特的长度(不包含CRC)，NCC是整体级联码的码长，RCC是整体级联码的码率。
表2
NR LDPC码的仿真参数如表3所示。其中，KNR-LDPC是NR LDPC码的消息比特数，RNR-LDPC为NR LDPC码的码率。
表3
本申请实施例提供的级联码的性能与NR LDPC码的性能对比如图12所示。其中，横轴为消息比特数，纵轴是达到误码率等于0.01时所需要的SNR，达到误码率等于0.01时所需的SNR越小，说明码字的纠错性能越好。从图12中可以看出，本申请所提方案能满足速率兼容的要求，并且在不同码长和码率下，都比现有的NR LDPC码具有更优异的纠错性能。
以上介绍了本申请提供的级联码编码和译码的方法，下面介绍本申请提供的通信装置。
参见图13，图13为本申请提供的通信装置的示意性框图。如图13，通信装置1300包括处理单元1310和收发单元1320。
可选地，通信装置1300可以对应本申请方法实施例中的发送端。在此情况下，通信装置1300的各单元用于实现如下功能：
处理单元1310，用于：对待编码的消息比特序列进行极化编码，得到长度为N_o的第一编码码字，该N_o为正整数；对第二编码码字进行改进的LDPC码编码，得到长度为N_i的级联码码字，该第二编码码字是根据该第一编码码字确定的，该N_i为正整数；其中，该改进的LDPC码的基矩阵的前t列为全零列，该t为正整数，且2≤t＜T，该T等于该N_o与p的比值，该p为该基矩阵需要扩展的倍数，该p为正整数；该改进的LDPC码的校验矩阵包括至少s列列重为1的列，该至少s列包括后(N_i-N_o)列。
收发单元1320，用于输出该级联码码字。
可选地，通信装置1300可以对应本申请方法实施例中的接收端。在此情况下，通信装置1300的各单元用于实现如下功能：
收发单元1320，用于获取长度为N_i的信道接收矢量，N_i为级联码的内码的长度，该级联码的内码为改进的LDPC码，该级联码的外码为极化码，该N_i为正整数。
处理单元1310，用于：采用改进的LDPC码的SISO译码算法，对该信道接收矢量进行译码，获得长度为N_i的第一软信息序列，该SISO译码算法与该改进的LDPC码的校验矩阵相关；其中，该改进的LDPC码的基矩阵的前t列为全零列，该t为正整数，且2≤t＜T，该T等于该N_o与p的比值，该p为该基矩阵需要扩展的倍数，该p为正整数；该改进的LDPC码的校验矩阵包括至少s列列重为1的列，该至少s列包括后(N_i-N_o)列；基于该第二软信息序列、该信道接收矢量和该级联码的预设定的最大迭代次数，通过该极化码的软SCL译码算法和该改进的LDPC码的SISO译码算法，进行软信息迭代译码，获得第三软信息序列，该第二软信息序列是根据该第一软信息序列确定的；以及，对该第三软信息序列进行硬判决，获得估计序列。
收发单元1320，用于输出该估计序列。
在通信装置1300对应发送端的各实施例中，处理单元1310用于执行除了发送和接收的动作之外由发送端内部实现的处理和/或操作。收发单元1320用于执行发送端的接收(或者说输入)的动作，和/或，用于执行发送端的发送(或者说输出)的动作。
例如，在图5中，处理单元1310用于执行S510，收发单元1320用于执行S520。
又例如，在图7中，处理单元1310用于执行S710-S730，收发单元1320用于执行S740。
在通信装置1300对应接收端的各实施例中，处理单元1310用于执行除了发送和接收的动作之外由接收端内部实现的处理和/或操作。收发单元1320用于执行接收端的接收(或者说输入)的动作，和/或，用于执行接收端的发送(或者说输出)的动作。
例如，在图5中，处理单元1310用于执行S530。
又例如，在图10中，收发单元1320用于执行S1010，处理单元1320用于执行S1020-S1050，收发单元1320用于执行S1060。
参见图14，图14为本申请提供的通信装置的示意性结构图。如图14，通信装置1400包括：一个或多个处理器1410，一个或多个存储器1420以及一个或多个通信接口1430。处理器1410用于控制通信接口1430收发信号，存储器1420用于存储计算机程序，处理器1410用于从存储器1420中调用并运行该计算机程序，以使得通信装置1400执行本申请各方法实施例中由发送端或接收端执行的处理。
例如，处理器1410可以具有图13中所示的处理单元1310的功能，通信接口1430可以具有图13中所示的收发单元1320的功能。具体地，处理器1410可以用于执行由通信装置内部执行的处理或操作，通信接口1430用于执行通信装置的发送和/或接收的操作。
其中，图14中器件(例如，处理器、存储器或通信接口)后面的虚线框表示该器件可以为一个以上。
可选地，上述各装置实施例中的存储器与处理器可以是物理上相互独立的单元，或者，存储器也可以和处理器集成在一起，本文不作限定。
此外，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得本申请各方法实施例中由发送端执行的操作和/或处理被执行。
本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得本申请各方法实施例中由接收端执行的操作和/或处理被执行。
此外，本申请还提供一种计算机程序产品，计算机程序产品包括计算机程序代码或指令，当计算机程序代码或指令在计算机上运行时，使得本申请各方法实施例中由发送端执行的操作和/或处理被执行。
本申请还提供一种计算机程序产品，计算机程序产品包括计算机程序代码或指令，当计算机程序代码或指令在计算机上运行时，使得本申请各方法实施例中由接收端执行的操作和/或处理被执行。
此外，本申请还提供一种芯片，所述芯片包括处理器，用于存储计算机程序的存储器独立于芯片而设置，处理器用于执行存储器中存储的计算机程序，使得安装有所述芯片的装置执行任意一个方法实施例中由发送端执行的操作和/或处理。
进一步地，所述芯片还可以包括通信接口。所述通信接口可以是输入/输出接口，也可以为接口电路等。进一步地，所述芯片还可以包括所述存储器。
本申请还提供一种芯片，所述芯片包括处理器，用于存储计算机程序的存储器独立于芯片而设置，处理器用于执行存储器中存储的计算机程序，使得安装有所述芯片的装置执行任意一个方法实施例中由接收端执行的操作和/或处理。
进一步地，所述芯片还可以包括通信接口。所述通信接口可以是输入/输出接口，也可以为接口电路等。进一步地，所述芯片还可以包括所述存储器。
可选地，上述处理器可以为一个或多个，所述存储器可以为一个或多个，所述存储器可以为一个或多个。
此外，本申请还提供一种通信装置(例如，可以为芯片或芯片系统)，包括处理器和通信接口，根据前述任意一个方法实施例中由发送端执行的操作和/或处理，所述通信接口用于接收(或称为输入)待编码的消息比特，所述处理器对待编码的消息比特进行编码。可选地，通信接口还用于发送(或称为输出)处理器处理后的数据和/或信息，例如，发送级联码码字。
本申请还提供一种通信装置(例如，可以为芯片或芯片系统)，包括处理器和通信接口，根据前述任意一个方法实施例中由接收端执行的操作和/或处理，所述通信接口用于接收(或称为输入)信道接收矢量，所述处理器用于对信道接收矢量译码。可选地，所述通信接口还用于发送(或称为输出)译码估计序列。
此外，本申请还提供一种通信装置，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合，所述至少一个处理器用于执行所述至少一个存储器中存储的计算机程序或指令，使得所述通信装置执行任意一个方法实施例中由发送端执行的操作和/或处理。
本申请还提供一种通信装置，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合，所述至少一个处理器用于执行所述至少一个存储器中存储的计算机程序或指令，使得所述通信装置执行任意一个方法实施例中由接收端执行的操作和/或处理。
此外，本申请还提供一种通信系统，包括本申请方法实施例中的发送端和接收端。
本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory,ROM)、可编程只读存储器(programmable ROM,PROM)、可擦除可编程只读存储器(erasable PROM,EPROM)、电可擦除可编程只读存储器(electrically EPROM,EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory,RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM,DRAM)、同步动态随机存取存储器(synchronous DRAM,SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM,DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM,ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM,SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM,DRRAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
上述实施例所提供的方法，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品可以包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line,DSL))或无线(例如，红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等编号对功能和作用基本相同的相同项或相似项进行区分。例如，第一信息和第二信息仅仅是为了区分不同的信息，并不对其发送/接收的先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等编号并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在本申请实施例中，“消息位”和“信息位”有时候会替换使用，例如，polar外码的消息位也可以表述为polar外码的信息位。此外，N_o和No也可能替换使用，N_i和Ni也可能替换使用。文中还有一些类似的替换表达，不再一一赘述。
本申请实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领 域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种级联码的编码的方法，其特征在于，包括：
    对待编码的消息比特序列进行极化码编码，得到长度为N_o的第一编码码字，所述N_o为正整数；
    对第二编码码字进行改进的低密度奇偶校验LDPC码编码，得到长度为N_i的级联码码字，所述第二编码码字是根据所述第一编码码字确定的，所述N_i为正整数；
    输出所述级联码码字；
    其中，所述改进的LDPC码的基矩阵的前t列为全零列，所述t为正整数，且2≤t＜T，所述T等于所述N_o与p的比值，所述p为所述基矩阵需要扩展的倍数，所述p为正整数；
    所述改进的LDPC码的校验矩阵包括至少s列列重为1的列，所述至少s列包括后(N_i-N_o)列，所述s为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述基矩阵的大小为m行n列，所述方法还包括：
    构造一个大小为m的行矢量和一个大小为v的列矢量，且，所述行矢量中任意两个元素不同，所述列矢量中任意两个元素不同，所述m、所述n和所述v均为正整数，所述m和所述v均小于或等于所述p，v＝n，或者，v＝n-t；
    根据所述行矢量和所述列矢量，得到提升矩阵；
    根据所述提升矩阵和所述基矩阵，得到更新后的基矩阵；
    根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述行矢量和所述列矢量，得到所述提升矩阵，包括：
    构造所述提升矩阵M(i,j)＝ri·cjmod p，
    其中，所述行矢量Crows＝(r1,r2,...,rm)，ri为所述行矢量Crows中的第i个元素，1≤i≤m，所述列矢量Ccols＝(c1,c2,...,cv)，cj为所述列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
  4. 根据权利要求2或3所述的方法，其特征在于，所述根据提升矩阵和所述基矩阵，得到更新后的基矩阵，包括：
    若v＝n，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，
    若v＝n-t，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；
    其中，所述Hopt为所述基矩阵，所述Hopt2为通过提取所述基矩阵中的非零列得到的矩阵，所述M为所述提升矩阵。
  5. 根据权利要求2至4中任一项所述的方法，其特征在于，所述根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵，包括：
    若v＝n，则对所述更新后的基矩阵进行p倍的扩展得到所述校验矩阵；或者，
    若v＝n-t，则对所述更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对所述中间校验矩阵补充t*p列全零列得到所述校验矩阵。
  6. 一种级联码的译码的方法，其特征在于，包括：
    获取长度为N_i的信道接收矢量，所述N_i为级联码的内码的长度，所述级联码的内码为改进的低密度奇偶校验LDPC码，所述级联码的外码为极化码，所述N_i为正整数；
    其中，所述改进的LDPC码的基矩阵的前t列为全零列，所述t为正整数，且2≤t＜T，所述T等于所述N_o与p的比值，所述p为所述基矩阵需要扩展的倍数，所述p为正整数；
    所述改进的LDPC码的校验矩阵包括至少s列列重为1的列，所述至少s列包括后(N_i-N_o)列，所述s为正整数；
    对所述信道接收矢量进行译码，输出译码结果。
  7. 根据权利要求6所述的方法，其特征在于，所述基矩阵的大小为m行n列，所述方法还包括：
    构造一个大小为m的行矢量和一个大小为v的列矢量，且，所述行矢量中任意两个元素不同，所述列矢量中任意两个元素不同，所述m、所述n和所述v均为正整数，所述m和所述v均小于或等于 所述p，v＝n，或者，v＝n-t；
    根据所述行矢量和所述列矢量，得到提升矩阵；
    根据所述提升矩阵和所述基矩阵，得到更新后的基矩阵；
    根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵。
  8. 根据权利要求7所述的方法，其特征在于，所述根据所述行矢量和所述列矢量，得到所述提升矩阵，包括：
    构造所述提升矩阵M(i,j)＝ri·cjmod p，
    其中，所述行矢量Crows＝(r1,r2,...,rm)，ri为所述行矢量Crows中的第i个元素，1≤i≤m，所述列矢量Ccols＝(c1,c2,...,cv)，cj为所述列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
  9. 根据权利要求7或8所述的方法，其特征在于，所述根据提升矩阵和所述基矩阵，得到更新后的基矩阵，包括：
    若v＝n，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，
    若v＝n-t，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；
    其中，所述Hopt为所述基矩阵，所述Hopt2为通过提取所述基矩阵中的非零列得到的矩阵，所述M为所述提升矩阵。
  10. 根据权利要求7至9中任一项所述的方法，其特征在于，所述根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵，包括：
    若v＝n，则对所述更新后的基矩阵进行p倍的扩展得到所述校验矩阵；或者，
    若v＝n-t，则对所述更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对所述中间校验矩阵补充t*p列全零列得到所述校验矩阵。
  11. 一种通信装置，其特征在于，包括：
    处理单元，用于：
    对待编码的消息比特序列进行极化码编码，得到长度为N_o的第一编码码字，所述N_o为正整数；
    对第二编码码字进行改进的低密度奇偶校验LDPC码编码，得到长度为N_i的级联码码字，所述第二编码码字是根据所述第一编码码字确定的，所述N_i为正整数；
    收发单元，用于输出所述级联码码字；
    其中，所述改进的LDPC码的基矩阵的前t列为全零列，所述t为正整数，且2≤t＜T，所述T等于所述N_o与p的比值，所述p为所述基矩阵需要扩展的倍数，所述p为正整数；
    所述改进的LDPC码的校验矩阵包括至少s列列重为1的列，所述至少s列包括后(N_i-N_o)列，所述s为正整数。
  12. 根据权利要求11所述的通信装置，其特征在于，所述基矩阵的大小为m行n列，所述处理单元还用于：
    构造一个大小为m的行矢量和一个大小为v的列矢量，且，所述行矢量中任意两个元素不同，所述列矢量中任意两个元素不同，所述m、所述n和所述v均为正整数，所述m和所述v均小于或等于所述p，v＝n，或者，v＝n-t；
    根据所述行矢量和所述列矢量，得到提升矩阵；
    根据所述提升矩阵和所述基矩阵，得到更新后的基矩阵；
    根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵。
  13. 根据权利要求12所述的通信装置，其特征在于，所述处理单元具体用于：
    构造所述提升矩阵M(i,j)＝ri·cjmod p，
    其中，所述行矢量Crows＝(r1,r2,...,rm)，ri为所述行矢量Crows中的第i个元素，1≤i≤m，所述列矢量Ccols＝(c1,c2,...,cv)，cj为所述列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
  14. 根据权利要求12或13所述的通信装置，其特征在于，所述处理单元具体用于：
    若v＝n，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，
    若v＝n-t，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；
    其中，所述Hopt为所述基矩阵，所述Hopt2为通过提取所述基矩阵中的非零列得到的矩阵，所述M为所述提升矩阵。
  15. 根据权利要求12至14中任一项所述的通信装置，其特征在于，所述处理单元具体用于：
    若v＝n，则对所述更新后的基矩阵进行p倍的扩展得到所述校验矩阵；或者，
    若v＝n-t，则对所述更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对所述中间校验矩阵补充t*p列全零列得到所述校验矩阵。
  16. 一种通信装置，其特征在于，包括：
    收发单元，用于获取长度为N_i的信道接收矢量，所述N_i为级联码的内码的长度，所述级联码的内码为改进的低密度奇偶校验LDPC码，所述级联码的外码为极化码，所述N_i为正整数；
    其中，所述改进的LDPC码的基矩阵的前t列为全零列，所述t为正整数，且2≤t＜T，所述T等于所述N_o与p的比值，所述p为所述基矩阵需要扩展的倍数，所述p为正整数；
    所述改进的LDPC码的校验矩阵包括至少s列列重为1的列，所述至少s列包括后(N_i-N_o)列，所述s为正整数；
    处理单元，用于对所述信道接收矢量进行译码；
    所述收发单元，还用于输出译码结果。
  17. 根据权利要求16所述的通信装置，其特征在于，所述基矩阵的大小为m行n列，所述处理单元还用于：
    构造一个大小为m的行矢量和一个大小为v的列矢量，且，所述行矢量中任意两个元素不同，所述列矢量中任意两个元素不同，所述m、所述n和所述v均为正整数，所述m和所述v均小于或等于所述p，v＝n，或者，v＝n-t；
    根据所述行矢量和所述列矢量，得到提升矩阵；
    根据所述提升矩阵和所述基矩阵，得到更新后的基矩阵；
    根据所述更新后的基矩阵，得到所述改进的LDPC码的校验矩阵。
  18. 根据权利要求17所述的通信装置，其特征在于，所述处理单元具体用于：
    构造所述提升矩阵M(i,j)＝ri·cjmod p，
    其中，所述行矢量Crows＝(r1,r2,...,rm)，ri为所述行矢量Crows中的第i个元素，1≤i≤m，所述列矢量Ccols＝(c1,c2,...,cv)，cj为所述列矢量Ccols中的第j个元素，1≤j≤v，mod为取余运算。
  19. 根据权利要求17或18所述的通信装置，其特征在于，所述处理单元具体用于：
    若v＝n，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt⊙M；或者，
    若v＝n-t，则确定所述更新后的基矩阵Hm表示为：Hm＝Hopt2⊙M；
    其中，所述Hopt为所述基矩阵，所述Hopt2为通过提取所述基矩阵中的非零列得到的矩阵，所述M为所述提升矩阵。
  20. 根据权利要求17至19中任一项所述的通信装置，其特征在于，所述处理单元具体用于：
    若v＝n，则对所述更新后的基矩阵进行p倍的扩展得到所述校验矩阵；或者，
    若v＝n-t，则对所述更新后的基矩阵进行p倍的扩展得到中间校验矩阵，对所述中间校验矩阵补充t*p列全零列得到所述校验矩阵。
  21. 一种通信装置，其特征在于，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合，所述至少一个处理器用于执行所述至少一个存储器中存储的计算机程序或指令，以使所述通信装置执行如权利要求1-5中任一项所述的方法，或者如权利要求6-10中任一项所述的方法。
  22. 一种芯片，其特征在于，包括处理器和通信接口，所述通信接口用于接收待编码的消息比特序列，并将所述待编码的消息比特序列发送至所述处理器，所述处理器根据如权利要求1-5中任一项所述的方法，对所述待编码的消息比特序列进行级联编码，获得级联码字；所述通信接口还用于输出所述级联码字；或者，
    所述通信接口用于接收信道接收矢量，并所述信道接收矢量发送至所述处理器，所述处理器根据如权利要求6-10中任一项所述的方法进行级联码的译码，获得译码结果；所述通信接口用于输出所述译码结果。
  23. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得如权利要求1-5中任一项所述的方法，或如权利要求6-10中任一项所述的方法被实现。
  24. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得如权利要求1-5中任一项所述的方法，或如权利要求6-10中任一项所述的方法被实现。
  25. 一种系统，其特征在于，包括如权利要求11-15中任一项所述的通信装置，以及包括如权利要求16至20中任一项所述的通信装置。
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